diff --git a/arch/arm/src/sam34/chip.h b/arch/arm/src/sam34/chip.h index b577ff1b947..26ebb2565d3 100644 --- a/arch/arm/src/sam34/chip.h +++ b/arch/arm/src/sam34/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,19 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_CHIP_H #define __ARCH_ARM_SRC_SAM34_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the memory map and the chip definitions file. Other chip hardware files - * should then include this file for the proper setup. +/* Include the memory map and the chip definitions file. + * Other chip hardware files should then include this file for the proper + * setup. */ #include @@ -38,13 +39,13 @@ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Provide the required number of peripheral interrupt vector definitions as well. - * The definition SAM_IRQ_NEXTINT simply comes from the chip-specific IRQ header - * file included by arch/sam34/irq.h. +/* Provide the required number of peripheral interrupt vector definitions as + * well. The definition SAM_IRQ_NEXTINT simply comes from the chip-specific + * IRQ header file included by arch/sam34/irq.h. */ #define ARMV7M_PERIPHERAL_INTERRUPTS SAM_IRQ_NEXTINT diff --git a/arch/arm/src/sam34/hardware/sam3u_memorymap.h b/arch/arm/src/sam34/hardware/sam3u_memorymap.h index 4d7090b389d..eeee517fa89 100644 --- a/arch/arm/src/sam34/hardware/sam3u_memorymap.h +++ b/arch/arm/src/sam34/hardware/sam3u_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam3u_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ #define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ # define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */ @@ -113,18 +113,18 @@ #define SAM_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */ #define SAM_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */ #define SAM_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */ - /* 0x490e1400-0x4007ffff: Reserved */ + /* 0x490e1400-0x4007ffff: Reserved */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H */ diff --git a/arch/arm/src/sam34/hardware/sam3u_pinmap.h b/arch/arm/src/sam34/hardware/sam3u_pinmap.h index f56d0849a45..0c52cadcaed 100644 --- a/arch/arm/src/sam34/hardware/sam3u_pinmap.h +++ b/arch/arm/src/sam34/hardware/sam3u_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam3u_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPIO pin definitions *************************************************************/ +/* GPIO pin definitions *****************************************************/ #define GPIO_ADC0_AD0 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21) #define GPIO_ADC0_AD1 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30) @@ -172,19 +172,19 @@ #define GPIO_USB_VBUS (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -195,9 +195,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/hardware/sam3u_pio.h b/arch/arm/src/sam34/hardware/sam3u_pio.h index dd50eb1d6f2..d014ca04aee 100644 --- a/arch/arm/src/sam34/hardware/sam3u_pio.h +++ b/arch/arm/src/sam34/hardware/sam3u_pio.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam3u_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* PIO register offsets *****************************************************************/ +/* PIO register offsets *****************************************************/ #define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ #define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ @@ -93,7 +93,7 @@ /* 0x00ec-0x00f8: Reserved */ /* 0x0100-0x0144: Reserved */ -/* PIO register addresses ***************************************************************/ +/* PIO register addresses ***************************************************/ #define PIOA (0) #define PIOB (1) @@ -417,7 +417,7 @@ # define SAM_PIOF_WPSR (SAM_PIOF_BASE+SAM_PIO_WPSR_OFFSET) #endif -/* PIO register bit definitions *********************************************************/ +/* PIO register bit definitions *********************************************/ /* Common bit definitions for ALMOST all IO registers (exceptions follow) */ @@ -436,16 +436,16 @@ #define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H */ diff --git a/arch/arm/src/sam34/hardware/sam3x_memorymap.h b/arch/arm/src/sam34/hardware/sam3x_memorymap.h index 1773e7e95f7..b0adc1048b8 100644 --- a/arch/arm/src/sam34/hardware/sam3x_memorymap.h +++ b/arch/arm/src/sam34/hardware/sam3x_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam3x_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ /* Address regions */ @@ -47,6 +47,7 @@ #define SAM_INTFLASH1_BASE (0x00080000 + SAM34_FLASH_SIZE/2) #define SAM_INTROM_BASE 0x00100000 /* 0x00100000-0x001fffff: Internal ROM */ /* 0x00200000-0x1fffffff: Reserved */ + /* Internal SRAM memory region */ #define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: Internal SRAM 0 */ @@ -56,6 +57,7 @@ /* 0x20200000-0x201fffff: Undefined */ #define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */ /* 0x24000000-0x3fffffff: Undefined */ + /* Peripherals address region */ #define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ @@ -101,6 +103,7 @@ /* 0x41000000-0x41ffffff: Undefined */ #define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ /* 0x44000000-0x5fffffff: Undefined */ + /* System Controller Register Blocks: 0x400e0000-0x4007ffff */ #define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ @@ -127,6 +130,7 @@ #define SAM_RTC_BASE 0x400e1a60 /* 0x400e1a60-0x400e1a8f: Real Time Clock */ #define SAM_GPBR_BASE 0x400e1a90 /* 0x400e1a90-0x400e1aaf: GPBR */ /* 0x400e1ab0-0x4007ffff: Reserved */ + /* External RAM memory region */ #define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ @@ -144,16 +148,16 @@ #define SAM_SDRAMCS_BASE 0x70000000 /* 0x70000000-0x7fffffff: SDRAM chip select */ /* 0x80000000-0x9fffffff: Reserved */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H */ diff --git a/arch/arm/src/sam34/hardware/sam3x_pinmap.h b/arch/arm/src/sam34/hardware/sam3x_pinmap.h index ad2c97d05b0..1f5e170e463 100644 --- a/arch/arm/src/sam34/hardware/sam3x_pinmap.h +++ b/arch/arm/src/sam34/hardware/sam3x_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam3x_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,42 +16,43 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ -/* GPIO pin definitions *************************************************************/ /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the PWM0 Output high on PE15, then the following definition should appear - * in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if we wanted the PWM0 Output high on PE15, then the following + * definition should appear in the board.h header file for that board: * * #define GPIO_PWM0_H GPIO_PWM0_H_1 * * The driver will then automatically configure RE15 as the PWM0 H pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* 12-bit Analog-to-Digital Conververt (ADC) */ @@ -408,19 +409,19 @@ #define GPIO_SWI_SWDIO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN31) #define GPIO_SWI_TRACESWO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN30) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -431,9 +432,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/hardware/sam4cm_aes.h b/arch/arm/src/sam34/hardware/sam4cm_aes.h index 749fbac679a..8d63e0f1732 100644 --- a/arch/arm/src/sam34/hardware/sam4cm_aes.h +++ b/arch/arm/src/sam34/hardware/sam4cm_aes.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4cm_aes.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* AES register offsets *********************************************************************/ +/* AES register offsets *****************************************************/ #define SAM_AES_CR_OFFSET 0x0000 /* Control Register */ #define SAM_AES_MR_OFFSET 0x0004 /* Control Register */ @@ -53,7 +53,7 @@ #define SAM_AES_CTRR_OFFSET 0x0098 /* GCM Encryption Counter Value Register */ #define SAM_AES_GCMHR_OFFSET 0x009C /* GCM H World Register */ -/* AES register addresses *******************************************************************/ +/* AES register addresses ***************************************************/ #define SAM_AES_CR (SAM_AES_BASE + SAM_AES_CR_OFFSET) #define SAM_AES_MR (SAM_AES_BASE + SAM_AES_MR_OFFSET) @@ -72,7 +72,7 @@ #define SAM_AES_CTRR (SAM_AES_BASE + SAM_AES_CTRR_OFFSET) #define SAM_AES_GCMHR (SAM_AES_BASE + SAM_AES_GCMHR_OFFSET) -/* AES register bit definitions *************************************************************/ +/* AES register bit definitions *********************************************/ /* AES Control Register */ diff --git a/arch/arm/src/sam34/hardware/sam4cm_ipc.h b/arch/arm/src/sam34/hardware/sam4cm_ipc.h index 5ca6f30ab15..65566485c01 100644 --- a/arch/arm/src/sam34/hardware/sam4cm_ipc.h +++ b/arch/arm/src/sam34/hardware/sam4cm_ipc.h @@ -1,4 +1,4 @@ -/*********************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4cm_ipc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ***********************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H -/*********************************************************************************** +/**************************************************************************** * Included Files - ***********************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/*********************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ***********************************************************************************/ + ****************************************************************************/ -/* IPC register offsets ************************************************************/ +/* IPC register offsets *****************************************************/ #define SAM_SLCDC_CR_OFFSET 0x0000 /* Control Register */ @@ -44,7 +44,7 @@ #define SAM_IPC_IMR_OFFSET 0x0014 /* Interrupt Mask Register */ #define SAM_IPC_ISR_OFFSET 0x0018 /* Interrupt Status Register */ -/* IPC register addresses **********************************************************/ +/* IPC register addresses ***************************************************/ #define SAM_IPC0_ISCR (SAM_IPC0_BASE + SAM_IPC_ISCR_OFFSET) #define SAM_IPC0_ICCR (SAM_IPC0_BASE + SAM_IPC_ICCR_OFFSET) diff --git a/arch/arm/src/sam34/hardware/sam4cm_memorymap.h b/arch/arm/src/sam34/hardware/sam4cm_memorymap.h index e89b19be41a..b58da7983ad 100644 --- a/arch/arm/src/sam34/hardware/sam4cm_memorymap.h +++ b/arch/arm/src/sam34/hardware/sam4cm_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4cm_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_MEMORYMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_MEMORYMAP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ /* Address regions */ @@ -53,6 +53,7 @@ #define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 1 */ #define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */ /* 0x24000000-0x3fffffff: Undefined */ + /* Peripherals address region */ #define SAM_AES_BASE 0x40000000 @@ -113,20 +114,21 @@ # define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ # define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ /* 0x64000000-0x9fffffff: Reserved */ + /* System memory region */ #define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ #define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -139,7 +141,8 @@ extern "C" static inline unsigned long SAM_PION_BASE(int n) { - switch(n) { + switch (n) + { case 0: return SAM_PIOA_BASE; case 1: @@ -148,12 +151,12 @@ static inline unsigned long SAM_PION_BASE(int n) return SAM_PIOC_BASE; default: return 0; - } + } } -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/hardware/sam4cm_pinmap.h b/arch/arm/src/sam34/hardware/sam4cm_pinmap.h index be039663af9..516f5d6a226 100644 --- a/arch/arm/src/sam34/hardware/sam4cm_pinmap.h +++ b/arch/arm/src/sam34/hardware/sam4cm_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4cm_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,42 +16,44 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_PINMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ -/* GPIO pin definitions *************************************************************/ /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the programmable clock output PCK0 on PA6, then the following definition - * should appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if we wanted the programmable clock output PCK0 on PA6, then the + * following definition should appear in the board.h header file for that + * board: * * #define GPIO_PCK0 GPIO_PCK0_1 * * The driver will then automatically configure PA6 as the PCK0 pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* 12-bit Analog-to-Digital Converter (ADC) */ @@ -237,7 +239,8 @@ #define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) /* Segment LCD Controller (SLCDC) */ -//TODO: add rest of segment pins + +/* TODO: add rest of segment pins */ #define GPIO_SLCDC_COM0 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN0) #define GPIO_SLCDC_COM1 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN1) @@ -270,20 +273,19 @@ #define GPIO_SLCDC_SEG21 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN27) #define GPIO_SLCDC_SEG22 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN28) - -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -294,9 +296,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/hardware/sam4cm_slcdc.h b/arch/arm/src/sam34/hardware/sam4cm_slcdc.h index e529e478f71..579dfd2ca34 100644 --- a/arch/arm/src/sam34/hardware/sam4cm_slcdc.h +++ b/arch/arm/src/sam34/hardware/sam4cm_slcdc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4cm_slcdc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SLCDC register offsets ************************************************************/ +/* SLCDC register offsets ***************************************************/ #define SAM_SLCDC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_SLCDC_MR_OFFSET 0x0004 /* Mode Register */ @@ -54,7 +54,7 @@ #define SAM_SLCDC_LMEMR_OFFSET(com) (0x200 + (com)*8 + 0x0) #define SAM_SLCDC_MMEMR_OFFSET(com) (0x200 + (com)*8 + 0x4) -/* SLCDC register addresses **********************************************************/ +/* SLCDC register addresses *************************************************/ #define SAM_SLCDC_CR (SAM_SLCDC_BASE + SAM_SLCDC_CR_OFFSET) #define SAM_SLCDC_MR (SAM_SLCDC_BASE + SAM_SLCDC_MR_OFFSET) @@ -74,7 +74,7 @@ #define SAM_SLCDC_LMEMR(com) (SAM_SLCDC_BASE + SAM_SLCDC_LMEMR_OFFSET(com)) #define SAM_SLCDC_MMEMR(com) (SAM_SLCDC_BASE + SAM_SLCDC_MMEMR_OFFSET(com)) -/* SLCDC register bit definitions ****************************************************/ +/* SLCDC register bit definitions *******************************************/ /* Control Register */ diff --git a/arch/arm/src/sam34/hardware/sam4cm_supc.h b/arch/arm/src/sam34/hardware/sam4cm_supc.h index 0670ea8da52..f3629e302c4 100644 --- a/arch/arm/src/sam34/hardware/sam4cm_supc.h +++ b/arch/arm/src/sam34/hardware/sam4cm_supc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4cm_supc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SUPC register offsets ****************************************************************/ +/* SUPC register offsets ****************************************************/ #define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ #define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ @@ -43,7 +43,7 @@ #define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ #define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ -/* SUPC register addresses **************************************************************/ +/* SUPC register addresses **************************************************/ #define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) #define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) @@ -52,7 +52,8 @@ #define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) #define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) -/* SUPC register bit definitions ********************************************************/ +/* SUPC register bit definitions ********************************************/ + /* Supply Controller Control Register */ #define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ @@ -89,6 +90,7 @@ # define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ # define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ # define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ + #define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ #define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ @@ -116,6 +118,7 @@ # define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ # define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ # define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ + #define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ #define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) # define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ @@ -146,16 +149,16 @@ #define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */ #define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H */ diff --git a/arch/arm/src/sam34/hardware/sam4e_memorymap.h b/arch/arm/src/sam34/hardware/sam4e_memorymap.h index c98302cadae..099b438b424 100644 --- a/arch/arm/src/sam34/hardware/sam4e_memorymap.h +++ b/arch/arm/src/sam34/hardware/sam4e_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4e_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ /* Address regions */ @@ -47,6 +47,7 @@ #define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */ #define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */ /* 0x00c00000-0x1fffffff: Reserved */ + /* Internal SRAM memory region */ #define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */ @@ -111,7 +112,7 @@ /* System Controller Register Blocks: 0x400e0000-0x4007ffff */ - /* 0x400e0000-0x400e01ff: Reserved */ + /* 0x400e0000-0x400e01ff: Reserved */ #define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ #define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ #define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */ @@ -144,21 +145,22 @@ # define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ # define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ /* 0x64000000-0x9fffffff: Reserved */ + /* System memory region */ #define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ #define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H */ diff --git a/arch/arm/src/sam34/hardware/sam4e_pinmap.h b/arch/arm/src/sam34/hardware/sam4e_pinmap.h index 48ab04ced63..f2e7c92ec82 100644 --- a/arch/arm/src/sam34/hardware/sam4e_pinmap.h +++ b/arch/arm/src/sam34/hardware/sam4e_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4e_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,42 +16,44 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ -/* GPIO pin definitions *************************************************************/ /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the programmable clock output PCK0 on PA6, then the following definition - * should appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if we wanted the programmable clock output PCK0 on PA6, then the + * following definition should appear in the board.h header file for that + * board: * * #define GPIO_PCK0 GPIO_PCK0_1 * * The driver will then automatically configure PA6 as the PCK0 pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* Analog Front End (AFE) */ @@ -286,19 +288,19 @@ #define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) #define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -309,9 +311,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/hardware/sam4e_pio.h b/arch/arm/src/sam34/hardware/sam4e_pio.h index 003a3d84871..c3c0e2f7a16 100644 --- a/arch/arm/src/sam34/hardware/sam4e_pio.h +++ b/arch/arm/src/sam34/hardware/sam4e_pio.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4e_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* PIO register offsets *****************************************************************/ +/* PIO register offsets *****************************************************/ #define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ #define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ @@ -107,7 +107,7 @@ #define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */ /* 0x0168-0x018c: Reserved for PDC registers */ -/* PIO register addresses ***************************************************************/ +/* PIO register addresses ***************************************************/ #define PIOA (0) #define PIOB (1) @@ -450,7 +450,7 @@ #define SAM_PIOE_PCISR (SAM_PIOE_BASE+SAM_PIO_PCISR_OFFSET) #define SAM_PIOE_PCRHR (SAM_PIOE_BASE+SAM_PIO_PCRHR_OFFSET -/* PIO register bit definitions *********************************************************/ +/* PIO register bit definitions *********************************************/ /* Common bit definitions for ALMOST all IO registers (exceptions follow) */ @@ -512,27 +512,30 @@ # define PIO_PCMR_DSIZE_BYTE (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */ # define PIO_PCMR_DSIZE_HWORD (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */ # define PIO_PCMR_DSIZE_WORD (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */ + #define PIO_PCMR_ALWYS (1 << 9) /* Bit 9: Parallel Capture Mode Always Sampling */ #define PIO_PCMR_HALFS (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */ #define PIO_PCMR_FRSTS (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */ -/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */ +/* PIO Parallel Capture Interrupt Enable, Disable, Mask, + * and Status Registers + */ #define PIOC_PCINT_DRDY (1 << 0) /* Bit 0: Parallel Capture Mode Data Ready Interrupt Enable */ #define PIOC_PCINT_OVRE (1 << 1) /* Bit 1: Parallel Capture Mode Overrun Error Interrupt Enable */ #define PIOC_PCINT_ENDRX (1 << 2) /* Bit 2: End of Reception Transfer Interrupt Enable */ #define PIOC_PCINT_RXBUFF (1 << 3) /* Bit 3: Reception Buffer Full Interrupt Enable */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_bpm.h b/arch/arm/src/sam34/hardware/sam4l_bpm.h index 12f73727648..03809efe65e 100644 --- a/arch/arm/src/sam34/hardware/sam4l_bpm.h +++ b/arch/arm/src/sam34/hardware/sam4l_bpm.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_bpm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* BPM register offsets ****************************************************************/ +/* BPM register offsets *****************************************************/ #define SAM_BPM_IER_OFFSET 0x0000 /* Interrupt Enable Register */ #define SAM_BPM_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ @@ -50,7 +50,7 @@ #define SAM_BPM_IORET_OFFSET 0x0034 /* Input Output Retention Register */ #define SAM_BPM_VERSION_OFFSET 0x00fc /* Version Register */ -/* BPM register addresses **************************************************************/ +/* BPM register addresses ***************************************************/ #define SAM_BPM_IER (SAM_BPM_BASE+SAM_BPM_IER_OFFSET) #define SAM_BPM_IDR (SAM_BPM_BASE+SAM_BPM_IDR_OFFSET) @@ -66,13 +66,18 @@ #define SAM_BPM_IORET (SAM_BPM_BASE+SAM_BPM_IORET_OFFSET) #define SAM_BPM_VERSION (SAM_BPM_BASE+SAM_BPM_VERSION_OFFSET) -/* BPM register bit definitions ********************************************************/ +/* BPM register bit definitions *********************************************/ /* Interrupt Enable Register */ + /* Interrupt Disable Register */ + /* Interrupt Mask Register */ + /* Interrupt Status Register */ + /* Interrupt Clear Register */ + /* Status Register */ #define BPM_INT_PSOK (1 << 0) /* Bit 0: Power Scaling OK */ @@ -104,6 +109,7 @@ # define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */ # define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */ # define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */ + #define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */ #define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */ @@ -148,16 +154,16 @@ #define BPM_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ #define BPM_VERSION_VARIANT_MASK (15 << BPM_VERSION_VARIANT_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_bscif.h b/arch/arm/src/sam34/hardware/sam4l_bscif.h index f3eb716b23c..df85dc0156b 100644 --- a/arch/arm/src/sam34/hardware/sam4l_bscif.h +++ b/arch/arm/src/sam34/hardware/sam4l_bscif.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_bscif.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* BSCIF register offsets ***************************************************************/ +/* BSCIF register offsets ***************************************************/ #define SAM_BSCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */ #define SAM_BSCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ @@ -70,7 +70,7 @@ #define SAM_BSCIF_OSC32IFAVERSION_OFFSET 0x03f8 /* 32 kHz Oscillator Version Register */ #define SAM_BSCIF_VERSION_OFFSET 0x03fc /* BSCIF Version Register */ -/* BSCIF register addresses *************************************************************/ +/* BSCIF register addresses *************************************************/ #define SAM_BSCIF_IER (SAM_BSCIF_BASE+SAM_BSCIF_IER_OFFSET) #define SAM_BSCIF_IDR (SAM_BSCIF_BASE+SAM_BSCIF_IDR_OFFSET) @@ -106,12 +106,16 @@ #define SAM_BSCIF_OSC32IFAVERSION (SAM_BSCIF_BASE+SAM_BSCIF_OSC32IFAVERSION_OFFSET) #define SAM_BSCIF_VERSION (SAM_BSCIF_BASE+SAM_BSCIF_VERSION_OFFSET) -/* BSCIF register bit definitions *******************************************************/ +/* BSCIF register bit definitions *******************************************/ /* Interrupt Enable Register */ + /* Interrupt Disable Register */ + /* Interrupt Mask Register */ + /* Interrupt Status Register */ + /* Interrupt Clear Register */ #define BSCIF_INT_OSC32RDY (1 << 0) /* Bit 0 */ @@ -167,6 +171,7 @@ # define BSCIF_OSCCTRL32_MODE_XTALAC (3 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + amplitude controlled mode */ # define BSCIF_OSCCTRL32_MODE_XTALHC (4 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current mode */ # define BSCIF_OSCCTRL32_MODE_XTALHCAC (5 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current + amplitude controlled mode */ + #define BSCIF_OSCCTRL32_SELCURR_SHIFT (12) /* Bits 12-15: Current Selection */ #define BSCIF_OSCCTRL32_SELCURR_MASK (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT) # define BSCIF_OSCCTRL32_SELCURR_50 (0 << BSCIF_OSCCTRL32_SELCURR_SHIFT) @@ -185,6 +190,7 @@ # define BSCIF_OSCCTRL32_SELCURR_375 (13 << BSCIF_OSCCTRL32_SELCURR_SHIFT) # define BSCIF_OSCCTRL32_SELCURR_400 (14 << BSCIF_OSCCTRL32_SELCURR_SHIFT) # define BSCIF_OSCCTRL32_SELCURR_425 (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT) + #define BSCIF_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Start-up Time */ #define BSCIF_OSCCTRL32_STARTUP_MASK (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) # define BSCIF_OSCCTRL32_STARTUP_0 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) @@ -195,6 +201,7 @@ # define BSCIF_OSCCTRL32_STARTUP_128K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 131072 1.1 s */ # define BSCIF_OSCCTRL32_STARTUP_256K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 262144 2.3 s */ # define BSCIF_OSCCTRL32_STARTUP_512K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 524288 4.6 s */ + #define BSCIF_OSCCTRL32_RESERVED (1 << 31) /* Bit 31: Reserved, must always be written as zero */ /* 32kHz RC Oscillator Control Register */ @@ -215,18 +222,22 @@ #define BSCIF_RC32KTUNE_COARSE_MASK (0x7f << BSCIF_RC32KTUNE_COARSE_SHIFT) /* BOD33 Control Register */ + /* BOD18 Control Register */ #define BSCIF_BODCTRL_EN (1 << 0) /* Bit 0: Enable */ #define BSCIF_BODCTRL_HYST (1 << 1) /* Bit 1: BOD Hysteresis */ #define BSCIF_BODCTRL_ACTION_SHIFT (8) /* Bits 8-9: Action */ + # define BSCIF_BODCTRL_ACTION_RESET (1 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates a reset */ # define BSCIF_BODCTRL_ACTION_INTR (2 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates an interrupt */ + #define BSCIF_BODCTRL_MODE (1 << 0) /* Bit 0: Operation modes */ #define BSCIF_BODCTRL_FCD (1 << 0) /* Bit 0: BOD Fuse Calibration Done */ #define BSCIF_BODCTRL_SFV (1 << 0) /* Bit 0: BOD Control Register Store Final Value */ /* BOD33 Level Register */ + /* BOD18 Level Register */ #define BSCIF_BODLEVEL_CEN (1 << 0) /* Bit 0: Clock Enable */ @@ -235,6 +246,7 @@ #define BSCIF_BODLEVEL_PSEL_MASK (15 << BSCIF_BODLEVEL_PSEL_SHIFT) /* BOD33 Sampling Control Register */ + /* BOD18 Sampling Control Register */ #define BSCIF_BODSAMPLING_VAL_SHIFT (0) /* Bits 0-5: BOD Value */ @@ -274,11 +286,17 @@ /* 0x0078-0x0084 Backup register n=0..3 (32-bit data) */ /* Backup Register Interface Version Register */ + /* BGREFIF Version Register */ + /* Voltage Regulator Version Register */ + /* BOD Version Register */ + /* 32kHz RC Oscillator Version Register */ + /* 32 kHz Oscillator Version Register */ + /* BSCIF Version Register */ #define BSCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ @@ -286,16 +304,16 @@ #define BSCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ #define BSCIF_VARIANT_MASK (15 << BSCIF_VARIANT_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_flashcalw.h b/arch/arm/src/sam34/hardware/sam4l_flashcalw.h index 01508b50c7c..d70863e716d 100644 --- a/arch/arm/src/sam34/hardware/sam4l_flashcalw.h +++ b/arch/arm/src/sam34/hardware/sam4l_flashcalw.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_flashcalw.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* Register offsets *********************************************************/ -/* Register offsets *****************************************************************/ /* Relative to SAM_FLASHCALW_BASE */ #define SAM_FLASHCALW_FCR_OFFSET 0x0000 /* Flash Control Register */ @@ -57,7 +58,7 @@ #define SAM_PICOCACHE_MSR_OFFSET 0x0034 /* PicoCache Monitor Status Register */ #define SAM_PICOCACHE_PVR_OFFSET 0x00fc /* Version Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define SAM_FLASHCALW_FCR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCR_OFFSET) #define SAM_FLASHCALW_FCMD (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCMD_OFFSET) @@ -77,7 +78,7 @@ #define SAM_PICOCACHE_MSR (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MSR_OFFSET) #define SAM_PICOCACHE_PVR (SAM_PICOCACHE_BASE+SAM_PICOCACHE_PVR_OFFSET) -/* Register Bit-field Definitions ***************************************************/ +/* Register Bit-field Definitions *******************************************/ /* Flash Control Register */ @@ -110,6 +111,7 @@ # define FLASHCALW_FCMD_CMD_QPRUP (15 << FLASHCALW_FCMD_CMD_SHIFT) /* Quick Page Read User Page */ # define FLASHCALW_FCMD_CMD_HSEN (16 << FLASHCALW_FCMD_CMD_SHIFT) /* High Speed Mode Enable */ # define FLASHCALW_FCMD_CMD_HSDIS (17 << FLASHCALW_FCMD_CMD_SHIFT) /* High Speed Mode Disable */ + #define FLASHCALW_FCMD_PAGEN_SHIFT (8) /* Bits 8-23: Page number */ #define FLASHCALW_FCMD_PAGEN_MASK (0xffff << FLASHCALW_FCMD_PAGEN_SHIFT) #define FLASHCALW_FCMD_KEY_SHIFT (14) /* Bits 24-31: Write protection key */ @@ -163,6 +165,7 @@ # define FLASHCALW_FPR_FSZ_768KB (12 << FLASHCALW_FPR_FSZ_SHIFT) /* 768 Kbytes */ # define FLASHCALW_FPR_FSZ_1MB (13 << FLASHCALW_FPR_FSZ_SHIFT) /* 1024 Kbytes */ # define FLASHCALW_FPR_FSZ_2MB (14 << FLASHCALW_FPR_FSZ_SHIFT) /* 2048 Kbytes */ + #define FLASHCALW_FPR_PSZ_SHIFT (8) /* Bits 8-9: Page Size */ #define FLASHCALW_FPR_PSZ_MASK (7 << FLASHCALW_FPR_PSZ_SHIFT) # define FLASHCALW_FPR_PSZ_32KB (0 << FLASHCALW_FPR_PSZ_SHIFT) /* 32 Kbytes */ @@ -295,7 +298,7 @@ #define PICOCACHE_PVR_MFN_SHIFT (16) /* Bits 16-19: MFN */ #define PICOCACHE_PVR_MFN_MASK (15 << PICOCACHE_PVR_FVR_MFN_SHIFT) -/* Flash Command Set ****************************************************************/ +/* Flash Command Set ********************************************************/ #define FLASH_CMD_NOP 0 /* No operation */ #define FLASH_CMD_WP 1 /* Write Page */ @@ -346,16 +349,16 @@ #define FLASH_MAXFREQ_PS2_HSEN_FWS0 (24000000ul) #define FLASH_MAXFREQ_PS2_HSEN_FWS1 (48000000ul) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_gpio.h b/arch/arm/src/sam34/hardware/sam4l_gpio.h index 757c6f8e152..e3c0334560c 100644 --- a/arch/arm/src/sam34/hardware/sam4l_gpio.h +++ b/arch/arm/src/sam34/hardware/sam4l_gpio.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* PIO register offsets *****************************************************************/ +/* PIO register offsets *****************************************************/ #define SAM_GPIO_GPER_OFFSET 0x0000 /* GPIO Enable Register Read/Write */ #define SAM_GPIO_GPERS_OFFSET 0x0004 /* GPIO Enable Register Set */ @@ -48,10 +48,11 @@ * 010 C 110 G * 011 D 111 H * - * NOTE: Labeling in the data sheet is inconsistent. In the pin multiplexing table, - * It shows GPIO functions A-G with 000 apparently corresponding to the GPIO. In the - * register description, it should A-H with presumably A corresponding to 000. Here - * we adopt the above convention. + * NOTE: + * Labeling in the data sheet is inconsistent. In the pin multiplexing table, + * It shows GPIO functions A-G with 000 apparently corresponding to the GPIO. + * In the register description, it should A-H with presumably A + * corresponding to 000. Here we adopt the above convention. */ #define SAM_GPIO_PMR0_OFFSET 0x0010 /* Peripheral Mux Register 0 Read/Write */ @@ -166,7 +167,7 @@ #define SAM_GPIO_PARAMETER_OFFSET 0x01f8 /* Parameter Register Read */ #define SAM_GPIO_VERSION_OFFSET 0x01fc /* Version Register Read */ -/* GPIO port offsets and addresses ******************************************************/ +/* GPIO port offsets and addresses ******************************************/ #define SAM_GPIOA 0 #define SAM_GPIOB 1 @@ -179,7 +180,7 @@ #define SAM_GPIOB_BASE SAM_GPION_BASE(SAM_GPIOB) #define SAM_GPIOC_BASE SAM_GPION_BASE(SAM_GPIOC) -/* GPIO register addresses **************************************************************/ +/* GPIO register addresses **************************************************/ #define SAM_GPIO_GPER(n) (SAM_GPION_BASE(n)+SAM_GPIO_GPER_OFFSET) #define SAM_GPIO_GPERS(n) (SAM_GPION_BASE(n)+SAM_GPIO_GPERS_OFFSET) @@ -274,7 +275,7 @@ #define SAM_GPIO_PARAMETER(n) (SAM_GPION_BASE(n)+SAM_GPIO_PARAMETER_OFFSET) #define SAM_GPIO_VERSION (n) (SAM_GPION_BASE(n)+SAM_GPIO_VERSION_OFFSET) -/* GPIO PORTA register addresses ********************************************************/ +/* GPIO PORTA register addresses ********************************************/ #define SAM_GPIOA_GPER (SAM_GPIOA_BASE+SAM_GPIO_GPER_OFFSET) #define SAM_GPIOA_GPERS (SAM_GPIOA_BASE+SAM_GPIO_GPERS_OFFSET) @@ -369,7 +370,7 @@ #define SAM_GPIOA_PARAMETER (SAM_GPIOA_BASE+SAM_GPIO_PARAMETER_OFFSET) #define SAM_GPIOA_VERSION (SAM_GPIOA_BASE+SAM_GPIO_VERSION_OFFSET) -/* GPIO PORTB register addresses ********************************************************/ +/* GPIO PORTB register addresses ********************************************/ #define SAM_GPIOB_GPER (SAM_GPIOB_BASE+SAM_GPIO_GPER_OFFSET) #define SAM_GPIOB_GPERS (SAM_GPIOB_BASE+SAM_GPIO_GPERS_OFFSET) @@ -464,7 +465,7 @@ #define SAM_GPIOB_PARAMETER (SAM_GPIOB_BASE+SAM_GPIO_PARAMETER_OFFSET) #define SAM_GPIOB_VERSION (SAM_GPIOB_BASE+SAM_GPIO_VERSION_OFFSET) -/* GPIO PORTC register addresses ********************************************************/ +/* GPIO PORTC register addresses ********************************************/ #define SAM_GPIOC_GPER (SAM_GPIOC_BASE+SAM_GPIO_GPER_OFFSET) #define SAM_GPIOC_GPERS (SAM_GPIOC_BASE+SAM_GPIO_GPERS_OFFSET) @@ -559,22 +560,22 @@ #define SAM_GPIOC_PARAMETER (SAM_GPIOC_BASE+SAM_GPIO_PARAMETER_OFFSET) #define SAM_GPIOC_VERSION (SAM_GPIOC_BASE+SAM_GPIO_VERSION_OFFSET) -/* GPIO register bit definitions ********************************************************/ +/* GPIO register bit definitions ********************************************/ /* Common bit definitions for all GPIO registers */ #define PIN(n) (1 << (n)) /* Bit n: PIO n */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_lcdca.h b/arch/arm/src/sam34/hardware/sam4l_lcdca.h index c84702ac238..7407879c1b8 100644 --- a/arch/arm/src/sam34/hardware/sam4l_lcdca.h +++ b/arch/arm/src/sam34/hardware/sam4l_lcdca.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_lcdca.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* LCDCA register offsets ************************************************************/ +/* LCDCA register offsets ***************************************************/ #define SAM_LCDCA_CR_OFFSET 0x0000 /* Control Register */ #define SAM_LCDCA_CFG_OFFSET 0x0004 /* Configuration Register */ @@ -67,7 +67,7 @@ #define SAM_LCDCA_IMR_OFFSET 0x0060 /* Interrupt Mask Register */ #define SAM_LCDCA_VERSION_OFFSET 0x0064 /* Version Register */ -/* LCDCA register addresses **********************************************************/ +/* LCDCA register addresses *************************************************/ #define SAM_LCDCA_CR (SAM_LCDCA_BASE+SAM_LCDCA_CR_OFFSET) #define SAM_LCDCA_CFG (SAM_LCDCA_BASE+SAM_LCDCA_CFG_OFFSET) @@ -100,7 +100,7 @@ #define SAM_LCDCA_IMR (SAM_LCDCA_BASE+SAM_LCDCA_IMR_OFFSET) #define SAM_LCDCA_VERSION (SAM_LCDCA_BASE+SAM_LCDCA_VERSION_OFFSET) -/* LCDCA register bit definitions ****************************************************/ +/* LCDCA register bit definitions *******************************************/ /* Control Register */ @@ -132,9 +132,11 @@ # define LCDCA_CFG_DUTY_STATIC (1 << LCDCA_CFG_DUTY_SHIFT) /* Static, Static, COM0 */ # define LCDCA_CFG_DUTY_1TO2 (2 << LCDCA_CFG_DUTY_SHIFT) /* 1/2, 1/3, COM[0:1] */ # define LCDCA_CFG_DUTY_1TO3 (3 << LCDCA_CFG_DUTY_SHIFT) /* 1/3, 1/3, COM[0:2] */ + #define LCDCA_CFG_FCST_SHIFT (16) /* Bits 16-21: Fine Contrast */ #define LCDCA_CFG_FCST_MASK (63 << LCDCA_CFG_FCST_SHIFT) # define LCDCA_CFG_FCST(n) (((uint32_t)(n) & 63) << LCDCA_CFG_FCST_SHIFT) /* n = -32..31 */ + #define LCDCA_CFG_NSU_SHIFT (24) /* Bits 24-29: Number of Segment Terminals in Use */ #define LCDCA_CFG_NSU_MASK (63 << LCDCA_CFG_NSU_SHIFT) # define LCDCA_CFG_NSU(n) ((n) << LCDCA_CFG_NSU_SHIFT) /* n=0-40 */ @@ -145,13 +147,16 @@ #define LCDCA_TIM_CLKDIV_SHIFT (1) /* Bits 1-3: LCD Clock Division */ #define LCDCA_TIM_CLKDIV_MASK (7 << LCDCA_TIM_CLKDIV_SHIFT) # define LCDCA_TIM_CLKDIV(n) (((n)-1) << LCDCA_TIM_CLKDIV_SHIFT) /* n=1..8 */ + #define LCDCA_TIM_FC0_SHIFT (8) /* Bits 8-12: Frame Counter 0 */ #define LCDCA_TIM_FC0_MASK (31 << LCDCA_TIM_FC0_SHIFT) # define LCDCA_TIM_FC0(n) ((n) << LCDCA_TIM_FC0_SHIFT) /* n=0-31 */ + #define LCDCA_TIM_FC0PB (1 << 13) /* Bit 13: Frame Counter 0 Prescaler Bypass */ #define LCDCA_TIM_FC1_SHIFT (16) /* Bits 16-20: Frame Counter 1 */ #define LCDCA_TIM_FC1_MASK (31 << LCDCA_TIM_FC1_SHIFT) # define LCDCA_TIM_FC1(n) ((n) << LCDCA_TIM_FC1_SHIFT) /* n=0-31 */ + #define LCDCA_TIM_FC2_SHIFT (24) /* Bits 24-28: Frame Counter 2 */ #define LCDCA_TIM_FC2_MASK (31 << LCDCA_TIM_FC2_SHIFT) # define LCDCA_TIM_FC2(n) ((n) << LCDCA_TIM_FC2_SHIFT) /* n=0-31 */ @@ -172,14 +177,14 @@ #define LCDCA_SCR_FC0R (1 << 0) /* Bit 0: Frame Counter 0 Rollover */ -/* Data Register Low 0-3 (32-bit data, each bit defines a segment value in display - * memory for segments 0-31). +/* Data Register Low 0-3 (32-bit data, each bit defines a segment value in + * display memory for segments 0-31). */ #define LCDCA_DRL_MASK 0xffffffff -/* Data Register High 0-3 (8 bits data, each bit defines a segment value in display - * memory for segments 32-39) +/* Data Register High 0-3 (8 bits data, each bit defines a segment value in + * display memory for segments 32-39) */ #define LCDCA_DRH_MASK 0xff @@ -221,6 +226,7 @@ # define LCDCA_BCFG_FCS0 (0 << LCDCA_BCFG_FCS_SHIFT) # define LCDCA_BCFG_FCS1 (1 << LCDCA_BCFG_FCS_SHIFT) # define LCDCA_BCFG_FCS2 (2 << LCDCA_BCFG_FCS_SHIFT) + #define LCDCA_BCFG_BSS0_SHIFT (8) /* Bits 8-11: Blink Segment Selection 0 */ #define LCDCA_BCFG_BSS0_MASK (15 << LCDCA_BCFG_BSS0_SHIFT) # define LCDCA_BCFG_BSS0(n) ((n) << LCDCA_BCFG_BSS0_SHIFT) /* n=bitset */ @@ -228,6 +234,7 @@ # define LCDCA_BCFG_BSS01 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM1 selected */ # define LCDCA_BCFG_BSS02 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM2 selected */ # define LCDCA_BCFG_BSS03 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM3 selected */ + #define LCDCA_BCFG_BSS1_SHIFT (12) /* Bits 12-15: Blink Segment Selection 1 */ #define LCDCA_BCFG_BSS1_MASK (15 << LCDCA_BCFG_BSS1_SHIFT) # define LCDCA_BCFG_BSS1(n) ((n) << LCDCA_BCFG_BSS1_SHIFT) /* n=bitset */ @@ -245,9 +252,11 @@ # define LCDCA_CSRCFG_FCS0 (0 << LCDCA_CSRCFG_FCS_SHIFT) # define LCDCA_CSRCFG_FCS1 (1 << LCDCA_CSRCFG_FCS_SHIFT) # define LCDCA_CSRCFG_FCS2 (2 << LCDCA_CSRCFG_FCS_SHIFT) + #define LCDCA_CSRCFG_SIZE_SHIFT (3) /* Bits 3-5: Size */ #define LCDCA_CSRCFG_SIZE_MASK (7 << LCDCA_CSRCFG_SIZE_SHIFT) # define LCDCA_CSRCFG_SIZE(n) (((n)-1) << LCDCA_CSRCFG_SIZE_SHIFT) /* n=1..8 */ + #define LCDCA_CSRCFG_DATA_SHIFT (8) /* Bits 8-15: Circular Shift Register Value */ #define LCDCA_CSRCFG_DATA_MASK (0xff << LCDCA_CSRCFG_DATA_SHIFT) # define LCDCA_CSRCFG_DATA(n) ((n) << LCDCA_CSRCFG_DATA_SHIFT) @@ -261,6 +270,7 @@ # define LCDCA_CMCFG_TDG_7S4C (1 << LCDCA_CMCFG_TDG_SHIFT) /* 7-segment with 4 common terminals */ # define LCDCA_CMCFG_TDG_14S4C (2 << LCDCA_CMCFG_TDG_SHIFT) /* 14-segment with 4 common terminals */ # define LCDCA_CMCFG_TDG_14S3C (3 << LCDCA_CMCFG_TDG_SHIFT) /* 16-segment with 3 common terminals */ + #define LCDCA_CMCFG_STSEG_SHIFT (8) /* Bits 8-13: Start Segment */ #define LCDCA_CMCFG_STSEG_MASK (63 << LCDCA_CMCFG_STSEG_SHIFT) # define LCDCA_CMCFG_STSEG(n) ((n) << LCDCA_CMCFG_STSEG_SHIFT) @@ -278,6 +288,7 @@ # define LCDCA_ACMCFG_FCS0 (0 << LCDCA_ACMCFG_FCS_SHIFT) # define LCDCA_ACMCFG_FCS1 (1 << LCDCA_ACMCFG_FCS_SHIFT) # define LCDCA_ACMCFG_FCS2 (2 << LCDCA_ACMCFG_FCS_SHIFT) + #define LCDCA_ACMCFG_MODE (1 << 3) /* Bit 3: Mode */ #define LCDCA_ACMCFG_DREV (1 << 4) /* Bit 4: Digit Reverse */ #define LCDCA_ACMCFG_TDG_SHIFT (5) /* Bits 5-6: Type of Digit */ @@ -286,12 +297,15 @@ # define LCDCA_ACMCFG_TDG_7S4C (1 << LCDCA_ACMCFG_TDG_SHIFT) /* 7-segment with 4 common terminals */ # define LCDCA_ACMCFG_TDG_14S4C (2 << LCDCA_ACMCFG_TDG_SHIFT) /* 14-segment with 4 common terminals */ # define LCDCA_ACMCFG_TDG_14S3C (3 << LCDCA_ACMCFG_TDG_SHIFT) /* 16-segment with 3 common terminals */ + #define LCDCA_ACMCFG_STSEG_SHIFT (8) /* Bits 8-13: Start Segment */ #define LCDCA_ACMCFG_STSEG_MASK (63 << LCDCA_ACMCFG_STSEG_SHIFT) # define LCDCA_ACMCFG_STSEG(n) ((n) << LCDCA_ACMCFG_STSEG_SHIFT) + #define LCDCA_ACMCFG_STEPS_SHIFT (16) /* Bits 16-23: Scrolling Steps */ #define LCDCA_ACMCFG_STEPS_MASK (0xff << LCDCA_ACMCFG_STEPS_SHIFT) # define LCDCA_ACMCFG_STEPS(n) ((n) << LCDCA_ACMCFG_STEPS_SHIFT) /* n = string length - DIGN + 1 */ + #define LCDCA_ACMCFG_DIGN_SHIFT (24) /* Bits 24-27: Digit Number */ #define LCDCA_ACMCFG_DIGN_MASK (15 << LCDCA_ACMCFG_DIGN_SHIFT) # define LCDCA_ACMCFG_DIGN(n) ((n) << LCDCA_ACMCFG_DIGN_SHIFT) /* n=1..15 */ @@ -309,6 +323,7 @@ # define LCDCA_ABMCFG_FCS0 (0 << LCDCA_ABMCFG_FCS_SHIFT) # define LCDCA_ABMCFG_FCS1 (1 << LCDCA_ABMCFG_FCS_SHIFT) # define LCDCA_ABMCFG_FCS2 (2 << LCDCA_ABMCFG_FCS_SHIFT) + #define LCDCA_ABMCFG_SIZE_SHIFT (8) /* Bits 8-12: Size */ #define LCDCA_ABMCFG_SIZE_MASK (31 << LCDCA_ABMCFG_SIZE_SHIFT) # define LCDCA_ABMCFG_SIZE(n) (((n)-1) << LCDCA_ABMCFG_SIZE_SHIFT) /* n=1..31 */ @@ -342,7 +357,9 @@ # define LCDCA_ABMDR_OFF(n) (31 << LCDCA_ABMDR_OFF_SHIFT) /* Interrupt Enable Register */ + /* Interrupt Disable Register */ + /* Interrupt Mask Register */ #define LCDCA_INT_FC0R (1 << 0) /* Bit 0: Frame Counter 0 Rollover */ @@ -354,16 +371,16 @@ #define LCDCA_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ #define LCDCA_VARIANT_MASK (15 << LCDCA_VARIANT_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_memorymap.h b/arch/arm/src/sam34/hardware/sam4l_memorymap.h index 8cc3d1da98d..6c38a01949a 100644 --- a/arch/arm/src/sam34/hardware/sam4l_memorymap.h +++ b/arch/arm/src/sam34/hardware/sam4l_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ /* Global Memory Space */ @@ -45,12 +45,14 @@ #define SAM_INTFLASH_BASE 0x00000000 /* 0x00000000-0x003fffff: Internal FLASH */ /* 0x00400000-0x1fffffff: Reserved */ + /* Internal SRAM Space */ #define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: HRAMC0 (see chip.h) */ /* 0x20008000-0x20ffffff: Reserved */ #define SAM_INTSRAM1_BASE 0x21000000 /* 0x21000000-0x210007ff: HRAMC1 (see chip.h) */ /* 0x21000800-0x21ffffff: Reserved */ + /* Peripherals Space */ #define SAM_PERIPHA_BASE 0x40000000 /* 0x40000000-0x4009ffff: Peripheral Bridge A */ @@ -60,7 +62,9 @@ #define SAM_PERIPHC_BASE 0x400e0000 /* 0x400e0000-0x400effff: Peripheral Bridge C */ #define SAM_PERIPHD_BASE 0x400e0000 /* 0x400f0000-0x400fffff: Peripheral Bridge D */ /* 0x40100000-0x5fffffff: Reserved */ + /* Peripheral Bridge A */ + /* 0x40000000-0x40003fff: Reserved */ #define SAM_I2SC_BASE 0x40004000 /* 0x40004000-0x40007fff: I2S Controller */ #define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ @@ -93,6 +97,7 @@ #define SAM_TWIM3_BASE 0x4007c000 /* 0x4007c000-0x4007ffff: Two-wire Master Interface 3 */ #define SAM_LCDCA_BASE 0x40080000 /* 0x40080000-0x40083fff: LCD Controller A */ /* 0x40084000-0x4009ffff: Reserved */ + /* Peripheral Bridge B */ #define SAM_FLASHCALW_BASE 0x400a0000 /* 0x400a0000-0x400a03ff: FLASHCALW */ @@ -104,6 +109,7 @@ #define SAM_USBC_BASE 0x400a5000 /* 0x400a5000-0x400a5fff: USB 2.0 Interface */ #define SAM_PEVC_BASE 0x400a6000 /* 0x400a6000-0x400a63ff: Peripheral Event Controller */ /* 0x400a6400-0x400affff: Reserved */ + /* Peripheral Bridge C */ #define SAM_PM_BASE 0x400e0000 /* 0x400e0000-0x400e073f: Power Manager */ @@ -112,6 +118,7 @@ #define SAM_FREQM_BASE 0x400e0c00 /* 0x400e0c00-0x400e0fff: Frequency Meter */ #define SAM_GPIO_BASE 0x400e1000 /* 0x400e1000-0x400e17ff: GPIO */ /* 0x400e1800-0x400effff: Reserved */ + /* Peripheral Bridge D */ #define SAM_BPM_BASE 0x400f0000 /* 0x400f0000-0x400f03ff: Backup Power Manager */ @@ -121,6 +128,7 @@ #define SAM_EIC_BASE 0x400f1000 /* 0x400f1000-0x400f13ff: External Interrupt Controller */ #define SAM_PICOUART_BASE 0x400f1400 /* 0x400f1400-0x400f17ff: PICOUART */ /* 0x400f1800-0x400fffff: Reserved */ + /* System Space */ #define SAM_ITM_BASE 0xe0000000 /* 0xe0000000-0xe0000fff: ITM */ @@ -135,16 +143,16 @@ #define SAM_ROMTAB_BASE 0xe00ff000 /* 0xe00ff000-0xe00fffff: ROM Table */ /* 0xe0100000-0xffffffff: Reserved */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_pdca.h b/arch/arm/src/sam34/hardware/sam4l_pdca.h index 3b1550dbb45..04d5c7b4c65 100644 --- a/arch/arm/src/sam34/hardware/sam4l_pdca.h +++ b/arch/arm/src/sam34/hardware/sam4l_pdca.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_pdca.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* PDCA channel offsets *****************************************************************/ +/* PDCA channel offsets *****************************************************/ #define SAM_PDCA_CHAN_OFFSET(n) ((n) << 6) #define SAM_PDCA_CHAN0_OFFSET 0x0000 @@ -54,7 +54,8 @@ #define SAM_PDCA_CHAN14_OFFSET 0x0380 #define SAM_PDCA_CHAN15_OFFSET 0x03c0 -/* PDCA register offsets ****************************************************************/ +/* PDCA register offsets ****************************************************/ + /* Channel register offsets */ #define SAM_PDCA_MAR_OFFSET 0x0000 /* Memory Address Register */ @@ -74,7 +75,8 @@ #define SAM_PDCA_VERSION_OFFSET 0x834 /* Version Register */ -/* PDCA channel addresses ***************************************************************/ +/* PDCA channel addresses ***************************************************/ + /* Channel register base addresses */ #define SAM_PDCA_CHAN(n) (SAM_PDCA_BASE+SAM_PDCA_CHAN_OFFSET(n)) @@ -95,7 +97,8 @@ #define SAM_PDCA_CHAN14 (SAM_PDCA_BASE+SAM_PDCA_CHAN14_OFFSET) #define SAM_PDCA_CHAN15 (SAM_PDCA_BASE+SAM_PDCA_CHAN15_OFFSET) -/* PDCA register addresses **************************************************************/ +/* PDCA register addresses **************************************************/ + /* Channel register addresses */ #define SAM_PDCA_MAR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_MAR_OFFSET) @@ -115,7 +118,7 @@ #define SAM_PDCA_VERSION (SAM_PDCA_BASE+SAM_PDCA_VERSION_OFFSET) -/* PDCA register bit definitions ********************************************************/ +/* PDCA register bit definitions ********************************************/ /* Memory Address Register (32-bit address) */ @@ -125,7 +128,7 @@ /* Transfer Counter Register */ -#define PDCA_TCR_MASK 0xffff /* Bits 0-15: Transfer Counter Value +#define PDCA_TCR_MASK 0xffff /* Bits 0-15: Transfer Counter Value */ /* Memory Address Reload Register (32-bit address) */ @@ -158,7 +161,9 @@ #define PDCA_IER_ /* Interrupt Disable Register */ + /* Interrupt Mask Register */ + /* Interrupt Status Register */ #define PDCA_INT_RCZ (1 << 2) /* Bit 0: Reload Counter Zero */ @@ -174,16 +179,16 @@ #define PDCA_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ #define PDCA_VARIANT_MASK (15 << PDCA_VARIANT_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_picouart.h b/arch/arm/src/sam34/hardware/sam4l_picouart.h index 6498cd8a3be..4a6821a44f0 100644 --- a/arch/arm/src/sam34/hardware/sam4l_picouart.h +++ b/arch/arm/src/sam34/hardware/sam4l_picouart.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_picouart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* PICOUART register offsets ************************************************************/ +/* PICOUART register offsets ************************************************/ #define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ #define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */ @@ -42,7 +42,7 @@ #define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */ #define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ -/* PICOUART register addresses **********************************************************/ +/* PICOUART register addresses **********************************************/ #define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ #define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */ @@ -55,7 +55,7 @@ #define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ #define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */ -/* PICOUART register bit definitions ****************************************************/ +/* PICOUART register bit definitions ****************************************/ /* Control Register */ @@ -70,6 +70,7 @@ # define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */ # define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */ # define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */ + #define PICOUART_CFG_ACTION (1 << 0) /* Bit 0: Action to perform */ #define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */ #define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */ @@ -91,16 +92,16 @@ #define PICOUART_VARIANT_SHIFT (16) /* Bits 16-18: Reserved */ #define PICOUART_VARIANT_MASK (7 << PICOUART_VARIANT_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_pinmap.h b/arch/arm/src/sam34/hardware/sam4l_pinmap.h index 19bd175f3c7..c4b18312bd9 100644 --- a/arch/arm/src/sam34/hardware/sam4l_pinmap.h +++ b/arch/arm/src/sam34/hardware/sam4l_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,40 +16,41 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if - * SPI MSIO connects vis PA21 on some board, then the following definition should - * appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if SPI MSIO connects vis PA21 on some board, then the following + * definition should appear in the board.h header file for that board: * * #define GPIO_SPI_MISO GPIO_SPI_MISO_1 * * The driver will then automatically configure PA21 as the SPI MISO pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* Audio Bitstream DAC */ @@ -528,19 +529,19 @@ #define GPIO_USBC_DM (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN25) #define GPIO_USBC_DP (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN26) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -551,9 +552,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/hardware/sam4l_pm.h b/arch/arm/src/sam34/hardware/sam4l_pm.h index a3cba58bc12..654fd8a124c 100644 --- a/arch/arm/src/sam34/hardware/sam4l_pm.h +++ b/arch/arm/src/sam34/hardware/sam4l_pm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_pm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************/ +/* Register offsets *********************************************************/ #define SAM_PM_MCCTRL_OFFSET 0x0000 /* Main Clock Control Register */ #define SAM_PM_CPUSEL_OFFSET 0x0004 /* CPU Clock Select Register */ @@ -66,7 +66,7 @@ #define SAM_PM_CONFIG_OFFSET 0x03f8 /* Configuration Register */ #define SAM_PM_VERSION_OFFSET 0x03fc /* Version Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define SAM_PM_MCCTRL (SAM_PM_BASE+SAM_PM_MCCTRL_OFFSET) #define SAM_PM_CPUSEL (SAM_PM_BASE+SAM_PM_CPUSEL_OFFSET) @@ -98,7 +98,7 @@ #define SAM_PM_CONFIG (SAM_PM_BASE+SAM_PM_CONFIG_OFFSET) #define SAM_PM_VERSION (SAM_PM_BASE+SAM_PM_VERSION_OFFSET) -/* Register Bit-field Definitions ***************************************************/ +/* Register Bit-field Definitions *******************************************/ /* Main Clock Control Register Bit-field Definitions */ @@ -231,10 +231,15 @@ # define PM_UNLOCK_KEY(n) ((n) << PM_UNLOCK_KEY_SHIFT) /* Interrupt Enable Register Bit-field Definitions */ + /* Interrupt Disable Register Bit-field Definitions */ + /* Interrupt Mask Register Bit-field Definitions */ + /* Interrupt Status Register Bit-field Definitions */ + /* Interrupt Clear Register Bit-field Definitions */ + /* Status Register Register */ #define PM_INT_CFD (1 << 0) /* Bit 0: CFD */ @@ -318,16 +323,16 @@ #define PM_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ #define PM_VERSION_VARIANT_MASK (15 << PM_VERSION_VARIANT_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_scif.h b/arch/arm/src/sam34/hardware/sam4l_scif.h index 6c5f075e3a3..755ccc9948e 100644 --- a/arch/arm/src/sam34/hardware/sam4l_scif.h +++ b/arch/arm/src/sam34/hardware/sam4l_scif.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_scif.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SCIF register offsets ****************************************************************/ +/* SCIF register offsets ****************************************************/ #define SAM_SCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */ #define SAM_SCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */ @@ -83,7 +83,7 @@ #define SAM_SCIF_GCLKVERSION_OFFSET 0x03f8 /* Generic Clock Version Register */ #define SAM_SCIF_VERSION_OFFSET 0x03fc /* SCIF Version Register */ -/* SCIF register addresses **************************************************************/ +/* SCIF register addresses **************************************************/ #define SAM_SCIF_IER (SAM_SCIF_BASE+SAM_SCIF_IER_OFFSET) #define SAM_SCIF_IDR (SAM_SCIF_BASE+SAM_SCIF_IDR_OFFSET) @@ -132,13 +132,18 @@ #define SAM_SCIF_GCLKVERSION (SAM_SCIF_BASE+SAM_SCIF_GCLKVERSION_OFFSET) #define SAM_SCIF_VERSION (SAM_SCIF_BASE+SAM_SCIF_VERSION_OFFSET) -/* SCIF register bit definitions ********************************************************/ +/* SCIF register bit definitions ********************************************/ /* Interrupt Enable Register */ + /* Interrupt Disable Register */ + /* Interrupt Mask Register */ + /* Interrupt Status Register */ + /* Interrupt Clear Register */ + /* Power and Clocks Status Register */ #define SCIF_INT_OSC0RDY (1 << 0) /* Bit 0: OSC0 Ready */ @@ -187,6 +192,7 @@ # define SCIF_OSCCTRL0_STARTUP_512 (13 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 512 4.5 ms */ # define SCIF_OSCCTRL0_STARTUP_1K (14 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 1024 8.9 ms */ # define SCIF_OSCCTRL0_STARTUP_32K2 (15 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2768 285 ms */ + #define SCIF_OSCCTRL0_OSCEN (1 << 16) /* Bit 16: Oscillator Enable */ /* PLL0 Control Register */ @@ -196,11 +202,13 @@ #define SCIF_PLL0_PLLOSC_MASK (3 << SCIF_PLL0_PLLOSC_SHIFT) # define SCIF_PLL0_PLLOSC_OSC0 (0 << SCIF_PLL0_PLLOSC_SHIFT) /* Output clock from Oscillator0 */ # define SCIF_PLL0_PLLOSC_GCLK9 (1 << SCIF_PLL0_PLLOSC_SHIFT) /* Generic clock 9 */ + #define SCIF_PLL0_PLLOPT_SHIFT (3) /* Bits 3-5: PLL Option */ #define SCIF_PLL0_PLLOPT_MASK (7 << SCIF_PLL0_PLLOPT_SHIFT) # define SCIF_PLL0_PLLOPT_FVO (1 << SCIF_PLL0_PLLOPT_SHIFT) /* Selects the VCO frequency range (fvco) */ # define SCIF_PLL0_PLLOPT_DIV2 (2 << SCIF_PLL0_PLLOPT_SHIFT) /* Divides the output frequency by 2 */ # define SCIF_PLL0_PLLOPT_WBM (4 << SCIF_PLL0_PLLOPT_SHIFT) /* Wide-Bandwidth mode */ + #define SCIF_PLL0_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */ #define SCIF_PLL0_PLLDIV_MASK (15 << SCIF_PLL0_PLLDIV_SHIFT) #define SCIF_PLL0_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */ @@ -209,7 +217,8 @@ #define SCIF_PLL0_PLLCOUNT_MASK (63 << SCIF_PLL0_PLLCOUNT_SHIFT) # define SCIF_PLL0_PLLCOUNT_MAX (63 << SCIF_PLL0_PLLCOUNT_SHIFT) -/* PLL0 operates in two frequency ranges as determined by SCIF_PLL0_PLLOPT_FVO: +/* PLL0 operates in two frequency ranges as determined by + * SCIF_PLL0_PLLOPT_FVO: * * 0: 80MHz < fvco < 180MHz * 1: 160MHz < fvco < 240MHz @@ -240,6 +249,7 @@ # define SCIF_DFLL0CONF_RANGE1 (1 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 50-110MHz */ # define SCIF_DFLL0CONF_RANGE2 (2 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 25-55MHz */ # define SCIF_DFLL0CONF_RANGE3 (3 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 20-30MHz */ + #define SCIF_DFLL0CONF_FCD (1 << 23) /* Bit 23: Fuse Calibration Done */ #define SCIF_DFLL0CONF_CALIB_SHIFT (24) /* Bits 24-27: Calibration Value */ #define SCIF_DFLL0CONF_CALIB_MASK (15 << SCIF_DFLL0CONF_CALIB_SHIFT) @@ -311,6 +321,7 @@ # define SCIF_RCFASTCFG_FRANGE_4MHZ (0 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 4MHz range selected */ # define SCIF_RCFASTCFG_FRANGE_8MHZ (1 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 8MHz range selected */ # define SCIF_RCFASTCFG_FRANGE_12MHZ (2 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 12MHz range selected */ + #define SCIF_RCFASTCFG_LOCKMARGIN_SHIFT (12) /* Bits 12-15: Accepted Count Error for Lock */ #define SCIF_RCFASTCFG_LOCKMARGIN_MASK (15 << SCIF_RCFASTCFG_LOCKMARGIN_SHIFT) #define SCIF_RCFASTCFG_CALIB_SHIFT (16) /* Bits 16-22: Oscillator Calibration Value */ @@ -383,18 +394,27 @@ # define SCIF_GCCTRL_OSCSEL_GCLKIN0 (19 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN0 */ # define SCIF_GCCTRL_OSCSEL_GCLKIN1 (20 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN1 */ # define SCIF_GCCTRL_OSCSEL_GCLK11 (21 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLK11 */ + #define SCIF_GCCTRL_DIV_SHIFT (16) /* Bits 16-31: Division Factor */ #define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT) # define SCIF_GCCTRL_DIV(n) ((n) << SCIF_GCCTRL_DIV_SHIFT) /* 4/8/12MHz RC Oscillator Version Register */ + /* Generic Clock Prescaler Version Register */ + /* PLL Version Register */ + /* Oscillator0 Version Register */ + /* DFLL Version Register */ + /* System RC Oscillator Version Register */ + /* 80MHz RC Oscillator Version Register */ + /* Generic Clock Version Register */ + /* SCIF Version Register */ #define SCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */ @@ -402,16 +422,16 @@ #define SCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ #define SCIF_VARIANT_MASK (15 << SCIF_VARIANT_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_usart.h b/arch/arm/src/sam34/hardware/sam4l_usart.h index 865471364c0..bbfaee3efc1 100644 --- a/arch/arm/src/sam34/hardware/sam4l_usart.h +++ b/arch/arm/src/sam34/hardware/sam4l_usart.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_usart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* USART register offsets ***********************************************************************/ +/* USART register offsets ***************************************************/ #define SAM_UART_CR_OFFSET 0x0000 /* Control Register */ #define SAM_UART_MR_OFFSET 0x0004 /* Mode Register */ @@ -63,7 +63,7 @@ #define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register */ /* 0x0100-0x0124: PDC Area */ -/* USART register addresses *********************************************************************/ +/* USART register addresses *************************************************/ #define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET) #define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET) @@ -175,7 +175,7 @@ #define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET) #define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET) -/* USART register bit definitions ***************************************************************/ +/* USART register bit definitions *******************************************/ /* USART Control Register */ @@ -214,17 +214,20 @@ # define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */ # define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master */ # define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave */ + #define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */ #define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) # define UART_MR_USCLKS_USART (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART */ # define UART_MR_USCLKS_USARTDIV (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART/DIV(1) */ # define UART_MR_USCLKS_CLK (0 << UART_MR_USCLKS_SHIFT) /* CLK */ + #define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length */ #define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) # define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */ # define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */ # define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */ # define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ + #define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select */ #define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase */ #define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type */ @@ -235,17 +238,20 @@ # define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 */ # define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity */ # define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode */ + #define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits */ #define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT) # define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ # define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ # define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ + #define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */ #define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) # define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ # define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ # define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ # define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ + #define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first */ #define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity */ #define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length */ @@ -262,7 +268,8 @@ #define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode */ #define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector */ -/* USART Interrupt Enable Register, USART Interrupt Disable Register, USART Interrupt Mask +/* USART Interrupt Enable Register + * USART Interrupt Disable Register, USART Interrupt Mask * Register, and USART Status Register common bit field definitions. * * - Bits that provide interrupts with UART_INT_ @@ -357,6 +364,7 @@ # define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */ # define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */ + #define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity */ #define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length */ #define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT) @@ -366,6 +374,7 @@ # define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */ # define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ + #define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity */ #define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation */ @@ -376,6 +385,7 @@ # define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */ # define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */ # define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does neither */ + #define UART_LINMR_PARDIS (1 << 2) /* Bit 0: Parity Disable */ #define UART_LINMR_CHKDIS (1 << 3) /* Bit 0: Checksum Disable */ #define UART_LINMR_CHKTYP (1 << 4) /* Bit 0: Checksum Type */ @@ -417,16 +427,16 @@ #define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved */ #define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT) -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H */ diff --git a/arch/arm/src/sam34/hardware/sam4l_wdt.h b/arch/arm/src/sam34/hardware/sam4l_wdt.h index ef7ff74f2f1..dd8554b19f3 100644 --- a/arch/arm/src/sam34/hardware/sam4l_wdt.h +++ b/arch/arm/src/sam34/hardware/sam4l_wdt.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4l_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* WDT register offsets ****************************************************************/ +/* WDT register offsets *****************************************************/ #define SAM_WDT_CTRL_OFFSET 0x0000 /* Control Register */ #define SAM_WDT_CLR_OFFSET 0x0004 /* Clear Register */ @@ -46,7 +46,7 @@ #define SAM_WDT_ICR_OFFSET 0x001c /* Interrupt Clear Register */ #define SAM_WDT_VERSION_OFFSET 0x03fc /* Version Register */ -/* WDT register addresses **************************************************************/ +/* WDT register addresses ***************************************************/ #define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET) #define SAM_WDT_CLR (SAM_WDT_BASE+SAM_WDT_CLR_OFFSET) @@ -58,7 +58,7 @@ #define SAM_WDT_ICR (SAM_WDT_BASE+SAM_WDT_ICR_OFFSET) #define SAM_WDT_VERSION (SAM_WDT_BASE+SAM_WDT_VERSION_OFFSET) -/* WDT register bit definitions ********************************************************/ +/* WDT register bit definitions *********************************************/ /* Control Register */ @@ -93,9 +93,13 @@ #define WDT_SR_CLEARED (1 << 1) /* Bit 1: WDT Counter Cleared */ /* Interrupt Enable Register */ + /* Interrupt Disable Register */ + /* Interrupt Mask Register */ + /* Interrupt Status Register */ + /* Interrupt Clear Register */ #define WDT_WINT (1 << 2) /* Bit 2: WINT */ @@ -107,16 +111,16 @@ #define WDT_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */ #define WDT_VARIANT_MASK (15 << WDT_VARIANT_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H */ diff --git a/arch/arm/src/sam34/hardware/sam4s_memorymap.h b/arch/arm/src/sam34/hardware/sam4s_memorymap.h index 5922b77eb54..7e1d5006038 100644 --- a/arch/arm/src/sam34/hardware/sam4s_memorymap.h +++ b/arch/arm/src/sam34/hardware/sam4s_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4s_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ /* Address regions */ @@ -47,11 +47,13 @@ #define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */ #define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */ /* 0x00c00000-0x1fffffff: Reserved */ + /* Internal SRAM memory region */ #define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */ #define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */ /* 0x24000000-0x3fffffff: Undefined */ + /* Peripherals address region */ #define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ @@ -89,6 +91,7 @@ /* 0x40100000-0x4002ffff: Reserved */ #define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32MB bit-band region */ /* 0x44000000-0x5fffffff: Reserved */ + /* System Controller Register Blocks: 0x400e0000-0x4007ffff */ #define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ @@ -112,6 +115,7 @@ #define SAM_RTC_BASE 0x400e1460 /* 0x400e1460-0x400e148f: Real Time Clock */ #define SAM_GPBR_BASE 0x400e1490 /* 0x400e1490-0x400e15ff: GPBR */ /* 0x400e1600-0x4007ffff: Reserved */ + /* External RAM memory region */ #define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ @@ -121,21 +125,22 @@ # define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ # define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ /* 0x64000000-0x9fffffff: Reserved */ + /* System memory region */ #define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ #define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H */ diff --git a/arch/arm/src/sam34/hardware/sam4s_pinmap.h b/arch/arm/src/sam34/hardware/sam4s_pinmap.h index 9c18dccd669..d8a751d6ba5 100644 --- a/arch/arm/src/sam34/hardware/sam4s_pinmap.h +++ b/arch/arm/src/sam34/hardware/sam4s_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4s_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,42 +16,44 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ -/* GPIO pin definitions *************************************************************/ /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the programmable clock output PCK0 on PA6, then the following definition - * should appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if we wanted the programmable clock output PCK0 on PA6, then the + * following definition should appear in the board.h header file for that + * board: * * #define GPIO_PCK0 GPIO_PCK0_1 * * The driver will then automatically configure PA6 as the PCK0 pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* 12-bit Analog-to-Digital Converter (ADC) */ @@ -263,19 +265,19 @@ #define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) #define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -286,9 +288,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/hardware/sam4s_pio.h b/arch/arm/src/sam34/hardware/sam4s_pio.h index 396cae6da4f..42d1c631f90 100644 --- a/arch/arm/src/sam34/hardware/sam4s_pio.h +++ b/arch/arm/src/sam34/hardware/sam4s_pio.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam4s_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* PIO register offsets *****************************************************************/ +/* PIO register offsets *****************************************************/ #define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ #define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ @@ -105,7 +105,7 @@ #define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */ /* 0x0168-0x018c: Reserved for PDC registers */ -/* PIO register addresses ***************************************************************/ +/* PIO register addresses ***************************************************/ #define PIOA (0) #define PIOB (1) @@ -332,7 +332,7 @@ #define SAM_PIOC_PCISR (SAM_PIOC_BASE+SAM_PIO_PCISR_OFFSET) #define SAM_PIOC_PCRHR (SAM_PIOC_BASE+SAM_PIO_PCRHR_OFFSET -/* PIO register bit definitions *********************************************************/ +/* PIO register bit definitions *********************************************/ /* Common bit definitions for ALMOST all IO registers (exceptions follow) */ @@ -359,27 +359,30 @@ # define PIO_PCMR_DSIZE_BYTE (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */ # define PIO_PCMR_DSIZE_HWORD (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */ # define PIO_PCMR_DSIZE_WORD (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */ + #define PIO_PCMR_ALWYS (1 << 9) /* Bit 9: Parallel Capture Mode Always Sampling */ #define PIO_PCMR_HALFS (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */ #define PIO_PCMR_FRSTS (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */ -/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */ +/* PIO Parallel Capture Interrupt Enable, Disable, Mask, + * and Status Registers + */ #define PIOC_PCINT_DRDY (1 << 0) /* Bit 0: Parallel Capture Mode Data Ready Interrupt Enable */ #define PIOC_PCINT_OVRE (1 << 1) /* Bit 1: Parallel Capture Mode Overrun Error Interrupt Enable */ #define PIOC_PCINT_ENDRX (1 << 2) /* Bit 2: End of Reception Transfer Interrupt Enable */ #define PIOC_PCINT_RXBUFF (1 << 3) /* Bit 3: Reception Buffer Full Interrupt Enable */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H */ diff --git a/arch/arm/src/sam34/hardware/sam_acc.h b/arch/arm/src/sam34/hardware/sam_acc.h index e1d8e3d95b9..3bfae732134 100644 --- a/arch/arm/src/sam34/hardware/sam_acc.h +++ b/arch/arm/src/sam34/hardware/sam_acc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_acc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* ACC register offsets *****************************************************************/ +/* ACC register offsets *****************************************************/ #define SAM_ACC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_ACC_MR_OFFSET 0x0004 /* Mode Register */ @@ -46,7 +46,7 @@ #define SAM_ACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ #define SAM_ACC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ -/* ACC register addresses **************************************************************/ +/* ACC register addresses ***************************************************/ #define SAM_ACC_CR (SAM_ACC_BASE+SAM_ACC_CR_OFFSET) #define SAM_ACC_MR (SAM_ACC_BASE+SAM_ACC_MR_OFFSET) @@ -58,7 +58,7 @@ #define SAM_ACC_WPMR (SAM_ACC_BASE+SAM_ACC_WPMR_OFFSET) #define SAM_ACC_WPSR (SAM_ACC_BASE+SAM_ACC_WPSR_OFFSET -/* ACC register bit definitions ********************************************************/ +/* ACC register bit definitions *********************************************/ /* Control Register */ @@ -76,9 +76,11 @@ # define ACC_MR_SELMINUS_AD1 (5 << ACC_MR_SELMINUS_SHIFT) /* Select AD1 */ # define ACC_MR_SELMINUS_AD2 (6 << ACC_MR_SELMINUS_SHIFT) /* Select AD2 */ # define ACC_MR_SELMINUS_AD3 (7 << ACC_MR_SELMINUS_SHIFT) /* Select AD3 */ + #define ACC_MR_SELPLUS_SHIFT (4) /* Bits 4-6: Selection for plus comparator input */ #define ACC_MR_SELPLUS_MASK (7 << ACC_MR_SELPLUS_SHIFT) # define ACC_MR_SELPLUS_AD(n) ((uint32_t)(n) << ACC_MR_SELPLUS_SHIFT) /* Select and, n=0-7 */ + # define ACC_MR_SELPLUS_AD0 (0 << ACC_MR_SELPLUS_SHIFT) /* Select AD0 */ # define ACC_MR_SELPLUS_AD1 (1 << ACC_MR_SELPLUS_SHIFT) /* Select AD1 */ # define ACC_MR_SELPLUS_AD2 (2 << ACC_MR_SELPLUS_SHIFT) /* Select AD2 */ @@ -87,17 +89,21 @@ # define ACC_MR_SELPLUS_AD5 (5 << ACC_MR_SELPLUS_SHIFT) /* Select AD5 */ # define ACC_MR_SELPLUS_AD6 (6 << ACC_MR_SELPLUS_SHIFT) /* Select AD6 */ # define ACC_MR_SELPLUS_AD7 (7 << ACC_MR_SELPLUS_SHIFT) /* Select AD7 */ + #define ACC_MR_ACEN (1 << 8) /* Bit 8: Analog comparator enable */ #define ACC_MR_EDGETYP_SHIFT (9) /* Bits 9-10: Edge type */ #define ACC_MR_EDGETYP_MASK (3 << ACC_MR_EDGETYP_SHIFT) # define ACC_MR_EDGETYP_RISING (0 << ACC_MR_EDGETYP_SHIFT) /* Only rising edge of comparator output */ # define ACC_MR_EDGETYP_FALLING (1 << ACC_MR_EDGETYP_SHIFT) /* Falling edge of comparator output */ # define ACC_MR_EDGETYP_ANY (2 << ACC_MR_EDGETYP_SHIFT) /* Any edge of comparator output */ + #define ACC_MR_INV (1 << 12) /* Bit 12: Invert comparator output */ #define ACC_MR_SELFS (1 << 13) /* Bit 13: Selection of fault source */ #define ACC_MR_FE (1 << 14) /* Bit 14: Fault enable */ -/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status */ +/* Interrupt Enable, Interrupt Disable, Interrupt Mask, + * and Interrupt Status + */ #define ACC_INT_CE (1 << 0) /* Bit 0: Comparison edge interrupt */ @@ -123,16 +129,16 @@ #define ACC_WPSR_WPROTERR (1 << 0) /* Bit 0: Write protection error */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_adc.h b/arch/arm/src/sam34/hardware/sam_adc.h index 15b99b0d16e..68b782d6a4e 100644 --- a/arch/arm/src/sam34/hardware/sam_adc.h +++ b/arch/arm/src/sam34/hardware/sam_adc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General definitions ******************************************************************/ + ****************************************************************************/ + +/* General definitions ******************************************************/ #define SAM_ADC_NCHANNELS 8 /* 8 ADC Channels */ -/* ADC register offsets *****************************************************************/ +/* ADC register offsets *****************************************************/ #define SAM_ADC_CR_OFFSET 0x00 /* Control Register (Both) */ #define SAM_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */ @@ -63,7 +64,7 @@ #define SAM_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */ #define SAM_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */ -/* ADC register addresses ***************************************************************/ +/* ADC register addresses ***************************************************/ #define SAM_ADC12B_CR (SAM_ADC12B_BASE+SAM_ADC_CR_OFFSET) #define SAM_ADC12B_MR (SAM_ADC12B_BASE+SAM_ADC_MR_OFFSET) @@ -107,14 +108,18 @@ # define SAM_ADC_CDR6 (SAM_ADC_BASE+SAM_ADC_CDR6_OFFSET) # define SAM_ADC_CDR7 (SAM_ADC_BASE+SAM_ADC_CDR7_OFFSET) -/* ADC register bit definitions *********************************************************/ +/* ADC register bit definitions *********************************************/ -/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */ +/* ADC12B Control Register and ADC(10B) Control Register common bit-field + * definitions + */ #define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */ #define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */ -/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */ +/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field + * definitions + */ #define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */ #define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */ @@ -135,8 +140,9 @@ #define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT) # define ADC_MR_SHTIM(n) ((uint32_t)(n) << ADC_MR_SHTIM_SHIFT) -/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel - * Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register, +/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, + * ADC12B Channel Status Register, ADC(10B) Channel Enable Register, + * ADC(10B) Channel Disable Register, * and ADC(10B) Channel Status Register common bit-field definitions */ @@ -168,9 +174,10 @@ #define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT) # define ADC12B_EMR_OFFMSTIME(n) ((uint32_t)(n) << ADC12B_EMR_OFFMSTIME_SHIFT) -/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt - * Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register, - * ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and +/* ADC12B Status Register , ADC12B Interrupt Enable Register, + * ADC12B Interrupt Disable Register, ADC12B Interrupt Mask Register, + * ADC(10B) Status Register, ADC(10B) Interrupt Enable Register, + * ADC(10B) Interrupt Disable Register, and * ADC(10B) Interrupt Mask Register common bit-field definitions */ @@ -217,16 +224,16 @@ #define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */ #define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_aes.h b/arch/arm/src/sam34/hardware/sam_aes.h index 56c4180192d..cde72ae73a3 100644 --- a/arch/arm/src/sam34/hardware/sam_aes.h +++ b/arch/arm/src/sam34/hardware/sam_aes.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_aes.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* AES register offsets *****************************************************************/ +/* AES register offsets *****************************************************/ #define SAM_AES_CR_OFFSET 0x0000 /* Control Register */ #define SAM_AES_MR_OFFSET 0x0004 /* Mode Register */ @@ -65,7 +65,7 @@ #define SAM_AES_IVR3_OFFSET 0x006c /* Initialization Vector Register 3 */ /* 0x0070-0x00fc: Reserved */ -/* AES register addresses ***************************************************************/ +/* AES register addresses ***************************************************/ #define SAM_AES_CR (SAM_AES_BASE+SAM_AES_CR_OFFSET) #define SAM_AES_MR (SAM_AES_BASE+SAM_AES_MR_OFFSET) @@ -94,7 +94,7 @@ #define SAM_AES_IVR2 (SAM_AES_BASE+SAM_AES_IVR2_OFFSET) #define SAM_AES_IVR3 (SAM_AES_BASE+SAM_AES_IVR3_OFFSET) -/* AES register bit definitions ********************************************************/ +/* AES register bit definitions *********************************************/ /* Control Register */ @@ -113,11 +113,13 @@ # define AES_MR_SMOD_MANUAL (0 << AES_MR_SMOD_SHIFT) /* Manual Mode */ # define AES_MR_SMOD_AUTO (1 << AES_MR_SMOD_SHIFT) /* Auto Mode */ # define AES_MR_SMOD_IDATR0 (2 << AES_MR_SMOD_SHIFT) /* AES_IDATAR0 access only Auto Mode */ + #define AES_MR_KEYSIZE_SHIFT (10) /* Bits 10-11: Key Size */ #define AES_MR_KEYSIZE_MASK (2 << AES_MR_KEYSIZE_SHIFT) # define AES_MR_KEYSIZE_AES128 (0 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 128 bits */ # define AES_MR_KEYSIZE_AES192 (1 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 192 bits */ # define AES_MR_KEYSIZE_AES256 (2 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 256 bits */ + #define AES_MR_OPMOD_SHIFT (12) /* Bits 12-14: Operation Mode */ #define AES_MR_OPMOD_MASK (7 << AES_MR_OPMOD_SHIFT) # define AES_MR_OPMOD_ECB (0 << AES_MR_OPMOD_SHIFT) /* ECB: Electronic Code Book mode */ @@ -125,6 +127,7 @@ # define AES_MR_OPMOD_OFB (2 << AES_MR_OPMOD_SHIFT) /* OFB: Output Feedback mode */ # define AES_MR_OPMOD_CFB (3 << AES_MR_OPMOD_SHIFT) /* CFB: Cipher Feedback mode */ # define AES_MR_OPMOD_CTR (4 << AES_MR_OPMOD_SHIFT) /* CTR: Counter mode (16-bit counter) */ + #define AES_MR_LOD (1 << 15) /* Bit 15: Last Output Data Mode */ #define AES_MR_CFBS_SHIFT (16) /* Bits 16-18: Cipher Feedback Data Size */ #define AES_MR_CFBS_MASK (7 << AES_MR_CFBS_SHIFT) @@ -133,11 +136,14 @@ # define AES_MR_CFBS_32BIT (2 << AES_MR_CFBS_SHIFT) /* 32-bit */ # define AES_MR_CFBS_16BIT (3 << AES_MR_CFBS_SHIFT) /* 16-bit */ # define AES_MR_CFBS_8BIT (4 << AES_MR_CFBS_SHIFT) /* 8-bit */ + #define AES_MR_CKEY_SHIFT (20) /* Bits 20-23: Key */ #define AES_MR_CKEY_MASK (15 << AES_MR_CKEY_SHIFT) # define AES_MR_CKEY (14 << AES_MR_CKEY_SHIFT) -/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */ +/* Interrupt Enable, Interrupt Disable, Interrupt Mask, + * and Interrupt Status Register + */ #define AES_INT_DATRDY (1 << 0) /* Bit 0: Data Ready Interrupt */ #define AES_INT_URAD (1 << 8) /* Bit 8: Unspecified Register Access Detection Interrupt */ @@ -154,19 +160,21 @@ # define AES_ISR_URAT_WORRDACC (5 << AES_ISR_URAT_SHIFT) /* WRONLY register read access */ /* Key Word Register 0-7 (32-bit value) */ + /* Input Data Register 0-7 (32-bit value) */ + /* Initialization Vector Register 0-7 (32-bit value) */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H */ diff --git a/arch/arm/src/sam34/hardware/sam_afec.h b/arch/arm/src/sam34/hardware/sam_afec.h index 2399b29dcbe..cafb4e638e2 100644 --- a/arch/arm/src/sam34/hardware/sam_afec.h +++ b/arch/arm/src/sam34/hardware/sam_afec.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_afec.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General definitions ******************************************************************/ + ****************************************************************************/ + +/* General definitions ******************************************************/ #define SAM_ADC_NCHANNELS 16 /* 16 ADC Channels */ -/* AFEC register offsets ****************************************************************/ +/* AFEC register offsets ****************************************************/ #define SAM_AFEC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_AFEC_MR_OFFSET 0x0004 /* Mode Register */ @@ -73,7 +74,7 @@ /* 0x0fc Reserved */ /* 0x0100-0x0124 Reserved for PDC */ -/* AFEC register addresses **************************************************************/ +/* AFEC register addresses **************************************************/ #define SAM_AFEC0_CR (SAM_AFEC0_BASE+SAM_AFEC_CR_OFFSET) #define SAM_AFEC0_MR (SAM_AFEC0_BASE+SAM_AFEC_MR_OFFSET) @@ -129,7 +130,7 @@ #define SAM_AFEC1_WPMR (SAM_AFEC1_BASE+SAM_AFEC_WPMR_OFFSET) #define SAM_AFEC1_WPSR (SAM_AFEC1_BASE+SAM_AFEC_WPSR_OFFSET) -/* AFEC register bit definitions *******************************************************/ +/* AFEC register bit definitions ********************************************/ /* Control Register */ @@ -148,6 +149,7 @@ # define AFEC_MR_TRGSEL_TIOA2 (3 << AFEC_MR_TRGSEL_SHIFT) /* TIOA2 */ # define AFEC_MR_TRGSEL_PWM0 (4 << AFEC_MR_TRGSEL_SHIFT) /* PWM Event Line 0 */ # define AFEC_MR_TRGSEL_PWM1 (5 << AFEC_MR_TRGSEL_SHIFT) /* PWM Event Line 1 */ + #define AFEC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ #define AFEC_MR_FWUP (1 << 6) /* Bit 6: Fast Wake Up */ #define AFEC_MR_FREERUN (1 << 7) /* Bit 7: Free Run Mode */ @@ -172,12 +174,14 @@ # define AFEC_MR_STARTUP_832 (13 << AFEC_MR_STARTUP_SHIFT) /* 832 periods of ADCClock */ # define AFEC_MR_STARTUP_896 (14 << AFEC_MR_STARTUP_SHIFT) /* 896 periods of ADCClock */ # define AFEC_MR_STARTUP_960 (15 << AFEC_MR_STARTUP_SHIFT) /* 960 periods of ADCClock */ + #define AFEC_MR_SETTLING_SHIFT (20) /* Bits 20-21: Analog Settling Time */ #define AFEC_MR_SETTLING_MASK (15 << AFEC_MR_SETTLING_SHIFT) # define AFEC_MR_SETTLING_3 (0 << AFEC_MR_SETTLING_SHIFT) /* 3 periods of ADCClock */ # define AFEC_MR_SETTLING_5 (1 << AFEC_MR_SETTLING_SHIFT) /* 5 periods of ADCClock */ # define AFEC_MR_SETTLING_9 (2 << AFEC_MR_SETTLING_SHIFT) /* 9 periods of ADCClock */ # define AFEC_MR_SETTLING_17 (3 << AFEC_MR_SETTLING_SHIFT) /* 17 periods of ADCClock */ + #define AFEC_MR_ANACH (1 << 23) /* Bit 23: Analog Change */ #define AFEC_MR_TRACKTIM_SHIFT (24) /* Bits 24-27: Tracking Time */ #define AFEC_MR_TRACKTIM_MASK (15 << AFEC_MR_TRACKTIM_SHIFT) @@ -195,6 +199,7 @@ # define AFEC_EMR_CMPMODE_HIGH (1 << AFEC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */ # define AFEC_EMR_CMPMODE_IN (2 << AFEC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */ # define AFEC_EMR_CMPMODE_OUT (3 << AFEC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */ + #define AFEC_EMR_CMPSEL_SHIFT (3) /* Bit 3-7: Comparison Selected Channel */ #define AFEC_EMR_CMPSEL_MASK (31 << AFEC_EMR_CMPSEL_SHIFT) # define AFEC_EMR_CMPSEL(n) ((uint32_t)(n) << AFEC_EMR_CMPSEL_SHIFT) @@ -210,6 +215,7 @@ # define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */ # define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */ # define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */ + #define AFEC_EMR_TAG (1 << 24) /* Bit 24: TAG of the AFEC_LDCR register */ #define AFEC_EMR_STM (1 << 25) /* Bit 25: Single Trigger Mode */ @@ -301,7 +307,9 @@ #define AFEC_LCDR_CHANB_SHIFT (24) /* Bits 24-27: Channel number */ #define AFEC_LCDR_CHANB_MASK (15 << AFEC_LCDR_CHANB_SHIFT) -/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Registers */ +/* Interrupt Enable, Interrupt Disable, Interrupt Mask, + * and Interrupt Status Registers + */ #define AFEC_INT_EOC(n) (1 << (n)) # define AFEC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */ @@ -415,7 +423,9 @@ #define AFEC_CGR_GAIN15_MASK (3 << AFEC_CGR_GAIN15_SHIFT) # define AFEC_CGR_GAIN15(v) ((uint32_t)(v) << AFEC_CGR_GAIN15_SHIFT) -/* Channel Calibration DC Offset Register (Used in Automatic Calibration Procedure) */ +/* Channel Calibration DC Offset Register + * (Used in Automatic Calibration Procedure) + */ #define AFEC_CDOR_OFF(n) (1 << (n)) # define AFEC_CDOR_OFF0 (1 << 0) /* Bit 0: Offset for channel 0 */ @@ -507,16 +517,16 @@ #define AFEC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define AFEC_WPSR_WPVSRC_MASK (0x0000ffff << AFEC_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_can.h b/arch/arm/src/sam34/hardware/sam_can.h index e9b1611460d..79927163062 100644 --- a/arch/arm/src/sam34/hardware/sam_can.h +++ b/arch/arm/src/sam34/hardware/sam_can.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_can.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ #define SAM_CAN_NMBOXES 8 /* 8 Mailboxes */ #define SAM_CAN_MBOX(n) (n) @@ -45,7 +45,7 @@ #define SAM_CAN_MBOX6 6 #define SAM_CAN_MBOX7 7 -/* CAN register offsets *****************************************************************/ +/* CAN register offsets *****************************************************/ #define SAM_CAN_MR_OFFSET 0x0000 /* Mode Register */ #define SAM_CAN_IER_OFFSET 0x0004 /* Interrupt Enable Register */ @@ -58,10 +58,13 @@ #define SAM_CAN_ECR_OFFSET 0x0020 /* Error Counter Register */ #define SAM_CAN_TCR_OFFSET 0x0024 /* Transfer Command Register */ #define SAM_CAN_ACR_OFFSET 0x0028 /* Abort Command Register */ + /* 0x002c-0x00e0: Reserved */ #define SAM_CAN_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ #define SAM_CAN_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x00eC-0x01fc: Reserved */ + /* Mailbox Registers */ #define SAM_CAN_MBOX_OFFSET(n) (0x0200+((n) << 5)) @@ -74,7 +77,7 @@ #define SAM_CAN_MDH_OFFSET 0x0018 /* Mailbox Data High Register */ #define SAM_CAN_MCR_OFFSET 0x001c /* Mailbox Control Register */ -/* CAN register addresses ***************************************************************/ +/* CAN register addresses ***************************************************/ #define SAM_CAN0_MR (SAM_CAN0_BASE+SAM_CAN_MR_OFFSET) #define SAM_CAN0_IER (SAM_CAN0_BASE+SAM_CAN_IER_OFFSET) @@ -128,7 +131,7 @@ #define SAM_CAN1_MDH(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MDH_OFFSET) #define SAM_CAN1_MCR(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MCR_OFFSET) -/* CAN register bit definitions *********************************************************/ +/* CAN register bit definitions *********************************************/ /* Mode Register */ @@ -144,6 +147,7 @@ /* Interrupt Enable, Interrupt Disable, Interrupt Mask and Status Register */ #define CAN_INT_MB(n) (1 << (n)) /* Bit n: Mailbox n Interrupt */ + #define CAN_INT_ERRA (1 << 16) /* Bit 16: Error Active Mode Interrupt */ #define CAN_INT_WARN (1 << 17) /* Bit 17: Warning Limit Interrupt */ #define CAN_INT_ERRP (1 << 18) /* Bit 18: Error Passive Mode Interrupt */ @@ -179,7 +183,7 @@ #define CAN_BR_BRP_SHIFT (16) /* Bits 16-22: Baudrate Prescaler */ #define CAN_BR_BRP_MASK (127 << CAN_BR_BRP_SHIFT) # define CAN_BR_BRP(n) ((uint32_t)(n) << CAN_BR_BRP_SHIFT) -#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode +#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode */ /* Timer Register */ @@ -277,6 +281,7 @@ #define CAN_MSR_MMI (1 << 24) /* Bit 24: Mailbox Message Ignored */ /* Mailbox Data Low Register (32-bit value) */ + /* Mailbox Data High Register (32-bit value) */ /* Mailbox Control Register */ @@ -288,16 +293,16 @@ #define CAN_MCR_MACR (1 << 22) /* Bit 22: Abort Request for Mailbox n */ #define CAN_MCR_MTCR (1 << 23) /* Bit 23: Mailbox Transfer Command */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H */ diff --git a/arch/arm/src/sam34/hardware/sam_chipid.h b/arch/arm/src/sam34/hardware/sam_chipid.h index 1c7ca4331b9..cea21144368 100644 --- a/arch/arm/src/sam34/hardware/sam_chipid.h +++ b/arch/arm/src/sam34/hardware/sam_chipid.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_chipid.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,35 +16,35 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* CHIPID register offsets **************************************************************/ +/* CHIPID register offsets **************************************************/ #define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */ #define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */ -/* CHIPID register addresses ************************************************************/ +/* CHIPID register addresses ************************************************/ #define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR) #define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID) -/* CHIPID register bit definitions ******************************************************/ +/* CHIPID register bit definitions ******************************************/ #define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */ #define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT) @@ -57,6 +57,7 @@ # define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */ # define CHIPID_CIDR_EPROC_CORTEXA5 (6 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-A5 */ # define CHIPID_CIDR_EPROC_CORTEXM4 (7 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M4 */ + #define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */ #define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) # define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ @@ -69,6 +70,7 @@ # define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ # define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ # define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ + #define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */ #define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) # define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ @@ -81,6 +83,7 @@ # define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ # define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ # define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ + #define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */ #define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) # define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ @@ -101,6 +104,7 @@ # define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */ # define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */ # define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */ + #define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */ #define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT) # define CHIPID_CIDR_ARCH_AT91SAM9XX (0x19 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */ @@ -144,6 +148,7 @@ # define CHIPID_CIDR_ARCH_SAM4LB (0xb1 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxB Series */ # define CHIPID_CIDR_ARCH_SAM4LC (0xb2 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxC Series */ # define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ + #define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ #define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) # define CHIPID_CIDR_NVPTYP_ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ @@ -151,6 +156,7 @@ # define CHIPID_CIDR_NVPTYP_SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ # define CHIPID_CIDR_NVPTYP_EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ # define CHIPID_CIDR_NVPTYP_REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ + #define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ /* Chip ID Extension Register (32-bit value for SAM3U and SAM4S) */ @@ -170,16 +176,16 @@ # define CHIPID_EXID_PACKAGE_144PIN (5 << CHIPID_EXID_PACKAGE_SHIFT) /* 144-pin package */ #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H */ diff --git a/arch/arm/src/sam34/hardware/sam_cmcc.h b/arch/arm/src/sam34/hardware/sam_cmcc.h index 470b7faa308..b44bd4a6749 100644 --- a/arch/arm/src/sam34/hardware/sam_cmcc.h +++ b/arch/arm/src/sam34/hardware/sam_cmcc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_cmcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,27 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* This information is available in the Cache Type Register. How every, it is more - * efficient if we do not to do the decoding on each cache access. + ****************************************************************************/ + +/* This information is available in the Cache Type Register. + * How ever, it is more efficient if we do not to do the decoding on each + * cache access. * * CacheSize = CacheLineSize * NCacheLines * NWays * CacheAddressRange = CacheLineSize * NCacheLines = CacheSize / NWays @@ -46,7 +48,7 @@ # define CMCC_NWAYS 4 #endif -/* CMCC register offsets ****************************************************************/ +/* CMCC register offsets ****************************************************/ #define SAM_CMCC_TYPE_OFFSET 0x0000 /* Cache Type Register */ #define SAM_CMCC_CFG_OFFSET 0x0004 /* Cache Configuration Register */ @@ -61,7 +63,7 @@ #define SAM_CMCC_MSR_OFFSET 0x0034 /* Cache Monitor Status Register */ /* 0x0038-0x00fc Reserved */ -/* CMCC register addresses **************************************************************/ +/* CMCC register addresses **************************************************/ #define SAM_CMCC_TYPE (SAM_CMCC_BASE+SAM_CMCC_TYPE_OFFSET) #define SAM_CMCC_CFG (SAM_CMCC_BASE+SAM_CMCC_CFG_OFFSET) @@ -74,7 +76,7 @@ #define SAM_CMCC_MCTRL (SAM_CMCC_BASE+SAM_CMCC_MCTRL_OFFSET) #define SAM_CMCC_MSR (SAM_CMCC_BASE+SAM_CMCC_MSR_OFFSET) -/* CMCC register bit definitions ********************************************************/ +/* CMCC register bit definitions ********************************************/ /* Cache Type Register */ @@ -89,6 +91,7 @@ # define CMCC_TYPE_WAYNUM_ARCH2WAY (1 << CMCC_TYPE_WAYNUM_SHIFT) /* 2-WAY set associative */ # define CMCC_TYPE_WAYNUM_ARCH4WAY (2 << CMCC_TYPE_WAYNUM_SHIFT) /* 4-WAY set associative */ # define CMCC_TYPE_WAYNUM_ARCH8WAY (3 << CMCC_TYPE_WAYNUM_SHIFT) /* 8-WAY set associative */ + #define CMCC_TYPE_LCKDOWN (1 << 7) /* Bit 7: Lock Down Supported */ #define CMCC_TYPE_CSIZE_SHIFT (8) /* Bits 8-10: Cache Size */ #define CMCC_TYPE_CSIZE_MASK (7 << CMCC_TYPE_CSIZE_SHIFT) @@ -96,6 +99,7 @@ # define CMCC_TYPE_CSIZE_2KB (1 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 2 Kbytes */ # define CMCC_TYPE_CSIZE_4KB (2 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 4 Kbytes */ # define CMCC_TYPE_CSIZE_8KB (3 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 8 Kbytes */ + #define CMCC_TYPE_CLSIZE_SHIFT (11) /* Bits 11-13: Cache Line Size */ #define CMCC_TYPE_CLSIZE_MASK (7 << CMCC_TYPE_CLSIZE_SHIFT) # define CMCC_TYPE_CLSIZE_4B (0 << CMCC_TYPE_CLSIZE_SHIFT) /* 4 Bytes */ @@ -150,16 +154,16 @@ /* Cache Monitor Status Register -- 32-bit event count */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_dacc.h b/arch/arm/src/sam34/hardware/sam_dacc.h index 96a445a86b0..cdd84768e36 100644 --- a/arch/arm/src/sam34/hardware/sam_dacc.h +++ b/arch/arm/src/sam34/hardware/sam_dacc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_dacc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* DACC register offsets *****************************************************************/ +/* DACC register offsets ****************************************************/ #define SAM_DACC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_DACC_MR_OFFSET 0x0004 /* Mode Register */ @@ -50,7 +50,7 @@ #define SAM_DACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode register */ #define SAM_DACC_WPSR_OFFSET 0x00e8 /* Write Protect Status register */ -/* DACC register addresses **************************************************************/ +/* DACC register addresses **************************************************/ #define SAM_DACC_CR (SAM_DACC_BASE+SAM_DACC_CR_OFFSET) #define SAM_DACC_MR (SAM_DACC_BASE+SAM_DACC_MR_OFFSET) @@ -66,7 +66,7 @@ #define SAM_DACC_WPMR (SAM_DACC_BASE+SAM_DACC_WPMR_OFFSET) #define SAM_DACC_WPSR (SAM_DACC_BASE+SAM_DACC_WPSR_OFFSET) -/* DACC register bit definitions ********************************************************/ +/* DACC register bit definitions ********************************************/ /* Control Register */ @@ -83,6 +83,7 @@ # define DACC_MR_TRGSEL_TIO2 (3 << DACC_MR_TRGSEL_SHIFT) /* TIO Output of the TC Channel 2 */ # define DACC_MR_TRGSEL_PWM0 (4 << DACC_MR_TRGSEL_SHIFT) /* PWM Event Line 0 */ # define DACC_MR_TRGSEL_PWM1 (5 << DACC_MR_TRGSEL_SHIFT) /* PWM Event Line 1 */ + #define DACC_MR_WORD (1 << 4) /* Bit 4: Word Transfer */ #define DACC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ #define DACC_MR_FASTWKUP (1 << 6) /* Bit 6: Fast Wake up Mode */ @@ -92,13 +93,17 @@ #define DACC_MR_USERSEL_MASK (3 << DACC_MR_USERSEL_SHIFT) # define DACC_MR_USERSEL_CHAN0 (0 << DACC_MR_USERSEL_SHIFT) /* Channel 0 */ # define DACC_MR_USERSEL_CHAN1 (1 << DACC_MR_USERSEL_SHIFT) /* Channel 1 */ + #define DACC_MR_TAG (1 << 20) /* Bit 20: Tag Selection Mode */ #define DACC_MR_MAXS (1 << 21) /* Bit 21: Max Speed Mode */ #define DACC_MR_CLKDIV (1 << 22) /* Bit 22: Clock Divider */ + # define DACC_MR_CLKDIV_2 (0) /* DAC clock is MCK divided by 2 */ # define DACC_MR_CLKDIV_4 DACC_MR_CLKDIV /* DAC clock is MCK divided by 4 */ + #define DACC_MR_STARTUP_SHIFT (24) /* Bits 24-29: Startup Time Select */ #define DACC_MR_STARTUP_MASK (63 << DACC_MR_STARTUP_SHIFT) + # define DACC_MR_STARTUP_0 (0 << DACC_MR_STARTUP_SHIFT) /* 0 periods of DACClock */ # define DACC_MR_STARTUP_8 (1 << DACC_MR_STARTUP_SHIFT) /* 8 periods of DACClock */ # define DACC_MR_STARTUP_16 (2 << DACC_MR_STARTUP_SHIFT) /* 16 periods of DACClock */ @@ -171,7 +176,9 @@ /* Conversion Data Register -- 32-bit data */ -/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */ +/* Interrupt Enable, Interrupt Disable, Interrupt Mask, + * and Interrupt Status Register + */ #define DACC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready Interrupt */ #define DACC_INT_EOC (1 << 1) /* Bit 1: End of Conversion Interrupt Flag */ @@ -201,16 +208,16 @@ #define DACC_WPSR_WPROTADDR_SHIFT (8) /* Bits 8-15: Write protection error address */ #define DACC_WPSR_WPROTADDR_MASK (0xff << DACC_WPSR_WPROTADDR_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_dmac.h b/arch/arm/src/sam34/hardware/sam_dmac.h index 5661acaee62..1e279d9dceb 100644 --- a/arch/arm/src/sam34/hardware/sam_dmac.h +++ b/arch/arm/src/sam34/hardware/sam_dmac.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* DMAC register offsets ****************************************************************/ +/* DMAC register offsets ****************************************************/ /* Global Registers */ @@ -52,6 +52,7 @@ #define SAM_DMAC_CHDR_OFFSET 0x002c /* DMAC Channel Handler Disable Register */ #define SAM_DMAC_CHSR_OFFSET 0x0030 /* DMAC Channel Handler Status Register */ /* 0x034-0x38: Reserved */ + /* DMA channel registers */ #define SAM_DMACHAN_OFFSET(n) (0x003c+((n)*0x28)) @@ -68,7 +69,7 @@ #define SAM_DMACHAN_CTRLA_OFFSET 0x000c /* DMAC Channel Control A Register */ #define SAM_DMACHAN_CTRLB_OFFSET 0x0010 /* DMAC Channel Control B Register */ #define SAM_DMACHAN_CFG_OFFSET 0x0014 /* DMAC Channel Configuration Register */ - /* 0x18-0x24: Reserved */ + /* 0x18-0x24: Reserved */ /* More Global Registers */ @@ -77,7 +78,7 @@ # define SAM_DMAC_WPSR_OFFSET 0x01e8 /* DMAC Write Protect Status Register DMAC_WPSR */ #endif -/* DMAC register addresses **************************************************************/ +/* DMAC register addresses **************************************************/ /* Global Registers */ @@ -146,7 +147,7 @@ # define SAM_DMAC_WPSR (SAM_DMAC_BASE+SAM_DMAC_WPSR_OFFSET) #endif -/* DMAC register bit definitions ********************************************************/ +/* DMAC register bit definitions ********************************************/ /* Global Registers */ @@ -236,10 +237,14 @@ # define DMAC_LAST_DLAST2 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST2_SHIFT) # define DMAC_LAST_DLAST3 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST3_SHIFT) -/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register, - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register, - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common +/* DMAC Error, Buffer Transfer and Chained Buffer + * Transfer Interrupt Enable Register, + * DMAC Error, Buffer Transfer and Chained Buffer + * Transfer Interrupt Disable Register, + * DMAC Error, Buffer Transfer and Chained Buffer + * Transfer Interrupt Mask Register, and + * DMAC Error, Buffer Transfer and Chained Buffer + * Transfer Status Register common * bit field definitions */ @@ -344,10 +349,22 @@ # define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3)) /* DMA channel registers */ -/* DMAC Channel n [n = 0..3] Source Address Register -- 32-bit address*/ -/* DMAC Channel n [n = 0..3] Destination Address Register -- 32-bit address*/ -/* DMAC Channel n [n = 0..3] Descriptor Address Register -- 32-bit address*/ -/* DMAC Channel n [n = 0..3] Control A Register */ + +/* DMAC Channel n [n = 0..3] + * Source Address Register -- 32-bit address + */ + +/* DMAC Channel n [n = 0..3] + * Destination Address Register -- 32-bit address + */ + +/* DMAC Channel n [n = 0..3] + * Descriptor Address Register -- 32-bit address + */ + +/* DMAC Channel n [n = 0..3] + * Control A Register + */ #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ defined(CONFIG_ARCH_CHIP_SAM3A) @@ -395,6 +412,7 @@ # define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */ # define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */ # define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */ + #define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */ #define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT) # define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */ @@ -402,6 +420,7 @@ # define DMACHAN_CTRLB_SRCINCR_DECR (1 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Decrementing address */ # endif # define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */ + #define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */ #define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT) # define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */ @@ -409,6 +428,7 @@ # define DMACHAN_CTRLB_DSTINCR_DECR (1 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Decrementing address */ # endif # define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */ + #define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */ /* DMAC Channel n [n = 0..3] Configuration Register */ @@ -453,7 +473,7 @@ # define DMAC_WPSR_WPVSRC_MASK (0xffff << DMAC_WPSR_WPVSRC_SHIFT) #endif -/* DMA Hardware interface numbers *******************************************************/ +/* DMA Hardware interface numbers *******************************************/ #if defined(CONFIG_ARCH_CHIP_SAM3U) @@ -496,9 +516,9 @@ #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ /* DMA multi buffer transfer link list entry structure */ @@ -511,12 +531,12 @@ struct dma_linklist_s uint32_t next; /* Next descriptor address */ }; -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_eefc.h b/arch/arm/src/sam34/hardware/sam_eefc.h index b6064501e2a..ed879387a43 100644 --- a/arch/arm/src/sam34/hardware/sam_eefc.h +++ b/arch/arm/src/sam34/hardware/sam_eefc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_eefc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,32 +16,32 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* EEFC register offsets ****************************************************************/ +/* EEFC register offsets ****************************************************/ #define SAM_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */ #define SAM_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */ #define SAM_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */ #define SAM_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */ -/* EEFC register addresses **************************************************************/ +/* EEFC register addresses **************************************************/ #define SAM_EEFC_FMR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FMR_OFFSET) #define SAM_EEFC_FCR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FCR_OFFSET) @@ -60,7 +60,8 @@ # define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET) #endif -/* EEFC register bit definitions ********************************************************/ +/* EEFC register bit definitions ********************************************/ + /* EEFC Flash Mode Register */ #define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ @@ -135,16 +136,16 @@ /* EEFC Flash Result Register -- 32-bit value */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_emac.h b/arch/arm/src/sam34/hardware/sam_emac.h index 32fa77381ab..72e5c7b9b1d 100644 --- a/arch/arm/src/sam34/hardware/sam_emac.h +++ b/arch/arm/src/sam34/hardware/sam_emac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_emac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* EMAC Register Offsets ************************************************************/ + ****************************************************************************/ + +/* EMAC Register Offsets ****************************************************/ #define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */ #define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */ @@ -71,6 +72,7 @@ #define SAM_EMAC_SAMB1_OFFSET 0x00c8 /* Specific Address 1 Mask Bottom [31:0] Register */ #define SAM_EMAC_SAMT1_OFFSET 0x00cc /* Specific Address 1 Mask Top [47:32] Register */ /* 0x00fc: Reserved */ + /* Statistics registers */ #define SAM_EMAC_OTLO_OFFSET 0x0100 /* Octets Transmitted [31:0] Register */ @@ -137,7 +139,7 @@ #define SAM_EMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */ /* 0x0280-0x0298: Reserved */ -/* EMAC Register Addresses **********************************************************/ +/* EMAC Register Addresses **************************************************/ #define SAM_EMAC_NCR (SAM_EMAC_BASE+SAM_EMAC_NCR_OFFSET) #define SAM_EMAC_NCFGR (SAM_EMAC_BASE+SAM_EMAC_NCFGR_OFFSET) @@ -240,7 +242,7 @@ #define SAM_EMAC_PEFRS (SAM_EMAC_BASE+SAM_EMAC_PEFRS_OFFSET) #define SAM_EMAC_PEFRN (SAM_EMAC_BASE+SAM_EMAC_PEFRN_OFFSET) -/* EMAC Register Bit Definitions ****************************************************/ +/* EMAC Register Bit Definitions ********************************************/ /* Network Control Register */ @@ -282,6 +284,7 @@ # define EMAC_NCFGR_RXBUFO_1 (1 << EMAC_NCFGR_RXBUFO_SHIFT) /* One-byte offset from RX buffer start */ # define EMAC_NCFGR_RXBUFO_2 (2 << EMAC_NCFGR_RXBUFO_SHIFT) /* Two-byte offset from RX buffer start */ # define EMAC_NCFGR_RXBUFO_3 (3 << EMAC_NCFGR_RXBUFO_SHIFT) /* Three-byte offset fromRX buffer start */ + #define EMAC_NCFGR_LFERD (1 << 16) /* Bit 16: Length Field Error Frame Discard */ #define EMAC_NCFGR_RFCS (1 << 17) /* Bit 17: Remove FCS */ #define EMAC_NCFGR_CLK_SHIFT (18) /* Bits 18-20: MDC clock divider */ @@ -292,9 +295,11 @@ # define EMAC_NCFGR_CLK_DIV48 (3 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */ # define EMAC_NCFGR_CLK_DIV64 (4 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */ # define EMAC_NCFGR_CLK_DIV96 (5 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */ + #define EMAC_NCFGR_DBW_SHIFT (21) /* Bit 21-22: Data Bus Width */ #define EMAC_NCFGR_DBW_MASK (3 << EMAC_NCFGR_DBW_SHIFT) # define EMAC_NCFGR_DBW_ZERO (0 << EMAC_NCFGR_DBW_SHIFT) /* Must be zero */ + #define EMAC_NCFGR_DCPF (1 << 23) /* Bit 23: Disable Copy of Pause Frames */ #define EMAC_NCFGR_RXCOEN (1 << 24) /* Bit 24: Receive Checksum Offload Enable */ #define EMAC_NCFGR_EFRHD (1 << 25) /* Bit 25: Enable Frames Received in Half Duplex */ @@ -316,10 +321,11 @@ #define EMAC_DCFGR_FBLDO_SHIFT (0) /* Bits 0-4: Fixed Burst Length for DMA Data Operations */ #define EMAC_DCFGR_FBLDO_MASK (31 << EMAC_DCFGR_FBLDO_SHIFT) -# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */ -# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */ -# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */ +# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */ +# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */ +# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */ # define EMAC_DCFGR_FBLDO_INCR16 (16 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR16 AHB bursts */ + #define EMAC_DCFGR_ESMA (1 << 6) /* Bit 6: Endian Swap Mode Enable for Management Descriptor Accesses */ #define EMAC_DCFGR_ESPA (1 << 7) /* Bit 7: Endian Swap Mode Enable for Packet Data Accesses */ #define EMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */ @@ -352,7 +358,9 @@ #define EMAC_RSR_RXOVR (1 << 2) /* Bit 2: Receive Overrun */ #define EMAC_RSR_HNO (1 << 3) /* Bit 3: HRESP Not OK */ -/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) */ +/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), + * Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) + */ #define EMAC_INT_MFS (1 << 0) /* Bit 0: Management Frame Sent */ #define EMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */ @@ -412,24 +420,29 @@ #define EMAC_TPQ_MASK (0x0000ffff) /* Bits 0-15: Transmit Pause Quantum */ /* Hash Register Bottom [31:0] Register (LS 32-bit hash address) */ + /* Hash Register Top [63:32] Register (MS 32-bit hash address) */ /* Specific Address 1 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 1 Top [47:32] Register */ #define EMAC_SAT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 2 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 2 Top [47:32] Register */ #define EMAC_SAT2_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 3 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 3 Top [47:32] Register */ #define EMAC_SAT3_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 4 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 4 Top [47:32] Register */ #define EMAC_SAT4_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ @@ -461,6 +474,7 @@ #define EMAC_TPFCP_PQ_MASK (0xff << EMAC_TPFCP_PQ_SHIFT) /* Specific Address 1 Mask Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 1 Mask Top [47:32] Register (MS 16-bit address) */ #define EMAC_SAMT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of Specific Address 1 Mask */ @@ -517,11 +531,13 @@ /* PTP/1588 Timer Registers */ /* 1588 Timer Sync Strobe Seconds Register (32-bit timer value) */ + /* 1588 Timer Sync Strobe Nanoseconds Register (30-bit timer value) */ #define EMAC_TSSN_MASK (0x3fffffff) /* Bit 0-29: Value Timer Nanoseconds Register Capture */ /* 1588 Timer Seconds Register (32-bit timer value) */ + /* 1588 Timer Nanoseconds Register (30-bit timer value) */ #define EMAC_TN_MASK (0x3fffffff) /* Bit 0-29: Timer Count in Nanoseconds */ @@ -546,31 +562,35 @@ # define EMAC_TI_NIT(n) ((uint32_t)(n) << EMAC_TI_NIT_SHIFT) /* PTP Event Frame Transmitted Seconds (32-bit timer value) */ + /* PTP Event Frame Transmitted Nanoseconds (30-bit timer value) */ #define EMAC_EFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Event Frame Received Seconds (32-bit timer value) */ + /* PTP Event Frame Received Nanoseconds (30-bit timer value) */ #define EMAC_EFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Peer Event Frame Transmitted Seconds (32-bit timer value) */ + /* PTP Peer Event Frame Transmitted Nanoseconds (30-bit timer value) */ #define EMAC_PEFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Peer Event Frame Received Seconds (32-bit timer value) */ + /* PTP Peer Event Frame Received Nanoseconds (30-bit timer value) */ #define EMAC_PEFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ -/* Descriptors **********************************************************************/ +/* Descriptors **************************************************************/ /* Receive buffer descriptor: Address word */ -#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */ -#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ +#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */ +#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ #define EMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */ /* Receive buffer descriptor: Control word */ @@ -587,20 +607,22 @@ #define EMACRXD_STA_VLPRIO_MASK (7 << EMACRXD_STA_VLANPRIO_SHIFT) #define EMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */ #define EMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */ -#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */ +#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */ #define EMACRXD_STA_TYPEID_MASK (3 << EMACRXD_STA_TYPEID_SHIFT) # define EMACRXD_STA_TYPEID1 (0 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 1 match */ # define EMACRXD_STA_TYPEID2 (1 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 2 match */ # define EMACRXD_STA_TYPEID3 (2 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 3 match */ # define EMACRXD_STA_TYPEID4 (3 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 4 match */ + #define EMACRXD_STA_TYPEIDMATCH (1 << 24) /* Bit 24: Type ID register match found */ #define EMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */ -#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */ +#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */ #define EMACRXD_STA_ADDR_MASK (3 << EMACRXD_STA_ADDR_SHIFT) # define EMACRXD_STA_ADDR1 (0 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */ # define EMACRXD_STA_ADDR2 (1 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ # define EMACRXD_STA_ADDR3 (2 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ # define EMACRXD_STA_ADDR4 (3 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ + #define EMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific address match found */ /* Bit 28: Reserved */ #define EMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */ @@ -608,6 +630,7 @@ #define EMACRXD_STA_BCAST (1 << 31) /* Bit 31: Global all ones broadcast address detected */ /* Transmit buffer descriptor: Address word (un-aligned, 32-bit address */ + /* Transmit buffer descriptor: Control word */ #define EMACTXD_STA_BUFLEN_SHIFT (0) /* Bits 0-13: Length of buffer */ @@ -626,6 +649,7 @@ # define EMACTXD_STA_CHKERR_BADFRAG (5 << EMACTXD_STA_CHKERR_SHIFT) /* Unsupported fragmentation */ # define EMACTXD_STA_CHKERR_PKTTYPE (6 << EMACTXD_STA_CHKERR_SHIFT) /* Not TCP or UDP */ # define EMACTXD_STA_CHKERR_EPKT (7 << EMACTXD_STA_CHKERR_SHIFT) /* Premature end of packet */ + /* Bits 23-25: Reserved */ #define EMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision, transmit error detected */ #define EMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit frame corruption due to AHB error */ @@ -634,9 +658,10 @@ #define EMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */ #define EMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the EMAC to read from buffer */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* Receive buffer descriptor */ struct emac_rxdesc_s diff --git a/arch/arm/src/sam34/hardware/sam_gpbr.h b/arch/arm/src/sam34/hardware/sam_gpbr.h index d02c9bd60cf..05e98ad5688 100644 --- a/arch/arm/src/sam34/hardware/sam_gpbr.h +++ b/arch/arm/src/sam34/hardware/sam_gpbr.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_gpbr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* GPBR register offsets ****************************************************************/ +/* GPBR register offsets ****************************************************/ #define SAM_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */ #define SAM_GPBR0_OFFSET 0x00 @@ -61,7 +61,7 @@ # define SAM_GPBR19_OFFSET 0x4c #endif -/* GPBR register addresses **************************************************************/ +/* GPBR register addresses **************************************************/ #define SAM_GPBR(n)) (SAM_GPBR_BASE+SAM_GPBR_OFFSET(n)) #define SAM_GPBR0 (SAM_GPBR_BASE+SAM_GPBR0_OFFSET) @@ -88,20 +88,20 @@ # define SAM_GPBR19 (SAM_GPBR_BASE+SAM_GPBR19_OFFSET) #endif -/* GPBR register bit definitions ********************************************************/ +/* GPBR register bit definitions ********************************************/ /* All 32-bit values */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H */ diff --git a/arch/arm/src/sam34/hardware/sam_hsmci.h b/arch/arm/src/sam34/hardware/sam_hsmci.h index 0bef7ce8943..006446ace9c 100644 --- a/arch/arm/src/sam34/hardware/sam_hsmci.h +++ b/arch/arm/src/sam34/hardware/sam_hsmci.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_hsmci.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include @@ -31,11 +31,11 @@ #include "hardware/sam_pdc.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* HSMCI register offsets ***************************************************************/ +/* HSMCI register offsets ***************************************************/ #define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */ @@ -69,7 +69,7 @@ /* 0x0100-0x0124: Reserved for PCD registers */ #define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */ -/* HSMCI register addresses *************************************************************/ +/* HSMCI register addresses *************************************************/ #define SAM_HSMCI_CR (SAM_HSMCI_BASE+SAM_HSMCI_CR_OFFSET) #define SAM_HSMCI_MR (SAM_HSMCI_BASE+SAM_HSMCI_MR_OFFSET) @@ -112,7 +112,7 @@ # define SAM_HSMCI_PDC_PTSR (SAM_HSMCI_BASE+SAM_PDC_PTSR_OFFSET) #endif -/* HSMCI register bit definitions *******************************************************/ +/* HSMCI register bit definitions *******************************************/ /* HSMCI Control Register */ @@ -191,6 +191,7 @@ # define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */ # define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */ # define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */ + #define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */ #define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT) # define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */ @@ -201,6 +202,7 @@ # define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */ # define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */ # define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */ + #define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */ #define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */ #define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */ @@ -208,6 +210,7 @@ # define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */ # define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */ # define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */ + #define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */ # define HSMCI_CMDR_TRDIR_WRITE (0 << 18) # define HSMCI_CMDR_TRDIR_READ (1 << 18) @@ -218,11 +221,13 @@ # define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */ # define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */ # define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */ + #define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */ #define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT) # define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */ # define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ # define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ + #define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ #define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */ @@ -252,11 +257,14 @@ # define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) /* HSMCI Response Registers (32-bit data) */ + /* HSMCI Receive Data Registers (32-bit data) */ + /* HSMCI Transmit Data Registers (32-bit data) */ -/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable - * Register, and HSMCI Interrupt Mask Register common bit-field definitions +/* HSMCI Status Register, HSMCI Interrupt Enable Register, + * HSMCI Interrupt Disable Register, and HSMCI Interrupt Mask Register + * common bit-field definitions */ #define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */ @@ -336,16 +344,16 @@ #define HSMCI_WPSR_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ #define HSMCI_WPSR_VSRC_MASK (0xffff << HSMCI_WPSR_VSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H */ diff --git a/arch/arm/src/sam34/hardware/sam_matrix.h b/arch/arm/src/sam34/hardware/sam_matrix.h index 6cde8c1daa6..66058b401e0 100644 --- a/arch/arm/src/sam34/hardware/sam_matrix.h +++ b/arch/arm/src/sam34/hardware/sam_matrix.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_matrix.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* MATRIX register offsets **************************************************************/ +/* MATRIX register offsets **************************************************/ #define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2) #define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ @@ -110,7 +110,7 @@ #define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ /* 0x0110 - 0x01fc: Reserved */ -/* MATRIX register addresses ************************************************************/ +/* MATRIX register addresses ************************************************/ #define SAM_MATRIX_MCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n)) #define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET) @@ -183,7 +183,7 @@ #define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET) #define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET) -/* MATRIX register bit definitions ******************************************************/ +/* MATRIX register bit definitions ******************************************/ /* Master Configuration Registers */ @@ -342,12 +342,12 @@ #define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H */ diff --git a/arch/arm/src/sam34/hardware/sam_memorymap.h b/arch/arm/src/sam34/hardware/sam_memorymap.h index a6f39fe3d8f..05f9e4be325 100644 --- a/arch/arm/src/sam34/hardware/sam_memorymap.h +++ b/arch/arm/src/sam34/hardware/sam_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include diff --git a/arch/arm/src/sam34/hardware/sam_pdc.h b/arch/arm/src/sam34/hardware/sam_pdc.h index 60de492b75e..a76cb96c286 100644 --- a/arch/arm/src/sam34/hardware/sam_pdc.h +++ b/arch/arm/src/sam34/hardware/sam_pdc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_pdc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* PDC register offsets *****************************************************************/ +/* PDC register offsets *****************************************************/ #define SAM_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */ #define SAM_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */ @@ -47,31 +47,37 @@ #define SAM_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */ #define SAM_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */ -/* PDC register addresses ***************************************************************/ +/* PDC register addresses ***************************************************/ -/* These 10 registers are mapped in the peripheral memory space at the same offset. */ +/* These 10 registers are mapped in the peripheral memory space at the same + * offset. + */ -/* PDC register bit definitions *********************************************************/ +/* PDC register bit definitions *********************************************/ /* Receive Pointer Register -- 32-bit address value */ + /* Receive Counter Register -- 16-bit counter value */ #define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */ #define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT) /* Transmit Pointer Register -- 32-bit address value */ + /* Transmit Counter Register -- 16-bit counter value */ #define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */ #define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT) /* Receive Next Pointer Register -- 32-bit address value */ + /* Receive Next Counter Register -- 16-bit counter value */ #define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */ #define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT) /* Transmit Next Pointer Register -- 32-bit address value */ + /* Transmit Next Counter Register -- 16-bit counter value */ #define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */ @@ -89,16 +95,16 @@ #define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ #define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_pinmap.h b/arch/arm/src/sam34/hardware/sam_pinmap.h index 3b795eb724d..ebe448a85aa 100644 --- a/arch/arm/src/sam34/hardware/sam_pinmap.h +++ b/arch/arm/src/sam34/hardware/sam_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" diff --git a/arch/arm/src/sam34/hardware/sam_pmc.h b/arch/arm/src/sam34/hardware/sam_pmc.h index e93537210d7..2509d9daeac 100644 --- a/arch/arm/src/sam34/hardware/sam_pmc.h +++ b/arch/arm/src/sam34/hardware/sam_pmc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_pmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* PMC register offsets *********************************************************************/ +/* PMC register offsets *****************************************************/ #define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ #define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ @@ -56,7 +56,7 @@ defined(CONFIG_ARCH_CHIP_SAM3A) # define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ #endif - /* 0x001c: Reserved (SAM4S)*/ + /* 0x001c: Reserved (SAM4S) */ #define SAM_PMC_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ #define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ #define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ @@ -64,7 +64,7 @@ #if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S) # define SAM_PMC_CKGR_PLLBR_OFFSET 0x002c /* PLLB Register */ #endif - /* 0x002c: Reserved (SAM3U)*/ + /* 0x002c: Reserved (SAM3U) */ #define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ #if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \ @@ -111,7 +111,7 @@ # define SAM_PMC_PMMR_OFFSET 0x0130 /* PLL Maximum Multiplier Value Register */ #endif -/* PMC register addresses *******************************************************************/ +/* PMC register addresses ***************************************************/ #define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) #define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) @@ -182,10 +182,10 @@ # define SAM_PMC_PMMR (SAM_PMC_BASE+SAM_PMC_PMMR_OFFSET) #endif -/* PMC register bit definitions *************************************************************/ +/* PMC register bit definitions *********************************************/ -/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System - * Clock Status Register common bit-field definitions +/* PMC System Clock Enable Register, PMC System Clock Disable Register, + * and PMC System Clock Status Register common bit-field definitions */ #if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM4S) @@ -207,8 +207,9 @@ # define PMC_CPKEY (0xa << 20) #endif -/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC - * Peripheral Clock Status Register common bit-field definitions. +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable + * Register, and PMC Peripheral Clock Status Register common bit-field + * definitions. */ #define PMC_PIDL(n) (1 << (n)) @@ -267,6 +268,7 @@ # define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */ # define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */ # define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */ + #define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */ #define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT) # define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT) @@ -317,6 +319,7 @@ # define PMC_CKGR_PLLBR_DIV_ZERO (0 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is 0 */ # define PMC_CKGR_PLLBR_DIV_BYPASS (1 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ # define PMC_CKGR_PLLBR_DIV(n) ((n) << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ + # define PMC_CKGR_PLLBR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ # define PMC_CKGR_PLLBR_COUNT_MASK (63 << PMC_CKGR_PLLBR_COUNT_SHIFT) # define PMC_CKGR_PLLBR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ @@ -421,8 +424,8 @@ # define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ # define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ -/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, - * and PMC Interrupt Mask Register common bit-field definitions +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status + * Register, and PMC Interrupt Mask Register common bit-field definitions */ #define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ @@ -450,8 +453,8 @@ #define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ #define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ -/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field - * definitions +/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register + * common bit-field definitions */ #define PMC_FSTI(n) (1 << (n)) @@ -491,6 +494,7 @@ /* Fast Startup Polarity Register */ #define PMC_FSTP(n) (1 << (n)) /* Fast Startup Input Polarity n, n=0..15 */ + # define PMC_FSTP0 (1 << 0) /* Bit 0: Fast Startup Input Polarity 0 */ # define PMC_FSTP1 (1 << 1) /* Bit 1: Fast Startup Input Polarity 1 */ # define PMC_FSTP2 (1 << 2) /* Bit 2: Fast Startup Input Polarity 2 */ @@ -526,7 +530,9 @@ #define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) /* Peripheral Clock Enable Register 1 */ + /* Peripheral Clock Disable Register 1 */ + /* Peripheral Clock Status Register 1 */ #if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ @@ -567,6 +573,7 @@ # define PMC_PCR_DIV1 (0 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */ # define PMC_PCR_DIV2 (1 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */ # define PMC_PCR_DIV4 (2 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */ + # define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */ #endif @@ -593,16 +600,16 @@ # define PMC_PMMR_MASK (0x7ff) /* Bits 0-10: PLLA Maximum Allowed Multiplier */ #endif -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_pwm.h b/arch/arm/src/sam34/hardware/sam_pwm.h index 5fe5850353d..a3a7e6f3189 100644 --- a/arch/arm/src/sam34/hardware/sam_pwm.h +++ b/arch/arm/src/sam34/hardware/sam_pwm.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_pwm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* PWM register offsets *****************************************************************/ +/* PWM register offsets *****************************************************/ #define SAM_PWM_CLK_OFFSET 0x000 /* PWM Clock Register */ #define SAM_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */ @@ -91,6 +91,7 @@ #define SAM_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */ /* 0x100-0x128: Reserved for PDC registers */ /* 0x12c: Reserved */ + /* PWM Comparison Registers */ #define SAM_PWMCMP_OFFSET(n) (0x130+((n)<<4)) @@ -138,7 +139,8 @@ #define SAM_PWMCMP7_VUPD_OFFSET 0x1a4 /* PWM Comparison 7 Value Update Register */ #define SAM_PWMCMP7_M_OFFSET 0x1a8 /* PWM Comparison 7 Mode Register */ #define SAM_PWMCMP7_MUPD_OFFSET 0x1ac /* PWM Comparison 7 Mode Update Register */ - /* 0x1b0-0x1fc: Reserved */ + /* 0x1b0-0x1fc: Reserved */ + /* PWM Channel Registers */ #define SAM_PWMCH_OFFSET(n) (0x200+((n)<< 5)) @@ -210,7 +212,7 @@ # define SAM_PWMCH3_CAEUPD_OFFSET 0x0468 /* PWM Channel 3 Additional Edge Update Register */ #endif -/* PWM register addresses ***************************************************************/ +/* PWM register addresses ***************************************************/ #define SAM_PWM_CLK (SAM_PWM_BASE+SAM_PWM_CLK_OFFSET) #define SAM_PWM_ENA (SAM_PWM_BASE+SAM_PWM_ENA_OFFSET) @@ -388,7 +390,7 @@ # define SAM_PWMCH3_CAEUPD (SAM_PWMCH3_BASE2+SAM_PWMCH0_CAEUPD_OFFSET) #endif -/* PWM register bit definitions *********************************************************/ +/* PWM register bit definitions *********************************************/ /* PWM Clock Register */ @@ -410,6 +412,7 @@ # define PWM_CLK_PREA_MCKDIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */ # define PWM_CLK_PREA_MCKDIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */ # define PWM_CLK_PREA_MCKDIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */ + #define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */ #define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT) # define PWM_CLK_DIVB_OFF (0 << PWM_CLK_DIVB_SHIFT) @@ -429,7 +432,9 @@ # define PWM_CLK_PREB_MCKDIV512 (9 << PWM_CLK_PREB_SHIFT) /* MCK/512 */ # define PWM_CLK_PREB_MCKDIV1024 (10 << PWM_CLK_PREB_SHIFT) /* MCK/1024 */ -/* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */ +/* PWM Enable Register, PWM Disable Register, and + * PWM Status Register common bit-field definitions + */ #define SAM_ENAB_CHID(n) (1 << ((n)) # define SAM_ENAB_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ @@ -437,8 +442,9 @@ # define SAM_ENAB_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ # define SAM_ENAB_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ -/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt - * Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions +/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, + * PWM Interrupt Mask Register 1, and PWM Interrupt Status Register 1 + * common bit definitions */ #define SAM_INT_CHID(n) (1 << (n)) @@ -464,6 +470,7 @@ # define PWM_SCM_UPDM_MANMAN (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */ # define PWM_SCM_UPDM_MANAUTO (1 << PWM_SCM_UPDM_SHIFT) /* Manual write/automatic update */ # define PWM_SCM_UPDM_AUTOAUTO (2 << PWM_SCM_UPDM_SHIFT) /* Auto write/automatic update */ + #define PWM_SCM_PTRM (1 << 20) /* Bit 20: PDC Transfer Request Mode */ #define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: PDC Transfer Request Comparison Selection */ #define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT) @@ -488,7 +495,10 @@ #define PWM_SCUPUPD_MASK (15 << PWM_SCUPUPD_SHIFT) # define PWM_SCUPUPD(n) ((uint32_t)(n) << PWM_SCUPUPD_SHIFT) -/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */ +/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, + * PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 + * common bit-field definitions + */ #define SAM_INT_WRDY (1 << 0) /* Bit 0: Write Ready Update Interrupt */ #define SAM_INT_ENDTX (1 << 1) /* Bit 1: PDC End of TX Buffer Interrupt */ @@ -513,10 +523,10 @@ # define SAM_INT_CMPU6 (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */ # define SAM_INT_CMPU7 (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */ -/* PWM Output Override Value Register, PWM Output Selection Register, PWM Output - * Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection - * Set Update Register, and PWM Output Selection Clear Update Register common bit-field - * definitions +/* PWM Output Override Value Register, PWM Output Selection Register, + * PWM Output Selection Set Register, PWM Output Selection Clear Register, + * PWM Output Selection Set Update Register, and PWM Output Selection Clear + * Update Register common bit-field definitions */ #define PWM_OUT_OH(n) (1 << (n)) @@ -720,13 +730,17 @@ #define PWM_WPSR_WPVSRC_SHIFT (16) /* Bits 16-31: Write Protect Violation Source */ #define PWM_WPSR_WPVSRC_MASK (0xffff << PWM_WPSR_WPVSRC_SHIFT) -/* PWM Comparison x Value Register and PWM Comparison x Value Update Register */ +/* PWM Comparison x Value Register and + * PWM Comparison x Value Update Register + */ #define PWMCMP_CV_SHIFT (0) /* Bits 0-23: Comparison x Value */ #define PWMCMP_CV_MASK (0x00ffffff << PWMCMP_CV_SHIFT) #define PWMCMP_CVM (1 << 24) /* Bit 24: Comparison x Value Mode */ -/* PWM Comparison x Mode Register and PWM Comparison x Mode Update Register */ +/* PWM Comparison x Mode Register and + * PWM Comparison x Mode Update Register + */ #define PWMCMP_CEN (1 << 0) /* Bit 0: Comparison x Enable */ #define PWMCMP_CTR_SHIFT (4) /* Bits 4-7: Comparison x Trigger */ @@ -760,8 +774,9 @@ # define PWMCH_MR_CPRE_MCKDIV256 (8 << PWMCH_MR_CPRE_SHIFT) /* MCK/256 */ # define PWMCH_MR_CPRE_MCKDIV512 (9 << PWMCH_MR_CPRE_SHIFT) /* MCK/512 */ # define PWMCH_MR_CPRE_MCKDIV1024 (10 << PWMCH_MR_CPRE_SHIFT) /* MCK/1024 */ -# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /*CLKA */ +# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /* CLKA */ # define PWMCH_MR_CPRE_CLKB (12 << PWMCH_MR_CPRE_SHIFT) /* CLKB */ + #define PWMCH_MR_CALG (1 << 8) /* Bit 8: Channel Alignment */ #define PWMCH_MR_CPOL (1 << 9) /* Bit 9: Channel Polarity */ #define PWMCH_MR_CES (1 << 10) /* Bit 10: Counter Event Selection */ @@ -774,12 +789,16 @@ #define PWMCH_MR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */ #define PWMCH_MR_DTLI (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */ -/* PWM Channel Duty Cycle Register and PWM Channel Duty Cycle Update Register common bit-field definitions */ +/* PWM Channel Duty Cycle Register and + * PWM Channel Duty Cycle Update Register common bit-field definitions + */ #define PWMCH_DTY_SHIFT (0) /* Bits 0-23: Channel Duty-Cycle */ #define PWMCH_DTY_MASK (0x00ffffff << PWMCH_DTY_SHIFT) -/* PWM Channel Period Register and PWM Channel Period Update Register common bit-field definitions */ +/* PWM Channel Period Register and + * PWM Channel Period Update Register common bit-field definitions + */ #define PWMCH_PRD_SHIFT (0) /* Bits 0-23: Channel Period */ #define PWMCH_PRD_MASK (0x00ffffff << PWMCH_PRD_SHIFT) @@ -789,7 +808,9 @@ #define PWMCH_CCNT_SHIFT (0) /* Bits 0-23: Channel Counter Register */ #define PWMCH_CCNT_MASK (0x00ffffff << PWMCH_CCNT_SHIFT) -/* PWM Channel Dead Time Register and PWM Channel Dead Time Update Register common bit-field definitions */ +/* PWM Channel Dead Time Register and + * PWM Channel Dead Time Update Register common bit-field definitions + */ #define PWMCH_DTH_SHIFT (0) /* Bits 0-15: Dead-Time Value for PWMHx Output */ #define PWMCH_DTH_MASK (0xffff << PWMCH_DTH_SHIFT) @@ -805,7 +826,9 @@ # define PWMCH_CMUPD_CPOLINVUP (1 << 13) /* Bit 13: Channel Polarity Inversion Update */ #endif -/* PWM Channel Additional Edge Register and PWM Channel Additional Edge Update Register */ +/* PWM Channel Additional Edge Register and + * PWM Channel Additional Edge Update Register + */ #if defined(CONFIG_ARCH_CHIP_SAM4E) # define PWMCH_CAE_ADEDGV_SHIFT (0) /* Bits 0-23: Channel Additional Edge Value */ @@ -818,16 +841,16 @@ # define PWMCH_CAE_ADEDGM_BOTH (2 << PWMCH_CAE_ADEDGM_SHIFT) #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H */ diff --git a/arch/arm/src/sam34/hardware/sam_rstc.h b/arch/arm/src/sam34/hardware/sam_rstc.h index c7769cc237c..63fb5c6d92e 100644 --- a/arch/arm/src/sam34/hardware/sam_rstc.h +++ b/arch/arm/src/sam34/hardware/sam_rstc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_rstc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* RSTC register offsets ****************************************************************/ +/* RSTC register offsets ****************************************************/ #define SAM_RSTC_CR_OFFSET 0x00 /* Control Register */ #define SAM_RSTC_SR_OFFSET 0x04 /* Status Register */ @@ -44,7 +44,7 @@ # define SAM_RSTC_CPMR_OFFSET 0x0c /* Coprocessor Mode Register */ #endif -/* RSTC register addresses **************************************************************/ +/* RSTC register addresses **************************************************/ #define SAM_RSTC_CR (SAM_RSTC_BASE+SAM_RSTC_CR_OFFSET) #define SAM_RSTC_SR (SAM_RSTC_BASE+SAM_RSTC_SR_OFFSET) @@ -54,7 +54,7 @@ # define SAM_RSTC_CPMR (SAM_RSTC_BASE+SAM_RSTC_CPMR_OFFSET) #endif -/* RSTC register bit definitions ********************************************************/ +/* RSTC register bit definitions ********************************************/ /* Reset Controller Control Register */ @@ -75,6 +75,7 @@ # define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */ # define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */ # define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */ + #define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */ #define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */ @@ -92,21 +93,21 @@ #if defined(CONFIG_ARCH_CHIP_SAM4CM) /* Coprocessor Mode Register */ -# define RSTC_CPMR_CPROCEN (1 << 0) /* Coprocessor (second processor) Enable */ -# define RSTC_CPMR_CPEREN (1 << 4) /* Coprocessor Peripheral Enable */ +# define RSTC_CPMR_CPROCEN (1 << 0) /* Coprocessor (second processor) Enable */ +# define RSTC_CPMR_CPEREN (1 << 4) /* Coprocessor Peripheral Enable */ # define RSTC_CPMR_CPKEY (0x5a << 24) /* Key */ #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_rswdt.h b/arch/arm/src/sam34/hardware/sam_rswdt.h index b6c057880dc..644bb185f01 100644 --- a/arch/arm/src/sam34/hardware/sam_rswdt.h +++ b/arch/arm/src/sam34/hardware/sam_rswdt.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_rswdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,38 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* RSWDT register offsets ***************************************************************/ +/* RSWDT register offsets ***************************************************/ #define SAM_RSWDT_CR_OFFSET 0x0000 /* Control Register */ #define SAM_RSWDT_MR_OFFSET 0x0004 /* Mode Register */ #define SAM_RSWDT_SR_OFFSET 0x0008 /* Status Register */ -/* RSWDT register addresses *************************************************************/ +/* RSWDT register addresses *************************************************/ #define SAM_RSWDT_CR (SAM_RSWDT_BASE+SAM_RSWDT_CR_OFFSET) #define SAM_RSWDT_MR (SAM_RSWDT_BASE+SAM_RSWDT_MR_OFFSET) #define SAM_RSWDT_SR (SAM_RSWDT_BASE+SAM_RSWDT_SR_OFFSET) -/* RSWDT register bit definitions *******************************************************/ +/* RSWDT register bit definitions *******************************************/ + /* Watchdog Timer Control Register */ #define RSWDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ @@ -74,16 +75,16 @@ #define RSWDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ #define RSWDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H */ diff --git a/arch/arm/src/sam34/hardware/sam_rtc.h b/arch/arm/src/sam34/hardware/sam_rtc.h index 11f277513b4..42d9444db6d 100644 --- a/arch/arm/src/sam34/hardware/sam_rtc.h +++ b/arch/arm/src/sam34/hardware/sam_rtc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* RTC register offsets *****************************************************************/ +/* RTC register offsets *****************************************************/ #define SAM_RTC_CR_OFFSET 0x00 /* Control Register */ #define SAM_RTC_MR_OFFSET 0x04 /* Mode Register */ @@ -49,7 +49,7 @@ #define SAM_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */ #define SAM_RTC_VER_OFFSET 0x2c /* Valid Entry Register */ -/* RTC register addresses ***************************************************************/ +/* RTC register addresses ***************************************************/ #define SAM_RTC_CR (SAM_RTC_BASE+SAM_RTC_CR_OFFSET) #define SAM_RTC_MR (SAM_RTC_BASE+SAM_RTC_MR_OFFSET) @@ -64,7 +64,7 @@ #define SAM_RTC_IMR (SAM_RTC_BASE+SAM_RTC_IMR_OFFSET) #define SAM_RTC_VER (SAM_RTC_BASE+SAM_RTC_VER_OFFSET) -/* RTC register bit definitions *********************************************************/ +/* RTC register bit definitions *********************************************/ /* RTC Control Register */ @@ -103,6 +103,7 @@ # define RTC_MR_OUT0_ALARM_TOGGLE (5 << RTC_MR_OUT0_SHIFT) /* Output toggles when alarm flag rises */ # define RTC_MR_OUT0_ALARM_FLAG (6 << RTC_MR_OUT0_SHIFT) /* Output is a copy of the alarm flag */ # define RTC_MR_OUT0_PROG_PULSE (7 << RTC_MR_OUT0_SHIFT) /* Duty cycle programmable pulse */ + # define RTC_MR_OUT1_SHIFT (20) /* Bits 20-22: RTCOUT1 Output Source Selection */ # define RTC_MR_OUT1_MASK (7 << RTC_MR_OUT1_SHIFT) # define RTC_MR_OUT1_NOWAVE (0 << RTC_MR_OUT1_SHIFT) /* No waveform, stuck at 0 */ @@ -113,6 +114,7 @@ # define RTC_MR_OUT1_ALARM_TOGGLE (5 << RTC_MR_OUT1_SHIFT) /* Output toggles when alarm flag rises */ # define RTC_MR_OUT1_ALARM_FLAG (6 << RTC_MR_OUT1_SHIFT) /* Output is a copy of the alarm flag */ # define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */ + # define RTC_MR_THIGH_SHIFT (24) /* Bits 24-26: High Duration of the Output Pulse */ # define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT) # define RTC_MR_THIGH_31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */ @@ -123,6 +125,7 @@ # define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */ # define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */ # define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */ + # define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */ # define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT) # define RTC_MR_TPERIOD_1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */ @@ -252,16 +255,16 @@ #define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */ #define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_rtt.h b/arch/arm/src/sam34/hardware/sam_rtt.h index 123e8fd5525..294c82326a8 100644 --- a/arch/arm/src/sam34/hardware/sam_rtt.h +++ b/arch/arm/src/sam34/hardware/sam_rtt.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_rtt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,39 +16,39 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* RTT register offsets *****************************************************************/ +/* RTT register offsets *****************************************************/ #define SAM_RTT_MR_OFFSET 0x00 /* Mode Register */ #define SAM_RTT_AR_OFFSET 0x04 /* Alarm Register */ #define SAM_RTT_VR_OFFSET 0x08 /* Value Register */ #define SAM_RTT_SR_OFFSET 0x0c /* Status Register */ -/* RTT register addresses ***************************************************************/ +/* RTT register addresses ***************************************************/ #define SAM_RTT_MR (SAM_RTT_BASE+SAM_RTT_MR_OFFSET) #define SAM_RTT_AR (SAM_RTT_BASE+SAM_RTT_AR_OFFSET) #define SAM_RTT_VR (SAM_RTT_BASE+SAM_RTT_VR_OFFSET) #define SAM_RTT_SR (SAM_RTT_BASE+SAM_RTT_SR_OFFSET) -/* RTT register bit definitions ********************************************************/ +/* RTT register bit definitions *********************************************/ /* Real-time Timer Mode Register */ @@ -65,6 +65,7 @@ #endif /* Real-time Timer Alarm Register (32-bit alarm value) */ + /* Real-time Timer Value Register (32-bit timer value) */ /* Real-time Timer Status Register */ @@ -72,16 +73,16 @@ #define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */ #define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H */ diff --git a/arch/arm/src/sam34/hardware/sam_smc.h b/arch/arm/src/sam34/hardware/sam_smc.h index 92813bae298..9ebf055bfe6 100644 --- a/arch/arm/src/sam34/hardware/sam_smc.h +++ b/arch/arm/src/sam34/hardware/sam_smc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_smc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SMC register offsets *****************************************************************/ +/* SMC register offsets *****************************************************/ #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ defined(CONFIG_ARCH_CHIP_SAM3A) @@ -107,7 +107,7 @@ # error Unrecognized SAM architecture #endif -/* SMC register addresses ***************************************************************/ +/* SMC register addresses ***************************************************/ #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ defined(CONFIG_ARCH_CHIP_SAM3A) @@ -208,7 +208,7 @@ #define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET) #define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET) -/* SMC register bit definitions *********************************************************/ +/* SMC register bit definitions *********************************************/ /* SMC NFC Configuration Register */ @@ -220,6 +220,7 @@ # define SMC_CFG_PAGESIZE_1056 (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1024 Bytes + 32 bytes spare */ # define SMC_CFG_PAGESIZE_2122 (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2048 Bytes + 64 bytes spare */ # define SMC_CFG_PAGESIZE_4224 (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4096 Bytes + 128 bytes spare */ + # define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ # define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ # define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ @@ -246,8 +247,9 @@ # define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ #endif -/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt - * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions +/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, + * SMC NFC Interrupt Disable Register, and SMC NFC Interrupt Mask Register + * common bit-field definitions */ #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ @@ -314,6 +316,7 @@ # define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 1024 Bytes + 32 bytes spare */ # define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 2048 Bytes + 64 bytes spare */ # define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 4096 Bytes + 128 bytes spare */ + # define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ # define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) # define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ @@ -394,6 +397,7 @@ #endif /* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */ + /* SMC_ECC_PR0 */ #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ @@ -409,7 +413,9 @@ #endif #endif -/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */ +/* Registers for 1 ECC per 512 bytes for a page of + * 512/2048/4096 bytes, 8-bit word + */ #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ defined(CONFIG_ARCH_CHIP_SAM3A) @@ -421,7 +427,9 @@ # define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) #endif -/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */ +/* Registers for 1 ECC per 256 bytes for a page of + * 512/2048/4096 bytes, 8-bit word + */ #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ defined(CONFIG_ARCH_CHIP_SAM3A) @@ -535,7 +543,7 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) || \ defined(CONFIG_ARCH_CHIP_SAM4E) # define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ -# define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ +# define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ # define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) # define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ # define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ @@ -553,6 +561,7 @@ #if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) # define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */ + # define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */ # define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */ # define SMC_OCMS_CS2SE (1 << 18) /* Bit 18: Chip Select 2 Scrambling Enable */ @@ -585,16 +594,16 @@ #define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ #define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_spi.h b/arch/arm/src/sam34/hardware/sam_spi.h index b2456542fcb..e753781fa7f 100644 --- a/arch/arm/src/sam34/hardware/sam_spi.h +++ b/arch/arm/src/sam34/hardware/sam_spi.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General definitions ******************************************************************/ + ****************************************************************************/ + +/* General definitions ******************************************************/ #define SAM_SPI_NCS 4 /* Four chip selects */ -/* SPI register offsets *****************************************************************/ +/* SPI register offsets *****************************************************/ #define SAM_SPI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_SPI_MR_OFFSET 0x0004 /* Mode Register */ @@ -62,7 +63,7 @@ #endif /* 0x100-0x124 Reserved for PDC Registers */ -/* SPI register addresses ***************************************************************/ +/* SPI register addresses ***************************************************/ #define SAM_SPI0_CR (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ #define SAM_SPI0_MR (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ @@ -104,7 +105,7 @@ # define SAM_SPI1_VERSION (SAM_SPI1_BASE+SAM_SPI_VERSION_OFFSET) #endif -/* SPI register bit definitions *********************************************************/ +/* SPI register bit definitions *********************************************/ /* SPI Control Register */ @@ -137,6 +138,7 @@ # define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ # define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ # define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ + #define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */ #define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT) @@ -161,9 +163,11 @@ # define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ # define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ # define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ + #define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ -/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register, +/* SPI Status Register, SPI Interrupt Enable Register, + * SPI Interrupt Disable Register, * and SPI Interrupt Mask Register (common bit fields) */ @@ -193,6 +197,7 @@ #define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */ #define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT) # define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */ + # define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */ # define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */ # define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */ @@ -202,6 +207,7 @@ # define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */ # define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */ # define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */ + #define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */ #define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT) # define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT) @@ -259,16 +265,16 @@ # define SPI_VERSION_MFN_MASK (7 << SPI_VERSION_MFN_SHIFT) #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H */ diff --git a/arch/arm/src/sam34/hardware/sam_ssc.h b/arch/arm/src/sam34/hardware/sam_ssc.h index aa5e102dda6..801651b7d77 100644 --- a/arch/arm/src/sam34/hardware/sam_ssc.h +++ b/arch/arm/src/sam34/hardware/sam_ssc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_ssc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,38 +16,42 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SSC register offsets *****************************************************************/ +/* SSC register offsets *****************************************************/ #define SAM_SSC_CR_OFFSET 0x000 /* Control Register */ #define SAM_SSC_CMR_OFFSET 0x004 /* Clock Mode Register */ - /* 0x008: Reserved */ - /* 0x00c: Reserved */ + + /* 0x008: Reserved */ + + /* 0x00c: Reserved */ #define SAM_SSC_RCMR_OFFSET 0x010 /* Receive Clock Mode Register */ #define SAM_SSC_RFMR_OFFSET 0x014 /* Receive Frame Mode Register */ #define SAM_SSC_TCMR_OFFSET 0x018 /* Transmit Clock Mode Register */ #define SAM_SSC_TFMR_OFFSET 0x01c /* Transmit Frame Mode Register */ #define SAM_SSC_RHR_OFFSET 0x020 /* Receive Holding Register */ #define SAM_SSC_THR_OFFSET 0x024 /* Transmit Holding Register */ - /* 0x028: Reserved */ - /* 0x02c: Reserved */ + + /* 0x028: Reserved */ + + /* 0x02c: Reserved */ #define SAM_SSC_RSHR_OFFSET 0x030 /* Receive Sync. Holding Register */ #define SAM_SSC_TSHR_OFFSET 0x034 /* Transmit Sync. Holding Register */ #define SAM_SSC_RC0R_OFFSET 0x038 /* Receive Compare 0 Register */ @@ -58,10 +62,12 @@ #define SAM_SSC_IMR_OFFSET 0x04c /* Interrupt Mask Register */ #define SAM_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */ #define SAM_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */ - /* 0x050-0x0fc: Reserved */ - /* 0x100-0x124: Reserved for PDC registers */ -/* SSC register addresses ***************************************************************/ + /* 0x050-0x0fc: Reserved */ + + /* 0x100-0x124: Reserved for PDC registers */ + +/* SSC register addresses ***************************************************/ #define SAM_SSC_CR (SAM_SSC_BASE+SAM_SSC_CR_OFFSET) #define SAM_SSC_CMR (SAM_SSC_BASE+SAM_SSC_CMR_OFFSET) @@ -82,7 +88,7 @@ #define SAM_SSC_WPMR (SAM_SSC_BASE+SAM_SSC_WPMR_OFFSET) #define SAM_SSC_WPSR (SAM_SSC_BASE+SAM_SSC_WPSR_OFFSET) -/* SSC register bit definitions *********************************************************/ +/* SSC register bit definitions *********************************************/ /* SSC Control Register */ @@ -104,17 +110,20 @@ # define SSC_RCMR_CKS_DIVIDED (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */ # define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */ # define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ + #define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ #define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) # define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ # define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */ # define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */ + #define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ #define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */ #define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT) # define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */ # define SSC_RCMR_CKG_RFLOW (1 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Low */ # define SSC_RCMR_CKG_RFHIGH (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF High */ + #define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */ #define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT) # define SSC_RCMR_START_CONTINOUS (0 << SSC_RCMR_START_SHIFT) /* Continuous */ @@ -126,6 +135,7 @@ # define SSC_RCMR_START_ANYLEVEL (6 << SSC_RCMR_START_SHIFT) /* Any level change on RF signal */ # define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */ # define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ + #define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */ #define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */ #define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) @@ -150,6 +160,7 @@ # define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ # define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ # define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ + #define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detect */ #define SSC_RFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ #define SSC_RFMR_FSLENEXT_MASK (15 << SSC_RFMR_FSLENEXT_SHIFT) @@ -161,17 +172,20 @@ # define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ # define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */ # define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Pin */ + #define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ #define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) # define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ # define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */ # define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */ + #define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ #define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */ #define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT) # define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */ # define SSC_tCMR_CKG_TFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF Low */ # define SSC_TCMR_CKG_TFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF High */ + #define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */ #define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT) # define SSC_TCMR_START_CONTINOUS (0 << SSC_TCMR_START_SHIFT) /* Continuous */ @@ -182,6 +196,7 @@ # define SSC_TCMR_START_TFRISE (5 << SSC_TCMR_START_SHIFT) /* Rising edge on TF signal */ # define SSC_TCMR_START_ANYLEVEL (6 << SSC_TCMR_START_SHIFT) /* Any level change on TF signal */ # define SSC_TCMR_START_ANYEDGE (7 << SSC_TCMR_START_SHIFT) /* Any edge on TF signal */ + #define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */ #define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT) #define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */ @@ -205,6 +220,7 @@ # define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ # define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ # define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ + #define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */ #define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ #define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ @@ -264,16 +280,16 @@ #define SSC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define SSC_WPSR_WPVSRC_MASK (0xffff << SSC_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_supc.h b/arch/arm/src/sam34/hardware/sam_supc.h index 885340e6b2e..592dbb67585 100644 --- a/arch/arm/src/sam34/hardware/sam_supc.h +++ b/arch/arm/src/sam34/hardware/sam_supc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_supc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SUPC register offsets ****************************************************************/ +/* SUPC register offsets ****************************************************/ #define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ #define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ @@ -43,7 +43,7 @@ #define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ #define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ -/* SUPC register addresses **************************************************************/ +/* SUPC register addresses **************************************************/ #define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) #define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) @@ -52,7 +52,8 @@ #define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) #define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) -/* SUPC register bit definitions ********************************************************/ +/* SUPC register bit definitions ********************************************/ + /* Supply Controller Control Register */ #define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ @@ -112,6 +113,7 @@ # define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ # define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ # define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ + #define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ #define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ @@ -256,16 +258,16 @@ #define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) # define SUPC_SR_WKUPIS(n) (1 << (SUPC_SR_WKUPIS_SHIFT+(n))) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_tc.h b/arch/arm/src/sam34/hardware/sam_tc.h index 2f637089943..d783d19c02a 100644 --- a/arch/arm/src/sam34/hardware/sam_tc.h +++ b/arch/arm/src/sam34/hardware/sam_tc.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_tc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,27 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* TC register offsets **************************************************************************/ +/* TC register offsets ******************************************************/ -/* Timer channel offsets (with respect to timer base offset at 0x00, 0x40, and 0x80 */ +/* Timer channel offsets + *(with respect to timer base offset at 0x00, 0x40, and 0x80 + */ #define SAM_TC_CCR_OFFSET 0x0000 /* Channel Control Register */ #define SAM_TC_CMR_OFFSET 0x0004 /* Channel Mode Register */ @@ -76,7 +78,7 @@ # define SAM_TC_WPMR_OFFSET 0xe4 /* Write Protect Mode Register */ #endif -/* TC register addresses ************************************************************************/ +/* TC register addresses ****************************************************/ #define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TC_CCR_OFFSET) #define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TC_CMR_OFFSET) @@ -296,8 +298,9 @@ # define SAM_TC_QISR (SAM_TC_BASE+SAM_TC_QISR_OFFSET) #endif -/* TC register bit definitions ******************************************************************/ -/* Timer channel registers **********************************************************************/ +/* TC register bit definitions **********************************************/ + +/* Timer channel registers **************************************************/ /* TC Channel Control Register */ @@ -325,6 +328,7 @@ # define TC_CMR_BURST_XC0 (1 << TC_CMR_BURST_SHIFT) /* XC0 ANDed with selected clock */ # define TC_CMR_BURST_XC1 (2 << TC_CMR_BURST_SHIFT) /* XC1 ANDed with selected clock */ # define TC_CMR_BURST_XC2 (3 << TC_CMR_BURST_SHIFT) /* XC2 ANDed with selected clock */ + #define TC_CMR_WAVE (1 << 15) /* Bit 15: Waveform Mode */ /* TC Channel Mode Register -- Capture mode only */ @@ -337,6 +341,7 @@ # define TC_CMR_ETRGEDG_REDGE (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */ # define TC_CMR_ETRGEDG_FEDGE (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */ # define TC_CMR_ETRGEDG_EACH (3 << TC_CMR_ETRGEDG_SHIFT) /* Each */ + #define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */ #define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */ #define TC_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection */ @@ -345,6 +350,7 @@ # define TC_CMR_LDRA_REDGE (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ # define TC_CMR_LDRA_FEDGE (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ # define TC_CMR_LDRA_EACH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */ + #define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection */ #define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT) # define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */ @@ -372,12 +378,14 @@ # define TC_CMR_EEVTEDG_REDGE (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */ # define TC_CMR_EEVTEDG_FEDGE (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */ # define TC_CMR_EEVTEDG_EACH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */ + #define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */ #define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT) # define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB input */ # define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 output */ # define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 output */ # define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 output */ + #define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */ #define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */ #define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT) @@ -385,6 +393,7 @@ # define TC_CMR_WAVSEL_UPDWN (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */ # define TC_CMR_WAVSEL_UPAUTO (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */ # define TC_CMR_WAVSEL_UPDWNAUTO (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */ + #define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */ #define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT) # define TC_CMR_ACPA_NONE (0 << TC_CMR_ACPA_SHIFT) @@ -463,7 +472,10 @@ # define TC_RVALUE_MASK (0x0000ffff) #endif -/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */ +/* TC Status Register, TC Interrupt Enable Register, + * TC Interrupt Disable Register, and + * TC Interrupt Mask Register common bit-field definitions + */ #define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */ #define TC_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */ @@ -493,14 +505,17 @@ # define TC_EMR_TRIGSRCA_MASK (3 << TC_EMR_TRIGSRCA_SHIFT) # define TC_EMR_TRIGSRCA_TIOA (0 << TC_EMR_TRIGSRCA_SHIFT) /* Input A driven by pin TIOAx */ # define TC_EMR_TRIGSRCA_PWM (1 << TC_EMR_TRIGSRCA_SHIFT) /* Input A driven by PWMx */ + # define TC_EMR_TRIGSRCB_SHIFT (5) /* Bits 4-5: Trigger source for input B */ # define TC_EMR_TRIGSRCB_MASK (3 << TC_EMR_TRIGSRCB_SHIFT) # define TC_EMR_TRIGSRCB_TIOA (0 << TC_EMR_TRIGSRCB_SHIFT) /* Input B driven by pin TIOBx */ # define TC_EMR_TRIGSRCB_PWM (1 << TC_EMR_TRIGSRCB_SHIFT) /* Input B driven by PWMx */ + # define TC_EMR_NODIVCLK (1 << 8) /* Bit 8: NO DIVided CLocK */ #endif -/* Timer common registers ***********************************************************************/ +/* Timer common registers ***************************************************/ + /* TC Block Control Register */ #define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command */ @@ -566,16 +581,16 @@ # define TC_WPMR_WPKEY (0x0054494d << TC_WPMR_WPKEY_SHIFT) #endif -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H */ diff --git a/arch/arm/src/sam34/hardware/sam_twi.h b/arch/arm/src/sam34/hardware/sam_twi.h index dd4ecef078c..c6231ab1b9b 100644 --- a/arch/arm/src/sam34/hardware/sam_twi.h +++ b/arch/arm/src/sam34/hardware/sam_twi.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_twi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* TWI register offsets *****************************************************************/ +/* TWI register offsets *****************************************************/ #define SAM_TWI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_TWI_MMR_OFFSET 0x0004 /* Master Mode Register */ @@ -53,7 +53,7 @@ # define SAM_TWI_WPSR_OFFSET 0x00e8 /* Protection Status Register */ #endif -/* TWI register addresses ***************************************************************/ +/* TWI register addresses ***************************************************/ #define SAM_TWI_CR(n) (SAM_TWIN_BASE(n)+SAM_TWI_CR_OFFSET) #define SAM_TWI_MMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_MMR_OFFSET) @@ -103,7 +103,7 @@ # define SAM_TWI1_WPSR (SAM_TWI1_BASE)+SAM_TWI_WPSR_OFFSET) #endif -/* TWI register bit definitions *********************************************************/ +/* TWI register bit definitions *********************************************/ /* TWI Control Register */ @@ -124,6 +124,7 @@ # define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */ # define TWI_MMR_IADRSZ_2BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ # define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ + #define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ #define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */ #define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT) @@ -201,16 +202,16 @@ # define TWI_WPSR_WPVSRC_MASK (0xffff << TWI_WPSR_WPVSRC_SHIFT) #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H */ diff --git a/arch/arm/src/sam34/hardware/sam_uart.h b/arch/arm/src/sam34/hardware/sam_uart.h index 0616be32468..213fb0fa09a 100644 --- a/arch/arm/src/sam34/hardware/sam_uart.h +++ b/arch/arm/src/sam34/hardware/sam_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* UART register offsets ************************************************************************/ +/* UART register offsets ****************************************************/ #define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ #define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ @@ -66,7 +66,7 @@ #define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register (USART only, Not SAM4E) */ /* 0x0100-0x0124: PDC Area (Common) */ -/* UART register addresses **********************************************************************/ +/* UART register addresses **************************************************/ #define SAM_UART0_CR (SAM_UART0_BASE+SAM_UART_CR_OFFSET) #define SAM_UART0_MR (SAM_UART0_BASE+SAM_UART_MR_OFFSET) @@ -213,7 +213,7 @@ #define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET) #define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET) -/* UART register bit definitions ****************************************************************/ +/* UART register bit definitions ********************************************/ /* UART Control Register */ @@ -269,12 +269,14 @@ # define UART_MR_USCLKS_MCK (0 << UART_MR_USCLKS_SHIFT) /* MCK */ # define UART_MR_USCLKS_MCKDIV (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ # define UART_MR_USCLKS_SCK (3 << UART_MR_USCLKS_SHIFT) /* SCK */ + #define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ #define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) # define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */ # define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */ # define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */ # define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ + #define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ #define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART SPI mode only) */ #define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ @@ -285,11 +287,13 @@ # define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ # define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ # define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ + #define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ #define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT) # define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ # define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ # define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ + #define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ #define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) # define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ @@ -343,7 +347,8 @@ #define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ #define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ -/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask +/* UART Interrupt Enable Register, + * UART Interrupt Disable Register, UART Interrupt Mask * Register, and UART Status Register common bit field definitions */ @@ -475,6 +480,7 @@ # define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */ # define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */ + #define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ #define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ #define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT) @@ -485,6 +491,7 @@ # define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */ # define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ + #define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ #if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) @@ -501,6 +508,7 @@ # define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */ # define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */ # define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does not transmit or receive response */ + # define UART_LINMR_PARDIS (1 << 2) /* Bit 2: Parity Disable */ # define UART_LINMR_CHKDIS (1 << 3) /* Bit 3: Checksum Disable */ # define UART_LINMR_CHKTYP (1 << 4) /* Bit 4: Checksum Type */ @@ -540,16 +548,16 @@ #define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ #define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT) -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H */ diff --git a/arch/arm/src/sam34/hardware/sam_udp.h b/arch/arm/src/sam34/hardware/sam_udp.h index 2c9fd598158..ec7130f3ca1 100644 --- a/arch/arm/src/sam34/hardware/sam_udp.h +++ b/arch/arm/src/sam34/hardware/sam_udp.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_udp.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General Definitions ******************************************************************/ + ****************************************************************************/ + +/* General Definitions ******************************************************/ + /* Capabilities and characteristics of endpoints * * EP EP BANKS EP SIZE EP TYPE @@ -56,7 +58,7 @@ #define SAM_UDP_ISOCHRONOUS(ep) (((unsigned)(ep) != 0 && (unsigned)(ep) != 3)) #define SAM_UDP_INTERRUPT(ep) (true) -/* UDP register offsets *****************************************************************/ +/* UDP register offsets *****************************************************/ /* Global Registers */ @@ -72,6 +74,7 @@ /* 0x0024: Reserved */ #define SAM_UDP_RSTEP_OFFSET 0x0028 /* UDP Reset Endpoint Register */ /* 0x002c: Reserved */ + /* Endpoint registers */ #define SAM_UDPEP_CSR_OFFSET(n) (0x0030+((n)<<2)) @@ -96,7 +99,7 @@ #define SAM_UDP_TXVC_OFFSET 0x0074 /* Transceiver Control Register */ /* 0x0078-0x00fc: Reserved */ -/* UDP register addresses ***************************************************************/ +/* UDP register addresses ***************************************************/ /* Global Registers */ @@ -133,7 +136,7 @@ #define SAM_UDP_TXVC (SAM_UDP_BASE+SAM_UDP_TXVC_OFFSET) -/* UDP register bit definitions *********************************************************/ +/* UDP register bit definitions *********************************************/ /* Global Registers */ @@ -159,7 +162,8 @@ # define UDP_FADDR(n) ((uint32_t)(n)) #define UDP_FADDR_FEN (1 << 8) /* Bit 8: Function Enable */ -/* UDP Interrupt Enable, UDP Interrupt Disable, UDP Interrupt Mask, UDP Interrupt +/* UDP Interrupt Enable, UDP Interrupt Disable, + * UDP Interrupt Mask, UDP Interrupt * Status, and UDP Interrupt Clear Registers. */ @@ -195,6 +199,7 @@ # define UDP_RSTEP7 (1 << 7) /* Bit 7: Reset Endpoint 7 */ /* Endpoint registers */ + /* Endpoint Control and Status Registers */ #define UDPEP_CSR_TXCOMP (1 << 0) /* Bit 0: Generates an IN packet with data */ @@ -216,6 +221,7 @@ # define UDPEP_CSR_EPTYPE_BULKIN (6 << UDPEP_CSR_EPTYPE_SHIFT) /* Bulk IN */ # define UDPEP_CSR_EPTYPE_INTOUT (3 << UDPEP_CSR_EPTYPE_SHIFT) /* Interrupt OUT */ # define UDPEP_CSR_EPTYPE_INTIN (7 << UDPEP_CSR_EPTYPE_SHIFT) /* Interrupt IN */ + #define UDPEP_CSR_DTGLE (1 << 11) /* Bit 11: Data Toggle */ #define UDPEP_CSR_EPEDS (1 << 15) /* Bit 15: Endpoint Enable Disable */ #define UDPEP_CSR_RXBYTECNT_SHIFT (16) /* Bits 16-26: Number of Bytes Available in the FIFO */ @@ -230,16 +236,16 @@ #define UDP_TXVC_TXVDIS (1 << 8) /* Bit 8: Transceiver Disable */ #define UDP_TXVC_PUON (1 << 9) /* Bit 9: Pull-up On */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H */ diff --git a/arch/arm/src/sam34/hardware/sam_udphs.h b/arch/arm/src/sam34/hardware/sam_udphs.h index 82cf827ef5e..c2f951b3353 100644 --- a/arch/arm/src/sam34/hardware/sam_udphs.h +++ b/arch/arm/src/sam34/hardware/sam_udphs.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_udphs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* UDPHS register offsets ***************************************************************/ +/* UDPHS register offsets ***************************************************/ #define SAM_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */ #define SAM_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */ @@ -50,7 +50,8 @@ #define SAM_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */ #define SAM_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */ -/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180, +/* Endpoint registers: + * Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180, * 0x1a0, and 0x1c0 */ @@ -65,8 +66,10 @@ #define SAM_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */ /* 0x1e0-0x300: Reserved */ /* 0x300-0x30c: Reserved */ -/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and - * 0x360. NOTE that there is no DMA channel 0. + +/* DMA Channel Registers: + * Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and 0x360. + * NOTE that there is no DMA channel 0. */ #define SAM_UDPHSDMA_OFFSET(n) (0x310+((n)<<4)) @@ -75,7 +78,7 @@ #define SAM_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */ #define SAM_UDPHSDMA_STATUS_OFFSET 0x0c /* UDPHS DMA Channel Status Register */ -/* UDPHS register addresses *************************************************************/ +/* UDPHS register addresses *************************************************/ #define SAM_UDPHS_CTRL (SAM_UDPHS_BASE+SAM_UDPHS_CTRL_OFFSET) #define SAM_UDPHS_FNUM (SAM_UDPHS_BASE+SAM_UDPHS_FNUM_OFFSET) @@ -99,7 +102,7 @@ #define SAM_UDPHSEP_CLRSTA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CLRSTA_OFFSET) #define SAM_UDPHSEP_STA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_STA_OFFSET) -/* DMA Channel Registers*/ +/* DMA Channel Registers */ #define SAM_UDPHSDMA_BASE(n) (SAM_UDPHS_BASE+SAM_UDPHSDMA_OFFSET(n)) #define SAM_UDPHSDMA_NXTDSC(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_NXTDSC_OFFSET) @@ -107,7 +110,8 @@ #define SAM_UDPHSDMA_CONTROL(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_CONTROL_OFFSET) #define SAM_UDPHSDMA_STATUS(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_STATUS_OFFSET) -/* UDPHS register bit definitions *******************************************************/ +/* UDPHS register bit definitions *******************************************/ + /* UDPHS Control Register */ #define UDPHS_CTRL_DEVADDR_SHIFT (0) /* Bits 0-6: UDPHS Address */ @@ -127,8 +131,8 @@ #define UDPHS_FNUM_FNUMERR_SHIFT (8) /* Bits 8-13: Frame Number CRC Error */ #define UDPHS_FNUM_FNUMERR_MASK (63 << UDPHS_FNUM_FNUMERR_SHIFT) -/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear - * Interrupt Register common bit-field definitions +/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, + * and UDPHS Clear Interrupt Register common bit-field definitions */ #define USBPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt (Common) */ @@ -165,6 +169,7 @@ # define UDPHS_TST_SPEEDCFG_NORMAL (0 << UDPHS_TST_SPEEDCFG_SHIFT) /* Normal Mode */ # define UDPHS_TST_SPEEDCFG_HIGH (2 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force High Speed */ # define UDPHS_TST_SPEEDCFG_FULL (3 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force Full Speed */ + #define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */ #define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */ #define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mo */ @@ -190,6 +195,7 @@ # define UDPHS_IPFEATURES_FIFOMAXSIZE_4Kb (5 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 4096 bytes */ # define UDPHS_IPFEATURES_FIFOMAXSIZE_8Kb (6 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 8192 bytes */ # define UDPHS_IPFEATURES_FIFOMAXSIZE_16Kb (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 16384 bytes */ + #define UDPHS_IPFEATURES_BWDPRAM (1 << 15) /* Bit 15: DPRAM Byte Write Capability */ #define UDPHS_IPFEATURES_DATAB168 (1 << 15) /* Bit 15: UTMI DataBus16_8 */ #define UDPHS_IPFEATURES_ISOEPT(n) (1<<((n)+16) @@ -221,6 +227,7 @@ # define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */ # define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */ # define UDPHSEP_CFG_SIZE_1Kb (7 << UDPHSEP_CFG_SIZE_SHIFT) /* 1024 bytes */ + #define UDPHSEP_CFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */ #define UDPHSEP_CFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */ #define UDPHSEP_CFG_TYPE_MASK (3 << UDPHSEP_CFG_TYPE_SHIFT) @@ -228,18 +235,21 @@ # define UDPHSEP_CFG_TYPE_ISOC (1 << UDPHSEP_CFG_TYPE_SHIFT) /* Isochronous endpoint */ # define UDPHSEP_CFG_TYPE_BULK (2 << UDPHSEP_CFG_TYPE_SHIFT) /* Bulk endpoint */ # define UDPHSEP_CFG_TYPE_INTR (3 << UDPHSEP_CFG_TYPE_SHIFT) /* Interrupt endpoint */ + #define UDPHSEP_CFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */ #define UDPHSEP_CFG_BKNUMBER_MASK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) # define UDPHSEP_CFG_BKNUMBER_0BANK (0 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Zero bank (unmapped) */ # define UDPHSEP_CFG_BKNUMBER_1BANK (1 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* One bank (bank 0) */ # define UDPHSEP_CFG_BKNUMBER_2BANK (2 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Double bank (bank 0-1) */ # define UDPHSEP_CFG_BKNUMBER_3BANK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Triple bank (bank 0-2) */ -#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */ -#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT) -#define UDPHSEP_CFG_MAPD (1 << 31) /*Bit 31: Endpoint Mapped */ -/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register, - * and UDPHS Endpoint Control Register common bit-field definitions +#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */ +#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT) +#define UDPHSEP_CFG_MAPD (1 << 31) /* Bit 31: Endpoint Mapped */ + +/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control + * Disable Register, and UDPHS Endpoint Control Register common + * bit-field definitions */ #define UDPHSEP_INT_EPT (1 << 0) /* Bit 0: Endpoint Enable/Disable */ @@ -293,6 +303,7 @@ # define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */ # define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */ # define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */ + #define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */ #define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */ #define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */ @@ -340,16 +351,16 @@ #define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */ #define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H */ diff --git a/arch/arm/src/sam34/hardware/sam_wdt.h b/arch/arm/src/sam34/hardware/sam_wdt.h index 69e43f2a538..cc07003969d 100644 --- a/arch/arm/src/sam34/hardware/sam_wdt.h +++ b/arch/arm/src/sam34/hardware/sam_wdt.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sam34/hardware/sam_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,38 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H #define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* WDT register offsets *****************************************************************/ +/* WDT register offsets *****************************************************/ #define SAM_WDT_CR_OFFSET 0x00 /* Control Register */ #define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */ #define SAM_WDT_SR_OFFSET 0x08 /* Status Register */ -/* WDT register addresses ***************************************************************/ +/* WDT register addresses ***************************************************/ #define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET) #define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET) #define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) -/* WDT register bit definitions *********************************************************/ +/* WDT register bit definitions *********************************************/ + /* Watchdog Timer Control Register */ #define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ @@ -76,16 +77,16 @@ #define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ #define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H */ diff --git a/arch/arm/src/sam34/sam3u_gpio.h b/arch/arm/src/sam34/sam3u_gpio.h index 6edcd56670d..694d68ef47c 100644 --- a/arch/arm/src/sam34/sam3u_gpio.h +++ b/arch/arm/src/sam34/sam3u_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam3u_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H #define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #undef GPIO_HAVE_PULLDOWN #undef GPIO_HAVE_PERIPHCD #undef GPIO_HAVE_SCHMITT #undef GPIO_HAVE_DELAYR -/* Bit-encoded input to sam_configgpio() ********************************************/ +/* Bit-encoded input to sam_configgpio() ************************************/ /* 16-bit Encoding: * @@ -87,7 +88,8 @@ # define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL) # define GPIO_INT_BOTHEDGES (0) -/* If the pin is an GPIO output, then this identifies the initial output value: +/* If the pin is an GPIO output, then this identifies the initial + * output value: * * .... .... V... .... */ @@ -146,23 +148,23 @@ #define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) #define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 16-bit encoding */ typedef uint16_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -173,9 +175,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam3u_periphclks.h b/arch/arm/src/sam34/sam3u_periphclks.h index b3031bdcdeb..8209c498f13 100644 --- a/arch/arm/src/sam34/sam3u_periphclks.h +++ b/arch/arm/src/sam34/sam3u_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam3u_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperipheral(s) putreg32((1 << (s)), SAM_PMC_PCER) @@ -98,19 +99,19 @@ #define sam_dmac_disableclk() sam_disableperipheral(SAM_PID_DMAC) #define sam_udphs_disableclk() sam_disableperipheral(SAM_PID_UDPHS) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -121,9 +122,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam3x_gpio.h b/arch/arm/src/sam34/sam3x_gpio.h index 157becf2fca..9fe275cb51f 100644 --- a/arch/arm/src/sam34/sam3x_gpio.h +++ b/arch/arm/src/sam34/sam3x_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam3x_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM3X_GPIO_H #define __ARCH_ARM_SRC_SAM34_SAM3X_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #undef GPIO_HAVE_PULLDOWN #undef GPIO_HAVE_PERIPHCD #undef GPIO_HAVE_SCHMITT #undef GPIO_HAVE_DELAYR -/* Bit-encoded input to sam_configgpio() ********************************************/ +/* Bit-encoded input to sam_configgpio() ************************************/ /* 32-bit Encoding: * @@ -87,7 +88,8 @@ # define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL) # define GPIO_INT_BOTHEDGES (0) -/* If the pin is an GPIO output, then this identifies the initial output value: +/* If the pin is an GPIO output, then this identifies the initial + * output value: * * .... .... ...V .... .... */ @@ -149,23 +151,23 @@ #define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) #define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 32-bit encoding */ typedef uint32_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -176,9 +178,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam3x_periphclks.h b/arch/arm/src/sam34/sam3x_periphclks.h index f1454070649..f2983ef045f 100644 --- a/arch/arm/src/sam34/sam3x_periphclks.h +++ b/arch/arm/src/sam34/sam3x_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam3x_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM3X_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAM34_SAM3X_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) @@ -132,19 +133,19 @@ #define sam_can0_disableclk() sam_disableperiph1(SAM_PID_CAN0) #define sam_can1_disableclk() sam_disableperiph1(SAM_PID_CAN1) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -155,9 +156,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam4cm_freerun.c b/arch/arm/src/sam34/sam4cm_freerun.c index 51834ea1240..a8b09db2afa 100644 --- a/arch/arm/src/sam34/sam4cm_freerun.c +++ b/arch/arm/src/sam34/sam4cm_freerun.c @@ -64,6 +64,7 @@ /**************************************************************************** * Private Functions ****************************************************************************/ + /**************************************************************************** * Name: sam_freerun_handler * @@ -226,8 +227,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) DEBUGASSERT(freerun && freerun->tch && ts); - /* Temporarily disable the overflow counter. NOTE that we have to be careful - * here because sam_tc_getpending() will reset the pending interrupt status. + /* Temporarily disable the overflow counter. + * NOTE that we have to be careful here because sam_tc_getpending() + * will reset the pending interrupt status. * If we do not handle the overflow here then, it will be lost. */ diff --git a/arch/arm/src/sam34/sam4cm_gpio.h b/arch/arm/src/sam34/sam4cm_gpio.h index 06ae32ee99d..a71e6c30805 100644 --- a/arch/arm/src/sam34/sam4cm_gpio.h +++ b/arch/arm/src/sam34/sam4cm_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4cm_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_GPIO_H #define __ARCH_ARM_SRC_SAM34_SAM4CM_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #define GPIO_HAVE_PULLDOWN 1 #define GPIO_HAVE_PERIPHCD 1 #define GPIO_HAVE_SCHMITT 1 #undef GPIO_HAVE_DELAYR -/* Bit-encoded input to sam_configgpio() ********************************************/ +/* Bit-encoded input to sam_configgpio() ************************************/ /* 32-bit Encoding: * @@ -92,7 +93,8 @@ # define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL) # define GPIO_INT_BOTHEDGES (0) -/* If the pin is an GPIO output, then this identifies the initial output value: +/* If the pin is an GPIO output, then this identifies the initial + * output value: * * .... .... .... V... .... */ @@ -151,23 +153,23 @@ #define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) #define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 32-bit encoding */ typedef uint32_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -178,9 +180,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam4cm_oneshot.c b/arch/arm/src/sam34/sam4cm_oneshot.c index 296f2a8e6ea..2008d273d27 100644 --- a/arch/arm/src/sam34/sam4cm_oneshot.c +++ b/arch/arm/src/sam34/sam4cm_oneshot.c @@ -193,10 +193,12 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, * TC_CMR_BSWTRG_NONE - No software trigger effect on TIOB */ - cmr |= (TC_CMR_BURST_NOTGATED | TC_CMR_CPCSTOP | TC_CMR_EEVTEDG_NONE | - TC_CMR_EEVT_TIOB | TC_CMR_WAVSEL_UPAUTO | TC_CMR_WAVE | - TC_CMR_ACPA_NONE | TC_CMR_ACPC_NONE | TC_CMR_AEEVT_NONE | - TC_CMR_ASWTRG_NONE | TC_CMR_BCPB_NONE | TC_CMR_BCPC_NONE | + cmr |= (TC_CMR_BURST_NOTGATED | TC_CMR_CPCSTOP | + TC_CMR_EEVTEDG_NONE | TC_CMR_EEVT_TIOB | + TC_CMR_WAVSEL_UPAUTO | TC_CMR_WAVE | + TC_CMR_ACPA_NONE | TC_CMR_ACPC_NONE | + TC_CMR_AEEVT_NONE | TC_CMR_ASWTRG_NONE | + TC_CMR_BCPB_NONE | TC_CMR_BCPC_NONE | TC_CMR_BEEVT_NONE | TC_CMR_BSWTRG_NONE); oneshot->tch = sam_tc_allocate(chan, cmr); @@ -232,7 +234,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot && usec); - *usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch); + *usec = (0xffffull * USEC_PER_SEC) / + (uint64_t)sam_tc_divfreq(oneshot->tch); return OK; } @@ -266,7 +269,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, irqstate_t flags; tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", - handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + handler, arg, (unsigned long)ts->tv_sec, + (unsigned long)ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); /* Was the oneshot already running? */ @@ -287,9 +291,11 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, /* Express the delay in microseconds */ - usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); + usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); - /* Get the timer counter frequency and determine the number of counts need to achieve the requested delay. + /* Get the timer counter frequency and determine the number of counts need + * to achieve the requested delay. * * frequency = ticks / second * ticks = seconds * frequency @@ -331,8 +337,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, * of the oneshot timer/counter. * * The function up_timer_gettime() could also be used for this but it takes - * too long. If up_timer_gettime() is called within this function the problem - * vanishes at least if compiled with no optimisation. + * too long. If up_timer_gettime() is called within this function the + * problem vanishes at least if compiled with no optimisation. */ if (freerun != NULL) diff --git a/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c b/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c index 2dc7a168b63..6befdca27c0 100644 --- a/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c +++ b/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c @@ -39,7 +39,9 @@ * Private Types ****************************************************************************/ -/* This structure describes the state of the oneshot timer lower-half driver */ +/* This structure describes the state of the oneshot timer lower-half + * driver + */ struct sam_oneshot_lowerhalf_s { diff --git a/arch/arm/src/sam34/sam4cm_periphclks.h b/arch/arm/src/sam34/sam4cm_periphclks.h index 441f1cefeff..971f0b6a001 100644 --- a/arch/arm/src/sam34/sam4cm_periphclks.h +++ b/arch/arm/src/sam34/sam4cm_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4cm_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAM34_SAM4CM_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) @@ -118,19 +119,19 @@ #define sam_sram_disableclk() sam_disableperiph1(SAM_PID_SRAM) #define sam_smc1_disableclk() sam_disableperiph1(SAM_PID_SMC1) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -141,9 +142,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam4cm_supc.h b/arch/arm/src/sam34/sam4cm_supc.h index b8526c9f251..91d51838d6f 100644 --- a/arch/arm/src/sam34/sam4cm_supc.h +++ b/arch/arm/src/sam34/sam4cm_supc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4cm_supc.h * * Copyright (C) 2014 Gregory Nutt. All rights reserved. @@ -32,11 +32,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_SUPC_H #define __ARCH_ARM_SRC_SAM34_SAM4CM_SUPC_H @@ -47,13 +47,13 @@ #if defined(CONFIG_ARCH_CHIP_SAM4CM) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -66,9 +66,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ uint32_t supc_get_slcd_power_mode(void); void supc_set_slcd_power_mode(uint32_t mode); diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c index 5069b184979..6c61dbd5544 100644 --- a/arch/arm/src/sam34/sam4cm_tc.c +++ b/arch/arm/src/sam34/sam4cm_tc.c @@ -313,7 +313,9 @@ static const struct sam_chconfig_s g_configs[] = static struct sam_chan_s g_channels[ENABLED_CHANNELS]; -/* TC frequency data. This table provides the frequency for each selection of TCCLK */ +/* TC frequency data. + * This table provides the frequency for each selection of TCCLK + */ #define TC_NDIVIDERS 4 #define TC_NDIVOPTIONS 5 diff --git a/arch/arm/src/sam34/sam4cm_tc.h b/arch/arm/src/sam34/sam4cm_tc.h index 33663a3a033..ccc529f849d 100644 --- a/arch/arm/src/sam34/sam4cm_tc.h +++ b/arch/arm/src/sam34/sam4cm_tc.h @@ -67,6 +67,7 @@ /**************************************************************************** * Public Types ****************************************************************************/ + /* An opaque handle used to represent a timer channel */ typedef void *TC_HANDLE; diff --git a/arch/arm/src/sam34/sam4cm_tickless.c b/arch/arm/src/sam34/sam4cm_tickless.c index 4f68b771f8a..5fb1214558a 100644 --- a/arch/arm/src/sam34/sam4cm_tickless.c +++ b/arch/arm/src/sam34/sam4cm_tickless.c @@ -25,8 +25,8 @@ * is suppressed and the platform specific code is expected to provide the * following custom functions. * - * void up_timer_initialize(void): Initializes the timer facilities. Called - * early in the initialization sequence (by up_initialize()). + * void up_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_initialize()). * int up_timer_gettime(FAR struct timespec *ts): Returns the current * time from the platform specific time source. * int up_timer_cancel(void): Cancels the interval timer. @@ -40,6 +40,7 @@ * logic when the interval timer expires. * ****************************************************************************/ + /**************************************************************************** * SAM34 Timer Usage * @@ -351,9 +352,10 @@ int up_timer_gettime(FAR struct timespec *ts) int up_timer_cancel(FAR struct timespec *ts) { - return ONESHOT_INITIALIZED(&g_tickless.oneshot) && FREERUN_INITIALIZED(&g_tickless.freerun) ? - sam_oneshot_cancel(&g_tickless.oneshot, &g_tickless.freerun, ts) : - -EAGAIN; + return ONESHOT_INITIALIZED(&g_tickless.oneshot) && + FREERUN_INITIALIZED(&g_tickless.freerun) ? + sam_oneshot_cancel(&g_tickless.oneshot, + &g_tickless.freerun, ts) : -EAGAIN; } /**************************************************************************** @@ -384,7 +386,8 @@ int up_timer_cancel(FAR struct timespec *ts) int up_timer_start(FAR const struct timespec *ts) { return ONESHOT_INITIALIZED(&g_tickless.oneshot) ? - sam_oneshot_start(&g_tickless.oneshot, &g_tickless.freerun, sam_oneshot_handler, NULL, ts) : + sam_oneshot_start(&g_tickless.oneshot, + &g_tickless.freerun, sam_oneshot_handler, NULL, ts) : -EAGAIN; } #endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/sam34/sam4e_gpio.h b/arch/arm/src/sam34/sam4e_gpio.h index 747a58c40e0..7b1cfe99790 100644 --- a/arch/arm/src/sam34/sam4e_gpio.h +++ b/arch/arm/src/sam34/sam4e_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4e_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4E_GPIO_H #define __ARCH_ARM_SRC_SAM34_SAM4E_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #define GPIO_HAVE_PULLDOWN 1 #define GPIO_HAVE_PERIPHCD 1 #define GPIO_HAVE_SCHMITT 1 #define GPIO_HAVE_DELAYR 1 -/* Bit-encoded input to sam_configgpio() ********************************************/ +/* Bit-encoded input to sam_configgpio() ************************************/ /* 32-bit Encoding: * @@ -92,7 +93,8 @@ # define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL) # define GPIO_INT_BOTHEDGES (0) -/* If the pin is an GPIO output, then this identifies the initial output value: +/* If the pin is an GPIO output, then this identifies the initial output + * value: * * .... .... ...V .... .... */ @@ -153,23 +155,23 @@ #define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) #define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 32-bit encoding */ typedef uint32_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -180,9 +182,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam4e_periphclks.h b/arch/arm/src/sam34/sam4e_periphclks.h index 76ef9b3c487..17de80c1272 100644 --- a/arch/arm/src/sam34/sam4e_periphclks.h +++ b/arch/arm/src/sam34/sam4e_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4e_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4E_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAM34_SAM4E_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) @@ -128,19 +129,19 @@ #define sam_emac_disableclk() sam_disableperiph1(SAM_PID_EMAC) #define sam_uart1_disableclk() sam_disableperiph1(SAM_PID_UART1) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -151,9 +152,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam4l_clockconfig.c b/arch/arm/src/sam34/sam4l_clockconfig.c index e4625392819..3702ee827a5 100644 --- a/arch/arm/src/sam34/sam4l_clockconfig.c +++ b/arch/arm/src/sam34/sam4l_clockconfig.c @@ -45,13 +45,15 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_ARCH_RAMFUNCS # error "CONFIG_ARCH_RAMFUNCS must be defined" #endif -/* Board/Clock Setup *******************************************************/ +/* Board/Clock Setup ********************************************************/ + /* Verify dividers */ #if ((BOARD_CPU_SHIFT > BOARD_PBA_SHIFT) || (BOARD_CPU_SHIFT > BOARD_PBB_SHIFT) || \ @@ -185,8 +187,8 @@ /* RC80M. This might be the system clock or the source clock for the DFPLL * or it could be the source for GCLK9 that drives PLL0. * - * By selecting CONFIG_SAM34_RC80M, you can also force the clock to be enabled - * at boot time. + * By selecting CONFIG_SAM34_RC80M, you can also force the clock to be + * enabled at boot time. */ #if defined(CONFIG_SAM34_RC80M) || defined(BOARD_SYSCLK_SOURCE_RC80M) || \ @@ -480,15 +482,15 @@ static inline void sam_enableosc0(void) /* Enable and configure OSC0 */ - regval = SAM_OSC0_STARTUP_VALUE | SAM_OSC0_GAIN_VALUE | SAM_OSC0_MODE_VALUE | - SCIF_OSCCTRL0_OSCEN; - putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_OSCCTRL0_OFFSET), - SAM_SCIF_UNLOCK); + regval = SAM_OSC0_STARTUP_VALUE | SAM_OSC0_GAIN_VALUE | + SAM_OSC0_MODE_VALUE | SCIF_OSCCTRL0_OSCEN; + putreg32(SCIF_UNLOCK_KEY(0xaa) | + SCIF_UNLOCK_ADDR(SAM_SCIF_OSCCTRL0_OFFSET), SAM_SCIF_UNLOCK); putreg32(regval, SAM_SCIF_OSCCTRL0); /* Wait for OSC0 to be ready */ - while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_OSC0RDY) == 0); + while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_OSC0RDY) == 0); } #endif @@ -507,14 +509,16 @@ static inline void sam_enableosc32(void) uint32_t regval; /* Set up the OSCCTRL32 register using settings from the board.h file. - * Also enable the oscillator and provide bother the 32KHz and 1KHz output. + * Also enable the oscillator and provide bother the 32KHz and 1KHz + * output. */ - regval = SAM_OSC32_STARTUP_VALUE | BOARD_OSC32_SELCURR | SAM_OSC32_MODE_VALUE | - BSCIF_OSCCTRL32_EN1K | BSCIF_OSCCTRL32_EN32K | - BSCIF_OSCCTRL32_OSC32EN; + regval = SAM_OSC32_STARTUP_VALUE | BOARD_OSC32_SELCURR | + SAM_OSC32_MODE_VALUE | BSCIF_OSCCTRL32_EN1K | + BSCIF_OSCCTRL32_EN32K | BSCIF_OSCCTRL32_OSC32EN; - putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_OSCCTRL32_OFFSET), + putreg32(BSCIF_UNLOCK_KEY(0xaa) | + BSCIF_UNLOCK_ADDR(SAM_BSCIF_OSCCTRL32_OFFSET), SAM_BSCIF_UNLOCK); putreg32(regval, SAM_BSCIF_OSCCTRL32); @@ -547,7 +551,7 @@ static inline void sam_enablerc80m(void) /* Wait for OSC32 to be ready */ - while (getreg32(SAM_SCIF_RC80MCR) & SCIF_RC80MCR_EN) == 0); + while ((getreg32(SAM_SCIF_RC80MCR) & SCIF_RC80MCR_EN) == 0); } #endif @@ -571,13 +575,14 @@ static inline void sam_enablercfast(void) regval &= ~SCIF_RCFASTCFG_FRANGE_MASK; regval |= (SAM_RCFAST_RANGE | SCIF_RCFASTCFG_EN); - putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_RCFASTCFG_OFFSET), + putreg32(SCIF_UNLOCK_KEY(0xaa) | + SCIF_UNLOCK_ADDR(SAM_SCIF_RCFASTCFG_OFFSET), SAM_SCIF_UNLOCK); putreg32(regval, SAM_SCIF_RCFASTCFG); /* Wait for RCFAST to be ready */ - while (getreg32(SAM_SCIF_RCFASTCFG) & SCIF_RCFASTCFG_EN) == 0); + while ((getreg32(SAM_SCIF_RCFASTCFG) & SCIF_RCFASTCFG_EN) == 0); } #endif @@ -601,13 +606,14 @@ static inline void sam_enablerc1m(void) regval &= ~BSCIF_RCFASTCFG_FRANGE_MASK; regval |= (SAM_RCFAST_RANGE | BSCIF_RCFASTCFG_EN); - putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC1MCR_OFFSET), + putreg32(BSCIF_UNLOCK_KEY(0xaa) | + BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC1MCR_OFFSET), SAM_BSCIF_UNLOCK); putreg32(regval | BSCIF_RC1MCR_CLKOEN, SAM_BSCIF_RC1MCR); /* Wait for RCFAST to be ready */ - while (getreg32(SAM_BSCIF_RC1MCR) & BSCIF_RC1MCR_CLKOEN) == 0); + while ((getreg32(SAM_BSCIF_RC1MCR) & BSCIF_RC1MCR_CLKOEN) == 0); } #endif @@ -628,13 +634,15 @@ static inline void sam_enablerc32k(void) /* Configure and enable RC32K */ regval = getreg32(SAM_BSCIF_RC32KCR); - putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC32KCR_OFFSET), + putreg32(BSCIF_UNLOCK_KEY(0xaa) | + BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC32KCR_OFFSET), SAM_BSCIF_UNLOCK); - putreg32(regval | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN, SAM_BSCIF_RC32KCR); + putreg32(regval | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN, + SAM_BSCIF_RC32KCR); /* Wait for RCFAST to be ready */ - while (getreg32(SAM_BSCIF_RC32KCR) & BSCIF_RC32KCR_EN) == 0); + while ((getreg32(SAM_BSCIF_RC32KCR) & BSCIF_RC32KCR_EN) == 0); } #endif @@ -693,7 +701,9 @@ static inline void sam_enablepll0(void) /* Set up the multiers and dividers */ regval = getreg32(SAM_SCIF_PLL0); - regval &= ~(SCIF_PLL0_PLLOSC_MASK | SCIF_PLL0_PLLDIV_MASK | SCIF_PLL0_PLLMUL_MASK); + regval &= ~(SCIF_PLL0_PLLOSC_MASK | + SCIF_PLL0_PLLDIV_MASK | + SCIF_PLL0_PLLMUL_MASK); regval |= ((SAM_PLL0_MUL - 1) << SCIF_PLL0_PLLMUL_SHIFT) | (BOARD_DFLL0_DIV << SCIF_PLL0_PLLDIV_SHIFT) | SCIF_PLL0_PLLCOUNT_MAX | SAM_PLL0_SOURCE; @@ -797,7 +807,8 @@ static inline void sam_enabledfll0(void) * before this function was called. */ - putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_DFLL0CONF_OFFSET), + putreg32(SCIF_UNLOCK_KEY(0xaa) | + SCIF_UNLOCK_ADDR(SAM_SCIF_DFLL0CONF_OFFSET), SAM_SCIF_UNLOCK); putreg32(SCIF_DFLL0CONF_EN, SAM_SCIF_DFLL0CONF); @@ -882,19 +893,24 @@ static inline void sam_setdividers(void) /* Then set the divider values. */ - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET), + SAM_PM_UNLOCK); putreg32(cpusel, SAM_PM_CPUSEL); - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBASEL_OFFSET), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBASEL_OFFSET), + SAM_PM_UNLOCK); putreg32(pbasel, SAM_PM_PBASEL); - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBSEL_OFFSET), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBSEL_OFFSET), + SAM_PM_UNLOCK); putreg32(pbbsel, SAM_PM_PBBSEL); - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCSEL_OFFSET), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCSEL_OFFSET), + SAM_PM_UNLOCK); putreg32(pbcsel, SAM_PM_PBCSEL); - putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET), SAM_PM_UNLOCK); + putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET), + SAM_PM_UNLOCK); putreg32(pbdsel, SAM_PM_PBDSEL); } @@ -981,7 +997,8 @@ static inline void sam_flash_readmode(uint32_t command) * Description: * Configure FLASH read mode and wait states. * - * Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes + * Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various + * modes * (Table 42-30 in the big data sheet). * * ------- ------------------- ---------- ---------- @@ -1001,7 +1018,8 @@ static inline void sam_flash_readmode(uint32_t command) * ****************************************************************************/ -static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwkup) +static inline void sam_flash_config(uint32_t cpuclock, + uint32_t psm, bool fastwkup) { bool waitstate; uint32_t command; @@ -1178,7 +1196,6 @@ static inline void sam_usbclock(void) #endif #if SAM_CLOCK_USB_DIV > 0 - u_avr32_pm_gcctrl.GCCTRL.diven = diven; u_avr32_pm_gcctrl.GCCTRL.div = div; #endif @@ -1327,7 +1344,7 @@ void sam_clockconfig(void) * already running from RCSYS. */ - // sam_mainclk(PM_MCCTRL_MCSEL_RCSYS); + /* sam_mainclk(PM_MCCTRL_MCSEL_RCSYS); */ #elif defined(BOARD_SYSCLK_SOURCE_OSC0) /* Configure FLASH read mode and wait states */ diff --git a/arch/arm/src/sam34/sam4l_gpio.c b/arch/arm/src/sam34/sam4l_gpio.c index a7659281b90..89645b707c9 100644 --- a/arch/arm/src/sam34/sam4l_gpio.c +++ b/arch/arm/src/sam34/sam4l_gpio.c @@ -45,7 +45,10 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO -static const char g_portchar[4] = { 'A', 'B', 'C', 'D' }; +static const char g_portchar[4] = +{ + 'A', 'B', 'C', 'D' +}; #endif /**************************************************************************** @@ -89,7 +92,9 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset) * ****************************************************************************/ -static int sam_configinput(uintptr_t base, uint32_t pin, gpio_pinset_t cfgset) +static int sam_configinput(uintptr_t base, + uint32_t pin, + gpio_pinset_t cfgset) { /* Disable interrupts on the pin */ @@ -176,9 +181,9 @@ static inline int sam_configinterrupt(uintptr_t base, uint32_t pin, { int ret; - /* Just configure the pin as an input, then set the interrupt configuration. - * Here we exploit the fact that sam_configinput() enabled both rising and - * falling edges. + /* Just configure the pin as an input, then set the interrupt + * configuration. Here we exploit the fact that sam_configinput() enabled + * both rising and falling edges. */ ret = sam_configinput(base, pin, cfgset); @@ -499,13 +504,14 @@ bool sam_gpioread(gpio_pinset_t pinset) return (getreg32(base + SAM_GPIO_PVR_OFFSET) & pin) != 0; } -/************************************************************************************ +/**************************************************************************** * Function: sam_dumpgpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpgpio(uint32_t pinset, const char *msg) @@ -528,20 +534,30 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); gpioinfo(" GPER: %08x PMR0: %08x PMR1: %08x PMR2: %08x\n", - getreg32(base + SAM_GPIO_GPER_OFFSET), getreg32(base + SAM_GPIO_PMR0_OFFSET), - getreg32(base + SAM_GPIO_PMR1_OFFSET), getreg32(base + SAM_GPIO_PMR2_OFFSET)); + getreg32(base + SAM_GPIO_GPER_OFFSET), + getreg32(base + SAM_GPIO_PMR0_OFFSET), + getreg32(base + SAM_GPIO_PMR1_OFFSET), + getreg32(base + SAM_GPIO_PMR2_OFFSET)); gpioinfo(" ODER: %08x OVR: %08x PVR: %08x PUER: %08x\n", - getreg32(base + SAM_GPIO_ODER_OFFSET), getreg32(base + SAM_GPIO_OVR_OFFSET), - getreg32(base + SAM_GPIO_PVR_OFFSET), getreg32(base + SAM_GPIO_PUER_OFFSET)); + getreg32(base + SAM_GPIO_ODER_OFFSET), + getreg32(base + SAM_GPIO_OVR_OFFSET), + getreg32(base + SAM_GPIO_PVR_OFFSET), + getreg32(base + SAM_GPIO_PUER_OFFSET)); gpioinfo(" PDER: %08x IER: %08x IMR0: %08x IMR1: %08x\n", - getreg32(base + SAM_GPIO_PDER_OFFSET), getreg32(base + SAM_GPIO_IER_OFFSET), - getreg32(base + SAM_GPIO_IMR0_OFFSET), getreg32(base + SAM_GPIO_IMR1_OFFSET)); + getreg32(base + SAM_GPIO_PDER_OFFSET), + getreg32(base + SAM_GPIO_IER_OFFSET), + getreg32(base + SAM_GPIO_IMR0_OFFSET), + getreg32(base + SAM_GPIO_IMR1_OFFSET)); gpioinfo(" GFER: %08x IFR: %08x ODCR0: %08x ODCR1: %08x\n", - getreg32(base + SAM_GPIO_GFER_OFFSET), getreg32(base + SAM_GPIO_IFR_OFFSET), - getreg32(base + SAM_GPIO_ODCR0_OFFSET), getreg32(base + SAM_GPIO_ODCR1_OFFSET)); + getreg32(base + SAM_GPIO_GFER_OFFSET), + getreg32(base + SAM_GPIO_IFR_OFFSET), + getreg32(base + SAM_GPIO_ODCR0_OFFSET), + getreg32(base + SAM_GPIO_ODCR1_OFFSET)); gpioinfo(" OSRR0: %08x EVER: %08x PARAM: %08x VERS: %08x\n", - getreg32(base + SAM_GPIO_OSRR0_OFFSET), getreg32(base + SAM_GPIO_EVER_OFFSET), - getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET)); + getreg32(base + SAM_GPIO_OSRR0_OFFSET), + getreg32(base + SAM_GPIO_EVER_OFFSET), + getreg32(base + SAM_GPIO_PARAMETER_OFFSET), + getreg32(base + SAM_GPIO_VERSION_OFFSET)); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/sam34/sam4l_gpio.h b/arch/arm/src/sam34/sam4l_gpio.h index 2292c8021f8..0e172802eb5 100644 --- a/arch/arm/src/sam34/sam4l_gpio.h +++ b/arch/arm/src/sam34/sam4l_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4l_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4L_GPIO_H #define __ARCH_ARM_SRC_SAM34_SAM4L_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Bit-encoded input to sam_configgpio() ********************************************/ +/* Bit-encoded input to sam_configgpio() ************************************/ -/* 24-bit Encoding. This could be compacted into 16-bits by making the bit usage - * mode specific. However, by giving each bit field a unique position, we handle - * bad combinations of properties safely. +/* 24-bit Encoding. This could be compacted into 16-bits by making the bit + * usage mode specific. However, by giving each bit field a unique position, + * we handle bad combinations of properties safely. * * MODE BITFIELDS * ------------ ----------------------------- @@ -158,7 +158,8 @@ */ #define GPIO_DRIVE_SHIFT (14) /* Bits 14-15: Interrupting input control */ -#define GPIO_DRIVE_MASK (3 << GPIO_INT_SHIFT) /* Lowest drive strength*/ + +#define GPIO_DRIVE_MASK (3 << GPIO_INT_SHIFT) /* Lowest drive strength */ # define GPIO_DRIVE_LOW (0 << GPIO_INT_SHIFT) # define GPIO_DRIVE_MEDLOW (1 << GPIO_INT_SHIFT) # define GPIO_DRIVE_MEDHIGH (2 << GPIO_INT_SHIFT) @@ -178,7 +179,8 @@ #define GPIO_SLEW (1 << 13) /* Bit 13: Enable output slew control */ -/* If the pin is an GPIO output, then this identifies the initial output value: +/* If the pin is an GPIO output, then this identifies the initial + * output value: * * MODE BITFIELDS * ------------ ----------------------------- @@ -211,10 +213,12 @@ # define GPIO_INT_RISING (1 << GPIO_INT_SHIFT) /* Rising edge */ # define GPIO_INT_FALLING (2 << GPIO_INT_SHIFT) /* Falling edge */ -/* These combinations control events. These help to clean up pin definitions. */ +/* These combinations control events. + * These help to clean up pin definitions. + */ -#define GPIO_EVENT_CHANGE (GPIO_PERIPH_EVENTS | GPIO_INT_CHANGE) /* Pin change */ -#define GPIO_EVENT_RISING (GPIO_PERIPH_EVENTS | GPIO_INT_RISING) /* Rising edge */ +#define GPIO_EVENT_CHANGE (GPIO_PERIPH_EVENTS | GPIO_INT_CHANGE) /* Pin change */ +#define GPIO_EVENT_RISING (GPIO_PERIPH_EVENTS | GPIO_INT_RISING) /* Rising edge */ #define GPIO_EVENT_FALLING (GPIO_PERIPH_EVENTS | GPIO_INT_FALLING) /* Falling edge */ /* Enable input/periphal glitch filter @@ -310,23 +314,23 @@ #define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) #define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 24-bit encoding */ typedef uint32_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -337,9 +341,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam4l_periphclks.c b/arch/arm/src/sam34/sam4l_periphclks.c index fcf4b3ac72a..1f3fb7c3d12 100644 --- a/arch/arm/src/sam34/sam4l_periphclks.c +++ b/arch/arm/src/sam34/sam4l_periphclks.c @@ -37,6 +37,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* USBC source clock selection */ #ifdef CONFIG_SAM34_USBC @@ -594,7 +595,8 @@ void sam_pbb_disableperipheral(uint32_t bitset) * Name: sam_usbc_enableclk * * Description: - * Enable clocking for the USBC using settings from the board.h header files. + * Enable clocking for the USBC using settings from the board.h header + * files. * * "The USBC has two bus clocks connected: One High Speed Bus clock * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks diff --git a/arch/arm/src/sam34/sam4l_periphclks.h b/arch/arm/src/sam34/sam4l_periphclks.h index 8c5aa122c0b..d975a052af1 100644 --- a/arch/arm/src/sam34/sam4l_periphclks.h +++ b/arch/arm/src/sam34/sam4l_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4l_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,9 +31,9 @@ #ifdef CONFIG_ARCH_CHIP_SAM4L -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* SAM4L helper macros */ @@ -212,19 +212,19 @@ #define sam_eic_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_EIC) #define sam_picouart_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_PICOUART) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -235,87 +235,93 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_init_periphclks * * Description: * Called during boot to enable clocking on all selected peripherals. * - ************************************************************************************/ + ****************************************************************************/ void sam_init_periphclks(void); -/************************************************************************************ +/**************************************************************************** * Name: sam_modifyperipheral * * Description: - * This is a convenience function that is intended to be used to enable or disable - * module clocking. + * This is a convenience function that is intended to be used to enable or + * disable module clocking. * - ************************************************************************************/ + ****************************************************************************/ -void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits); +void sam_modifyperipheral(uintptr_t regaddr, + uint32_t clrbits, uint32_t setbits); -/************************************************************************************ +/**************************************************************************** * Name: sam_pba_modifydivmask * * Description: - * This is a convenience function that is intended to be used to modify bits in - * the PBA divided clock (DIVMASK) register. + * This is a convenience function that is intended to be used to modify + * bits in the PBA divided clock (DIVMASK) register. * - ************************************************************************************/ + ****************************************************************************/ void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits); -/************************************************************************************ +/**************************************************************************** * Name: sam_pba_enableperipheral * * Description: - * This is a convenience function to enable a peripheral on the APBA bridge. + * This is a convenience function to enable a peripheral on the APBA + * bridge. * - ************************************************************************************/ + ****************************************************************************/ void sam_pba_enableperipheral(uint32_t bitset); -/************************************************************************************ +/**************************************************************************** * Name: sam_pba_disableperipheral * * Description: - * This is a convenience function to disable a peripheral on the APBA bridge. + * This is a convenience function to disable a peripheral on the APBA + * bridge. * - ************************************************************************************/ + ****************************************************************************/ void sam_pba_disableperipheral(uint32_t bitset); -/************************************************************************************ +/**************************************************************************** * Name: sam_pbb_enableperipheral * * Description: - * This is a convenience function to enable a peripheral on the APBB bridge. + * This is a convenience function to enable a peripheral on the APBB + * bridge. * - ************************************************************************************/ + ****************************************************************************/ void sam_pbb_enableperipheral(uint32_t bitset); -/************************************************************************************ +/**************************************************************************** * Name: sam_pbb_disableperipheral * * Description: - * This is a convenience function to disable a peripheral on the APBA bridge. + * This is a convenience function to disable a peripheral on the APBA + * bridge. * - ************************************************************************************/ + ****************************************************************************/ void sam_pbb_disableperipheral(uint32_t bitset); -/************************************************************************************ +/**************************************************************************** * Name: sam_usbc_enableclk * * Description: - * Enable clocking for the USBC using settings from the board.h header files. + * Enable clocking for the USBC using settings from the board.h header + * files. * * "The USBC has two bus clocks connected: One High Speed Bus clock * (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks @@ -331,19 +337,19 @@ void sam_pbb_disableperipheral(uint32_t bitset); * the SCIF module. Before using the USB, the user must ensure that the * USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module." * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM34_USBC void sam_usbc_enableclk(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_usbc_disableclk * * Description: * Disable clocking to the USBC. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM34_USBC void sam_usbc_disableclk(void); diff --git a/arch/arm/src/sam34/sam4s_gpio.h b/arch/arm/src/sam34/sam4s_gpio.h index be8f91720f7..57197d52c09 100644 --- a/arch/arm/src/sam34/sam4s_gpio.h +++ b/arch/arm/src/sam34/sam4s_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4s_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H #define __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #define GPIO_HAVE_PULLDOWN 1 #define GPIO_HAVE_PERIPHCD 1 #define GPIO_HAVE_SCHMITT 1 #undef GPIO_HAVE_DELAYR -/* Bit-encoded input to sam_configgpio() ********************************************/ +/* Bit-encoded input to sam_configgpio() ************************************/ /* 32-bit Encoding: * @@ -92,7 +93,8 @@ # define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL) # define GPIO_INT_BOTHEDGES (0) -/* If the pin is an GPIO output, then this identifies the initial output value: +/* If the pin is an GPIO output, then this identifies the initial + * output value: * * .... .... .... V... .... */ @@ -151,23 +153,23 @@ #define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) #define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 32-bit encoding */ typedef uint32_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -178,9 +180,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam4s_periphclks.h b/arch/arm/src/sam34/sam4s_periphclks.h index 626d62dd96a..25b0fa361a8 100644 --- a/arch/arm/src/sam34/sam4s_periphclks.h +++ b/arch/arm/src/sam34/sam4s_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam4s_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) @@ -108,19 +109,19 @@ #define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC) #define sam_udp_disableclk() sam_disableperiph1(SAM_PID_UDP) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -131,9 +132,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam_aes.h b/arch/arm/src/sam34/sam_aes.h index b8ad8bd29d7..8d983e1e34c 100644 --- a/arch/arm/src/sam34/sam_aes.h +++ b/arch/arm/src/sam34/sam_aes.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_aes.h * * Copyright (C) 2014 Gregory Nutt. All rights reserved. @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_AES_H #define __ARCH_ARM_SRC_SAM34_SAM_AES_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -52,16 +52,16 @@ # error "Unknown chip for AES" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_SAM_AES_H */ diff --git a/arch/arm/src/sam34/sam_allocateheap.c b/arch/arm/src/sam34/sam_allocateheap.c index 08c977838f1..2b58ef75a07 100644 --- a/arch/arm/src/sam34/sam_allocateheap.c +++ b/arch/arm/src/sam34/sam_allocateheap.c @@ -44,6 +44,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* All SAM's have SRAM0. The SAM3U family also have SRAM1 and possibly * NFCSRAM. NFCSRAM may not be used, however, if NAND support is enabled. * In addition, the SAM3U and SAM4S have external SRAM at CS0 (EXTSRAM0). @@ -179,7 +180,8 @@ * * Kernel .data region. Size determined at link time. * Kernel .bss region Size determined at link time. - * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. * Padding for alignment * User .data region. Size determined at link time. * User .bss region Size determined at link time. @@ -196,7 +198,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; int log2; @@ -221,7 +224,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - sam_mpu_uheap((uintptr_t)ubase, usize); + sam_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -250,7 +253,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; int log2; diff --git a/arch/arm/src/sam34/sam_clockconfig.c b/arch/arm/src/sam34/sam_clockconfig.c index b8baa379262..883e89733a9 100644 --- a/arch/arm/src/sam34/sam_clockconfig.c +++ b/arch/arm/src/sam34/sam_clockconfig.c @@ -138,7 +138,8 @@ static inline void sam_supcsetup(void) putreg32((SUPC_CR_XTALSEL | SUPR_CR_KEY), SAM_SUPC_CR); for (delay = 0; - (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX; + (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && + delay < UINT32_MAX; delay++); } } @@ -178,10 +179,10 @@ static inline void sam_pmcsetup(void) { /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to * enable the main oscillator, the MOSCXTS bit in the Power Management - * Controller Status Register (PMC_SR) is cleared and the counter starts - * counting down on the slow clock divided by 8 from the MOSCXTCNT - * value. ... When the counter reaches 0, the MOSCXTS bit is set, - * indicating that the main clock is valid." + * Controller Status Register (PMC_SR) is cleared and the counter + * starts counting down on the slow clock divided by 8 from the + * MOSCXTCNT value. ... When the counter reaches 0, the MOSCXTS bit is + * set, indicating that the main clock is valid." */ putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR); @@ -191,9 +192,9 @@ static inline void sam_pmcsetup(void) /* "Switch to the main oscillator. The selection is made by writing the * MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of * the Main Clock source is glitch free, so there is no need to run out - * of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS - * bit of the power Management Controller Status Register (PMC_SR) allows - * knowing when the switch sequence is done." + * of SLCK, PLLACK or UPLLCK in order to change the selection. The + * MOSCSELS bit of the power Management Controller Status Register + * (PMC_SR) allows knowing when the switch sequence is done." * * MOSCSELS: Main Oscillator Selection Status * 0 = Selection is done @@ -204,12 +205,12 @@ static inline void sam_pmcsetup(void) sam_pmcwait(PMC_INT_MOSCSELS); /* "Select the master clock. "The Master Clock selection is made by writing - * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). - * The prescaler supports the division by a power of 2 of the selected clock - * between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs - * the prescaler. Each time PMC_MCKR is written to define a new Master Clock, - * the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is - * established. + * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock + * Register). The prescaler supports the division by a power of 2 of the + * selected clock between 1 and 64, and the division by 3. The PRES field + * in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to + * define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It + * reads 0 until the Master Clock is established. */ regval = getreg32(SAM_PMC_MCKR); @@ -225,7 +226,7 @@ static inline void sam_pmcsetup(void) * to PLLA_MMAX. */ - //putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR); + /* putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR); */ #endif /* Setup PLLA and wait for LOCKA */ @@ -340,18 +341,18 @@ static inline void sam_disabledefaultmaster(void) * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_clockconfig * * Description: - * Called to initialize the SAM3/4. This does whatever setup is needed to put the - * SoC in a usable state. This includes the initialization of clocking using the - * settings in board.h. (After power-on reset, the SAM3/4 is initially running on - * a 4MHz internal RC clock). This function also performs other low-level chip - * initialization of the chip including EFC, master clock, IRQ & watchdog - * configuration. + * Called to initialize the SAM3/4. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. (After power-on reset, the + * SAM3/4 is initially running on a 4MHz internal RC clock). This + * function also performs other low-level chip initialization of the chip + * including EFC, master clock, IRQ & watchdog configuration. * - ************************************************************************************/ + ****************************************************************************/ void sam_clockconfig(void) { diff --git a/arch/arm/src/sam34/sam_clockconfig.h b/arch/arm/src/sam34/sam_clockconfig.h index f6fb9cffc5c..86012e75fde 100644 --- a/arch/arm/src/sam34/sam_clockconfig.h +++ b/arch/arm/src/sam34/sam_clockconfig.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_clockconfig.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,34 +16,34 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_CLOCKCONFIG_H #define __ARCH_ARM_SRC_SAM34_SAM_CLOCKCONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -54,19 +54,19 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_clockconfig * * Description: - * Called to initialize the SAM3/4. This does whatever setup is needed to put the - * SoC in a usable state. This includes the initialization of clocking using the - * settings in board.h. + * Called to initialize the SAM3/4. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. * - ************************************************************************************/ + ****************************************************************************/ void sam_clockconfig(void); diff --git a/arch/arm/src/sam34/sam_cmcc.c b/arch/arm/src/sam34/sam_cmcc.c index 2f1c1a2ad3b..bfdd3f42c79 100644 --- a/arch/arm/src/sam34/sam_cmcc.c +++ b/arch/arm/src/sam34/sam_cmcc.c @@ -78,16 +78,16 @@ void sam_cmcc_enable(void) { /* "On reset, the cache controller data entries are all invalidated and the - * cache is disabled. The cache is transparent to processor operations. The - * cache controller is activated with its configuration registers. The + * cache is disabled. The cache is transparent to processor operations. + * The cache controller is activated with its configuration registers. The * configuration interface is memory mapped in the private peripheral bus. * * "Use the following sequence to enable the cache controller. * - * "1. Verify that the cache controller is disabled, reading the value of the - * CSTS (cache status) field of the CMCC_SR register. - * "2. Enable the cache controller, writing 1 to the CEN (cache enable) field - * of the CMCC_CTRL register." + * "1. Verify that the cache controller is disabled, reading the value of + * the CSTS (cache status) field of the CMCC_SR register. + * "2. Enable the cache controller, writing 1 to the CEN (cache enable) + * field of the CMCC_CTRL register." */ if ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) == 0) @@ -160,9 +160,9 @@ void sam_cmcc_invalidate(uintptr_t start, uintptr_t end) return; } - /* "When an invalidate by line command is issued the cache controller resets - * the valid bit information of the decoded cache line. As the line is no - * longer valid the replacement counter points to that line. + /* "When an invalidate by line command is issued the cache controller + * resets the valid bit information of the decoded cache line. As the + * line is no longer valid the replacement counter points to that line. * * "Use the following sequence to invalidate one line of cache. * diff --git a/arch/arm/src/sam34/sam_cmcc.h b/arch/arm/src/sam34/sam_cmcc.h index e0b8a7a1dfb..cb3b155b0e4 100644 --- a/arch/arm/src/sam34/sam_cmcc.h +++ b/arch/arm/src/sam34/sam_cmcc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_cmcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_CMCC_H #define __ARCH_ARM_SRC_SAM34_SAM_CMCC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,23 +31,23 @@ #ifdef CONFIG_SAM34_CMCC -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -58,9 +58,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_cmcc_enable @@ -112,7 +112,9 @@ void sam_cmcc_invalidateall(void); #endif /* __ASSEMBLY__ */ #else /* CONFIG_SAM34_CMCC */ -/* Stubs so that we don't have to put condition compilation in driver source */ +/* Stubs so that we don't have to put condition compilation in driver + * source + */ # define sam_cmcc_invalidate(start, end) # define sam_cmcc_invalidateall() diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c index bc613c2f763..292f87e650b 100644 --- a/arch/arm/src/sam34/sam_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -1206,7 +1206,9 @@ static inline int sam_multiple(struct sam_dma_s *dmach) putreg32(dmach->cfg, dmach->base + SAM_DMACHAN_CFG_OFFSET); - /* Program the DSCR register with the pointer to the firstlink list entry. */ + /* Program the DSCR register with the pointer to the firstlink + * list entry. + */ putreg32((uint32_t)llhead, dmach->base + SAM_DMACHAN_DSCR_OFFSET); @@ -1245,7 +1247,9 @@ static void sam_dmaterminate(struct sam_dma_s *dmach, int result) putreg32(DMAC_EBC_CHANINTS(dmach->chan), SAM_DMAC_EBCIDR); - /* Disable the channel by writing one to the write-only channel disable register */ + /* Disable the channel by writing one to the write-only channel + * disable register + */ putreg32(DMAC_CHDR_DIS(dmach->chan), SAM_DMAC_CHDR); @@ -1680,7 +1684,9 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) if (dmach->llhead) { - /* Save the callback info. This will be invoked when the DMA completes */ + /* Save the callback info. + * This will be invoked when the DMA completes + */ dmach->callback = callback; dmach->arg = arg; diff --git a/arch/arm/src/sam34/sam_dmac.h b/arch/arm/src/sam34/sam_dmac.h index f6f41b81234..000967e9f99 100644 --- a/arch/arm/src/sam34/sam_dmac.h +++ b/arch/arm/src/sam34/sam_dmac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_DMAC_H #define __ARCH_ARM_SRC_SAM34_SAM_DMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,15 +31,16 @@ #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* DMA ******************************************************************************/ +/* DMA **********************************************************************/ -/* Flags used to characterize the desired DMA channel. The naming convention is that - * one side is the peripheral and the other is memory (however, the interface could still - * be used if, for example, both sides were memory although the naming would be awkward) +/* Flags used to characterize the desired DMA channel. The naming convention + * is that one side is the peripheral and the other is memory (however, the + * interface could still be used if, for example, both sides were memory + * although the naming would be awkward) */ /* Unchange-able properties of the channel */ @@ -73,8 +74,10 @@ # define DMACH_FLAG_PERIPHWIDTH_8BITS (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */ # define DMACH_FLAG_PERIPHWIDTH_16BITS (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */ # define DMACH_FLAG_PERIPHWIDTH_32BITS (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */ + #define DMACH_FLAG_PERIPHINCREMENT (1 << 12) /* Bit 12: Autoincrement peripheral address */ #define DMACH_FLAG_PERIPHCHUNKSIZE (1 << 13) /* Bit 13: Peripheral chunk size */ + # define DMACH_FLAG_PERIPHCHUNKSIZE_1 (0) /* Peripheral chunksize = 1 */ # define DMACH_FLAG_PERIPHCHUNKSIZE_4 DMACH_FLAG_PERIPHCHUNKSIZE /* Peripheral chunksize = 4 */ @@ -89,20 +92,25 @@ # define DMACH_FLAG_MEMWIDTH_8BITS (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */ # define DMACH_FLAG_MEMWIDTH_16BITS (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */ # define DMACH_FLAG_MEMWIDTH_32BITS (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */ + #define DMACH_FLAG_MEMINCREMENT (1 << 22) /* Bit 22: Autoincrement memory address */ #define DMACH_FLAG_MEMCHUNKSIZE (1 << 23) /* Bit 23: Memory chunk size */ + # define DMACH_FLAG_MEMCHUNKSIZE_1 (0) /* Memory chunksize = 1 */ # define DMACH_FLAG_MEMCHUNKSIZE_4 DMACH_FLAG_MEMCHUNKSIZE /* Memory chunksize = 4 */ - /* Bits 24-31: Not used */ -/************************************************************************************ + /* Bits 24-31: Not used */ + +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA + * is selected + */ #ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s @@ -128,15 +136,15 @@ struct sam_dmaregs_s }; #endif -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -147,9 +155,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_dmachannel @@ -249,8 +257,8 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); * * Description: * Cancel the DMA. After sam_dmastop() is called, the DMA channel is - * reset and sam_dmarx/txsetup() must be called before sam_dmastart() can be - * called again + * reset and sam_dmarx/txsetup() must be called before sam_dmastart() can + * be called again * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_emac.h b/arch/arm/src/sam34/sam_emac.h index a36dd934bc1..b9b675e5216 100644 --- a/arch/arm/src/sam34/sam_emac.h +++ b/arch/arm/src/sam34/sam_emac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_emac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_ETHERNET_H #define __ARCH_ARM_SRC_SAM34_SAM_ETHERNET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -32,17 +32,17 @@ #ifdef CONFIG_SAM34_EMAC -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Definitions for use with sam_phy_boardinitialize */ #define EMAC_INTF 0 -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -74,15 +74,16 @@ extern "C" void arm_netinitialize(void); -/************************************************************************************ +/**************************************************************************** * Function: sam_phy_boardinitialize * * Description: - * Some boards require specialized initialization of the PHY before it can be used. - * This may include such things as configuring GPIOs, resetting the PHY, etc. If - * CONFIG_SAM34_PHYINIT is defined in the configuration then the board specific - * logic must provide sam_phyinitialize(); The SAM34 Ethernet driver will call - * this function one time before it first uses the PHY. + * Some boards require specialized initialization of the PHY before it can + * be used. This may include such things as configuring GPIOs, resetting + * the PHY, etc. If CONFIG_SAM34_PHYINIT is defined in the configuration + * then the board specific logic must provide sam_phyinitialize(); The + * SAM34 Ethernet driver will call this function one time before it first + * uses the PHY. * * Input Parameters: * intf - Always zero for now. @@ -92,7 +93,7 @@ void arm_netinitialize(void); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM34_PHYINIT int sam_phy_boardinitialize(int intf); diff --git a/arch/arm/src/sam34/sam_gpio.c b/arch/arm/src/sam34/sam_gpio.c index 797841bbcdd..86f97e15794 100644 --- a/arch/arm/src/sam34/sam_gpio.c +++ b/arch/arm/src/sam34/sam_gpio.c @@ -56,7 +56,10 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO -static const char g_portchar[4] = { 'A', 'B', 'C', 'D' }; +static const char g_portchar[4] = +{ + 'A', 'B', 'C', 'D' +}; #endif /**************************************************************************** @@ -410,6 +413,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, { regval |= pin; } + putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET); regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET); @@ -422,6 +426,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, { regval |= pin; } + putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET); #else @@ -440,6 +445,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, { regval |= pin; } + putreg32(regval, base + SAM_PIO_ABSR_OFFSET); #endif @@ -559,13 +565,14 @@ bool sam_gpioread(gpio_pinset_t pinset) return (regval & pin) != 0; } -/************************************************************************************ +/**************************************************************************** * Function: sam_dumpgpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpgpio(uint32_t pinset, const char *msg) @@ -586,36 +593,53 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n", - getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET), - getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET)); + getreg32(base + SAM_PIO_PSR_OFFSET), + getreg32(base + SAM_PIO_OSR_OFFSET), + getreg32(base + SAM_PIO_IFSR_OFFSET), + getreg32(base + SAM_PIO_ODSR_OFFSET)); gpioinfo(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n", - getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET), - getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET)); + getreg32(base + SAM_PIO_PDSR_OFFSET), + getreg32(base + SAM_PIO_IMR_OFFSET), + getreg32(base + SAM_PIO_ISR_OFFSET), + getreg32(base + SAM_PIO_MDSR_OFFSET)); #if defined(CONFIG_ARCH_CHIP_SAM3U) gpioinfo(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n", - getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET), - getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET)); + getreg32(base + SAM_PIO_ABSR_OFFSET), + getreg32(base + SAM_PIO_SCIFSR_OFFSET), + getreg32(base + SAM_PIO_DIFSR_OFFSET), + getreg32(base + SAM_PIO_IFDGSR_OFFSET)); #elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) gpioinfo(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n", - getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET), - getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET)); + getreg32(base + SAM_PIO_ABCDSR1_OFFSET), + getreg32(base + SAM_PIO_ABCDSR2_OFFSET), + getreg32(base + SAM_PIO_IFSCSR_OFFSET), + getreg32(base + SAM_PIO_PPDSR_OFFSET)); #endif gpioinfo(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n", - getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), - getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET)); + getreg32(base + SAM_PIO_PUSR_OFFSET), + getreg32(base + SAM_PIO_SCDR_OFFSET), + getreg32(base + SAM_PIO_OWSR_OFFSET), + getreg32(base + SAM_PIO_AIMMR_OFFSET)); gpioinfo(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n", - getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET), - getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET)); + getreg32(base + SAM_PIO_ESR_OFFSET), + getreg32(base + SAM_PIO_LSR_OFFSET), + getreg32(base + SAM_PIO_ELSR_OFFSET), + getreg32(base + SAM_PIO_FELLSR_OFFSET)); gpioinfo(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n", - getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET), - getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); + getreg32(base + SAM_PIO_FRLHSR_OFFSET), + getreg32(base + SAM_PIO_LOCKSR_OFFSET), + getreg32(base + SAM_PIO_WPMR_OFFSET), + getreg32(base + SAM_PIO_WPSR_OFFSET)); #if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n", - getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET), - getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET)); + getreg32(base + SAM_PIO_PCMR_OFFSET), + getreg32(base + SAM_PIO_PCIMR_OFFSET), + getreg32(base + SAM_PIO_PCISR_OFFSET), + getreg32(base + SAM_PIO_PCRHR_OFFSET)); #ifdef CONFIG_ARCH_CHIP_SAM4E gpioinfo("SCHMITT: %08x DELAYR:%08x\n", - getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DELAYR_OFFSET)); + getreg32(base + SAM_PIO_SCHMITT_OFFSET), + getreg32(base + SAM_PIO_DELAYR_OFFSET)); #else gpioinfo("SCHMITT: %08x\n", getreg32(base + SAM_PIO_SCHMITT_OFFSET)); diff --git a/arch/arm/src/sam34/sam_gpio.h b/arch/arm/src/sam34/sam_gpio.h index d5b896262a0..3314adebe74 100644 --- a/arch/arm/src/sam34/sam_gpio.h +++ b/arch/arm/src/sam34/sam_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_GPIO_H #define __ARCH_ARM_SRC_SAM34_SAM_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -48,11 +48,11 @@ # error Unrecognized SAM architecture #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ #if defined(CONFIG_SAM34_GPIOA_IRQ) || defined(CONFIG_SAM34_GPIOB_IRQ) || \ defined(CONFIG_SAM34_GPIOC_IRQ) || defined(CONFIG_SAM34_GPIOD_IRQ) || \ @@ -62,9 +62,9 @@ # undef CONFIG_SAM34_GPIO_IRQ #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -77,13 +77,14 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqinitialize * * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM34_GPIO_IRQ void sam_gpioirqinitialize(void); @@ -91,43 +92,43 @@ void sam_gpioirqinitialize(void); # define sam_gpioirqinitialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int sam_configgpio(gpio_pinset_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: sam_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void sam_gpiowrite(gpio_pinset_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioread * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool sam_gpioread(gpio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirq * * Description: * Configure an interrupt for the specified GPIO pin. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM34_GPIO_IRQ void sam_gpioirq(gpio_pinset_t pinset); @@ -135,13 +136,13 @@ void sam_gpioirq(gpio_pinset_t pinset); # define sam_gpioirq(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqenable * * Description: * Enable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM34_GPIO_IRQ void sam_gpioirqenable(int irq); @@ -149,13 +150,13 @@ void sam_gpioirqenable(int irq); # define sam_gpioirqenable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqdisable * * Description: * Disable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM34_GPIO_IRQ void sam_gpioirqdisable(int irq); @@ -163,13 +164,14 @@ void sam_gpioirqdisable(int irq); # define sam_gpioirqdisable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Function: sam_dumpgpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpgpio(uint32_t pinset, const char *msg); diff --git a/arch/arm/src/sam34/sam_gpioirq.c b/arch/arm/src/sam34/sam_gpioirq.c index 099846b3d6d..9d0a4a4f3f6 100644 --- a/arch/arm/src/sam34/sam_gpioirq.c +++ b/arch/arm/src/sam34/sam_gpioirq.c @@ -118,6 +118,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAM34_GPIOB_IRQ if (irq <= SAM_IRQ_PB31) { @@ -126,6 +127,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAM34_GPIOC_IRQ if (irq <= SAM_IRQ_PC31) { @@ -134,6 +136,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAM34_GPIOD_IRQ if (irq <= SAM_IRQ_PD31) { @@ -142,6 +145,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAM34_GPIOE_IRQ if (irq <= SAM_IRQ_PE31) { @@ -150,6 +154,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAM34_GPIOF_IRQ if (irq <= SAM_IRQ_PF31) { @@ -177,7 +182,8 @@ static int sam_gpiointerrupt(uint32_t base, int irq0, void *context) uint32_t bit; int irq; - pending = getreg32(base + SAM_PIO_ISR_OFFSET) & getreg32(base + SAM_PIO_IMR_OFFSET); + pending = getreg32(base + SAM_PIO_ISR_OFFSET) & + getreg32(base + SAM_PIO_IMR_OFFSET); for (bit = 1, irq = irq0; pending != 0; bit <<= 1, irq++) { if ((pending & bit) != 0) @@ -191,6 +197,7 @@ static int sam_gpiointerrupt(uint32_t base, int irq0, void *context) pending &= ~bit; } } + return OK; } @@ -360,13 +367,13 @@ void sam_gpioirqinitialize(void) #endif } -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirq * * Description: * Configure an interrupt for the specified GPIO pin. * - ************************************************************************************/ + ****************************************************************************/ void sam_gpioirq(gpio_pinset_t pinset) { @@ -411,13 +418,13 @@ void sam_gpioirq(gpio_pinset_t pinset) } } -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqenable * * Description: * Enable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void sam_gpioirqenable(int irq) { @@ -428,18 +435,19 @@ void sam_gpioirqenable(int irq) { /* Clear (all) pending interrupts and enable this pin interrupt */ - //(void)getreg32(base + SAM_PIO_ISR_OFFSET); + /* (void)getreg32(base + SAM_PIO_ISR_OFFSET); */ + putreg32((1 << pin), base + SAM_PIO_IER_OFFSET); } } -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqdisable * * Description: * Disable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void sam_gpioirqdisable(int irq) { diff --git a/arch/arm/src/sam34/sam_hsmci.h b/arch/arm/src/sam34/sam_hsmci.h index a3646f1081e..536705783d1 100644 --- a/arch/arm/src/sam34/sam_hsmci.h +++ b/arch/arm/src/sam34/sam_hsmci.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_hsmci.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_HSMCI_H #define __ARCH_ARM_SRC_SAM34_SAM_HSMCI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -32,23 +32,23 @@ #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -59,9 +59,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sdio_initialize @@ -73,7 +73,8 @@ extern "C" * slotno - Not used. * * Returned Value: - * A reference to an SDIO interface structure. NULL is returned on failures. + * A reference to an SDIO interface structure. + * NULL is returned on failures. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_lowputc.c b/arch/arm/src/sam34/sam_lowputc.c index 0bf400ca3ff..fccc567e12f 100644 --- a/arch/arm/src/sam34/sam_lowputc.c +++ b/arch/arm/src/sam34/sam_lowputc.c @@ -54,7 +54,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Configuration **********************************************************/ +/* Configuration ************************************************************/ /* If the USART is not being used as a UART, then it really isn't enabled * for our purposes. @@ -134,9 +134,9 @@ /* Select MCU-specific settings * - * For the SAM3U, SAM3A, SAM3X, SAM4E and SAM4S the USARTs are driven by the - * main clock. (This could also be the MCK/8 or an external clock but - * those options have not yet been necessary). + * For the SAM3U, SAM3A, SAM3X, SAM4E and SAM4S the USARTs are driven by + * the main clock. (This could also be the MCK/8 or an external clock + * but those options have not yet been necessary). * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is * selected by the PBADIVMASK register. */ @@ -295,7 +295,6 @@ void arm_lowputc(char ch) #endif } - /**************************************************************************** * Name: up_putc * @@ -429,8 +428,9 @@ void sam_lowsetup(void) * This may limit BAUD rates for lower USART clocks. */ - putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)), - SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET); + putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / + (SAM_CONSOLE_BAUD << 4)), + SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET); /* Enable receiver & transmitter */ diff --git a/arch/arm/src/sam34/sam_lowputc.h b/arch/arm/src/sam34/sam_lowputc.h index 1fcf48a6e13..a1db7c3b635 100644 --- a/arch/arm/src/sam34/sam_lowputc.h +++ b/arch/arm/src/sam34/sam_lowputc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_lowputc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_LOWPUTC_H #define __ARCH_ARM_SRC_SAM34_SAM_LOWPUTC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,23 +35,23 @@ #include "arm_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -62,19 +62,20 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. + * Called at the very beginning of _start. + * Performs low level initialization including setup of the console UART. + * This UART done early so that the serial console is available for + * debugging very early in the boot sequence. * - ************************************************************************************/ + ****************************************************************************/ void sam_lowsetup(void); diff --git a/arch/arm/src/sam34/sam_mpuinit.h b/arch/arm/src/sam34/sam_mpuinit.h index 4a4a01bd708..d4688f8e38c 100644 --- a/arch/arm/src/sam34/sam_mpuinit.h +++ b/arch/arm/src/sam34/sam_mpuinit.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_mpuinit.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,37 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_MPUINIT_H #define __ARCH_ARM_SRC_SAM34_SAM_MPUINIT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -57,16 +57,16 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_mpuinitialize * * Description: - * Configure the MPU to permit user-space access to only unrestricted SAM3/4 - * resources. + * Configure the MPU to permit user-space access to only unrestricted + * SAM3/4 resources. * ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_periphclks.h b/arch/arm/src/sam34/sam_periphclks.h index cd37d001cf5..77f6027fb02 100644 --- a/arch/arm/src/sam34/sam_periphclks.h +++ b/arch/arm/src/sam34/sam_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAM34_SAM_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -43,23 +43,23 @@ # error Unknown SAM chip #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -70,9 +70,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index e69ab682e97..cad96710b81 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_rtc.c * * Copyright (C) 2014 Gregory Nutt. All rights reserved. @@ -32,11 +32,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -60,10 +60,11 @@ #ifdef CONFIG_RTC -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #ifdef CONFIG_RTC_HIRES # if !defined(CONFIG_SAM34_RTT) @@ -80,9 +81,9 @@ #define RTC_MAGIC 0xdeadbeef -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ /* Callback to use when the alarm expires */ @@ -91,9 +92,9 @@ static alarmcb_t g_alarmcb; struct work_s g_alarmwork; #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /* g_rtc_enabled is set true after the RTC has successfully initialized */ @@ -105,10 +106,11 @@ volatile bool g_rtc_enabled = false; uint32_t g_rtt_offset = 0; #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ -/************************************************************************************ + ****************************************************************************/ + +/**************************************************************************** * Name: rtc_dumpregs * * Description: @@ -120,7 +122,7 @@ uint32_t g_rtt_offset = 0; * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) @@ -140,7 +142,7 @@ static void rtc_dumpregs(FAR const char *msg) # define rtc_dumpregs(msg) #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_dumptime * * Description: @@ -152,7 +154,7 @@ static void rtc_dumpregs(FAR const char *msg) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) @@ -169,7 +171,7 @@ static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) # define rtc_dumptime(tp, msg) #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_bin2bcd * * Description: @@ -181,7 +183,7 @@ static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) * Returned Value: * The value in BCD representation * - ************************************************************************************/ + ****************************************************************************/ static uint32_t rtc_bin2bcd(int value) { @@ -196,7 +198,7 @@ static uint32_t rtc_bin2bcd(int value) return (msbcd << 4) | value; } -/************************************************************************************ +/**************************************************************************** * Name: rtc_bin2bcd * * Description: @@ -208,7 +210,7 @@ static uint32_t rtc_bin2bcd(int value) * Returned Value: * The value in binary representation * - ************************************************************************************/ + ****************************************************************************/ static int rtc_bcd2bin(uint32_t value) { @@ -216,7 +218,7 @@ static int rtc_bcd2bin(uint32_t value) return (int)(tens + (value & 0x0f)); } -/************************************************************************************ +/**************************************************************************** * Name: rtc_worker * * Description: @@ -228,7 +230,7 @@ static int rtc_bcd2bin(uint32_t value) * Returned Value: * Zero (OK) on success; A negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM static void rtc_worker(FAR void *arg) @@ -248,7 +250,7 @@ static void rtc_worker(FAR void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_interrupt * * Description: @@ -261,7 +263,7 @@ static void rtc_worker(FAR void *arg) * Returned Value: * Zero (OK) on success; A negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM static int rtc_interrupt(int irq, void *context, FAR void *arg) @@ -288,7 +290,7 @@ static int rtc_interrupt(int irq, void *context, FAR void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_sync * * Description: @@ -297,11 +299,12 @@ static int rtc_interrupt(int irq, void *context, FAR void *arg) * * Returns value of the TIMR register * - ************************************************************************************/ + ****************************************************************************/ static uint32_t rtc_sync(void) { - uint32_t r0, r1; + uint32_t r0; + uint32_t r1; /* Get start second (stable) */ @@ -322,16 +325,16 @@ static uint32_t rtc_sync(void) return r1; } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_initialize * * Description: - * Initialize the hardware RTC per the selected configuration. This function is - * called once during the OS initialization sequence + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence * * Input Parameters: * None @@ -339,7 +342,7 @@ static uint32_t rtc_sync(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_initialize(void) { @@ -347,9 +350,9 @@ int up_rtc_initialize(void) rtc_dumpregs("On reset"); - /* No clocking setup need be performed. The Real-time Clock is continuously clocked - * at 32768 Hz (SCLK). The Power Management Controller has no effect on RTC - * behavior. + /* No clocking setup need be performed. The Real-time Clock is continuously + * clocked at 32768 Hz (SCLK). The Power Management Controller has no + * effect on RTC behavior. */ /* Set the 24 hour format */ @@ -366,9 +369,9 @@ int up_rtc_initialize(void) irq_attach(SAM_IRQ_RTC, rtc_interrupt, NULL); - /* Should RTC alarm interrupt be enabled at the peripheral? Let's assume so - * for now. Let's say yes if the time is valid and a valid alarm has been - * programmed. + /* Should RTC alarm interrupt be enabled at the peripheral? Let's assume + * so for now. Let's say yes if the time is valid and a valid alarm has + * been programmed. */ if (g_rtc_enabled && (ver & (RTC_VER_NVTIMALR | RTC_VER_NVCALALR)) == 0) @@ -397,7 +400,8 @@ int up_rtc_initialize(void) /* Disable ints, set prescaler, start counter */ - putreg32(RTT_MR_RTPRES(32768/CONFIG_RTC_FREQUENCY) | RTT_MR_RTTRST, SAM_RTT_MR); + putreg32(RTT_MR_RTPRES(32768 / CONFIG_RTC_FREQUENCY) | + RTT_MR_RTTRST, SAM_RTT_MR); /* wait for a second tick to get the RTT offset. * Interrupts are assumed to still be off at this point. @@ -405,8 +409,8 @@ int up_rtc_initialize(void) rtc_sync(); - /* Probably safe to read the RTT_VR register now since the clock just ticked, - * but we'll be careful anyway. + /* Probably safe to read the RTT_VR register now since the clock just + * ticked, but we'll be careful anyway. */ do @@ -420,20 +424,20 @@ int up_rtc_initialize(void) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_getdatetime * * Description: * Get the current date and time from the date/time RTC. This interface * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME - * are selected (and CONFIG_RTC_HIRES is not). + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. That - * sub-second accuracy is lost in this interface. However, since the system time - * is reinitialized on each power-up/reset, there will be no timing inaccuracy in - * the long run. + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is lost in this interface. However, since the + * system time is reinitialized on each power-up/reset, there will be no + * timing inaccuracy in the long run. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -441,7 +445,7 @@ int up_rtc_initialize(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_getdatetime(FAR struct tm *tp) { @@ -451,9 +455,9 @@ int up_rtc_getdatetime(FAR struct tm *tp) uint32_t year; uint32_t tmp; - /* Sample the data time registers. There is a race condition here... If we sample - * the time just before midnight on December 31, the date could be wrong because - * the day rolled over while were sampling. + /* Sample the data time registers. There is a race condition here... If + * we sample the time just before midnight on December 31, the date could + * be wrong because the day rolled over while were sampling. */ do @@ -514,12 +518,12 @@ int up_rtc_getdatetime(FAR struct tm *tp) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_settime * * Description: - * Set the RTC to the provided time. All RTC implementations must be able to - * set their time based on a standard timespec. + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. * * Input Parameters: * tp - the time to use @@ -527,7 +531,7 @@ int up_rtc_getdatetime(FAR struct tm *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_settime(FAR const struct timespec *tp) { @@ -538,7 +542,9 @@ int up_rtc_settime(FAR const struct timespec *tp) uint32_t cent; uint32_t year; - /* Break out the time values (note that the time is set only to units of seconds) */ + /* Break out the time values (note that the time is set only to units of + * seconds) + */ gmtime_r(&tp->tv_sec, &newtime); rtc_dumptime(&newtime, "Setting time"); @@ -555,9 +561,12 @@ int up_rtc_settime(FAR const struct timespec *tp) * *To allow for leap seconds. But these never actually happen. */ - timr = (rtc_bin2bcd(newtime.tm_sec) << RTC_TIMR_SEC_SHIFT) & RTC_TIMR_SEC_MASK; - timr |= (rtc_bin2bcd(newtime.tm_min) << RTC_TIMR_MIN_SHIFT) & RTC_TIMR_MIN_MASK; - timr |= (rtc_bin2bcd(newtime.tm_hour) << RTC_TIMR_HOUR_SHIFT) & RTC_TIMR_HOUR_MASK; + timr = (rtc_bin2bcd(newtime.tm_sec) << RTC_TIMR_SEC_SHIFT) & + RTC_TIMR_SEC_MASK; + timr |= (rtc_bin2bcd(newtime.tm_min) << RTC_TIMR_MIN_SHIFT) & + RTC_TIMR_MIN_MASK; + timr |= (rtc_bin2bcd(newtime.tm_hour) << RTC_TIMR_HOUR_SHIFT) & + RTC_TIMR_HOUR_MASK; /* Convert the struct tm format to RTC date register fields. * @@ -572,15 +581,20 @@ int up_rtc_settime(FAR const struct timespec *tp) * **Day of the week is not supported. Set to Monday. */ - calr = (rtc_bin2bcd(newtime.tm_mday) << RTC_CALR_DATE_SHIFT) & RTC_CALR_DATE_MASK; - calr |= (rtc_bin2bcd(1) << RTC_CALR_DAY_SHIFT) & RTC_CALR_DAY_MASK; - calr |= (rtc_bin2bcd(newtime.tm_mon+1) << RTC_CALR_MONTH_SHIFT) & RTC_CALR_MONTH_MASK; + calr = (rtc_bin2bcd(newtime.tm_mday) << RTC_CALR_DATE_SHIFT) & + RTC_CALR_DATE_MASK; + calr |= (rtc_bin2bcd(1) << RTC_CALR_DAY_SHIFT) & + RTC_CALR_DAY_MASK; + calr |= (rtc_bin2bcd(newtime.tm_mon + 1) << RTC_CALR_MONTH_SHIFT) & + RTC_CALR_MONTH_MASK; cent = newtime.tm_year / 100 + 19; year = newtime.tm_year % 100; - calr |= (rtc_bin2bcd(year) << RTC_CALR_YEAR_SHIFT) & RTC_CALR_YEAR_MASK; - calr |= (rtc_bin2bcd(cent) << RTC_CALR_CENT_SHIFT) & RTC_CALR_CENT_MASK; + calr |= (rtc_bin2bcd(year) << RTC_CALR_YEAR_SHIFT) & + RTC_CALR_YEAR_MASK; + calr |= (rtc_bin2bcd(cent) << RTC_CALR_CENT_SHIFT) & + RTC_CALR_CENT_MASK; /* Stop RTC time and date counting */ @@ -618,18 +632,20 @@ int up_rtc_settime(FAR const struct timespec *tp) /* The RTC should now be enabled */ - g_rtc_enabled = ((getreg32(SAM_RTC_VER) & (RTC_VER_NVTIM | RTC_VER_NVCAL)) == 0); + g_rtc_enabled = ((getreg32(SAM_RTC_VER) & (RTC_VER_NVTIM | + RTC_VER_NVCAL)) == 0); DEBUGASSERT(g_rtc_enabled); rtc_dumpregs("New time setting"); return OK; } -/************************************************************************************ +/**************************************************************************** * Name: sam_rtc_setalarm * * Description: - * Set up an alarm. Up to two alarms can be supported (ALARM A and ALARM B). + * Set up an alarm. Up to two alarms can be supported + * (ALARM A and ALARM B). * * Input Parameters: * tp - the time to set the alarm @@ -638,7 +654,7 @@ int up_rtc_settime(FAR const struct timespec *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) @@ -681,9 +697,12 @@ int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) * *To allow for leap seconds. But these never actually happen. */ - timalr = (rtc_bin2bcd(newalarm.tm_sec) << RTC_TIMALR_SEC_SHIFT) & RTC_TIMALR_SEC_MASK; - timalr |= (rtc_bin2bcd(newalarm.tm_min) << RTC_TIMALR_MIN_SHIFT) & RTC_TIMALR_MIN_MASK; - timalr |= (rtc_bin2bcd(newalarm.tm_hour) << RTC_TIMALR_HOUR_SHIFT) & RTC_TIMALR_HOUR_MASK; + timalr = (rtc_bin2bcd(newalarm.tm_sec) << RTC_TIMALR_SEC_SHIFT) & + RTC_TIMALR_SEC_MASK; + timalr |= (rtc_bin2bcd(newalarm.tm_min) << RTC_TIMALR_MIN_SHIFT) & + RTC_TIMALR_MIN_MASK; + timalr |= (rtc_bin2bcd(newalarm.tm_hour) << RTC_TIMALR_HOUR_SHIFT) & + RTC_TIMALR_HOUR_MASK; timalr |= (RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN); /* Convert the struct tm format to RTC date register fields. @@ -699,8 +718,12 @@ int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) * **Day of the week is not supported */ - calalr = (rtc_bin2bcd(newalarm.tm_mday) << RTC_CALALR_DATE_SHIFT) & RTC_CALALR_DATE_MASK; - calalr |= (rtc_bin2bcd(newalarm.tm_mon+1) << RTC_CALALR_MONTH_SHIFT) & RTC_CALALR_MONTH_MASK; + calalr = (rtc_bin2bcd(newalarm.tm_mday) << + RTC_CALALR_DATE_SHIFT) & + RTC_CALALR_DATE_MASK; + calalr |= (rtc_bin2bcd(newalarm.tm_mon + 1) << + RTC_CALALR_MONTH_SHIFT) & + RTC_CALALR_MONTH_MASK; calalr |= (RTC_CALALR_MTHEN | RTC_CALALR_DATEEN); /* Set the new date */ @@ -727,13 +750,13 @@ int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) } #endif - -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_gettime * * Description: - * Get the current time from the high resolution RTC clock/counter. This interface - * is only supported by the high-resolution RTC/counter hardware implementation. + * Get the current time from the high resolution RTC clock/counter. + * This interface is only supported by the high-resolution RTC/counter + * hardware implementation. * It is used to replace the system timer. * * Input Parameters: @@ -742,14 +765,16 @@ int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_HIRES) && defined (CONFIG_SAM34_RTT) int up_rtc_gettime(FAR struct timespec *tp) { /* This is a hack to emulate a high resolution rtc using the rtt */ - uint32_t rtc_cal, rtc_tim, rtt_val; + uint32_t rtc_cal; + uint32_t rtc_tim; + uint32_t rtt_val; struct tm t; do @@ -762,18 +787,25 @@ int up_rtc_gettime(FAR struct timespec *tp) rtc_tim != getreg32(SAM_RTC_TIMR) || rtt_val != getreg32(SAM_RTT_VR)); - t.tm_sec = rtc_bcd2bin((rtc_tim & RTC_TIMR_SEC_MASK) >> RTC_TIMR_SEC_SHIFT); - t.tm_min = rtc_bcd2bin((rtc_tim & RTC_TIMR_MIN_MASK) >> RTC_TIMR_MIN_SHIFT); - t.tm_hour = rtc_bcd2bin((rtc_tim & RTC_TIMR_HOUR_MASK) >> RTC_TIMR_HOUR_SHIFT); - t.tm_mday = rtc_bcd2bin((rtc_cal & RTC_CALR_DATE_MASK) >> RTC_CALR_DATE_SHIFT); - t.tm_mon = rtc_bcd2bin((rtc_cal & RTC_CALR_MONTH_MASK) >> RTC_CALR_MONTH_SHIFT); - t.tm_year = (rtc_bcd2bin((rtc_cal & RTC_CALR_CENT_MASK) >> RTC_CALR_CENT_SHIFT) * 100) - + rtc_bcd2bin((rtc_cal & RTC_CALR_YEAR_MASK) >> RTC_CALR_YEAR_SHIFT) + t.tm_sec = rtc_bcd2bin((rtc_tim & RTC_TIMR_SEC_MASK) >> + RTC_TIMR_SEC_SHIFT); + t.tm_min = rtc_bcd2bin((rtc_tim & RTC_TIMR_MIN_MASK) >> + RTC_TIMR_MIN_SHIFT); + t.tm_hour = rtc_bcd2bin((rtc_tim & RTC_TIMR_HOUR_MASK) >> + RTC_TIMR_HOUR_SHIFT); + t.tm_mday = rtc_bcd2bin((rtc_cal & RTC_CALR_DATE_MASK) >> + RTC_CALR_DATE_SHIFT); + t.tm_mon = rtc_bcd2bin((rtc_cal & RTC_CALR_MONTH_MASK) >> + RTC_CALR_MONTH_SHIFT); + t.tm_year = (rtc_bcd2bin((rtc_cal & RTC_CALR_CENT_MASK) >> + RTC_CALR_CENT_SHIFT) * 100) + + rtc_bcd2bin((rtc_cal & RTC_CALR_YEAR_MASK) >> + RTC_CALR_YEAR_SHIFT) - 1900; tp->tv_sec = mktime(&t); - tp->tv_nsec = (((rtt_val-g_rtt_offset) & (CONFIG_RTC_FREQUENCY-1)) * 1000000000ULL) / - CONFIG_RTC_FREQUENCY; + tp->tv_nsec = (((rtt_val - g_rtt_offset) & (CONFIG_RTC_FREQUENCY - 1)) * + 1000000000ull) / CONFIG_RTC_FREQUENCY; return OK; } diff --git a/arch/arm/src/sam34/sam_rtc.h b/arch/arm/src/sam34/sam_rtc.h index 93d6676decf..27ef853beed 100644 --- a/arch/arm/src/sam34/sam_rtc.h +++ b/arch/arm/src/sam34/sam_rtc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_rtc.h * * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. @@ -32,11 +32,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_RTC_H #define __ARCH_ARM_SRC_SAM34_SAM_RTC_H @@ -46,13 +46,13 @@ #include "chip.h" #include "hardware/sam_rtc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -60,9 +60,9 @@ typedef void (*alarmcb_t)(void); -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -73,11 +73,11 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_rtc_setalarm * * Description: @@ -90,7 +90,7 @@ extern "C" * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM struct timespec; diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index 8bf78c16afe..b4cbc9f256d 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -60,11 +60,13 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Clocking *****************************************************************/ #if defined(CONFIG_RTC_HIRES) && defined (CONFIG_SAM34_RTC) # define RTT_PRES (32768/CONFIG_RTC_FREQUENCY) #else + /* TODO: Allow prescaler selection. */ # define RTT_PRES 1 #endif @@ -81,6 +83,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * timer_lowerhalf_s structure. @@ -104,6 +107,7 @@ struct sam34_lowerhalf_s /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Register operations ******************************************************/ #ifdef CONFIG_SAM34_RTT_REGDEBUG @@ -134,6 +138,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, /**************************************************************************** * Private Data ****************************************************************************/ + /* "Lower half" driver methods */ static const struct timer_ops_s g_tcops = @@ -196,8 +201,8 @@ static uint32_t sam34_getreg(uint32_t addr) uint32_t val = getreg32(addr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. */ if (addr == prevaddr && val == preval) @@ -223,7 +228,7 @@ static uint32_t sam34_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - tmrinfo("[repeats %d more times]\n", count-3); + tmrinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -304,7 +309,8 @@ static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) vr = sam34_readvr(); priv->clkticks = - ((uint64_t)(priv->adjustment + priv->timeout)) * RTT_FCLK / 1000000; + ((uint64_t)(priv->adjustment + priv->timeout)) * + RTT_FCLK / 1000000; /* Subtract off how late we are, but only up to half an interval. * TODO calculate lost ticks? @@ -319,7 +325,7 @@ static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) /* Set next interval interval. */ priv->val = vr + priv->clkticks; - sam34_putreg(priv->val-1, SAM_RTT_AR); + sam34_putreg(priv->val - 1, SAM_RTT_AR); /* Re-enable alarm */ @@ -351,8 +357,8 @@ static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) * Start the timer, resetting the time to the current timeout, * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -387,8 +393,8 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) vr = 0; /* we're going to reset the counter */ #endif - priv->val = vr + priv->clkticks; /* value at end of interval */ - sam34_putreg(priv->val-1, SAM_RTT_AR); /* Set interval */ + priv->val = vr + priv->clkticks; /* value at end of interval */ + sam34_putreg(priv->val - 1, SAM_RTT_AR); /* Set interval */ if (priv->callback) { @@ -414,8 +420,8 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) * Stop the timer * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -452,8 +458,8 @@ static int sam34_stop(FAR struct timer_lowerhalf_s *lower) * Get the current timer status * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * status - The location to return the status information. * * Returned Value: @@ -488,7 +494,8 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ - status->timeleft = 1000000ULL*(sam34_getreg(SAM_RTT_AR) - sam34_readvr())/RTT_FCLK; + status->timeleft = 1000000ULL*(sam34_getreg(SAM_RTT_AR) - + sam34_readvr()) / RTT_FCLK; tmrinfo(" flags : %08x\n", status->flags); tmrinfo(" timeout : %d\n", status->timeout); @@ -503,8 +510,8 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, * Set a new timeout value (and reset the timer) * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * timeout - The new timeout value in milliseconds. * * Returned Value: @@ -552,8 +559,8 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, * Call this user provided timeout callback. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * callback - The new timer expiration function pointer. If this * function pointer is NULL, then the reset-on-expiration * behavior is restored, @@ -592,8 +599,8 @@ static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower, * are forwarded to the lower half driver through this method. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * cmd - The ioctl command value * arg - The optional argument that accompanies the 'cmd'. The * interpretation of this argument depends on the particular diff --git a/arch/arm/src/sam34/sam_rtt.h b/arch/arm/src/sam34/sam_rtt.h index 325c25ce8c6..43965e9cc08 100644 --- a/arch/arm/src/sam34/sam_rtt.h +++ b/arch/arm/src/sam34/sam_rtt.h @@ -64,7 +64,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #if defined(CONFIG_SAM34_RTT) @@ -89,7 +89,6 @@ void sam_rttinitialize(FAR const char *devpath); #endif // CONFIG_SAM34_RTT - #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/sam34/sam_spi.h b/arch/arm/src/sam34/sam_spi.h index 28739aa381f..5cbaa563967 100644 --- a/arch/arm/src/sam34/sam_spi.h +++ b/arch/arm/src/sam34/sam_spi.h @@ -131,7 +131,7 @@ struct spi_dev_s *sam_spibus_initialize(int port); * 1. Provide logic in sam_boardinitialize() to configure SPI chip select * pins. * 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in - * our board-specific logic. These functions will perform chip selection + * our board-specific logic. These functions will perform chip selection * and status operations using PIOs in the way your board is configured. * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide * sam_spi[0|1]cmddata() functions in your board-specific logic. This @@ -139,8 +139,8 @@ struct spi_dev_s *sam_spibus_initialize(int port); * the way your board is configured. * 3. Add a call to sam_spibus_initialize() in your low level application * initialization logic - * 4. The handle returned by sam_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by sam_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * diff --git a/arch/arm/src/sam34/sam_start.h b/arch/arm/src/sam34/sam_start.h index 42293150700..16cf53fff99 100644 --- a/arch/arm/src/sam34/sam_start.h +++ b/arch/arm/src/sam34/sam_start.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_START_H #define __ARCH_ARM_SRC_SAM34_SAM_START_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_boardinitialize * * Description: - * All SAM3/4 architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * All SAM3/4 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after + * clocking and memory have been configured but before caches have been + * enabled and before any devices have been initialized. * - ************************************************************************************/ + ****************************************************************************/ void sam_boardinitialize(void); diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index e6626477b97..6cc6014504a 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -63,6 +63,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_DEBUG_TIMER_INFO @@ -79,6 +80,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * timer_lowerhalf_s structure. @@ -103,6 +105,7 @@ struct sam34_lowerhalf_s /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Register operations ******************************************************/ #ifdef CONFIG_SAM34_TC_REGDEBUG @@ -133,6 +136,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, /**************************************************************************** * Private Data ****************************************************************************/ + /* "Lower half" driver methods */ static const struct timer_ops_s g_tcops = @@ -176,8 +180,8 @@ static uint32_t sam34_getreg(uint32_t addr) uint32_t val = getreg32(addr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. */ if (addr == prevaddr && val == preval) @@ -203,7 +207,7 @@ static uint32_t sam34_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - tmrinfo("[repeats %d more times]\n", count-3); + tmrinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -257,7 +261,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr) static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) { - FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0]; + FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq - SAM_IRQ_TC0]; tmrinfo("Entry\n"); DEBUGASSERT((irq >= SAM_IRQ_TC0) && (irq <= SAM_IRQ_TC5)); @@ -276,13 +280,16 @@ static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) { /* Calculate new ticks / dither adjustment */ - priv->clkticks = ((uint64_t)(priv->adjustment + priv->timeout))*TC_FCLK / 1000000; + priv->clkticks = ((uint64_t)(priv->adjustment + priv->timeout)) * + TC_FCLK / 1000000; - /* Set next interval interval. TODO: make sure the interval is not so soon it will be missed! */ + /* Set next interval interval. + * TODO: make sure the interval is not so soon it will be missed! + */ sam34_putreg(priv->clkticks, priv->base + SAM_TC_RC_OFFSET); - timeout = (1000000ULL * priv->clkticks) / TC_FCLK; /* truncated timeout */ + timeout = (1000000ULL * priv->clkticks) / TC_FCLK; /* truncated timeout */ priv->adjustment = (priv->adjustment + priv->timeout) - timeout; /* truncated time to be added to next interval (dither) */ } else @@ -306,8 +313,8 @@ static int sam34_interrupt(int irq, FAR void *context, FAR void *arg) * Start the timer, resetting the time to the current timeout, * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -362,8 +369,8 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) * Stop the timer * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -397,8 +404,8 @@ static int sam34_stop(FAR struct timer_lowerhalf_s *lower) * Get the current timer status * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * status - The location to return the status information. * * Returned Value: @@ -450,8 +457,8 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, * Set a new timeout value (and reset the timer) * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * timeout - The new timeout value in milliseconds. * * Returned Value: @@ -500,8 +507,8 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, * Call this user provided timeout callback. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * callback - The new timer expiration function pointer. If this * function pointer is NULL, then the reset-on-expiration * behavior is restored, @@ -526,8 +533,8 @@ static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower, /* Save the new callback and its argument */ - priv->callback = callback; - priv->arg = arg; + priv->callback = callback; + priv->arg = arg; leave_critical_section(flags); } @@ -540,8 +547,8 @@ static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower, * are forwarded to the lower half driver through this method. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * cmd - The ioctl command value * arg - The optional argument that accompanies the 'cmd'. The * interpretation of this argument depends on the particular @@ -587,7 +594,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, void sam_tcinitialize(FAR const char *devpath, int irq) { - FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0]; + FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq - SAM_IRQ_TC0]; tmrinfo("Entry: devpath=%s\n", devpath); DEBUGASSERT((irq >= SAM_IRQ_TC0) && (irq <= SAM_IRQ_TC5)); diff --git a/arch/arm/src/sam34/sam_tc.h b/arch/arm/src/sam34/sam_tc.h index 7ae228e882f..ccf4335a67d 100644 --- a/arch/arm/src/sam34/sam_tc.h +++ b/arch/arm/src/sam34/sam_tc.h @@ -64,7 +64,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/sam34/sam_timerisr.c b/arch/arm/src/sam34/sam_timerisr.c index a3f5439a8d0..4d85bceda30 100644 --- a/arch/arm/src/sam34/sam_timerisr.c +++ b/arch/arm/src/sam34/sam_timerisr.c @@ -40,6 +40,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Select MCU-specific settings * * For the SAM3U, SAM3A, and SAM3X, Systick is driven by the main clock diff --git a/arch/arm/src/sam34/sam_twi.h b/arch/arm/src/sam34/sam_twi.h index a5b57cd3fec..4148852d6d9 100644 --- a/arch/arm/src/sam34/sam_twi.h +++ b/arch/arm/src/sam34/sam_twi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_twi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_TWI_H #define __ARCH_ARM_SRC_SAM34_SAM_TWI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include diff --git a/arch/arm/src/sam34/sam_udp.h b/arch/arm/src/sam34/sam_udp.h index 9d2f695cdcf..e2c114b7060 100644 --- a/arch/arm/src/sam34/sam_udp.h +++ b/arch/arm/src/sam34/sam_udp.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_udp.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_UDP_H #define __ARCH_ARM_SRC_SAM34_SAM_UDP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -32,9 +32,9 @@ #include "chip.h" #include "hardware/sam_udp.h" -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -47,24 +47,27 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_udp_suspend * * Description: * Board logic must provide the sam_udp_suspend logic if the UDP driver is - * used. This function is called whenever the USB enters or leaves suspend mode. + * used. This function is called whenever the USB enters or leaves suspend + * mode. * - * When 'resume' is false, this function call provides an opportunity to perform - * board-specific power-saving actions so that less power is consumed while the - * USB is suspended. + * When 'resume' is false, this function call provides an opportunity to + * perform board-specific power-saving actions so that less power is + * consumed while the USB is suspended. * - * Certain power-saving operations are performed by the UDP driver when it enters - * suspend mode: The USB device peripheral clocks are be switched off. MCK and - * UDPCK are switched off and the USB transceiver is disabled. + * Certain power-saving operations are performed by the UDP driver when it + * enters suspend mode: The USB device peripheral clocks are be switched + * off. + * MCK and UDPCK are switched off and the USB transceiver is disabled. * - * When 'resume' is true, normal clocking and operations must all be restored. + * When 'resume' is true, normal clocking and operations must all be + * restored. * - ************************************************************************************/ + ****************************************************************************/ void sam_udp_suspend(FAR struct usbdev_s *dev, bool resume); diff --git a/arch/arm/src/sam34/sam_userspace.h b/arch/arm/src/sam34/sam_userspace.h index 208863ad2e1..892ccf8962a 100644 --- a/arch/arm/src/sam34/sam_userspace.h +++ b/arch/arm/src/sam34/sam_userspace.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sam34/sam_userspace.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_SAM_USERSPACE_H #define __ARCH_ARM_SRC_SAM34_SAM_USERSPACE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,23 +35,23 @@ #include "arm_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -62,9 +62,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_userspace diff --git a/arch/arm/src/sam34/sam_wdt.h b/arch/arm/src/sam34/sam_wdt.h index ab421e9fd6a..a6371776d7a 100644 --- a/arch/arm/src/sam34/sam_wdt.h +++ b/arch/arm/src/sam34/sam_wdt.h @@ -64,7 +64,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/sama5/chip.h b/arch/arm/src/sama5/chip.h index 34f2e80f189..c17a343b342 100644 --- a/arch/arm/src/sama5/chip.h +++ b/arch/arm/src/sama5/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_CHIP_H #define __ARCH_ARM_SRC_SAMA5_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,12 +33,12 @@ #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it to provide the - * address of the L2CC-PL310 implementation. +/* arch/arm/src/armv7-a/l2cc_pl310.h includes this file and expects it to + * provide the address of the L2CC-PL310 implementation. */ #define L2CC_VBASE SAM_L2CC_VSECTION diff --git a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h index bc42c6af480..dc11879fd3a 100644 --- a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h +++ b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Decimal configuration values may exceed 2Gb and, hence, overflow to negative - * values unless we force them to unsigned long: +/* Decimal configuration values may exceed 2Gb and, hence, overflow to + * negative values unless we force them to unsigned long: */ #define __CONCAT(a,b) a ## b @@ -180,7 +180,7 @@ * are not known apriori and must be specified with configuration settings. */ - /* 0x00000000-0x0fffffff: Internal Memories */ + /* 0x00000000-0x0fffffff: Internal Memories */ #define SAM_ROM_SIZE (256*1024) /* 0x00000000-0x0003ffff: ROM */ #ifdef CONFIG_ARMV7A_L2CC_PL310 # define SAM_SRAMREMAP_SIZE (128*1024) /* 0x00000000-0x0001ffff: Remapped ISRAM0 */ @@ -376,16 +376,16 @@ /* SAMA5 Virtual (mapped) Memory Map * * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it depends - * on some the virtual address definitions provided above. + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. */ #include /* SAMA5 Virtual (mapped) Memory Map. These are the mappings that will * be created if the page table lies in RAM. If the platform has another, - * read-only, pre-initialized page table (perhaps in ROM), then the board.h - * file must provide these definitions. + * read-only, pre-initialized page table (perhaps in ROM), then the + * board.h file must provide these definitions. */ #ifndef CONFIG_ARCH_ROMPGTABLE @@ -633,7 +633,8 @@ * page table will be squeezed into the end of internal SRAM in this * case. * - * Or... the user may specify the address of the page table explicitly be defining + * Or... + * the user may specify the address of the page table explicitly be defining * PGTABLE_BASE_VADDR and PGTABLE_BASE_PADDR in the board.h file. */ @@ -643,32 +644,32 @@ #if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR) - /* Sanity check.. if one is undefined, both should be undefined */ +/* Sanity check.. if one is undefined, both should be undefined */ # if defined(PGTABLE_BASE_PADDR) || defined(PGTABLE_BASE_VADDR) # error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined" # endif - /* A sanity check, if the configuration says that the page table is read-only - * and pre-initialized (maybe ROM), then it should have also defined both of - * the page table base addresses. - */ +/* A sanity check, if the configuration says that the page table is read-only + * and pre-initialized (maybe ROM), then it should have also defined both of + * the page table base addresses. + */ # ifdef CONFIG_ARCH_ROMPGTABLE # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif - /* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h - * - * We must declare the page table at the bottom or at the top of internal - * SRAM. We pick the bottom of internal SRAM *unless* there are vectors - * in the way at that position. - */ +/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory + * map probably do not apply because paging logic will probably partition + * the SRAM section differently. In particular, if the page table is located + * at the end of SRAM, then the virtual page table address defined below + * will probably be in error. In that case PGTABLE_BASE_VADDR is defined + * in the file mmu.h + * + * We must declare the page table at the bottom or at the top of internal + * SRAM. We pick the bottom of internal SRAM *unless* there are vectors + * in the way at that position. + */ # if defined(CONFIG_SAMA5_BOOT_ISRAM) && defined(CONFIG_ARCH_LOWVECTORS) @@ -709,10 +710,10 @@ # else /* CONFIG_SAMA5_BOOT_ISRAM && CONFIG_ARCH_LOWVECTORS */ - /* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, perhaps - * elsewhere in internal SRAM). The page table will then be positioned at - * the first 16Kb of ISRAM0. - */ +/* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, + * perhaps elsewhere in internal SRAM). The page table will then be + * positioned at the first 16Kb of ISRAM0. + */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR # ifndef CONFIG_PAGING @@ -727,15 +728,15 @@ # endif /* CONFIG_SAMA5_BOOT_ISRAM && CONFIG_ARCH_LOWVECTORS */ - /* In either case, the page table lies in ISRAM. If ISRAM is not the - * primary RAM region, then we will need to set-up a special mapping for - * the page table at boot time. - */ +/* In either case, the page table lies in ISRAM. If ISRAM is not the + * primary RAM region, then we will need to set-up a special mapping for + * the page table at boot time. + */ # if defined(CONFIG_BOOT_RUNFROMFLASH) - /* If we are running from FLASH, then the primary memory region is - * given by NUTTX_RAM_PADDR. - */ +/* If we are running from FLASH, then the primary memory region is + * given by NUTTX_RAM_PADDR. + */ # if NUTTX_RAM_PADDR != SAM_ISRAM_PSECTION # define ARMV7A_PGTABLE_MAPPING 1 @@ -751,7 +752,7 @@ #else /* !PGTABLE_BASE_PADDR || !PGTABLE_BASE_VADDR */ - /* Sanity check.. if one is defined, both should be defined */ +/* Sanity check.. if one is defined, both should be defined */ # if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR) # error "One of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is undefined" @@ -774,10 +775,10 @@ /* Level 2 Page table start addresses. * - * 16Kb of memory is reserved hold the page table for the virtual mappings. A - * portion of this table is not accessible in the virtual address space (for - * normal operation). There is this large whole in the physcal address space - * for which there will never be level 1 mappings: + * 16Kb of memory is reserved hold the page table for the virtual mappings. + * A portion of this table is not accessible in the virtual address space + * (for normal operation). There is this large whole in the physcal address + * space for which there will never be level 1 mappings: * * 0x80000000-0xefffffff: Undefined (1.75 GB) * @@ -848,7 +849,8 @@ * * SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM * SAM_VECTOR_VSRAM - Virtual address of vector table in SRAM - * SAM_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000) + * SAM_VECTOR_VADDR - Virtual address of vector table + * (0x00000000 or 0xffff0000) */ #define VECTOR_TABLE_SIZE 0x00010000 @@ -872,12 +874,12 @@ #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_MEMORYMAP_H */ diff --git a/arch/arm/src/sama5/hardware/_sama5d2x_pio.h b/arch/arm/src/sama5/hardware/_sama5d2x_pio.h index 9c29d3d8211..09e024cb3c5 100644 --- a/arch/arm/src/sama5/hardware/_sama5d2x_pio.h +++ b/arch/arm/src/sama5/hardware/_sama5d2x_pio.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/_sama5d2x_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PIO_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PIO_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* Misc Helper Definitions **************************************************************/ + ****************************************************************************/ + +/* Misc Helper Definitions **************************************************/ #define PIOA (0) #define PIOB (1) @@ -41,7 +42,7 @@ #define PIOD (3) #define PIOE (4) -/* PIO register offsets *****************************************************************/ +/* PIO register offsets *****************************************************/ #define SAM_PIO_IOGROUP_OFFSET(n) (0x0000 + ((n) << 6)) # define SAM_PIO_IOGROUPA_OFFSET 0x0000 @@ -98,7 +99,7 @@ #define SAM_SPIO_WPMR_OFFSET 0x15e0 /* Secure PIO Write Protection Mode Register */ #define SAM_SPIO_WPSR_OFFSET 0x15e4 /* Secure PIO Write Protection Status Register */ -/* PIO register addresses ***************************************************************/ +/* PIO register addresses ***************************************************/ #define SAM_PIO_IOGROUP_VBASE(n) (SAM_PIO_VBASE+SAM_PIO_IOGROUP_OFFSET(n)) # define SAM_PIO_IOGROUPA_VBASE (SAM_PIO_VBASE+SAM_PIO_IOGROUPA_OFFSET) @@ -235,7 +236,7 @@ #define SAM_SPIO_WPMR (SAM_PIO_VBASE+SAM_SPIO_WPMR_OFFSET) #define SAM_SPIO_WPSR (SAM_PIO_VBASE+SAM_SPIO_WPSR_OFFSET) -/* PIO register bit definitions *********************************************************/ +/* PIO register bit definitions *********************************************/ /* Common bit definitions for many IO registers (exceptions follow) */ @@ -254,6 +255,7 @@ # define PIO_CFGR_FUNC_PERIPHE (5 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral E */ # define PIO_CFGR_FUNC_PERIPHF (6 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral F */ # define PIO_CFGR_FUNC_PERIPHG (7 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral G */ + #define PIO_CFGR_DIR (1 << 8) /* Bit 8: Direction */ # define PIO_CFGR_DIR_INPUT (0) /* 0=Input */ # define PIO_CFGR_DIR_OUTPUT (1 << 8) /* 1=Output */ @@ -268,6 +270,7 @@ # define PIO_CFGR_DRVSTR_LOW (0 << PIO_CFGR_DRVSTR_SHIFT) /* Low drive */ # define PIO_CFGR_DRVSTR_MED (2 << PIO_CFGR_DRVSTR_SHIFT) /* Medium drive */ # define PIO_CFGR_DRVSTR_HIGH (3 << PIO_CFGR_DRVSTR_SHIFT) /* High drive */ + #define PIO_CFGR_EVTSEL_SHIFT (24) /* Bits 24-26: Event Selection */ #define PIO_CFGR_EVTSEL_MASK (7 << PIO_CFGR_EVTSEL_SHIFT) # define PIO_CFGR_EVTSEL_FALLING (0 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on input falling edge */ @@ -275,6 +278,7 @@ # define PIO_CFGR_EVTSEL_BOTH (2 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on input both edge */ # define PIO_CFGR_EVTSEL_LOW (3 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on low level input */ # define PIO_CFGR_EVTSEL_HIGH (4 << PIO_CFGR_EVTSEL_SHIFT) /* Event detection on high level input */ + #define PIO_CFGR_PCFS (1 << 29) /* Bit 29: Physical Configuration Freeze Status */ #define PIO_CFGR_ICFS (1 << 30) /* Bit 30: Interrupt Configuration Freeze Status */ @@ -286,7 +290,9 @@ #define PIO_IOFR_FRZKEY_MASK (0x00ffffff << PIO_IOFR_FRZKEY_SHIFT) # define PIO_IOFR_FRZKEY (0x00494F46 << PIO_IOFR_FRZKEY_SHIFT) /* ""IOF" */ -/* PIO Write Protection Mode Register and Secure PIO Write Protection Mode Register */ +/* PIO Write Protection Mode Register and Secure PIO Write Protection Mode + * Register + */ #define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */ #define PIO_WPMR_WPITEN (1 << 1) /* Bit 1: Write Protection Interrupt Enable */ @@ -294,7 +300,9 @@ #define PIO_WPMR_WPKEY_MASK (0x00ffffff << PIO_WPMR_WPKEY_SHIFT) # define PIO_WPMR_WPKEY (0x0050494f << PIO_WPMR_WPKEY_SHIFT) /* "PIO" */ -/* PIO Write Protection Status Register and Secure PIO Write Protection Status Register*/ +/* PIO Write Protection Status Register and Secure PIO Write Protection + * Status Register + */ #define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protection Violation Status */ #define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ @@ -306,16 +314,16 @@ #define SPIO_SCDR_DIV_MASK (0x3fff << SPIO_SCDR_DIV_SHIFT) # define SPIO_SCDR_DIV(n) ((uint32_t)(n) << SPIO_SCDR_DIV_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PIO_H */ diff --git a/arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h b/arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h index 8d34364f9c5..9a2b3697330 100644 --- a/arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h +++ b/arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3DX4X_PIO_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3DX4X_PIO_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* Misc Helper Definitions **************************************************************/ + ****************************************************************************/ + +/* Misc Helper Definitions **************************************************/ #define PIOA (0) #define PIOB (1) @@ -41,7 +42,7 @@ #define PIOD (3) #define PIOE (4) -/* PIO register offsets *****************************************************************/ +/* PIO register offsets *****************************************************/ #define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ #define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ @@ -115,7 +116,7 @@ #define SAM_PIO_DRIVER2_OFFSET 0x011c /* I/O Drive Register 2 */ /* 0x0120-0x14c: Reserved */ -/* PIO register addresses ***************************************************************/ +/* PIO register addresses ***************************************************/ #define PIOA (0) #define PIOB (1) @@ -482,7 +483,7 @@ #define SAM_PIOE_DRIVER1 (SAM_PIOE_VBASE+SAM_PIO_DRIVER1_OFFSET) #define SAM_PIOE_DRIVER2 (SAM_PIOE_VBASE+SAM_PIO_DRIVER2_OFFSET) -/* PIO register bit definitions *********************************************************/ +/* PIO register bit definitions *********************************************/ /* Common bit definitions for ALMOST all IO registers (exceptions follow) */ @@ -617,16 +618,16 @@ #define PIO_DRIVER2_LINE31_MASK (3 < #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Decimal configuration values may exceed 2Gb and, hence, overflow to negative - * values unless we force them to unsigned long: +/* Decimal configuration values may exceed 2Gb and, hence, overflow to + * negative values unless we force them to unsigned long: */ #define __CONCAT(a,b) a ## b @@ -126,8 +126,9 @@ # define SAM_SYSC_PADDR 0xffffc000 /* 0xffffc000-0xffffffff: System Controller */ # define SAM_SYSC_OFFSET 0x00000000 /* 0x0fffc000-0x0fffffff: System Controller */ -/* System Controller Peripheral Offsets. All relative to the beginning of the - * 16KB virtual or physical SYSC region (SAM_SYSC_VADDR or SAM_SYSC_PADDR). +/* System Controller Peripheral Offsets. + * All relative to the beginning of the 16KB virtual or physical SYSC region + * (SAM_SYSC_VADDR or SAM_SYSC_PADDR). */ #define SAM_HSMC_OFFSET 0x00000000 /* 0x00000000-0x00000fff: HSMC */ @@ -165,7 +166,7 @@ * are not known apriori and must be specified with configuration settings. */ - /* 0x00000000-0x0fffffff: Internal Memories */ + /* 0x00000000-0x0fffffff: Internal Memories */ #define SAM_BOOTMEM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: Boot memory */ #define SAM_ROM_SIZE (1*1024*1024) /* 0x00100000-0x001fffff: ROM */ #define SAM_NFCSRAM_SIZE (1*1024*1024) /* 0x00200000-0x002fffff: NFC SRAM */ @@ -313,8 +314,8 @@ /* SAMA5 Virtual (mapped) Memory Map * * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it depends - * on some the virtual address definitions provided above. + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. */ #include @@ -545,8 +546,9 @@ * page table will be squeezed into the end of internal SRAM in this * case. * - * Or... the user may specify the address of the page table explicitly be defining - * PGTABLE_BASE_VADDR and PGTABLE_BASE_PADDR in the board.h file. + * Or... the user may specify the address of the page table explicitly + * be defining PGTABLE_BASE_VADDR and PGTABLE_BASE_PADDR in the board.h + * file. */ #undef PGTABLE_IN_HIGHSRAM @@ -555,41 +557,41 @@ #if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR) - /* Sanity check.. if one is undefined, both should be undefined */ +/* Sanity check.. if one is undefined, both should be undefined */ # if defined(PGTABLE_BASE_PADDR) || defined(PGTABLE_BASE_VADDR) # error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined" # endif - /* A sanity check, if the configuration says that the page table is read-only - * and pre-initialized (maybe ROM), then it should have also defined both of - * the page table base addresses. - */ +/* A sanity check, if the configuration says that the page table is read-only + * and pre-initialized (maybe ROM), then it should have also defined both of + * the page table base addresses. + */ # ifdef CONFIG_ARCH_ROMPGTABLE # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif - /* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h - * - * We must declare the page table at the bottom or at the top of internal - * SRAM. We pick the bottom of internal SRAM *unless* there are vectors - * in the way at that position. - */ +/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory + * map probably do not apply because paging logic will probably partition + * the SRAM section differently. In particular, if the page table is located + * at the end of SRAM, then the virtual page table address defined below + * will probably be in error. In that case PGTABLE_BASE_VADDR is defined + * in the file mmu.h + * + * We must declare the page table at the bottom or at the top of internal + * SRAM. We pick the bottom of internal SRAM *unless* there are vectors + * in the way at that position. + */ # if defined(CONFIG_SAMA5_BOOT_ISRAM) && defined(CONFIG_ARCH_LOWVECTORS) - /* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 - * if ISRAM1 is not available in this architecture) - * - * If CONFIG_PAGING is defined, then mmu.h assign the virtual address - * of the page table. - */ +/* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 + * if ISRAM1 is not available in this architecture) + * + * If CONFIG_PAGING is defined, then mmu.h assign the virtual address + * of the page table. + */ # if SAM_ISRAM1_SIZE > 0 # define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) @@ -604,15 +606,15 @@ # endif # define PGTABLE_IN_HIGHSRAM 1 - /* If we execute from SRAM but keep data in SDRAM, then we will also have - * to position the initial, IDLE stack in SRAM. SDRAM will not be ready - * soon enough to serve as the stack. - * - * In this case, the initial IDLE stack can just follow the vector table, - * lying between the vector table and the page table. We don't really - * know how much memory to set aside for the vector table, but 4KiB should - * be much more than enough - */ +/* If we execute from SRAM but keep data in SDRAM, then we will also have + * to position the initial, IDLE stack in SRAM. SDRAM will not be ready + * soon enough to serve as the stack. + * + * In this case, the initial IDLE stack can just follow the vector table, + * lying between the vector table and the page table. We don't really + * know how much memory to set aside for the vector table, but 4KiB should + * be much more than enough + */ # ifdef CONFIG_BOOT_SDRAM_DATA # define IDLE_STACK_PBASE (SAM_ISRAM0_PADDR + 0x0001000) @@ -621,10 +623,10 @@ # else /* CONFIG_SAMA5_BOOT_ISRAM && CONFIG_ARCH_LOWVECTORS */ - /* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, perhaps - * elsewhere in internal SRAM). The page table will then be positioned at - * the first 16Kb of ISRAM0. - */ +/* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, + * perhaps elsewhere in internal SRAM). The page table will then be + * positioned at the first 16Kb of ISRAM0. + */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR # ifndef CONFIG_PAGING @@ -639,15 +641,15 @@ # endif /* CONFIG_SAMA5_BOOT_ISRAM && CONFIG_ARCH_LOWVECTORS */ - /* In either case, the page table lies in ISRAM. If ISRAM is not the - * primary RAM region, then we will need to set-up a special mapping for - * the page table at boot time. - */ +/* In either case, the page table lies in ISRAM. If ISRAM is not the + * primary RAM region, then we will need to set-up a special mapping for + * the page table at boot time. + */ # if defined(CONFIG_BOOT_RUNFROMFLASH) - /* If we are running from FLASH, than the primary memory region is - * given by NUTTX_RAM_PADDR. - */ +/* If we are running from FLASH, than the primary memory region is + * given by NUTTX_RAM_PADDR. + */ # if NUTTX_RAM_PADDR != SAM_ISRAM_PSECTION # define ARMV7A_PGTABLE_MAPPING 1 @@ -663,19 +665,19 @@ #else /* !PGTABLE_BASE_PADDR || !PGTABLE_BASE_VADDR */ - /* Sanity check.. if one is defined, both should be defined */ +/* Sanity check.. if one is defined, both should be defined */ # if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR) # error "One of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is undefined" # endif - /* If we execute from SRAM but keep data in SDRAM, then we will also have - * to position the initial, IDLE stack in SRAM. SDRAM will not be ready - * soon enough to serve as the stack. - * - * In this case, the initial IDLE stack can just follow the page table - * in ISRAM. - */ +/* If we execute from SRAM but keep data in SDRAM, then we will also have + * to position the initial, IDLE stack in SRAM. SDRAM will not be ready + * soon enough to serve as the stack. + * + * In this case, the initial IDLE stack can just follow the page table + * in ISRAM. + */ # ifdef CONFIG_BOOT_SDRAM_DATA # define IDLE_STACK_PBASE (SAM_ISRAM0_PADDR + PGTABLE_SIZE) @@ -686,32 +688,32 @@ /* Level 2 Page table start addresses. * - * 16Kb of memory is reserved hold the page table for the virtual mappings. A - * portion of this table is not accessible in the virtual address space (for - * normal operation). There is this large whole in the physcal address space - * for which there will never be level 1 mappings: + * 16Kb of memory is reserved hold the page table for the virtual mappings. + * A portion of this table is not accessible in the virtual address space + * (for normal operation). There is this large whole in the physcal address + * space for which there will never be level 1 mappings: * * 0x80000000-0xefffffff: Undefined (1.75 GB) * - * That is the offset where the main L2 page tables will be positioned. This - * corresponds to page table offsets 0x000002000 up to 0x000003c00. That - * is 1792 entries, each mapping 4KB of address for a total of 7MB of virtual - * address space) + * That is the offset where the main L2 page tables will be positioned. + * This corresponds to page table offsets 0x000002000 up to 0x000003c00. + * That is 1792 entries, each mapping 4KB of address for a total of 7MB of + * virtual address space) * * Up to two L2 page tables may be used: * - * 1) One mapping the vector table. However, L2 page tables must be aligned - * to 1KB address boundaries, so the minimum L2 page table size is then - * 1KB, mapping up a full megabyte of virtual address space. + * 1) One mapping the vector table. However, L2 page tables must be + * aligned to 1KB address boundaries, so the minimum L2 page table size + * is then 1KB, mapping up a full megabyte of virtual address space. * - * This L2 page table is only allocated if CONFIG_ARCH_LOWVECTORS is *not* - * defined. The SAMA5 boot-up logic will map the beginning of the boot - * memory to address 0x0000:0000 using both the MMU and the AXI matrix - * REMAP register. So no L2 page table is required. + * This L2 page table is only allocated if CONFIG_ARCH_LOWVECTORS is + * *not* defined. The SAMA5 boot-up logic will map the beginning of the + * boot memory to address 0x0000:0000 using both the MMU and the AXI + * matrix REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. This page table will use the remainder of - * the address space. + * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an + * additional L2 page table is needed. + * This page table will use the remainder of the address space. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -760,7 +762,8 @@ * * SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM * SAM_VECTOR_VSRAM - Virtual address of vector table in SRAM - * SAM_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000) + * SAM_VECTOR_VADDR - Virtual address of vector table + * (0x00000000 or 0xffff0000) */ #define VECTOR_TABLE_SIZE 0x00010000 @@ -784,12 +787,12 @@ #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MEMORYMAP_H */ diff --git a/arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h b/arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h index d1274852519..92562781021 100644 --- a/arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h +++ b/arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MPDDRC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MPDDRC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* MPDDRC Register Offsets **********************************************************/ + ****************************************************************************/ + +/* MPDDRC Register Offsets **************************************************/ #define SAM_MPDDRC_MR_OFFSET 0x0000 /* MPDDRC Mode Register */ #define SAM_MPDDRC_RTR_OFFSET 0x0004 /* MPDDRC Refresh Timer Register */ @@ -64,7 +65,7 @@ /* 0x158-0x1cc Reserved */ /* 0x1dc-0x1f8 Reserved */ -/* MPDDRC Register Addresses ********************************************************/ +/* MPDDRC Register Addresses ************************************************/ #define SAM_MPDDRC_MR (SAM_MPDDRC_VBASE+SAM_MPDDRC_MR_OFFSET) #define SAM_MPDDRC_RTR (SAM_MPDDRC_VBASE+SAM_MPDDRC_RTR_OFFSET) @@ -92,7 +93,7 @@ #define SAM_MPDDRC_WPCR (SAM_MPDDRC_VBASE+SAM_MPDDRC_WPCR_OFFSET) #define SAM_MPDDRC_WPSR (SAM_MPDDRC_VBASE+SAM_MPDDRC_WPSR_OFFSET) -/* MPDDRC Register Bit Definitions **************************************************/ +/* MPDDRC Register Bit Definitions ******************************************/ /* MPDDRC Mode Register */ @@ -106,6 +107,7 @@ # define MPDDRC_MR_MODE_EXTLMR (5 << MPDDRC_MR_MODE_SHIFT) /* 'Extended Load Mode Register' when device accessed */ # define MPDDRC_MR_MODE_DEEP (6 << MPDDRC_MR_MODE_SHIFT) /* Deep power mode */ # define MPDDRC_MR_MODE_LPDDR2 (7 << MPDDRC_MR_MODE_SHIFT) /* LPDDR2 Mode Register' when device accessed */ + #define MPDDRC_MR_MRS_SHIFT (8) /* Bits 8-15: Mode Register Select LPDDR2 */ #define MPDDRC_MR_MRS_MASK (0xff << MPDDRC_MR_MRS_SHIFT) # define MPDDRC_MR_MRS(n) ((n) << MPDDRC_MR_MRS_SHIFT) @@ -129,12 +131,14 @@ # define MPDDRC_CR_NC_10 (1 << MPDDRC_CR_NC_SHIFT) /* 10 DDR column bits */ # define MPDDRC_CR_NC_11 (2 << MPDDRC_CR_NC_SHIFT) /* 11 DDR column bits */ # define MPDDRC_CR_NC_12 (3 << MPDDRC_CR_NC_SHIFT) /* 12 DDR column bits */ + #define MPDDRC_CR_NR_SHIFT (2) /* Bits 2-3: Number of Row Bits */ #define MPDDRC_CR_NR_MASK (3 << MPDDRC_CR_NR_SHIFT) # define MPDDRC_CR_NR_11 (0 << MPDDRC_CR_NR_SHIFT) /* 00 ROW_11 11 row bits */ # define MPDDRC_CR_NR_12 (1 << MPDDRC_CR_NR_SHIFT) /* 01 ROW_12 12 row bits */ # define MPDDRC_CR_NR_13 (2 << MPDDRC_CR_NR_SHIFT) /* 10 ROW_13 13 row bits */ # define MPDDRC_CR_NR_14 (3 << MPDDRC_CR_NR_SHIFT) /* 11 ROW_14 14 row bits */ + #define MPDDRC_CR_CAS_SHIFT (4) /* Bits 4-6: CAS Latency */ #define MPDDRC_CR_CAS_MASK (7 << MPDDRC_CR_CAS_SHIFT) # define MPDDRC_CR_CAS_2 (2 << MPDDRC_CR_CAS_SHIFT) /* 010 DDR_CAS2 LPDDR1 CAS Latency 2 */ @@ -142,6 +146,7 @@ # define MPDDRC_CR_CAS_4 (4 << MPDDRC_CR_CAS_SHIFT) /* 100 DDR_CAS4 DDR2/LPDDR2 CAS Latency 4 */ # define MPDDRC_CR_CAS_5 (5 << MPDDRC_CR_CAS_SHIFT) /* 101 DDR_CAS5 DDR2/LPDDR2 CAS Latency 5 */ # define MPDDRC_CR_CAS_6 (6 << MPDDRC_CR_CAS_SHIFT) /* 110 DDR_CAS6 DDR2 CAS Latency 6 */ + #define MPDDRC_CR_DLL (1 << 7) /* Bit 7: Reset DLL */ #define MPDDRC_CR_DIC_DS (1 << 8) /* Bit 8: Output Driver Impedance Control (Drive Strength) */ #define MPDDRC_CR_DIS_DLL (1 << 9) /* Bit 9: Disable DLL */ @@ -151,15 +156,19 @@ # define MPDDRC_CR_ZQ_LONG (1 << MPDDRC_CR_ZQ_SHIFT) /* Long calibration */ # define MPDDRC_CR_ZQ_SHORT (2 << MPDDRC_CR_ZQ_SHIFT) /* Short calibration */ # define MPDDRC_CR_ZQ_RESET (3 << MPDDRC_CR_ZQ_SHIFT) /* ZQ Reset */ + #define MPDDRC_CR_OCD_SHIFT (12) /* Bits 12-14: Off-chip Driver */ #define MPDDRC_CR_OCD_MASK (7 << MPDDRC_CR_OCD_SHIFT) # define MPDDRC_CR_OCD_EXIT (0 << MPDDRC_CR_OCD_SHIFT) /* OCD calibration mode exit, maintain setting */ # define MPDDRC_CR_OCD_DEFAULT (7 << MPDDRC_CR_OCD_SHIFT) /* OCD calibration default */ + #define MPDDRC_CR_DQMS (1 << 16) /* Bit 16: Mask Data is Shared */ #define MPDDRC_CR_ENRDM (1 << 17) /* Bit 17: Enable Read Measure */ #define MPDDRC_CR_NB (1 << 20) /* Bit 20: Number of Banks */ -# define MPDDRC_CR_4BANKS (0) /* 4 banks */ + +# define MPDDRC_CR_4BANKS (0) /* 4 banks */ # define MPDDRC_CR_8BANKS MPDDRC_CR_NB /* 8 banks */ + #define MPDDRC_CR_NDQS (1 << 21) /* Bit 21: Not DQS */ #define MPDDRC_CR_DECOD (1 << 22) /* Bit 22: Type of Decoding */ #define MPDDRC_CR_UNAL (1 << 23) /* Bit 23: Support Unaligned Access */ @@ -233,6 +242,7 @@ # define MPDDRC_LPR_LPCB_SELFREFRESH (1 << MPDDRC_LPR_LPCB_SHIFT) /* Issues a 'Self Refresh' to device, clocks deactivated */ # define MPDDRC_LPR_LPCB_POWERDOWN (2 << MPDDRC_LPR_LPCB_SHIFT) /* Issues a 'Power-down' to device after each access */ # define MPDDRC_LPR_LPCB_DEEPPWD (3 << MPDDRC_LPR_LPCB_SHIFT) /* TIssues a 'Deep Power-down' to Low-power device */ + #define MPDDRC_LPR_CLK_FR (1 << 2) /* Bit 2: Clock Frozen Command */ #define MPDDRC_LPR_LPDDR2_PWOFF (1 << 3) /* Bit 3: LPDDR2 Power Off */ #define MPDDRC_LPR_PASR_SHIFT (4) /* Bits 4-6: Partial Array Self Refresh */ @@ -246,6 +256,7 @@ # define MPDDRC_LPR_TIMEOUT_0CLKS (0 << MPDDRC_LPR_TIMEOUT_SHIFT) /* Activates low-power mode after the end of transfer */ # define MPDDRC_LPR_TIMEOUT_64CLKS (1 << MPDDRC_LPR_TIMEOUT_SHIFT) /* Activates low-power mode 64 clocks after the end of transfer */ # define MPDDRC_LPR_TIMEOUT_128CLKS (2 << MPDDRC_LPR_TIMEOUT_SHIFT) /* 28 Activates low-power mode 128 clocks after the end of transfer */ + #define MPDDRC_LPR_APDE (1 << 16) /* Bit 16: ctive Power Down Exit Time */ # define MPDDRC_LPR_APDE_FAST (0) # define MPDDRC_LPR_APDE_SLOW MPDDRC_LPR_APDE @@ -262,8 +273,10 @@ # define MPDDRC_MD_LPDDR_SDRAM (2 << MPDDRC_MD_SHIFT) /* Low-power DDR1-SDRAM */ # define MPDDRC_MD_DDR2_SDRAM (6 << MPDDRC_MD_SHIFT) /* DDR2-SDRAM */ # define MPDDRC_MD_LPDDR2_SDRAM (7 << MPDDRC_MD_SHIFT) /* Low-Power DDR2-SDRAM */ + #define MPDDRC_MD_DBW (1 << 4) /* Bit 4: Data Bus Width */ # define MPDDRC_MD_DBW32 (0) /* Data bus width is 32 bits */ + # define MPDDRC_MD_DBW16 MPDDRC_MD_DBW /* Data bus width is 16 bits */ /* MPDDRC High Speed Register */ @@ -311,6 +324,7 @@ # define MPDDRC_IO_CALIBR_RZQ60_50 (4 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 60 Ohm DDR2/LPDDR1: RZQ = 50 Ohm */ # define MPDDRC_IO_CALIBR_RZQ80_67 (6 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2 RZQ = 80 Ohm DDR2/LPDDR1: RZQ = 66.7 Ohm */ # define MPDDRC_IO_CALIBR_RZQ120_100 (7 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 120 Oh m DDR2/LPDDR1: RZQ = 100 Ohm */ + #define MPDDRC_IO_CALIBR_TZQIO_SHIFT (8) /* Bits 8-10: IO Calibration */ #define MPDDRC_IO_CALIBR_TZQIO_MASK (7 << MPDDRC_IO_CALIBR_TZQIO_SHIFT) # define MPDDRC_IO_CALIBR_TZQIO(n) ((n) << MPDDRC_IO_CALIBR_TZQIO_SHIFT) @@ -326,6 +340,7 @@ #define MPDDRC_OCMS_SCR_EN (1 << 0) /* Bit 0: Scrambling enable */ /* MPDDRC OCMS KEY1 Register (32-bit key value) */ + /* MPDDRC OCMS KEY2 Register (32-bit key value) */ /* MPDDRC DLL Master Offset Register */ @@ -379,7 +394,7 @@ #define MPDDRC_WPCR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */ #define MPDDRC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY */ #define MPDDRC_WPCR_WPKEY_MASK (0x00ffffff << MPDDRC_WPCR_WPKEY_SHIFT) - #define MPDDRC_WPCR_WPKEY (0x00444452 << MPDDRC_WPCR_WPKEY_SHIFT) +# define MPDDRC_WPCR_WPKEY (0x00444452 << MPDDRC_WPCR_WPKEY_SHIFT) /* MPDDRC Write Protect Status Register */ diff --git a/arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h b/arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h index ec8a2b28a11..dded0936716 100644 --- a/arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h +++ b/arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,40 +16,43 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_PINMAP_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_PINMAP_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_pio.h" -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ + ****************************************************************************/ + +/* PIO pin definitions ******************************************************/ -/* PIO pin definitions **************************************************************************************/ /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however, will - * use the pin selection without the numeric suffix. Additional definitions are required in the board.h - * file. For example, if we wanted the LCD data bit 16 on PA16, then the following definition should appear - * in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. + * For example, if we wanted the LCD data bit 16 on PA16, then the following + * definition should appear in the board.h header file for that board: * * #define PIO_LCD_DAT16 PIO_LCD_DAT16_1 * * The LCD driver will then automatically configure PA16 as the DAT16 pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific PIO options such as frequency, open-drain/push-pull, - * and pull-up/down! Just the basics are defined for most pins in this file at the present time. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific PIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file at the present time. */ /* Touch Screen Analog-to-Digital Converter - ADC */ diff --git a/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h index 30a39603030..7945a42ed7d 100644 --- a/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h +++ b/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Decimal configuration values may exceed 2Gb and, hence, overflow to negative - * values unless we force them to unsigned long: + ****************************************************************************/ + +/* Decimal configuration values may exceed 2Gb and, hence, overflow to + * negative values unless we force them to unsigned long: */ #define __CONCAT(a,b) a ## b @@ -84,6 +85,7 @@ #define SAM_SMD_PSECTION 0x00900000 /* 0x00900000-0x009fffff: SMD */ #define SAM_L2CC_PSECTION 0x00a00000 /* 0x00a00000-0x00afffff: L2CC */ /* 0x00a00000-0x0fffffff: Undefined */ + /* SAMA5 Internal Peripheral Offsets */ #define SAM_PERIPHA_PSECTION 0xf0000000 /* 0xf0000000-0xffffffff: Internal Peripherals */ @@ -158,7 +160,8 @@ * region. The implemented sizes of the EBI CS0-3 and DDRCS regions * are not known apriori and must be specified with configuration settings. */ - /* 0x00000000-0x0fffffff: Internal Memories */ + + /* 0x00000000-0x0fffffff: Internal Memories */ #define SAM_BOOTMEM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: Boot memory */ #define SAM_ROM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: ROM */ #define SAM_NFCSRAM_SIZE (1*1024*1024) /* 0x00100000-0x001fffff: NFC SRAM */ @@ -311,8 +314,8 @@ /* SAMA5 Virtual (mapped) Memory Map * * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it depends - * on some the virtual address definitions provided above. + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. */ #include @@ -534,8 +537,8 @@ * page table will be squeezed into the end of internal SRAM in this * case. * - * Or... the user may specify the address of the page table explicitly be defining - * PGTABLE_BASE_VADDR and PGTABLE_BASE_PADDR in the board.h file. + * Or... the user may specify the address of the page table explicitly be + * defining PGTABLE_BASE_VADDR and PGTABLE_BASE_PADDR in the board.h file. */ #undef PGTABLE_IN_HIGHSRAM @@ -550,35 +553,35 @@ # error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined" # endif - /* A sanity check, if the configuration says that the page table is read-only - * and pre-initialized (maybe ROM), then it should have also defined both of - * the page table base addresses. - */ +/* A sanity check, if the configuration says that the page table is read-only + * and pre-initialized (maybe ROM), then it should have also defined both of + * the page table base addresses. + */ # ifdef CONFIG_ARCH_ROMPGTABLE # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif - /* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h - * - * We must declare the page table at the bottom or at the top of internal - * SRAM. We pick the bottom of internal SRAM *unless* there are vectors - * in the way at that position. - */ +/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory + * map probably do not apply because paging logic will probably partition + * the SRAM section differently. In particular, if the page table is located + * at the end of SRAM, then the virtual page table address defined below + * will probably be in error. In that case PGTABLE_BASE_VADDR is defined + * in the file mmu.h + * + * We must declare the page table at the bottom or at the top of internal + * SRAM. We pick the bottom of internal SRAM *unless* there are vectors + * in the way at that position. + */ # if defined(CONFIG_SAMA5_BOOT_ISRAM) && defined(CONFIG_ARCH_LOWVECTORS) - /* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 - * if ISRAM1 is not available in this architecture) - * - * If CONFIG_PAGING is defined, then mmu.h assign the virtual address - * of the page table. - */ +/* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 + * if ISRAM1 is not available in this architecture) + * + * If CONFIG_PAGING is defined, then mmu.h assign the virtual address + * of the page table. + */ # if SAM_ISRAM1_SIZE > 0 # define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) @@ -593,15 +596,15 @@ # endif # define PGTABLE_IN_HIGHSRAM 1 - /* If we execute from SRAM, but keep data in SDRAM, then we will also have - * to position the initial, IDLE stack in SRAM. SDRAM will not be ready - * soon enough to serve as the stack. - * - * In this case, the initial IDLE stack can just follow the vector table, - * lying between the vector table and the page table. We don't really - * know how much memory to set aside for the vector table, but 4KiB should - * be much more than enough - */ +/* If we execute from SRAM, but keep data in SDRAM, then we will also have + * to position the initial, IDLE stack in SRAM. SDRAM will not be ready + * soon enough to serve as the stack. + * + * In this case, the initial IDLE stack can just follow the vector table, + * lying between the vector table and the page table. We don't really + * know how much memory to set aside for the vector table, but 4KiB should + * be much more than enough + */ # ifdef CONFIG_BOOT_SDRAM_DATA # define IDLE_STACK_PBASE (SAM_ISRAM0_PADDR + 0x0001000) @@ -610,10 +613,10 @@ # else /* CONFIG_SAMA5_BOOT_ISRAM && CONFIG_ARCH_LOWVECTORS */ - /* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, perhaps - * elsewhere in internal SRAM). The page table will then be positioned at - * the first 16Kb of ISRAM0. - */ +/* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, + * perhaps elsewhere in internal SRAM). The page table will then be + * positioned at the first 16Kb of ISRAM0. + */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR # ifndef CONFIG_PAGING @@ -621,13 +624,13 @@ # endif # define PGTABLE_IN_LOWSRAM 1 - /* If we execute from SRAM, but keep data in SDRAM, then we will also have - * to position the initial, IDLE stack in SRAM. SDRAM will not be ready - * soon enough to serve as the stack. - * - * In this case, the initial IDLE stack can just follow the page table - * in ISRAM. - */ +/* If we execute from SRAM, but keep data in SDRAM, then we will also have + * to position the initial, IDLE stack in SRAM. SDRAM will not be ready + * soon enough to serve as the stack. + * + * In this case, the initial IDLE stack can just follow the page table + * in ISRAM. + */ # ifdef CONFIG_BOOT_SDRAM_DATA # define IDLE_STACK_PBASE (PGTABLE_BASE_PADDR + PGTABLE_SIZE) @@ -636,15 +639,15 @@ # endif /* CONFIG_SAMA5_BOOT_ISRAM && CONFIG_ARCH_LOWVECTORS */ - /* In either case, the page table lies in ISRAM. If ISRAM is not the - * primary RAM region, then we will need to set-up a special mapping for - * the page table at boot time. - */ +/* In either case, the page table lies in ISRAM. If ISRAM is not the + * primary RAM region, then we will need to set-up a special mapping for + * the page table at boot time. + */ # if defined(CONFIG_BOOT_RUNFROMFLASH) - /* If we are running from FLASH, than the primary memory region is - * given by NUTTX_RAM_PADDR. - */ +/* If we are running from FLASH, than the primary memory region is + * given by NUTTX_RAM_PADDR. + */ # if NUTTX_RAM_PADDR != SAM_ISRAM_PSECTION # define ARMV7A_PGTABLE_MAPPING 1 @@ -660,13 +663,13 @@ #else /* !PGTABLE_BASE_PADDR || !PGTABLE_BASE_VADDR */ - /* Sanity check.. if one is defined, both should be defined */ +/* Sanity check.. if one is defined, both should be defined */ # if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR) # error "One of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is undefined" # endif - /* If data is in SDRAM, then the IDLE stack at the beginning of ISRAM */ +/* If data is in SDRAM, then the IDLE stack at the beginning of ISRAM */ # ifdef CONFIG_BOOT_SDRAM_DATA # define IDLE_STACK_PBASE (SAM_ISRAM0_PADDR + PGTABLE_SIZE) @@ -677,17 +680,17 @@ /* Level 2 Page table start addresses. * - * 16Kb of memory is reserved hold the page table for the virtual mappings. A - * portion of this table is not accessible in the virtual address space (for - * normal operation). There is this large whole in the physcal address space - * for which there will never be level 1 mappings: + * 16Kb of memory is reserved hold the page table for the virtual mappings. + * A portion of this table is not accessible in the virtual address space + *(for normal operation). There is this large whole in the physcal + * address space for which there will never be level 1 mappings: * * 0x80000000-0xefffffff: Undefined (1.75 GB) * - * That is the offset where the main L2 page tables will be positioned. This - * corresponds to page table offsets 0x000002000 up to 0x000003c00. That - * is 1792 entries, each mapping 4KB of address for a total of 7MB of virtual - * address space) + * That is the offset where the main L2 page tables will be positioned. + * This corresponds to page table offsets 0x000002000 up to 0x000003c00. + * That is 1792 entries, each mapping 4KB of address for a total of 7MB of + * virtual address space) * * Up to two L2 page tables may be used: * @@ -751,7 +754,8 @@ * * SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM * SAM_VECTOR_VSRAM - Virtual address of vector table in SRAM - * SAM_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000) + * SAM_VECTOR_VADDR - Virtual address of vector table + * (0x00000000 or 0xffff0000) */ #define VECTOR_TABLE_SIZE 0x00010000 @@ -775,16 +779,16 @@ #endif /* CONFIG_ARCH_LOWVECTORS */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MEMORYMAP_H */ diff --git a/arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h b/arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h index 33a88417bdb..038543b95b4 100644 --- a/arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h +++ b/arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MPDDRC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MPDDRC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* MPDDRC Register Offsets ******************************************************************/ + ****************************************************************************/ + +/* MPDDRC Register Offsets **************************************************/ #define SAM_MPDDRC_MR_OFFSET 0x0000 /* MPDDRC Mode Register */ #define SAM_MPDDRC_RTR_OFFSET 0x0004 /* MPDDRC Refresh Timer Register */ @@ -97,9 +98,9 @@ #define SAM_MPDDRC_DLL_SWR3_OFFSET 0x0154 /* MPDDRC DLL Status CLKWR3 Register */ #define SAM_MPDDRC_DLL_SAD_OFFSET 0x0158 /* MPDDRC DLL Status CLKAD Register */ - /* 0x015c-0x01fxc Reserved */ + /* 0x015c-0x01fxc Reserved */ -/* MPDDRC Register Addresses ****************************************************************/ +/* MPDDRC Register Addresses ************************************************/ #define SAM_MPDDRC_MR (SAM_MPDDRC_VBASE+SAM_MPDDRC_MR_OFFSET) #define SAM_MPDDRC_RTR (SAM_MPDDRC_VBASE+SAM_MPDDRC_RTR_OFFSET) @@ -164,7 +165,7 @@ #define SAM_MPDDRC_DLL_SAD (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SAD_OFFSET) -/* MPDDRC Register Bit Definitions **********************************************************/ +/* MPDDRC Register Bit Definitions ******************************************/ /* MPDDRC Mode Register */ @@ -178,6 +179,7 @@ # define MPDDRC_MR_MODE_EXTLMR (5 << MPDDRC_MR_MODE_SHIFT) /* 'Extended Load Mode Register' when device accessed */ # define MPDDRC_MR_MODE_DEEP (6 << MPDDRC_MR_MODE_SHIFT) /* Deep power mode */ # define MPDDRC_MR_MODE_LPDDR2 (7 << MPDDRC_MR_MODE_SHIFT) /* LPDDR2 Mode Register' when device accessed */ + #define MPDDRC_MR_MRS_SHIFT (8) /* Bits 8-15: Mode Register Select LPDDR2 */ #define MPDDRC_MR_MRS_MASK (0xff << MPDDRC_MR_MRS_SHIFT) # define MPDDRC_MR_MRS(n) ((n) << MPDDRC_MR_MRS_SHIFT) @@ -201,12 +203,14 @@ # define MPDDRC_CR_NC_10 (1 << MPDDRC_CR_NC_SHIFT) /* 10 DDR column bits */ # define MPDDRC_CR_NC_11 (2 << MPDDRC_CR_NC_SHIFT) /* 11 DDR column bits */ # define MPDDRC_CR_NC_12 (3 << MPDDRC_CR_NC_SHIFT) /* 12 DDR column bits */ + #define MPDDRC_CR_NR_SHIFT (2) /* Bits 2-3: Number of Row Bits */ #define MPDDRC_CR_NR_MASK (3 << MPDDRC_CR_NR_SHIFT) # define MPDDRC_CR_NR_11 (0 << MPDDRC_CR_NR_SHIFT) /* 00 ROW_11 11 row bits */ # define MPDDRC_CR_NR_12 (1 << MPDDRC_CR_NR_SHIFT) /* 01 ROW_12 12 row bits */ # define MPDDRC_CR_NR_13 (2 << MPDDRC_CR_NR_SHIFT) /* 10 ROW_13 13 row bits */ # define MPDDRC_CR_NR_14 (3 << MPDDRC_CR_NR_SHIFT) /* 11 ROW_14 14 row bits */ + #define MPDDRC_CR_CAS_SHIFT (4) /* Bits 4-6: CAS Latency */ #define MPDDRC_CR_CAS_MASK (7 << MPDDRC_CR_CAS_SHIFT) # define MPDDRC_CR_CAS_2 (2 << MPDDRC_CR_CAS_SHIFT) /* 010 DDR_CAS2 LPDDR1 CAS Latency 2 */ @@ -214,6 +218,7 @@ # define MPDDRC_CR_CAS_4 (4 << MPDDRC_CR_CAS_SHIFT) /* 100 DDR_CAS4 DDR2/LPDDR2 CAS Latency 4 */ # define MPDDRC_CR_CAS_5 (5 << MPDDRC_CR_CAS_SHIFT) /* 101 DDR_CAS5 DDR2/LPDDR2 CAS Latency 5 */ # define MPDDRC_CR_CAS_6 (6 << MPDDRC_CR_CAS_SHIFT) /* 110 DDR_CAS6 DDR2 CAS Latency 6 */ + #define MPDDRC_CR_DLL (1 << 7) /* Bit 7: Reset DLL */ #define MPDDRC_CR_DIC_DS (1 << 8) /* Bit 8: Output Driver Impedance Control(Drive Strength) */ #define MPDDRC_CR_DIS_DLL (1 << 9) /* Bit 9: Disable DLL */ @@ -223,16 +228,20 @@ # define MPDDRC_CR_ZQ_LONG (1 << MPDDRC_CR_ZQ_SHIFT) /* Long calibration */ # define MPDDRC_CR_ZQ_SHORT (2 << MPDDRC_CR_ZQ_SHIFT) /* Short calibration */ # define MPDDRC_CR_ZQ_RESET (3 << MPDDRC_CR_ZQ_SHIFT) /* ZQ Reset */ + #define MPDDRC_CR_OCD_SHIFT (12) /* Bits 12-14: Off-chip Driver */ #define MPDDRC_CR_OCD_MASK (7 << MPDDRC_CR_OCD_SHIFT) # define MPDDRC_CR_OCD_EXIT (0 << MPDDRC_CR_OCD_SHIFT) /* OCD calibration mode exit, maintain setting */ # define MPDDRC_CR_OCD_DEFAULT (7 << MPDDRC_CR_OCD_SHIFT) /* OCD calibration default */ + #define MPDDRC_CR_DQMS (1 << 16) /* Bit 16: Mask Data is Shared */ #define MPDDRC_CR_ENRDM (1 << 17) /* Bit 17: Enable Read Measure */ #define MPDDRC_CR_LC_LPDDR1 (1 << 19) /* Bit 19: Low-cost Low-power DDR1 */ #define MPDDRC_CR_NB (1 << 20) /* Bit 20: Number of Banks */ -# define MPDDRC_CR_4BANKS (0) /* 4 banks */ + +# define MPDDRC_CR_4BANKS (0) /* 4 banks */ # define MPDDRC_CR_8BANKS MPDDRC_CR_NB /* 8 banks */ + #define MPDDRC_CR_NDQS (1 << 21) /* Bit 21: Not DQS */ #define MPDDRC_CR_DECOD (1 << 22) /* Bit 22: Type of Decoding */ #define MPDDRC_CR_UNAL (1 << 23) /* Bit 23: Support Unaligned Access */ @@ -306,6 +315,7 @@ # define MPDDRC_LPR_LPCB_SELFREFRESH (1 << MPDDRC_LPR_LPCB_SHIFT) /* Issues a 'Self Refresh' to device, clocks deactivated */ # define MPDDRC_LPR_LPCB_POWERDOWN (2 << MPDDRC_LPR_LPCB_SHIFT) /* Issues a 'Power-down' to device after each access */ # define MPDDRC_LPR_LPCB_DEEPPWD (3 << MPDDRC_LPR_LPCB_SHIFT) /* TIssues a 'Deep Power-down' to Low-power device */ + #define MPDDRC_LPR_CLK_FR (1 << 2) /* Bit 2: Clock Frozen Command */ #define MPDDRC_LPR_LPDDR2_PWOFF (1 << 3) /* Bit 3: LPDDR2 Power Off */ #define MPDDRC_LPR_PASR_SHIFT (4) /* Bits 4-6: Partial Array Self Refresh */ @@ -319,6 +329,7 @@ # define MPDDRC_LPR_TIMEOUT_0CLKS (0 << MPDDRC_LPR_TIMEOUT_SHIFT) /* Activates low-power mode after the end of transfer */ # define MPDDRC_LPR_TIMEOUT_64CLKS (1 << MPDDRC_LPR_TIMEOUT_SHIFT) /* Activates low-power mode 64 clocks after the end of transfer */ # define MPDDRC_LPR_TIMEOUT_128CLKS (2 << MPDDRC_LPR_TIMEOUT_SHIFT) /* 28 Activates low-power mode 128 clocks after the end of transfer */ + #define MPDDRC_LPR_APDE (1 << 16) /* Bit 16: ctive Power Down Exit Time */ # define MPDDRC_LPR_APDE_FAST (0) # define MPDDRC_LPR_APDE_SLOW MPDDRC_LPR_APDE @@ -336,8 +347,10 @@ # define MPDDRC_MD_LPDDR_SDRAM (3 << MPDDRC_MD_SHIFT) /* Low-power DDR1-SDRAM */ # define MPDDRC_MD_DDR2_SDRAM (6 << MPDDRC_MD_SHIFT) /* DDR2-SDRAM */ # define MPDDRC_MD_LPDDR2_SDRAM (7 << MPDDRC_MD_SHIFT) /* Low-power DDR2-SDRAM */ + #define MPDDRC_MD_DBW (1 << 4) /* Bit 4: Data Bus Width */ -# define MPDDRC_MD_DBW32 (0) /* Data bus width is 32 bits */ + +# define MPDDRC_MD_DBW32 (0) /* Data bus width is 32 bits */ # define MPDDRC_MD_DBW16 MPDDRC_MD_DBW /* Data bus width is 16 bits */ /* MPDDRC LPDDR2 Low-power Register */ @@ -377,6 +390,7 @@ # define MPDDRC_IO_CALIBR_RZQ60_50 (4 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 60 Ohm DDR2/LPDDR1: RZQ = 50 Ohm */ # define MPDDRC_IO_CALIBR_RZQ80_67 (6 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2 RZQ = 80 Ohm DDR2/LPDDR1: RZQ = 66.7 Ohm */ # define MPDDRC_IO_CALIBR_RZQ120_100 (7 << MPDDRC_IO_CALIBR_RDIV_SHIFT) /* LPDDR2:RZQ = 120 Oh m DDR2/LPDDR1: RZQ = 100 Ohm */ + #define MPDDRC_IO_CALIBR_EN_CALIB (1 << 4) /* Bit 4: Enable of the Calibration */ #define MPDDRC_IO_CALIBR_TZQIO_SHIFT (8) /* Bits 8-10: IO Calibration */ #define MPDDRC_IO_CALIBR_TZQIO_MASK (7 << MPDDRC_IO_CALIBR_TZQIO_SHIFT) @@ -393,6 +407,7 @@ #define MPDDRC_OCMS_SCR_EN (1 << 0) /* Bit 0: Scrambling enable */ /* MPDDRC OCMS KEY1 Register (32-bit key value) */ + /* MPDDRC OCMS KEY2 Register (32-bit key value) */ /* MPDDRC Configuration Arbiter Register */ @@ -402,18 +417,21 @@ # define MPDDRC_CONF_ARBITER_ARB_ROUND (0 << MPDDRC_CONF_ARBITER_ARB_SHIFT) /* Round Robin */ # define MPDDRC_CONF_ARBITER_ARB_NB_REQUEST (1 << MPDDRC_CONF_ARBITER_ARB_SHIFT) /* Request Policy */ # define MPDDRC_CONF_ARBITER_ARB_BANDWIDTH (2 << MPDDRC_CONF_ARBITER_ARB_SHIFT) /* Bandwidth Policy */ -#define MPDDRC_CONF_ARBITER_BDW_BURST (1 << 2) /* Bit 2: Bandwidth is Reached or Bandwidth and Current Burst Access is Ended */ -#define MPDDRC_CONF_ARBITER_BDW_MAX_CUR (1 << 3) /* Bit 3: Bandwidth Max or Current */ + +#define MPDDRC_CONF_ARBITER_BDW_BURST (1 << 2) /* Bit 2: Bandwidth is Reached or Bandwidth and Current Burst Access is Ended */ +#define MPDDRC_CONF_ARBITER_BDW_MAX_CUR (1 << 3) /* Bit 3: Bandwidth Max or Current */ #define MPDDRC_CONF_ARBITER_RQ_WD_P(n) (1 << ((n)+8) /* Bits 8-15: Request or Word from Port n */ -# define MPDDRC_CONF_ARBITER_RQ_WD_P0 (1 << 8) /* Bit 8: Request or Word from Port 0 */ -# define MPDDRC_CONF_ARBITER_RQ_WD_P1 (1 << 9) /* Bit 9: Request or Word from Port 1 */ -# define MPDDRC_CONF_ARBITER_RQ_WD_P2 (1 << 10) /* Bit 10: Request or Word from Port 2 */ -# define MPDDRC_CONF_ARBITER_RQ_WD_P3 (1 << 11) /* Bit 11: Request or Word from Port 3 */ -# define MPDDRC_CONF_ARBITER_RQ_WD_P4 (1 << 12) /* Bit 12: Request or Word from Port 4 */ -# define MPDDRC_CONF_ARBITER_RQ_WD_P5 (1 << 13) /* Bit 13: Request or Word from Port 5 */ -# define MPDDRC_CONF_ARBITER_RQ_WD_P6 (1 << 14) /* Bit 14: Request or Word from Port 6 */ -# define MPDDRC_CONF_ARBITER_RQ_WD_P7 (1 << 15) /* Bit 15: Request or Word from Port 7 */ + +# define MPDDRC_CONF_ARBITER_RQ_WD_P0 (1 << 8) /* Bit 8: Request or Word from Port 0 */ +# define MPDDRC_CONF_ARBITER_RQ_WD_P1 (1 << 9) /* Bit 9: Request or Word from Port 1 */ +# define MPDDRC_CONF_ARBITER_RQ_WD_P2 (1 << 10) /* Bit 10: Request or Word from Port 2 */ +# define MPDDRC_CONF_ARBITER_RQ_WD_P3 (1 << 11) /* Bit 11: Request or Word from Port 3 */ +# define MPDDRC_CONF_ARBITER_RQ_WD_P4 (1 << 12) /* Bit 12: Request or Word from Port 4 */ +# define MPDDRC_CONF_ARBITER_RQ_WD_P5 (1 << 13) /* Bit 13: Request or Word from Port 5 */ +# define MPDDRC_CONF_ARBITER_RQ_WD_P6 (1 << 14) /* Bit 14: Request or Word from Port 6 */ +# define MPDDRC_CONF_ARBITER_RQ_WD_P7 (1 << 15) /* Bit 15: Request or Word from Port 7 */ #define MPDDRC_CONF_ARBITER_MA_PR_P(n) (1 << ((n)+16)) /* Bits 16-23: Master or Software Provide Information */ + # define MPDDRC_CONF_ARBITER_MA_PR_P0 (1 << 16) /* Bit 16: Master or Software Provide Information */ # define MPDDRC_CONF_ARBITER_MA_PR_P1 (1 << 17) /* Bit 17: Master or Software Provide Information */ # define MPDDRC_CONF_ARBITER_MA_PR_P2 (1 << 18) /* Bit 18: Master or Software Provide Information */ @@ -457,8 +475,9 @@ #define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P_SHIFT(n) ((n)<<8) /* Number of Requests/Words/Allocation from Port n, n=0..3 */ #define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P_MASK(n) (0xff << PDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P_SHIFT(n)) + # define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P(n,v) ((uint32_t)(v) << PDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P_SHIFT(n)) -# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_SHIFT (0) /* Bits 0-7: Number of Requests/Words/Allocation from Port 0 */ +# define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_SHIFT (0) /* Bits 0-7: Number of Requests/Words/Allocation from Port 0 */ # define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_MASK (0xff << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_SHIFT) # define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0(n) ((uint32_t)(n) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_SHIFT) # define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_SHIFT (8) /* Bits 8-15: Number of Requests/Words/Allocation from Port 1 */ @@ -475,6 +494,7 @@ #define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P_SHIFT(n) ((n)<<8) /* Number of Requests/Words/Allocation from port n, n=4..7 */ #define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P_MASK(n) (0xff << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P_SHIFT(n)) + # define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P(n,v) ((uint32_t)(v) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P_SHIFT(n)) # define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_SHIFT (0) /* Bits 0-7: Number of Requests/Words/Allocation from port 4 */ # define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_MASK (0xff << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_SHIFT) @@ -547,6 +567,7 @@ # define MPDDRC_SAW_INCR_THRESH_8WORDS (8 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 8 word/dword max */ # define MPDDRC_SAW_INCR_THRESH_16WORDS (16 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 16 word/dword max */ # define MPDDRC_SAW_INCR_THRESH_32WORDS (21 << MPDDRC_SAW_INCR_THRESH_SHIFT) /* 32 word/dword max */ + #define MPDDRC_SAW_PFCH_THRESH_SHIFT (16) /* Bits 16-21: Prefetch Threshold */ #define MPDDRC_SAW_PFCH_THRESH_MASK (0x3f << MPDDRC_SAW_PFCH_THRESH_SHIFT) # define MPDDRC_SAW_PFCH_THRESH_2WORDS (2 << MPDDRC_SAW_PFCH_THRESH_SHIFT) /* 2 word/dword max */ @@ -558,7 +579,7 @@ #define MPDDRC_WPCR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */ #define MPDDRC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY */ #define MPDDRC_WPCR_WPKEY_MASK (0x00ffffff << MPDDRC_WPCR_WPKEY_SHIFT) - #define MPDDRC_WPCR_WPKEY (0x00444452 << MPDDRC_WPCR_WPKEY_SHIFT) +# define MPDDRC_WPCR_WPKEY (0x00444452 << MPDDRC_WPCR_WPKEY_SHIFT) /* MPDDRC Write Protect Status Register */ diff --git a/arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h b/arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h index bb84905377f..272bd50887c 100644 --- a/arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h +++ b/arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,40 +16,43 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_PINMAP_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_PINMAP_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_pio.h" -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ + ****************************************************************************/ + +/* PIO pin definitions ******************************************************/ -/* PIO pin definitions **************************************************************************************/ /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however, will - * use the pin selection without the numeric suffix. Additional definitions are required in the board.h - * file. For example, if we wanted the PCK0 on PB26, then the following definition should appear in the - * board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. + * For example, if we wanted the PCK0 on PB26, then the following definition + * should appear in the board.h header file for that board: * * #define PIO_PMC_PCK0 PIO_PMC_PCK0_1 * * The PCK logic will then automatically configure PB26 as the PCK0 pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific PIO options such as frequency, open-drain/push-pull, - * and pull-up/down! Just the basics are defined for most pins in this file at the present time. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific PIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file at the present time. */ /* Analog-to-Digital Converter - ADC */ diff --git a/arch/arm/src/sama5/hardware/sam_adc.h b/arch/arm/src/sama5/hardware/sam_adc.h index ea6d73c282d..fa48bef94ca 100644 --- a/arch/arm/src/sama5/hardware/sam_adc.h +++ b/arch/arm/src/sama5/hardware/sam_adc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ADC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ADC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General definitions ******************************************************************/ + ****************************************************************************/ + +/* General definitions ******************************************************/ #if defined(ATSAMA5D3) # define SAM_ADC_NCHANNELS 12 /* 12 ADC Channels */ @@ -44,7 +45,7 @@ #define SAM_ADC_MAXPERCLK 66000000 /* Maximum peripheral clock frequency */ #define SAM_ADC_CLOCKMAX 20000000 /* Maximum ADC Clock Frequency (Hz) */ -/* ADC register offsets ****************************************************************/ +/* ADC register offsets *****************************************************/ #define SAM_ADC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_ADC_MR_OFFSET 0x0004 /* Mode Register */ @@ -98,7 +99,7 @@ #define SAM_ADC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ /* 0x00ec-fc Reserved */ -/* ADC register addresses **************************************************************/ +/* ADC register addresses ***************************************************/ #define SAM_ADC_CR (SAM_TSADC_VBASE+SAM_ADC_CR_OFFSET) #define SAM_ADC_MR (SAM_TSADC_VBASE+SAM_ADC_MR_OFFSET) @@ -147,7 +148,7 @@ #define SAM_ADC_WPMR (SAM_TSADC_VBASE+SAM_ADC_WPMR_OFFSET) #define SAM_ADC_WPSR (SAM_TSADC_VBASE+SAM_ADC_WPSR_OFFSET) -/* ADC register bit definitions ********************************************************/ +/* ADC register bit definitions *********************************************/ /* Control Register and ADC Control Register common bit-field definitions */ @@ -209,6 +210,7 @@ # define ADC_MR_SETTLING_5 (1 << ADC_MR_SETTLING_SHIFT) /* 5 periods of ADCClock */ # define ADC_MR_SETTLING_9 (2 << ADC_MR_SETTLING_SHIFT) /* 9 periods of ADCClock */ # define ADC_MR_SETTLING_17 (3 << ADC_MR_SETTLING_SHIFT) /* 17 periods of ADCClock */ + # define ADC_MR_ANACH (1 << 23) /* Bit 23: Analog Change */ #endif @@ -275,8 +277,8 @@ #endif /* Channel Enable Register, Channel Disable Register, Channel - * Status Register, ADC Channel Enable Register, ADC Channel Disable Register, - * and ADC Channel Status Register common bit-field definitions + * Status Register, ADC Channel Enable Register, ADC Channel Disable + * Register, and ADC Channel Status Register common bit-field definitions */ #define ADC_CH(n) (1 << (n)) @@ -382,6 +384,7 @@ # define ADC_EMR_CMPMODE_HIGH (1 << ADC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */ # define ADC_EMR_CMPMODE_IN (2 << ADC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */ # define ADC_EMR_CMPMODE_OUT (3 << ADC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */ + #define ADC_EMR_CMPSEL_SHIFT (4) /* Bit 4-7: Comparison Selected Channel */ #define ADC_EMR_CMPSEL_MASK (15 << ADC_EMR_CMPSEL_SHIFT) # define ADC_EMR_CMPSEL(n) ((uint32_t)(n) << ADC_EMR_CMPSEL_SHIFT) @@ -396,6 +399,7 @@ # define ADC_EMR_OSR_NOAVG (0 << ADC_EMR_OSR_SHIFT) /* No averaging */ # define ADC_EMR_OSR_OSR4 (1 << ADC_EMR_OSR_SHIFT) /* 1-bit averaging. ADC sample rate / 4 */ # define ADC_EMR_OSR_OSR16 (2 << ADC_EMR_OSR_SHIFT) /* 2-bit averaging. ADC sample rate / 16 */ + # define ADC_EMR_ASTE (1 << 10) /* Bit 10: Averaging on Single Trigger Event */ #endif @@ -505,12 +509,14 @@ # define ADC_TSMR_TSMODE_4WIRENPM (1 << ADC_TSMR_TSMODE_SHIFT) /* 4-wire TS w/o pressure measurement */ # define ADC_TSMR_TSMODE_4WIRE (2 << ADC_TSMR_TSMODE_SHIFT) /* 4-wire TS w/ pressure measurement */ # define ADC_TSMR_TSMODE_5WIRE (3 << ADC_TSMR_TSMODE_SHIFT) /* 5-wire Touchscreen */ + #define ADC_TSMR_TSAV_SHIFT (4) /* Bit 4-5: Touchscreen Average */ #define ADC_TSMR_TSAV_MASK (3 << ADC_TSMR_TSAV_SHIFT) # define ADC_TSMR_TSAV_NOFILTER (0 << ADC_TSMR_TSAV_SHIFT) /* No Filtering */ # define ADC_TSMR_TSAV_2CONV (1 << ADC_TSMR_TSAV_SHIFT) /* Average 2 ADC conversions */ # define ADC_TSMR_TSAV_4CONV (2 << ADC_TSMR_TSAV_SHIFT) /* Average 4 ADC conversions */ # define ADC_TSMR_TSAV_8CONV (3 << ADC_TSMR_TSAV_SHIFT) /* Averages 8 ADC conversions */ + #define ADC_TSMR_TSFREQ_SHIFT (8) /* Bit 8-11: Touchscreen Frequency */ #define ADC_TSMR_TSFREQ_MASK (15 << ADC_TSMR_TSFREQ_SHIFT) # define ADC_TSMR_TSFREQ_DIV1 (0 << ADC_TSMR_TSFREQ_SHIFT) /* TS freq = trigger freq */ @@ -518,6 +524,7 @@ # define ADC_TSMR_TSFREQ_DIV4 (2 << ADC_TSMR_TSFREQ_SHIFT) /* TS freq = trigger freq / 4 */ # define ADC_TSMR_TSFREQ_DIV8 (3 << ADC_TSMR_TSFREQ_SHIFT) /* TS freq = trigger freq / 8 */ # define ADC_TSMR_TSFREQ(n) ((uint32_t)(n) << ADC_TSMR_TSFREQ_SHIFT) + #define ADC_TSMR_TSSCTIM_SHIFT (16) /* Bit 16-19: Touchscreen Switches Closure Time */ #define ADC_TSMR_TSSCTIM_MASK (15 << ADC_TSMR_TSSCTIM_SHIFT) # define ADC_TSMR_TSSCTIM(n) ((uint32_t)(n) << ADC_TSMR_TSSCTIM_SHIFT) @@ -559,6 +566,7 @@ # define ADC_TRGR_TRGMOD_PEN (4 << ADC_TRGR_TRGMOD_SHIFT) /* Pen Detect Trigger */ # define ADC_TRGR_TRGMOD_PERIOD (5 << ADC_TRGR_TRGMOD_SHIFT) /* Periodic Trigger */ # define ADC_TRGR_TRGMOD_CONT (6 << ADC_TRGR_TRGMOD_SHIFT) /* Continuous Mode */ + #define ADC_TRGR_TRGPER_SHIFT (16) /* Bit 16-31: Trigger Period */ #define ADC_TRGR_TRGPER_MASK (0xffff << ADC_TRGR_TRGPER_SHIFT) # define ADC_TRGR_TRGPER(n) ((uint32_t)(n) << ADC_TRGR_TRGPER_SHIFT) @@ -576,16 +584,16 @@ #define ADC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define ADC_WPSR_WPVSRC_MASK (0xffff << ADC_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ADC_H */ diff --git a/arch/arm/src/sama5/hardware/sam_aic.h b/arch/arm/src/sama5/hardware/sam_aic.h index ec07f7a53be..7fa4cf6ce0a 100644 --- a/arch/arm/src/sama5/hardware/sam_aic.h +++ b/arch/arm/src/sama5/hardware/sam_aic.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_aic.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AIC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AIC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* AIC Register Offsets *************************************************************/ + ****************************************************************************/ + +/* AIC Register Offsets *****************************************************/ #define SAM_AIC_SSR_OFFSET 0x0000 /* Source Select Register */ #define SAM_AIC_SMR_OFFSET 0x0004 /* Source Mode Register */ @@ -62,7 +63,7 @@ #define SAM_AIC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ #define SAM_AIC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ -/* AIC Register Addresses ***********************************************************/ +/* AIC Register Addresses ***************************************************/ #define SAM_AIC_SSR (SAM_AIC_VBASE+SAM_AIC_SSR_OFFSET) #define SAM_AIC_SMR (SAM_AIC_VBASE+SAM_AIC_SMR_OFFSET) @@ -117,7 +118,7 @@ # define SAM_SAIC_WPSR (SAM_SAIC_VBASE+SAM_AIC_WPSR_OFFSET) #endif -/* AIC Register Bit Definitions *****************************************************/ +/* AIC Register Bit Definitions *********************************************/ /* Source Select Register */ @@ -139,7 +140,9 @@ # define AIC_SMR_SRCTYPE_XRISING (3 << AIC_SMR_SRCTYPE_SHIFT) /* External rising edge */ /* Source Vector Register (32-bit address) */ + /* Interrupt Vector Register (32-bit address) */ + /* FIQ Interrupt Vector Register (32-bit address) */ /* Interrupt Status Register */ diff --git a/arch/arm/src/sama5/hardware/sam_aximx.h b/arch/arm/src/sama5/hardware/sam_aximx.h index b213712e6f6..f91352f0d7a 100644 --- a/arch/arm/src/sama5/hardware/sam_aximx.h +++ b/arch/arm/src/sama5/hardware/sam_aximx.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_aximx.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,39 +16,42 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AXIMX_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AXIMX_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* AXIMX Register Offsets ***********************************************************/ + ****************************************************************************/ + +/* AXIMX Register Offsets ***************************************************/ #define SAM_AXIMX_REMAP_OFFSET 0x0000 /* Remap Register */ -/* AXIMX Register Addresses *********************************************************/ +/* AXIMX Register Addresses *************************************************/ #define SAM_AXIMX_REMAP (SAM_AXIMX_VSECTION+SAM_AXIMX_REMAP_OFFSET) -/* AXIMX Register Bit Definitions ***************************************************/ +/* AXIMX Register Bit Definitions *******************************************/ /* Remap Register * * Boot state: ROM is seen at address 0x00000000 - * Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave interface) + * Remap State 0: SRAM is seen at address 0x00000000 + * (through AHB slave interface) * instead of ROM. - * Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave interface) + * Remap State 1: HEBI is seen at address 0x00000000 + * (through AHB slave interface) * instead of ROM for external boot. */ diff --git a/arch/arm/src/sama5/hardware/sam_bsc.h b/arch/arm/src/sama5/hardware/sam_bsc.h index bd146126257..ae0895b57cc 100644 --- a/arch/arm/src/sama5/hardware/sam_bsc.h +++ b/arch/arm/src/sama5/hardware/sam_bsc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_bsc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,30 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_BSC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_BSC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* BSC Register Offsets *************************************************************/ + ****************************************************************************/ + +/* BSC Register Offsets *****************************************************/ #define SAM_BSC_CR_OFFSET 0x0000 /* Boot Sequence Configuration Register */ -/* BSC Register Addresses ***********************************************************/ +/* BSC Register Addresses ***************************************************/ #define SAM_BSC_CR (SAM_BSC_VBASE+SAM_BSC_CR_OFFSET) -/* BSC Register Bit Definitions *****************************************************/ +/* BSC Register Bit Definitions *********************************************/ /* Boot Sequence Configuration Register */ diff --git a/arch/arm/src/sama5/hardware/sam_can.h b/arch/arm/src/sama5/hardware/sam_can.h index ce3c6c14385..2911707dc46 100644 --- a/arch/arm/src/sama5/hardware/sam_can.h +++ b/arch/arm/src/sama5/hardware/sam_can.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_can.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_CAN_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_CAN_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define SAM_CAN_NMAILBOXES 8 #define SAM_CAN_MAXPERCLK 66000000 -/* CAN Register Offsets *************************************************************/ +/* CAN Register Offsets *****************************************************/ #define SAM_CAN_MR_OFFSET 0x0000 /* Mode Register */ #define SAM_CAN_IER_OFFSET 0x0004 /* Interrupt Enable Register */ @@ -71,7 +71,7 @@ #define SAM_CAN_MnDH_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MDH_OFFSET) #define SAM_CAN_MnCR_OFFSET(n) (SAM_CAN_MBn_OFFSET(n)+SAM_CAN_MCR_OFFSET) -/* CAN Register Addresses ***********************************************************/ +/* CAN Register Addresses ***************************************************/ #define SAM_CAN0_MR (SAM_CAN0_VBASE+SAM_CAN_MR_OFFSET) #define SAM_CAN0_IER (SAM_CAN0_VBASE+SAM_CAN_IER_OFFSET) @@ -123,7 +123,7 @@ #define SAM_CAN1_MDH(n) (SAM_CAN1_VBASE+SAM_CAN_MnDH_OFFSET(n)) #define SAM_CAN1_MCR(n) (SAM_CAN1_VBASE+SAM_CAN_MnCR_OFFSET(n)) -/* CAN Register Bit Definitions *****************************************************/ +/* CAN Register Bit Definitions *********************************************/ /* Mode Register */ @@ -136,19 +136,19 @@ #define CAN_MR_TIMFRZ (1 << 6) /* Bit 6: Enable Timer Freeze */ #define CAN_MR_DRPT (1 << 7) /* Bit 7: Disable Repeat */ -/* Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, - * and Status Register +/* Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Status Register */ #define CAN_INT_MB(n) (1 << (n)) /* Bit n: Mailbox n Event */ -#define CAN_INT_MB0 (1 << 0) /* Bit 0: Mailbox 0 Event */ -#define CAN_INT_MB1 (1 << 1) /* Bit 1: Mailbox 1 Event */ -#define CAN_INT_MB2 (1 << 2) /* Bit 2: Mailbox 2 Event */ -#define CAN_INT_MB3 (1 << 3) /* Bit 3: Mailbox 3 Event */ -#define CAN_INT_MB4 (1 << 4) /* Bit 4: Mailbox 4 Event */ -#define CAN_INT_MB5 (1 << 5) /* Bit 5: Mailbox 5 Event */ -#define CAN_INT_MB6 (1 << 6) /* Bit 6: Mailbox 6 Event */ -#define CAN_INT_MB7 (1 << 7) /* Bit 7: Mailbox 7 Event */ +#define CAN_INT_MB0 (1 << 0) /* Bit 0: Mailbox 0 Event */ +#define CAN_INT_MB1 (1 << 1) /* Bit 1: Mailbox 1 Event */ +#define CAN_INT_MB2 (1 << 2) /* Bit 2: Mailbox 2 Event */ +#define CAN_INT_MB3 (1 << 3) /* Bit 3: Mailbox 3 Event */ +#define CAN_INT_MB4 (1 << 4) /* Bit 4: Mailbox 4 Event */ +#define CAN_INT_MB5 (1 << 5) /* Bit 5: Mailbox 5 Event */ +#define CAN_INT_MB6 (1 << 6) /* Bit 6: Mailbox 6 Event */ +#define CAN_INT_MB7 (1 << 7) /* Bit 7: Mailbox 7 Event */ #define CAN_INT_MBALL (0x000000ff) #define CAN_INT_ERRA (1 << 16) /* Bit 16: Error Active Mode */ @@ -188,7 +188,7 @@ #define CAN_BR_BRP_SHIFT (16) /* Bits 16-22: Baudrate Prescaler */ #define CAN_BR_BRP_MASK (0x7f << CAN_BR_BRP_SHIFT) # define CAN_BR_BRP(n) ((uint32_t)(n) << CAN_BR_BRP_SHIFT) -#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode */ +#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode */ # define CAN_BR_ONCE (0) /* Bit 24: 0:Bit stream sampled once at sample point */ # define CAN_BR_THREE CAN_BR_SMP /* Bit 24: 1:Sampling three times */ @@ -210,6 +210,7 @@ /* Transfer Command Register */ #define CAN_TCR_MB(n) (1 << (n)) /* Bit n: Transfer Request for Mailbox n */ + #define CAN_TCR_MB0 (1 << 0) /* Bit 0: Transfer Request for Mailbox 0 */ #define CAN_TCR_MB1 (1 << 1) /* Bit 1: Transfer Request for Mailbox 1 */ #define CAN_TCR_MB2 (1 << 2) /* Bit 2: Transfer Request for Mailbox 2 */ @@ -223,6 +224,7 @@ /* Abort Command Register */ #define CAN_ACR_MB(n) (1 << (n)) /* Bit n: Abort Request for Mailbox n */ + #define CAN_ACR_MB0 (1 << 0) /* Bit 0: Abort Request for Mailbox 0 */ #define CAN_ACR_MB1 (1 << 1) /* Bit 1: Abort Request for Mailbox 1 */ #define CAN_ACR_MB2 (1 << 2) /* Bit 2: Abort Request for Mailbox 2 */ diff --git a/arch/arm/src/sama5/hardware/sam_dbgu.h b/arch/arm/src/sama5/hardware/sam_dbgu.h index 757f1188d90..2018aa26ff2 100644 --- a/arch/arm/src/sama5/hardware/sam_dbgu.h +++ b/arch/arm/src/sama5/hardware/sam_dbgu.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_dbgu.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DBGU_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DBGU_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* DBGU register offsets ************************************************************************/ +/* DBGU register offsets ****************************************************/ #define SAM_DBGU_CR_OFFSET 0x0000 /* Control Register */ #define SAM_DBGU_MR_OFFSET 0x0004 /* Mode Register */ @@ -51,7 +51,7 @@ #define SAM_DBGU_FNR_OFFSET 0x0048 /* Force NTRST Register */ /* 0x004c-0x00fc: Reserved */ -/* DBGU register addresses **********************************************************************/ +/* DBGU register addresses **************************************************/ #define SAM_DBGU_CR (SAM_DBGU_VBASE+SAM_DBGU_CR_OFFSET) #define SAM_DBGU_MR (SAM_DBGU_VBASE+SAM_DBGU_MR_OFFSET) @@ -66,7 +66,7 @@ #define SAM_DBGU_EXID (SAM_DBGU_VBASE+SAM_DBGU_EXID_OFFSET) #define SAM_DBGU_FNR (SAM_DBGU_VBASE+SAM_DBGU_FNR_OFFSET) -/* DBGU register bit definitions ****************************************************************/ +/* DBGU register bit definitions ********************************************/ /* DBGU Control Register */ @@ -91,6 +91,7 @@ # define DBGU_MR_PAR_SPACE (2 << DBGU_MR_PAR_SHIFT) /* Space: parity forced to 0 */ # define DBGU_MR_PAR_MARK (3 << DBGU_MR_PAR_SHIFT) /* Mark: parity forced to 1 */ # define DBGU_MR_PAR_NONE (4 << DBGU_MR_PAR_SHIFT) /* No parity */ + #define DBGU_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */ #define DBGU_MR_CHMODE_MASK (3 << DBGU_MR_CHMODE_SHIFT) # define DBGU_MR_CHMODE_NORMAL (0 << DBGU_MR_CHMODE_SHIFT) /* Normal Mode */ @@ -98,7 +99,8 @@ # define DBGU_MR_CHMODE_LLPBK (2 << DBGU_MR_CHMODE_SHIFT) /* Local Loopback */ # define DBGU_MR_CHMODE_RLPBK (3 << DBGU_MR_CHMODE_SHIFT) /* Remote Loopback */ -/* DBGU Interrupt Enable Register, DBGU Interrupt Disable Register, DBGU Interrupt Mask +/* DBGU Interrupt Enable Register, + * DBGU Interrupt Disable Register, DBGU Interrupt Mask * Register, and DBGU Status Register common bit field definitions */ @@ -142,6 +144,7 @@ # define DBGU_CIDR_EPROC_ARM920T (4 << DBGU_CIDR_EPROC_SHIFT) /* ARM920T */ # define DBGU_CIDR_EPROC_ARM926EJS (5 << DBGU_CIDR_EPROC_SHIFT) /* ARM926EJS */ # define DBGU_CIDR_EPROC_CA5 (6 << DBGU_CIDR_EPROC_SHIFT) /* Cortex-A5 */ + #define DBGU_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */ #define DBGU_CIDR_NVPSIZ_MASK (15 << DBGU_CIDR_NVPSIZ_SHIFT) # define DBGU_CIDR_NVPSIZ_NONE (0 << DBGU_CIDR_NVPSIZ_SHIFT) /* None */ @@ -154,6 +157,7 @@ # define DBGU_CIDR_NVPSIZ_512K (10 << DBGU_CIDR_NVPSIZ_SHIFT) /* 512 Kbytes */ # define DBGU_CIDR_NVPSIZ_1M (12 << DBGU_CIDR_NVPSIZ_SHIFT) /* 1024 Kbytes */ # define DBGU_CIDR_NVPSIZ_2M (14 << DBGU_CIDR_NVPSIZ_SHIFT) /* 2048 Kbytes */ + #define DBGU_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Second Nonvolatile Program Memory Size */ #define DBGU_CIDR_NVPSIZ2_MASK (15 << DBGU_CIDR_NVPSIZ2_SHIFT) # define DBGU_CIDR_NVPSIZ2_NONE (0 << DBGU_CIDR_NVPSIZ2_SHIFT) /* None */ @@ -166,6 +170,7 @@ # define DBGU_CIDR_NVPSIZ2_512K (10 << DBGU_CIDR_NVPSIZ2_SHIFT) /* 512 Kbytes */ # define DBGU_CIDR_NVPSIZ2_1M (12 << DBGU_CIDR_NVPSIZ2_SHIFT) /* 1024 Kbytes */ # define DBGU_CIDR_NVPSIZ2_2M (14 << DBGU_CIDR_NVPSIZ2_SHIFT) /* 2048 Kbytes */ + #define DBGU_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */ #define DBGU_CIDR_SRAMSIZ_MASK (15 << DBGU_CIDR_SRAMSIZ_SHIFT) # define DBGU_CIDR_SRAMSIZ_1K (1 << DBGU_CIDR_SRAMSIZ_SHIFT) /* 1 Kbytes */ @@ -183,6 +188,7 @@ # define DBGU_CIDR_SRAMSIZ_256K (13 << DBGU_CIDR_SRAMSIZ_SHIFT) /* 256 Kbytes */ # define DBGU_CIDR_SRAMSIZ_96K (14 << DBGU_CIDR_SRAMSIZ_SHIFT) /* 96 Kbytes */ # define DBGU_CIDR_SRAMSIZ_512K (15 << DBGU_CIDR_SRAMSIZ_SHIFT) /* 512 Kbytes */ + #define DBGU_CIDR_ARCH_SHIFT (20) /* Bits 20-23: Architecture Identifier */ #define DBGU_CIDR_ARCH_MASK (15 << DBGU_CIDR_ARCH_SHIFT) # define DBGU_CIDR_ARCH_AT91SAM9xx (0x19 << DBGU_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */ @@ -221,6 +227,7 @@ # define DBGU_CIDR_ARCH_ATSAM3SDxC (0x9a << DBGU_CIDR_ARCH_SHIFT) /* ATSAM3SDxC Series (100-pin) */ # define DBGU_CIDR_ARCH_ATSAMA5xx (0xa5 << DBGU_CIDR_ARCH_SHIFT) /* ATSAMA5xx Series */ # define DBGU_CIDR_ARCH_AT75Cxx (0xf0 << DBGU_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ + #define DBGU_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ #define DBGU_CIDR_NVPTYP_MASK (7 << DBGU_CIDR_NVPTYP_SHIFT) # define DBGU_CIDR_NVPTYP_ROM (0 << DBGU_CIDR_NVPTYP_SHIFT) /* ROM */ @@ -228,6 +235,7 @@ # define DBGU_CIDR_NVPTYP_SRAM (4 << DBGU_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ # define DBGU_CIDR_NVPTYP_FLASH (2 << DBGU_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ # define DBGU_CIDR_NVPTYP_ROMFLASH (3 << DBGU_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ + #define DBGU_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ /* Chip ID Extension Register (32-bit ID */ @@ -236,16 +244,16 @@ #define DBGU_FNR_FNTRST (1 << 0) /* Bit 0: Force NTRST */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DBGU_H */ diff --git a/arch/arm/src/sama5/hardware/sam_dmac.h b/arch/arm/src/sama5/hardware/sam_dmac.h index 6cc3bdf9734..5f840161a04 100644 --- a/arch/arm/src/sama5/hardware/sam_dmac.h +++ b/arch/arm/src/sama5/hardware/sam_dmac.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DMAC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DMAC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* DMAC register offsets ****************************************************************/ +/* DMAC register offsets ****************************************************/ /* Global Registers */ @@ -52,6 +52,7 @@ #define SAM_DMAC_CHDR_OFFSET 0x002c /* DMAC Channel Handler Disable Register */ #define SAM_DMAC_CHSR_OFFSET 0x0030 /* DMAC Channel Handler Status Register */ /* 0x034-0x38: Reserved */ + /* DMA channel registers */ #define SAM_DMAC_CH_OFFSET(n) (0x003c+((n)*0x0028)) @@ -77,7 +78,8 @@ #define SAM_DMAC_WPSR_OFFSET 0x01e8 /* DMAC Write Protect Status Register */ /* 0x01ec-0x1fc: Reserved */ -/* DMAC0 register addresses *************************************************************/ +/* DMAC0 register addresses *************************************************/ + /* DMAC0 Global Registers */ #define SAM_DMAC0_GCFG (SAM_DMAC0_VBASE+SAM_DMAC_GCFG_OFFSET) @@ -189,7 +191,8 @@ #define SAM_DMAC0_CH7_SPIP (SAM_DMAC0_CH7_BASE+SAM_DMAC_CH_SPIP_OFFSET) #define SAM_DMAC0_CH7_DPIP (SAM_DMAC0_CH7_BASE+SAM_DMAC_CH_DPIP_OFFSET) -/* DMAC1 register addresses *************************************************************/ +/* DMAC1 register addresses *************************************************/ + /* DMAC1 Global Registers */ #define SAM_DMAC1_GCFG (SAM_DMAC1_VBASE+SAM_DMAC_GCFG_OFFSET) @@ -301,7 +304,7 @@ #define SAM_DMAC1_CH7_SPIP (SAM_DMAC1_CH7_BASE+SAM_DMAC_CH_SPIP_OFFSET) #define SAM_DMAC1_CH7_DPIP (SAM_DMAC1_CH7_BASE+SAM_DMAC_CH_DPIP_OFFSET) -/* DMAC register bit definitions ********************************************************/ +/* DMAC register bit definitions ********************************************/ /* Global Registers */ @@ -442,11 +445,14 @@ # define DMAC_LAST_DLAST6 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST6_SHIFT)) # define DMAC_LAST_DLAST7 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST7_SHIFT)) -/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register, - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register, - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common - * bit field definitions +/* DMAC Error, Buffer Transfer and Chained Buffer Transfer + * Interrupt Enable Register, + * DMAC Error, Buffer Transfer and Chained Buffer Transfer + * Interrupt Disable Register, + * DMAC Error, Buffer Transfer and Chained Buffer Transfer + * Interrupt Mask Register, and + * DMAC Error, Buffer Transfer and Chained Buffer Transfer + * Status Register common bit field definitions */ #define DMAC_EBC_BTC_SHIFT (0) /* Bits 0-7: Buffer Transfer Completed */ @@ -609,7 +615,9 @@ # define DMAC_CHSR_STAL7 (1 << (DMAC_CHSR_STAL_SHIFT+7)) /* DMA channel registers */ + /* DMAC Channel x [x = 0..7] Source Address Register (32-bit address) */ + /* DMAC Channel x [x = 0..7] Destination Address Register (32-bit address) */ /* DMAC Channel x [x = 0..7] Descriptor Address Register */ @@ -619,6 +627,7 @@ # define DMAC_CH_DSCR_AHB_IF0 (0 << DMAC_CH_DSCR_IF_SHIFT) /* Fetched via AHB-Lite Interface 0 */ # define DMAC_CH_DSCR_AHB_IF1 (1 << DMAC_CH_DSCR_IF_SHIFT) /* Fetched via AHB-Lite Interface 1 */ # define DMAC_CH_DSCR_AHB_IF2 (2 << DMAC_CH_DSCR_IF_SHIFT) /* Fetched via AHB-Lite Interface 2 */ + #define DMAC_CH_DSCR_MASK (0xfffffffc) /* Bits 2-31: Buffer Transfer Descriptor Address */ /* DMAC Channel n [n = 0..7] Control A Register */ @@ -659,11 +668,13 @@ # define DMAC_CH_CTRLB_SIF_IF0 (0 << DMAC_CH_CTRLB_SIF_SHIFT) /* Via AHB-Lite Interface 0 */ # define DMAC_CH_CTRLB_SIF_IF1 (1 << DMAC_CH_CTRLB_SIF_SHIFT) /* Via AHB-Lite Interface 1 */ # define DMAC_CH_CTRLB_SIF_IF2 (2 << DMAC_CH_CTRLB_SIF_SHIFT) /* Via AHB-Lite Interface 2 */ + #define DMAC_CH_CTRLB_DIF_SHIFT (4) /* Bits 4-5: Destination Interface Selection Field */ #define DMAC_CH_CTRLB_DIF_MASK (3 << DMAC_CH_CTRLB_DIF_SHIFT) # define DMAC_CH_CTRLB_DIF_IF0 (0 << DMAC_CH_CTRLB_DIF_SHIFT) /* Via AHB-Lite Interface 0 */ # define DMAC_CH_CTRLB_DIF_IF1 (1 << DMAC_CH_CTRLB_DIF_SHIFT) /* Via AHB-Lite Interface 1 */ # define DMAC_CH_CTRLB_DIF_IF2 (2 << DMAC_CH_CTRLB_DIF_SHIFT) /* Via AHB-Lite Interface 2 */ + #define DMAC_CH_CTRLB_SRC_PIP (1 << 8) /* Bit 8: Source Picture-in-Picture Mode */ #define DMAC_CH_CTRLB_DST_PIP (1 << 12) /* Bit 12: Destination Picture-in-Picture Mode */ #define DMAC_CH_CTRLB_SRCDSCR (1 << 16) /* Bit 16: Source buffer descriptor fetch operation disabled */ @@ -674,16 +685,19 @@ # define DMAC_CH_CTRLB_FC_M2P (1 << DMAC_CH_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */ # define DMAC_CH_CTRLB_FC_P2M (2 << DMAC_CH_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */ # define DMAC_CH_CTRLB_FC_P2P (3 << DMAC_CH_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */ + #define DMAC_CH_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */ #define DMAC_CH_CTRLB_SRCINCR_MASK (3 << DMAC_CH_CTRLB_SRCINCR_SHIFT) # define DMAC_CH_CTRLB_SRCINCR_INCR (0 << DMAC_CH_CTRLB_SRCINCR_SHIFT) /* Incrementing address */ # define DMAC_CH_CTRLB_SRCINCR_DECR (1 << DMAC_CH_CTRLB_SRCINCR_SHIFT) /* Decrementing address */ # define DMAC_CH_CTRLB_SRCINCR_FIXED (2 << DMAC_CH_CTRLB_SRCINCR_SHIFT) /* Fixed address */ + #define DMAC_CH_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */ #define DMAC_CH_CTRLB_DSTINCR_MASK (3 << DMAC_CH_CTRLB_DSTINCR_SHIFT) # define DMAC_CH_CTRLB_DSTINCR_INCR (0 << DMAC_CH_CTRLB_DSTINCR_SHIFT) /* Incrementing address */ # define DMAC_CH_CTRLB_DSTINCR_DECR (1 << DMAC_CH_CTRLB_DSTINCR_SHIFT) /* Decrementing address */ # define DMAC_CH_CTRLB_DSTINCR_FIXED (2 << DMAC_CH_CTRLB_DSTINCR_SHIFT) /* Fixed address */ + #define DMAC_CH_CTRLB_IEN (1 << 30) /* Bit 30: Interrupt Enable Not */ #define DMAC_CH_CTRLB_AUTO (1 << 31) /* Bit 31: Automatic Multiple Buffer Transfer*/ @@ -705,25 +719,31 @@ #define DMAC_CH_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */ #define DMAC_CH_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */ #define DMAC_CH_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */ + #define DMAC_CH_CFG_AHBPROT_SHIFT (24) /* Bits 24-26: AHB access privilege */ #define DMAC_CH_CFG_AHBPROT_MASK (7 << DMAC_CH_CFG_AHBPROT_SHIFT) # define DMAC_CH_CFG_AHBPROT_PRIV (1 << DMAC_CH_CFG_AHBPROT_SHIFT) /* Privileged Access */ # define DMAC_CH_CFG_AHBPROT_BUFF (2 << DMAC_CH_CFG_AHBPROT_SHIFT) /* Bufferable */ # define DMAC_CH_CFG_AHBPROT_CACHE (4 << DMAC_CH_CFG_AHBPROT_SHIFT) /* Cacheable */ + #define DMAC_CH_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29: FIFO Configuration */ #define DMAC_CH_CFG_FIFOCFG_MASK (3 << DMAC_CH_CFG_FIFOCFG_SHIFT) # define DMAC_CH_CFG_FIFOCFG_ALAP (0 << DMAC_CH_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */ # define DMAC_CH_CFG_FIFOCFG_HALF (1 << DMAC_CH_CFG_FIFOCFG_SHIFT) /* Half FIFO size */ # define DMAC_CH_CFG_FIFOCFG_ASAP (2 << DMAC_CH_CFG_FIFOCFG_SHIFT) /* Single AHB access ASAP */ -/* DMAC Channel n [n = 0..7] Source Picture-in-Picture Configuration Register */ +/* DMAC Channel n [n = 0..7] + * Source Picture-in-Picture Configuration Register + */ #define DMAC_CH_SPIP_HOLE_SHIFT (0) /* Bits 0-15: Source Picture-in-Picture Hole */ #define DMAC_CH_SPIP_HOLE_MASK (0xffff << DMAC_CH_SPIP_HOLE_SHIFT) #define DMAC_CH_SPIP_BOUNDARY_SHIFT (16) /* Bits 16-25: Source Picture-in-Picture Boundary */ #define DMAC_CH_SPIP_BOUNDARY_MASK (0x3ff << DMAC_CH_SPIP_BOUNDARY_SHIFT) -/* DMAC Channel n [n = 0..7] Destination Picture-in-Picture Configuration Register */ +/* DMAC Channel n [n = 0..7] + * Destination Picture-in-Picture Configuration Register + */ #define DMAC_CH_DPIP_HOLE_SHIFT (0) /* Bits 0-15: Destination Picture-in-Picture Hole */ #define DMAC_CH_DPIP_HOLE_MASK (0xffff << DMAC_CH_DPIP_HOLE_SHIFT) @@ -743,7 +763,8 @@ #define DMAC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define DMAC_WPSR_WPVSRC_MASK (0xffff << DMAC_WPSR_WPVSRC_SHIFT) -/* DMA Channel Definitions **************************************************************/ +/* DMA Channel Definitions **************************************************/ + /* DMA Controller 0 Channel Definitions */ #define DMAC0_CH_HSMCI0 (0) /* HSMCI0 Receive/transmit */ @@ -789,9 +810,9 @@ #define DMAC1_CH_TDES_TX (20) /* TDES Transmit */ #define DMAC1_CH_TDES_RX (21) /* TDES Receive */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ /* DMA multi buffer transfer link list entry structure */ @@ -816,12 +837,12 @@ struct dma_crc16_linklist_s uint32_t crc16; /* 20 CRC */ }; -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DMAC_H */ diff --git a/arch/arm/src/sama5/hardware/sam_ehci.h b/arch/arm/src/sama5/hardware/sam_ehci.h index a477d8e7bf7..e67fba833e1 100644 --- a/arch/arm/src/sama5/hardware/sam_ehci.h +++ b/arch/arm/src/sama5/hardware/sam_ehci.h @@ -34,11 +34,13 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* The SAMA5 supports 3 root hub ports */ #define SAM_EHCI_NRHPORT 3 /* Registers ****************************************************************/ + /* Traditionally, NuttX specifies register locations using individual * register offsets from a base address. That tradition is broken here and, * instead, register blocks are represented as structures. This is done here @@ -75,7 +77,7 @@ ****************************************************************************/ /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EHCI_H */ diff --git a/arch/arm/src/sama5/hardware/sam_emac.h b/arch/arm/src/sama5/hardware/sam_emac.h index 77dce575e24..2cf34d6a3be 100644 --- a/arch/arm/src/sama5/hardware/sam_emac.h +++ b/arch/arm/src/sama5/hardware/sam_emac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_emac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMAC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* These two EMAC implementations differ in naming and in register layout but are - * functionally equivalent. Here they are distinguished as 'A' and 'B'. For now, - * the 'A' and 'B' drivers are kept separate (mostly because the 'B' driver needs - * to support two EMAC blocks. But the 'B' driver should replace the 'A' driver - * someday. +/* These two EMAC implementations differ in naming and in register layout but + * are functionally equivalent. Here they are distinguished as 'A' and 'B'. + * For now, the 'A' and 'B' drivers are kept separate (mostly because the 'B' + * driver needs to support two EMAC blocks. + * But the 'B' driver should replace the 'A' driver someday. */ #if defined(CONFIG_SAMA5_EMACA) diff --git a/arch/arm/src/sama5/hardware/sam_emaca.h b/arch/arm/src/sama5/hardware/sam_emaca.h index b1b3e7663c5..c6d65aebabe 100644 --- a/arch/arm/src/sama5/hardware/sam_emaca.h +++ b/arch/arm/src/sama5/hardware/sam_emaca.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_emaca.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACA_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACA_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* EMAC Register Offsets ************************************************************/ + ****************************************************************************/ + +/* EMAC Register Offsets ****************************************************/ #define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */ #define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */ @@ -82,7 +83,7 @@ #define SAM_EMAC_WOL_OFFSET 0x00c4 /* Wake on LAN Register */ /* 0x00c8-0x00fc Reserved */ -/* EMAC Register Addresses **********************************************************/ +/* EMAC Register Addresses **************************************************/ #define SAM_EMAC_NCR (SAM_EMAC_VBASE+SAM_EMAC_NCR_OFFSET) #define SAM_EMAC_NCFGR (SAM_EMAC_VBASE+SAM_EMAC_NCFGR_OFFSET) @@ -131,7 +132,7 @@ #define SAM_EMAC_USRIO (SAM_EMAC_VBASE+SAM_EMAC_USRIO_OFFSET) #define SAM_EMAC_WOL (SAM_EMAC_VBASE+SAM_EMAC_WOL_OFFSET) -/* EMAC Register Bit Definitions ****************************************************/ +/* EMAC Register Bit Definitions ********************************************/ /* Network Control Register */ @@ -163,6 +164,7 @@ # define EMAC_NCFGR_CLK_DIV16 (1 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 16 (MCK up to 40 MHz) */ # define EMAC_NCFGR_CLK_DIV32 (2 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 32 (MCK up to 80 MHz) */ # define EMAC_NCFGR_CLK_DIV64 (3 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */ + #define EMAC_NCFGR_RTY (1 << 12) /* Bit 12: Retry test */ #define EMAC_NCFGR_PAE (1 << 13) /* Bit 13: Pause Enable */ #define EMAC_NCFGR_RBOF_SHIFT (14) /* Bits 14-15: Receive Buffer Offset */ @@ -171,6 +173,7 @@ # define EMAC_NCFGR_RBOF_1 (1 << EMAC_NCFGR_RBOF_SHIFT) /* One-byte offset from RX buffer start */ # define EMAC_NCFGR_RBOF_2 (2 << EMAC_NCFGR_RBOF_SHIFT) /* Two-byte offset from RX buffer start */ # define EMAC_NCFGR_RBOF_3 (3 << EMAC_NCFGR_RBOF_SHIFT) /* Three-byte offset fromRX buffer start */ + #define EMAC_NCFGR_RLCE (1 << 16) /* Bit 16: Receive Length field Checking Enable */ #define EMAC_NCFGR_DRFCS (1 << 17) /* Bit 17: Discard Receive FCS */ #define EMAC_NCFGR_EFRHD (1 << 18) /* Bit 18: Enable RX frames in HD mode while transmitting */ @@ -205,7 +208,11 @@ #define EMAC_RSR_REC (1 << 1) /* Bit 1: Frame Received */ #define EMAC_RSR_OVR (1 << 2) /* Bit 2: Receive Overrun */ -/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) */ +/* Interrupt Status Register (ISR), + * Interrupt Enable Register (IER), + * Interrupt Disable Register (IDR) + * and Interrupt Mask Register (IMR) + */ #define EMAC_INT_MFD (1 << 0) /* Bit 0: Management Frame Done */ #define EMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */ @@ -331,24 +338,29 @@ #define EMAC_RLE_MASK (0x000000ff) /* Bits 0-7: Receive Length Field Mismatch */ /* Hash Register Bottom [31:0] Register (LS 32-bit hash address) */ + /* Hash Register Top [63:32] Register (MS 32-bit hash address) */ /* Specific Address 1 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 1 Top [47:32] Register */ #define EMAC_SA1T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 2 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 2 Top [47:32] Register */ #define EMAC_SA2T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 3 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 3 Top [47:32] Register */ #define EMAC_SA3T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 4 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 4 Top [47:32] Register */ #define EMAC_SA4T_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ @@ -371,12 +383,12 @@ #define EMAC_WOL_SA1 (1 << 18) /* Bit 18: Specific address register 1 event enable */ #define EMAC_WOL_MTI (1 << 19) /* Bit 19: Multicast hash event enable */ -/* Descriptors **********************************************************************/ +/* Descriptors **************************************************************/ /* Receive buffer descriptor: Address word */ -#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */ -#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ +#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */ +#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ #define EMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */ /* Receive buffer descriptor: Control word */ @@ -419,9 +431,10 @@ #define EMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */ #define EMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the EMAC to read from buffer */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* Receive buffer descriptor */ struct emac_rxdesc_s diff --git a/arch/arm/src/sama5/hardware/sam_emacb.h b/arch/arm/src/sama5/hardware/sam_emacb.h index ace0124447f..f27a803db39 100644 --- a/arch/arm/src/sama5/hardware/sam_emacb.h +++ b/arch/arm/src/sama5/hardware/sam_emacb.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_emacb.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,27 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/* This is the form of the EMAC interface used the SAMA5D4 (and also the SAM43). - * This is referred as GMAC in the documentation even though it does not support - * Gibabit Ethernet. +/* This is the form of the EMAC interface used the SAMA5D4 (and also the + * SAM43). This is referred as GMAC in the documentation even though it does + * not support Gibabit Ethernet. */ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACB_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACB_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* EMAC Register Offsets ************************************************************/ + ****************************************************************************/ + +/* EMAC Register Offsets ****************************************************/ #define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */ #define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */ @@ -76,6 +77,7 @@ #define SAM_EMAC_SAMB1_OFFSET 0x00c8 /* Specific Address 1 Mask Bottom [31:0] Register */ #define SAM_EMAC_SAMT1_OFFSET 0x00cc /* Specific Address 1 Mask Top [47:32] Register */ /* 0x00fc: Reserved */ + /* Statistics registers */ #define SAM_EMAC_OTLO_OFFSET 0x0100 /* Octets Transmitted [31:0] Register */ @@ -142,7 +144,7 @@ #define SAM_EMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */ /* 0x0280-0x0298: Reserved */ -/* EMAC Register Addresses **********************************************************/ +/* EMAC Register Addresses **************************************************/ #ifdef CONFIG_SAMA5_EMAC0 /* EMAC0 base addresses */ @@ -354,7 +356,7 @@ # define SAM_EMAC1_PEFRN (SAM_EMAC1_BASE+SAM_EMAC_PEFRN_OFFSET) #endif -/* EMAC Register Bit Definitions ****************************************************/ +/* EMAC Register Bit Definitions ********************************************/ /* Network Control Register */ @@ -395,6 +397,7 @@ # define EMAC_NCFGR_RXBUFO_1 (1 << EMAC_NCFGR_RXBUFO_SHIFT) /* One-byte offset from RX buffer start */ # define EMAC_NCFGR_RXBUFO_2 (2 << EMAC_NCFGR_RXBUFO_SHIFT) /* Two-byte offset from RX buffer start */ # define EMAC_NCFGR_RXBUFO_3 (3 << EMAC_NCFGR_RXBUFO_SHIFT) /* Three-byte offset fromRX buffer start */ + #define EMAC_NCFGR_LFERD (1 << 16) /* Bit 16: Length Field Error Frame Discard */ #define EMAC_NCFGR_RFCS (1 << 17) /* Bit 17: Remove FCS */ #define EMAC_NCFGR_CLK_SHIFT (18) /* Bits 18-20: MDC clock divider */ @@ -405,9 +408,11 @@ # define EMAC_NCFGR_CLK_DIV48 (3 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */ # define EMAC_NCFGR_CLK_DIV64 (4 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */ # define EMAC_NCFGR_CLK_DIV96 (5 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */ + #define EMAC_NCFGR_DBW_SHIFT (21) /* Bit 21-22: Data Bus Width */ #define EMAC_NCFGR_DBW_MASK (3 << EMAC_NCFGR_DBW_SHIFT) # define EMAC_NCFGR_DBW_ZERO (0 << EMAC_NCFGR_DBW_SHIFT) /* Must be zero */ + #define EMAC_NCFGR_DCPF (1 << 23) /* Bit 23: Disable Copy of Pause Frames */ #define EMAC_NCFGR_RXCOEN (1 << 24) /* Bit 24: Receive Checksum Offload Enable */ #define EMAC_NCFGR_EFRHD (1 << 25) /* Bit 25: Enable Frames Received in Half Duplex */ @@ -429,10 +434,11 @@ #define EMAC_DCFGR_FBLDO_SHIFT (0) /* Bits 0-4: Fixed Burst Length for DMA Data Operations */ #define EMAC_DCFGR_FBLDO_MASK (31 << EMAC_DCFGR_FBLDO_SHIFT) -# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */ -# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */ -# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */ +# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */ +# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */ +# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */ # define EMAC_DCFGR_FBLDO_INCR16 (16 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR16 AHB bursts */ + #define EMAC_DCFGR_ESMA (1 << 6) /* Bit 6: Endian Swap Mode Enable for Management Descriptor Accesses */ #define EMAC_DCFGR_ESPA (1 << 7) /* Bit 7: Endian Swap Mode Enable for Packet Data Accesses */ #define EMAC_DCFGR_DRBS_SHIFT (16) /* Bits 16-23: DMA Receive Buffer Size */ @@ -465,7 +471,11 @@ #define EMAC_RSR_RXOVR (1 << 2) /* Bit 2: Receive Overrun */ #define EMAC_RSR_HNO (1 << 3) /* Bit 3: HRESP Not OK */ -/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) */ +/* Interrupt Status Register (ISR), + * Interrupt Enable Register (IER), + * Interrupt Disable Register (IDR) + * and Interrupt Mask Register (IMR) + */ #define EMAC_INT_MFS (1 << 0) /* Bit 0: Management Frame Sent */ #define EMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */ @@ -525,24 +535,29 @@ #define EMAC_TPQ_MASK (0x0000ffff) /* Bits 0-15: Transmit Pause Quantum */ /* Hash Register Bottom [31:0] Register (LS 32-bit hash address) */ + /* Hash Register Top [63:32] Register (MS 32-bit hash address) */ /* Specific Address 1 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 1 Top [47:32] Register */ #define EMAC_SAT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 2 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 2 Top [47:32] Register */ #define EMAC_SAT2_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 3 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 3 Top [47:32] Register */ #define EMAC_SAT3_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 4 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 4 Top [47:32] Register */ #define EMAC_SAT4_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ @@ -584,6 +599,7 @@ #define EMAC_TPFCP_PQ_MASK (0xff << EMAC_TPFCP_PQ_SHIFT) /* Specific Address 1 Mask Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 1 Mask Top [47:32] Register (MS 16-bit address) */ #define EMAC_SAMT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of Specific Address 1 Mask */ @@ -640,11 +656,13 @@ /* PTP/1588 Timer Registers */ /* 1588 Timer Sync Strobe Seconds Register (32-bit timer value) */ + /* 1588 Timer Sync Strobe Nanoseconds Register (30-bit timer value) */ #define EMAC_TSSN_MASK (0x3fffffff) /* Bit 0-29: Value Timer Nanoseconds Register Capture */ /* 1588 Timer Seconds Register (32-bit timer value) */ + /* 1588 Timer Nanoseconds Register (30-bit timer value) */ #define EMAC_TN_MASK (0x3fffffff) /* Bit 0-29: Timer Count in Nanoseconds */ @@ -669,31 +687,35 @@ # define EMAC_TI_NIT(n) ((uint32_t)(n) << EMAC_TI_NIT_SHIFT) /* PTP Event Frame Transmitted Seconds (32-bit timer value) */ + /* PTP Event Frame Transmitted Nanoseconds (30-bit timer value) */ #define EMAC_EFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Event Frame Received Seconds (32-bit timer value) */ + /* PTP Event Frame Received Nanoseconds (30-bit timer value) */ #define EMAC_EFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Peer Event Frame Transmitted Seconds (32-bit timer value) */ + /* PTP Peer Event Frame Transmitted Nanoseconds (30-bit timer value) */ #define EMAC_PEFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Peer Event Frame Received Seconds (32-bit timer value) */ + /* PTP Peer Event Frame Received Nanoseconds (30-bit timer value) */ #define EMAC_PEFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ -/* Descriptors **********************************************************************/ +/* Descriptors **************************************************************/ /* Receive buffer descriptor: Address word */ -#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */ -#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ +#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */ +#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ #define EMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */ /* Receive buffer descriptor: Control word */ @@ -710,20 +732,22 @@ #define EMACRXD_STA_VLPRIO_MASK (7 << EMACRXD_STA_VLANPRIO_SHIFT) #define EMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */ #define EMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */ -#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */ +#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */ #define EMACRXD_STA_TYPEID_MASK (3 << EMACRXD_STA_TYPEID_SHIFT) # define EMACRXD_STA_TYPEID1 (0 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 1 match */ # define EMACRXD_STA_TYPEID2 (1 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 2 match */ # define EMACRXD_STA_TYPEID3 (2 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 3 match */ # define EMACRXD_STA_TYPEID4 (3 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 4 match */ + #define EMACRXD_STA_TYPEIDMATCH (1 << 24) /* Bit 24: Type ID register match found */ #define EMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */ -#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */ +#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */ #define EMACRXD_STA_ADDR_MASK (3 << EMACRXD_STA_ADDR_SHIFT) # define EMACRXD_STA_ADDR1 (0 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */ # define EMACRXD_STA_ADDR2 (1 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ # define EMACRXD_STA_ADDR3 (2 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ # define EMACRXD_STA_ADDR4 (3 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ + #define EMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific address match found */ /* Bit 28: Reserved */ #define EMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */ @@ -731,6 +755,7 @@ #define EMACRXD_STA_BCAST (1 << 31) /* Bit 31: Global all ones broadcast address detected */ /* Transmit buffer descriptor: Address word (un-aligned, 32-bit address */ + /* Transmit buffer descriptor: Control word */ #define EMACTXD_STA_BUFLEN_SHIFT (0) /* Bits 0-13: Length of buffer */ @@ -749,6 +774,7 @@ # define EMACTXD_STA_CHKERR_BADFRAG (5 << EMACTXD_STA_CHKERR_SHIFT) /* Unsupported fragmentation */ # define EMACTXD_STA_CHKERR_PKTTYPE (6 << EMACTXD_STA_CHKERR_SHIFT) /* Not TCP or UDP */ # define EMACTXD_STA_CHKERR_EPKT (7 << EMACTXD_STA_CHKERR_SHIFT) /* Premature end of packet */ + /* Bits 23-25: Reserved */ #define EMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision, transmit error detected */ #define EMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit frame corruption due to AHB error */ @@ -757,9 +783,10 @@ #define EMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */ #define EMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the EMAC to read from buffer */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* Receive buffer descriptor */ struct emac_rxdesc_s diff --git a/arch/arm/src/sama5/hardware/sam_flexcom.h b/arch/arm/src/sama5/hardware/sam_flexcom.h index 33c790526a5..057117b975c 100644 --- a/arch/arm/src/sama5/hardware/sam_flexcom.h +++ b/arch/arm/src/sama5/hardware/sam_flexcom.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_flexcom.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Common Flexcom Register Offsets **************************************************/ +/* Common Flexcom Register Offsets ******************************************/ #define SAM_FLEX_MR_OFFSET 0x000 /* FLEXCOM Mode Register */ /* 0x0004–0x000c Reserved */ @@ -46,7 +46,7 @@ /* 0x0400-0x05ff: Flexcom USART register */ /* 0x0600-0x07ff: Flexcom USART register */ -/* Common Flexcom Register Addresses ************************************************/ +/* Common Flexcom Register Addresses ****************************************/ #ifdef CONFIG_SAMA5_HAVE_FLEXCOM0 # define SAM_FLEX0_MR (SAM_FLEXCOM0_VBASE+SAM_FLEX_MR_OFFSET) @@ -78,7 +78,7 @@ # define SAM_FLEX4_THR (SAM_FLEXCOM4_VBASE+SAM_FLEX_THR_OFFSET) #endif -/* Common Flexcom Register Bit Field Definitions ************************************/ +/* Common Flexcom Register Bit Field Definitions ****************************/ /* FLEXCOM Mode Register */ @@ -97,15 +97,15 @@ #define FLEX_THR_MASK (0xffff) -/* Flexcom USART Register Definitions ***********************************************/ +/* Flexcom USART Register Definitions ***************************************/ #include "hardware/sam_flexcom_usart.h" -/* Flexcom SPI Register Definitions *************************************************/ +/* Flexcom SPI Register Definitions *****************************************/ #include "hardware/sam_flexcom_spi.h" -/* Flexcom TWI Register Definitions *************************************************/ +/* Flexcom TWI Register Definitions *****************************************/ #include "hardware/sam_flexcom_twi.h" diff --git a/arch/arm/src/sama5/hardware/sam_flexcom_spi.h b/arch/arm/src/sama5/hardware/sam_flexcom_spi.h index 0207f5c6bd3..154392ba5a1 100644 --- a/arch/arm/src/sama5/hardware/sam_flexcom_spi.h +++ b/arch/arm/src/sama5/hardware/sam_flexcom_spi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_flexcom_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_SPI_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_SPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Flexcom SPI Register Offsets *****************************************************/ +/* Flexcom SPI Register Offsets *********************************************/ -/* Flexcom SPI Register Addresses ***************************************************/ +/* Flexcom SPI Register Addresses *******************************************/ -/* Flexcom SPI Register Bit Field Definitions ***************************************/ +/* Flexcom SPI Register Bit Field Definitions *******************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_SPI_H */ diff --git a/arch/arm/src/sama5/hardware/sam_flexcom_twi.h b/arch/arm/src/sama5/hardware/sam_flexcom_twi.h index 8e100d3eb19..ba68566e92c 100644 --- a/arch/arm/src/sama5/hardware/sam_flexcom_twi.h +++ b/arch/arm/src/sama5/hardware/sam_flexcom_twi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_flexcom_twi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_TWI_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_TWI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Flexcom TWI Register Offsets *****************************************************/ +/* Flexcom TWI Register Offsets *********************************************/ -/* Flexcom TWI Register Addresses ***************************************************/ +/* Flexcom TWI Register Addresses *******************************************/ -/* Flexcom TWI Register Bit Field Definitions ***************************************/ +/* Flexcom TWI Register Bit Field Definitions *******************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_TWI_H */ diff --git a/arch/arm/src/sama5/hardware/sam_flexcom_usart.h b/arch/arm/src/sama5/hardware/sam_flexcom_usart.h index 603654052e4..f82f57be68e 100644 --- a/arch/arm/src/sama5/hardware/sam_flexcom_usart.h +++ b/arch/arm/src/sama5/hardware/sam_flexcom_usart.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_flexcom_usart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_FLEXUS_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_FLEXUS_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* USART register offsets ***********************************************************************/ +/* USART register offsets ***************************************************/ #define SAM_FLEXUS_CR_OFFSET 0x0200 /* USART Control Register */ #define SAM_FLEXUS_MR_OFFSET 0x0204 /* USART Mode Register */ @@ -69,7 +69,7 @@ #define SAM_FLEXUS_WPSR_OFFSET 0x02e8 /* Write Protect Status Register (4) */ /* 0x02ec-0x02fc: Reserved (USART) */ -/* USART register addresses **********************************************************************/ +/* USART register addresses *************************************************/ #ifdef CONFIG_SAMA5_HAVE_FLEXCOM0 # define SAM_FLEXUS0_CR (SAM_FLEXCOM0_VBASE+SAM_FLEXUS_CR_OFFSET) @@ -225,7 +225,8 @@ # define SAM_FLEXUS4_WPSR (SAM_FLEXCOM4_VBASE+SAM_FLEXUS_WPSR_OFFSET) #endif -/* USART register bit definitions ****************************************************************/ +/* USART register bit definitions *******************************************/ + /* USART Control Register */ #define FLEXUS_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver */ @@ -265,18 +266,21 @@ # define FLEXUS_MR_MODE_IRDA (8 << FLEXUS_MR_MODE_SHIFT) /* IrDA */ # define FLEXUS_MR_MODE_LINMASTER (10 << FLEXUS_MR_MODE_SHIFT) /* LIN master */ # define FLEXUS_MR_MODE_LINSLAVE (11 << FLEXUS_MR_MODE_SHIFT) /* LIN slave */ + #define FLEXUS_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */ #define FLEXUS_MR_USCLKS_MASK (3 << FLEXUS_MR_USCLKS_SHIFT) # define FLEXUS_MR_USCLKS_MCK (0 << FLEXUS_MR_USCLKS_SHIFT) /* MCK */ # define FLEXUS_MR_USCLKS_MCKDIV (1 << FLEXUS_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ # define FLEXUS_MR_USCLKS_PMCPCK (2 << FLEXUS_MR_USCLKS_SHIFT) /* PMC Programmable clock */ # define FLEXUS_MR_USCLKS_SCK (3 << FLEXUS_MR_USCLKS_SHIFT) /* ExtenaleSCK */ + #define FLEXUS_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length */ #define FLEXUS_MR_CHRL_MASK (3 << FLEXUS_MR_CHRL_SHIFT) # define FLEXUS_MR_CHRL_5BITS (0 << FLEXUS_MR_CHRL_SHIFT) /* 5 bits */ # define FLEXUS_MR_CHRL_6BITS (1 << FLEXUS_MR_CHRL_SHIFT) /* 6 bits */ # define FLEXUS_MR_CHRL_7BITS (2 << FLEXUS_MR_CHRL_SHIFT) /* 7 bits */ # define FLEXUS_MR_CHRL_8BITS (3 << FLEXUS_MR_CHRL_SHIFT) /* 8 bits */ + #define FLEXUS_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select */ #define FLEXUS_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type */ #define FLEXUS_MR_PAR_MASK (7 << FLEXUS_MR_PAR_SHIFT) @@ -286,17 +290,20 @@ # define FLEXUS_MR_PAR_MARK (3 << FLEXUS_MR_PAR_SHIFT) /* Mark: parity forced to 1 */ # define FLEXUS_MR_PAR_NONE (4 << FLEXUS_MR_PAR_SHIFT) /* No parity */ # define FLEXUS_MR_PAR_MULTIDROP (6 << FLEXUS_MR_PAR_SHIFT) /* Multidrop mode */ + #define FLEXUS_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits */ #define FLEXUS_MR_NBSTOP_MASK (3 << FLEXUS_MR_NBSTOP_SHIFT) # define FLEXUS_MR_NBSTOP_1 (0 << FLEXUS_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ # define FLEXUS_MR_NBSTOP_1p5 (1 << FLEXUS_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ # define FLEXUS_MR_NBSTOP_2 (2 << FLEXUS_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ + #define FLEXUS_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */ #define FLEXUS_MR_CHMODE_MASK (3 << FLEXUS_MR_CHMODE_SHIFT) # define FLEXUS_MR_CHMODE_NORMAL (0 << FLEXUS_MR_CHMODE_SHIFT) /* Normal Mode */ # define FLEXUS_MR_CHMODE_ECHO (1 << FLEXUS_MR_CHMODE_SHIFT) /* Automatic Echo */ # define FLEXUS_MR_CHMODE_LLPBK (2 << FLEXUS_MR_CHMODE_SHIFT) /* Local Loopback */ # define FLEXUS_MR_CHMODE_RLPBK (3 << FLEXUS_MR_CHMODE_SHIFT) /* Remote Loopback */ + #define FLEXUS_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first */ #define FLEXUS_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length */ #define FLEXUS_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select */ @@ -313,7 +320,8 @@ #define FLEXUS_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode */ #define FLEXUS_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector */ -/* USART Interrupt Enable Register, USART Interrupt Disable Register, USART Interrupt Mask +/* USART Interrupt Enable Register, + * USART Interrupt Disable Register, USART Interrupt Mask * Register, and USART Status Register common bit field definitions */ @@ -429,6 +437,7 @@ # define FLEXUS_MAN_TXPP_ALLZERO (1 << FLEXUS_MAN_TXPP_SHIFT) /* ALL_ZERO */ # define FLEXUS_MAN_TXPP_ZEROONE (2 << FLEXUS_MAN_TXPP_SHIFT) /* ZERO_ONE */ # define FLEXUS_MAN_TXPP_ONEZERO (3 << FLEXUS_MAN_TXPP_SHIFT) /* ONE_ZERO */ + #define FLEXUS_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity */ #define FLEXUS_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length */ #define FLEXUS_MAN_RXPL_MASK (15 << FLEXUS_MAN_RXPL_SHIFT) @@ -439,6 +448,7 @@ # define FLEXUS_MAN_RXPP_ALLZERO (1 << FLEXUS_MAN_RXPP_SHIFT) /* ALL_ZERO */ # define FLEXUS_MAN_RXPP_ZEROONE (2 << FLEXUS_MAN_RXPP_SHIFT) /* ZERO_ONE */ # define FLEXUS_MAN_RXPP_ONEZERO (3 << FLEXUS_MAN_RXPP_SHIFT) /* ONE_ZERO */ + #define FLEXUS_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity */ #define FLEXUS_MAN_ONE (1 << 29) /* Bit 29: Must Be Set to 1 */ #define FLEXUS_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation */ @@ -451,6 +461,7 @@ # define FLEXUS_LINMR_NACT_PUBLISH (0 << FLEXUS_LINMR_NACT_SHIFT) /* USART transmits response */ # define FLEXUS_LINMR_NACT_SUBSCRIBE (1 << FLEXUS_LINMR_NACT_SHIFT) /* USART receives response */ # define FLEXUS_LINMR_NACT_IGNORE (2 << FLEXUS_LINMR_NACT_SHIFT) /* USART does not transmit or receive response */ + #define FLEXUS_LINMR_PARDIS (1 << 2) /* Bit 2: Parity Disable */ #define FLEXUS_LINMR_CHKDIS (1 << 3) /* Bit 3: Checksum Disable */ #define FLEXUS_LINMR_CHKTYP (1 << 4) /* Bit 4: Checksum Type */ @@ -496,11 +507,13 @@ # define FLEXUS_FMR_TXRDYM_ONE (0 << FLEXUS_FMR_TXRDYM_SHIFT) /* TXRDY level 1 when can write one data */ # define FLEXUS_FMR_TXRDYM_TWO (1 << FLEXUS_FMR_TXRDYM_SHIFT) /* TXRDY level 1 when can write two data */ # define FLEXUS_FMR_TXRDYM_FOUR (2 << FLEXUS_FMR_TXRDYM_SHIFT) /* TXRDY level 1 when can write four data */ + #define FLEXUS_FMR_RXRDYM_SHIFT (4) /* Bits 4-5: Receiver Ready Mode */ #define FLEXUS_FMR_RXRDYM_MASK (3 << FLEXUS_FMR_RXRDYM_SHIFT) # define FLEXUS_FMR_RXRDYM_ONE (0 << FLEXUS_FMR_RXRDYM_SHIFT) /* TXRDY level 1 when can read one data */ # define FLEXUS_FMR_RXRDYM_TWO (1 << FLEXUS_FMR_RXRDYM_SHIFT) /* TXRDY level 1 when can read two data */ # define FLEXUS_FMR_RXRDYM_FOUR (2 << FLEXUS_FMR_RXRDYM_SHIFT) /* TXRDY level 1 when can read four data */ + #define FLEXUS_FMR_FRTSC (1 << 7) /* Bit 7: FIFO RTS pin Control enable */ #define FLEXUS_FMR_TXFTHRES_SHIFT (8) /* Bits 8-13: Transmit FIFO Threshold */ #define FLEXUS_FMR_TXFTHRES_MASK (0x3f << FLEXUS_FMR_TXFTHRES_SHIFT) @@ -521,7 +534,8 @@ #define FLEXUS_FLR_RXFL_MASK (0x3f << FLEXUS_FLR_RXFL_SHIFT) # define FLEXUS_FLR_RXFL(n) ((uint32_t)(n) << FLEXUS_FLR_RXFL_SHIFT) -/* USART FIFO Interrupt Enable Register, USART FIFO Interrupt Disable Register, USART FIFO +/* USART FIFO Interrupt Enable Register, + * USART FIFO Interrupt Disable Register, USART FIFO * Interrupt Mask Register, and USART FIFO Event Status Register. */ @@ -549,16 +563,16 @@ #define FLEXUS_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ #define FLEXUS_WPSR_WPVSRC_MASK (0xffff << FLEXUS_WPSR_WPVSRC_SHIFT) -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_FLEXUS_H */ diff --git a/arch/arm/src/sama5/hardware/sam_gmac.h b/arch/arm/src/sama5/hardware/sam_gmac.h index 714cbf3b64b..42180aff1b0 100644 --- a/arch/arm/src/sama5/hardware/sam_gmac.h +++ b/arch/arm/src/sama5/hardware/sam_gmac.h @@ -55,8 +55,10 @@ /* 0x0048-0x007c Reserved */ #define SAM_GMAC_HRB_OFFSET 0x0080 /* Hash Register Bottom [31:0] */ #define SAM_GMAC_HRT_OFFSET 0x0084 /* Hash Register Top [63:32] */ + #define SAM_GMAC_SAB_OFFSET(n) (0x0088 + (((n)-1) << 3)) /* n=1..4 */ #define SAM_GMAC_SAT_OFFSET(n) (0x008c + (((n)-1) << 3)) /* n=1..4 */ + #define SAM_GMAC_SAB1_OFFSET 0x0088 /* Specific Address 1 Bottom [31:0] Register */ #define SAM_GMAC_SAT1_OFFSET 0x008c /* Specific Address 1 Top [47:32] Register */ #define SAM_GMAC_SAB2_OFFSET 0x0090 /* Specific Address 2 Bottom [31:0] Register */ @@ -65,7 +67,9 @@ #define SAM_GMAC_SAT3_OFFSET 0x009c /* Specific Address 3 Top [47:32] Register */ #define SAM_GMAC_SAB4_OFFSET 0x00a0 /* Specific Address 4 Bottom [31:0] Register */ #define SAM_GMAC_SAT4_OFFSET 0x00a4 /* Specific Address 4 Top [47:32] Register */ + #define SAM_GMAC_TIDM_OFFSET(n) (0x00a8 + (((n)-1) << 2)) /* n=1..4 */ + #define SAM_GMAC_TIDM1_OFFSET 0x00a8 /* Type ID Match 1 Register */ #define SAM_GMAC_TIDM2_OFFSET 0x00ac /* Type ID Match 2 Register */ #define SAM_GMAC_TIDM3_OFFSET 0x00b0 /* Type ID Match 3 Register */ @@ -138,7 +142,9 @@ #define SAM_GMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */ /* 0x0200-0x023c Reserved */ /* 0x0280-0x0298 Reserved */ + #define SAM_GMAC_ISRPQ_OFFSET(n) (0x400 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_ISRPQ0_OFFSET 0x400 /* Interrupt Status Register Priority Queue 0 */ #define SAM_GMAC_ISRPQ1_OFFSET 0x404 /* Interrupt Status Register Priority Queue 1 */ #define SAM_GMAC_ISRPQ2_OFFSET 0x408 /* Interrupt Status Register Priority Queue 2 */ @@ -146,7 +152,9 @@ #define SAM_GMAC_ISRPQ4_OFFSET 0x410 /* Interrupt Status Register Priority Queue 4 */ #define SAM_GMAC_ISRPQ5_OFFSET 0x414 /* Interrupt Status Register Priority Queue 5 */ #define SAM_GMAC_ISRPQ6_OFFSET 0x418 /* Interrupt Status Register Priority Queue 6 */ + #define SAM_GMAC_TBQBAPQ_OFFSET(n) (0x440 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_TBQBAPQ0_OFFSET 0x440 /* Transmit Buffer Queue Base Address Priority Queue 0 */ #define SAM_GMAC_TBQBAPQ1_OFFSET 0x444 /* Transmit Buffer Queue Base Address Priority Queue 1 */ #define SAM_GMAC_TBQBAPQ2_OFFSET 0x448 /* Transmit Buffer Queue Base Address Priority Queue 2 */ @@ -154,7 +162,9 @@ #define SAM_GMAC_TBQBAPQ4_OFFSET 0x450 /* Transmit Buffer Queue Base Address Priority Queue 4 */ #define SAM_GMAC_TBQBAPQ5_OFFSET 0x454 /* Transmit Buffer Queue Base Address Priority Queue 5 */ #define SAM_GMAC_TBQBAPQ6_OFFSET 0x458 /* Transmit Buffer Queue Base Address Priority Queue 6 */ + #define SAM_GMAC_RBQBAPQ_OFFSET(n) (0x480 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_RBQBAPQ0_OFFSET 0x480 /* Receive Buffer Queue Base Address Priority Queue 0 */ #define SAM_GMAC_RBQBAPQ1_OFFSET 0x484 /* Receive Buffer Queue Base Address Priority Queue 1 */ #define SAM_GMAC_RBQBAPQ2_OFFSET 0x488 /* Receive Buffer Queue Base Address Priority Queue 2 */ @@ -162,7 +172,9 @@ #define SAM_GMAC_RBQBAPQ4_OFFSET 0x490 /* Receive Buffer Queue Base Address Priority Queue 4 */ #define SAM_GMAC_RBQBAPQ5_OFFSET 0x494 /* Receive Buffer Queue Base Address Priority Queue 5 */ #define SAM_GMAC_RBQBAPQ6_OFFSET 0x498 /* Receive Buffer Queue Base Address Priority Queue 6 */ + #define SAM_GMAC_RBSRPQ_OFFSET(n) (0x4a0 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_RBSRPQ0_OFFSET 0x4a0 /* Receive Buffer Size Register Priority Queue 0 */ #define SAM_GMAC_RBSRPQ1_OFFSET 0x4a4 /* Receive Buffer Size Register Priority Queue 1 */ #define SAM_GMAC_RBSRPQ2_OFFSET 0x4a8 /* Receive Buffer Size Register Priority Queue 2 */ @@ -170,7 +182,9 @@ #define SAM_GMAC_RBSRPQ4_OFFSET 0x4b0 /* Receive Buffer Size Register Priority Queue 4 */ #define SAM_GMAC_RBSRPQ5_OFFSET 0x4b4 /* Receive Buffer Size Register Priority Queue 5 */ #define SAM_GMAC_RBSRPQ6_OFFSET 0x4b8 /* Receive Buffer Size Register Priority Queue 6 */ + #define SAM_GMAC_ST1RPQ_OFFSET(n) (0x500 + ((n) << 2)) /* n=0..15 */ + #define SAM_GMAC_ST1RPQ0_OFFSET 0x500 /* Screening Type1 Register Priority Queue 0 */ #define SAM_GMAC_ST1RPQ1_OFFSET 0x504 /* Screening Type1 Register Priority Queue 1 */ #define SAM_GMAC_ST1RPQ2_OFFSET 0x508 /* Screening Type1 Register Priority Queue 2 */ @@ -187,7 +201,9 @@ #define SAM_GMAC_ST1RPQ13_OFFSET 0x534 /* Screening Type1 Register Priority Queue 13 */ #define SAM_GMAC_ST1RPQ14_OFFSET 0x538 /* Screening Type1 Register Priority Queue 14 */ #define SAM_GMAC_ST1RPQ15_OFFSET 0x53c /* Screening Type1 Register Priority Queue 15 */ + #define SAM_GMAC_ST2RPQ_OFFSET(n) (0x540 + ((n) << 2)) /* n=0..15 */ + #define SAM_GMAC_ST2RPQ0_OFFSET 0x540 /* Screening Type2 Register Priority Queue 0 */ #define SAM_GMAC_ST2RPQ1_OFFSET 0x544 /* Screening Type2 Register Priority Queue 1 */ #define SAM_GMAC_ST2RPQ2_OFFSET 0x548 /* Screening Type2 Register Priority Queue 2 */ @@ -204,7 +220,9 @@ #define SAM_GMAC_ST2RPQ13_OFFSET 0x574 /* Screening Type2 Register Priority Queue 13 */ #define SAM_GMAC_ST2RPQ14_OFFSET 0x578 /* Screening Type2 Register Priority Queue 14 */ #define SAM_GMAC_ST2RPQ15_OFFSET 0x57c /* Screening Type2 Register Priority Queue 15 */ + #define SAM_GMAC_IERPQ_OFFSET(n) (0x600 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_IERPQ0_OFFSET 0x600 /* Interrupt Enable Register Priority Queue 0 */ #define SAM_GMAC_IERPQ1_OFFSET 0x604 /* Interrupt Enable Register Priority Queue 1 */ #define SAM_GMAC_IERPQ2_OFFSET 0x608 /* Interrupt Enable Register Priority Queue 2 */ @@ -212,7 +230,9 @@ #define SAM_GMAC_IERPQ4_OFFSET 0x610 /* Interrupt Enable Register Priority Queue 4 */ #define SAM_GMAC_IERPQ5_OFFSET 0x614 /* Interrupt Enable Register Priority Queue 5 */ #define SAM_GMAC_IERPQ6_OFFSET 0x618 /* Interrupt Enable Register Priority Queue 6 */ + #define SAM_GMAC_IDRPQ_OFFSET(n) (0x620 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_IDRPQ0_OFFSET 0x620 /* Interrupt Disable Register Priority Queue 0 */ #define SAM_GMAC_IDRPQ1_OFFSET 0x624 /* Interrupt Disable Register Priority Queue 1 */ #define SAM_GMAC_IDRPQ2_OFFSET 0x628 /* Interrupt Disable Register Priority Queue 2 */ @@ -220,7 +240,9 @@ #define SAM_GMAC_IDRPQ4_OFFSET 0x630 /* Interrupt Disable Register Priority Queue 4 */ #define SAM_GMAC_IDRPQ5_OFFSET 0x630 /* Interrupt Disable Register Priority Queue 5 */ #define SAM_GMAC_IDRPQ6_OFFSET 0x638 /* Interrupt Disable Register Priority Queue 6 */ + #define SAM_GMAC_IMRPQ_OFFSET(n) (0x640 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_IMRPQ0_OFFSET 0x640 /* Interrupt Mask Register Priority Queue 0 */ #define SAM_GMAC_IMRPQ1_OFFSET 0x644 /* Interrupt Mask Register Priority Queue 1 */ #define SAM_GMAC_IMRPQ2_OFFSET 0x648 /* Interrupt Mask Register Priority Queue 2 */ @@ -470,10 +492,12 @@ # define GMAC_NCFGR_CLK_DIV48 (3 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */ # define GMAC_NCFGR_CLK_DIV64 (4 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */ # define GMAC_NCFGR_CLK_DIV96 (5 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */ + #define GMAC_NCFGR_DBW_SHIFT (21) /* Bits 21-22: Data Bus Width */ #define GMAC_NCFGR_DBW_MASK (3 << GMAC_NCFGR_DBW_SHIFT) # define GMAC_NCFGR_DBW_32 (0 << GMAC_NCFGR_DBW_SHIFT) /* 32-bit data bus width */ # define GMAC_NCFGR_DBW_64 (1 << GMAC_NCFGR_DBW_SHIFT) /* 64-bit data bus width */ + #define GMAC_NCFGR_DCPF (1 << 23) /* Bit 23: Disable Copy of Pause Frames */ #define GMAC_NCFGR_RXCOEN (1 << 24) /* Bit 24: Receive Checksum Offload Enable */ #define GMAC_NCFGR_EFRHD (1 << 25) /* Bit 25: Enable Frames Received in Half Duplex */ @@ -499,6 +523,7 @@ # define GMAC_DCFGR_FBLDO_INCR4 (4 << GMAC_DCFGR_FBLDO_SHIFT) /* 001xx: Attempt to use INCR4 AHB bursts */ # define GMAC_DCFGR_FBLDO_INCR8 (8 << GMAC_DCFGR_FBLDO_SHIFT) /* 01xxx: Attempt to use INCR8 AHB bursts */ # define GMAC_DCFGR_FBLDO_INCR16 (16 << GMAC_DCFGR_FBLDO_SHIFT) /* 1xxxx: Attempt to use INCR16 AHB bursts */ + #define GMAC_DCFGR_ESMA (1 << 6) /* Bit 6: Endian Swap Mode Enable for Management Descriptor Accesses */ #define GMAC_DCFGR_ESPA (1 << 7) /* Bit 7: Endian Swap Mode Enable for Packet Data Accesses */ #define GMAC_DCFGR_RXBMS_SHIFT (8) /* Bits 8-9: Receiver Packet Buffer Memory Size Select */ @@ -507,6 +532,7 @@ # define GMAC_DCFGR_RXBMS_QTR (1 << GMAC_DCFGR_RXBMS_SHIFT) /* 1Kbyte Memory Size */ # define GMAC_DCFGR_RXBMS_HALF (2 << GMAC_DCFGR_RXBMS_SHIFT) /* 2 Kbytes Memory Size */ # define GMAC_DCFGR_RXBMS_FULL (3 << GMAC_DCFGR_RXBMS_SHIFT) /* 4 Kbytes Memory Size */ + #define GMAC_DCFGR_TXPBMS (1 << 10) /* Bit 10: Transmitter Packet Buffer Memory Size Select */ #define GMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */ #define GMAC_DCFGR_DRBS_SHIFT (16) /* Bits 16-23: DMA Receive Buffer Size */ @@ -541,7 +567,9 @@ #define GMAC_RSR_RXOVR (1 << 2) /* Bit 2: Receive Overrun */ #define GMAC_RSR_HNO (1 << 3) /* Bit 3: HRESP Not OK */ -/* Interrupt Status Register, Interrupt Enable Register, Interrupt Disable Register */ +/* Interrupt Status Register, Interrupt Enable Register, + * Interrupt Disable Register + */ #define GMAC_INT_MFS (1 << 0) /* Bit 0: Management Frame Sent */ #define GMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */ @@ -615,24 +643,29 @@ #define GMAC_RPSF_ENRXP (1 << 31) /* Bit 31: Enable RX Partial Store and Forward Operation */ /* Hash Register Bottom [31:0] (32-bit value) */ + /* Hash Register Top [63:32] (32-bit value) */ /* Specific Address 1 Bottom [31:0] Register (32-bit value) */ + /* Specific Address 1 Top [47:32] Register */ #define GMAC_SAT1_MASK (0x0000ffff) /* Bits 0-15: Specific Address 1 [47:32] */ /* Specific Address 2 Bottom [31:0] Register (32-bit value) */ + /* Specific Address 2 Top [47:32] Register */ #define GMAC_SAT2_MASK (0x0000ffff) /* Bits 0-15: Specific Address 2 [47:32] */ /* Specific Address 3 Bottom [31:0] Register (32-bit value) */ + /* Specific Address 3 Top [47:32] Register */ #define GMAC_SAT3_MASK (0x0000ffff) /* Bits 0-15: Specific Address 3 [47:32] */ /* Specific Address 4 Bottom [31:0] Register (32-bit value) */ + /* Specific Address 4 Top [47:32] Register */ #define GMAC_SAT4_MASK (0x0000ffff) /* Bits 0-15: Specific Address 4 [47:32] */ @@ -681,17 +714,21 @@ #define GMAC_TPFCP_PQ_MASK (0xff << GMAC_TPFCP_PQ_SHIFT) /* Specific Address 1 Mask Bottom [31:0] Register (32-bit mask) */ + /* Specific Address 1 Mask Top [47:32] Register */ #define GMAC_SAMT1_MASK (0x0000ffff) /* Bits 0-15: Specific Address 1 Mask [47:32] */ /* Octets Transmitted [31:0] Register (32-bit value) */ + /* Octets Transmitted [47:32] Register */ #define GMAC_OTHI_MASK (0x0000ffff) /* Bits 0-15: Transmitted Octets [47:32] */ /* Frames Transmitted Register (32-bit value) */ + /* Broadcast Frames Transmitted Register (32-bit value) */ + /* Multicast Frames Transmitted Register (32-bit value) */ /* Pause Frames Transmitted Register */ @@ -699,11 +736,17 @@ #define GMAC_PFT_MASK (0x0000ffff) /* Bits 0-15: Pause Frames Transmitted */ /* 64 Byte Frames Transmitted Register (32-bit value) */ + /* 65 to 127 Byte Frames Transmitted Register (32-bit value) */ + /* 128 to 255 Byte Frames Transmitted Register (32-bit value) */ + /* 256 to 511 Byte Frames Transmitted Register (32-bit value) */ + /* 512 to 1023 Byte Frames Transmitted Register (32-bit value) */ + /* 1024 to 1518 Byte Frames Transmitted Register (32-bit value) */ + /* Greater Than 1518 Byte Frames Transmitted Register (32-bit value) */ /* Transmit Under Runs Register */ @@ -735,23 +778,33 @@ #define GMAC_CSE_MASK (0x000003ff) /* Bits 0-9: Carrier Sense Error */ /* Octets Received [31:0] Received (32-bit value) */ + /* Octets Received [47:32] Received */ #define GMAC_ORHI_MASK (0x0000ffff) /* Bits 0-15: Received Octets [47:32] */ /* Frames Received Register (32-bit value) */ + /* Broadcast Frames Received Register (32-bit value) */ + /* Multicast Frames Received Register (32-bit value) */ + /* Pause Frames Received Register */ #define GMAC_PFR_MASK (0x0000ffff) /* Bits 0-15: Pause Frames Received */ /* 64 Byte Frames Received Register (32-bit value) */ + /* 65 to 127 Byte Frames Received Register (32-bit value) */ + /* 128 to 255 Byte Frames Received Register (32-bit value) */ + /* 256 to 511Byte Frames Received Register (32-bit value) */ + /* 512 to 1023 Byte Frames Received Register (32-bit value) */ + /* 1024 to 1518 Byte Frames Received Register (32-bit value) */ + /* 1519 to Maximum Byte Frames Received Register (32-bit value) */ /* Undersize Frames Received Register */ @@ -803,11 +856,13 @@ #define GMAC_UCE_MASK (0x000000ff) /* Bits 0-7: UDP Header Checksum Errors */ /* 1588 Timer Sync Strobe Seconds Register (32-bit value) */ + /* 1588 Timer Sync Strobe Nanoseconds Register */ #define GMAC_TSSN_MASK (0x3fffffff) /* Bits 0-29: Value Timer Nanoseconds Register Capture */ /* 1588 Timer Seconds Register (32-bit value) */ + /* 1588 Timer Nanoseconds Register */ #define GMAC_TN_MASK (0x3fffffff) /* Bits 0-29: Timer Count in Nanoseconds */ @@ -831,21 +886,25 @@ # define GMAC_TI_NIT(n) ((uint32_t)(n) << GMAC_TI_NIT_SHIFT) /* PTP Event Frame Transmitted Seconds (32-bit value) */ + /* PTP Event Frame Transmitted Nanoseconds */ #define GMAC_EFTN_MASK (0x3fffffff) /* Bits 0-29: Register Update */ /* PTP Event Frame Received Seconds (32-bit value) */ + /* PTP Event Frame Received Nanoseconds */ #define GMAC_EFRN_MASK (0x3fffffff) /* Bits 0-29: Register Update */ /* PTP Peer Event Frame Transmitted Seconds (32-bit value) */ + /* PTP Peer Event Frame Transmitted Nanoseconds */ #define GMAC_PEFTN_MASK (0x3fffffff) /* Bits 0-29: Register Update */ /* PTP Peer Event Frame Received Seconds (32-bit value) */ + /* PTP Peer Event Frame Received Nanoseconds */ #define GMAC_PEFRS_MASK (0x3fffffff) /* Bits 0-29: Register Update */ @@ -906,8 +965,8 @@ /* Receive buffer descriptor: Address word */ -#define GMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=GMAC owns */ -#define GMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ +#define GMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=GMAC owns */ +#define GMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ #define GMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */ /* Receive buffer descriptor: Control word */ @@ -924,18 +983,21 @@ #define GMACRXD_STA_VLPRIO_MASK (7 << GMACRXD_STA_VLANPRIO_SHIFT) #define GMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */ #define GMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */ + #define GMACRXD_STA_TYPID_SHIFT (22) /* Bits 22-23: Type ID register match */ #define GMACRXD_STA_TYPID_MASK (3 << GMACRXD_STA_TYPID_SHIFT) # define GMACRXD_STA_TYPID1 (0 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 1 match */ # define GMACRXD_STA_TYPID2 (1 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 2 match */ # define GMACRXD_STA_TYPID3 (2 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 3 match */ # define GMACRXD_STA_TYPID4 (3 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 4 match */ + #define GMACRXD_STA_SNAP_SHIFT (22) /* Bits 22-23: Specific Address Register match */ #define GMACRXD_STA_SNAP_MASK (3 << GMACRXD_STA_SNAP_SHIFT) # define GMACRXD_STA_SNAP_NOCHK (0 << GMACRXD_STA_SNAP_SHIFT) /* Checksum not checked */ # define GMACRXD_STA_SNAP_IPCHK (1 << GMACRXD_STA_SNAP_SHIFT) /* IP header checksum checked */ # define GMACRXD_STA_SNAP_TCPCHK (2 << GMACRXD_STA_SNAP_SHIFT) /* IP header and TCP checksum checked */ # define GMACRXD_STA_SNAP_UDPCHK (3 << GMACRXD_STA_SNAP_SHIFT) /* IP header and UDP checksum checked */ + #define GMACRXD_STA_TYPID (1 << 24) /* Bit 24: Type ID match found */ #define GMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */ #define GMACRXD_STA_ADDR_SHIFT (25) /* Bits 25-26: Specific Address Register match */ @@ -944,6 +1006,7 @@ # define GMACRXD_STA_ADDR2_MATCH (1 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ # define GMACRXD_STA_ADDR3_MATCH (2 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ # define GMACRXD_STA_ADDR4_MATCH (3 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ + #define GMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific Address Register match found */ /* Bit 28: Reserved */ #define GMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */ @@ -970,6 +1033,7 @@ # define GMACTXD_STA_CKERR_FRAG (5 << GMACTXD_STA_CKERR_SHIFT) /* Bad packet fragmentation */ # define GMACTXD_STA_CKERR_PROTO (6 << GMACTXD_STA_CKERR_SHIFT) /* Not TCP or UDP */ # define GMACTXD_STA_CKERR_END (7 << GMACTXD_STA_CKERR_SHIFT) /* Premature end of packet */ + /* Bits 23-25: Reserved */ #define GMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision */ #define GMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit Frame Corruption due to AHB error */ diff --git a/arch/arm/src/sama5/hardware/sam_gpbr.h b/arch/arm/src/sama5/hardware/sam_gpbr.h index 550faa9d280..c91a0662775 100644 --- a/arch/arm/src/sama5/hardware/sam_gpbr.h +++ b/arch/arm/src/sama5/hardware/sam_gpbr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_gpbr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,30 +16,32 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GPBR_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GPBR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* GPBR Register Offsets ************************************************************/ + ****************************************************************************/ + +/* GPBR Register Offsets ****************************************************/ #define SAM_SYS_GPBR_OFFSET(n) ((n) << 2) /* General Purpose Backup Register n, 1=0..3 */ + #define SAM_SYS_GPBR0_OFFSET 0x0000 /* General Purpose Backup Register 0 */ #define SAM_SYS_GPBR1_OFFSET 0x0004 /* General Purpose Backup Register 0 */ #define SAM_SYS_GPBR2_OFFSET 0x0008 /* General Purpose Backup Register 0 */ #define SAM_SYS_GPBR3_OFFSET 0x000c /* General Purpose Backup Register 0 */ -/* GPBR Register Addresses **********************************************************/ +/* GPBR Register Addresses **************************************************/ #define SAM_SYS_GPBR(n) (SAM_GPBR_VBASE+SAM_SYS_GPBR_OFFSET(n)) #define SAM_SYS_GPBR0 (SAM_GPBR_VBASE+SAM_SYS_GPBR0_OFFSET) @@ -47,7 +49,8 @@ #define SAM_SYS_GPBR2 (SAM_GPBR_VBASE+SAM_SYS_GPBR2_OFFSET) #define SAM_SYS_GPBR3 (SAM_GPBR_VBASE+SAM_SYS_GPBR3_OFFSET) -/* GPBR Register Bit Definitions ****************************************************/ +/* GPBR Register Bit Definitions ********************************************/ + /* All GPBR registers hold user-defined, 32-bit values */ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GPBR_H */ diff --git a/arch/arm/src/sama5/hardware/sam_hsmc.h b/arch/arm/src/sama5/hardware/sam_hsmc.h index f096e7ef8ae..e83626d3eba 100644 --- a/arch/arm/src/sama5/hardware/sam_hsmc.h +++ b/arch/arm/src/sama5/hardware/sam_hsmc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_hsmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Chip Select Definitions **********************************************************/ + ****************************************************************************/ + +/* Chip Select Definitions **************************************************/ #define HSMC_CS0 0 #define HSMC_CS1 1 @@ -41,7 +42,7 @@ #define NFCSRAM_BASE SAM_NFCSRAM_VSECTION #define NFCCMD_BASE SAM_NFCCR_VSECTION -/* SMC Register Offsets *************************************************************/ +/* SMC Register Offsets *****************************************************/ #define SAM_HSMC_CFG_OFFSET 0x0000 /* HSMC NFC Configuration Register */ #define SAM_HSMC_CTRL_OFFSET 0x0004 /* HSMC NFC Control Register */ @@ -64,6 +65,7 @@ #define SAM_HSMC_PMECCIMR_OFFSET 0x0094 /* PMECC Interrupt Mask Register */ #define SAM_HSMC_PMECCISR_OFFSET 0x0098 /* PMECC Interrupt Status Register */ /* 0x009c-0x00ac Reserved */ + #define SAM_HSMC_PMECC_OFFSET(n) (0x00b0 + ((n) << 6)) /* PMECC sector offset */ # define SAM_HSMC_PMECC0_OFFSET(n) (0x00b0 + ((n) << 6)) /* PMECC Redundancy 0 Register */ # define SAM_HSMC_PMECC1_OFFSET(n) (0x00b4 + ((n) << 6)) /* PMECC Redundancy 1 Register */ @@ -89,6 +91,7 @@ # define SAM_HSMC_REM9_OFFSET(n) (0x02b4 + ((n) << 6)) /* PMECC Remainder 9 Register */ # define SAM_HSMC_REM10_OFFSET(n) (0x02b8 + ((n) << 6)) /* PMECC Remainder 10 Register */ # define SAM_HSMC_REM11_OFFSET(n) (0x02bc + ((n) << 6)) /* PMECC Remainder 11 Register */ + /* 0x04a0-0x04fc Reserved */ #define SAM_HSMC_ELCFG_OFFSET 0x0500 /* PMECC Error Location Configuration Register */ #define SAM_HSMC_ELPRIM_OFFSET 0x0504 /* PMECC Error Location Primitive Register */ @@ -99,8 +102,10 @@ #define SAM_HSMC_ELIDR_OFFSET 0x0518 /* PMECC Error Location Interrupt Disable Register */ #define SAM_HSMC_ELIMR_OFFSET 0x051c /* PMECC Error Location Interrupt Mask Register */ #define SAM_HSMC_ELISR_OFFSET 0x0520 /* PMECC Error Location Interrupt Status Register */ + /* 0x0524-0x052c Reserved */ #define SAM_HSMC_SIGMA_OFFSET(n) (0x0528 + ((n) << 2)) /* PMECC Error Location SIGMA n Register */ + # define SAM_HSMC_SIGMA0_OFFSET 0x0528 /* PMECC Error Location SIGMA 0 Register */ # define SAM_HSMC_SIGMA1_OFFSET 0x052c /* PMECC Error Location SIGMA 1 Register */ # define SAM_HSMC_SIGMA2_OFFSET 0x0530 /* PMECC Error Location SIGMA 2 Register */ @@ -126,7 +131,9 @@ # define SAM_HSMC_SIGMA22_OFFSET 0x0580 /* PMECC Error Location SIGMA 22 Register */ # define SAM_HSMC_SIGMA23_OFFSET 0x0584 /* PMECC Error Location SIGMA 23 Register */ # define SAM_HSMC_SIGMA24_OFFSET 0x0588 /* PMECC Error Location SIGMA 24 Register */ + #define SAM_HSMC_ERRLOC_OFFSET(n) (0x058c + ((n) << 2)) /* PMECC Error Location n Register */ + # define SAM_HSMC_ERRLOC0_OFFSET 0x058c /* PMECC Error Location 0 Register */ # define SAM_HSMC_ERRLOC1_OFFSET 0x0590 /* PMECC Error Location 1 Register */ # define SAM_HSMC_ERRLOC2_OFFSET 0x0594 /* PMECC Error Location 2 Register */ @@ -151,12 +158,14 @@ # define SAM_HSMC_ERRLOC21_OFFSET 0x05e0 /* PMECC Error Location 21 Register */ # define SAM_HSMC_ERRLOC22_OFFSET 0x05e4 /* PMECC Error Location 22 Register */ # define SAM_HSMC_ERRLOC23_OFFSET 0x05e8 /* PMECC Error Location 23 Register */ + /* 0x05ec-0x05fc Reserved */ #define SAM_HSMC_SETUP_OFFSET(n) (0x0600 + 0x14 * (n)) /* HSMC Setup Register */ #define SAM_HSMC_PULSE_OFFSET(n) (0x0604 + 0x14 * (n)) /* HSMC Pulse Register */ #define SAM_HSMC_CYCLE_OFFSET(n) (0x0608 + 0x14 * (n)) /* HSMC Cycle Register */ #define SAM_HSMC_TIMINGS_OFFSET(n) (0x060c + 0x14 * (n)) /* HSMC Timings Register */ #define SAM_HSMC_MODE_OFFSET(n) (0x0610 + 0x14 * (n)) /* HSMC Mode Register */ + #define SAM_HSMC_OCMS_OFFSET 0x06a0 /* HSMC OCMS Register */ #define SAM_HSMC_KEY1_OFFSET 0x06a4 /* HSMC OCMS KEY1 Register */ #define SAM_HSMC_KEY2_OFFSET 0x06a8 /* HSMC OCMS KEY2 Register */ @@ -165,7 +174,7 @@ #define SAM_HSMC_WPSR_OFFSET 0x06e8 /* HSMC Write Protection Status Register */ /* 0x06fc Reserved */ -/* SMC Register Addresses ***********************************************************/ +/* SMC Register Addresses ***************************************************/ #define SAM_HSMC_CFG (SAM_HSMC_VBASE+SAM_HSMC_CFG_OFFSET) #define SAM_HSMC_CTRL (SAM_HSMC_VBASE+SAM_HSMC_CTRL_OFFSET) @@ -281,7 +290,7 @@ #define SAM_HSMC_WPMR (SAM_HSMC_VBASE+SAM_HSMC_WPMR_OFFSET) #define SAM_HSMC_WPSR (SAM_HSMC_VBASE+SAM_HSMC_WPSR_OFFSET) -/* SMC Register Bit Definitions *****************************************************/ +/* SMC Register Bit Definitions *********************************************/ /* HSMC NFC Configuration Register */ @@ -292,6 +301,7 @@ # define HSMC_CFG_PAGESIZE_2048 (2 << HSMC_CFG_PAGESIZE_SHIFT) /* Main area 2048 Bytes */ # define HSMC_CFG_PAGESIZE_4096 (3 << HSMC_CFG_PAGESIZE_SHIFT) /* Main area 4096 Bytes */ # define HSMC_CFG_PAGESIZE_8192 (4 << HSMC_CFG_PAGESIZE_SHIFT) /* Main area 8192 Bytes */ + #define HSMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ #define HSMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ #define HSMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ @@ -309,6 +319,7 @@ # define HSMC_CFG_DTOMUL_4096 (5 << HSMC_CFG_DTOMUL_SHIFT) /* DTOCYC x 4096 */ # define HSMC_CFG_DTOMUL_65536 (6 << HSMC_CFG_DTOMUL_SHIFT) /* DTOCYC x 65536 */ # define HSMC_CFG_DTOMUL_1048576 (7 << HSMC_CFG_DTOMUL_SHIFT) /* DTOCYC x 1048576 */ + #define HSMC_CFG_NFCSPARESIZE_SHIFT (24) /* Bit 24-30: NAND Flash Spare Area Size */ #define HSMC_CFG_NFCSPARESIZE_MASK (0x7f << HSMC_CFG_NFCSPARESIZE_SHIFT) # define HSMC_CFG_NFCSPARESIZE(n) ((uint32_t)(n) << HSMC_CFG_NFCSPARESIZE_SHIFT) @@ -319,8 +330,11 @@ #define HSMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ /* HSMC NFC Status Register */ + /* HSMC NFC Interrupt Enable Register */ + /* HSMC NFC Interrupt Disable Register */ + /* HSMC NFC Interrupt Mask Register */ #define HSMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller Status (SR only) */ @@ -357,16 +371,19 @@ # define HSMC_PMECCFG_BCHERR_8 (2 << HSMC_PMECCFG_BCHERR_SHIFT) /* 8 errors */ # define HSMC_PMECCFG_BCHERR_12 (3 << HSMC_PMECCFG_BCHERR_SHIFT) /* 12 errors */ # define HSMC_PMECCFG_BCHERR_24 (4 << HSMC_PMECCFG_BCHERR_SHIFT) /* 24 errors */ + #define HSMC_PMECCFG_SECTORSZ_SHIFT (4) /* Bit 4: Sector Size */ #define HSMC_PMECCFG_SECTORSZ_MASK (1 << HSMC_PMECCFG_SECTORSZ_SHIFT) # define HSMC_PMECCFG_SECTORSZ_512 (0 << HSMC_PMECCFG_SECTORSZ_SHIFT) # define HSMC_PMECCFG_SECTORSZ_1024 (1 << HSMC_PMECCFG_SECTORSZ_SHIFT) + #define HSMC_PMECCFG_PAGESIZE_SHIFT (8) /* Bit 8-9: Number of Sectors in the Page */ #define HSMC_PMECCFG_PAGESIZE_MASK (3 << HSMC_PMECCFG_PAGESIZE_SHIFT) # define HSMC_PMECCFG_PAGESIZE_1SEC (0 << HSMC_PMECCFG_PAGESIZE_SHIFT) /* 1 sector (5121K) */ # define HSMC_PMECCFG_PAGESIZE_2SEC (1 << HSMC_PMECCFG_PAGESIZE_SHIFT) /* 2 sectors (1/2K) */ # define HSMC_PMECCFG_PAGESIZE_4SEC (2 << HSMC_PMECCFG_PAGESIZE_SHIFT) /* 4 sectors (2/4K) */ # define HSMC_PMECCFG_PAGESIZE_8SEC (3 << HSMC_PMECCFG_PAGESIZE_SHIFT) /* 8 sectors (4/8K) */ + #define HSMC_PMECCFG_NANDWR_SHIFT (12) /* Bit 12: NAND Write Access */ #define HSMC_PMECCFG_NANDWR_MASK (1 << HSMC_PMECCFG_NANDWR_SHIFT) # define HSMC_PMECCFG_NANDWR_READ (0 << HSMC_PMECCFG_NANDWR_SHIFT) @@ -406,7 +423,9 @@ #define HSMC_PMECCSR_ENABLE (1 << 4) /* Bit 4: PMECC Enable bit */ /* PMECC Interrupt Enable Register */ + /* PMECC Interrupt Disable Register */ + /* PMECC Interrupt Mask Register */ #define HSMC_PMECCINT_ERRI (1 << 0) /* Bit 0: Error Interrupt */ @@ -453,7 +472,9 @@ #define HSMC_ELSR_BUSY (1 << 0) /* Bit 0: Error Location Engine Busy */ /* PMECC Error Location Interrupt Enable Register */ + /* PMECC Error Location Interrupt Disable Register */ + /* PMECC Error Location Interrupt Mask Register */ #define HSMC_ELIINT_DONE (1 << 0) /* Bit 0: Computation Terminated Interrupt */ @@ -502,7 +523,7 @@ #define HSMC_CYCLE_NWE_CYCLE_SHIFT (0) /* Bit 0-8: Total Write Cycle Length */ #define HSMC_CYCLE_NWE_CYCLE_MASK (0x1ff << HSMC_CYCLE_NWE_CYCLE_SHIFT) - #define HSMC_CYCLE_NWE_CYCLE(n) ((n) << HSMC_CYCLE_NWE_CYCLE_SHIFT) +# define HSMC_CYCLE_NWE_CYCLE(n) ((n) << HSMC_CYCLE_NWE_CYCLE_SHIFT) #define HSMC_CYCLE_NRD_CYCLE_SHIFT (16) /* Bit 16-24: Total Read Cycle Length */ #define HSMC_CYCLE_NRD_CYCLE_MASK (0x1ff << HSMC_CYCLE_NRD_CYCLE_SHIFT) # define HSMC_CYCLE_NRD_CYCLE(n) ((n) << HSMC_CYCLE_NRD_CYCLE_SHIFT) @@ -539,10 +560,13 @@ # define HSMC_MODE_EXNWMODE_DISABLED (0 << HSMC_MODE_EXNWMODE_SHIFT) /* Disabled */ # define HSMC_MODE_EXNWMODE_FROZEN (2 << HSMC_MODE_EXNWMODE_SHIFT) /* Frozen Mode */ # define HSMC_MODE_EXNWMODE_READY (3 << HSMC_MODE_EXNWMODE_SHIFT) /* Ready Mode */ + #define HSMC_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ #define HSMC_MODE_DBW (1 << 12) /* Bit 12: Data Bus Width */ + # define HSMC_MODE_BIT_8 (0) /* 0=8-bit bus */ # define HSMC_MODE_BIT_16 HSMC_MODE_DBW /* 1=16-bit bus */ + #define HSMC_MODE_TDFCYCLES_SHIFT (16) /* Bit 16-19: Data Float Time */ #define HSMC_MODE_TDFCYCLES_MASK (15 << HSMC_MODE_TDFCYCLES_SHIFT) # define HSMC_MODE_TDFCYCLES(n) ((n) << HSMC_MODE_TDFCYCLES_SHIFT) @@ -554,6 +578,7 @@ #define HSMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ /* HSMC OCMS KEY1 Register (32-bits of 64-bit key value) */ + /* HSMC OCMS KEY2 Register (32-bits of 64-bit key value) */ /* HSMC Write Protection Mode Register */ @@ -570,7 +595,7 @@ #define HSMC_WPSR_WPVSRC_SHIFT (8) /* Bit 8-23: Write Protection Violation Source */ #define HSMC_WPSR_WPVSRC_MASK (0xffff << HSMC_WPSR_WPVSRC_SHIFT) -/* NFC Command/Data Registers *******************************************************/ +/* NFC Command/Data Registers ***********************************************/ /* NFC Command and Status Registers */ @@ -584,15 +609,18 @@ #define NFCADDR_CMD_ACYCLE_SHIFT (19) /* Bits 19-21: Number of Address required for command */ #define NFCADDR_CMD_ACYCLE_MASK (7 << NFCADDR_CMD_ACYCLE_SHIFT) # define NFCADDR_CMD_ACYCLE(n) ((uint32_t)(n) << NFCADDR_CMD_ACYCLE_SHIFT) /* n address cycles, n=0-5 */ + # define NFCADDR_CMD_ACYCLE_NONE (0 << NFCADDR_CMD_ACYCLE_SHIFT) /* No address cycle */ # define NFCADDR_CMD_ACYCLE_ONE (1 << NFCADDR_CMD_ACYCLE_SHIFT) /* One address cycle */ # define NFCADDR_CMD_ACYCLE_TWO (2 << NFCADDR_CMD_ACYCLE_SHIFT) /* Two address cycles */ # define NFCADDR_CMD_ACYCLE_THREE (3 << NFCADDR_CMD_ACYCLE_SHIFT) /* Three address cycles */ # define NFCADDR_CMD_ACYCLE_FOUR (4 << NFCADDR_CMD_ACYCLE_SHIFT) /* Four address cycles */ # define NFCADDR_CMD_ACYCLE_FIVE (5 << NFCADDR_CMD_ACYCLE_SHIFT) /* Five address cycles */ + #define NFCADDR_CMD_CSID_SHIFT (22) /* Bits 22-24: Chip Select Identifier */ #define NFCADDR_CMD_CSID_MASK (7 << NFCADDR_CMD_CSID_SHIFT) # define NFCADDR_CMD_CSID(n) ((uint32_t)(n) << NFCADDR_CMD_CSID_SHIFT) /* CSn, n=0-7 */ + # define NFCADDR_CMD_CSID_0 (0 << NFCADDR_CMD_CSID_SHIFT) /* CS0 */ # define NFCADDR_CMD_CSID_1 (1 << NFCADDR_CMD_CSID_SHIFT) /* CS1 */ # define NFCADDR_CMD_CSID_2 (2 << NFCADDR_CMD_CSID_SHIFT) /* CS2 */ @@ -601,6 +629,7 @@ # define NFCADDR_CMD_CSID_5 (5 << NFCADDR_CMD_CSID_SHIFT) /* CS5 */ # define NFCADDR_CMD_CSID_6 (6 << NFCADDR_CMD_CSID_SHIFT) /* CS6 */ # define NFCADDR_CMD_CSID_7 (7 << NFCADDR_CMD_CSID_SHIFT) /* CS7 */ + #define NFCADDR_CMD_DATAEN (1 << 25) /* Bit 25: 1=NFC Data Enable */ #define NFCADDR_CMD_DATADIS (0 << 25) /* Bit 25: 0=NFC Data disable */ #define NFCADDR_CMD_NFCRD (0 << 26) /* Bit 26: 0=NFC Read Enable */ diff --git a/arch/arm/src/sama5/hardware/sam_hsmci.h b/arch/arm/src/sama5/hardware/sam_hsmci.h index c2ce6f03c85..4d8264e5649 100644 --- a/arch/arm/src/sama5/hardware/sam_hsmci.h +++ b/arch/arm/src/sama5/hardware/sam_hsmci.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_hsmci.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMCI_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMCI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* HSMCI register offsets ***************************************************************/ +/* HSMCI register offsets ***************************************************/ #define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */ @@ -64,7 +64,7 @@ /* 0x0100-0x0124: Reserved for PCD registers */ #define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x05fc FIFO Memory Aperture */ -/* HSMCI register addresses *************************************************************/ +/* HSMCI register addresses *************************************************/ #define SAM_HSMCI0_CR (SAM_HSMCI0_VBASE+SAM_HSMCI_CR_OFFSET) #define SAM_HSMCI0_MR (SAM_HSMCI0_VBASE+SAM_HSMCI_MR_OFFSET) @@ -140,7 +140,7 @@ # define SAM_HSMCI2_FIFO (SAM_HSMCI2_VBASE+SAM_HSMCI_FIFO_OFFSET) #endif -/* HSMCI register bit definitions *******************************************************/ +/* HSMCI register bit definitions *******************************************/ /* HSMCI Control Register */ @@ -183,11 +183,13 @@ /* HSMCI SDCard/SDIO Register */ #define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */ + #define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT) /* Slot A is selected */ # define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */ # define HSMCI_SDCR_SDCSEL_SLOTB (1 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */ # define HSMCI_SDCR_SDCSEL_SLOTC (2 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */ # define HSMCI_SDCR_SDCSEL_SLOTD (3 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */ + #define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */ #define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT) # define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT) @@ -206,6 +208,7 @@ # define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */ # define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */ # define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */ + #define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */ #define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT) # define HSMCI_CMDR_SPCMD_STD (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */ @@ -216,6 +219,7 @@ # define HSMCI_CMDR_SPCMD_ITRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */ # define HSMCI_CMDR_SPCMD_BOR (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */ # define HSMCI_CMDR_SPCMD_EBO (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */ + #define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */ #define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */ #define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */ @@ -223,6 +227,7 @@ # define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */ # define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */ # define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */ + #define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */ # define HSMCI_CMDR_TRDIR_WRITE (0 << 18) # define HSMCI_CMDR_TRDIR_READ (1 << 18) @@ -233,11 +238,13 @@ # define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */ # define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */ # define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */ + #define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */ #define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT) # define HSMCI_CMDR_IOSPCMD_STD (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */ # define HSMCI_CMDR_IOSPCMD_SUSPEND (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ # define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ + #define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ #define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */ @@ -267,10 +274,13 @@ # define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) /* HSMCI Response Registers (32-bit data) */ + /* HSMCI Receive Data Registers (32-bit data) */ + /* HSMCI Transmit Data Registers (32-bit data) */ -/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable +/* HSMCI Status Register, + * HSMCI Interrupt Enable Register, HSMCI Interrupt Disable * Register, and HSMCI Interrupt Mask Register common bit-field definitions */ @@ -320,6 +330,7 @@ # define HSMCI_DMA_CHKSIZE_8 (2 << HSMCI_DMA_CHKSIZE_SHIFT) /* 8 data available */ # define HSMCI_DMA_CHKSIZE_16 (3 << HSMCI_DMA_CHKSIZE_SHIFT) /* 16 data available */ # define HSMCI_DMA_CHKSIZE_32 (4 << HSMCI_DMA_CHKSIZE_SHIFT) /* 32 data available */ + #define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ #ifdef ATSAMA5D3 @@ -346,16 +357,16 @@ #define HSMCI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ #define HSMCI_WPSR_WPVSRC_MASK (0xffff << HSMCI_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMCI_H */ diff --git a/arch/arm/src/sama5/hardware/sam_isi.h b/arch/arm/src/sama5/hardware/sam_isi.h index ca23def2290..00c6fcbb900 100644 --- a/arch/arm/src/sama5/hardware/sam_isi.h +++ b/arch/arm/src/sama5/hardware/sam_isi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_isi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ISI_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ISI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* ISI Register Offsets *************************************************************/ + ****************************************************************************/ + +/* ISI Register Offsets *****************************************************/ #define SAM_ISI_CFG1_OFFSET 0x0000 /* ISI Configuration 1 Register */ #define SAM_ISI_CFG2_OFFSET 0x0004 /* ISI Configuration 2 Register */ @@ -61,7 +62,7 @@ #define SAM_ISI_WPSR_OFFSET 000xe8 /* Write Protection Status Register */ /* 0x00ec-0x00fc Reserved */ -/* ISI Register Addresses ***********************************************************/ +/* ISI Register Addresses ***************************************************/ #define SAM_ISI_CFG1 (SAM_ISI_VBASE+SAM_ISI_CFG1_OFFSET) #define SAM_ISI_CFG2 (SAM_ISI_VBASE+SAM_ISI_CFG2_OFFSET) @@ -89,7 +90,7 @@ #define SAM_ISI_WPMR (SAM_ISI_VBASE+SAM_ISI_WPMR_OFFSET) #define SAM_ISI_WPSR (SAM_ISI_VBASE+SAM_ISI_WPSR_OFFSET) -/* ISI Register Bit Definitions *****************************************************/ +/* ISI Register Bit Definitions *********************************************/ /* ISI Configuration 1 Register */ @@ -108,6 +109,7 @@ # define ISI_CFG1_THMASK_BEATS4 (0 << ISI_CFG1_THMASK_SHIFT) /* Only 4 beats AHB burst allowed */ # define ISI_CFG1_THMASK_BEATS8 (1 << ISI_CFG1_THMASK_SHIFT) /* Only 4 and 8 beats AHB burst allowed */ # define ISI_CFG1_THMASK_BEATS16 (2 << ISI_CFG1_THMASK_SHIFT) /* 4, 8 and 16 beats AHB burst allowed */ + #define ISI_CFG1_SLD_SHIFT (16) /* Bits 16-23: Start of Line Delay */ #define ISI_CFG1_SLD_MASK (0xff << ISI_CFG1_SLD_SHIFT) # define ISI_CFG1_SLD(n) ((uint32_t)(n) << ISI_CFG1_SLD_SHIFT) @@ -138,6 +140,7 @@ # define ISI_CFG2_YCCSWAP_MODE1 (1 << ISI_CFG2_YCCSWAP_SHIFT) /* Cr(i) Y(i) Cb(i) Y(i+1) */ # define ISI_CFG2_YCCSWAP_MODE2 (2 << ISI_CFG2_YCCSWAP_SHIFT) /* Y(i) Cb(i) Y(i+1) Cr(i) */ # define ISI_CFG2_YCCSWAP_MODE3 (3 << ISI_CFG2_YCCSWAP_SHIFT) /* Y(i) Cr(i) Y(i+1) Cb(i) */ + #define ISI_CFG2_RGBCFG_SHIFT (30) /* Bits 30-31: Defines RGB Pattern when RGB_MODE is set to 1 */ #define ISI_CFG2_RGBCFG_MASK (3 << ISI_CFG2_RGBCFG_SHIFT) # define ISI_CFG2_RGBCFG_DEFAULT (0 << ISI_CFG2_RGBCFG_SHIFT) /* R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B */ @@ -245,8 +248,8 @@ #define ISI_INT_CRCERR (1 << 26) /* Bit 26: CRC Synchronization Error */ #define ISI_INT_FROVR (1 << 27) /* Bit 27: Frame Rate Overrun */ -/* DMA Channel Enable Register, DMA Channel Disable Register, and DMA Channel Status - * Register +/* DMA Channel Enable Register, DMA Channel Disable Register, + * and DMA Channel Status Register */ #define ISI_DMA_PCH (1 << 0) /* Bit 0: Preview Channel */ @@ -305,18 +308,21 @@ # define ISI_WPSR_WPVSRC_R2Y_SET1 (8 << ISI_WPSR_WPVSRC_SHIFT) /* Write access in ISI_R2Y_SET1 */ # define ISI_WPSR_WPVSRC_R2Y_SET2 (9 << ISI_WPSR_WPVSRC_SHIFT) /* Write access in ISI_R2Y_SET2 */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ -/* "The destination frame buffers are defined by a series of Frame Buffer Descriptors - * (FBD). Each FBD controls the transfer of one entire frame and then optionally - * loads a further FBD to switch the DMA operation at another frame buffer address. + ****************************************************************************/ + +/* "The destination frame buffers are defined by a series of Frame Buffer + * Descriptors (FBD). Each FBD controls the transfer of one entire frame + * and then optionally loads a further FBD to switch the DMA operation at + * another frame buffer address. * - * "The FBD is defined by a series of three words. The first one defines the current - * frame buffer address (named DMA_X_ADDR register), the second defines control - * information (named DMA_X_CTRL register) and the third defines the next descriptor - * address (named DMA_X_DSCR). DMA transfer mode with linked list support is - * available for both codec and preview datapath." + * "The FBD is defined by a series of three words. The first one defines the + * current frame buffer address (named DMA_X_ADDR register), the second + * defines control information (named DMA_X_CTRL register) and the third + * defines the next descriptor address (named DMA_X_DSCR). DMA transfer + * mode with linked list support is available for both codec and preview + * datapath." */ struct isi_dscr_s diff --git a/arch/arm/src/sama5/hardware/sam_lcdc.h b/arch/arm/src/sama5/hardware/sam_lcdc.h index a720d857322..d049fbe76fa 100644 --- a/arch/arm/src/sama5/hardware/sam_lcdc.h +++ b/arch/arm/src/sama5/hardware/sam_lcdc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_lcdc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_LCDC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_LCDC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define SAM_LCDC_NCLUT 256 /* Number of entries in the CLUTs */ -/* LCDC Register Offsets ************************************************************/ +/* LCDC Register Offsets ****************************************************/ #define SAM_LCDC_LCDCFG0_OFFSET 0x0000 /* LCD Controller Configuration Register 0 */ #define SAM_LCDC_LCDCFG1_OFFSET 0x0004 /* LCD Controller Configuration Register 1 */ @@ -225,6 +225,7 @@ # define SAM_LCDC_PPCFG5_OFFSET 0x0580 /* Post Processing Configuration Register 5 */ #endif /* 0x0584-0x05fc Reserved */ + /* 0x0600-0x08fc Base CLUT Registers 0-255 */ #define SAM_LCDC_BASECLUT_OFFSET(n) (0x0600 + ((n) << 2)) @@ -247,7 +248,8 @@ # define SAM_LCDC_HCRCLUT_OFFSET(n) (0x1600 + ((n) << 2)) #endif /* 0x1a00-0x1fe4 Reserved */ -/* LCDC Register Addresses *********************************************************/ + +/* LCDC Register Addresses **************************************************/ #define SAM_LCDC_LCDCFG0 (SAM_LCDC_VBASE+SAM_LCDC_LCDCFG0_OFFSET) #define SAM_LCDC_LCDCFG1 (SAM_LCDC_VBASE+SAM_LCDC_LCDCFG1_OFFSET) @@ -457,7 +459,7 @@ # define SAM_LCDC_HCRCLUT(n) (SAM_LCDC_VBASE+SAM_LCDC_HCRCLUT_OFFSET(n)) #endif -/* LCDC Register Bit Definitions ***************************************************/ +/* LCDC Register Bit Definitions ********************************************/ /* LCD Controller Configuration Register 0 */ @@ -585,6 +587,7 @@ # define LCDC_LCDCFG6_PWMPS_DIV16 (4 << LCDC_LCDCFG6_PWMPS_SHIFT) /* Fcounter = Fpwm_selected_clock/16 */ # define LCDC_LCDCFG6_PWMPS_DIV32 (5 << LCDC_LCDCFG6_PWMPS_SHIFT) /* Fcounter = Fpwm_selected_clock/32 */ # define LCDC_LCDCFG6_PWMPS_DIV64 (6 << LCDC_LCDCFG6_PWMPS_SHIFT) /* Fcounter = Fpwm_selected_clock/64 */ + #define LCDC_LCDCFG6_PWMPOL (1 << 4) /* Bit 4: LCD Controller PWM Signal Polarity */ #define LCDC_LCDCFG6_PWMCVAL_SHIFT (8) /* Bits 8-15: LCD Controller PWM Compare Value */ #define LCDC_LCDCFG6_PWMCVAL_MASK (0xff << LCDC_LCDCFG6_PWMCVAL_SHIFT) @@ -616,8 +619,10 @@ #define LCDC_LCDSR_PWM (1 << 3) /* Bit 3: LCDC PWM Signal Status */ #define LCDC_LCDSR_SIP (1 << 4) /* Bit 4: Synchronization In Progress */ -/* LCD Controller Interrupt Enable Register, LCD Controller Interrupt Disable Register, - * LCD Controller Interrupt Mask Register, and LCD Controller Interrupt Status Register +/* LCD Controller Interrupt Enable Register, + * LCD Controller Interrupt Disable Register, + * LCD Controller Interrupt Mask Register, + * and LCD Controller Interrupt Status Register */ #define LCDC_LCDINT_SOF (1 << 0) /* Bit 0: Start of Frame Interrupt */ @@ -667,8 +672,10 @@ #define LCDC_BASECHSR_UPDATE (1 << 1) /* Bit 1: Update Overlay Attributes In */ #define LCDC_BASECHSR_A2Q (1 << 2) /* Bit 2: Add To Queue Pending */ -/* Base Layer Interrupt Enable Register, Base Layer Interrupt Disable Register, - * Base Layer Interrupt Mask Register, and Base Layer Interrupt Status Register. +/* Base Layer Interrupt Enable Register, + * Base Layer Interrupt Disable Register, + * Base Layer Interrupt Mask Register, + * and Base Layer Interrupt Status Register. */ #define LCDC_BASEINT_DMA (1 << 2) /* Bit 2: End of DMA Transfer */ @@ -682,6 +689,7 @@ #define LCDC_BASEHEAD_MASK (0xfffffffc) /* Bits 2-31: DMA Head Pointer */ /* Base DMA Address Register (32-bit address) */ + /* Base DMA Control Register */ #define LCDC_BASECTRL_DFETCH (1 << 0) /* Bit 0: Transfer Descriptor Fetch Enable */ @@ -723,6 +731,7 @@ # define LCDC_BASECFG1_25BPP_TRGB1888 (11 << LCDC_BASECFG1_RGBMODE_SHIFT) /* 25 bpp TRGB 1888 */ # define LCDC_BASECFG1_32BPP_ARGB8888 (12 << LCDC_BASECFG1_RGBMODE_SHIFT) /* 32 bpp ARGB 8888 */ # define LCDC_BASECFG1_32BPP_RGBA8888 (13 << LCDC_BASECFG1_RGBMODE_SHIFT) /* 32 bpp RGBA 8888 */ + #define LCDC_BASECFG1_CLUTMODE_SHIFT (8) /* Bits 8-9: CLUT Input Mode Selection */ #define LCDC_BASECFG1_CLUTMODE_MASK (3 << LCDC_BASECFG1_CLUTMODE_SHIFT) # define LCDC_BASECFG1_CLUTMODE_1BPP (0 << LCDC_BASECFG1_CLUTMODE_SHIFT) /* CLUT input 1 bit per pixel */ @@ -731,6 +740,7 @@ # define LCDC_BASECFG1_CLUTMODE_8BPP (3 << LCDC_BASECFG1_CLUTMODE_SHIFT) /* CLUT input 8 bits per pixel */ /* Base Configuration register 2 (32-bit value) */ + /* Base Configuration register 3 */ #define LCDC_BASECFG3_BDEF_SHIFT (0) /* Bits 0-7: B Default */ @@ -843,6 +853,7 @@ # define LCDC_OVR1CFG1_25BPP_TRGB1888 (11 << LCDC_OVR1CFG1_RGBMODE_SHIFT) /* 25 bpp TRGB 1888 */ # define LCDC_OVR1CFG1_32BPP_ARGB8888 (12 << LCDC_OVR1CFG1_RGBMODE_SHIFT) /* 32 bpp ARGB 8888 */ # define LCDC_OVR1CFG1_32BPP_RGBA8888 (13 << LCDC_OVR1CFG1_RGBMODE_SHIFT) /* 32 bpp RGBA 8888 */ + #define LCDC_OVR1CFG1_CLUTMODE_SHIFT (8) /* Bits 8-9: CLUT Input Mode Selection */ #define LCDC_OVR1CFG1_CLUTMODE_MASK (3 << LCDC_OVR1CFG1_CLUTMODE_SHIFT) # define LCDC_OVR1CFG1_CLUTMODE_1BPP (0 << LCDC_OVR1CFG1_CLUTMODE_SHIFT) /* CLUT input 1 bit per pixel */ @@ -869,6 +880,7 @@ # define LCDC_OVR1CFG3_YSIZE(n) ((uint32_t)(n) << LCDC_OVR1CFG3_YSIZE_SHIFT) /* Overlay 1 Configuration 4 Register (32-bit horizontal stride value) */ + /* Overlay 1 Configuration 5 Register (32-bit pixel stride value) */ /* Overlay 1 Configuration 6 Register */ @@ -999,6 +1011,7 @@ # define LCDC_OVR2CFG1_25BPP_TRGB1888 (11 << LCDC_OVR2CFG1_RGBMODE_SHIFT) /* 25 bpp TRGB 1888 */ # define LCDC_OVR2CFG1_32BPP_ARGB8888 (12 << LCDC_OVR2CFG1_RGBMODE_SHIFT) /* 32 bpp ARGB 8888 */ # define LCDC_OVR2CFG1_32BPP_RGBA8888 (13 << LCDC_OVR2CFG1_RGBMODE_SHIFT) /* 32 bpp RGBA 8888 */ + #define LCDC_OVR2CFG1_CLUTMODE_SHIFT (8) /* Bits 8-9: CLUT Input Mode Selection */ #define LCDC_OVR2CFG1_CLUTMODE_MASK (3 << LCDC_OVR2CFG1_CLUTMODE_SHIFT) # define LCDC_OVR2CFG1_CLUTMODE_1BPP (0 << LCDC_OVR2CFG1_CLUTMODE_SHIFT) /* CLUT input 1 bit per pixel */ @@ -1025,7 +1038,8 @@ # define LCDC_OVR2CFG3_YSIZE(n) ((uint32_t)(n) << LCDC_OVR2CFG3_YSIZE_SHIFT) /* Overlay 2 Configuration 4 Register (32-bit horizontal stride value) */ -/* Overlay 2 Configuration 5 Register (32-bit pixel stride value)*/ + +/* Overlay 2 Configuration 5 Register (32-bit pixel stride value) */ /* Overlay 2 Configuration 6 Register */ @@ -1097,8 +1111,10 @@ #define LCDC_HEOCHSR_UPDATE (1 << 1) /* Bit 1: Update Overlay Attributes In */ #define LCDC_HEOCHSR_A2Q (1 << 2) /* Bit 2: Add To Queue Pending */ -/* High-End Overlay Interrupt Enable Register, High-End Overlay Interrupt Disable Register, - * High-End Overlay Interrupt Mask Register, and High-End Overlay Interrupt Status Register +/* High-End Overlay Interrupt Enable Register, + * High-End Overlay Interrupt Disable Register, + * High-End Overlay Interrupt Mask Register, + * and High-End Overlay Interrupt Status Register */ #define LCDC_HEOINT_DMA (1 << 2) /* Bit 2: End of DMA Transfer */ @@ -1133,7 +1149,9 @@ #define LCDC_HEOCTRL_DONEIEN (1 << 5) /* Bit 5: End of List Interrupt Enable */ /* High-End Overlay DMA Next Register (32-bit address) */ + /* High-End Overlay U-UV DMA Head Register (32-bit address) */ + /* High-End Overlay U-UV DMA Address Register (32-bit address) */ /* High-End Overlay U-UV DMA Control Register */ @@ -1145,7 +1163,9 @@ #define LCDC_HEOUCTRL_DONEIEN (1 << 5) /* Bit 5: End of List Interrupt Enable */ /* High-End Overlay U-UV DMA Next Register (32-bit address) */ + /* High-End Overlay V DMA Head Register (32-bit address) */ + /* High-End Overlay V DMA Address Register )32-bit address) */ /* High-End Overlay V DMA Control Register */ @@ -1197,12 +1217,14 @@ # define LCDC_HEOCFG1_25BPP_TRGB1888 (11 << LCDC_HEOCFG1_RGBMODE_SHIFT) /* 25 bpp TRGB 1888 */ # define LCDC_HEOCFG1_32BPP_ARGB8888 (12 << LCDC_HEOCFG1_RGBMODE_SHIFT) /* 32 bpp ARGB 8888 */ # define LCDC_HEOCFG1_32BPP_RGBA8888 (13 << LCDC_HEOCFG1_RGBMODE_SHIFT) /* 32 bpp RGBA 8888 */ + #define LCDC_HEOCFG1_CLUTMODE_SHIFT (8) /* Bits 8-9: CLUT Input Mode Selection */ #define LCDC_HEOCFG1_CLUTMODE_MASK (3 << LCDC_HEOCFG1_CLUTMODE_SHIFT) # define LCDC_HEOCFG1_CLUTMODE_1BPP (0 << LCDC_HEOCFG1_CLUTMODE_SHIFT) /* CLUT input 1 bit per pixel */ # define LCDC_HEOCFG1_CLUTMODE_2BPP (1 << LCDC_HEOCFG1_CLUTMODE_SHIFT) /* CLUT input 2 bits per pixel */ # define LCDC_HEOCFG1_CLUTMODE_4BPP (2 << LCDC_HEOCFG1_CLUTMODE_SHIFT) /* CLUT input 4 bits per pixel */ # define LCDC_HEOCFG1_CLUTMODE_8BPP (3 << LCDC_HEOCFG1_CLUTMODE_SHIFT) /* CLUT input 8 bits per pixel */ + #define LCDC_HEOCFG1_YUVMODE_SHIFT (12) /* Bits 12-15: YUV Mode Input Selection */ #define LCDC_HEOCFG1_YUVMODE_MASK (15 << LCDC_HEOCFG1_YUVMODE_SHIFT) # define LCDC_HEOCFG1_32BPP_AYCBCR (0 << LCDC_HEOCFG1_YUVMODE_SHIFT) /* 32 bpp AYCbCr 444 */ @@ -1214,6 +1236,7 @@ # define LCDC_HEOCFG1_16BPP_YCBCR_PLANAR (6 << LCDC_HEOCFG1_YUVMODE_SHIFT) /* 16 bpp Planar 422 YCbCr */ # define LCDC_HEOCFG1_12BPP_YCBCR_SEMIPLANAR (7 << LCDC_HEOCFG1_YUVMODE_SHIFT) /* 12 bpp Semiplanar 420 YCbCr */ # define LCDC_HEOCFG1_12BPP_YCBCR_PLANAR (8 << LCDC_HEOCFG1_YUVMODE_SHIFT) /* 12 bpp Planar 420 YCbCr */ + #define LCDC_HEOCFG1_YUV422ROT (1 << 16) /* Bit 16: YUV 4:2:2 Rotation */ #define LCDC_HEOCFG1_YUV422SWP (1 << 17) /* Bit 17: YUV 4:2:2 SWAP */ #define LCDC_HEOCFG1_DSCALEOPT (1 << 20) /* Bit 20: Down Scaling Bandwidth Optimization */ @@ -1245,10 +1268,21 @@ #define LCDC_HEOCFG4_YMEMSIZE_MASK (0x7ff << LCDC_HEOCFG4_YMEMSIZE_SHIFT) # define LCDC_HEOCFG4_YMEMSIZE(n) ((uint32_t)(n) << LCDC_HEOCFG4_YMEMSIZE_SHIFT) -/* High-End Overlay Configuration Register 5 (32-bit horizontal stride value) */ -/* High-End Overlay Configuration Register 6 (32-bit pixel stride value) */ -/* High-End Overlay Configuration Register 7 (32-bit horizontal stride value) */ -/* High-End Overlay Configuration Register 8 (32-bit pixel stride value) */ +/* High-End Overlay Configuration Register 5 + * (32-bit horizontal stride value) + */ + +/* High-End Overlay Configuration Register 6 + * (32-bit pixel stride value) + */ + +/* High-End Overlay Configuration Register 7 + * (32-bit horizontal stride value) + */ + +/* High-End Overlay Configuration Register 8 + * (32-bit pixel stride value) + */ /* High-End Overlay Configuration Register 9 */ @@ -1644,8 +1678,10 @@ # define LCDC_HCRCHSR_UPDATE (1 << 1) /* Bit 1: Update Overlay Attributes In */ # define LCDC_HCRCHSR_A2Q (1 << 2) /* Bit 2: Add To Queue Pending */ -/* Hardware Cursor Interrupt Enable Register, Hardware Cursor Interrupt Disable Register, - * Hardware Cursor Interrupt Mask Register, and Hardware Cursor Interrupt Status Register +/* Hardware Cursor Interrupt Enable Register, + * Hardware Cursor Interrupt Disable Register, + * Hardware Cursor Interrupt Mask Register, + * and Hardware Cursor Interrupt Status Register */ # define LCDC_HCRINT_DMA (1 << 2) /* Bit 2: End of DMA Transfer */ @@ -1701,6 +1737,7 @@ # define LCDC_HCRCFG1_25BPP_TRGB1888 (11 << LCDC_HCRCFG1_RGBMODE_SHIFT) /* 25 bpp TRGB 1888 */ # define LCDC_HCRCFG1_32BPP_ARGB8888 (12 << LCDC_HCRCFG1_RGBMODE_SHIFT) /* 32 bpp ARGB 8888 */ # define LCDC_HCRCFG1_32BPP_RGBA8888 (13 << LCDC_HCRCFG1_RGBMODE_SHIFT) /* 32 bpp RGBA 8888 */ + # define LCDC_HCRCFG1_CLUTMODE_SHIFT (8) /* Bits 8-9: CLUT Input Mode Selection */ # define LCDC_HCRCFG1_CLUTMODE_MASK (3 << LCDC_HCRCFG1_CLUTMODE_SHIFT) # define LCDC_HCRCFG1_CLUTMODE_1BPP (0 << LCDC_HCRCFG1_CLUTMODE_SHIFT) /* CLUT input 1 bit per pixel */ @@ -1726,7 +1763,9 @@ # define LCDC_HCRCFG3_YSIZE_MASK (0x7ff << LCDC_HCRCFG3_YSIZE_SHIFT) # define LCDC_HCRCFG3_YSIZE(n) ((uint32_t)(n) << LCDC_HCRCFG3_YSIZE_SHIFT) -/* Hardware Cursor Configuration 4 Register (32-bit horizontal stride value) */ +/* Hardware Cursor Configuration 4 Register + * (32-bit horizontal stride value) + */ /* Hardware Cursor Configuration 6 Register */ @@ -1798,8 +1837,10 @@ # define LCDC_PPCHSR_UPDATE (1 << 1) /* Bit 1: Update Overlay Attributes In */ # define LCDC_PPCHSR_A2Q (1 << 2) /* Bit 2: Add To Queue Pending */ -/* Post Processing Interrupt Enable Register, Post Processing Interrupt Disable Register, - * Post Processing Interrupt Mask Register, and Post Processing Interrupt Status Register +/* Post Processing Interrupt Enable Register, + * Post Processing Interrupt Disable Register, + * Post Processing Interrupt Mask Register, + * and Post Processing Interrupt Status Register */ # define LCDC_PPINT_DMA (1 << 2) /* Bit 2: End of DMA Transfer */ @@ -1845,6 +1886,7 @@ # define LCDC_PPCFG1_PPMODE_YCBCR_422_MODE1 (4 << LCDC_PPCFG1_PPMODE_SHIFT) /* YCbCr 422 16 bpp (Mode 1) */ # define LCDC_PPCFG1_PPMODE_YCBCR_422_MODE2 (5 << LCDC_PPCFG1_PPMODE_SHIFT) /* YCbCr 422 16 bpp (Mode 2) */ # define LCDC_PPCFG1_PPMODE_YCBCR_422_MODE3 (6 << LCDC_PPCFG1_PPMODE_SHIFT) /* YCbCr 422 16 bpp (Mode 3) */ + # define LCDC_PPCFG1_ITUBT601 (1 << 4) /* Bit 4: Color Space Conversion U */ /* Post Processing Configuration Register 2 (32-bit horizontal stride) */ @@ -1963,11 +2005,13 @@ # define LCDC_HCRCLUT_ACLUT(n) ((uint32_t)(n) << LCDC_HCRCLUT_ACLUT_SHIFT) #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/* DMA channel descriptor. This descriptor must be aligned on a 64-bit boundary. */ +/* DMA channel descriptor. + * This descriptor must be aligned on a 64-bit boundary. + */ struct sam_dscr_s { diff --git a/arch/arm/src/sama5/hardware/sam_matrix.h b/arch/arm/src/sama5/hardware/sam_matrix.h index 6596edeae4e..e3014a0c931 100644 --- a/arch/arm/src/sama5/hardware/sam_matrix.h +++ b/arch/arm/src/sama5/hardware/sam_matrix.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_matrix.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MATRIX_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MATRIX_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ #ifdef ATSAMA5D2 -/* These are bits maps of PIDs in the H64MX SPSELR registers. These are used by - * application code to quickly determine if a given PID is served by H32MX or H64MX - * which, in turn, is needed to know if the peripheral secured in SPSELR). +/* These are bits maps of PIDs in the H64MX SPSELR registers. These are + * used by application code to quickly determine if a given PID is served + * by H32MX or H64MX which, in turn, is needed to know if the peripheral + * secured in SPSELR). * Reference: "In Matrix" column of "Table 9-2. Peripheral identifiers." * * NOTE that these hard-code bit values must match the PID assignments in @@ -63,9 +64,10 @@ #ifdef ATSAMA5D4 # define H64MX_DDR_SLAVE_PORT0 3 -/* These are bits maps of PIDs in the H64MX SPSELR registers. These are used by - * application code to quickly determine if a given PID is served by H32MX or H64MX - * which, in turn, is needed to know if the peripheral secured in SPSELR). +/* These are bits maps of PIDs in the H64MX SPSELR registers. These are + * used by application code to quickly determine if a given PID is served + * by H32MX or H64MX which, in turn, is needed to know if the peripheral + * secured in SPSELR). * Reference: "In Matrix" column of "Table 9-1. Peripheral identifiers." * * NOTE that these hard-code bit values must match the PID assignments in @@ -86,7 +88,7 @@ #endif -/* MATRIX register offsets **************************************************************/ +/* MATRIX register offsets **************************************************/ #define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2) #define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ @@ -270,7 +272,7 @@ # define SAM_MATRIX_SPSELR3_OFFSET 0x02c8 /* Security Peripheral Select 3 Register */ #endif -/* MATRIX register addresses ************************************************************/ +/* MATRIX register addresses ************************************************/ #ifdef ATSAMA5D3 # define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_VBASE+SAM_MATRIX_MCFG_OFFSET(n)) @@ -680,7 +682,8 @@ #endif /* ATSAMA5D2 || ATSAMA5D4 */ -/* MATRIX register bit definitions ******************************************************/ +/* MATRIX register bit definitions ******************************************/ + /* Master Configuration Registers */ #define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ @@ -797,8 +800,9 @@ #endif #if defined(ATSAMA5D2) || defined(ATSAMA5D4) -/* Master Error Interrupt Enable Register, Master Error Interrupt Disable Register, - * Master Error Interrupt Mask Register, and Master Error Status Register +/* Master Error Interrupt Enable Register, Master Error Interrupt Disable + * Register, Master Error Interrupt Mask Register, and Master Error + * Status Register */ # define MATRIX_MEINT_MERR(n) (1 << (n)) /* Master x Access Error, n=0..9 */ @@ -893,27 +897,35 @@ # define MATRIX_SASSR_SASPLIT_SHIFT(n) ((n) << 4) /* Security Areas Split for HSELn Security Region, n=0..7 */ # define MATRIX_SASSR_SASPLIT_MASK(n) (15 << MATRIX_SASSR_SASPLIT_SHIFT(n)) # define MATRIX_SASSR_SASPLIT(n,v) ((uint32_t)(v) << MATRIX_SASSR_SASPLIT_SHIFT(n)) /* See definitions above */ + # define MATRIX_SASSR_SASPLIT0_SHIFT (0) /* Bits 0-3: Security Areas Split for HSEL0 Security Region */ # define MATRIX_SASSR_SASPLIT0_MASK (15 << MATRIX_SASSR_SASPLIT0_SHIFT) # define MATRIX_SASSR_SASPLIT0(n) ((uint32_t)(n) << MATRIX_SASSR_SASPLIT0_SHIFT) /* See definitions above */ + # define MATRIX_SASSR_SASPLIT1_SHIFT (0) /* Bits 0-3: Security Areas Split for HSEL0 Security Region */ # define MATRIX_SASSR_SASPLIT1_MASK (15 << MATRIX_SASSR_SASPLIT1_SHIFT) # define MATRIX_SASSR_SASPLIT1(n) ((uint32_t)(n) << MATRIX_SASSR_SASPLIT1_SHIFT) /* See definitions above */ + # define MATRIX_SASSR_SASPLIT2_SHIFT (0) /* Bits 0-3: Security Areas Split for HSEL0 Security Region */ # define MATRIX_SASSR_SASPLIT2_MASK (15 << MATRIX_SASSR_SASPLIT2_SHIFT) # define MATRIX_SASSR_SASPLIT2(n) ((uint32_t)(n) << MATRIX_SASSR_SASPLIT2_SHIFT) /* See definitions above */ + # define MATRIX_SASSR_SASPLIT3_SHIFT (0) /* Bits 0-3: Security Areas Split for HSEL0 Security Region */ # define MATRIX_SASSR_SASPLIT3_MASK (15 << MATRIX_SASSR_SASPLIT3_SHIFT) # define MATRIX_SASSR_SASPLIT3(n) ((uint32_t)(n) << MATRIX_SASSR_SASPLIT3_SHIFT) /* See definitions above */ + # define MATRIX_SASSR_SASPLIT4_SHIFT (0) /* Bits 0-3: Security Areas Split for HSEL0 Security Region */ # define MATRIX_SASSR_SASPLIT4_MASK (15 << MATRIX_SASSR_SASPLIT4_SHIFT) # define MATRIX_SASSR_SASPLIT4(n) ((uint32_t)(n) << MATRIX_SASSR_SASPLIT4_SHIFT) /* See definitions above */ + # define MATRIX_SASSR_SASPLIT5_SHIFT (0) /* Bits 0-3: Security Areas Split for HSEL0 Security Region */ # define MATRIX_SASSR_SASPLIT5_MASK (15 << MATRIX_SASSR_SASPLIT5_SHIFT) # define MATRIX_SASSR_SASPLIT5(n) ((uint32_t)(n) << MATRIX_SASSR_SASPLIT5_SHIFT) /* See definitions above */ + # define MATRIX_SASSR_SASPLIT6_SHIFT (0) /* Bits 0-3: Security Areas Split for HSEL0 Security Region */ # define MATRIX_SASSR_SASPLIT6_MASK (15 << MATRIX_SASSR_SASPLIT6_SHIFT) # define MATRIX_SASSR_SASPLIT6(n) ((uint32_t)(n) << MATRIX_SASSR_SASPLIT6_SHIFT) /* See definitions above */ + # define MATRIX_SASSR_SASPLIT7_SHIFT (0) /* Bits 0-3: Security Areas Split for HSEL0 Security Region */ # define MATRIX_SASSR_SASPLIT7_MASK (15 << MATRIX_SASSR_SASPLIT7_SHIFT) # define MATRIX_SASSR_SASPLIT7(n) ((uint32_t)(n) << MATRIX_SASSR_SASPLIT7_SHIFT) /* See definitions above */ @@ -940,27 +952,35 @@ # define MATRIX_SRTSR_SRTOP_SHIFT(n) ((n) << 4) /* HSELn Security Region Top, n=0..7 */ # define MATRIX_SRTSR_SRTOP_MASK(n) (15 << MATRIX_SRTSR_SRTOP_SHIFT(n)) # define MATRIX_SRTSR_SRTOP(n,v) ((uint32_t)(v) << MATRIX_SRTSR_SRTOP_SHIFT(n)) /* See definitions above */ + # define MATRIX_SRTSR_SRTOP0_SHIFT (0) /* Bits 0-3: HSEL0 Security Region Top */ # define MATRIX_SRTSR_SRTOP0_MASK (15 << MATRIX_SRTSR_SRTOP0_SHIFT) # define MATRIX_SRTSR_SRTOP0(n) ((uint32_t)(n) << MATRIX_SRTSR_SRTOP0_SHIFT) /* See definitions above */ + # define MATRIX_SRTSR_SRTOP1_SHIFT (0) /* Bits 0-3: HSEL0 Security Region Top */ # define MATRIX_SRTSR_SRTOP1_MASK (15 << MATRIX_SRTSR_SRTOP1_SHIFT) # define MATRIX_SRTSR_SRTOP1(n) ((uint32_t)(n) << MATRIX_SRTSR_SRTOP1_SHIFT) /* See definitions above */ + # define MATRIX_SRTSR_SRTOP2_SHIFT (0) /* Bits 0-3: HSEL0 Security Region Top */ # define MATRIX_SRTSR_SRTOP2_MASK (15 << MATRIX_SRTSR_SRTOP2_SHIFT) # define MATRIX_SRTSR_SRTOP2(n) ((uint32_t)(n) << MATRIX_SRTSR_SRTOP2_SHIFT) /* See definitions above */ + # define MATRIX_SRTSR_SRTOP3_SHIFT (0) /* Bits 0-3: HSEL0 Security Region Top */ # define MATRIX_SRTSR_SRTOP3_MASK (15 << MATRIX_SRTSR_SRTOP3_SHIFT) # define MATRIX_SRTSR_SRTOP3(n) ((uint32_t)(n) << MATRIX_SRTSR_SRTOP3_SHIFT) /* See definitions above */ + # define MATRIX_SRTSR_SRTOP4_SHIFT (0) /* Bits 0-3: HSEL0 Security Region Top */ # define MATRIX_SRTSR_SRTOP4_MASK (15 << MATRIX_SRTSR_SRTOP4_SHIFT) # define MATRIX_SRTSR_SRTOP4(n) ((uint32_t)(n) << MATRIX_SRTSR_SRTOP4_SHIFT) /* See definitions above */ + # define MATRIX_SRTSR_SRTOP5_SHIFT (0) /* Bits 0-3: HSEL0 Security Region Top */ # define MATRIX_SRTSR_SRTOP5_MASK (15 << MATRIX_SRTSR_SRTOP5_SHIFT) # define MATRIX_SRTSR_SRTOP5(n) ((uint32_t)(n) << MATRIX_SRTSR_SRTOP5_SHIFT) /* See definitions above */ + # define MATRIX_SRTSR_SRTOP6_SHIFT (0) /* Bits 0-3: HSEL0 Security Region Top */ # define MATRIX_SRTSR_SRTOP6_MASK (15 << MATRIX_SRTSR_SRTOP6_SHIFT) # define MATRIX_SRTSR_SRTOP6(n) ((uint32_t)(n) << MATRIX_SRTSR_SRTOP6_SHIFT) /* See definitions above */ + # define MATRIX_SRTSR_SRTOP7_SHIFT (0) /* Bits 0-3: HSEL0 Security Region Top */ # define MATRIX_SRTSR_SRTOP7_MASK (15 << MATRIX_SRTSR_SRTOP7_SHIFT) # define MATRIX_SRTSR_SRTOP7(n) ((uint32_t)(n) << MATRIX_SRTSR_SRTOP7_SHIFT) /* See definitions above */ @@ -978,16 +998,16 @@ # define MATRIX_SPSELR3_NSECP(n) (1 << ((n)-64)) /* PID n Not Secured Peripheral, n=64-96 */ #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MATRIX_H */ diff --git a/arch/arm/src/sama5/hardware/sam_memorymap.h b/arch/arm/src/sama5/hardware/sam_memorymap.h index dbeec00f514..83ee507919e 100644 --- a/arch/arm/src/sama5/hardware/sam_memorymap.h +++ b/arch/arm/src/sama5/hardware/sam_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include diff --git a/arch/arm/src/sama5/hardware/sam_mpddrc.h b/arch/arm/src/sama5/hardware/sam_mpddrc.h index a2f7c036327..1d5f54e2a04 100644 --- a/arch/arm/src/sama5/hardware/sam_mpddrc.h +++ b/arch/arm/src/sama5/hardware/sam_mpddrc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_mpddrc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MPDDRC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MPDDRC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include diff --git a/arch/arm/src/sama5/hardware/sam_ohci.h b/arch/arm/src/sama5/hardware/sam_ohci.h index 7a70ee25e50..49aaca13910 100644 --- a/arch/arm/src/sama5/hardware/sam_ohci.h +++ b/arch/arm/src/sama5/hardware/sam_ohci.h @@ -34,11 +34,13 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* The SAMA5 supports 3 root hub ports */ #define SAM_OHCI_NRHPORT 3 /* Register offsets *********************************************************/ + /* See nuttx/usb/ohci.h */ /* Register addresses *******************************************************/ @@ -80,6 +82,7 @@ #define SAM_USBHOST_RHPORTST3 (SAM_UHPOHCI_VSECTION+OHCI_RHPORTST3_OFFSET) /* Register bit definitions *************************************************/ + /* See include/nuttx/usb/ohci.h */ /**************************************************************************** @@ -91,7 +94,7 @@ ****************************************************************************/ /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_OHCI_H */ diff --git a/arch/arm/src/sama5/hardware/sam_pinmap.h b/arch/arm/src/sama5/hardware/sam_pinmap.h index 276c84044fb..8c8dfe93b16 100644 --- a/arch/arm/src/sama5/hardware/sam_pinmap.h +++ b/arch/arm/src/sama5/hardware/sam_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PINMAP_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include diff --git a/arch/arm/src/sama5/hardware/sam_pio.h b/arch/arm/src/sama5/hardware/sam_pio.h index 077177fc07d..cc6394b81b6 100644 --- a/arch/arm/src/sama5/hardware/sam_pio.h +++ b/arch/arm/src/sama5/hardware/sam_pio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIO_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include diff --git a/arch/arm/src/sama5/hardware/sam_pit.h b/arch/arm/src/sama5/hardware/sam_pit.h index dc79853e7ff..5bd9fa18756 100644 --- a/arch/arm/src/sama5/hardware/sam_pit.h +++ b/arch/arm/src/sama5/hardware/sam_pit.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_pit.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,36 +16,37 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIT_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* PIT Register Offsets *************************************************************/ + ****************************************************************************/ + +/* PIT Register Offsets *****************************************************/ #define SAM_PIT_MR_OFFSET 0x0000 /* Mode Register */ #define SAM_PIT_SR_OFFSET 0x0004 /* Status Register */ #define SAM_PIT_PIVR_OFFSET 0x0008 /* Periodic Interval Value Register */ #define SAM_PIT_PIIR_OFFSET 0x000c /* Periodic Interval Image Register */ -/* PIT Register Addresses ***********************************************************/ +/* PIT Register Addresses ***************************************************/ #define SAM_PIT_MR (SAM_PITC_VBASE+SAM_PIT_MR_OFFSET) #define SAM_PIT_SR (SAM_PITC_VBASE+SAM_PIT_SR_OFFSET) #define SAM_PIT_PIVR (SAM_PITC_VBASE+SAM_PIT_PIVR_OFFSET) #define SAM_PIT_PIIR (SAM_PITC_VBASE+SAM_PIT_PIIR_OFFSET) -/* PIT Register Bit Definitions *****************************************************/ +/* PIT Register Bit Definitions *********************************************/ /* Mode Register */ @@ -60,6 +61,7 @@ #define PIT_SR_S (1 << 0) /* Bit 0: Periodic Interval Timer Status */ /* Periodic Interval Value Register */ + /* Periodic Interval Image Register */ #define PIT_CPIV_SHIFT (0) /* Bits 0-19: Current Periodic Interval Value */ diff --git a/arch/arm/src/sama5/hardware/sam_pmc.h b/arch/arm/src/sama5/hardware/sam_pmc.h index ec8af64bab9..202b228966a 100644 --- a/arch/arm/src/sama5/hardware/sam_pmc.h +++ b/arch/arm/src/sama5/hardware/sam_pmc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_pmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PMC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PMC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* PMC register offsets *********************************************************************/ +/* PMC register offsets *****************************************************/ #define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ #define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ @@ -102,7 +102,7 @@ # define SAM_PMC_AUDIO_PLL1_OFFSET 0x0150 /* Audio PLL Register 1 */ #endif -/* PMC register addresses *******************************************************************/ +/* PMC register addresses ***************************************************/ #define SAM_PMC_SCER (SAM_PMC_VBASE+SAM_PMC_SCER_OFFSET) #define SAM_PMC_SCDR (SAM_PMC_VBASE+SAM_PMC_SCDR_OFFSET) @@ -162,10 +162,10 @@ # define SAM_PMC_AUDIO_PLL1 (SAM_PMC_VBASE+SAM_PMC_AUDIO_PLL1_OFFSET) #endif -/* PMC register bit definitions *************************************************************/ +/* PMC register bit definitions *********************************************/ -/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System - * Clock Status Register common bit-field definitions +/* PMC System Clock Enable Register, PMC System Clock Disable Register, + * and PMC System Clock Status Register common bit-field definitions */ #if defined(ATSAMA5D2) || defined(ATSAMA5D3) @@ -191,8 +191,9 @@ # define PMC_ISCCK (1 << 18) /* Bit 18: ISC Clock Enable */ #endif -/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC - * Peripheral Clock Status Register common bit-field definitions. +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable + * Register, and PMC Peripheral Clock Status Register common bit-field + * definitions. */ #define PMC_PIDL(n) (1 << (n)) @@ -285,9 +286,9 @@ # define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ # define SAMA5_HAVE_PLLAR_DIV 1 -/* According the preliminary documentation, there is no DIV field in the SAMA5D4 - * PLLAR register. However, through trial and error, I find that the PLL output - * is still disabled if the DIV field is set to zero. +/* According the preliminary documentation, there is no DIV field in the + * SAMA5D4 PLLAR register. However, through trial and error, I find that + * the PLL output is still disabled if the DIV field is set to zero. */ #elif defined(ATSAMA5D4) @@ -300,6 +301,7 @@ #define PMC_CKGR_PLLAR_OUT_SHIFT (14) /* Bits 14-17: PLLA Clock Frequency Range */ #define PMC_CKGR_PLLAR_OUT_MASK (15 << PMC_CKGR_PLLAR_OUT_SHIFT) # define PMC_CKGR_PLLAR_OUT (0 << PMC_CKGR_PLLAR_OUT_SHIFT) /* To be programmed to 0 */ + #define PMC_CKGR_PLLAR_MUL_SHIFT (18) /* Bits 18-24: PLLA Multiplier */ #define PMC_CKGR_PLLAR_MUL_MASK (0x7f << PMC_CKGR_PLLAR_MUL_SHIFT) # define PMC_CKGR_PLLAR_MUL(n) ((uint32_t)(n) << PMC_CKGR_PLLAR_MUL_SHIFT) @@ -313,6 +315,7 @@ # define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ # define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ # define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ + #define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ #define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) # define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ @@ -322,12 +325,14 @@ # define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ # define PMC_MCKR_PRES_DIV32 (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ # define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ + #define PMC_MCKR_MDIV_SHIFT (8) /* Bits 8-9: Master Clock Division */ #define PMC_MCKR_MDIV_MASK (3 << PMC_MCKR_MDIV_SHIFT) # define PMC_MCKR_MDIV_PCKDIV1 (0 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 1 */ # define PMC_MCKR_MDIV_PCKDIV2 (1 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 2 */ # define PMC_MCKR_MDIV_PCKDIV4 (2 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 4 */ # define PMC_MCKR_MDIV_PCKDIV3 (3 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 3 */ + #define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */ #if defined(ATSAMA5D2) || defined(ATSAMA5D4) @@ -385,8 +390,8 @@ # define PMC_PCK_PRES(n) ((uint32_t)(n) << PMC_PCK_PRES_SHIFT) #endif -/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, - * and PMC Interrupt Mask Register common bit-field definitions +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status + * Register, and PMC Interrupt Mask Register common bit-field definitions */ #define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ @@ -420,6 +425,7 @@ /* Fast Startup Mode Register */ # define PMC_FSMR_FSTT(n) (1 << (n)) /* Bits 0-8: Fast Startup Input Enable 0 to 8 */ + # define PMC_FSMR_FSTT0 (1 << 0) /* Bit 0: Fast Startup Input Enable 0 */ # define PMC_FSMR_FSTT1 (1 << 1) /* Bit 1: Fast Startup Input Enable 1 */ # define PMC_FSMR_FSTT2 (1 << 2) /* Bit 2: Fast Startup Input Enable 2 */ @@ -440,6 +446,7 @@ /* Fast Startup Polarity Register */ # define PMC_FSPR_FSTP(n) (1 << (n)) /* Bits 0-8: Fast Startup Input Polarity 0 to 8 */ + # define PMC_FSPR_FSTP0 (1 << 0) /* Bit 0: Fast Startup Input Polarity 0 */ # define PMC_FSPR_FSTP1 (1 << 1) /* Bit 1: Fast Startup Input Polarity 1 */ # define PMC_FSPR_FSTP2 (1 << 2) /* Bit 2: Fast Startup Input Polarity 2 */ @@ -484,7 +491,9 @@ #define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) /* Peripheral Clock Enable Register 1 */ + /* Peripheral Clock Disable Register 1 */ + /* Peripheral Clock Status Register 1 */ #define PMC_PIDH(n) (1 << ((n) - 32)) @@ -576,11 +585,12 @@ #endif #ifdef ATSAMA5D2 -/* SleepWalking Enable Register 0, SleepWalking Disable Register 0, and SleepWalking - * Activity Status Register 0. +/* SleepWalking Enable Register 0, SleepWalking Disable Register 0, and + * SleepWalking Activity Status Register 0. */ # define PMC_SLPWK_ER0(n) (1 << (n)) /* Peripheral n SleepWalking Enable */ + # define PMC_SLPWK_ER0_PID19 (1 << 19) /* Peripheral 19 SleepWalking Enable */ # define PMC_SLPWK_ER0_PID20 (1 << 19) /* Peripheral 20 SleepWalking Enable */ # define PMC_SLPWK_ER0_PID21 (1 << 19) /* Peripheral 21 SleepWalking Enable */ @@ -596,17 +606,18 @@ #endif #ifdef ATSAMA5D2 -/* SleepWalking Enable Register 1, SleepWalking Disable Register 1, and SleepWalking Status - * Register 1, and SleepWalking Activity Status Register 1. +/* SleepWalking Enable Register 1, SleepWalking Disable Register 1, and + * SleepWalking Status Register 1, and SleepWalking Activity Status + * Register 1. */ # define PMC_SLPWK_ER1(n) (1 << ((n)-1)) /* Peripheral n SleepWalking Enable */ + # define PMC_SLPWK_ER1_PID33 (1 << 1) /* Peripheral 33 SleepWalking Enable */ # define PMC_SLPWK_ER1_PID34 (1 << 2) /* Peripheral 34 SleepWalking Enable */ # define PMC_SLPWK_ER1_PID40 (1 << 8) /* Peripheral 40 SleepWalking Enable */ #endif - #ifdef ATSAMA5D2 /* SleepWalking Activity In Progress Register */ @@ -652,16 +663,16 @@ # define PMC_AUDIO_PLL1_QDAUDIO(n) ((uint32_t)(n) << PMC_AUDIO_PLL1_QDAUDIO_SHIFT) #endif -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PMC_H */ diff --git a/arch/arm/src/sama5/hardware/sam_pwm.h b/arch/arm/src/sama5/hardware/sam_pwm.h index ffa1f9f88b2..f3823465968 100644 --- a/arch/arm/src/sama5/hardware/sam_pwm.h +++ b/arch/arm/src/sama5/hardware/sam_pwm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_pwm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PWM_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PWM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define SAM_PWM_NCHANNELS 4 /* Four channels numbered 0..3 */ -/* PWM Register Offsets *************************************************************/ +/* PWM Register Offsets *****************************************************/ #define SAM_PWM_CLK_OFFSET 0x0000 /* PWM Clock Register */ #define SAM_PWM_ENA_OFFSET 0x0004 /* PWM Enable Register */ @@ -132,7 +132,9 @@ #define SAM_PWM_CMPM7_OFFSET 0x01a8 /* PWM Comparison 7 Mode Register */ #define SAM_PWM_CMPMUPD7_OFFSET 0x01ac /* PWM Comparison 7 Mode Update Register */ /* 0x01b0 - 0x01fc Reserved */ + #define SAM_PWM_CHANA_OFFSET(n) (0x0200 + ((int)(n) << 5)) /* n=0..3 */ + #define SAM_PWM_CMR_OFFSET 0x0000 /* PWM Channel Mode Register */ #define SAM_PWM_CDTY_OFFSET 0x0004 /* PWM Channel Duty Cycle Register */ #define SAM_PWM_CDTYUPD_OFFSET 0x0008 /* PWM Channel Duty Cycle Update Register */ @@ -146,10 +148,11 @@ #ifdef ATSAMA5D4 # define SAM_PWM_CHANB_OFFSET(n) (0x0400 + ((int)(n) << 5)) /* n=0..3 */ + # define SAM_PWM_CMUPD_OFFSET 0x0000 /* PWM Channel Mode Update Register */ #endif -/* PWM Register Addresses ***********************************************************/ +/* PWM Register Addresses ***************************************************/ #define SAM_PWM_CLK (SAM_PWMC_VBASE+SAM_PWM_CLK_OFFSET) #define SAM_PWM_ENA (SAM_PWMC_VBASE+SAM_PWM_ENA_OFFSET) @@ -260,7 +263,7 @@ # define SAM_PWM_CMUPD(n) (SAM_PWM_CHANB_BASE(n)+SAM_PWM_CMUPD_OFFSET) #endif -/* PWM Register Bit Definitions *****************************************************/ +/* PWM Register Bit Definitions *********************************************/ /* PWM Clock Register */ @@ -269,6 +272,7 @@ # define PWM_CLK_DIVA_OFF (0 << PWM_CLK_DIVA_SHIFT) /* CLKA clock = off */ # define PWM_CLK_DIVA_PREA (1 << PWM_CLK_DIVA_SHIFT) /* CLKA clock = clock selected by PREA */ # define PWM_CLK_DIVA(n) ((uint32_t)(n) << PWM_CLK_DIVA_SHIFT) /* CLKA clock = clock selected by PREA / DIVA */ + #define PWM_CLK_PREA_SHIFT (8) /* Bits 8-11: CLKA Source Clock Selection */ #define PWM_CLK_PREA_MASK (15 << PWM_CLK_PREA_SHIFT) # define PWM_CLK_PREA_DIV(n) ((uint32_t)(n) << PWM_CLK_PREA_SHIFT) @@ -283,11 +287,13 @@ # define PWM_CLK_PREA_DIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */ # define PWM_CLK_PREA_DIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */ # define PWM_CLK_PREA_DIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */ + #define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */ #define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT) # define PWM_CLK_DIVB_OFF (0 << PWM_CLK_DIVB_SHIFT) /* CLKB clock = off */ # define PWM_CLK_DIVB_PREB (1 << PWM_CLK_DIVB_SHIFT) /* CLKB clock = clock selected by PREB */ # define PWM_CLK_DIVB(n) ((uint32_t)(n) << PWM_CLK_DIVB_SHIFT) /* CLKB clock = clock selected by PREB / DIVB */ + #define PWM_CLK_PREB_SHIFT (24) /* Bits 24-27: CLKB Source Clock Selection */ #define PWM_CLK_PREB_MASK (15 << PWM_CLK_PREB_SHIFT) # define PWM_CLK_PREB_DIV(n) ((uint32_t)(n) << PWM_CLK_PREB_SHIFT) @@ -307,8 +313,8 @@ #define PWM_CHID(n) (1 << (n)) /* Bits 0-3: Channel ID n, n=0..3 */ -/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt - * Mask Register 1, and PWM Interrupt Status Register 1 +/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, + * PWM Interrupt Mask Register 1, and PWM Interrupt Status Register 1 */ #define PWM_INT1_CHID(n) (1 << (n)) /* Bits 0-3: Counter Event on Channel n Interrupt, n=0..3 */ @@ -361,13 +367,15 @@ #define PWM_SCUPUPD_UPRUPD_MASK (15 << PWM_SCUPUPD_UPRUPD_SHIFT) # define PWM_SCUPUPD_UPRUPD(n) ((uint32_t)(n) << PWM_SCUPUPD_UPRUPD_SHIFT) -/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt - * Mask Register 2, and PWM Interrupt Status Register 2. +/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, + * PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2. */ #define PWM_INT2_WRDY (1 << 0) /* Bit 0: Write Ready for Synchronous Channels Update Interrupt Enable */ #define PWM_INT2_UNRE (1 << 3) /* Bit 3: Synchronous Channels Update Underrun Error Interrupt Enable */ + #define PWM_INT2_CMPM(n) (1 << ((n)+8)) /* Bits 8-15: Comparison n Match Interrupt Enable, n=0..7 */ + # define PWM_INT2_CMPM0 (1 << 8) /* Bit 8: Comparison 0 Match Interrupt Enable */ # define PWM_INT2_CMPM1 (1 << 9) /* Bit 9: Comparison 1 Match Interrupt Enable */ # define PWM_INT2_CMPM2 (1 << 10) /* Bit 10: Comparison 2 Match Interrupt Enable */ @@ -376,7 +384,9 @@ # define PWM_INT2_CMPM5 (1 << 13) /* Bit 13: Comparison 5 Match Interrupt Enable */ # define PWM_INT2_CMPM6 (1 << 14) /* Bit 14: Comparison 6 Match Interrupt Enable */ # define PWM_INT2_CMPM7 (1 << 15) /* Bit 15: Comparison 7 Match Interrupt Enable */ + #define PWM_INT2_CMPU(n) (1 << ((n)+16)) /* Bits 16-23: Comparison n Update Interrupt Enable, n=0..7 */ + # define PWM_INT2_CMPU0 (1 << 16) /* Bit 16: Comparison 0 Update Interrupt Enable */ # define PWM_INT2_CMPU1 (1 << 17) /* Bit 17: Comparison 1 Update Interrupt Enable */ # define PWM_INT2_CMPU2 (1 << 18) /* Bit 18: Comparison 2 Update Interrupt Enable */ @@ -390,11 +400,14 @@ /* PWM Output Override Value Register */ #define PWM_OOV_H(n) (1 << (n)) /* Bits 0-3: Output Override PWMH channel n, n=0..3 */ + # define PWM_OOV_H0 (1 << 0) /* Bit 0: Output Override PWMH channel 0 */ # define PWM_OOV_H1 (1 << 1) /* Bit 1: Output Override PWMH channel 1 */ # define PWM_OOV_H2 (1 << 2) /* Bit 2: Output Override PWMH channel 2 */ # define PWM_OOV_H3 (1 << 3) /* Bit 3: Output Override PWMH channel 3 */ + #define PWM_OOV_L(n) (1 << ((n)+16)) /* Bits 16-19: Output Override PWML channel n, n=0..3 */ + # define PWM_OOV_L0 (1 << 16) /* Bit 16: Output Override PWML channel 0 */ # define PWM_OOV_L1 (1 << 17) /* Bit 17: Output Override PWML channel 1 */ # define PWM_OOV_L2 (1 << 18) /* Bit 18: Output Override PWML channel 2 */ @@ -403,11 +416,14 @@ /* PWM Output Selection Register */ #define PWM_OS_H(n) (1 << (n)) /* Bits 0-3: Output Selection for PWMH channel n, n=0..3 */ + # define PWM_OS_H0 (1 << 0) /* Bit 0: Output Selection for PWMH channel 0 */ # define PWM_OS_H1 (1 << 1) /* Bit 0: Output Selection for PWMH channel 0 */ # define PWM_OS_H2 (1 << 2) /* Bit 0: Output Selection for PWMH channel 0 */ # define PWM_OS_H3 (1 << 3) /* Bit 0: Output Selection for PWMH channel 0 */ + #define PWM_OS_L(n) (1 << ((n)+16)) /* Bits 16-19: Output Selection for PWML channel n, n=0..3 */ + # define PWM_OS_L0 (1 << 16) /* Bit 16: Output Selection for PWML channel 0 */ # define PWM_OS_L1 (1 << 17) /* Bit 17: Output Selection for PWML channel 1 */ # define PWM_OS_L2 (1 << 18) /* Bit 18: Output Selection for PWML channel 2 */ @@ -416,11 +432,14 @@ /* PWM Output Selection Set Register */ #define PWM_OSS_H(n) (1 << (n)) /* Bits 0-3: Output Selection Set for PWMH channel n, n=0..3 */ + # define PWM_OSS_H0 (1 << 0) /* Bit 0: Output Selection Set for PWMH channel 0 */ # define PWM_OSS_H1 (1 << 1) /* Bit 1: Output Selection Set for PWMH channel 1 */ # define PWM_OSS_H2 (1 << 2) /* Bit 2: Output Selection Set for PWMH channel 2 */ # define PWM_OSS_H3 (1 << 3) /* Bit 3: Output Selection Set for PWMH channel 3 */ + #define PWM_OSS_L(n) (1 << ((n)+16)) /* Bits 16-19: Output Selection Set for PWML channel n, n=0..3 */ + # define PWM_OSS_L0 (1 << 16) /* Bit 16: Output Selection Set for PWML channel 0 */ # define PWM_OSS_L1 (1 << 17) /* Bit 17: Output Selection Set for PWML channel 1 */ # define PWM_OSS_L2 (1 << 18) /* Bit 18: Output Selection Set for PWML channel 2 */ @@ -429,11 +448,14 @@ /* PWM Output Selection Clear Register */ #define PWM_OSC_H(n) (1 << (n)) /* Bits 0-3: Output Selection Clear for PWMH channel n, n=0..3 */ + # define PWM_OSC_H0 (1 << 0) /* Bit 0: Output Selection Clear for PWMH channel 0 */ # define PWM_OSC_H1 (1 << 1) /* Bit 1: Output Selection Clear for PWMH channel 1 */ # define PWM_OSC_H2 (1 << 2) /* Bit 2: Output Selection Clear for PWMH channel 2 */ # define PWM_OSC_H3 (1 << 3) /* Bit 3: Output Selection Clear for PWMH channel 3 */ + #define PWM_OSC_L(n) (1 << ((n)+16)) /* Bits 16-19: Output Selection Clear for PWML channel n, n=0..3 */ + # define PWM_OSC_L0 (1 << 16) /* Bit 16: Output Selection Clear for PWML channel 0 */ # define PWM_OSC_L1 (1 << 17) /* Bit 17: Output Selection Clear for PWML channel 1 */ # define PWM_OSC_L2 (1 << 18) /* Bit 18: Output Selection Clear for PWML channel 2 */ @@ -442,11 +464,14 @@ /* PWM Output Selection Set Update Register */ #define PWM_OSSUPD_H(n) (1 << (n)) /* Bits 0-3: Output Selection Set for PWMH channel n, n=0..3 */ + # define PWM_OSSUPD_H0 (1 << 0) /* Bit 0: Output Selection Set for PWMH channel 0 */ # define PWM_OSSUPD_H1 (1 << 1) /* Bit 1: Output Selection Set for PWMH channel 1 */ # define PWM_OSSUPD_H2 (1 << 2) /* Bit 2: Output Selection Set for PWMH channel 2 */ # define PWM_OSSUPD_H3 (1 << 3) /* Bit 3: Output Selection Set for PWMH channel 3 */ + #define PWM_OSSUPD_L(n) (1 << ((n)+16)) /* Bits 16-19: Output Selection Set for PWML channel n, n=0..3 */ + # define PWM_OSSUPD_L0 (1 << 16) /* Bit 16: Output Selection Set for PWML channel 0 */ # define PWM_OSSUPD_L1 (1 << 17) /* Bit 17: Output Selection Set for PWML channel 1 */ # define PWM_OSSUPD_L2 (1 << 18) /* Bit 18: Output Selection Set for PWML channel 2 */ @@ -455,11 +480,14 @@ /* PWM Output Selection Clear Update Register */ #define PWM_OSCUPD_H(n) (1 << (n)) /* Bits 0-3: Output Selection Clear for PWMH channel n, n=0..3 */ + # define PWM_OSCUPD_H0 (1 << 0) /* Bit 0: Output Selection Clear for PWMH channel 0 */ # define PWM_OSCUPD_H1 (1 << 1) /* Bit 1: Output Selection Clear for PWMH channel 1 */ # define PWM_OSCUPD_H2 (1 << 2) /* Bit 2: Output Selection Clear for PWMH channel 2 */ # define PWM_OSCUPD_H3 (1 << 3) /* Bit 3: Output Selection Clear for PWMH channel 3 */ + #define PWM_OSCUPD_L(n) (1 << ((n)+16)) /* Bits 16-19: Output Selection Clear for PWML channel n, n=0..3 */ + # define PWM_OSCUPD_L0 (1 << 16) /* Bit 16: Output Selection Clear for PWML channel 0 */ # define PWM_OSCUPD_L1 (1 << 17) /* Bit 17: Output Selection Clear for PWML channel 1 */ # define PWM_OSCUPD_L2 (1 << 18) /* Bit 18: Output Selection Clear for PWML channel 2 */ @@ -495,11 +523,14 @@ /* PWM Fault Protection Value Register 1 */ #define PWM_FPV_H(n) (1 << (n)) /* Bits 0-3: Fault Protection PWMH output on channel n, n=0..3 */ + # define PWM_FPV_H0 (1 << 0) /* Bit 0: Fault Protection PWMH output on channel 0 */ # define PWM_FPV_H1 (1 << 1) /* Bit 1: Fault Protection PWMH output on channel 1 */ # define PWM_FPV_H2 (1 << 2) /* Bit 2: Fault Protection PWMH output on channel 2 */ # define PWM_FPV_H3 (1 << 3) /* Bit 3: Fault Protection PWMH output on channel 3 */ + #define PWM_FPV_L(n) (1 << ((n)+16)) /* Bits 16-19: Fault Protection PWML output on channel n, n=0..3 */ + # define PWM_FPV_L0 (1 << 16) /* Bit 16: Fault Protection PWML output on channel 0 */ # define PWM_FPV_L1 (1 << 17) /* Bit 17: Fault Protection PWML output on channel 1 */ # define PWM_FPV_L2 (1 << 18) /* Bit 18: Fault Protection PWML output on channel 2 */ @@ -526,6 +557,7 @@ /* PWM Event Line 0/1 Mode Register */ #define PWM_ELMR_CSEL(n) (1 << (n)) /* Bits 0-7: Comparison n Selection, n=0..7 */ + # define PWM_ELMR_CSEL0 (1 << 0) /* Bit 0: Comparison 0 Selection */ # define PWM_ELMR_CSEL1 (1 << 1) /* Bit 1: Comparison 1 Selection */ # define PWM_ELMR_CSEL2 (1 << 2) /* Bit 2: Comparison 2 Selection */ @@ -565,11 +597,14 @@ /* PWM Fault Protection Value Register 2 */ #define PWM_FPV2_FPZH(n) (1 << (n)) /* Bits 0-3: Fault Protection Hi-Z for PWMH channel n, n=0..3 */ + # define PWM_FPV2_FPZH0 (1 << 0) /* Bit 0: Fault Protection Hi-Z for PWMH channel 0 */ # define PWM_FPV2_FPZH1 (1 << 1) /* Bit 1: Fault Protection Hi-Z for PWMH channel 1 */ # define PWM_FPV2_FPZH2 (1 << 2) /* Bit 2: Fault Protection Hi-Z for PWMH channel 2 */ # define PWM_FPV2_FPZH3 (1 << 3) /* Bit 3: Fault Protection Hi-Z for PWMH channel 3 */ + #define PWM_FPV2_L(n) (1 << ((n)+16)) /* Bits 16-19: Fault Protection Hi-Z for PWML channel n, n=0..3 */ + # define PWM_FPV2_FPZL0 (1 << 16) /* Bit 16: Fault Protection Hi-Z for PWML channel 0 */ # define PWM_FPV2_FPZL1 (1 << 17) /* Bit 17: Fault Protection Hi-Z for PWML channel 1 */ # define PWM_FPV2_FPZL2 (1 << 18) /* Bit 18: Fault Protection Hi-Z for PWML channel 2 */ @@ -583,7 +618,9 @@ # define PWM_WPCR_WPCMD_DSWPROT (0 << PWM_WPCR_WPCMD_SHIFT) /* Disable software write protection */ # define PWM_WPCR_WPCMD_ESWPROT (1 << PWM_WPCR_WPCMD_SHIFT) /* Enable software write protection */ # define PWM_WPCR_WPCMD_EHWPROT (2 << PWM_WPCR_WPCMD_SHIFT) /* Enable hardware write protection */ + #define PWM_WPCR_WPRG(n) (1 << ((n)+2)) /* Bits 2-7: Write Protect Register Group n, n=0..5 */ + # define PWM_WPCR_WPRG0 (1 << 2) /* Bit 2: Write Protect Register Group 0 */ # define PWM_WPCR_WPRG1 (1 << 3) /* Bit 3: Write Protect Register Group 1 */ # define PWM_WPCR_WPRG2 (1 << 4) /* Bit 4: Write Protect Register Group 2 */ @@ -597,6 +634,7 @@ /* PWM Write Protect Status Register */ #define PWM_WPSR_WPSWS(n) (1 << (n)) /* Bits 0-5: Write Protect SW Status, n=0..5 */ + # define PWM_WPSR_WPSWS0 (1 << 0) /* Bit 0: Write Protect SW Status 0 */ # define PWM_WPSR_WPSWS1 (1 << 1) /* Bit 1: Write Protect SW Status 1 */ # define PWM_WPSR_WPSWS2 (1 << 2) /* Bit 2: Write Protect SW Status 2 */ @@ -604,7 +642,9 @@ # define PWM_WPSR_WPSWS4 (1 << 4) /* Bit 4: Write Protect SW Status 4 */ # define PWM_WPSR_WPSWS5 (1 << 5) /* Bit 5: Write Protect SW Status 5 */ #define PWM_WPSR_WPVS (1 << 7) /* Bit 7: Write Protect Violation Status */ + #define PWM_WPSR_WPHWS(n) (1 << ((n)+8)) /* Bits 8-13: Write Protect HW Status, n=0..5 */ + # define PWM_WPSR_WPHWS0 (1 << 8) /* Bit 8: Write Protect HW Status 0 */ # define PWM_WPSR_WPHWS1 (1 << 9) /* Bit 9: Write Protect HW Status 1 */ # define PWM_WPSR_WPHWS2 (1 << 10) /* Bit 10: Write Protect HW Status 2 */ @@ -665,6 +705,7 @@ #define PWM_CMR_CPRE_SHIFT (0) /* Bits 0-3: Channel Pre-scaler */ #define PWM_CMR_CPRE_MASK (15 << PWM_CMR_CPRE_SHIFT) # define PWM_CMR_CPRE_MCKDIV(n) ((uint32_t)(n) << PWM_CMR_CPRE_SHIFT) /* Master clock */ + # define PWM_CMR_CPRE_MCKDIV1 (0 << PWM_CMR_CPRE_SHIFT) /* Master clock/2 */ # define PWM_CMR_CPRE_MCKDIV2 (1 << PWM_CMR_CPRE_SHIFT) /* Master clock/2 */ # define PWM_CMR_CPRE_MCKDIV4 (2 << PWM_CMR_CPRE_SHIFT) /* Master clock/4 */ @@ -678,6 +719,7 @@ # define PWM_CMR_CPRE_MCKDIV1024 (10 << PWM_CMR_CPRE_SHIFT) /* Master clock/1024 */ # define PWM_CMR_CPRE_CLKA (11 << PWM_CMR_CPRE_SHIFT) /* Clock A */ # define PWM_CMR_CPRE_CLKB (12 << PWM_CMR_CPRE_SHIFT) /* Clock B */ + #define PWM_CMR_CALG (1 << 8) /* Bit 8: Channel Alignment */ #define PWM_CMR_CPOL (1 << 9) /* Bit 9: Channel Polarity */ #define PWM_CMR_CES (1 << 10) /* Bit 10: Counter Event Selection */ diff --git a/arch/arm/src/sama5/hardware/sam_rstc.h b/arch/arm/src/sama5/hardware/sam_rstc.h index ed894e3111f..fe9477d0ffb 100644 --- a/arch/arm/src/sama5/hardware/sam_rstc.h +++ b/arch/arm/src/sama5/hardware/sam_rstc.h @@ -66,6 +66,7 @@ # define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */ # define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */ # define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */ + #define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */ #define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */ diff --git a/arch/arm/src/sama5/hardware/sam_rtc.h b/arch/arm/src/sama5/hardware/sam_rtc.h index 6b50b7affc4..2f6d31c0ac6 100644 --- a/arch/arm/src/sama5/hardware/sam_rtc.h +++ b/arch/arm/src/sama5/hardware/sam_rtc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RTC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RTC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* RTC register offsets *****************************************************************/ +/* RTC register offsets *****************************************************/ #define SAM_RTC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_RTC_MR_OFFSET 0x0004 /* Mode Register */ @@ -58,7 +58,7 @@ # define SAM_RTC_TSSR1_OFFSET 0x00c4 /* TimeStamp Source Register 1 */ #endif -/* RTC register addresses ***************************************************************/ +/* RTC register addresses ***************************************************/ #define SAM_RTC_CR (SAM_RTCC_VBASE+SAM_RTC_CR_OFFSET) #define SAM_RTC_MR (SAM_RTCC_VBASE+SAM_RTC_MR_OFFSET) @@ -82,7 +82,7 @@ # define SAM_RTC_TSSR1 (SAM_RTCC_VBASE+SAM_RTC_TSSR1_OFFSET) #endif -/* RTC register bit definitions *********************************************************/ +/* RTC register bit definitions *********************************************/ /* RTC Control Register */ @@ -282,7 +282,7 @@ #endif #ifdef ATSAMA5D4 -/* TimeStamp Source Register 0 and 1*/ +/* TimeStamp Source Register 0 and 1 */ # define RTC_TSSR_SHLDM (1 << 0) /* Bit 0: Shield Monitor */ # define RTC_TSSR_DBLFM (1 << 1) /* Bit 1: Double Frequency Monitor */ @@ -320,16 +320,16 @@ # define RTC_TSSR_DET15 (1 << 31) /* Bit 31: PIOBU Intrusion Detector */ #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RTC_H */ diff --git a/arch/arm/src/sama5/hardware/sam_rxlp.h b/arch/arm/src/sama5/hardware/sam_rxlp.h index cfe4c6df63e..e267e2387d0 100644 --- a/arch/arm/src/sama5/hardware/sam_rxlp.h +++ b/arch/arm/src/sama5/hardware/sam_rxlp.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_rxlp.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RXLP_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RXLP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* RXLP register offsets ************************************************************************/ +/* RXLP register offsets ****************************************************/ #define SAM_RXLP_CR_OFFSET 0x0000 /* Control Register */ #define SAM_RXLP_MR_OFFSET 0x0004 /* Mode Register */ @@ -47,7 +47,7 @@ #define SAM_RXLP_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (4) */ /* 0x00e8-0xfc: Reserved */ -/* RXLP register addresses **********************************************************************/ +/* RXLP register addresses **************************************************/ #define SAM_RXLP0_CR (SAM_RXLP_VBASE+SAM_RXLP_CR_OFFSET) #define SAM_RXLP0_MR (SAM_RXLP_VBASE+SAM_RXLP_MR_OFFSET) @@ -56,7 +56,7 @@ #define SAM_RXLP0_CMPR (SAM_RXLP_VBASE+SAM_RXLP_CMPR_OFFSET) #define SAM_RXLP0_WPMR (SAM_RXLP_VBASE+SAM_RXLP_WPMR_OFFSET) -/* RXLP register bit definitions ****************************************************************/ +/* RXLP register bit definitions ********************************************/ /* RXLP Control Register */ @@ -102,16 +102,16 @@ #define RXLP_WPMR_WPKEY_MASK (0x00ffffff << RXLP_WPMR_WPKEY_SHIFT) # define RXLP_WPMR_WPKEY (0x0052584c << RXLP_WPMR_WPKEY_SHIFT) /* "RXL" */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RXLP_H */ diff --git a/arch/arm/src/sama5/hardware/sam_sckc.h b/arch/arm/src/sama5/hardware/sam_sckc.h index 2d8bd5b8041..329f1df06a0 100644 --- a/arch/arm/src/sama5/hardware/sam_sckc.h +++ b/arch/arm/src/sama5/hardware/sam_sckc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_sckc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,30 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SCKC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SCKC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* SCKC Register Offsets ************************************************************/ + ****************************************************************************/ + +/* SCKC Register Offsets ****************************************************/ #define SAM_SCKC_CR_OFFSET 0x0000 /* Slow Clock Controller Configuration Register */ -/* SCKC Register Addresses **********************************************************/ +/* SCKC Register Addresses **************************************************/ #define SAM_SCKC_CR (SAM_SCKCR_VBASE+SAM_SCKC_CR_OFFSET) -/* SCKC Register Bit Definitions ****************************************************/ +/* SCKC Register Bit Definitions ********************************************/ /* Slow Clock Controller Configuration Register */ diff --git a/arch/arm/src/sama5/hardware/sam_sdmmc.h b/arch/arm/src/sama5/hardware/sam_sdmmc.h index 0df9658215f..ceec0139b28 100644 --- a/arch/arm/src/sama5/hardware/sam_sdmmc.h +++ b/arch/arm/src/sama5/hardware/sam_sdmmc.h @@ -189,6 +189,7 @@ # define SDMMC_XFERTYP_RSPTYP_LEN136 (1 << SDMMC_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */ # define SDMMC_XFERTYP_RSPTYP_LEN48 (2 << SDMMC_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */ # define SDMMC_XFERTYP_RSPTYP_LEN48BSY (3 << SDMMC_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */ + /* Bit 18: Reserved */ #define SDMMC_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */ #define SDMMC_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */ @@ -199,6 +200,7 @@ # define SDMMC_XFERTYP_CMDTYP_SUSPEND (1 << SDMMC_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */ # define SDMMC_XFERTYP_CMDTYP_RESUME (2 << SDMMC_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */ # define SDMMC_XFERTYP_CMDTYP_ABORT (3 << SDMMC_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */ + #define SDMMC_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */ #define SDMMC_XFERTYP_CMDINX_MASK (0x3f << SDMMC_XFERTYP_CMDINX_SHIFT) /* Bits 30-31: Reserved */ @@ -244,6 +246,7 @@ #define SDMMC_PROCTL_DTW_MASK (1 << SDMMC_PROCTL_DTW_SHIFT) # define SDMMC_PROCTL_DTW_1BIT (0 << SDMMC_PROCTL_DTW_SHIFT) /* 1-bit mode */ # define SDMMC_PROCTL_DTW_4BIT (1 << SDMMC_PROCTL_DTW_SHIFT) /* 4-bit mode */ + #define SDMMC_PROCTL_HSEN (1 << 2) /* Bit 2: High Speed Enable */ #define SDMMC_PROCTL_DMAS_SHIFT (3) /* Bits 3-4: DMA Select */ #define SDMMC_PROCTL_DMAS_MASK (3 << SDMMC_PROCTL_DMAS_SHIFT) @@ -251,6 +254,7 @@ # define SDMMC_PROCTL_DMAS_RES1 (1 << SDMMC_PROCTL_DMAS_SHIFT) /* Reserved */ # define SDMMC_PROCTL_DMAS_ADMA (2 << SDMMC_PROCTL_DMAS_SHIFT) /* ADMA is selected */ # define SDMMC_PROCTL_DMAS_RES2 (1 << SDMMC_PROCTL_DMAS_SHIFT) /* Reserved */ + #define SDMMC_PROCTL_EXTDW_SHIFT (5) /* Bits 3-4: DMA Select */ #define SDMMC_PROCTL_EXTDW_MASK (1 << SDMMC_PROCTL_EXTDW_SHIFT) /* Bits 6-7: Reserved */ @@ -271,6 +275,7 @@ # define SDMMC_PROCTL_BURST_INCR (1 << SDMMC_PROCTL_BURST_SHIFT) /* Burst for Incr */ # define SDMMC_PROCTL_BURST_4816 (2 << SDMMC_PROCTL_BURST_SHIFT) /* Burst for 4/8/16 */ # define SDMMC_PROCTL_BURST_4W8W16W (4 << SDMMC_PROCTL_BURST_SHIFT) /* Burst for 4w/8w/16w */ + #define SDMMC_PROTCTL_NEBLKRD (1 << 30) /* Bit 30: Non-exect block read */ /* Bit 31: Reserved */ @@ -289,12 +294,13 @@ #define SDMMC_SYSCTL_CLKGSEL (1 << 5) /* Bit 5: Clock Generator Select */ #define SDMMC_SYSCTL_USDCLKFSEL (3 << 6) /* Bit 0: Upper bits of SDCLK Frequency Select */ #define SDMMC_SYSCTL_CLKFSEL (0xf0) /* Bit 0: SDCLK Frequency Select */ -#define SDMMC_CLOCK_MUL_MASK (0x00ff0000) -#define SDMMC_CLOCK_MUL_SHIFT (16) +#define SDMMC_CLOCK_MUL_MASK (0x00ff0000) +#define SDMMC_CLOCK_MUL_SHIFT (16) #define SDMMC_SYSCTL_DVS_SHIFT (4) /* Bits 4-7: Divisor */ #define SDMMC_SYSCTL_DVS_MASK (0x0f << SDMMC_SYSCTL_DVS_SHIFT) # define SDMMC_SYSCTL_DVS_DIV(n) (((n) - 1) << SDMMC_SYSCTL_DVS_SHIFT) /* Divide by n, n=1..16 */ + #define SDMMC_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */ #define SDMMC_SYSCTL_SDCLKFS_MASK (0xff << SDMMC_SYSCTL_SDCLKFS_SHIFT) # define SDMMC_SYSCTL_SDCLKFS_BYPASS (0x00 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Bypass the prescaler */ @@ -306,10 +312,12 @@ # define SDMMC_SYSCTL_SDCLKFS_DIV64 (0x20 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 64 */ # define SDMMC_SYSCTL_SDCLKFS_DIV128 (0x40 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 128 */ # define SDMMC_SYSCTL_SDCLKFS_DIV256 (0x80 << SDMMC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 256 */ + #define SDMMC_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */ #define SDMMC_SYSCTL_DTOCV_MASK (0x0f << SDMMC_SYSCTL_DTOCV_SHIFT) # define SDMMC_SYSCTL_DTOCV_MUL(n) (((n) - 213) << SDMMC_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */ - /* Bits 20-22: Reserved */ + + /* Bits 20-22: Reserved */ #define SDMMC_SYSCTL_IPPRSTN (1 << 23) /* Bit 23: Card /reset (default 1) */ #define SDMMC_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */ #define SDMMC_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */ @@ -444,9 +452,11 @@ # define SDMMC_ADMAES_FDS (1 << SDMMC_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */ # define SDMMC_ADMAES_CADR (2 << SDMMC_ADMAES_ADMAES_SHIFT) /* Change address */ # define SDMMC_ADMAES_TFR (3 << SDMMC_ADMAES_ADMAES_SHIFT) /* Transfer data */ + #define SDMMC_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */ #define SDMMC_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */ /* Bits 4-31: Reserved */ + /* ADMA System Address Register */ #define SDMMC_ADSADDR_SHIFT (0) /* Bits 1-31: ADMA System Address */ diff --git a/arch/arm/src/sama5/hardware/sam_sfr.h b/arch/arm/src/sama5/hardware/sam_sfr.h index 173c99cc5e3..c8ae212766a 100644 --- a/arch/arm/src/sama5/hardware/sam_sfr.h +++ b/arch/arm/src/sama5/hardware/sam_sfr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_sfr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SFR_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SFR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* SFR Register Offsets *************************************************************/ + ****************************************************************************/ + +/* SFR Register Offsets *****************************************************/ /* 0x0000: Reserved */ #define SAM_SFR_DDRCFG_OFFSET 0x0004 /* DDR Configuration register */ @@ -70,7 +71,7 @@ #endif /* 0x0098-0x3ffc: Reserved */ -/* SFR Register Addresses ***********************************************************/ +/* SFR Register Addresses ***************************************************/ #define SAM_SFR_DDRCFG (SAM_SFR_VBASE+SAM_SFR_DDRCFG_OFFSET) /* REVISIT */ #define SAM_SFR_OHCIICR (SAM_SFR_VBASE+SAM_SFR_OHCIICR_OFFSET) @@ -103,7 +104,7 @@ # define SAM_SFR_QSPICLK (SAM_SFR_VBASE+SAM_SFR_QSPICLK_OFFSET) #endif -/* SFR Register Bit Definitions *****************************************************/ +/* SFR Register Bit Definitions *********************************************/ /* DDR Configuration register */ @@ -113,11 +114,11 @@ /* OHCI Interrupt Configuration Register */ #define SFR_OHCIICR_RES(n) (1 << (n)) /* Bit 0: USB port n reset, n=0..2 */ -# define SFR_OHCIICR_RES0 (1 << 0) /* Bit 0: USB port 0 reset */ -# define SFR_OHCIICR_RES1 (1 << 1) /* Bit 1: USB port 1 reset */ -# define SFR_OHCIICR_RES2 (1 << 2) /* Bit 2: USB port 2 reset */ -#define SFR_OHCIICR_ARIE (1 << 4) /* Bit 4: OHCI asynchronous resume interrupt enable */ -#define SFR_OHCIICR_APPSTART (0) /* Bit 5: Reserved, must write 0 */ +# define SFR_OHCIICR_RES0 (1 << 0) /* Bit 0: USB port 0 reset */ +# define SFR_OHCIICR_RES1 (1 << 1) /* Bit 1: USB port 1 reset */ +# define SFR_OHCIICR_RES2 (1 << 2) /* Bit 2: USB port 2 reset */ +#define SFR_OHCIICR_ARIE (1 << 4) /* Bit 4: OHCI asynchronous resume interrupt enable */ +#define SFR_OHCIICR_APPSTART (0) /* Bit 5: Reserved, must write 0 */ #ifdef ATSAMA5D2 # define SFR_OHCIICR_SUSPEND(n) (1 << ((n)+8)) @@ -204,9 +205,9 @@ /* UTMI DP/DM Pin Swapping Register */ # define SFR_UTMISWAP_PORT(n) (1 << (n)) /* Bit n: PORT n DP/DM Pin Swapping */ -# define SFR_UTMISWAP_PORT0 (1 << 0) /* Bit 0: PORT 0 DP/DM Pin Swapping */ -# define SFR_UTMISWAP_PORT1 (1 << 1) /* Bit 1: PORT 1 DP/DM Pin Swapping */ -# define SFR_UTMISWAP_PORT2 (1 << 2) /* Bit 2: PORT 2 DP/DM Pin Swapping */ +# define SFR_UTMISWAP_PORT0 (1 << 0) /* Bit 0: PORT 0 DP/DM Pin Swapping */ +# define SFR_UTMISWAP_PORT1 (1 << 1) /* Bit 1: PORT 1 DP/DM Pin Swapping */ +# define SFR_UTMISWAP_PORT2 (1 << 2) /* Bit 2: PORT 2 DP/DM Pin Swapping */ #endif /* EBI Configuration Register */ @@ -256,7 +257,9 @@ #endif #if defined(ATSAMA5D2) || defined(ATSAMA5D4) + /* Serial Number 0 Register (32-bit value) */ + /* Serial Number 1 Register (32-bit value) */ /* AIC Redirection Register */ diff --git a/arch/arm/src/sama5/hardware/sam_spi.h b/arch/arm/src/sama5/hardware/sam_spi.h index 13549f1e4f7..49192dc86ad 100644 --- a/arch/arm/src/sama5/hardware/sam_spi.h +++ b/arch/arm/src/sama5/hardware/sam_spi.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SPI_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SPI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General definitions ******************************************************************/ + ****************************************************************************/ + +/* General definitions ******************************************************/ #define SAM_SPI_NCS 4 /* Four chip selects */ -/* SPI register offsets *****************************************************************/ +/* SPI register offsets *****************************************************/ #define SAM_SPI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_SPI_MR_OFFSET 0x0004 /* Mode Register */ @@ -57,7 +58,7 @@ #define SAM_SPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ /* 0xec-0x124: Reserved */ -/* SPI register addresses ***************************************************************/ +/* SPI register addresses ***************************************************/ #define SAM_SPI0_CR (SAM_SPI0_VBASE+SAM_SPI_CR_OFFSET) #define SAM_SPI0_MR (SAM_SPI0_VBASE+SAM_SPI_MR_OFFSET) @@ -106,7 +107,7 @@ # define SAM_SPI2_WPSR (SAM_SPI2_VBASE+SAM_SPI_WPSR_OFFSET) #endif -/* SPI register bit definitions *********************************************************/ +/* SPI register bit definitions *********************************************/ /* SPI Control Register */ @@ -129,6 +130,7 @@ # define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ # define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ # define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ + #define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */ #define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT) @@ -153,10 +155,11 @@ # define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ # define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ # define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ + #define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ -/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register, - * and SPI Interrupt Mask Register (common bit fields) +/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt + * Disable Register, and SPI Interrupt Mask Register (common bit fields) */ #define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */ @@ -177,6 +180,7 @@ #define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */ #define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT) # define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */ + # define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */ # define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */ # define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */ @@ -186,6 +190,7 @@ # define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */ # define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */ # define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */ + #define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */ #define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT) # define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT) @@ -210,16 +215,16 @@ #define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ #define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SPI_H */ diff --git a/arch/arm/src/sama5/hardware/sam_ssc.h b/arch/arm/src/sama5/hardware/sam_ssc.h index 56c1e7929db..ff395226e97 100644 --- a/arch/arm/src/sama5/hardware/sam_ssc.h +++ b/arch/arm/src/sama5/hardware/sam_ssc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_ssc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SSC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SSC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define SAM_SSC_MAXPERCLK 66000000 /* Maximum peripheral clock frequency */ -/* SSC Register Offsets *************************************************************/ +/* SSC Register Offsets *****************************************************/ #define SAM_SSC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_SSC_CMR_OFFSET 0x0004 /* Clock Mode Register */ @@ -58,7 +58,7 @@ #define SAM_SSC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ /* 0x50-0x124 Reserved */ -/* SSC Register Addresses ***********************************************************/ +/* SSC Register Addresses ***************************************************/ #define SAM_SSC0_CR (SAM_SSC0_VBASE+SAM_SSC_CR_OFFSET) #define SAM_SSC0_CMR (SAM_SSC0_VBASE+SAM_SSC_CMR_OFFSET) @@ -98,7 +98,7 @@ #define SAM_SSC1_WPMR (SAM_SSC1_VBASE+SAM_SSC_WPMR_OFFSET) #define SAM_SSC1_WPSR (SAM_SSC1_VBASE+SAM_SSC_WPSR_OFFSET) -/* SSC Register Bit Definitions *****************************************************/ +/* SSC Register Bit Definitions *********************************************/ /* Control Register */ @@ -119,17 +119,20 @@ # define SSC_RCMR_CKS_MCK (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */ # define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */ # define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ + #define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ #define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) # define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None, RK pin is an input */ # define SSC_RCMR_CKO_CONT (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock, RK pin is an output */ # define SSC_RCMR_CKO_TRANSFER (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock during transfers, RK pin is an output */ + #define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ #define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */ #define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT) # define SSC_RCMR_CKG_CONT (0 << SSC_RCMR_CKG_SHIFT) /* None */ # define SSC_RCMR_CKG_ENRFLOW (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Pin is Low */ # define SSC_RCMR_CKG_ENRFHIGH (3 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Pin is High */ + #define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */ #define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT) # define SSC_RCMR_START_CONT (0 << SSC_RCMR_START_SHIFT) /* Continuous */ @@ -141,6 +144,7 @@ # define SSC_RCMR_START_LEVEL (6 << SSC_RCMR_START_SHIFT) /* Detection of any level change on RF signal */ # define SSC_RCMR_START_EDGE (7 << SSC_RCMR_START_SHIFT) /* Detection of any edge on RF signal */ # define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ + #define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Selection */ #define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */ #define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) @@ -170,6 +174,7 @@ # define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* Low during transfer, RF pin is an output */ # define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* High during transfer, RF pin is an output */ # define SSC_RFMR_FSOS_TOGGLING (5 << SSC_RFMR_FSOS_SHIFT) /* Toggling each transfer, RF pin is an output */ + #define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ # define SSC_RFMR_FSEDGE_POS (0) /* Bit 24: 0=Positive Edge Detection */ # define SSC_RFMR_FSEDGE_NEG (1 << 24) /* Bit 24: 1=Negative Edge Detection */ @@ -184,17 +189,20 @@ # define SSC_TCMR_CKS_MCK (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ # define SSC_TCMR_CKS_RK (1 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */ # define SSC_TCMR_CKS_TK (2 << SSC_TCMR_CKS_SHIFT) /* TK pin */ + #define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ #define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) # define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None, TK pin is an input */ # define SSC_TCMR_CKO_CONT (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock, TK pin is an output */ # define SSC_TCMR_CKO_TRANSFER (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock during transfers, TK pin is an output */ + #define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ #define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */ #define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT) # define SSC_TCMR_CKG_CONT (0 << SSC_TCMR_CKG_SHIFT) /* None */ # define SSC_TCMR_CKG_ENTFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Transmit Clock enabled only if TF pin is Low */ -# define SSC_TCMR_CKG_ENTFHIGH (2 << SSC_TCMR_CKG_SHIFT) /*Transmit Clock enabled only if TF pin is High */ +# define SSC_TCMR_CKG_ENTFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Transmit Clock enabled only if TF pin is High */ + #define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */ #define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT) # define SSC_TCMR_START_CONT (0 << SSC_TCMR_START_SHIFT) /* Continuous */ @@ -205,6 +213,7 @@ # define SSC_TCMR_START_RISING (5 << SSC_TCMR_START_SHIFT) /* Detection of a rising edge on TF signal */ # define SSC_TCMR_START_LEVEL (6 << SSC_TCMR_START_SHIFT) /* Detection of any level change on TF signal */ # define SSC_TCMR_START_EDGE (7 << SSC_TCMR_START_SHIFT) /* Detection of any edge on TF signal */ + #define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 15-23: Transmit Start Delay */ #define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT) # define SSC_TCMR_STTDLY(n) ((uint32_t)(n) << SSC_TCMR_STTDLY_SHIFT) @@ -233,6 +242,7 @@ # define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* TF pin Driven Low during data transfer */ # define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* TF pin Driven High during data transfer */ # define SSC_TFMR_FSOS_TOGGLING (5 << SSC_TFMR_FSOS_SHIFT) /* TF pin Toggles at each start of data transfer */ + #define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */ #define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ # define SSC_TFMR_FSEDGE_POS (0) /* Bit 24: 0=Positive Edge Detection */ @@ -242,6 +252,7 @@ # define SSC_TFMR_FSLENEXT(n) ((uint32_t)(n) << SSC_TFMR_FSLENEXT_SHIFT) /* Receive Holding Register (32-bit data value) */ + /* Transmit Holding Register (32-bit data value) */ /* Receive Sync. Holding Register */ @@ -260,7 +271,8 @@ #define SSC_RC1R_MASK (0x0000ffff) /* Bit 0-15: Receive Compare Data 1 */ -/* Status Register , Interrupt Enable Register, Interrupt Disable Register, and +/* Status Register, + * Interrupt Enable Register, Interrupt Disable Register, and * Interrupt Mask Register */ diff --git a/arch/arm/src/sama5/hardware/sam_tc.h b/arch/arm/src/sama5/hardware/sam_tc.h index 894ad8c6d4d..5f8b09c96d6 100644 --- a/arch/arm/src/sama5/hardware/sam_tc.h +++ b/arch/arm/src/sama5/hardware/sam_tc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_tc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define SAM_TC_NCHANNELS 3 /* Number of channels per TC peripheral */ #define SAM_TC_MAXPERCLK 66000000 /* Maximum peripheral input clock frequency */ -/* TC Register Offsets **************************************************************/ +/* TC Register Offsets ******************************************************/ #define SAM_TC_CHAN_OFFSET(n) ((n) << 6) /* Channel n offset */ #define SAM_TC_CCR_OFFSET 0x0000 /* Channel Control Register */ @@ -136,7 +136,7 @@ #define SAM_TC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ -/* TC Register Addresses ************************************************************/ +/* TC Register Addresses ****************************************************/ #define SAM_TC012_CHAN_BASE(n) (SAM_TC012_VBASE+SAM_TC_CHAN_OFFSET(n)) @@ -387,7 +387,7 @@ #define SAM_TC678_WPMR (SAM_TC678_VBASE+SAM_TC_WPMR_OFFSET) -/* TC Register Bit Definitions ******************************************************/ +/* TC Register Bit Definitions **********************************************/ /* Channel Control Register */ @@ -408,6 +408,7 @@ # define TC_CMR_TCCLKS_XC0 (5 << TC_CMR_TCCLKS_SHIFT) /* XC0 Clock selected */ # define TC_CMR_TCCLKS_XC1 (6 << TC_CMR_TCCLKS_SHIFT) /* XC1 Clock selected */ # define TC_CMR_TCCLKS_XC2 (7 << TC_CMR_TCCLKS_SHIFT) /* XC2 Clock selected */ + #define TC_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert */ #define TC_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection */ #define TC_CMR_BURST_MASK (3 << TC_CMR_BURST_SHIFT) @@ -426,6 +427,7 @@ # define TC_CMR_ETRGEDG_RISING (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */ # define TC_CMR_ETRGEDG_FALLING (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */ # define TC_CMR_ETRGEDG_BOTH (3 << TC_CMR_ETRGEDG_SHIFT) /* EDGE Each edge */ + #define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */ #define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */ #define TC_CMR_CAPTURE (0) /* Bit 15: 0=Capture Mode */ @@ -435,6 +437,7 @@ # define TC_CMR_LDRA_RISING (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ # define TC_CMR_LDRA_FALLING (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ # define TC_CMR_LDRA_BOTH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */ + #define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Edge Selection */ #define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT) # define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */ @@ -462,12 +465,14 @@ # define TC_CMR_EEVTEDG_RISING (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */ # define TC_CMR_EEVTEDG_FALLING (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */ # define TC_CMR_EEVTEDG_BOTH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */ + #define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection */ #define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT) # define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB(1) input */ # define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 output */ # define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 output */ # define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 output */ + #define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable */ #define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection */ #define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT) @@ -475,6 +480,7 @@ # define TC_CMR_WAVSEL_UPDOWN (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o trigger on RC Compare */ # define TC_CMR_WAVSEL_UPRC (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode w/ trigger on RC Compare */ # define TC_CMR_WAVSEL_UPDOWNRC (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN w/ with trigger on RC Compare */ + #define TC_CMR_WAVE (1 << 15) /* Bit 15: 1=Waveform Mode */ #define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA */ #define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT) @@ -482,42 +488,49 @@ # define TC_CMR_ACPA_SET (1 << TC_CMR_ACPA_SHIFT) /* Set */ # define TC_CMR_ACPA_CLEAR (2 << TC_CMR_ACPA_SHIFT) /* Clear */ # define TC_CMR_ACPA_TOGGLE (3 << TC_CMR_ACPA_SHIFT) /* Toggle */ + #define TC_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA */ #define TC_CMR_ACPC_MASK (3 << TC_CMR_ACPC_SHIFT) # define TC_CMR_ACPC_NONE (0 << TC_CMR_ACPC_SHIFT) /* None */ # define TC_CMR_ACPC_SET (1 << TC_CMR_ACPC_SHIFT) /* Set */ # define TC_CMR_ACPC_CLEAR (2 << TC_CMR_ACPC_SHIFT) /* Clear */ # define TC_CMR_ACPC_TOGGLE (3 << TC_CMR_ACPC_SHIFT) /* Toggle */ + #define TC_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA */ #define TC_CMR_AEEVT_MASK (3 << TC_CMR_AEEVT_SHIFT) # define TC_CMR_AEEVT_NONE (0 << TC_CMR_AEEVT_SHIFT) /* None */ # define TC_CMR_AEEVT_SET (1 << TC_CMR_AEEVT_SHIFT) /* Set */ # define TC_CMR_AEEVT_CLEAR (2 << TC_CMR_AEEVT_SHIFT) /* Clear */ # define TC_CMR_AEEVT_TOGGLE (3 << TC_CMR_AEEVT_SHIFT) /* Toggle */ + #define TC_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA */ #define TC_CMR_ASWTRG_MASK (3 << TC_CMR_ASWTRG_SHIFT) # define TC_CMR_ASWTRG_NONE (0 << TC_CMR_ASWTRG_SHIFT) /* None */ # define TC_CMR_ASWTRG_SET (1 << TC_CMR_ASWTRG_SHIFT) /* Set */ # define TC_CMR_ASWTRG_CLEAR (2 << TC_CMR_ASWTRG_SHIFT) /* Clear */ # define TC_CMR_ASWTRG_TOGGLE (3 << TC_CMR_ASWTRG_SHIFT) /* Toggle */ + #define TC_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB */ #define TC_CMR_BCPB_MASK (3 << TC_CMR_BCPB_SHIFT) # define TC_CMR_BCPB_NONE (0 << TC_CMR_BCPB_SHIFT) /* None */ # define TC_CMR_BCPB_SET (1 << TC_CMR_BCPB_SHIFT) /* Set */ # define TC_CMR_BCPB_CLEAR (2 << TC_CMR_BCPB_SHIFT) /* Clear */ # define TC_CMR_BCPB_TOGGLE (3 << TC_CMR_BCPB_SHIFT) /* Toggle */ + #define TC_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB */ #define TC_CMR_BCPC_MASK (3 << TC_CMR_BCPC_SHIFT) # define TC_CMR_BCPC_NONE (0 << TC_CMR_BCPC_SHIFT) /* None */ # define TC_CMR_BCPC_SET (1 << TC_CMR_BCPC_SHIFT) /* Set */ # define TC_CMR_BCPC_CLEAR (2 << TC_CMR_BCPC_SHIFT) /* Clear */ # define TC_CMR_BCPC_TOGGLE (3 << TC_CMR_BCPC_SHIFT) /* Toggle */ + #define TC_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB */ #define TC_CMR_BEEVT_MASK (3 << TC_CMR_BEEVT_SHIFT) # define TC_CMR_BEEVT_NONE (0 << TC_CMR_BEEVT_SHIFT) /* None */ # define TC_CMR_BEEVT_SET (1 << TC_CMR_BEEVT_SHIFT) /* Set */ # define TC_CMR_BEEVT_CLEAR (2 << TC_CMR_BEEVT_SHIFT) /* Clear */ # define TC_CMR_BEEVT_TOGGLE (3 << TC_CMR_BEEVT_SHIFT) /* Toggle */ + #define TC_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB */ #define TC_CMR_BSWTRG_MASK (3 << TC_CMR_BSWTRG_SHIFT) # define TC_CMR_BSWTRG_NONE (0 << TC_CMR_BSWTRG_SHIFT) /* None */ @@ -531,13 +544,17 @@ #define TC_SMMR_DOWN (1 << 1) /* Bit 1: DOWN Count */ /* Register AB (32-bit capture value) */ + /* Counter Value (32-bit counter value) */ + /* Register A (32-bit value) */ + /* Register B (32-bit value) */ + /* Register C (32-bit value) */ -/* Status Register, Interrupt Enable Register, Interrupt Disable Register, and - * Interrupt Mask Register +/* Status Register, Interrupt Enable Register, + * Interrupt Disable Register, and Interrupt Mask Register */ #define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow Status */ @@ -561,10 +578,12 @@ # define TC_EMR_TRIGSRCA_MASK (3 << TC_EMR_TRIGSRCA_SHIFT) # define TC_EMR_TRIGSRCA_TIOA (0 << TC_EMR_TRIGSRCA_SHIFT) /* Trigger/capture input A driven by TIOAx */ # define TC_EMR_TRIGSRCA_PWM (1 << TC_EMR_TRIGSRCA_SHIFT) /* Trigger/capture input A driven by PWMx */ + # define TC_EMR_TRIGSRCB_SHIFT (4) /* Bits 4-5: Trigger source for input B */ # define TC_EMR_TRIGSRCB_MASK (3 << TC_EMR_TRIGSRCB_SHIFT) # define TC_EMR_TRIGSRCB_TIOB (0 << TC_EMR_TRIGSRCB_SHIFT) /* Trigger/capture input B driven by TIOBx */ # define TC_EMR_TRIGSRCB_PWM (1 << TC_EMR_TRIGSRCB_SHIFT) /* Trigger/capture input B driven PWMx */ + # define TC_EMR_NODIVCLK (1 << 8) /* Bit 8: No divided clock */ #endif @@ -579,16 +598,19 @@ # define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT) /* TCLK0 Signal to XC0 */ # define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT) /* TIOA1 Signal to XC0 */ # define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT) /* TIOA2 Signal to XC0 */ + #define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */ #define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_SHIFT) # define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT) /* TCLK1 Signal to XC1 */ # define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT) /* TIOA0 Signal to XC1 */ # define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) /* TIOA2 Signal to XC1 */ + #define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */ #define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) # define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) /* TCLK2 Signal to XC2 */ # define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) /* TIOA0 Signal to XC2 */ # define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) /* TIOA1 Signal to XC2 */ + #define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder ENabled */ #define TC_BMR_POSEN (1 << 9) /* Bit 9: POSition ENabled */ #define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: SPEED ENabled */ @@ -604,7 +626,8 @@ #define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT) # define TC_BMR_MAXFILT(n) ((uint32_t)(n) << TC_BMR_MAXFILT_SHIFT) -/* QDEC Interrupt Enable Register, QDEC Interrupt Disable Register, QDEC Interrupt Mask Register, and QDEC Interrupt Status Register. +/* QDEC Interrupt Enable Register, QDEC Interrupt Disable Register, + * QDEC Interrupt Mask Register, and QDEC Interrupt Status Register. */ #define TC_QINT_IDX (1 << 0) /* Bit 0: Index */ diff --git a/arch/arm/src/sama5/hardware/sam_trng.h b/arch/arm/src/sama5/hardware/sam_trng.h index 68d8a20b7b0..8806bcf120e 100644 --- a/arch/arm/src/sama5/hardware/sam_trng.h +++ b/arch/arm/src/sama5/hardware/sam_trng.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_trng.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TRNG_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TRNG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* TRNG Register Offsets ************************************************************/ + ****************************************************************************/ + +/* TRNG Register Offsets ****************************************************/ #define SAM_TRNG_CR_OFFSET 0x0000 /* Control Register */ #define SAM_TRNG_IER_OFFSET 0x0010 /* Interrupt Enable Register */ @@ -40,7 +41,7 @@ #define SAM_TRNG_ISR_OFFSET 0x001c /* Interrupt Status Register */ #define SAM_TRNG_ODATA_OFFSET 0x0050 /* Output Data Register */ -/* TRNG Register Addresses **********************************************************/ +/* TRNG Register Addresses **************************************************/ #define SAM_TRNG_CR (SAM_TRNG_VBASE+SAM_TRNG_CR_OFFSET) #define SAM_TRNG_IER (SAM_TRNG_VBASE+SAM_TRNG_IER_OFFSET) @@ -49,7 +50,7 @@ #define SAM_TRNG_ISR (SAM_TRNG_VBASE+SAM_TRNG_ISR_OFFSET) #define SAM_TRNG_ODATA (SAM_TRNG_VBASE+SAM_TRNG_ODATA_OFFSET) -/* TRNG Register Bit Definitions ****************************************************/ +/* TRNG Register Bit Definitions ********************************************/ /* Control Register */ @@ -59,7 +60,8 @@ #define TRNG_CR_KEY_MASK (0xffffff << TRNG_CR_KEY_SHIFT) # define TRNG_CR_KEY (0x524e47 << TRNG_CR_KEY_SHIFT) /* RNG in ASCII */ -/* Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, +/* Interrupt Enable Register, + * Interrupt Disable Register, Interrupt Mask Register, * and Interrupt Status Register */ diff --git a/arch/arm/src/sama5/hardware/sam_twi.h b/arch/arm/src/sama5/hardware/sam_twi.h index 8f55e935b7d..d3282acf4a4 100644 --- a/arch/arm/src/sama5/hardware/sam_twi.h +++ b/arch/arm/src/sama5/hardware/sam_twi.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_twi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TWI_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TWI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* TWI register offsets *****************************************************************/ +/* TWI register offsets *****************************************************/ #define SAM_TWI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_TWI_MMR_OFFSET 0x0004 /* Master Mode Register */ @@ -53,7 +53,7 @@ #define SAM_TWI_WPSR_OFFSET 0x00e8 /* Protection Status Register */ /* 0x00ec-0x00fc: Reserved */ -/* TWI register addresses ***************************************************************/ +/* TWI register addresses ***************************************************/ #define SAM_TWI0_CR (SAM_TWI0_VBASE+SAM_TWI_CR_OFFSET) #define SAM_TWI0_MMR (SAM_TWI0_VBASE+SAM_TWI_MMR_OFFSET) @@ -113,7 +113,7 @@ # define SAM_TWI3_WPSR (SAM_TWI3_VBASE+SAM_TWI_WPSR_OFFSET) #endif -/* TWI register bit definitions *********************************************************/ +/* TWI register bit definitions *********************************************/ /* TWI Control Register */ @@ -134,6 +134,7 @@ # define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */ # define TWI_MMR_IADRSZ_2BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ # define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ + #define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ #define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */ #define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT) @@ -211,16 +212,16 @@ #define TWI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-31: Write Protection Violation Source */ #define TWI_WPSR_WPVSRC_MASK (0x00ffffff << TWI_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TWI_H */ diff --git a/arch/arm/src/sama5/hardware/sam_uart.h b/arch/arm/src/sama5/hardware/sam_uart.h index 138cbb187b1..9e0722bb515 100644 --- a/arch/arm/src/sama5/hardware/sam_uart.h +++ b/arch/arm/src/sama5/hardware/sam_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,30 +16,32 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ -/* Universal Asynchronous Receiver Transmitter (UART) for the SAMA5D2, SAMA5D3, and SAMA5D4 and - * Universal Synchronous Asynchronous Receiver Transmitter (USART) definitions for the SAMA5D3 - * and SAMAD4 +/* Universal Asynchronous Receiver Transmitter (UART) + * for the SAMA5D2, SAMA5D3, and SAMA5D4 and + * Universal Synchronous Asynchronous Receiver Transmitter (USART) + * definitions for the SAMA5D3 and SAMAD4 */ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UART_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UART_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ + +/* UART register offsets ****************************************************/ -/* UART register offsets ************************************************************************/ /* Key: * (1) Common to both UART and SAMA5D3/4 USART * (2) SAMA5D3/4 USART only @@ -79,7 +81,7 @@ #endif /* 0x00ec-0xfc: Reserved (USART) */ -/* UART register addresses **********************************************************************/ +/* UART register addresses **************************************************/ #define SAM_UART0_CR (SAM_UART0_VBASE+SAM_UART_CR_OFFSET) #define SAM_UART0_MR (SAM_UART0_VBASE+SAM_UART_MR_OFFSET) @@ -264,7 +266,7 @@ # endif #endif -/* UART register bit definitions ****************************************************************/ +/* UART register bit definitions ********************************************/ /* UART Control Register */ @@ -316,17 +318,20 @@ # define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */ # define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master (SPI mode only) */ # define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave (SPI mode only) */ + # define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (3) */ # define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) # define UART_MR_USCLKS_MCK (0 << UART_MR_USCLKS_SHIFT) /* MCK */ # define UART_MR_USCLKS_MCKDIV (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ # define UART_MR_USCLKS_SCK (3 << UART_MR_USCLKS_SHIFT) /* SCK */ + # define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (3) */ # define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) # define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */ # define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */ # define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */ # define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ + # define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select (4) */ # define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (5) */ #endif @@ -382,8 +387,10 @@ # define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (4) */ #endif -/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask - * Register, and UART Status Register common bit field definitions +/* UART Interrupt Enable Register, + * UART Interrupt Disable Register, + * UART Interrupt Mask Register, and + * UART Status Register common bit field definitions * * NOTES: * (1) Common to UART and USART (all modes) @@ -517,6 +524,7 @@ # define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */ # define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */ + # define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ # define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ # define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT) @@ -526,6 +534,7 @@ # define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */ # define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ + # define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ # define UART_MAN_ONE (1 << 29) /* Bit 29: Must Be Set to 1 */ # define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ @@ -540,6 +549,7 @@ # define UART_WPMR_WPKEY (0x00554152 << UART_WPMR_WPKEY_SHIFT) /* "UAR" */ #if defined(ATSAMA5D3) ||defined(ATSAMA5D4) + /* USART Write Protect Status Register (USART only) */ # define UART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ @@ -547,16 +557,16 @@ # define UART_WPSR_WPVSRC_MASK (0xffff << UART_WPSR_WPVSRC_SHIFT) #endif -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UART_H */ diff --git a/arch/arm/src/sama5/hardware/sam_udphs.h b/arch/arm/src/sama5/hardware/sam_udphs.h index 761c1d6bd05..c10b1875e60 100644 --- a/arch/arm/src/sama5/hardware/sam_udphs.h +++ b/arch/arm/src/sama5/hardware/sam_udphs.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_udphs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * SAMA5D3 Series Data Sheet @@ -25,19 +25,21 @@ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UDPHS_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UDPHS_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* General Definitions **********************************************************************/ + ****************************************************************************/ + +/* General Definitions ******************************************************/ + /* Number of endpoints and DMA channels */ #define SAM_UDPHS_NENDPOINTS 16 /* EP0-15 */ @@ -52,7 +54,7 @@ #define SAM_UDPHS_DMA(ep) \ (((unsigned)(ep) < 1) ? false : (((unsigned)(ep) < 8) ? true : false)) -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ /* Global Registers */ @@ -66,6 +68,7 @@ /* 0x0020-0x00cc Reserved */ #define SAM_UDPHS_TST_OFFSET 0x00e0 /* UDPHS Test Register */ /* 0x00e4-0x00e8 Reserved */ + /* Endpoint Offsets */ #define SAM_UDPHS_EP_OFFSET(ep) (0x0100+((unsigned int)(ep)<<5)) @@ -115,7 +118,7 @@ #define SAM_UDPHS_DMACONTROL_OFFSET 0x0008 /* UDPHS DMA Channel Control Register */ #define SAM_UDPHS_DMASTATUS_OFFSET 0x000c /* UDPHS DMA Channel Status Register */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ /* Global Registers */ @@ -175,7 +178,7 @@ #define SAM_UDPHS_DMACONTROL(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMACONTROL_OFFSET) #define SAM_UDPHS_DMASTATUS(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMASTATUS_OFFSET) -/* Register bit-field definitions ***********************************************************/ +/* Register bit-field definitions *******************************************/ /* Global Registers */ @@ -199,12 +202,13 @@ #define UDPHS_FNUM_FNUMERR (1 << 31) /* Bit 31: Frame Number CRC Error */ /* Common interrupt bits */ + /* UDPHS Interrupt Status Register (only) */ #define UDPHS_INTSTA_SPEED (1 << 0) /* Bit 0: Speed Status */ -/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear - * Interrupt Register +/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, + * and UDPHS Clear Interrupt Register */ #define UDPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt */ @@ -220,6 +224,7 @@ #define UDPHS_INT_EPT_SHIFT (8) /* Bits 8-23: Endpoint interrupts */ #define UDPHS_INT_EPT_MASK (0xffff << UDPHS_INT_EPT_SHIFT) #define UDPHS_INT_EPT(ep) (1 << +((ep)+8)) /* Endpoint ep Interrupt */ + # define UDPHS_INT_EPT0 (1 << 8) /* Bit 8: Endpoint 0 Interrupt */ # define UDPHS_INT_EPT1 (1 << 9) /* Bit 9: Endpoint 1 Interrupt */ # define UDPHS_INT_EPT2 (1 << 10) /* Bit 10: Endpoint 2 Interrupt */ @@ -239,6 +244,7 @@ #define UDPHS_INT_DMA_SHIFT (25) /* Bits 25-31: Endpoint interrupts */ #define UDPHS_INT_DMA_MASK (0x7f << UDPHS_INT_DMA_SHIFT) #define UDPHS_INT_DMA(ch) (1 << ((ch)+24)) /* DMA Channel ch Interrupt */ + # define UDPHS_INT_DMA1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt */ # define UDPHS_INT_DMA2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt */ # define UDPHS_INT_DMA3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt */ @@ -250,6 +256,7 @@ /* UDPHS Endpoints Reset Register */ #define UDPHS_EPTRST(ep) (1 << (ep)) /* Endpoint ep Reset */ + # define UDPHS_EPT0RST (1 << 0) /* Bit 0: Endpoint 0 Reset */ # define UDPHS_EPT1RST (1 << 1) /* Bit 1: Endpoint 1 Reset */ # define UDPHS_EPT2RST (1 << 2) /* Bit 2: Endpoint 2 Reset */ @@ -274,12 +281,14 @@ # define UDPHS_TST_SPEED_NORMAL (0 << UDPHS_TST_SPEED_SHIFT) /* Normal Mode */ # define UDPHS_TST_SPEED_HIGH (2 << UDPHS_TST_SPEED_SHIFT) /* Force High Speed */ # define UDPHS_TST_SPEED_FULL (3 << UDPHS_TST_SPEED_SHIFT) /* Force Full Speed */ + #define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */ #define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */ #define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mode */ #define UDPHS_TST_OPMODE2 (1 << 5) /* Bit 4: OpMode2 */ /* Endpoint registers */ + /* UDPHS Endpoint Configuration Register */ #define UDPHS_EPTCFG_SIZE_SHIFT (0) /* Bits 0-2: Endpoint Size */ @@ -292,6 +301,7 @@ # define UDPHS_EPTCFG_SIZE_256 (5 << UDPHS_EPTCFG_SIZE_SHIFT) /* 256 bytes */ # define UDPHS_EPTCFG_SIZE_512 (6 << UDPHS_EPTCFG_SIZE_SHIFT) /* 512 bytes */ # define UDPHS_EPTCFG_SIZE_1024 (7 << UDPHS_EPTCFG_SIZE_SHIFT) /* 1024 bytes */ + #define UDPHS_EPTCFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */ #define UDPHS_EPTCFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */ #define UDPHS_EPTCFG_TYPE_MASK (3 << UDPHS_EPTCFG_TYPE_SHIFT) @@ -299,117 +309,143 @@ # define UDPHS_EPTCFG_TYPE_ISO (1 << UDPHS_EPTCFG_TYPE_SHIFT) /* Isochronous endpoint */ # define UDPHS_EPTCFG_TYPE_BULK (2 << UDPHS_EPTCFG_TYPE_SHIFT) /* Bulk endpoint */ # define UDPHS_EPTCFG_TYPE_INT (3 << UDPHS_EPTCFG_TYPE_SHIFT) /* Interrupt endpoint */ + #define UDPHS_EPTCFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */ #define UDPHS_EPTCFG_BKNUMBER_MASK (3 << UDPHS_EPTCFG_BKNUMBER_SHIFT) #define UDPHS_EPTCFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Transaction per uframe */ #define UDPHS_EPTCFG_NBTRANS_MASK (3 << UDPHS_EPTCFG_NBTRANS_SHIFT) #define UDPHS_EPTCFG_MAPD (1 << 31) /* Bit 31: Endpoint Mapped */ -/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register, and UDPHS +/* UDPHS Endpoint Control Enable Register, + * UDPHS Endpoint Control Disable Register, and UDPHS * Endpoint Control Register */ - /* Common bits definitions */ + + /* Common bits definitions */ + #define UDPHS_EPTCTL_EPTENABL (1 << 0) /* Bit 0: Endpoint Enable */ #define UDPHS_EPTCTL_AUTOVALID (1 << 1) /* Bit 1: Packet Auto-Valid Enable */ #define UDPHS_EPTCTL_INTDISDMA (1 << 3) /* Bit 3: Interrupts Disable DMA */ - /*--- Control/Bulk/Interrupt --- */ + + /* Control/Bulk/Interrupt */ + #define UDPHS_EPTCTL_NYETDIS (1 << 4) /* Bit 4: NYET Disable (High Speed Bulk OUT) */ - /* --- Isochronous Endpoints Only --- */ + + /* Isochronous Endpoints Only */ + #define UDPHS_EPTCTL_DATAXRX (1 << 8) /* Bit 8: Interrupt Enable (Isochronous OUT) */ #define UDPHS_EPTCTL_MDATARX (1 << 9) /* Bit 9: MDATA Interrupt Enable (Isochronous OUT) */ - /* --- Common Bit Definitions --- */ + + /* Common Bit Definitions */ + #define UDPHS_EPTCTL_ERROVFLW (1 << 8) /* Bit 8: Overflow Error Interrupt Enable */ #define UDPHS_EPTCTL_RXRDYTXKL (1 << 9) /* Bit 9: Received OUT Data Interrupt Enable */ #define UDPHS_EPTCTL_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Interrupt Enable */ - /*--- Control/Bulk/Interrupt --- */ + + /* Control/Bulk/Interrupt */ + #define UDPHS_EPTCTL_TXRDY (1 << 11) /* Bit 11: TX Packet Ready Interrupt Enable */ #define UDPHS_EPTCTL_RXSETUP (1 << 12) /* Bit 12: Received SETUP */ #define UDPHS_EPTCTL_STALLSNT (1 << 13) /* Bit 13: Stall Sent Interrupt Enable */ #define UDPHS_EPTCTL_NAKIN (1 << 14) /* Bit 14: NAKIN Interrupt Enable */ #define UDPHS_EPTCTL_NAKOUT (1 << 15) /* Bit 15: NAKOUT Interrupt Enable */ - /* --- Isochronous Endpoints Only --- */ + + /* Isochronous Endpoints Only */ + #define UDPHS_EPTCTL_TXRDYTRER (1 << 11) /* Bit 11: TX Packet Ready/Transaction Error Interrupt Enable */ #define UDPHS_EPTCTL_ERRFLISO (1 << 12) /* Bit 12: Error Flow Interrupt Enable */ #define UDPHS_EPTCTL_ERRCRCNTR (1 << 13) /* Bit 13: ISO CRC Error/Number of Transaction Error Interrupt Enable */ #define UDPHS_EPTCTL_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Interrupt Enable */ - /* --- Common Bit Definitions --- */ + + /* Common Bit Definitions */ + #define UDPHS_EPTCTL_BUSYBANK (1 << 18) /* Bit 28: Busy Bank Interrupt Enable */ #define UDPHS_EPTCTL_SHRTPCKT (1 << 31) /* Bit 31: Short Packet Send/Short Packet Interrupt Enable */ /* UDPHS Endpoint Set Status Register */ - /*--- Control/Bulk/Interrupt --- */ + + /* Control/Bulk/Interrupt */ #define UDPHS_EPTSETSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Set */ - /* --- Common Bit Definitions --- */ + /* Common Bit Definitions */ #define UDPHS_EPTSETSTA_RXRDYTXKL (1 << 9) /* Bit 9: KILL Bank Set (IN Endpoint) */ - /*--- Control/Bulk/Interrupt --- */ + /* Control/Bulk/Interrupt */ #define UDPHS_EPTSETSTA_TXRDY (1 << 11) /* Bit 11: TX Packet Ready Set */ - /* --- Isochronous Endpoints Only --- */ + /* Isochronous Endpoints Only */ #define UDPHS_EPTSETSTA_TXRDYTRER (1 << 11) /* Bit 11: TX Packet Ready Set */ /* UDPHS Endpoint Clear Status Register */ - /*--- Control/Bulk/Interrupt --- */ + + /* Control/Bulk/Interrupt */ #define UDPHS_EPTCLRSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Clear */ - /* --- Common Bit Definitions --- */ + /* Common Bit Definitions */ #define UDPHS_EPTCLRSTA_TOGGLESQ (1 << 6) /* Bit 6: Data Toggle Clear */ #define UDPHS_EPTCLRSTA_RXRDYTXKL (1 << 9) /* Bit 9: Received OUT Data Clear */ #define UDPHS_EPTCLRSTA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Clear */ - /*--- Control/Bulk/Interrupt --- */ + /* Control/Bulk/Interrupt */ #define UDPHS_EPTCLRSTA_RXSETUP (1 << 12) /* Bit 12: Received SETUP Clear */ #define UDPHS_EPTCLRSTA_STALLSNT (1 << 13) /* Bit 13: Stall Sent Clear */ #define UDPHS_EPTCLRSTA_NAKIN (1 << 14) /* Bit 14: NAKIN Clear */ #define UDPHS_EPTCLRSTA_NAKOUT (1 << 15) /* Bit 15: NAKOUT Clear */ - /* --- Isochronous Endpoints Only --- */ + /* Isochronous Endpoints Only */ #define UDPHS_EPTCLRSTA_ERRFLISO (1 << 12) /* Bit 12: Error Flow Clear */ #define UDPHS_EPTCLRSTA_ERRCRCNTR (1 << 13) /* Bit 13: Number of Transaction Error Clear */ #define UDPHS_EPTCLRSTA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Clear */ /* UDPHS Endpoint Status Register */ - /*--- Control/Bulk/Interrupt --- */ + + /* Control/Bulk/Interrupt */ #define UDPHS_EPTSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request */ - /* --- Common Bit Definitions --- */ + /* Common Bit Definitions */ #define UDPHS_EPTSTA_TOGGLESQ_SHIFT (6) /* Bits 6-7: Toggle Sequencing */ #define UDPHS_EPTSTA_TOGGLESQ_MASK (3 << UDPHS_EPTSTA_TOGGLESQ_SHIFT) # define UDPHS_EPTSTA_TOGGLESQ_DATA0 (0 << UDPHS_EPTSTA_TOGGLESQ_SHIFT) /* DATA0 */ # define UDPHS_EPTSTA_TOGGLESQ_DATA1 (1 << UDPHS_EPTSTA_TOGGLESQ_SHIFT) /* DATA1 */ # define UDPHS_EPTSTA_TOGGLESQ_DATA2 (2 << UDPHS_EPTSTA_TOGGLESQ_SHIFT) /* Isochronous Endpoint */ # define UDPHS_EPTSTA_TOGGLESQ_MDATA (3 << UDPHS_EPTSTA_TOGGLESQ_SHIFT) /* Isochronous Endpoint */ + #define UDPHS_EPTSTA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */ #define UDPHS_EPTSTA_RXRDYTXKL (1 << 9) /* Bit 9: Received OUT Data/KILL Bank */ #define UDPHS_EPTSTA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */ - /*--- Control/Bulk/Interrupt --- */ + /* Control/Bulk/Interrupt */ #define UDPHS_EPTSTA_TXRDY (1 << 11) /* Bit 11: TX Packet Ready */ #define UDPHS_EPTSTA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */ #define UDPHS_EPTSTA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */ #define UDPHS_EPTSTA_NAKIN (1 << 14) /* Bit 14: NAK IN */ #define UDPHS_EPTSTA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */ - /* --- Isochronous Endpoints Only --- */ + /* Isochronous Endpoints Only */ #define UDPHS_EPTSTA_TXRDYTRER (1 << 11) /* Bit 11: TX Packet Ready/Transaction Error */ #define UDPHS_EPTSTA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */ #define UDPHS_EPTSTA_ERRCRCNTR (1 << 13) /* Bit 13: CRC ISO Error/Number of Transaction Error */ #define UDPHS_EPTSTA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */ - /*--- Control Only --- */ + /* Control Only */ #define UDPHS_EPTSTA_CTLDIR_SHIFT (16) /* Bits 16-17: Control Direction */ #define UDPHS_EPTSTA_CTLDIR_MASK (3 << UDPHS_EPTSTA_CTLDIR_SHIFT) # define UDPHS_EPTSTA_CTLDIR_WRITE (0 << UDPHS_EPTSTA_CTLDIR_SHIFT) /* Control Write requested */ # define UDPHS_EPTSTA_CTLDIR_READ (1 << UDPHS_EPTSTA_CTLDIR_SHIFT) /* Control Read requested */ - /* --- Bulk/Interrupt/Isochronous --- */ + + /* Bulk/Interrupt/Isochronous */ + #define UDPHS_EPTSTA_CURBK_SHIFT (16) /* Bits 16-17: Current Bank */ #define UDPHS_EPTSTA_CURBK_MASK (3 << UDPHS_EPTSTA_CURBK_SHIFT) # define UDPHS_EPTSTA_CURBK_BANK0 (0 << UDPHS_EPTSTA_CURBK_SHIFT) /* Bank 0 (or single bank) */ # define UDPHS_EPTSTA_CURBK_BANK1 (1 << UDPHS_EPTSTA_CURBK_SHIFT) /* Bank 1 */ # define UDPHS_EPTSTA_CURBK_BANK2 (2 << UDPHS_EPTSTA_CURBK_SHIFT) /* Bank 2 */ - /* --- Common Bit Definitions --- */ + + /* Common Bit Definitions */ #define UDPHS_EPTSTA_BUSYBANK_SHIFT (18) /* Bits 18-19: Busy Bank Number */ #define UDPHS_EPTSTA_BUSYBANK_MASK (3 << UDPHS_EPTSTA_BUSYBANK_SHIFT) # define UDPHS_EPTSTA_BUSYBANK_1 (0 << UDPHS_EPTSTA_BUSYBANK_SHIFT) /* 1 busy bank */ # define UDPHS_EPTSTA_BUSYBANK_2 (1 << UDPHS_EPTSTA_BUSYBANK_SHIFT) /* 2 busy banks */ # define UDPHS_EPTSTA_BUSYBANK_3 (2 << UDPHS_EPTSTA_BUSYBANK_SHIFT) /* 3 busy banks */ -#define UDPHS_EPTSTA_BYTECNT_SHIFT (20) /* Bits 20-30: UDPHS Byte Count */ + +#define UDPHS_EPTSTA_BYTECNT_SHIFT (20) /* Bits 20-30: UDPHS Byte Count */ #define UDPHS_EPTSTA_BYTECNT_MASK (0x7ff << UDPHS_EPTSTA_BYTECNT_SHIFT) #define UDPHS_EPTSTA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet */ /* DMA Channel Registers */ + /* UDPHS DMA Next Descriptor Address Register (32-bit address) */ + /* UDPHS DMA Channel Address Register (32-bit address) */ /* UDPHS DMA Channel Control Register */ @@ -436,16 +472,17 @@ #define UDPHS_DMASTATUS_BUFCNT_SHIFT (16) /* Bits 16-31: Buffer Byte Counut */ #define UDPHS_DMASTATUS_BUFCNT_MASK (0xffff << UDPHS_DMASTATUS_BUFCNT_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/* This structure defines the UDPHS DMA Transfer Descriptor. Instances of DMA transfer - * descriptors must by aligned to 16-byte address boundaries. +/* This structure defines the UDPHS DMA Transfer Descriptor. + * Instances of DMA transfer descriptors must by aligned to 16-byte + * address boundaries. * - * Each value contains the next value of each of three UDPHS DMA registers. The first - * register value (UDPHS_DMANXTDSCx) is a link that can be used to chain sequences of - * DMA transfers. + * Each value contains the next value of each of three UDPHS DMA registers. + * The first register value (UDPHS_DMANXTDSCx) is a link that can be used + * to chain sequences of DMA transfers. */ struct udphs_dtd_s @@ -456,12 +493,12 @@ struct udphs_dtd_s }; #define SIZEOF_USPHS_DTD_S 12 -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UDPHS_H */ diff --git a/arch/arm/src/sama5/hardware/sam_wdt.h b/arch/arm/src/sama5/hardware/sam_wdt.h index c75f796ac4a..f7c2c0dd857 100644 --- a/arch/arm/src/sama5/hardware/sam_wdt.h +++ b/arch/arm/src/sama5/hardware/sam_wdt.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,38 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_WDT_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_WDT_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* WDT register offsets ****************************************************************/ +/* WDT register offsets *****************************************************/ #define SAM_WDT_CR_OFFSET 0x00 /* Control Register */ #define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */ #define SAM_WDT_SR_OFFSET 0x08 /* Status Register */ -/* WDT register addresses **************************************************************/ +/* WDT register addresses ***************************************************/ #define SAM_WDT_CR (SAM_WDT_VBASE+SAM_WDT_CR_OFFSET) #define SAM_WDT_MR (SAM_WDT_VBASE+SAM_WDT_MR_OFFSET) #define SAM_WDT_SR (SAM_WDT_VBASE+SAM_WDT_SR_OFFSET) -/* WDT register bit definitions ********************************************************/ +/* WDT register bit definitions *********************************************/ + /* Watchdog Timer Control Register */ #define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Restart */ @@ -83,16 +84,16 @@ #define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ #define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_WDT_H */ diff --git a/arch/arm/src/sama5/hardware/sam_xdmac.h b/arch/arm/src/sama5/hardware/sam_xdmac.h index bf47444429b..b882d422d58 100644 --- a/arch/arm/src/sama5/hardware/sam_xdmac.h +++ b/arch/arm/src/sama5/hardware/sam_xdmac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sam_xdmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_XDMAC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_XDMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ -/* XDMAC Register Offsets ***********************************************************/ + ****************************************************************************/ + +/* XDMAC Register Offsets ***************************************************/ #define SAM_XDMAC_GTYPE_OFFSET 0x0000 /* Global Type Register */ #define SAM_XDMAC_GCFG_OFFSET 0x0004 /* Global Configuration Register */ @@ -72,7 +73,9 @@ # define SAM_XDMAC_CH14_OFFSET 0x03d0 # define SAM_XDMAC_CH15_OFFSET 0x0410 -/* Offsets to channel registers relative to the base of the DMA channel registers */ +/* Offsets to channel registers relative to the base of the DMA channel + * registers + */ #define SAM_XDMACH_CIE_OFFSET 0x0000 /* Channel Interrupt Enable Register */ #define SAM_XDMACH_CID_OFFSET 0x0004 /* Channel Interrupt Disable Register */ @@ -91,7 +94,7 @@ /* 0x0038-0x003c Reserved */ /* 0x0fec–0x0ffc Reserved */ -/* XDMAC Register Addresses *********************************************************/ +/* XDMAC Register Addresses *************************************************/ #define SAM_XDMAC0_GTYPE (SAM_XDMAC0_VBASE+SAM_XDMAC_GTYPE_OFFSET) #define SAM_XDMAC0_GCFG (SAM_XDMAC0_VBASE+SAM_XDMAC_GCFG_OFFSET) @@ -203,13 +206,13 @@ #define SAM_XDMACH1_CSUS(n) (SAM_XDMACH1_CH_BASE(n)+SAM_XDMACH_CSUS_OFFSET) #define SAM_XDMACH1_CDUS(n) (SAM_XDMACH1_CH_BASE(n)+SAM_XDMACH_CDUS_OFFSET) -/* XDMAC Register Bit Definitions ***************************************************/ +/* XDMAC Register Bit Definitions *******************************************/ /* Global Type Register */ #define XDMAC_GTYPE_NB_CH_SHIFT (0) /* Bits 0-4: Number of Channels Minus One */ #define XDMAC_GTYPE_NB_CH_MASK (31 << XDMAC_GTYPE_NB_CH_SHIFT) - #define XDMAC_GTYPE_NB_CH(n) ((uint32_t)(n) << XDMAC_GTYPE_NB_CH_SHIFT) +# define XDMAC_GTYPE_NB_CH(n) ((uint32_t)(n) << XDMAC_GTYPE_NB_CH_SHIFT) #define XDMAC_GTYPE_FIFO_SZ_SHIFT (5) /* Bits 5-15: Number of Bytes */ #define XDMAC_GTYPE_FIFO_SZ_MASK (0x7ff << XDMAC_GTYPE_FIFO_SZ_SHIFT) # define XDMAC_GTYPE_FIFO_SZ(n) ((uint32_t)(n) << XDMAC_GTYPE_FIFO_SZ_SHIFT) @@ -242,25 +245,26 @@ /* All of these registers have the same layout: * - * - Global Interrupt Enable Register, Global Interrupt Disable Register, Interrupt - * Mask Register, and Global Interrupt Status Register. + * - Global Interrupt Enable Register, Global Interrupt Disable Register, + * Interrupt Mask Register, and Global Interrupt Status Register. * - * - Global Channel Enable Register, Global Channel Disable Register, and Global - * Channel Status Register + * - Global Channel Enable Register, Global Channel Disable Register, and + * Global Channel Status Register * - * - Global Channel Read Suspend Register, Global Channel Write Suspend Register, - * Channel Read Write Suspend Register, and Global Channel Read Write Resume + * - Global Channel Read Suspend Register, Global Channel Write Suspend + * Register, Channel Read Write Suspend Register, and Global Channel Read + * Write Resume Register + * + * - Global Channel Software Request Register, Global Channel Software + * Request Status Register, and Global Channel Software Flush Request * Register - * - * - Global Channel Software Request Register, Global Channel Software Request - * Status Register, and Global Channel Software Flush Request Register */ #define XDMAC_CHAN(n) (1 << (n)) #define XDMAC_CHAN_ALL (0x0000ffff) -/* Channel Interrupt Enable Register, Channel Interrupt Disable Register, Channel - * Interrupt Mask Register, and Channel Interrupt Status Register. +/* Channel Interrupt Enable Register, Channel Interrupt Disable Register, + * Channel Interrupt Mask Register, and Channel Interrupt Status Register. */ #define XDMAC_CHINT_BI (1 << 0) /* Bit 0: End of Block Interrupt */ @@ -275,9 +279,12 @@ #define XDMAC_CHINT_ALL (0x0000007f) /* Channel Source Address (SA) Register (aligned 32-bit address) */ + /* Channel Destination Address (DA) Register (aligned 32-bit address) */ -/* Channel Next Descriptor Address (CNDA) Register (aligned 32-bit address) */ +/* Channel Next Descriptor Address (CNDA) Register + * (aligned 32-bit address) + */ #define XDMACH_CNDA_NDAIF (1 << 0) /* Bit 0: Channel Next Descriptor Interface */ @@ -309,10 +316,12 @@ #define XDMACH_CC_MBSIZE_SHIFT (1) /* Bits 1-2: Channel Memory Burst Size */ #define XDMACH_CC_MBSIZE_MASK (3 << XDMACH_CC_MBSIZE_SHIFT) # define XDMACH_CC_MBSIZE(n) ((uint32_t)(n) << XDMACH_CC_MBSIZE_SHIFT) /* n=0-3 */ + # define XDMACH_CC_MBSIZE_1 (0 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to one */ # define XDMACH_CC_MBSIZE_4 (1 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to four */ # define XDMACH_CC_MBSIZE_8 (2 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to eight */ # define XDMACH_CC_MBSIZE_16 (3 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to sixteen */ + #define XDMACH_CC_DSYNC (1 << 4) /* Bit 4: Channel Synchronization */ #define XDMACH_CC_PROT (1 << 5) /* Bit 5: Channel Protection */ #define XDMACH_CC_SWREQ (1 << 6) /* Bit 6: Channel Software Request Trigger */ @@ -324,12 +333,14 @@ # define XDMACH_CC_CSIZE_4 (2 << XDMACH_CC_CSIZE_SHIFT) /* 4 data transferred */ # define XDMACH_CC_CSIZE_8 (3 << XDMACH_CC_CSIZE_SHIFT) /* 8 data transferred */ # define XDMACH_CC_CSIZE_16 (4 << XDMACH_CC_CSIZE_SHIFT) /* 16 data transferred */ + #define XDMACH_CC_DWIDTH_SHIFT (11) /* Bits 11-12: Channel Data Width */ #define XDMACH_CC_DWIDTH_MASK (3 << XDMACH_CC_DWIDTH_SHIFT) # define XDMACH_CC_DWIDTH_BYTE (0 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 8 bits */ # define XDMACH_CC_DWIDTH_HWORD (1 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 16 bits */ # define XDMACH_CC_DWIDTH_WORD (2 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 32 bits */ # define XDMACH_CC_DWIDTH_DWORD (3 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 64 bits */ + #define XDMACH_CC_SIF (1 << 13) /* Bit 13: Channel Source Interface Identifier */ #define XDMACH_CC_DIF (1 << 14) /* Bit 14: Channel Destination Interface Identifier */ #define XDMACH_CC_SAM_SHIFT (16) /* Bits 16-17: Channel Source Addressing Mode */ @@ -338,12 +349,14 @@ # define XDMACH_CC_SAM_INCR (1 << XDMACH_CC_SAM_SHIFT) /* Address is incremented */ # define XDMACH_CC_SAM_UBS (2 << XDMACH_CC_SAM_SHIFT) /* Microblock stride is added */ # define XDMACH_CC_SAM_UBSDS (3 << XDMACH_CC_SAM_SHIFT) /* Microblock stride and data stride is added */ + #define XDMACH_CC_DAM_SHIFT (18) /* Bits 18-19: Channel Destination Addressing Mode */ #define XDMACH_CC_DAM_MASK (3 << XDMACH_CC_DAM_SHIFT) # define XDMACH_CC_DAM_FIXED (0 << XDMACH_CC_DAM_SHIFT) /* The address remains unchanged */ # define XDMACH_CC_DAM_INCR (1 << XDMACH_CC_DAM_SHIFT) /* Address is incremented */ # define XDMACH_CC_DAM_UBS (2 << XDMACH_CC_DAM_SHIFT) /* Microblock stride is added */ # define XDMACH_CC_DAM_UBSDS (3 << XDMACH_CC_DAM_SHIFT) /* Microblock stride and data stride is added */ + #define XDMACH_CC_INITD (1 << 21) /* Bit 21: Channel Initialization Terminated */ #define XDMACH_CC_RDIP (1 << 22) /* Bit 22: Read in Progress */ #define XDMACH_CC_WRIP (1 << 23) /* Bit 23: Write in Progress */ @@ -368,7 +381,8 @@ #define XDMACH_CDUS_DUBS_MASK (0x00ffffff) /* Bits 0-23: Channel Destination Microblock Stride */ -/* XDMA Channel Definitions *************************************************************/ +/* XDMA Channel Definitions *************************************************/ + /* XDMA Controller 0 Channel Definitions (always secure) */ #define XDMAC0_CH_HSMCI0 0 /* HSMCI0 Receive/Transmit */ @@ -456,7 +470,7 @@ #define XDMAC1_CH_SMD_TX 33 /* SMD Transmit */ #define XDMAC1_CH_SMD_RX 34 /* SMD Receive */ -/* Descriptor structure member definitions **********************************************/ +/* Descriptor structure member definitions **********************************/ /* Next Descriptor Address (32-bit address) */ @@ -476,18 +490,22 @@ # define CHNEXT_UBC_NVIEW_3 (3 << CHNEXT_UBC_NVIEW_SHIFT) /* Next Descriptor View 3 */ /* Source Address (32-bit address) */ + /* Destination Address (32-bit address) */ /* Configuration Register */ + /* Block Control */ /* Data Stride (32-bit value) */ + /* Source Microblock Stride (32-bit value) */ + /* Destination Microblock Stride (32-bit value) */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ struct chnext_view0_s { diff --git a/arch/arm/src/sama5/hardware/sama5d2_sdmmc.h b/arch/arm/src/sama5/hardware/sama5d2_sdmmc.h index 5bd7aacbd11..c7d8664485c 100644 --- a/arch/arm/src/sama5/hardware/sama5d2_sdmmc.h +++ b/arch/arm/src/sama5/hardware/sama5d2_sdmmc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/hardware/sama5d2_sdmmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5D2_SDMMC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5D2_SDMMC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define SAMA5D2_SDMMC_SSAR_OFFSET 0x0000 /* SDMA System Address / Argument 2 Register */ #define SAMA5D2_SDMMC_BSR_OFFSET 0x0004 /* Block Size Register */ @@ -69,7 +69,9 @@ #define SAMA5D2_SDMMC_FEREIS_OFFSET 0x0052 /* Force Event Register for Error Interrupt Status */ #define SAMA5D2_SDMMC_AESR_OFFSET 0x0054 /* ADMA Error Status Register */ #define SAMA5D2_SDMMC_ASAR0_OFFSET 0x0054 /* ADMA System Address Register 0 */ + #define SAMA5D2_SDMMC_PVRX_OFFSET(x) (0x60 + x * 0x02) /* Preset Value Register */ + #define SAMA5D2_SDMMC_PVR0_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(0) /* Initialization */ #define SAMA5D2_SDMMC_PVR1_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(1) /* Default Speed */ #define SAMA5D2_SDMMC_PVR2_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(2) /* High Speed */ @@ -78,6 +80,7 @@ #define SAMA5D2_SDMMC_PVR5_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(5) /* SDR50 */ #define SAMA5D2_SDMMC_PVR6_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(6) /* SDR104/HS200 */ #define SAMA5D2_SDMMC_PVR7_OFFSET SAMA5D2_SDMMC_PVRX_OFFSET(7) /* DDR50 */ + #define SAMA5D2_SDMMC_SISR_OFFSET 0x00fc /* Slot Interrupt Status Register */ #define SAMA5D2_SDMMC_HCVR_OFFSET 0x00fe /* Host Controller Version Register */ #define SAMA5D2_SDMMC_APSR_OFFSET 0x0200 /* Additional Present State Register */ @@ -96,7 +99,7 @@ #define SAMA5D2_SDMMC_CACR_OFFSET 0x0230 /* Capabilities Control Register */ #define SAMA5D2_SDMMC_CALCR_OFFSET 0x0240 /* Calibration Control Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ /* For SDMMC0 ... */ @@ -224,7 +227,7 @@ #define SAMA5D2_SDMMC1_CACR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CACR_OFFSET) #define SAMA5D2_SDMMC1_CALCR (SAM_SDMMC1_VBASE + SAMA5D2_SDMMC_CALCR_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Block Size Register (0x04) */ @@ -280,6 +283,7 @@ # define SDMMC_CR_CMDTYP_SUSPEND (1 << SDMMC_CR_CMDTYP_SHIFT) /* CMD52 to write "Bus Suspend" in CCCR */ # define SDMMC_CR_CMDTYP_RESUME (2 << SDMMC_CR_CMDTYP_SHIFT) /* CMD52 to write "Function Select" in CCCR */ # define SDMMC_CR_CMDTYP_ABORT (3 << SDMMC_CR_CMDTYP_SHIFT) /* CMD12, CMD52 to write "I/O Abort" in CCCR */ + #define SDMMC_CR_CMDINX_SHIFT (8) /* Bits 8-13: Command Index */ #define SDMMC_CR_CMDINX_MASK (0x3f << SDMMC_CR_CMDINX_SHIFT) @@ -313,11 +317,13 @@ #define SDMMC_HC1R_DW_MASK (1 << SDMMC_HC1R_DW_SHIFT) # define SDMMC_HC1R_DW_1BIT (0 << SDMMC_HC1R_DW_SHIFT) /* 1-bit mode */ # define SDMMC_HC1R_DW_4BIT (1 << SDMMC_HC1R_DW_SHIFT) /* 4-bit mode */ + #define SDMMC_H1CR_HSEN (1 << 2) /* Bit 2: High Speed Enable */ #define SDMMC_H1CR_DMASEL_SHIFT (3) /* Bits 3-4: DMA Select */ #define SDMMC_H1CR_DMASEL_MASK (3 << SDMMC_DMASEL_SHIFT) # define SDMMC_H1CR_DMASEL_SDMA (0 << SDMMC_DMASEL_SHIFT) /* SDMA is selected */ # define SDMMC_H1CR_DMASEL_ADMA32 (2 << SDMMC_DMASEL_SHIFT) /* 32-bit Address ADMA2 is selected */ + #define SDMMC_H1CR_EXTDW (1 << 5) /* Bit 5: Extended Data Width (e.MMC) */ #define SDMMC_H1CR_CARDDTL (1 << 6) /* Bit 6: Card Detect Test Level */ #define SDMMC_H1CR_CARDDSEL (1 << 7) /* Bit 7: Card Detect Signal Selection */ @@ -464,9 +470,11 @@ # define SDMMC_HC2R_UHSMS_SDR50 (2 << SDMMC_HC2R_UHSMS_SHIFT) /* UHS SDR50 Mode */ # define SDMMC_HC2R_UHSMS_SDR104 (3 << SDMMC_HC2R_UHSMS_SHIFT) /* UHS SDR104 Mode */ # define SDMMC_HC2R_UHSMS_DDR50 (4 << SDMMC_HC2R_UHSMS_SHIFT) /* UHS DDR50 Mode */ + #define SDMMC_HC2R_HS200EN_SHIFT (0) /* Bits 0-3: HS200 Mode Enable (e.MMC) */ #define SDMMC_HC2R_HS200EN_MASK (0x0f << SDMMC_HC2R_HS200EN_SHIFT) # define SDMMC_HC2R_HS200EN_ENABLE (0x0b << SDMMC_HC2R_HS200EN_SHIFT) /* HS200 mode is enabled */ + #define SDMMC_HC2R_VS18EN (1 << 3) /* Bit 3: 1.8V Signaling Enable */ #define SDMMC_HC2R_DRVSEL_SHIFT (4) /* Bits 4-5: Driver Strength Select */ #define SDMMC_HC2R_DRVSEL_MASK (3 << SDMMC_HC2R_DRVSEL_SHIFT) @@ -474,6 +482,7 @@ # define SDMMC_HC2R_DRVSEL_TYPEA (1 << SDMMC_HC2R_DRVSEL_SHIFT) /* Driver Type A is selected */ # define SDMMC_HC2R_DRVSEL_TYPEC (2 << SDMMC_HC2R_DRVSEL_SHIFT) /* Driver Type C is selected */ # define SDMMC_HC2R_DRVSEL_TYPED (3 << SDMMC_HC2R_DRVSEL_SHIFT) /* Driver Type D is selected */ + #define SDMMC_HC2R_EXTUN (1 << 6) /* Bit 6: Execute Tuning */ #define SDMMC_HC2R_SCLKSEL (1 << 7) /* Bit 7: Sampling Clock Select */ #define SDMMC_HC2R_ASINTEN (1 << 14) /* Bit 14: Asynchronous Interrupt Enable */ @@ -496,6 +505,7 @@ #define SDMMC_CA0R_MAXBLKL_1024 (1 << SDMMC_CA0R_MAXBLKL_SHIFT) /* 1024 bytes */ #define SDMMC_CA0R_MAXBLKL_2048 (2 << SDMMC_CA0R_MAXBLKL_SHIFT) /* 2048 bytes */ #define SDMMC_CA0R_MAXBLKL_NONE (3 << SDMMC_CA0R_MAXBLKL_SHIFT) /* Reserved */ + #define SDMMC_CA0R_ED8SUP (1 << 18) /* Bit 18: 8-Bit Support for Embedded Device */ #define SDMMC_CA0R_ADMA2SUP (1 << 19) /* Bit 19: ADMA2 Support */ #define SDMMC_CA0R_HSSUP (1 << 21) /* Bit 21: High Speed Support */ @@ -528,6 +538,7 @@ #define SDMMC_CA1R_RTMOD_MODE1 (0 << SDMMC_CA1R_RTMOD_SHIFT) /* MODE1: Timer */ #define SDMMC_CA1R_RTMOD_MODE2 (1 << SDMMC_CA1R_RTMOD_SHIFT) /* MODE2: Timer and Retuning Request */ #define SDMMC_CA1R_RTMOD_MODE3 (2 << SDMMC_CA1R_RTMOD_SHIFT) /* MODE3: Auto Retuning Timer and Retuning Request */ + #define SDMMC_CA1R_CLKMULT_SHIFT (16) /* Bits 16-23: Clock Multiplier */ #define SDMMC_CA1R_CLKMULT_MASK (0xf << SDMMC_CA1R_CLKMULT_SHIFT) #define SDMMC_CA1R_CLKMULT(n) ((n & 0xf) << SDMMC_CA1R_CLKMULT_SHIFT) @@ -589,16 +600,16 @@ #define SDMMC_CACR_KEY_ENABLE (0x46 << SDMMC_CACR_KEY_SHIFT) #define SDMMC_CACR_KEY_DISABLE (0x00 << SDMMC_CACR_KEY_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAMA5D2_SDMMC_H */ diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c index e94170af17c..21bf51a71dc 100644 --- a/arch/arm/src/sama5/sam_allocateheap.c +++ b/arch/arm/src/sama5/sam_allocateheap.c @@ -43,7 +43,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a * single heap access with the standard allocations (malloc/free). This * heap is referred to as the user heap. In the protected build @@ -67,6 +69,7 @@ #endif /* The Primary Heap *********************************************************/ + /* The physical address of the primary heap is defined by CONFIG_RAM_START, * CONFIG_RAM_SIZE, and CONFIG_RAM_END where: * @@ -110,6 +113,7 @@ */ /* Memory Regions ***********************************************************/ + /* Check if we have been asked to reserve memory at the end of the primary * memory region. This option is only available if we are executing from * DRAM and only if CONFIG_SAMA5_DDRCS_RESERVE is selected. @@ -181,8 +185,8 @@ #endif /* The heap space in the primary memory region is added automatically when - * up_allocate_heap is called. So if the memory region is the primary region, - * it should not be added to the heap (again). + * up_allocate_heap is called. So if the memory region is the primary + * region, it should not be added to the heap (again). */ #if (CONFIG_RAM_VSTART & 0xfff00000) == SAM_ISRAM0_VADDR @@ -383,8 +387,9 @@ void arm_addregion(void) if (nregions > 0) { - serr("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS); + serr("ERROR: Not all regions added to heap: %d added,", + CONFIG_MM_REGIONS - nregions); + serr(" but CONFIG_MM_NREGIONS=%d\n", CONFIG_MM_REGIONS); serr(" Decrease the size of CONFIG_MM_NREGIONS\n"); } } diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c index 5111b8f65cb..ec9007d4e42 100644 --- a/arch/arm/src/sama5/sam_boot.c +++ b/arch/arm/src/sama5/sam_boot.c @@ -208,8 +208,8 @@ static void sam_vectormapping(void) * Description: * Copy the interrupt block to its final destination. Vectors are already * positioned at the beginning of the text region and only need to be - * copied in the case where we are using high vectors or where the beginning - * of the text region cannot be remapped to address zero. + * copied in the case where we are using high vectors or where the + * beginning of the text region cannot be remapped to address zero. * ****************************************************************************/ @@ -228,8 +228,8 @@ static void sam_copyvectorblock(void) sam_vectorpermissions(MMU_L2_VECTRWFLAGS); #endif - /* Copy the vectors into ISRAM at the address that will be mapped to the vector - * address: + /* Copy the vectors into ISRAM at the address that will be mapped to the + * vector address: * * SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM * SAM_VECTOR_VSRAM - Virtual address of vector table in SRAM @@ -252,7 +252,9 @@ static void sam_copyvectorblock(void) sam_vectorpermissions(MMU_L2_VECTORFLAGS); #else - /* Flush the DCache to assure that the vector data is in physical in ISRAM */ + /* Flush the DCache to assure that the vector data is in physical in + * ISRAM + */ up_clean_dcache((uintptr_t)SAM_VECTOR_VSRAM, (uintptr_t)SAM_VECTOR_VSRAM + sam_vectorsize()); diff --git a/arch/arm/src/sama5/sam_boot.h b/arch/arm/src/sama5/sam_boot.h index 0b632be31c5..43315e7f957 100644 --- a/arch/arm/src/sama5/sam_boot.h +++ b/arch/arm/src/sama5/sam_boot.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_boot.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_BOOT_H #define __ARCH_ARM_SRC_SAMA5_SAM_BOOT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_boardinitialize * * Description: - * All SAMA5 architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * All SAMA5 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after + * clocking and memory have been configured but before caches have been + * enabled and before any devices have been initialized. * - ************************************************************************************/ + ****************************************************************************/ void sam_boardinitialize(void); diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index a2de85cffca..5f6789588be 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -1198,7 +1198,9 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) # warning REVISIT #endif - /* The message buffer is probably not properaly aligned for 32-bit accesses */ + /* The message buffer is probably not properaly aligned for 32-bit + * accesses + */ ptr = msg->cm_data; regval = CAN_MDL0(ptr[0]) | CAN_MDL1(ptr[1]) | CAN_MDL2(ptr[2]) | diff --git a/arch/arm/src/sama5/sam_can.h b/arch/arm/src/sama5/sam_can.h index edf0733cf4b..2a76d13d020 100644 --- a/arch/arm/src/sama5/sam_can.h +++ b/arch/arm/src/sama5/sam_can.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_can.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_CAN_H #define __ARCH_ARM_SRC_SAMA5_SAM_CAN_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -34,10 +34,11 @@ #if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1)) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ /* CAN BAUD */ @@ -81,15 +82,15 @@ # define CONFIG_SAMA5_CAN1_NRECVMB 0 #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -100,9 +101,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ /**************************************************************************** * Name: sama5_caninitialize diff --git a/arch/arm/src/sama5/sam_clockconfig.c b/arch/arm/src/sama5/sam_clockconfig.c index c9fde103a6a..d1135c86b05 100644 --- a/arch/arm/src/sama5/sam_clockconfig.c +++ b/arch/arm/src/sama5/sam_clockconfig.c @@ -278,7 +278,9 @@ static void __ramfunc__ sam_plladivider(void) putreg32(regval, SAM_PMC_MCKR); - /* We changed the PLLA divider. Wait for the main clock to be ready again */ + /* We changed the PLLA divider. + * Wait for the main clock to be ready again + */ sam_pmcwait(PMC_INT_MCKRDY); } diff --git a/arch/arm/src/sama5/sam_config.h b/arch/arm/src/sama5/sam_config.h index 9c9eac5cdf3..c9a5b0a9ed3 100644 --- a/arch/arm/src/sama5/sam_config.h +++ b/arch/arm/src/sama5/sam_config.h @@ -31,7 +31,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Configuration **********************************************************/ +/* Configuration ************************************************************/ /* If the USART is not being used as a UART, then it really isn't enabled * for our purposes. diff --git a/arch/arm/src/sama5/sam_dmac.h b/arch/arm/src/sama5/sam_dmac.h index 2dcfe284771..96b169f5867 100644 --- a/arch/arm/src/sama5/sam_dmac.h +++ b/arch/arm/src/sama5/sam_dmac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_DMAC_H #define __ARCH_ARM_SRC_SAMA5_SAM_DMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,34 +31,38 @@ #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ #ifndef CONFIG_DEBUG_FEATURES # undef CONFIG_DEBUG_DMA #endif -/* DMA ******************************************************************************/ +/* DMA **********************************************************************/ -/* Flags used to characterize the DMA channel. The naming convention is that one - * side is the peripheral and the other is memory (however, the interface could still - * be used if, for example, both sides were memory although the naming would be - * awkward) +/* Flags used to characterize the DMA channel. The naming convention is that + * one side is the peripheral and the other is memory (however, the interface + * could still be used if, for example, both sides were memory although the + * naming would be awkward) */ #if defined(ATSAMA5D3) /* MMMM MMMM MMMM MMMP PPPP PPPP PPPP PPFF - * .... .... .... .... .... .... .... ..FF Configurable properties of the channel - * .... .... .... ...P PPPP PPPP PPPP PP.. Peripheral endpoint characteristics - * MMMM MMMM MMMM MMM. .... .... .... .... Memory endpoint characteristics + * .... .... .... .... .... .... .... ..FF Configurable properties of + * the channel + * .... .... .... ...P PPPP PPPP PPPP PP.. Peripheral endpoint + * characteristics + * MMMM MMMM MMMM MMM. .... .... .... .... Memory endpoint + * characteristics */ /* Bits 0-1: Configurable properties of the channel * - * .... .... .... .... .... .... .... ..FF Configurable properties of the channel + * .... .... .... .... .... .... .... ..FF Configurable properties of + * the channel */ # define DMACH_FLAG_BURST_LARGEST 0 /* Largest length AHB burst */ @@ -73,13 +77,15 @@ /* Bits 2-16: Peripheral endpoint characteristics * - * .... .... .... ...P PPPP PPPP PPPP PP.. Peripheral endpoint characteristics + * .... .... .... ...P PPPP PPPP PPPP PP.. Peripheral endpoint + * characteristics * .... .... .... .... .... .... IIII II.. Peripheral ID, range 0-49 * .... .... .... .... .... ...H .... .... HW Handshaking * .... .... .... .... .... ..P. .... .... 0=memory; 1=peripheral * .... .... .... .... .... NN.. .... .... Peripheral ABH layer number * .... .... .... .... ..WW .... .... .... Peripheral width - * .... .... .... .... .A.. .... .... .... Auto-increment peripheral address + * .... .... .... .... .A.. .... .... .... Auto-increment peripheral + * address * .... .... .... ...S S... .... .... .... Peripheral chunk size */ @@ -94,12 +100,14 @@ # define DMACH_FLAG_PERIPHAHB_AHB_IF0 (0 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 0 */ # define DMACH_FLAG_PERIPHAHB_AHB_IF1 (1 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 1 */ # define DMACH_FLAG_PERIPHAHB_AHB_IF2 (2 << DMACH_FLAG_PERIPHAHB_SHIFT) /* AHB-Lite Interface 2 */ + # define DMACH_FLAG_PERIPHWIDTH_SHIFT (12) /* Bits 12-13: Peripheral width */ # define DMACH_FLAG_PERIPHWIDTH_MASK (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) # define DMACH_FLAG_PERIPHWIDTH_8BITS (0 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 8 bits */ # define DMACH_FLAG_PERIPHWIDTH_16BITS (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */ # define DMACH_FLAG_PERIPHWIDTH_32BITS (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */ # define DMACH_FLAG_PERIPHWIDTH_64BITS (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 64 bits */ + # define DMACH_FLAG_PERIPHINCREMENT (1 << 14) /* Bit 14: Auto-increment peripheral address */ # define DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT (15) /* Bits 15-16: Peripheral chunk size */ # define DMACH_FLAG_PERIPHCHUNKSIZE_MASK (3 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) @@ -111,13 +119,16 @@ /* Bits 17-31: Memory endpoint characteristics * - * MMMM MMMM MMMM MMM. .... .... .... .... Memory endpoint characteristics - * .... .... .III III. .... .... .... .... Memory/peripheral ID, range 0-49 + * MMMM MMMM MMMM MMM. .... .... .... .... Memory endpoint + * characteristics + * .... .... .III III. .... .... .... .... Memory/peripheral ID, + * range 0-49 * .... .... H... .... .... .... .... .... HW Handshaking * .... ...P .... .... .... .... .... .... 0=memory; 1=peripheral * .... .NN. .... .... .... .... .... .... Peripheral ABH layer number * ...W W... .... .... .... .... .... .... Peripheral width - * ..A. .... .... .... .... .... .... .... Auto-increment peripheral address + * ..A. .... .... .... .... .... .... .... Auto-increment peripheral + * address * SS.. .... .... .... .... .... .... .... Peripheral chunk size */ @@ -132,12 +143,14 @@ # define DMACH_FLAG_MEMAHB_AHB_IF0 (0 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 0 */ # define DMACH_FLAG_MEMAHB_AHB_IF1 (1 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 1 */ # define DMACH_FLAG_MEMAHB_AHB_IF2 (2 << DMACH_FLAG_MEMAHB_SHIFT) /* AHB-Lite Interface 2 */ + # define DMACH_FLAG_MEMWIDTH_SHIFT (27) /* Bits 27-28: Memory width */ # define DMACH_FLAG_MEMWIDTH_MASK (3 << DMACH_FLAG_MEMWIDTH_SHIFT) # define DMACH_FLAG_MEMWIDTH_8BITS (0 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 8 bits */ # define DMACH_FLAG_MEMWIDTH_16BITS (1 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 16 bits */ # define DMACH_FLAG_MEMWIDTH_32BITS (2 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 32 bits */ # define DMACH_FLAG_MEMWIDTH_64BITS (3 << DMACH_FLAG_MEMWIDTH_SHIFT) /* 64 bits */ + # define DMACH_FLAG_MEMINCREMENT (1 << 29) /* Bit 29: Auto-increment memory address */ # define DMACH_FLAG_MEMCHUNKSIZE_SHIFT (30) /* Bit 30-31: Memory chunk size */ # define DMACH_FLAG_MEMCHUNKSIZE_MASK (3 << DMACH_FLAG_MEMCHUNKSIZE_SHIFT) @@ -154,14 +167,18 @@ #elif defined(ATSAMA5D4) /* .... .... .... MMMM .PPP PPPP PPPP PPPP - * .... .... .... .... .... .... .... .... Configurable properties of the channel - * .... .... .... .... .PPP PPPP PPPP PPPP Peripheral endpoint characteristics - * .... .... .... MMMM .... .... .... .... Memory endpoint characteristics + * .... .... .... .... .... .... .... .... Configurable properties of + * the channel + * .... .... .... .... .PPP PPPP PPPP PPPP Peripheral endpoint + * characteristics + * .... .... .... MMMM .... .... .... .... Memory endpoint + * characteristics */ /* Bits 0-1: Configurable properties of the channel * - * .... .... .... .... .... .... .... .... Configurable properties of the channel + * .... .... .... .... .... .... .... .... Configurable properties + * of the channel * * NOTE: Many "peripheral" attributes are really "channel" attributes for * the SAMA5D4's XDMAC since it does not support peripheral-to-peripheral @@ -174,13 +191,15 @@ /* Bits 0-15: Peripheral endpoint characteristics * - * .... .... .... .... .PPP PPPP PPPP PPPP Peripheral endpoint characteristics + * .... .... .... .... .PPP PPPP PPPP PPPP Peripheral endpoint + * characteristics * .... .... .... .... .... .... .III IIII Peripheral ID, range 0-67 * .... .... .... .... .... .... .... .... No HW Handshaking * .... .... .... .... .... .... P... .... 0=memory; 1=peripheral * .... .... .... .... .... ...N .... .... Peripheral ABH layer number * .... .... .... .... .... .WW. .... .... Peripheral width - * .... .... .... .... .... A... .... .... Auto-increment peripheral address + * .... .... .... .... .... A... .... .... Auto-increment peripheral + * address * .... .... .... .... .SSS .... .... .... Peripheral chunk size */ @@ -199,6 +218,7 @@ # define DMACH_FLAG_PERIPHWIDTH_16BITS (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */ # define DMACH_FLAG_PERIPHWIDTH_32BITS (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */ # define DMACH_FLAG_PERIPHWIDTH_64BITS (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 64 bits */ + # define DMACH_FLAG_PERIPHINCREMENT (1 << 11) /* Bit 11: Auto-increment peripheral address */ # define DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT (12) /* Bits 12-14: Peripheral chunk size */ # define DMACH_FLAG_PERIPHCHUNKSIZE_MASK (7 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) @@ -210,8 +230,10 @@ /* Bits 16-19: Memory endpoint characteristics * - * .... .... .... MMMM .... .... .... .... Memory endpoint characteristics - * .... .... .... .... .... .... .... .... No memory peripheral ID, range 0-49 + * .... .... .... MMMM .... .... .... .... Memory endpoint + * characteristics + * .... .... .... .... .... .... .... .... No memory peripheral ID, + * range 0-49 * .... .... .... .... .... .... .... .... No HW Handshaking * .... .... .... .... .... .... .... .... No peripheral-to-peripheral * .... .... .... ...N .... .... .... .... Memory ABH layer number @@ -251,14 +273,16 @@ #endif /* ATSAMA5D4 */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA + * is selected + */ #ifdef CONFIG_DEBUG_DMA #if defined(CONFIG_SAMA5_DMAC0) || defined(CONFIG_SAMA5_DMAC1) @@ -325,15 +349,15 @@ struct sam_dmaregs_s #endif /* CONFIG_SAMA5_XDMAC0 || CONFIG_SAMA5_XDMAC1 */ #endif /* CONFIG_DEBUG_DMA */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -344,37 +368,39 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_dmachannel * * Description: - * Allocate a DMA channel. This function sets aside a DMA channel then gives the + * Allocate a DMA channel. + * This function sets aside a DMA channel then gives the * caller exclusive access to the DMA channel. * - * The naming convention in all of the DMA interfaces is that one side is the - * 'peripheral' and the other is 'memory'. However, the interface could still - * be used if, for example, both sides were memory although the naming would be - * awkward. + * The naming convention in all of the DMA interfaces is that one side is + * the 'peripheral' and the other is 'memory'. However, the interface + * could still be used if, for example, both sides were memory although the + * naming would be awkward. * * Returned Value: - * If a DMA channel is available, this function returns a non-NULL, void* DMA - * channel handle. NULL is returned on any failure. + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. * - ************************************************************************************/ + ****************************************************************************/ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmaconfig * * Description: - * There are two channel usage models: (1) The channel is allocated and configured - * in one step. This is the typical case where a DMA channel performs a constant - * role. The alternative is (2) where the DMA channel is reconfigured on the fly. + * There are two channel usage models: + * (1) The channel is allocated and configured in one step. This is the + * typical case where a DMA channel performs a constant role. + * The alternative is (2) where the DMA channel is reconfigured on the fly. * In this case, the chflags provided to sam_dmachannel are not used and * sam_dmaconfig() is called before each DMA to configure the DMA channel * appropriately. @@ -382,78 +408,83 @@ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags); * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmafree * * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must NEVER be - * used again until sam_dmachannel() is called again to re-gain a valid handle. + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again until + * sam_dmachannel() is called again to re-gain a valid handle. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_dmafree(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmatxsetup * * Description: - * Configure DMA for transmit of one buffer (memory to peripheral). This function - * may be called multiple times to handle large and/or discontinuous transfers. - * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the - * same transfer, however. + * Configure DMA for transmit of one buffer (memory to peripheral). This + * function may be called multiple times to handle large and/or + * discontinuous transfers. Calls to sam_dmatxsetup() and sam_dmarxsetup() + * must not be intermixed on the same transfer, however. * - ************************************************************************************/ + ****************************************************************************/ -int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes); +int sam_dmatxsetup(DMA_HANDLE handle, + uint32_t paddr, uint32_t maddr, size_t nbytes); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmarxsetup * * Description: - * Configure DMA for receipt of one buffer (peripheral to memory). This function - * may be called multiple times to handle large and/or discontinuous transfers. - * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the - * same transfer, however. + * Configure DMA for receipt of one buffer (peripheral to memory). This + * function may be called multiple times to handle large and/or + * discontinuous transfers. Calls to sam_dmatxsetup() and sam_dmarxsetup() + * must not be intermixed on the same transfer, however. * - ************************************************************************************/ + ****************************************************************************/ -int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes); +int sam_dmarxsetup(DMA_HANDLE handle, + uint32_t paddr, uint32_t maddr, size_t nbytes); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmastart * * Description: * Start the DMA transfer * - ************************************************************************************/ + ****************************************************************************/ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmastop * * Description: - * Cancel the DMA. After sam_dmastop() is called, the DMA channel is reset and - * sam_dmarx/txsetup() must be called before sam_dmastart() can be called again + * Cancel the DMA. + * After sam_dmastop() is called, the DMA channel is reset and + * sam_dmarx/txsetup() must be called before sam_dmastart() can be called + * again * - ************************************************************************************/ + ****************************************************************************/ void sam_dmastop(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmasample * * Description: * Sample DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); @@ -461,16 +492,17 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); # define sam_dmasample(handle,regs) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_dmadump * * Description: * Dump previously sampled DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA -void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg); +void sam_dmadump(DMA_HANDLE handle, + const struct sam_dmaregs_s *regs, const char *msg); #else # define sam_dmadump(handle,regs,msg) #endif diff --git a/arch/arm/src/sama5/sam_ethernet.h b/arch/arm/src/sama5/sam_ethernet.h index bde170b3482..4a19c925810 100644 --- a/arch/arm/src/sama5/sam_ethernet.h +++ b/arch/arm/src/sama5/sam_ethernet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_ethernet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_ETHERNET_H #define __ARCH_ARM_SRC_SAMA5_SAM_ETHERNET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,9 +31,10 @@ #include "hardware/sam_emac.h" #include "hardware/sam_gmac.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Understood PHY types */ #define SAMA5_PHY_DM9161 0 @@ -235,9 +236,9 @@ # endif #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -294,15 +295,16 @@ int sam_emac_initialize(void); int sam_emac_initialize(int intf); #endif -/************************************************************************************ +/**************************************************************************** * Function: sam_phy_boardinitialize * * Description: - * Some boards require specialized initialization of the PHY before it can be used. - * This may include such things as configuring GPIOs, resetting the PHY, etc. If - * CONFIG_SAMA5_PHYINIT is defined in the configuration then the board specific - * logic must provide sam_phyinitialize(); The SAMA5 Ethernet driver will call - * this function one time before it first uses the PHY. + * Some boards require specialized initialization of the PHY before it can + * be used. This may include such things as configuring GPIOs, resetting + * the PHY, etc. If CONFIG_SAMA5_PHYINIT is defined in the configuration + * then the board specific logic must provide sam_phyinitialize(); + * The SAMA5 Ethernet driver will call this function one time before it + * first uses the PHY. * * Input Parameters: * intf - Always zero for now. @@ -312,7 +314,7 @@ int sam_emac_initialize(int intf); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMA5_PHYINIT int sam_phy_boardinitialize(int intf); diff --git a/arch/arm/src/sama5/sam_freerun.c b/arch/arm/src/sama5/sam_freerun.c index 1b8b7d04410..3298cd68d6c 100644 --- a/arch/arm/src/sama5/sam_freerun.c +++ b/arch/arm/src/sama5/sam_freerun.c @@ -228,8 +228,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) DEBUGASSERT(freerun && freerun->tch && ts); - /* Temporarily disable the overflow counter. NOTE that we have to be careful - * here because sam_tc_getpending() will reset the pending interrupt status. + /* Temporarily disable the overflow counter. + * NOTE that we have to be careful here because sam_tc_getpending() will + * reset the pending interrupt status. * If we do not handle the overflow here then, it will be lost. */ diff --git a/arch/arm/src/sama5/sam_gf1024.c b/arch/arm/src/sama5/sam_gf1024.c index f85965d0c34..f7e013654b3 100644 --- a/arch/arm/src/sama5/sam_gf1024.c +++ b/arch/arm/src/sama5/sam_gf1024.c @@ -1,10 +1,12 @@ -/********************************************************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/sam_gf1024.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Taken from Atmel NoOS sample code. The Atmel sample code has a BSD compatible license that requires this copyright notice: + * Taken from Atmel NoOS sample code. + * The Atmel sample code has a BSD compatible license that + * requires this copyright notice: * * Copyright (c) 2012, Atmel Corporation * @@ -35,11 +37,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - **********************************************************************************************************************************/ + ****************************************************************************/ -/********************************************************************************************************************************** +/**************************************************************************** * Included Files - **********************************************************************************************************************************/ + ****************************************************************************/ #include #include @@ -50,2070 +52,4125 @@ #if defined(CONFIG_SAMA5_HAVE_PMECC) && !defined(CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES) -/********************************************************************************************************************************** +/**************************************************************************** * Public Data - **********************************************************************************************************************************/ + ****************************************************************************/ -/* Gallois Field tables for 1024 bytes sectors. First raw is "index_of" and second one is "alpha_to" */ +/* Gallois Field tables for 1024 bytes sectors. + * First raw is "index_of" and second one is "alpha_to" + */ + + /* "index_of" table */ const uint16_t pmecc_gf_1024[2][PMECC_GF_SIZEOF_1024] = { - /* "index_of" table */ { - 0xffff, 0x0000, 0x0001, 0x0572, 0x0002, 0x0ae4, 0x0573, 0x015b, 0x0003, 0x06cd, 0x0ae5, 0x1ad9, 0x0574, 0x012e, 0x015c, 0x1056, - 0x0004, 0x15c8, 0x06ce, 0x288d, 0x0ae6, 0x02b6, 0x1ada, 0x06a0, 0x0575, 0x2ed2, 0x012f, 0x0c3f, 0x015d, 0x204b, 0x1057, 0x3812, - 0x0005, 0x3d84, 0x15c9, 0x0289, 0x06cf, 0x347d, 0x288e, 0x25bd, 0x0ae7, 0x10d1, 0x02b7, 0x3444, 0x1adb, 0x11b1, 0x06a1, 0x109c, - 0x0576, 0x1c34, 0x2ed3, 0x1b3a, 0x0130, 0x2dff, 0x0c40, 0x2238, 0x015e, 0x0c12, 0x204c, 0x3d67, 0x1058, 0x3f47, 0x3813, 0x0828, - 0x0006, 0x0d9a, 0x3d85, 0x15d2, 0x15ca, 0x35b2, 0x028a, 0x04ba, 0x06d0, 0x1f3c, 0x347e, 0x1184, 0x288f, 0x02da, 0x25be, 0x302d, - 0x0ae8, 0x025c, 0x10d2, 0x21a6, 0x02b8, 0x20ac, 0x3445, 0x034f, 0x1adc, 0x27aa, 0x11b2, 0x2bb3, 0x06a2, 0x396d, 0x109d, 0x3371, - 0x0577, 0x3bd2, 0x1c35, 0x02f7, 0x2ed4, 0x07fb, 0x1b3b, 0x1a8e, 0x0131, 0x2b2f, 0x2e00, 0x0411, 0x0c41, 0x0beb, 0x2239, 0x39ef, - 0x015f, 0x160e, 0x0c13, 0x0012, 0x204d, 0x363b, 0x3d68, 0x1723, 0x1059, 0x29e8, 0x3f48, 0x1643, 0x3814, 0x39b6, 0x0829, 0x1c07, - 0x0007, 0x2179, 0x0d9b, 0x2142, 0x3d86, 0x2393, 0x15d3, 0x3f28, 0x15cb, 0x1305, 0x35b3, 0x2f5a, 0x028b, 0x1bb5, 0x04bb, 0x2310, - 0x06d1, 0x270d, 0x1f3d, 0x1b80, 0x347f, 0x0584, 0x1185, 0x1d8f, 0x2890, 0x1c95, 0x02db, 0x3940, 0x25bf, 0x27e8, 0x302e, 0x3bad, - 0x0ae9, 0x3ec2, 0x025d, 0x0145, 0x10d3, 0x0869, 0x21a7, 0x3a22, 0x02b9, 0x2000, 0x20ad, 0x22b9, 0x3446, 0x0367, 0x0350, 0x0d6d, - 0x1add, 0x3f61, 0x27ab, 0x00a3, 0x11b3, 0x3000, 0x2bb4, 0x115d, 0x06a3, 0x10bd, 0x396e, 0x30a1, 0x109e, 0x0983, 0x3372, 0x37ad, - 0x0578, 0x3048, 0x3bd3, 0x130c, 0x1c36, 0x1b44, 0x02f8, 0x29bb, 0x2ed5, 0x0a2c, 0x07fc, 0x3744, 0x1b3c, 0x11f7, 0x1a8f, 0x3b24, - 0x0132, 0x359f, 0x2b30, 0x0488, 0x2e01, 0x3cf5, 0x0412, 0x084c, 0x0c42, 0x12ec, 0x0bec, 0x24ae, 0x223a, 0x16f6, 0x39f0, 0x122c, - 0x0160, 0x38e3, 0x160f, 0x09ac, 0x0c14, 0x03a2, 0x0013, 0x3edf, 0x204e, 0x03e4, 0x363c, 0x2d1c, 0x3d69, 0x3125, 0x1724, 0x14c0, - 0x105a, 0x1bca, 0x29e9, 0x07ce, 0x3f49, 0x2718, 0x1644, 0x193c, 0x3815, 0x08c1, 0x39b7, 0x35d8, 0x082a, 0x2d6b, 0x1c08, 0x261e, - 0x0008, 0x2b90, 0x217a, 0x0d46, 0x0d9c, 0x111b, 0x2143, 0x32dd, 0x3d87, 0x2b75, 0x2394, 0x0e33, 0x15d4, 0x3b4a, 0x3f29, 0x3e95, - 0x15cc, 0x056c, 0x1306, 0x213c, 0x35b4, 0x0d40, 0x2f5b, 0x26e5, 0x028c, 0x1eae, 0x1bb6, 0x327a, 0x04bc, 0x30fc, 0x2311, 0x2c8a, - 0x06d2, 0x0076, 0x270e, 0x3e55, 0x1f3e, 0x0f1e, 0x1b81, 0x3d2d, 0x3480, 0x0452, 0x0585, 0x1ab7, 0x1186, 0x3dd4, 0x1d90, 0x0914, - 0x2891, 0x1a32, 0x1c96, 0x2baa, 0x02dc, 0x1be9, 0x3941, 0x3697, 0x25c0, 0x2e82, 0x27e9, 0x0956, 0x302f, 0x328e, 0x3bae, 0x1665, - 0x0aea, 0x1da5, 0x3ec3, 0x35ba, 0x025e, 0x187e, 0x0146, 0x0f57, 0x10d4, 0x2f2d, 0x086a, 0x3796, 0x21a8, 0x1e5b, 0x3a23, 0x20b6, - 0x02ba, 0x0097, 0x2001, 0x2366, 0x20ae, 0x3025, 0x22ba, 0x1769, 0x3447, 0x016d, 0x0368, 0x0f9e, 0x0351, 0x3cb6, 0x0d6e, 0x13d5, - 0x1ade, 0x179e, 0x3f62, 0x072b, 0x27ac, 0x3b66, 0x00a4, 0x1c68, 0x11b4, 0x19c3, 0x3001, 0x185e, 0x2bb5, 0x2a20, 0x115e, 0x2b43, - 0x06a4, 0x0d33, 0x10be, 0x3b11, 0x396f, 0x09fa, 0x30a2, 0x16ed, 0x109f, 0x0dbe, 0x0984, 0x0242, 0x3373, 0x1d62, 0x37ae, 0x0268, - 0x0579, 0x2d0e, 0x3049, 0x26eb, 0x3bd4, 0x26b4, 0x130d, 0x0a5e, 0x1c37, 0x049b, 0x1b45, 0x2102, 0x02f9, 0x2c47, 0x29bc, 0x2905, - 0x2ed6, 0x2882, 0x0a2d, 0x3ac8, 0x07fd, 0x1841, 0x3745, 0x2127, 0x1b3d, 0x35ab, 0x11f8, 0x1877, 0x1a90, 0x34cc, 0x3b25, 0x08a8, - 0x0133, 0x0120, 0x35a0, 0x0c2e, 0x2b31, 0x04aa, 0x0489, 0x2d5a, 0x2e02, 0x2b20, 0x3cf6, 0x2207, 0x0413, 0x3eb2, 0x084d, 0x1a21, - 0x0c43, 0x081b, 0x12ed, 0x2c7f, 0x0bed, 0x20f2, 0x24af, 0x03b7, 0x223b, 0x2301, 0x16f7, 0x1760, 0x39f1, 0x2a10, 0x122d, 0x0af6, - 0x0161, 0x3d1f, 0x38e4, 0x2f61, 0x1610, 0x11ff, 0x09ad, 0x0ef5, 0x0c15, 0x172d, 0x03a3, 0x162f, 0x0014, 0x3613, 0x3ee0, 0x0b0e, - 0x204f, 0x20a0, 0x03e5, 0x04d4, 0x363d, 0x0615, 0x2d1d, 0x2218, 0x3d6a, 0x16cf, 0x3126, 0x370d, 0x1725, 0x0a24, 0x14c1, 0x3572, - 0x105b, 0x3d11, 0x1bcb, 0x0435, 0x29ea, 0x06b7, 0x07cf, 0x01b4, 0x3f4a, 0x3f94, 0x2719, 0x11ca, 0x1645, 0x3188, 0x193d, 0x0ddb, - 0x3816, 0x12df, 0x08c2, 0x1a3f, 0x39b8, 0x284e, 0x35d9, 0x08d9, 0x082b, 0x00ae, 0x2d6c, 0x2572, 0x1c09, 0x282b, 0x261f, 0x2097, - 0x0009, 0x2609, 0x2b91, 0x1eb4, 0x217b, 0x2e1a, 0x0d47, 0x2d9d, 0x0d9d, 0x3769, 0x111c, 0x0620, 0x2144, 0x2ae4, 0x32de, 0x1447, - 0x3d88, 0x085f, 0x2b76, 0x1851, 0x2395, 0x1fb1, 0x0e34, 0x0052, 0x15d5, 0x0e4b, 0x3b4b, 0x3ca0, 0x3f2a, 0x1387, 0x3e96, 0x2dc0, - 0x15cd, 0x02f2, 0x056d, 0x0284, 0x1307, 0x09a7, 0x213d, 0x0140, 0x35b5, 0x0726, 0x0d41, 0x3e50, 0x2f5c, 0x0430, 0x26e6, 0x0c29, - 0x028d, 0x134d, 0x1eaf, 0x027f, 0x1bb7, 0x068d, 0x327b, 0x36fa, 0x04bd, 0x05e3, 0x30fd, 0x0507, 0x2312, 0x173c, 0x2c8b, 0x1d0b, - 0x06d3, 0x1e28, 0x0077, 0x0292, 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0x0e0b, 0x10f5, 0x36b1, 0x3411, + 0x142a, 0x2279, 0x1197, 0x0399, 0x19b5, 0x2912, 0x2927, 0x332e, + 0x2830, 0x2f10, 0x3820, 0x26c9, 0x1321, 0x1547, 0x19fe, 0x25a5, + 0x3e8b, 0x1820, 0x1786, 0x0ce5, 0x1bfb, 0x3864, 0x1ceb, 0x123b, + 0x14f8, 0x19ce, 0x0647, 0x2e95, 0x18ce, 0x37bd, 0x2259, 0x14da, + 0x235e, 0x219e, 0x1f9c, 0x2c32, 0x28f7, 0x3b05, 0x324f, 0x18b7, + 0x2624, 0x3a97, 0x3f9f, 0x1943, 0x3563, 0x07d6, 0x30b1, 0x28a9, + 0x2410, 0x1bd3, 0x0e82, 0x0ed6, 0x0404, 0x0bab, 0x2389, 0x31f8, + 0x25f9, 0x1064, 0x1f8f, 0x372f, 0x2e73, 0x3925, 0x0d15, 0x0e16, + 0x107c, 0x1e24, 0x389b, 0x3ae0, 0x085b, 0x2605, 0x1349, 0x02ee, + 0x209c, 0x3d1b, 0x12db, 0x3d0d, 0x287e, 0x2d0a, 0x0817, 0x011c, + 0x0093, 0x1da1, 0x0d2f, 0x179a, 0x0568, 0x2b8c, 0x1a2e, 0x0072, + 0x359b, 0x3044, 0x1bc6, 0x38df, 0x2709, 0x2175, 0x3f5d, 0x3ebe, + 0x0258, 0x0d96, 0x160a, 0x3bce, 0x15c4, 0x3ffb, 0x1c30, 0x3d80 }, /* "alpha_to" table */ { - 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x0443, 0x0886, - 0x110c, 0x2218, 0x0073, 0x00e6, 0x01cc, 0x0398, 0x0730, 0x0e60, 0x1cc0, 0x3980, 0x3743, 0x2ac5, 0x11c9, 0x2392, 0x0367, 0x06ce, - 0x0d9c, 0x1b38, 0x3670, 0x28a3, 0x1505, 0x2a0a, 0x1057, 0x20ae, 0x051f, 0x0a3e, 0x147c, 0x28f8, 0x15b3, 0x2b66, 0x128f, 0x251e, - 0x0e7f, 0x1cfe, 0x39fc, 0x37bb, 0x2b35, 0x1229, 0x2452, 0x0ce7, 0x19ce, 0x339c, 0x237b, 0x02b5, 0x056a, 0x0ad4, 0x15a8, 0x2b50, - 0x12e3, 0x25c6, 0x0fcf, 0x1f9e, 0x3f3c, 0x3a3b, 0x3035, 0x2429, 0x0c11, 0x1822, 0x3044, 0x24cb, 0x0dd5, 0x1baa, 0x3754, 0x2aeb, - 0x1195, 0x232a, 0x0217, 0x042e, 0x085c, 0x10b8, 0x2170, 0x06a3, 0x0d46, 0x1a8c, 0x3518, 0x2e73, 0x18a5, 0x314a, 0x26d7, 0x09ed, - 0x13da, 0x27b4, 0x0b2b, 0x1656, 0x2cac, 0x1d1b, 0x3a36, 0x302f, 0x241d, 0x0c79, 0x18f2, 0x31e4, 0x278b, 0x0b55, 0x16aa, 0x2d54, - 0x1eeb, 0x3dd6, 0x3fef, 0x3b9d, 0x3379, 0x22b1, 0x0121, 0x0242, 0x0484, 0x0908, 0x1210, 0x2420, 0x0c03, 0x1806, 0x300c, 0x245b, - 0x0cf5, 0x19ea, 0x33d4, 0x23eb, 0x0395, 0x072a, 0x0e54, 0x1ca8, 0x3950, 0x36e3, 0x2985, 0x1749, 0x2e92, 0x1967, 0x32ce, 0x21df, - 0x07fd, 0x0ffa, 0x1ff4, 0x3fe8, 0x3b93, 0x3365, 0x2289, 0x0151, 0x02a2, 0x0544, 0x0a88, 0x1510, 0x2a20, 0x1003, 0x2006, 0x044f, - 0x089e, 0x113c, 0x2278, 0x00b3, 0x0166, 0x02cc, 0x0598, 0x0b30, 0x1660, 0x2cc0, 0x1dc3, 0x3b86, 0x334f, 0x22dd, 0x01f9, 0x03f2, - 0x07e4, 0x0fc8, 0x1f90, 0x3f20, 0x3a03, 0x3045, 0x24c9, 0x0dd1, 0x1ba2, 0x3744, 0x2acb, 0x11d5, 0x23aa, 0x0317, 0x062e, 0x0c5c, - 0x18b8, 0x3170, 0x26a3, 0x0905, 0x120a, 0x2414, 0x0c6b, 0x18d6, 0x31ac, 0x271b, 0x0a75, 0x14ea, 0x29d4, 0x17eb, 0x2fd6, 0x1bef, - 0x37de, 0x2bff, 0x13bd, 0x277a, 0x0ab7, 0x156e, 0x2adc, 0x11fb, 0x23f6, 0x03af, 0x075e, 0x0ebc, 0x1d78, 0x3af0, 0x31a3, 0x2705, - 0x0a49, 0x1492, 0x2924, 0x160b, 0x2c16, 0x1c6f, 0x38de, 0x35ff, 0x2fbd, 0x1b39, 0x3672, 0x28a7, 0x150d, 0x2a1a, 0x1077, 0x20ee, - 0x059f, 0x0b3e, 0x167c, 0x2cf8, 0x1db3, 0x3b66, 0x328f, 0x215d, 0x06f9, 0x0df2, 0x1be4, 0x37c8, 0x2bd3, 0x13e5, 0x27ca, 0x0bd7, - 0x17ae, 0x2f5c, 0x1afb, 0x35f6, 0x2faf, 0x1b1d, 0x363a, 0x2837, 0x142d, 0x285a, 0x14f7, 0x29ee, 0x179f, 0x2f3e, 0x1a3f, 0x347e, - 0x2cbf, 0x1d3d, 0x3a7a, 0x30b7, 0x252d, 0x0e19, 0x1c32, 0x3864, 0x348b, 0x2d55, 0x1ee9, 0x3dd2, 0x3fe7, 0x3b8d, 0x3359, 0x22f1, - 0x01a1, 0x0342, 0x0684, 0x0d08, 0x1a10, 0x3420, 0x2c03, 0x1c45, 0x388a, 0x3557, 0x2eed, 0x1999, 0x3332, 0x2227, 0x000d, 0x001a, - 0x0034, 0x0068, 0x00d0, 0x01a0, 0x0340, 0x0680, 0x0d00, 0x1a00, 0x3400, 0x2c43, 0x1cc5, 0x398a, 0x3757, 0x2aed, 0x1199, 0x2332, - 0x0227, 0x044e, 0x089c, 0x1138, 0x2270, 0x00a3, 0x0146, 0x028c, 0x0518, 0x0a30, 0x1460, 0x28c0, 0x15c3, 0x2b86, 0x134f, 0x269e, - 0x097f, 0x12fe, 0x25fc, 0x0fbb, 0x1f76, 0x3eec, 0x399b, 0x3775, 0x2aa9, 0x1111, 0x2222, 0x0007, 0x000e, 0x001c, 0x0038, 0x0070, - 0x00e0, 0x01c0, 0x0380, 0x0700, 0x0e00, 0x1c00, 0x3800, 0x3443, 0x2cc5, 0x1dc9, 0x3b92, 0x3367, 0x228d, 0x0159, 0x02b2, 0x0564, - 0x0ac8, 0x1590, 0x2b20, 0x1203, 0x2406, 0x0c4f, 0x189e, 0x313c, 0x263b, 0x0835, 0x106a, 0x20d4, 0x05eb, 0x0bd6, 0x17ac, 0x2f58, - 0x1af3, 0x35e6, 0x2f8f, 0x1b5d, 0x36ba, 0x2937, 0x162d, 0x2c5a, 0x1cf7, 0x39ee, 0x379f, 0x2b7d, 0x12b9, 0x2572, 0x0ea7, 0x1d4e, - 0x3a9c, 0x317b, 0x26b5, 0x0929, 0x1252, 0x24a4, 0x0d0b, 0x1a16, 0x342c, 0x2c1b, 0x1c75, 0x38ea, 0x3597, 0x2f6d, 0x1a99, 0x3532, - 0x2e27, 0x180d, 0x301a, 0x2477, 0x0cad, 0x195a, 0x32b4, 0x212b, 0x0615, 0x0c2a, 0x1854, 0x30a8, 0x2513, 0x0e65, 0x1cca, 0x3994, - 0x376b, 0x2a95, 0x1169, 0x22d2, 0x01e7, 0x03ce, 0x079c, 0x0f38, 0x1e70, 0x3ce0, 0x3d83, 0x3f45, 0x3ac9, 0x31d1, 0x27e1, 0x0b81, - 0x1702, 0x2e04, 0x184b, 0x3096, 0x256f, 0x0e9d, 0x1d3a, 0x3a74, 0x30ab, 0x2515, 0x0e69, 0x1cd2, 0x39a4, 0x370b, 0x2a55, 0x10e9, - 0x21d2, 0x07e7, 0x0fce, 0x1f9c, 0x3f38, 0x3a33, 0x3025, 0x2409, 0x0c51, 0x18a2, 0x3144, 0x26cb, 0x09d5, 0x13aa, 0x2754, 0x0aeb, - 0x15d6, 0x2bac, 0x131b, 0x2636, 0x082f, 0x105e, 0x20bc, 0x053b, 0x0a76, 0x14ec, 0x29d8, 0x17f3, 0x2fe6, 0x1b8f, 0x371e, 0x2a7f, - 0x10bd, 0x217a, 0x06b7, 0x0d6e, 0x1adc, 0x35b8, 0x2f33, 0x1a25, 0x344a, 0x2cd7, 0x1ded, 0x3bda, 0x33f7, 0x23ad, 0x0319, 0x0632, - 0x0c64, 0x18c8, 0x3190, 0x2763, 0x0a85, 0x150a, 0x2a14, 0x106b, 0x20d6, 0x05ef, 0x0bde, 0x17bc, 0x2f78, 0x1ab3, 0x3566, 0x2e8f, - 0x195d, 0x32ba, 0x2137, 0x062d, 0x0c5a, 0x18b4, 0x3168, 0x2693, 0x0965, 0x12ca, 0x2594, 0x0f6b, 0x1ed6, 0x3dac, 0x3f1b, 0x3a75, - 0x30a9, 0x2511, 0x0e61, 0x1cc2, 0x3984, 0x374b, 0x2ad5, 0x11e9, 0x23d2, 0x03e7, 0x07ce, 0x0f9c, 0x1f38, 0x3e70, 0x38a3, 0x3505, - 0x2e49, 0x18d1, 0x31a2, 0x2707, 0x0a4d, 0x149a, 0x2934, 0x162b, 0x2c56, 0x1cef, 0x39de, 0x37ff, 0x2bbd, 0x1339, 0x2672, 0x08a7, - 0x114e, 0x229c, 0x017b, 0x02f6, 0x05ec, 0x0bd8, 0x17b0, 0x2f60, 0x1a83, 0x3506, 0x2e4f, 0x18dd, 0x31ba, 0x2737, 0x0a2d, 0x145a, - 0x28b4, 0x152b, 0x2a56, 0x10ef, 0x21de, 0x07ff, 0x0ffe, 0x1ffc, 0x3ff8, 0x3bb3, 0x3325, 0x2209, 0x0051, 0x00a2, 0x0144, 0x0288, - 0x0510, 0x0a20, 0x1440, 0x2880, 0x1543, 0x2a86, 0x114f, 0x229e, 0x017f, 0x02fe, 0x05fc, 0x0bf8, 0x17f0, 0x2fe0, 0x1b83, 0x3706, - 0x2a4f, 0x10dd, 0x21ba, 0x0737, 0x0e6e, 0x1cdc, 0x39b8, 0x3733, 0x2a25, 0x1009, 0x2012, 0x0467, 0x08ce, 0x119c, 0x2338, 0x0233, - 0x0466, 0x08cc, 0x1198, 0x2330, 0x0223, 0x0446, 0x088c, 0x1118, 0x2230, 0x0023, 0x0046, 0x008c, 0x0118, 0x0230, 0x0460, 0x08c0, - 0x1180, 0x2300, 0x0243, 0x0486, 0x090c, 0x1218, 0x2430, 0x0c23, 0x1846, 0x308c, 0x255b, 0x0ef5, 0x1dea, 0x3bd4, 0x33eb, 0x2395, - 0x0369, 0x06d2, 0x0da4, 0x1b48, 0x3690, 0x2963, 0x1685, 0x2d0a, 0x1e57, 0x3cae, 0x3d1f, 0x3e7d, 0x38b9, 0x3531, 0x2e21, 0x1801, - 0x3002, 0x2447, 0x0ccd, 0x199a, 0x3334, 0x222b, 0x0015, 0x002a, 0x0054, 0x00a8, 0x0150, 0x02a0, 0x0540, 0x0a80, 0x1500, 0x2a00, - 0x1043, 0x2086, 0x054f, 0x0a9e, 0x153c, 0x2a78, 0x10b3, 0x2166, 0x068f, 0x0d1e, 0x1a3c, 0x3478, 0x2cb3, 0x1d25, 0x3a4a, 0x30d7, - 0x25ed, 0x0f99, 0x1f32, 0x3e64, 0x388b, 0x3555, 0x2ee9, 0x1991, 0x3322, 0x2207, 0x004d, 0x009a, 0x0134, 0x0268, 0x04d0, 0x09a0, - 0x1340, 0x2680, 0x0943, 0x1286, 0x250c, 0x0e5b, 0x1cb6, 0x396c, 0x369b, 0x2975, 0x16a9, 0x2d52, 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0x003d, + 0x007a, 0x00f4, 0x01e8, 0x03d0, 0x07a0, 0x0f40, 0x1e80, 0x3d00, + 0x3e43, 0x38c5, 0x35c9, 0x2fd1, 0x1be1, 0x37c2, 0x2bc7, 0x13cd, + 0x279a, 0x0b77, 0x16ee, 0x2ddc, 0x1ffb, 0x3ff6, 0x3baf, 0x331d, + 0x2279, 0x00b1, 0x0162, 0x02c4, 0x0588, 0x0b10, 0x1620, 0x2c40, + 0x1cc3, 0x3986, 0x374f, 0x2add, 0x11f9, 0x23f2, 0x03a7, 0x074e, + 0x0e9c, 0x1d38, 0x3a70, 0x30a3, 0x2505, 0x0e49, 0x1c92, 0x3924, + 0x360b, 0x2855, 0x14e9, 0x29d2, 0x17e7, 0x2fce, 0x1bdf, 0x37be, + 0x2b3f, 0x123d, 0x247a, 0x0cb7, 0x196e, 0x32dc, 0x21fb, 0x07b5, + 0x0f6a, 0x1ed4, 0x3da8, 0x3f13, 0x3a65, 0x3089, 0x2551, 0x0ee1, + 0x1dc2, 0x3b84, 0x334b, 0x22d5, 0x01e9, 0x03d2, 0x07a4, 0x0f48, + 0x1e90, 0x3d20, 0x3e03, 0x3845, 0x34c9, 0x2dd1, 0x1fe1, 0x3fc2, + 0x3bc7, 0x33cd, 0x23d9, 0x03f1, 0x07e2, 0x0fc4, 0x1f88, 0x3f10, + 0x3a63, 0x3085, 0x2549, 0x0ed1, 0x1da2, 0x3b44, 0x32cb, 0x21d5, + 0x07e9, 0x0fd2, 0x1fa4, 0x3f48, 0x3ad3, 0x31e5, 0x2789, 0x0b51, + 0x16a2, 0x2d44, 0x1ecb, 0x3d96, 0x3f6f, 0x3a9d, 0x3179, 0x26b1, + 0x0921, 0x1242, 0x2484, 0x0d4b, 0x1a96, 0x352c, 0x2e1b, 0x1875, + 0x30ea, 0x2597, 0x0f6d, 0x1eda, 0x3db4, 0x3f2b, 0x3a15, 0x3069, + 0x2491, 0x0d61, 0x1ac2, 0x3584, 0x2f4b, 0x1ad5, 0x35aa, 0x2f17, + 0x1a6d, 0x34da, 0x2df7, 0x1fad, 0x3f5a, 0x3af7, 0x31ad, 0x2719, + 0x0a71, 0x14e2, 0x29c4, 0x17cb, 0x2f96, 0x1b6f, 0x36de, 0x29ff, + 0x17bd, 0x2f7a, 0x1ab7, 0x356e, 0x2e9f, 0x197d, 0x32fa, 0x21b7, + 0x072d, 0x0e5a, 0x1cb4, 0x3968, 0x3693, 0x2965, 0x1689, 0x2d12, + 0x1e67, 0x3cce, 0x3ddf, 0x3ffd, 0x3bb9, 0x3331, 0x2221, 0x0001 } }; #endif /* CONFIG_SAMA5_HAVE_PMECC && !CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_gf512.c b/arch/arm/src/sama5/sam_gf512.c index bdbbc678022..85347aa36ec 100644 --- a/arch/arm/src/sama5/sam_gf512.c +++ b/arch/arm/src/sama5/sam_gf512.c @@ -1,10 +1,12 @@ -/********************************************************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/sam_gf512.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Taken from Atmel NoOS sample code. The Atmel sample code has a BSD compatible license that requires this copyright notice: + * Taken from Atmel NoOS sample code. + * The Atmel sample code has a BSD compatible license that requires + * this copyright notice: * * Copyright (c) 2012, Atmel Corporation * @@ -35,11 +37,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - **********************************************************************************************************************************/ + ****************************************************************************/ -/********************************************************************************************************************************** +/**************************************************************************** * Included Files - **********************************************************************************************************************************/ + ****************************************************************************/ #include #include @@ -50,1046 +52,2077 @@ #if defined(CONFIG_SAMA5_HAVE_PMECC) && !defined(CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES) -/********************************************************************************************************************************** +/**************************************************************************** * Public Data - **********************************************************************************************************************************/ + ****************************************************************************/ -/* Gallois Field tables for 512 bytes sectors. First raw is "index_of" and second one is "alpha_to" */ +/* Gallois Field tables for 512 bytes sectors. + * First raw is "index_of" and second one is "alpha_to" + */ + + /* "index_of" table */ const uint16_t pmecc_gf512[2][PMECC_GF_SIZEOF_512] = { - /* "index_of" table */ { - 0xffff, 0x0000, 0x0001, 0x03a6, 0x0002, 0x074c, 0x03a7, 0x18c0, 0x0003, 0x1c66, 0x074d, 0x01ea, 0x03a8, 0x005d, 0x18c1, 0x0af2, - 0x0004, 0x0e98, 0x1c67, 0x183e, 0x074e, 0x1181, 0x01eb, 0x0403, 0x03a9, 0x119c, 0x005e, 0x000d, 0x18c2, 0x0590, 0x0af3, 0x1877, - 0x0005, 0x1c1d, 0x0e99, 0x191d, 0x1c68, 0x0d6f, 0x183f, 0x0936, 0x074f, 0x13d9, 0x1182, 0x1542, 0x01ec, 0x03b3, 0x0404, 0x1395, - 0x03aa, 0x1aaa, 0x119d, 0x123e, 0x005f, 0x1be4, 0x000e, 0x0bda, 0x18c3, 0x07a9, 0x0591, 0x1d35, 0x0af4, 0x19ae, 0x1878, 0x1527, - 0x0006, 0x18cd, 0x1c1e, 0x174b, 0x0e9a, 0x03d4, 0x191e, 0x1d54, 0x1c69, 0x057f, 0x0d70, 0x0b4f, 0x1840, 0x00dc, 0x0937, 0x0a5d, - 0x0750, 0x00ba, 0x13da, 0x1e50, 0x1183, 0x15e4, 0x1543, 0x155a, 0x01ed, 0x0f80, 0x03b4, 0x05f3, 0x0405, 0x1138, 0x1396, 0x1f8a, - 0x03ab, 0x0122, 0x1aab, 0x1fc3, 0x119e, 0x1cc3, 0x123f, 0x164b, 0x0060, 0x0cdc, 0x1be5, 0x0a42, 0x000f, 0x1eb9, 0x0bdb, 0x1115, - 0x18c4, 0x173b, 0x07aa, 0x094b, 0x0592, 0x1444, 0x1d36, 0x0759, 0x0af5, 0x10ff, 0x19af, 0x177f, 0x1879, 0x18e8, 0x1528, 0x0247, - 0x0007, 0x05ed, 0x18ce, 0x091f, 0x1c1f, 0x049b, 0x174c, 0x1c8e, 0x0e9b, 0x13ac, 0x03d5, 0x14a5, 0x191f, 0x1b25, 0x1d55, 0x1fe1, - 0x1c6a, 0x169f, 0x0580, 0x1ae1, 0x0d71, 0x0cf1, 0x0b50, 0x136b, 0x1841, 0x0aff, 0x00dd, 0x18d4, 0x0938, 0x194d, 0x0a5e, 0x17ea, - 0x0751, 0x15f6, 0x00bb, 0x04c8, 0x13db, 0x036a, 0x1e51, 0x1bbb, 0x1184, 0x19f1, 0x15e5, 0x02f2, 0x1544, 0x1a28, 0x155b, 0x006a, - 0x01ee, 0x14bb, 0x0f81, 0x126f, 0x03b5, 0x11f9, 0x05f4, 0x0260, 0x0406, 0x01b9, 0x1139, 0x1082, 0x1397, 0x0de8, 0x1f8b, 0x1674, - 0x03ac, 0x1a21, 0x0123, 0x1c73, 0x1aac, 0x1af1, 0x1fc4, 0x189b, 0x119f, 0x00fb, 0x1cc4, 0x0142, 0x1240, 0x0c56, 0x164c, 0x077a, - 0x0061, 0x0e03, 0x0cdd, 0x1309, 0x1be6, 0x18ad, 0x0a43, 0x0482, 0x0010, 0x1a61, 0x1eba, 0x0925, 0x0bdc, 0x0ef5, 0x1116, 0x0c9a, - 0x18c5, 0x0331, 0x173c, 0x1386, 0x07ab, 0x0f4a, 0x094c, 0x14de, 0x0593, 0x11de, 0x1445, 0x1326, 0x1d37, 0x0999, 0x075a, 0x1d67, - 0x0af6, 0x1ef8, 0x1100, 0x0460, 0x19b0, 0x01f7, 0x1780, 0x0340, 0x187a, 0x1900, 0x18e9, 0x0630, 0x1529, 0x0285, 0x0248, 0x198a, - 0x0008, 0x1d30, 0x05ee, 0x177a, 0x18cf, 0x107d, 0x0920, 0x062b, 0x1c20, 0x157f, 0x049c, 0x1ca6, 0x174d, 0x09d6, 0x1c8f, 0x1d92, - 0x0e9c, 0x0303, 0x13ad, 0x029f, 0x03d6, 0x0806, 0x14a6, 0x0a14, 0x1920, 0x06e6, 0x1b26, 0x1c25, 0x1d56, 0x101a, 0x1fe2, 0x059d, - 0x1c6b, 0x1a0b, 0x16a0, 0x06d7, 0x0581, 0x172c, 0x1ae2, 0x19e2, 0x0d72, 0x1884, 0x0cf2, 0x07ba, 0x0b51, 0x012a, 0x136c, 0x12f0, - 0x1842, 0x010e, 0x0b00, 0x15c3, 0x00de, 0x0f0c, 0x18d5, 0x0d3f, 0x0939, 0x043b, 0x194e, 0x1584, 0x0a5f, 0x16cc, 0x17eb, 0x0fe8, - 0x0752, 0x0339, 0x15f7, 0x1dc7, 0x00bc, 0x001a, 0x04c9, 0x0f59, 0x13dc, 0x1c41, 0x036b, 0x0d05, 0x1e52, 0x0abf, 0x1bbc, 0x1e97, - 0x1185, 0x0b20, 0x19f2, 0x0c37, 0x15e6, 0x10ef, 0x02f3, 0x0ffc, 0x1545, 0x020c, 0x1a29, 0x04a1, 0x155c, 0x04e8, 0x006b, 0x102b, - 0x01ef, 0x1040, 0x14bc, 0x0fd5, 0x0f82, 0x0852, 0x1270, 0x129b, 0x03b6, 0x0c79, 0x11fa, 0x1e07, 0x05f5, 0x0ccb, 0x0261, 0x09c0, - 0x0407, 0x056d, 0x01ba, 0x11a9, 0x113a, 0x16af, 0x1083, 0x15fe, 0x1398, 0x0828, 0x0de9, 0x1cab, 0x1f8c, 0x1b07, 0x1675, 0x1c53, - 0x03ad, 0x1eb3, 0x1a22, 0x0993, 0x0124, 0x0cc5, 0x1c74, 0x0318, 0x1aad, 0x0035, 0x1af2, 0x0179, 0x1fc5, 0x0b3a, 0x189c, 0x0841, - 0x11a0, 0x0388, 0x00fc, 0x09f9, 0x1cc5, 0x1f1f, 0x0143, 0x1ecb, 0x1241, 0x0dcc, 0x0c57, 0x1752, 0x164d, 0x184b, 0x077b, 0x14ed, - 0x0062, 0x1b90, 0x0e04, 0x0bf0, 0x0cde, 0x0e1b, 0x130a, 0x1cf3, 0x1be7, 0x0673, 0x18ae, 0x0ea5, 0x0a44, 0x1c7a, 0x0483, 0x1b98, - 0x0011, 0x0c04, 0x1a62, 0x1a45, 0x1ebb, 0x1e87, 0x0926, 0x197a, 0x0bdd, 0x1711, 0x0ef6, 0x09db, 0x1117, 0x10cf, 0x0c9b, 0x1097, - 0x18c6, 0x1a1a, 0x0332, 0x1a13, 0x173d, 0x1436, 0x1387, 0x118e, 0x07ac, 0x100c, 0x0f4b, 0x055f, 0x094d, 0x1428, 0x14df, 0x0665, - 0x0594, 0x10b6, 0x11df, 0x1861, 0x1446, 0x1615, 0x1327, 0x0423, 0x1d38, 0x0606, 0x099a, 0x1c94, 0x075b, 0x053e, 0x1d68, 0x159f, - 0x0af7, 0x0dc4, 0x1ef9, 0x199c, 0x1101, 0x086e, 0x0461, 0x0e7c, 0x19b1, 0x1f61, 0x01f8, 0x13f2, 0x1781, 0x031e, 0x0341, 0x0710, - 0x187b, 0x0410, 0x1901, 0x095b, 0x18ea, 0x1048, 0x0631, 0x1dce, 0x152a, 0x1f47, 0x0286, 0x1d97, 0x0249, 0x0698, 0x198b, 0x1e3f, - 0x0009, 0x01e6, 0x1d31, 0x153e, 0x05ef, 0x0b4b, 0x177b, 0x0a3e, 0x18d0, 0x14a1, 0x107e, 0x02ee, 0x0921, 0x013e, 0x062c, 0x1322, - 0x1c21, 0x1ca2, 0x1580, 0x07b6, 0x049d, 0x0d01, 0x1ca7, 0x1e03, 0x174e, 0x0175, 0x09d7, 0x0ea1, 0x1c90, 0x055b, 0x1d93, 0x13ee, - 0x0e9d, 0x02ea, 0x0304, 0x116a, 0x13ae, 0x1d42, 0x02a0, 0x09a8, 0x03d7, 0x1222, 0x0807, 0x116e, 0x14a7, 0x1ab3, 0x0a15, 0x0c14, - 0x1921, 0x0ab6, 0x06e7, 0x0a88, 0x1b27, 0x07dd, 0x1c26, 0x06c4, 0x1d57, 0x0bca, 0x101b, 0x0308, 0x1fe3, 0x1798, 0x059e, 0x05ae, - 0x1c6c, 0x1744, 0x1a0c, 0x1dc0, 0x16a1, 0x1db9, 0x06d8, 0x12e2, 0x0582, 0x1534, 0x172d, 0x1d46, 0x1ae3, 0x0452, 0x19e3, 0x17dc, - 0x0d73, 0x0a0b, 0x1885, 0x0ed2, 0x0cf3, 0x115c, 0x07bb, 0x17ce, 0x0b52, 0x07d3, 0x012b, 0x13b2, 0x136d, 0x0905, 0x12f1, 0x1487, - 0x1843, 0x1945, 0x010f, 0x0517, 0x0b01, 0x0f6c, 0x15c4, 0x08e4, 0x00df, 0x0b6b, 0x0f0d, 0x09ac, 0x18d6, 0x003b, 0x0d40, 0x0b75, - 0x093a, 0x1a02, 0x043c, 0x145c, 0x194f, 0x1c07, 0x1585, 0x00c3, 0x0a60, 0x07c9, 0x16cd, 0x02a4, 0x17ec, 0x0614, 0x0fe9, 0x19bb, - 0x0753, 0x0bd4, 0x033a, 0x025a, 0x15f8, 0x0d39, 0x1dc8, 0x1974, 0x00bd, 0x06be, 0x001b, 0x1226, 0x04ca, 0x1628, 0x0f5a, 0x106b, - 0x13dd, 0x0be7, 0x1c42, 0x0769, 0x036c, 0x0971, 0x0d06, 0x0ee0, 0x1e53, 0x1f01, 0x0ac0, 0x03db, 0x1bbd, 0x051f, 0x1e98, 0x0a9f, - 0x1186, 0x1893, 0x0b21, 0x146d, 0x19f3, 0x054c, 0x0c38, 0x1bf1, 0x15e7, 0x0c47, 0x10f0, 0x1172, 0x02f4, 0x1af8, 0x0ffd, 0x0e0c, - 0x1546, 0x1f16, 0x020d, 0x072e, 0x1a2a, 0x0d9f, 0x04a2, 0x122c, 0x155d, 0x0272, 0x04e9, 0x080b, 0x006c, 0x089a, 0x102c, 0x02c6, - 0x01f0, 0x143d, 0x1041, 0x16a8, 0x14bd, 0x1c00, 0x0fd6, 0x1475, 0x0f83, 0x15ad, 0x0853, 0x1ab7, 0x1271, 0x0d81, 0x129c, 0x1349, - 0x03b7, 0x065c, 0x0c7a, 0x0faa, 0x11fb, 0x1deb, 0x1e08, 0x17b9, 0x05f6, 0x1d20, 0x0ccc, 0x14ab, 0x0262, 0x1935, 0x09c1, 0x022e, - 0x0408, 0x1ef0, 0x056e, 0x1f36, 0x01bb, 0x0f96, 0x11aa, 0x05be, 0x113b, 0x009a, 0x16b0, 0x0c18, 0x1084, 0x017f, 0x15ff, 0x11c1, - 0x1399, 0x1f3e, 0x0829, 0x1b45, 0x0dea, 0x14c4, 0x1cac, 0x0021, 0x1f8d, 0x1660, 0x1b08, 0x0a19, 0x1676, 0x124b, 0x1c54, 0x1d76, - 0x03ae, 0x0058, 0x1eb4, 0x00d7, 0x1a23, 0x1b20, 0x0994, 0x0c51, 0x0125, 0x09d1, 0x0cc6, 0x0aba, 0x1c75, 0x0b35, 0x0319, 0x1423, - 0x1aae, 0x0139, 0x0036, 0x044d, 0x1af3, 0x1623, 0x017a, 0x0d7c, 0x1fc6, 0x0b30, 0x0b3b, 0x1925, 0x189d, 0x004d, 0x0842, 0x10bf, - 0x11a1, 0x0943, 0x0389, 0x1454, 0x00fd, 0x05dc, 0x09fa, 0x13c0, 0x1cc6, 0x0419, 0x1f20, 0x0a8c, 0x0144, 0x1fcb, 0x1ecc, 0x1a79, - 0x1242, 0x027c, 0x0dcd, 0x06a9, 0x0c58, 0x0645, 0x1753, 0x162e, 0x164e, 0x0dba, 0x184c, 0x06eb, 0x077c, 0x0f35, 0x14ee, 0x0bac, - 0x0063, 0x138e, 0x1b91, 0x12e9, 0x0e05, 0x0c0d, 0x0bf1, 0x1a72, 0x0cdf, 0x0fcb, 0x0e1c, 0x07e1, 0x130b, 0x192a, 0x1cf4, 0x1335, - 0x1be8, 0x1bb2, 0x0674, 0x04b4, 0x18af, 0x1969, 0x0ea6, 0x17a8, 0x0a45, 0x10e5, 0x1c7b, 0x1b2b, 0x0484, 0x1f0b, 0x1b99, 0x12b2, - 0x0012, 0x03cc, 0x0c05, 0x1db1, 0x1a63, 0x0a7d, 0x1a46, 0x0eb7, 0x1ebc, 0x1d88, 0x1e88, 0x06c8, 0x0927, 0x0b40, 0x197b, 0x1ad2, - 0x0bde, 0x1696, 0x1712, 0x0391, 0x0ef7, 0x147c, 0x09dc, 0x04d0, 0x1118, 0x0431, 0x10d0, 0x1c2a, 0x0c9c, 0x0b60, 0x1098, 0x0e4d, - 0x18c7, 0x1ff9, 0x1a1b, 0x05e7, 0x0333, 0x1d2a, 0x1a14, 0x1ead, 0x173e, 0x01e0, 0x1437, 0x0bce, 0x1388, 0x0052, 0x118f, 0x1ff3, - 0x07ad, 0x1835, 0x100d, 0x0913, 0x0f4c, 0x154f, 0x0560, 0x11ed, 0x094e, 0x19a4, 0x1429, 0x1d5b, 0x14e0, 0x0117, 0x0666, 0x1a55, - 0x0595, 0x186f, 0x10b7, 0x13e6, 0x11e0, 0x137b, 0x1862, 0x0532, 0x1447, 0x1641, 0x1616, 0x030c, 0x1328, 0x18a2, 0x0424, 0x0bf8, - 0x1d39, 0x0d66, 0x0607, 0x15b7, 0x099b, 0x1fd6, 0x1c95, 0x1071, 0x075c, 0x00b0, 0x053f, 0x101f, 0x1d69, 0x01ae, 0x15a0, 0x0c6d, - 0x0af8, 0x1195, 0x0dc5, 0x06df, 0x1efa, 0x016e, 0x199d, 0x0b29, 0x1102, 0x12ff, 0x086f, 0x179c, 0x0462, 0x10c4, 0x0e7d, 0x03c0, - 0x19b2, 0x023e, 0x1f62, 0x120e, 0x01f9, 0x0e71, 0x13f3, 0x0e65, 0x1782, 0x0f40, 0x031f, 0x1fe7, 0x0342, 0x10ab, 0x0711, 0x00a4, - 0x187c, 0x13d1, 0x0411, 0x121a, 0x1902, 0x0c2c, 0x095c, 0x088e, 0x18eb, 0x166a, 0x1049, 0x05b2, 0x0632, 0x0847, 0x1dcf, 0x0650, - 0x152b, 0x0576, 0x1f48, 0x0ec6, 0x0287, 0x0fdd, 0x1d98, 0x0f60, 0x024a, 0x13a2, 0x0699, 0x05a2, 0x198c, 0x1574, 0x1e40, 0x1495, - 0x000a, 0x183b, 0x01e7, 0x03a3, 0x1d32, 0x123b, 0x153f, 0x191a, 0x05f0, 0x1e4d, 0x0b4c, 0x1748, 0x177c, 0x0948, 0x0a3f, 0x1fc0, - 0x18d1, 0x1ade, 0x14a2, 0x091c, 0x107f, 0x126c, 0x02ef, 0x04c5, 0x0922, 0x1306, 0x013f, 0x1c70, 0x062d, 0x045d, 0x1323, 0x1383, - 0x1c22, 0x029c, 0x1ca3, 0x1777, 0x1581, 0x15c0, 0x07b7, 0x06d4, 0x049e, 0x0c34, 0x0d02, 0x1dc4, 0x1ca8, 0x11a6, 0x1e04, 0x0fd2, - 0x174f, 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0x05d1, 0x071b, 0x1a82, 0x1b5c, + 0x011a, 0x1038, 0x193d, 0x03c4, 0x0442, 0x0961, 0x1564, 0x05cc, + 0x0669, 0x1253, 0x0078, 0x15cf, 0x0fc0, 0x1f94, 0x11af, 0x082f, + 0x1a58, 0x1d17, 0x140e, 0x0e81, 0x0e42, 0x0bb5, 0x13fd, 0x1283, + 0x0598, 0x0fe3, 0x1026, 0x1c4e, 0x14e8, 0x1092, 0x159a, 0x1e3a, + 0x1872, 0x1522, 0x1f85, 0x0242, 0x17e5, 0x166f, 0x0c95, 0x1985, + 0x10ba, 0x0ba7, 0x12ad, 0x0e48, 0x1a50, 0x0c68, 0x009f, 0x1490, + 0x13e9, 0x05a9, 0x1482, 0x19b6, 0x0a9a, 0x02c1, 0x0229, 0x1d71, + 0x11e3, 0x19c4, 0x09e6, 0x08c8, 0x181d, 0x019a, 0x16df, 0x1d0a, + 0x137e, 0x1994, 0x1f2e, 0x1212, 0x1c0d, 0x18f0, 0x0378, 0x1c31, + 0x1865, 0x0e3b, 0x034a, 0x018d, 0x06f2, 0x0d12, 0x1140, 0x14ca, + 0x0535, 0x10a2, 0x0b7e, 0x1f66, 0x1fa8, 0x007f, 0x0357, 0x14fd, + 0x144a, 0x028d, 0x1bc9, 0x02ab, 0x16f1, 0x0ca4, 0x1cd4, 0x12c5, + 0x1644, 0x14d7, 0x1294, 0x0e75, 0x08dd, 0x05b7, 0x0eb0, 0x0887, + 0x1619, 0x1ee1, 0x114d, 0x0bbb, 0x0f26, 0x1ba3, 0x0c1d, 0x01d1, + 0x030f, 0x1ea4, 0x0efd, 0x01fd, 0x1129, 0x1a9b, 0x048c, 0x11cf, + 0x132b, 0x1f9c, 0x0503, 0x1cfe, 0x06ff, 0x1f79, 0x105a, 0x0b9b, + 0x18a5, 0x160d, 0x1de3, 0x0e69, 0x1955, 0x104e, 0x0812, 0x0acc, + 0x0427, 0x1b55, 0x0b94, 0x0784, 0x1e5f, 0x0a20, 0x16b5, 0x0df0, + 0x0bfb, 0x0d5d, 0x1e6f, 0x13f7, 0x0351, 0x0ad8, 0x0ade, 0x0d1f, + 0x1d3c, 0x0f66, 0x0546, 0x0f90, 0x05d6, 0x0a77, 0x1375, 0x0c26, + 0x0d69, 0x1cbd, 0x0364, 0x0f44, 0x1726, 0x084c, 0x0e15, 0x0868, + 0x060a, 0x150a, 0x08b7, 0x1403, 0x02d7, 0x02cf, 0x0184, 0x180d, + 0x15ba, 0x06a0, 0x04d6, 0x1786, 0x1cdd, 0x17f4, 0x0152, 0x1b66, + 0x099e, 0x08f7, 0x0a30, 0x0aa8, 0x0720, 0x0d2b, 0x0220, 0x008c, + 0x1fd9, 0x0839, 0x1063, 0x1feb, 0x00c9, 0x0637, 0x1ac4, 0x10d7, + 0x1c98, 0x16be, 0x128d, 0x0b12, 0x1853, 0x0860, 0x1089, 0x0027, + 0x1074, 0x1b17, 0x0474, 0x0323, 0x1fb5, 0x15d6, 0x0ae4, 0x079b, + 0x075f, 0x1d9e, 0x1356, 0x16d4, 0x1a87, 0x1b7b, 0x16e8, 0x0074, + 0x00b3, 0x0dfc, 0x0b19, 0x10af, 0x0a04, 0x0655, 0x1bab, 0x0237, + 0x0542, 0x08b3, 0x0a2c, 0x1289, 0x1352, 0x0a28, 0x11c6, 0x1ed6, + 0x1022, 0x12a9, 0x09e2, 0x0346, 0x1bc5, 0x1149, 0x04ff, 0x0b90, + 0x1d6c, 0x14f8, 0x11ca, 0x0d1a, 0x1b61, 0x0796, 0x0b8b, 0x078b, + 0x01b1, 0x1709, 0x026a, 0x00a8, 0x158b, 0x1dd4, 0x04f0, 0x127e, + 0x15a3, 0x167e, 0x1eda, 0x08ac, 0x0d8e, 0x1b0f, 0x1604, 0x1cb2, + 0x0c70, 0x1d7f, 0x175d, 0x0715, 0x0194, 0x1f73, 0x0d25, 0x0790, + 0x0afb, 0x13a8, 0x01b5, 0x19ed, 0x1a5d, 0x00f7, 0x18fc, 0x11da, + 0x1198, 0x1c62, 0x07a5, 0x13d5, 0x0f7c, 0x057b, 0x10fb, 0x0cd8, + 0x0dc8, 0x0031, 0x170d, 0x066f, 0x0602, 0x1008, 0x1f43, 0x1f5d, + 0x06e2, 0x157b, 0x0437, 0x1880, 0x0208, 0x1c3d, 0x0824, 0x0c75, + 0x1efd, 0x06ba, 0x026e, 0x0c43, 0x1d1c, 0x15a9, 0x165c, 0x0096, + 0x0171, 0x149d, 0x0bc6, 0x121e, 0x07cf, 0x1530, 0x07c5, 0x0b67, + 0x19a0, 0x01dc, 0x00ac, 0x163d, 0x0f3c, 0x12fb, 0x139e, 0x1666, + 0x0b2c, 0x09cd, 0x0db6, 0x0415, 0x10e1, 0x0fc7, 0x042d, 0x1d84, + 0x1105, 0x0250, 0x158f, 0x061b, 0x1413, 0x0e55, 0x02b6, 0x08d4, + 0x1302, 0x1e49, 0x185a, 0x0c30, 0x0fa3, 0x0ecb, 0x1207, 0x04ad, + 0x0872, 0x0d95, 0x1dd8, 0x1259, 0x0218, 0x1e14, 0x1b4a, 0x01c8, + 0x179f, 0x0ff3, 0x111e, 0x1906, 0x19d0, 0x12d0, 0x12ba, 0x1762, + 0x0465, 0x11b7, 0x04f4, 0x0c86, 0x0e86, 0x1684, 0x1b70, 0x1e66, + 0x10c7, 0x0de0, 0x01a6, 0x0892, 0x0a66, 0x1f4d, 0x08a1, 0x0d4a, + 0x0e80, 0x1d16, 0x1282, 0x0bb4, 0x15ce, 0x1252, 0x082e, 0x1f93, + 0x03c3, 0x1037, 0x05cb, 0x0960, 0x06f9, 0x1817, 0x1b5b, 0x071a, + 0x19b5, 0x05a8, 0x1d70, 0x02c0, 0x0e47, 0x0ba6, 0x148f, 0x0c67, + 0x0241, 0x1521, 0x1984, 0x166e, 0x1c4d, 0x0fe2, 0x1e39, 0x1091, + 0x1f65, 0x10a1, 0x14fc, 0x007e, 0x018c, 0x0e3a, 0x14c9, 0x0d11, + 0x1211, 0x1993, 0x1c30, 0x18ef, 0x08c7, 0x19c3, 0x1d09, 0x0199, + 0x01fc, 0x1ea3, 0x11ce, 0x1a9a, 0x0bba, 0x1ee0, 0x01d0, 0x1ba2, + 0x0e74, 0x14d6, 0x0886, 0x05b6, 0x02aa, 0x028c, 0x12c4, 0x0ca3, + 0x13f6, 0x0d5c, 0x0d1e, 0x0ad7, 0x0783, 0x1b54, 0x0def, 0x0a1f, + 0x0e68, 0x160c, 0x0acb, 0x104d, 0x1cfd, 0x1f9b, 0x0b9a, 0x1f78, + 0x1785, 0x069f, 0x1b65, 0x17f3, 0x1402, 0x1509, 0x180c, 0x02ce, + 0x0f43, 0x1cbc, 0x0867, 0x084b, 0x0f8f, 0x0f65, 0x0c25, 0x0a76, + 0x0322, 0x1b16, 0x079a, 0x15d5, 0x0b11, 0x16bd, 0x0026, 0x085f, + 0x1fea, 0x0838, 0x10d6, 0x0636, 0x0aa7, 0x08f6, 0x008b, 0x0d2a, + 0x0345, 0x12a8, 0x0b8f, 0x1148, 0x1288, 0x08b2, 0x1ed5, 0x0a27, + 0x10ae, 0x0dfb, 0x0236, 0x0654, 0x16d3, 0x1d9d, 0x0073, 0x1b7a, + 0x0714, 0x1d7e, 0x078f, 0x1f72, 0x08ab, 0x167d, 0x1cb1, 0x1b0e, + 0x00a7, 0x1708, 0x127d, 0x1dd3, 0x0d19, 0x14f7, 0x078a, 0x0795, + 0x187f, 0x157a, 0x0c74, 0x1c3c, 0x066e, 0x0030, 0x1f5c, 0x1007, + 0x13d4, 0x1c61, 0x0cd7, 0x057a, 0x19ec, 0x13a7, 0x11d9, 0x00f6, + 0x0414, 0x09cc, 0x1d83, 0x0fc6, 0x163c, 0x01db, 0x1665, 0x12fa, + 0x121d, 0x149c, 0x0b66, 0x152f, 0x0c42, 0x06b9, 0x0095, 0x15a8, + 0x1905, 0x0ff2, 0x1761, 0x12cf, 0x1258, 0x0d94, 0x01c7, 0x1e13, + 0x0c2f, 0x1e48, 0x04ac, 0x0eca, 0x061a, 0x024f, 0x08d3, 0x0e54, + 0x095f, 0x1036, 0x0719, 0x1816, 0x0bb3, 0x1d15, 0x1f92, 0x1251, + 0x0891, 0x0ddf, 0x0d49, 0x1f4c, 0x0c85, 0x11b6, 0x1e65, 0x1683, + 0x18ee, 0x1992, 0x0198, 0x19c2, 0x007d, 0x10a0, 0x0d10, 0x0e39, + 0x166d, 0x1520, 0x1090, 0x0fe1, 0x02bf, 0x05a7, 0x0c66, 0x0ba5, + 0x104c, 0x160b, 0x1f77, 0x1f9a, 0x0ad6, 0x0d5b, 0x0a1e, 0x1b53, + 0x05b5, 0x14d5, 0x0ca2, 0x028b, 0x1a99, 0x1ea2, 0x1ba1, 0x1edf, + 0x0635, 0x0837, 0x0d29, 0x08f5, 0x15d4, 0x1b15, 0x085e, 0x16bc, + 0x084a, 0x1cbb, 0x0a75, 0x0f64, 0x17f2, 0x069e, 0x02cd, 0x1508, + 0x1dd2, 0x1707, 0x0794, 0x14f6, 0x1f71, 0x1d7d, 0x1b0d, 0x167c, + 0x0653, 0x0dfa, 0x1b79, 0x1d9c, 0x1147, 0x12a7, 0x0a26, 0x08b1, + 0x152e, 0x149b, 0x15a7, 0x06b8, 0x0fc5, 0x09cb, 0x12f9, 0x01da, + 0x0579, 0x1c60, 0x00f5, 0x13a6, 0x1c3b, 0x1579, 0x1006, 0x002f, + 0x1f4b, 0x0dde, 0x1682, 0x11b5, 0x1815, 0x1035, 0x1250, 0x1d14, + 0x0ec9, 0x1e47, 0x0e53, 0x024e, 0x12ce, 0x0ff1, 0x1e12, 0x0d93, + 0x028a, 0x14d4, 0x1ede, 0x1ea1, 0x1f99, 0x160a, 0x1b52, 0x0d5a, + 0x0fe0, 0x151f, 0x0ba4, 0x05a6, 0x19c1, 0x1991, 0x0e38, 0x109f, + 0x1d9b, 0x0df9, 0x08b0, 0x12a6, 0x14f5, 0x1706, 0x167b, 0x1d7c, + 0x0f63, 0x1cba, 0x1507, 0x069d, 0x08f4, 0x0836, 0x16bb, 0x1b14, + 0x024d, 0x1e46, 0x0d92, 0x0ff0, 0x11b4, 0x0ddd, 0x1d13, 0x1034, + 0x13a5, 0x1c5f, 0x002e, 0x1578, 0x06b7, 0x149a, 0x01d9, 0x09ca, + 0x069c, 0x1cb9, 0x1b13, 0x0835, 0x12a5, 0x0df8, 0x1d7b, 0x1705, + 0x05a5, 0x151e, 0x109e, 0x1990, 0x1ea0, 0x14d3, 0x0d59, 0x1609, + 0x198f, 0x151d, 0x1608, 0x14d2, 0x0834, 0x1cb8, 0x1704, 0x0df7, + 0x1577, 0x1c5e, 0x09c9, 0x1499, 0x0fef, 0x1e45, 0x1033, 0x0ddc, + 0x1e43, 0x1c5c, 0x1cb6, 0x151b, 0x151a, 0x1c5b, 0x1c59, 0x1c5a, + 0x1498, 0x1c5d, 0x0ddb, 0x1e44, 0x14d1, 0x151c, 0x0df6, 0x1cb7 }, /* "alpha_to" table */ { - 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x001b, 0x0036, 0x006c, - 0x00d8, 0x01b0, 0x0360, 0x06c0, 0x0d80, 0x1b00, 0x161b, 0x0c2d, 0x185a, 0x10af, 0x0145, 0x028a, 0x0514, 0x0a28, 0x1450, 0x08bb, - 0x1176, 0x02f7, 0x05ee, 0x0bdc, 0x17b8, 0x0f6b, 0x1ed6, 0x1db7, 0x1b75, 0x16f1, 0x0df9, 0x1bf2, 0x17ff, 0x0fe5, 0x1fca, 0x1f8f, - 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0x003b, 0x0076, 0x00ec, + 0x01d8, 0x03b0, 0x0760, 0x0ec0, 0x1d80, 0x1b1b, 0x162d, 0x0c41, + 0x1882, 0x111f, 0x0225, 0x044a, 0x0894, 0x1128, 0x024b, 0x0496, + 0x092c, 0x1258, 0x04ab, 0x0956, 0x12ac, 0x0543, 0x0a86, 0x150c, + 0x0a03, 0x1406, 0x0817, 0x102e, 0x0047, 0x008e, 0x011c, 0x0238, + 0x0470, 0x08e0, 0x11c0, 0x039b, 0x0736, 0x0e6c, 0x1cd8, 0x19ab, + 0x134d, 0x0681, 0x0d02, 0x1a04, 0x1413, 0x083d, 0x107a, 0x00ef, + 0x01de, 0x03bc, 0x0778, 0x0ef0, 0x1de0, 0x1bdb, 0x17ad, 0x0f41, + 0x1e82, 0x1d1f, 0x1a25, 0x1451, 0x08b9, 0x1172, 0x02ff, 0x05fe, + 0x0bfc, 0x17f8, 0x0feb, 0x1fd6, 0x1fb7, 0x1f75, 0x1ef1, 0x1df9, + 0x1be9, 0x17c9, 0x0f89, 0x1f12, 0x1e3f, 0x1c65, 0x18d1, 0x11b9, + 0x0369, 0x06d2, 0x0da4, 0x1b48, 0x168b, 0x0d0d, 0x1a1a, 0x142f, + 0x0845, 0x108a, 0x010f, 0x021e, 0x043c, 0x0878, 0x10f0, 0x01fb, + 0x03f6, 0x07ec, 0x0fd8, 0x1fb0, 0x1f7b, 0x1eed, 0x1dc1, 0x1b99, + 0x1729, 0x0e49, 0x1c92, 0x193f, 0x1265, 0x04d1, 0x09a2, 0x1344, + 0x0693, 0x0d26, 0x1a4c, 0x1483, 0x091d, 0x123a, 0x046f, 0x08de, + 0x11bc, 0x0363, 0x06c6, 0x0d8c, 0x1b18, 0x162b, 0x0c4d, 0x189a, + 0x112f, 0x0245, 0x048a, 0x0914, 0x1228, 0x044b, 0x0896, 0x112c, + 0x0243, 0x0486, 0x090c, 0x1218, 0x042b, 0x0856, 0x10ac, 0x0143, + 0x0286, 0x050c, 0x0a18, 0x1430, 0x087b, 0x10f6, 0x01f7, 0x03ee, + 0x07dc, 0x0fb8, 0x1f70, 0x1efb, 0x1ded, 0x1bc1, 0x1799, 0x0f29, + 0x1e52, 0x1cbf, 0x1965, 0x12d1, 0x05b9, 0x0b72, 0x16e4, 0x0dd3, + 0x1ba6, 0x1757, 0x0eb5, 0x1d6a, 0x1acf, 0x1585, 0x0b11, 0x1622, + 0x0c5f, 0x18be, 0x1167, 0x02d5, 0x05aa, 0x0b54, 0x16a8, 0x0d4b, + 0x1a96, 0x1537, 0x0a75, 0x14ea, 0x09cf, 0x139e, 0x0727, 0x0e4e, + 0x1c9c, 0x1923, 0x125d, 0x04a1, 0x0942, 0x1284, 0x0513, 0x0a26, + 0x144c, 0x0883, 0x1106, 0x0217, 0x042e, 0x085c, 0x10b8, 0x016b, + 0x02d6, 0x05ac, 0x0b58, 0x16b0, 0x0d7b, 0x1af6, 0x15f7, 0x0bf5, + 0x17ea, 0x0fcf, 0x1f9e, 0x1f27, 0x1e55, 0x1cb1, 0x1979, 0x12e9, + 0x05c9, 0x0b92, 0x1724, 0x0e53, 0x1ca6, 0x1957, 0x12b5, 0x0571, + 0x0ae2, 0x15c4, 0x0b93, 0x1726, 0x0e57, 0x1cae, 0x1947, 0x1295, + 0x0531, 0x0a62, 0x14c4, 0x0993, 0x1326, 0x0657, 0x0cae, 0x195c, + 0x12a3, 0x055d, 0x0aba, 0x1574, 0x0af3, 0x15e6, 0x0bd7, 0x17ae, + 0x0f47, 0x1e8e, 0x1d07, 0x1a15, 0x1431, 0x0879, 0x10f2, 0x01ff, + 0x03fe, 0x07fc, 0x0ff8, 0x1ff0, 0x1ffb, 0x1fed, 0x1fc1, 0x1f99, + 0x1f29, 0x1e49, 0x1c89, 0x1909, 0x1209, 0x0409, 0x0812, 0x1024, + 0x0053, 0x00a6, 0x014c, 0x0298, 0x0530, 0x0a60, 0x14c0, 0x099b, + 0x1336, 0x0677, 0x0cee, 0x19dc, 0x13a3, 0x075d, 0x0eba, 0x1d74, + 0x1af3, 0x15fd, 0x0be1, 0x17c2, 0x0f9f, 0x1f3e, 0x1e67, 0x1cd5, + 0x19b1, 0x1379, 0x06e9, 0x0dd2, 0x1ba4, 0x1753, 0x0ebd, 0x1d7a, + 0x1aef, 0x15c5, 0x0b91, 0x1722, 0x0e5f, 0x1cbe, 0x1967, 0x12d5, + 0x05b1, 0x0b62, 0x16c4, 0x0d93, 0x1b26, 0x1657, 0x0cb5, 0x196a, + 0x12cf, 0x0585, 0x0b0a, 0x1614, 0x0c33, 0x1866, 0x10d7, 0x01b5, + 0x036a, 0x06d4, 0x0da8, 0x1b50, 0x16bb, 0x0d6d, 0x1ada, 0x15af, + 0x0b45, 0x168a, 0x0d0f, 0x1a1e, 0x1427, 0x0855, 0x10aa, 0x014f, + 0x029e, 0x053c, 0x0a78, 0x14f0, 0x09fb, 0x13f6, 0x07f7, 0x0fee, + 0x1fdc, 0x1fa3, 0x1f5d, 0x1ea1, 0x1d59, 0x1aa9, 0x1549, 0x0a89, + 0x1512, 0x0a3f, 0x147e, 0x08e7, 0x11ce, 0x0387, 0x070e, 0x0e1c, + 0x1c38, 0x186b, 0x10cd, 0x0181, 0x0302, 0x0604, 0x0c08, 0x1810, + 0x103b, 0x006d, 0x00da, 0x01b4, 0x0368, 0x06d0, 0x0da0, 0x1b40, + 0x169b, 0x0d2d, 0x1a5a, 0x14af, 0x0945, 0x128a, 0x050f, 0x0a1e, + 0x143c, 0x0863, 0x10c6, 0x0197, 0x032e, 0x065c, 0x0cb8, 0x1970, + 0x12fb, 0x05ed, 0x0bda, 0x17b4, 0x0f73, 0x1ee6, 0x1dd7, 0x1bb5, + 0x1771, 0x0ef9, 0x1df2, 0x1bff, 0x17e5, 0x0fd1, 0x1fa2, 0x1f5f, + 0x1ea5, 0x1d51, 0x1ab9, 0x1569, 0x0ac9, 0x1592, 0x0b3f, 0x167e, + 0x0ce7, 0x19ce, 0x1387, 0x0715, 0x0e2a, 0x1c54, 0x18b3, 0x117d, + 0x02e1, 0x05c2, 0x0b84, 0x1708, 0x0e0b, 0x1c16, 0x1837, 0x1075, + 0x00f1, 0x01e2, 0x03c4, 0x0788, 0x0f10, 0x1e20, 0x1c5b, 0x18ad, + 0x1141, 0x0299, 0x0532, 0x0a64, 0x14c8, 0x098b, 0x1316, 0x0637, + 0x0c6e, 0x18dc, 0x11a3, 0x035d, 0x06ba, 0x0d74, 0x1ae8, 0x15cb, + 0x0b8d, 0x171a, 0x0e2f, 0x1c5e, 0x18a7, 0x1155, 0x02b1, 0x0562, + 0x0ac4, 0x1588, 0x0b0b, 0x1616, 0x0c37, 0x186e, 0x10c7, 0x0195, + 0x032a, 0x0654, 0x0ca8, 0x1950, 0x12bb, 0x056d, 0x0ada, 0x15b4, + 0x0b73, 0x16e6, 0x0dd7, 0x1bae, 0x1747, 0x0e95, 0x1d2a, 0x1a4f, + 0x1485, 0x0911, 0x1222, 0x045f, 0x08be, 0x117c, 0x02e3, 0x05c6, + 0x0b8c, 0x1718, 0x0e2b, 0x1c56, 0x18b7, 0x1175, 0x02f1, 0x05e2, + 0x0bc4, 0x1788, 0x0f0b, 0x1e16, 0x1c37, 0x1875, 0x10f1, 0x01f9, + 0x03f2, 0x07e4, 0x0fc8, 0x1f90, 0x1f3b, 0x1e6d, 0x1cc1, 0x1999, + 0x1329, 0x0649, 0x0c92, 0x1924, 0x1253, 0x04bd, 0x097a, 0x12f4, + 0x05f3, 0x0be6, 0x17cc, 0x0f83, 0x1f06, 0x1e17, 0x1c35, 0x1871, + 0x10f9, 0x01e9, 0x03d2, 0x07a4, 0x0f48, 0x1e90, 0x1d3b, 0x1a6d, + 0x14c1, 0x0999, 0x1332, 0x067f, 0x0cfe, 0x19fc, 0x13e3, 0x07dd, + 0x0fba, 0x1f74, 0x1ef3, 0x1dfd, 0x1be1, 0x17d9, 0x0fa9, 0x1f52, + 0x1ebf, 0x1d65, 0x1ad1, 0x15b9, 0x0b69, 0x16d2, 0x0dbf, 0x1b7e, + 0x16e7, 0x0dd5, 0x1baa, 0x174f, 0x0e85, 0x1d0a, 0x1a0f, 0x1405, + 0x0811, 0x1022, 0x005f, 0x00be, 0x017c, 0x02f8, 0x05f0, 0x0be0, + 0x17c0, 0x0f9b, 0x1f36, 0x1e77, 0x1cf5, 0x19f1, 0x13f9, 0x07e9, + 0x0fd2, 0x1fa4, 0x1f53, 0x1ebd, 0x1d61, 0x1ad9, 0x15a9, 0x0b49, + 0x1692, 0x0d3f, 0x1a7e, 0x14e7, 0x09d5, 0x13aa, 0x074f, 0x0e9e, + 0x1d3c, 0x1a63, 0x14dd, 0x09a1, 0x1342, 0x069f, 0x0d3e, 0x1a7c, + 0x14e3, 0x09dd, 0x13ba, 0x076f, 0x0ede, 0x1dbc, 0x1b63, 0x16dd, + 0x0da1, 0x1b42, 0x169f, 0x0d25, 0x1a4a, 0x148f, 0x0905, 0x120a, + 0x040f, 0x081e, 0x103c, 0x0063, 0x00c6, 0x018c, 0x0318, 0x0630, + 0x0c60, 0x18c0, 0x119b, 0x032d, 0x065a, 0x0cb4, 0x1968, 0x12cb, + 0x058d, 0x0b1a, 0x1634, 0x0c73, 0x18e6, 0x11d7, 0x03b5, 0x076a, + 0x0ed4, 0x1da8, 0x1b4b, 0x168d, 0x0d01, 0x1a02, 0x141f, 0x0825, + 0x104a, 0x008f, 0x011e, 0x023c, 0x0478, 0x08f0, 0x11e0, 0x03db, + 0x07b6, 0x0f6c, 0x1ed8, 0x1dab, 0x1b4d, 0x1681, 0x0d19, 0x1a32, + 0x147f, 0x08e5, 0x11ca, 0x038f, 0x071e, 0x0e3c, 0x1c78, 0x18eb, + 0x11cd, 0x0381, 0x0702, 0x0e04, 0x1c08, 0x180b, 0x100d, 0x0001 } }; #endif /* CONFIG_SAMA5_HAVE_PMECC && !CONFIG_SAMA5_PMECC_GALOIS_ROMTABLES */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_hsmci.h b/arch/arm/src/sama5/sam_hsmci.h index 709db3f293e..bf480db300f 100644 --- a/arch/arm/src/sama5/sam_hsmci.h +++ b/arch/arm/src/sama5/sam_hsmci.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_hsmci.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_HSMCI_H #define __ARCH_ARM_SRC_SAMA5_SAM_HSMCI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -32,23 +32,23 @@ #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -59,9 +59,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sdio_initialize @@ -73,7 +73,8 @@ extern "C" * slotno - Not used. * * Returned Value: - * A reference to an SDIO interface structure. NULL is returned on failures. + * A reference to an SDIO interface structure. + * NULL is returned on failures. * ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c index 52020b718c3..b4e21158765 100644 --- a/arch/arm/src/sama5/sam_irq.c +++ b/arch/arm/src/sama5/sam_irq.c @@ -191,9 +191,9 @@ static inline size_t sam_vectorsize(void) * * Paragraph 17.8.6, Spurious Interrupt: "The Advanced Interrupt Controller * features protection against spurious interrupts. A spurious interrupt is - * defined as being the assertion of an interrupt source long enough for the - * AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This - * is most prone to occur when: + * defined as being the assertion of an interrupt source long enough for + * the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. + * This is most prone to occur when: * * o An external interrupt source is programmed in level-sensitive mode * and an active level occurs for only a short time. @@ -459,9 +459,10 @@ void up_irqinitialize(void) * This is the method used when booting from SDRAM. * * - When executing from NOR FLASH, the first level bootloader is supposed - * to provide the AXI MATRIX mapping for us at boot time base on the state - * of the BMS pin. However, I have found that in the test environments - * that I use, I cannot always be assured of that physical address mapping. + * to provide the AXI MATRIX mapping for us at boot time base on the + * state of the BMS pin. However, I have found that in the test + * environments that I use, I cannot always be assured of that physical + * address mapping. * * - If we are executing out of ISRAM, then the SAMA5 primary bootloader * probably copied us into ISRAM and set the AXI REMAP bit for us. @@ -577,18 +578,18 @@ static uint32_t *sam_decodeirq(uintptr_t base, uint32_t *regs) /* Paragraph 17.8.5 Protect Mode: "The Protect Mode permits reading the * Interrupt Vector Register without performing the associated automatic - * operations. ... Writing PROT in AIC_DCR (Debug Control Register) at 0x1 - * enables the Protect Mode. + * operations. ... Writing PROT in AIC_DCR (Debug Control Register) at + * 0x1 enables the Protect Mode. * * "When the Protect Mode is enabled, the AIC performs interrupt stacking * only when a write access is performed on the AIC_IVR. Therefore, the * Interrupt Service Routines must write (arbitrary data) to the AIC_IVR - * just after reading it. The new context of the AIC, including the value - * of the Interrupt Status Register (AIC_ISR), is updated with the current - * interrupt only when AIC_IVR is written. ..." + * just after reading it. The new context of the AIC, including the + * value of the Interrupt Status Register (AIC_ISR), is updated with the + * current interrupt only when AIC_IVR is written. ..." * - * "To summarize, in normal operating mode, the read of AIC_IVR performs the - * following operations within the AIC: + * "To summarize, in normal operating mode, the read of AIC_IVR performs + * the following operations within the AIC: * * 1. Calculates active interrupt (higher than current or spurious). * 2. Determines and returns the vector of the active interrupt. @@ -596,13 +597,14 @@ static uint32_t *sam_decodeirq(uintptr_t base, uint32_t *regs) * 4. Pushes the current priority level onto the internal stack. * 5. Acknowledges the interrupt. * - * "However, while the Protect Mode is activated, only operations 1 to 3 are - * performed when AIC_IVR is read. Operations 4 and 5 are only performed by - * the AIC when AIC_IVR is written. + * "However, while the Protect Mode is activated, only operations 1 to 3 + * are performed when AIC_IVR is read. Operations 4 and 5 are only + * performed by the AIC when AIC_IVR is written. * - * "Software that has been written and debugged using the Protect Mode runs - * correctly in Normal Mode without modification. However, in Normal Mode the - * AIC_IVR write has no effect and can be removed to optimize the code. + * "Software that has been written and debugged using the Protect Mode + * runs correctly in Normal Mode without modification. However, in Normal + * Mode the AIC_IVR write has no effect and can be removed to optimize the + * code. */ /* Write in the IVR to support Protect Mode */ @@ -786,7 +788,8 @@ static int sam_prioritize_irq(uint32_t base, int irq, int priority) irqstate_t flags; uint32_t regval; - DEBUGASSERT(irq < SAM_IRQ_NINT && (unsigned)priority <= AIC_SMR_PRIOR_MASK); + DEBUGASSERT(irq < SAM_IRQ_NINT && + (unsigned)priority <= AIC_SMR_PRIOR_MASK); if (irq < SAM_IRQ_NINT) { /* These operations must be atomic */ diff --git a/arch/arm/src/sama5/sam_isi.c b/arch/arm/src/sama5/sam_isi.c index 6f0ac246698..b5076ef51db 100644 --- a/arch/arm/src/sama5/sam_isi.c +++ b/arch/arm/src/sama5/sam_isi.c @@ -58,6 +58,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure defines the overall state of the ISI interface */ struct sam_isi_s @@ -107,6 +108,7 @@ int sam_isi_initialize(void) int ret; /* Configure PIO pins for the ISI (outputs) */ + /* Data pins */ sam_configpio(PIO_ISI_D0); @@ -144,7 +146,8 @@ int sam_isi_initialize(void) * initialized? */ - g_isi.actual = sam_pck_configure(ISI_PCKID, PCKSRC_MCK, CONFIG_ISI_MCKFREQ); + g_isi.actual = sam_pck_configure(ISI_PCKID, PCKSRC_MCK, + CONFIG_ISI_MCKFREQ); ginfo("PCK%d frequency=%d actual=%d\n", ISI_PCKID, CONFIG_ISI_MCKFREQ, g_isi.actual); diff --git a/arch/arm/src/sama5/sam_isi.h b/arch/arm/src/sama5/sam_isi.h index 0b5673e573f..418def8cd60 100644 --- a/arch/arm/src/sama5/sam_isi.h +++ b/arch/arm/src/sama5/sam_isi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_isi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,27 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_ISI_H #define __ARCH_ARM_SRC_SAMA5_SAM_ISI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_isi.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ diff --git a/arch/arm/src/sama5/sam_lcd.h b/arch/arm/src/sama5/sam_lcd.h index 8e82958d80b..1f2a8cb37ba 100644 --- a/arch/arm/src/sama5/sam_lcd.h +++ b/arch/arm/src/sama5/sam_lcd.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_lcd.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_LCDC_H #define __ARCH_ARM_SRC_SAMA5_SAM_LCDC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -35,11 +35,12 @@ #ifdef CONFIG_SAMA5_LCDC -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* These definitions provide the LCDC framebuffer memory description needed to - * remap that region to be non-cacheable and non-bufferable + ****************************************************************************/ + +/* These definitions provide the LCDC framebuffer memory description needed + * to remap that region to be non-cacheable and non-bufferable */ #if (CONFIG_SAMA5_LCDC_FB_VBASE & 0x000fffff) != 0 @@ -53,42 +54,43 @@ #define SAMA5_LCDC_FBNSECTIONS \ ((CONFIG_SAMA5_LCDC_FB_SIZE + 0x000fffff) >> 20) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ /* The SAMA5 LCD driver uses the common framebuffer interfaces declared in * include/nuttx/video/fb.h. */ -/************************************************************************************ +/**************************************************************************** * Name: sam_lcdclear * * Description: - * This is a non-standard LCD interface just for the SAMA5. Clearing the display - * in the normal way by writing a sequences of runs that covers the entire display - * can be slow. Here the display is cleared by simply setting all VRAM memory to - * the specified color. + * This is a non-standard LCD interface just for the SAMA5. Clearing the + * display in the normal way by writing a sequences of runs that covers the + * entire display can be slow. Here the display is cleared by simply + * setting all VRAM memory to the specified color. * - ************************************************************************************/ + ****************************************************************************/ void sam_lcdclear(nxgl_mxpixel_t color); -/************************************************************************************ +/**************************************************************************** * Name: sam_backlight * * Description: - * If CONFIG_SAM_LCD_BACKLIGHT is defined, then the board-specific logic must - * provide this interface to turn the backlight on and off. + * If CONFIG_SAM_LCD_BACKLIGHT is defined, then the board-specific logic + * must provide this interface to turn the backlight on and off. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM_LCD_BACKLIGHT void sam_backlight(bool blon); diff --git a/arch/arm/src/sama5/sam_lowputc.c b/arch/arm/src/sama5/sam_lowputc.c index 85c5c104325..3f9002b6edb 100644 --- a/arch/arm/src/sama5/sam_lowputc.c +++ b/arch/arm/src/sama5/sam_lowputc.c @@ -561,8 +561,9 @@ void sam_lowsetup(void) * This may limit BAUD rates for lower USART clocks. */ - putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)), - SAM_CONSOLE_VBASE + SAM_UART_BRGR_OFFSET); + putreg32(((SAM_USART_CLOCK + + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)), + SAM_CONSOLE_VBASE + SAM_UART_BRGR_OFFSET); /* Enable receiver & transmitter */ @@ -576,7 +577,8 @@ void sam_lowsetup(void) /* Reset and disable receiver and transmitter */ - putreg32((FLEXUS_CR_RSTRX | FLEXUS_CR_RSTTX | FLEXUS_CR_RXDIS | FLEXUS_CR_TXDIS), + putreg32((FLEXUS_CR_RSTRX | FLEXUS_CR_RSTTX | + FLEXUS_CR_RXDIS | FLEXUS_CR_TXDIS), SAM_CONSOLE_VBASE + SAM_FLEXUS_CR_OFFSET); /* Disable all interrupts */ @@ -591,7 +593,8 @@ void sam_lowsetup(void) * This may limit BAUD rates for lower USART clocks. */ - putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)), + putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / + (SAM_CONSOLE_BAUD << 4)), SAM_CONSOLE_VBASE + SAM_FLEXUS_BRGR_OFFSET); /* Enable receiver & transmitter */ diff --git a/arch/arm/src/sama5/sam_memorymap.c b/arch/arm/src/sama5/sam_memorymap.c index 1eaf70350cd..95393feff49 100644 --- a/arch/arm/src/sama5/sam_memorymap.c +++ b/arch/arm/src/sama5/sam_memorymap.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_memorymap.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ /* chip.h holds the characteristics of the configured chip */ @@ -38,3 +38,7 @@ #else # error Unrecognized SAMA5 family #endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_memorymap.h b/arch/arm/src/sama5/sam_memorymap.h index 8cc49a1d707..cfbc04c6ab2 100644 --- a/arch/arm/src/sama5/sam_memorymap.h +++ b/arch/arm/src/sama5/sam_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMA5_SAM_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "mmu.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* The vectors are, by default, positioned at the beginning of the text * section. Under what conditions do we have to remap these vectors? @@ -48,8 +48,8 @@ * is required because the vectors are position at the beginning of the * boot memory at link time and no additional MMU mapping required. * - * 2) We are not using a ROM page table. We cannot set any custom mappings in - * the case and the build must conform to the ROM page table properties + * 2) We are not using a ROM page table. We cannot set any custom mappings + * in the case and the build must conform to the ROM page table properties */ #if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_ARCH_ROMPGTABLE) @@ -74,11 +74,11 @@ # define NEED_SDRAM_REMAPPING 1 #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ - /* This table describes how to map a set of 1Mb pages to space the physical +/* This table describes how to map a set of 1Mb pages to space the physical * address space of the SAMA5. */ diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index 467fd8d544e..8ea76ccbf47 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -422,7 +422,9 @@ static int nand_operation_complete(struct sam_nandcs_s *priv) nand_nfc_cleale(priv, 0, COMMAND_STATUS, 0, 0, 0); status = READ_DATA8(&priv->raw); - /* On successful completion, the NAND will be READY with no ERROR conditions */ + /* On successful completion, + * the NAND will be READY with no ERROR conditions + */ if ((status & STATUS_ERROR) != 0) { @@ -738,7 +740,9 @@ static void nand_setup_cmddone(struct sam_nandcs_s *priv) nand_putreg(SAM_HSMC_IER, HSMC_NFCINT_CMDDONE); leave_critical_section(flags); #else - /* Just sample and clear any pending NFC status, then clear CMDDONE status */ + /* Just sample and clear any pending NFC status, + * then clear CMDDONE status + */ nand_nfc_poll(); g_nand.cmddone = false; @@ -824,7 +828,9 @@ static void nand_setup_xfrdone(struct sam_nandcs_s *priv) nand_putreg(SAM_HSMC_IER, HSMC_NFCINT_XFRDONE); leave_critical_section(flags); #else - /* Just sample and clear any pending NFC status, then clear XFRDONE status */ + /* Just sample and clear any pending NFC status, + * then clear XFRDONE status + */ nand_nfc_poll(); g_nand.xfrdone = false; @@ -910,7 +916,9 @@ static void nand_setup_rbedge(struct sam_nandcs_s *priv) nand_putreg(SAM_HSMC_IER, HSMC_NFCINT_RBEDGE0); leave_critical_section(flags); #else - /* Just sample and clear any pending NFC status, then clear RBEDGE0 status */ + /* Just sample and clear any pending NFC status, + * then clear RBEDGE0 status + */ nand_nfc_poll(); g_nand.rbedge = false; @@ -2863,7 +2871,9 @@ struct mtd_dev_s *sam_nand_initialize(int cs) finfo("CS%d\n", cs); - /* Select the device structure (In SAMA5D3, NAND is only supported on CS3). */ + /* Select the device structure + * (In SAMA5D3, NAND is only supported on CS3). + */ #ifdef CONFIG_SAMA5_EBICS0_NAND if (cs == HSMC_CS0) diff --git a/arch/arm/src/sama5/sam_nand.h b/arch/arm/src/sama5/sam_nand.h index b61e04dccda..20a9980d5af 100644 --- a/arch/arm/src/sama5/sam_nand.h +++ b/arch/arm/src/sama5/sam_nand.h @@ -44,7 +44,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* DMA. DMA support requires that DMAC0 be enabled. According to * "Table 15-2. SAMA5 Master to Slave Access", DMAC1 does not have access * to NFC SRAM. @@ -76,7 +78,6 @@ # endif #endif - /* Hardware ECC types. These are extensions to the NANDECC_HWECC value * defined in include/nuttx/mtd/nand_raw.h. * @@ -88,6 +89,7 @@ #define NANDECC_PMECC (NANDECC_HWECC + 1) /* Per NAND bank ECC selections */ + /* Only CS3 can support NAND. The rest is a fantasy */ # undef CONFIG_SAMA5_EBICS0_NAND @@ -278,6 +280,7 @@ /**************************************************************************** * Public Types ****************************************************************************/ + /* This type represents the state of a raw NAND MTD device on a single chip * select. The struct nand_raw_s must appear at the beginning of the * definition so that you can freely cast between pointers to struct @@ -343,10 +346,10 @@ struct sam_nand_s #ifdef CONFIG_SAMA5_NAND_REGDEBUG /* Register debug state */ - bool wr; /* Last was a write */ - uint32_t regadddr; /* Last address */ - uint32_t regval; /* Last value */ - int ntimes; /* Number of times */ + bool wr; /* Last was a write */ + uint32_t regadddr; /* Last address */ + uint32_t regval; /* Last value */ + int ntimes; /* Number of times */ #endif }; @@ -370,7 +373,7 @@ extern "C" EXTERN struct sam_nand_s g_nand; /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** @@ -471,7 +474,8 @@ void board_nand_ce(int cs, bool enable); * Name: nand_checkreg * * Description: - * Check if the current HSMC register access is a duplicate of the preceding. + * Check if the current HSMC register access is a duplicate of the + * preceding. * * Input Parameters: * regval - The value to be written @@ -543,7 +547,8 @@ static inline void nand_putreg(uintptr_t regaddr, uint32_t regval) ****************************************************************************/ #ifdef CONFIG_SAMA5_PMECC_TRIMPAGE -static inline void nand_trimffs_enable(struct sam_nandcs_s *priv, bool enable) +static inline void nand_trimffs_enable(struct sam_nandcs_s *priv, + bool enable) { priv->dropjss = enable; } @@ -588,7 +593,8 @@ static inline bool nand_trrimffs(struct sam_nandcs_s *priv) ****************************************************************************/ #ifdef CONFIG_SAMA5_PMECC_TRIMPAGE -static inline void nand_set_trimpage(struct sam_nandcs_s *priv, uint16_t page) +static inline void nand_set_trimpage(struct sam_nandcs_s *priv, + uint16_t page) { priv->trimpage = page; } diff --git a/arch/arm/src/sama5/sam_oneshot.c b/arch/arm/src/sama5/sam_oneshot.c index 07243dcb99b..2a3ffff9a7d 100644 --- a/arch/arm/src/sama5/sam_oneshot.c +++ b/arch/arm/src/sama5/sam_oneshot.c @@ -244,7 +244,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); - *usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch); + *usec = (0xffffull * USEC_PER_SEC) / + (uint64_t)sam_tc_divfreq(oneshot->tch); return OK; } @@ -278,7 +279,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, irqstate_t flags; tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", - handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + handler, arg, (unsigned long)ts->tv_sec, + (unsigned long)ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); /* Was the oneshot already running? */ @@ -299,9 +301,12 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, /* Express the delay in microseconds */ - usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); + usec = (uint64_t)ts->tv_sec * + USEC_PER_SEC + (uint64_t)(ts->tv_nsec / + NSEC_PER_USEC); - /* Get the timer counter frequency and determine the number of counts need to achieve the requested delay. + /* Get the timer counter frequency and determine the number of counts + * need to achieve the requested delay. * * frequency = ticks / second * ticks = seconds * frequency @@ -343,8 +348,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, * of the oneshot timer/counter. * * The function up_timer_gettime() could also be used for this but it takes - * too long. If up_timer_gettime() is called within this function the problem - * vanishes at least if compiled with no optimisation. + * too long. If up_timer_gettime() is called within this function the + * problem vanishes at least if compiled with no optimisation. */ if (freerun != NULL) diff --git a/arch/arm/src/sama5/sam_oneshot_lowerhalf.c b/arch/arm/src/sama5/sam_oneshot_lowerhalf.c index 7eff2854364..d6f524a5f7d 100644 --- a/arch/arm/src/sama5/sam_oneshot_lowerhalf.c +++ b/arch/arm/src/sama5/sam_oneshot_lowerhalf.c @@ -41,7 +41,9 @@ * Private Types ****************************************************************************/ -/* This structure describes the state of the oneshot timer lower-half driver */ +/* This structure describes the state of the oneshot timer lower-half + * driver + */ struct sam_oneshot_lowerhalf_s { diff --git a/arch/arm/src/sama5/sam_pck.c b/arch/arm/src/sama5/sam_pck.c index 2997ec2aebe..1067b5726ea 100644 --- a/arch/arm/src/sama5/sam_pck.c +++ b/arch/arm/src/sama5/sam_pck.c @@ -99,7 +99,7 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc, * MAINCK,or SCK are supported here. */ - switch (clksrc) + switch (clksrc) { case PCKSRC_MCK: /* Source clock = MCK or PLLACK */ { @@ -141,7 +141,9 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc, } #ifdef SAMA5_HAVE_PCK_INT_PRES - /* Programmable Clock frequency is selected clock frequency divided by PRES + 1 */ + /* Programmable Clock frequency is selected clock frequency divided by + * PRES + 1 + */ pres = clkin / frequency; if (pres < 1) diff --git a/arch/arm/src/sama5/sam_pck.h b/arch/arm/src/sama5/sam_pck.h index a88fa817270..246c8351cff 100644 --- a/arch/arm/src/sama5/sam_pck.h +++ b/arch/arm/src/sama5/sam_pck.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_pck.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,27 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_PCK_H #define __ARCH_ARM_SRC_SAMA5_SAM_PCK_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* Identifies the programmable clock */ enum pckid_e @@ -53,9 +54,9 @@ enum pckid_clksrc_e PCKSRC_SCK /* Source clock is the slow clock (SCK) */ }; -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ diff --git a/arch/arm/src/sama5/sam_periphclks.h b/arch/arm/src/sama5/sam_periphclks.h index 6d47259af40..41c0c45b3a5 100644 --- a/arch/arm/src/sama5/sam_periphclks.h +++ b/arch/arm/src/sama5/sam_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAMA5_SAM_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ /* chip.h holds the characteristics of the configured chip */ diff --git a/arch/arm/src/sama5/sam_pgalloc.c b/arch/arm/src/sama5/sam_pgalloc.c index 567154c8409..97aac1001cb 100644 --- a/arch/arm/src/sama5/sam_pgalloc.c +++ b/arch/arm/src/sama5/sam_pgalloc.c @@ -42,6 +42,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Currently, page cache memory must be allocated in DRAM. There are other * possibilities, but the logic in this file will have to extended in order * handle any other possibility. @@ -121,7 +122,8 @@ uintptr_t sam_virtpgaddr(uintptr_t paddr) * The correct solutions is complex and, perhaps, will never be needed. */ - poolstart = ((uintptr_t)SAM_DDRCS_PSECTION + CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET); + poolstart = ((uintptr_t)SAM_DDRCS_PSECTION + + CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET); poolend = poolstart + CONFIG_SAMA5_DDRCS_PGHEAP_SIZE; if (paddr >= poolstart && paddr < poolend) diff --git a/arch/arm/src/sama5/sam_pio.c b/arch/arm/src/sama5/sam_pio.c index 61cc0f97b9e..497107c4ed9 100644 --- a/arch/arm/src/sama5/sam_pio.c +++ b/arch/arm/src/sama5/sam_pio.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_pio.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ /* chip.h holds the characteristics of the configured chip */ @@ -36,3 +36,7 @@ #else # error Unrecognized SAMA5 family #endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_pio.h b/arch/arm/src/sama5/sam_pio.h index b243d1dfa36..fc1620fc54e 100644 --- a/arch/arm/src/sama5/sam_pio.h +++ b/arch/arm/src/sama5/sam_pio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_PIO_H #define __ARCH_ARM_SRC_SAMA5_SAM_PIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -34,10 +34,6 @@ #include "hardware/sam_memorymap.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - /* Definitions and types customized for each SAMA5Dx family */ #if defined(ATSAMA5D2) @@ -48,9 +44,13 @@ # error Unrecognized SAMA5 architecture #endif -/************************************************************************************ +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Lookup for non-secure PIOs */ @@ -64,15 +64,15 @@ extern const uintptr_t g_spiobase[SAM_NPIO]; # define sam_spion_vbase(n) (g_spiobase[(n)]) #endif -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -83,17 +83,18 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_pioirqinitialize * * Description: - * Initialize logic to support a second level of interrupt decoding for PIO pins. + * Initialize logic to support a second level of interrupt decoding for PIO + * pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMA5_PIO_IRQ void sam_pioirqinitialize(void); @@ -101,43 +102,43 @@ void sam_pioirqinitialize(void); # define sam_pioirqinitialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_configpio * * Description: * Configure a PIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int sam_configpio(pio_pinset_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: sam_piowrite * * Description: * Write one or zero to the selected PIO pin * - ************************************************************************************/ + ****************************************************************************/ void sam_piowrite(pio_pinset_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: sam_pioread * * Description: * Read one or zero from the selected PIO pin * - ************************************************************************************/ + ****************************************************************************/ bool sam_pioread(pio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: sam_pioirq * * Description: * Configure an interrupt for the specified PIO pin. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMA5_PIO_IRQ void sam_pioirq(pio_pinset_t pinset); @@ -145,13 +146,13 @@ void sam_pioirq(pio_pinset_t pinset); # define sam_pioirq(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_pioirqenable * * Description: * Enable the interrupt for specified PIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMA5_PIO_IRQ void sam_pioirqenable(int irq); @@ -159,13 +160,13 @@ void sam_pioirqenable(int irq); # define sam_pioirqenable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_pioirqdisable * * Description: * Disable the interrupt for specified PIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMA5_PIO_IRQ void sam_pioirqdisable(int irq); @@ -173,30 +174,33 @@ void sam_pioirqdisable(int irq); # define sam_pioirqdisable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_pio_forceclk * * Description: - * Enable PIO clocking. This logic is overly conservative and does not enable PIO - * clocking unless necessary (PIO input selected, glitch/filtering enable, or PIO - * interrupts enabled). There are, however, certain conditions were we may want - * for force the PIO clock to be enabled. An example is reading the input value - * from an open drain output. + * Enable PIO clocking. + * This logic is overly conservative and does not enable PIO clocking unless + * necessary (PIO input selected, glitch/filtering enable, or PIO interrupts + * enabled). There are, however, certain conditions were we may want for + * force the PIO clock to be enabled. An example is reading the input value + * from an open drain output. * - * The PIO automatic enable/disable logic is not smart enough enough to know about - * these cases. For those cases, sam_pio_forceclk() is provided. + * The PIO automatic enable/disable logic is not smart enough enough to know + * about these cases. + * For those cases, sam_pio_forceclk() is provided. * - ************************************************************************************/ + ****************************************************************************/ void sam_pio_forceclk(pio_pinset_t pinset, bool enable); -/************************************************************************************ +/**************************************************************************** * Function: sam_dumppio * * Description: - * Dump all PIO registers associated with the base address of the provided pinset. + * Dump all PIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumppio(uint32_t pinset, const char *msg); diff --git a/arch/arm/src/sama5/sam_pmc.c b/arch/arm/src/sama5/sam_pmc.c index b72c66624d1..687c49de204 100644 --- a/arch/arm/src/sama5/sam_pmc.c +++ b/arch/arm/src/sama5/sam_pmc.c @@ -193,12 +193,14 @@ uint32_t sam_pck_frequency(uint32_t mainclk) switch (regval & PMC_MCKR_CSS_MASK) { case PMC_MCKR_CSS_MAIN: /* Main Clock */ + /* Use the Main Clock frequency */ pck = mainclk; break; case PMC_MCKR_CSS_PLLA: /* PLLA Clock */ + /* Use the PLLA output clock */ pck = sam_plladiv2_frequency(mainclk); @@ -254,7 +256,9 @@ uint32_t sam_mck_frequency(uint32_t mainclk) return 0; } - /* MDIV = n: Master Clock is Prescaler Output Clock divided by encoded value */ + /* MDIV = n: + * Master Clock is Prescaler Output Clock divided by encoded value + */ regval = getreg32(SAM_PMC_MCKR); switch (regval & PMC_MCKR_MDIV_MASK) diff --git a/arch/arm/src/sama5/sam_pmc.h b/arch/arm/src/sama5/sam_pmc.h index 449dba82f41..14d63c91b8b 100644 --- a/arch/arm/src/sama5/sam_pmc.h +++ b/arch/arm/src/sama5/sam_pmc.h @@ -43,7 +43,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index 2d6be3d53a3..4a525d3a4fa 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -49,6 +49,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_DEBUG_PWM_INFO @@ -246,6 +247,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* Channel clock sources */ enum pwm_clksrc_e @@ -294,20 +296,24 @@ struct sam_pwm_s /**************************************************************************** * Static Function Prototypes ****************************************************************************/ + /* Register access */ #ifdef CONFIG_SAMA5_PWM_REGDEBUG -static bool pwm_checkreg(FAR struct sam_pwm_s *chan, bool wr, uint32_t regval, +static bool pwm_checkreg(FAR struct sam_pwm_s *chan, + bool wr, uint32_t regval, uintptr_t regaddr); #else # define pwm_checkreg(chan,wr,regval,regaddr) (false) #endif static uint32_t pwm_getreg(FAR struct sam_pwm_chan_s *chan, int offset); -static void pwm_putreg(FAR struct sam_pwm_chan_s *chan, int offset, uint32_t regval); +static void pwm_putreg(FAR struct sam_pwm_chan_s *chan, + int offset, uint32_t regval); #ifdef CONFIG_DEBUG_PWM_INFO -static void pwm_dumpregs(FAR struct sam_pwm_chan_s *chan, FAR const char *msg); +static void pwm_dumpregs(FAR struct sam_pwm_chan_s *chan, + FAR const char *msg); #else # define pwm_dumpregs(chan,msg) #endif @@ -340,6 +346,7 @@ static void pwm_resetpins(FAR struct sam_pwm_chan_s *chan); /**************************************************************************** * Private Data ****************************************************************************/ + /* This is the list of lower half PWM driver methods used by the upper * half driver */ @@ -953,8 +960,10 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, case PWM_CLKSRC_CLKA: { regval = pwm_getreg(chan, SAM_PWM_CLK_OFFSET); - prelog2 = (unsigned int)((regval & PWM_CLK_PREA_MASK) >> PWM_CLK_PREA_SHIFT); - div = (unsigned int)((regval & PWM_CLK_DIVA_MASK) >> PWM_CLK_DIVA_SHIFT); + prelog2 = (unsigned int)((regval & PWM_CLK_PREA_MASK) >> + PWM_CLK_PREA_SHIFT); + div = (unsigned int)((regval & PWM_CLK_DIVA_MASK) >> + PWM_CLK_DIVA_SHIFT); mck = BOARD_MCK_FREQUENCY; fsrc = pwm_clk_frequency(mck, prelog2, div); regval = PWM_CMR_CPRE_CLKA; @@ -966,8 +975,10 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, case PWM_CLKSRC_CLKB: { regval = pwm_getreg(chan, SAM_PWM_CLK_OFFSET); - prelog2 = (unsigned int)((regval & PWM_CLK_PREB_MASK) >> PWM_CLK_PREB_SHIFT); - div = (unsigned int)((regval & PWM_CLK_DIVB_MASK) >> PWM_CLK_DIVB_SHIFT); + prelog2 = (unsigned int)((regval & PWM_CLK_PREB_MASK) >> + PWM_CLK_PREB_SHIFT); + div = (unsigned int)((regval & PWM_CLK_DIVB_MASK) >> + PWM_CLK_DIVB_SHIFT); mck = BOARD_MCK_FREQUENCY; fsrc = pwm_clk_frequency(mck, prelog2, div); regval = PWM_CMR_CPRE_CLKB; @@ -976,7 +987,8 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, #endif default: - pwmerr("ERROR: Invalid or unsupported clock source value: %d\n", chan->clksrc); + pwmerr("ERROR: Invalid or unsupported clock source value: %d\n", + chan->clksrc); return -EINVAL; } @@ -1081,7 +1093,8 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) * ****************************************************************************/ -static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) +static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO FAR struct sam_pwm_chan_s *chan = (FAR struct sam_pwm_chan_s *)dev; @@ -1296,6 +1309,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) { #ifdef CONFIG_SAMA5_PWM_CHAN0 case 0: + /* Select the Channel 0 interface */ chan = &g_pwm_chan0; @@ -1304,6 +1318,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) #ifdef CONFIG_SAMA5_PWM_CHAN1 case 1: + /* Select the Channel 1 interface */ chan = &g_pwm_chan1; @@ -1312,6 +1327,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) #ifdef CONFIG_SAMA5_PWM_CHAN2 case 2: + /* Select the Channel 2 interface */ chan = &g_pwm_chan2; @@ -1320,6 +1336,7 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) #ifdef CONFIG_SAMA5_PWM_CHAN3 case 3: + /* Select the Channel 3 interface */ chan = &g_pwm_chan3; @@ -1353,8 +1370,10 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) #ifdef CONFIG_SAMA5_PWM_CLKA /* Set clock A configuration */ - prelog2 = pwm_clk_prescaler_log2(mck, CONFIG_SAMA5_PWM_CLKA_FREQUENCY); - div = pwm_clk_divider(mck, CONFIG_SAMA5_PWM_CLKA_FREQUENCY, prelog2); + prelog2 = pwm_clk_prescaler_log2(mck, + CONFIG_SAMA5_PWM_CLKA_FREQUENCY); + div = pwm_clk_divider(mck, + CONFIG_SAMA5_PWM_CLKA_FREQUENCY, prelog2); regval = (PWM_CLK_DIVA(div) | PWM_CLK_PREA_DIV(prelog2)); #else regval = 0; @@ -1363,8 +1382,10 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) #ifdef CONFIG_SAMA5_PWM_CLKB /* Set clock B configuration */ - prelog2 = pwm_clk_prescaler_log2(mck, CONFIG_SAMA5_PWM_CLKB_FREQUENCY); - div = pwm_clk_divider(mck, CONFIG_SAMA5_PWM_CLKA_FREQUENCY, prelog2); + prelog2 = pwm_clk_prescaler_log2(mck, + CONFIG_SAMA5_PWM_CLKB_FREQUENCY); + div = pwm_clk_divider(mck, + CONFIG_SAMA5_PWM_CLKA_FREQUENCY, prelog2); regval |= (PWM_CLK_DIVB(div) | PWM_CLK_PREB_DIV(prelog2)); #endif @@ -1383,7 +1404,6 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) { pwmerr("ERROR: Failed to attach IRQ%d\n", channel); return NULL; - } #endif diff --git a/arch/arm/src/sama5/sam_pwm.h b/arch/arm/src/sama5/sam_pwm.h index 39c2090930f..2591456396a 100644 --- a/arch/arm/src/sama5/sam_pwm.h +++ b/arch/arm/src/sama5/sam_pwm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_pwm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_PWM_H #define __ARCH_ARM_SRC_SAMA5_SAM_PWM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -32,12 +32,15 @@ #ifdef CONFIG_SAMA5_PWM -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ -/* Do we have any PWM channels enabled? If not, then why is the PWM enabled? */ +/* Configuration ************************************************************/ + +/* Do we have any PWM channels enabled? + * If not, then why is the PWM enabled? + */ #if !defined(CONFIG_SAMA5_PWM_CHAN0) && !defined(CONFIG_SAMA5_PWM_CHAN1) && \ !defined(CONFIG_SAMA5_PWM_CHAN2) && !defined(CONFIG_SAMA5_PWM_CHAN3) @@ -45,13 +48,13 @@ # undef CONFIG_SAMA5_PWM #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -64,9 +67,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ /**************************************************************************** * Name: sam_pwminitialize diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c index 1ba4290fdbd..ab7cec3926a 100644 --- a/arch/arm/src/sama5/sam_rtc.c +++ b/arch/arm/src/sama5/sam_rtc.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_rtc.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -42,10 +42,12 @@ #ifdef CONFIG_RTC -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ + /* This RTC implementation supports only date/time RTC hardware */ #ifndef CONFIG_RTC_DATETIME @@ -62,9 +64,9 @@ #define RTC_MAGIC 0xdeadbeef -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ /* Callback to use when the alarm expires */ @@ -73,18 +75,19 @@ static alarmcb_t g_alarmcb; struct work_s g_alarmwork; #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /* g_rtc_enabled is set true after the RTC has successfully initialized */ volatile bool g_rtc_enabled = false; -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ -/************************************************************************************ + ****************************************************************************/ + +/**************************************************************************** * Name: rtc_dumpregs * * Description: @@ -96,7 +99,7 @@ volatile bool g_rtc_enabled = false; * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) @@ -116,7 +119,7 @@ static void rtc_dumpregs(FAR const char *msg) # define rtc_dumpregs(msg) #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_dumptime * * Description: @@ -128,7 +131,7 @@ static void rtc_dumpregs(FAR const char *msg) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) @@ -145,7 +148,7 @@ static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) # define rtc_dumptime(tp, msg) #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_bin2bcd * * Description: @@ -157,7 +160,7 @@ static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) * Returned Value: * The value in BCD representation * - ************************************************************************************/ + ****************************************************************************/ static uint32_t rtc_bin2bcd(int value) { @@ -172,7 +175,7 @@ static uint32_t rtc_bin2bcd(int value) return (msbcd << 4) | value; } -/************************************************************************************ +/**************************************************************************** * Name: rtc_bin2bcd * * Description: @@ -184,7 +187,7 @@ static uint32_t rtc_bin2bcd(int value) * Returned Value: * The value in binary representation * - ************************************************************************************/ + ****************************************************************************/ static int rtc_bcd2bin(uint32_t value) { @@ -192,7 +195,7 @@ static int rtc_bcd2bin(uint32_t value) return (int)(tens + (value & 0x0f)); } -/************************************************************************************ +/**************************************************************************** * Name: rtc_worker * * Description: @@ -204,7 +207,7 @@ static int rtc_bcd2bin(uint32_t value) * Returned Value: * Zero (OK) on success; A negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM static void rtc_worker(FAR void *arg) @@ -224,7 +227,7 @@ static void rtc_worker(FAR void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_interrupt * * Description: @@ -237,7 +240,7 @@ static void rtc_worker(FAR void *arg) * Returned Value: * Zero (OK) on success; A negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM static int rtc_interrupt(int irq, void *context, FAR void *arg) @@ -264,16 +267,16 @@ static int rtc_interrupt(int irq, void *context, FAR void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_initialize * * Description: - * Initialize the hardware RTC per the selected configuration. This function is - * called once during the OS initialization sequence + * Initialize the hardware RTC per the selected configuration. This + * function is called once during the OS initialization sequence * * Input Parameters: * None @@ -281,7 +284,7 @@ static int rtc_interrupt(int irq, void *context, FAR void *arg) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_initialize(void) { @@ -289,9 +292,9 @@ int up_rtc_initialize(void) rtc_dumpregs("On reset"); - /* No clocking setup need be performed. The Real-time Clock is continuously clocked - * at 32768 Hz (SCLK). The Power Management Controller has no effect on RTC - * behavior. + /* No clocking setup need be performed. + * The Real-time Clock is continuously clocked at 32768 Hz (SCLK). + * The Power Management Controller has no effect on RTC behavior. */ /* Set the 24 hour format */ @@ -308,9 +311,9 @@ int up_rtc_initialize(void) irq_attach(SAM_PID_SYS, rtc_interrupt, NULL); - /* Should RTC alarm interrupt be enabled at the peripheral? Let's assume so - * for now. Let's say yes if the time is valid and a valid alarm has been - * programmed. + /* Should RTC alarm interrupt be enabled at the peripheral? Let's + * assume so for now. Let's say yes if the time is valid and a valid + * alarm has been programmed. */ if (g_rtc_enabled && (ver & (RTC_VER_NVTIMALR | RTC_VER_NVCALALR)) == 0) @@ -336,20 +339,21 @@ int up_rtc_initialize(void) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_getdatetime * * Description: * Get the current date and time from the date/time RTC. This interface * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME - * are selected (and CONFIG_RTC_HIRES is not). + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. That - * sub-second accuracy is lost in this interface. However, since the system time - * is reinitialized on each power-up/reset, there will be no timing inaccuracy in - * the long run. + * NOTE: + * Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is lost in this interface. However, since + * the system time is reinitialized on each power-up/reset, there will + * be no timing inaccuracy in the long run. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -357,7 +361,7 @@ int up_rtc_initialize(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_getdatetime(FAR struct tm *tp) { @@ -367,9 +371,10 @@ int up_rtc_getdatetime(FAR struct tm *tp) uint32_t year; uint32_t tmp; - /* Sample the data time registers. There is a race condition here... If we sample - * the time just before midnight on December 31, the date could be wrong because - * the day rolled over while were sampling. + /* Sample the data time registers. + * There is a race condition here... If we sample the time just before + * midnight on December 31, the date could be wrong because the day rolled + * over while were sampling. */ do @@ -430,12 +435,13 @@ int up_rtc_getdatetime(FAR struct tm *tp) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_settime * * Description: - * Set the RTC to the provided time. All RTC implementations must be able to - * set their time based on a standard timespec. + * Set the RTC to the provided time. + * All RTC implementations must be able to set their time based on a + * standard timespec. * * Input Parameters: * tp - the time to use @@ -443,7 +449,7 @@ int up_rtc_getdatetime(FAR struct tm *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_settime(FAR const struct timespec *tp) { @@ -454,7 +460,9 @@ int up_rtc_settime(FAR const struct timespec *tp) uint32_t cent; uint32_t year; - /* Break out the time values (note that the time is set only to units of seconds) */ + /* Break out the time values + * (note that the time is set only to units of seconds) + */ gmtime_r(&tp->tv_sec, &newtime); rtc_dumptime(&newtime, "Setting time"); @@ -471,9 +479,12 @@ int up_rtc_settime(FAR const struct timespec *tp) * *To allow for leap seconds. But these never actually happen. */ - timr = (rtc_bin2bcd(newtime.tm_sec) << RTC_TIMR_SEC_SHIFT) & RTC_TIMR_SEC_MASK; - timr |= (rtc_bin2bcd(newtime.tm_min) << RTC_TIMR_MIN_SHIFT) & RTC_TIMR_MIN_MASK; - timr |= (rtc_bin2bcd(newtime.tm_hour) << RTC_TIMR_HOUR_SHIFT) & RTC_TIMR_HOUR_MASK; + timr = (rtc_bin2bcd(newtime.tm_sec) << RTC_TIMR_SEC_SHIFT) & + RTC_TIMR_SEC_MASK; + timr |= (rtc_bin2bcd(newtime.tm_min) << RTC_TIMR_MIN_SHIFT) & + RTC_TIMR_MIN_MASK; + timr |= (rtc_bin2bcd(newtime.tm_hour) << RTC_TIMR_HOUR_SHIFT) & + RTC_TIMR_HOUR_MASK; /* Convert the struct tm format to RTC date register fields. * @@ -488,15 +499,20 @@ int up_rtc_settime(FAR const struct timespec *tp) * **Day of the week is not supported. Set to Monday. */ - calr = (rtc_bin2bcd(newtime.tm_mday) << RTC_CALR_DATE_SHIFT) & RTC_CALR_DATE_MASK; - calr |= (rtc_bin2bcd(1) << RTC_CALR_DAY_SHIFT) & RTC_CALR_DAY_MASK; - calr |= (rtc_bin2bcd(newtime.tm_mon+1) << RTC_CALR_MONTH_SHIFT) & RTC_CALR_MONTH_MASK; + calr = (rtc_bin2bcd(newtime.tm_mday) << RTC_CALR_DATE_SHIFT) & + RTC_CALR_DATE_MASK; + calr |= (rtc_bin2bcd(1) << RTC_CALR_DAY_SHIFT) & + RTC_CALR_DAY_MASK; + calr |= (rtc_bin2bcd(newtime.tm_mon + 1) << RTC_CALR_MONTH_SHIFT) & + RTC_CALR_MONTH_MASK; cent = newtime.tm_year / 100 + 19; year = newtime.tm_year % 100; - calr |= (rtc_bin2bcd(year) << RTC_CALR_YEAR_SHIFT) & RTC_CALR_YEAR_MASK; - calr |= (rtc_bin2bcd(cent) << RTC_CALR_CENT_SHIFT) & RTC_CALR_CENT_MASK; + calr |= (rtc_bin2bcd(year) << RTC_CALR_YEAR_SHIFT) & + RTC_CALR_YEAR_MASK; + calr |= (rtc_bin2bcd(cent) << RTC_CALR_CENT_SHIFT) & + RTC_CALR_CENT_MASK; /* Stop RTC time and date counting */ @@ -534,18 +550,20 @@ int up_rtc_settime(FAR const struct timespec *tp) /* The RTC should now be enabled */ - g_rtc_enabled = ((getreg32(SAM_RTC_VER) & (RTC_VER_NVTIM | RTC_VER_NVCAL)) == 0); + g_rtc_enabled = ((getreg32(SAM_RTC_VER) & + (RTC_VER_NVTIM | RTC_VER_NVCAL)) == 0); DEBUGASSERT(g_rtc_enabled); rtc_dumpregs("New time setting"); return OK; } -/************************************************************************************ +/**************************************************************************** * Name: sam_rtc_setalarm * * Description: - * Set up an alarm. Up to two alarms can be supported (ALARM A and ALARM B). + * Set up an alarm. + * Up to two alarms can be supported (ALARM A and ALARM B). * * Input Parameters: * tp - the time to set the alarm @@ -554,7 +572,7 @@ int up_rtc_settime(FAR const struct timespec *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) @@ -597,9 +615,12 @@ int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) * *To allow for leap seconds. But these never actually happen. */ - timalr = (rtc_bin2bcd(newalarm.tm_sec) << RTC_TIMALR_SEC_SHIFT) & RTC_TIMALR_SEC_MASK; - timalr |= (rtc_bin2bcd(newalarm.tm_min) << RTC_TIMALR_MIN_SHIFT) & RTC_TIMALR_MIN_MASK; - timalr |= (rtc_bin2bcd(newalarm.tm_hour) << RTC_TIMALR_HOUR_SHIFT) & RTC_TIMALR_HOUR_MASK; + timalr = (rtc_bin2bcd(newalarm.tm_sec) << RTC_TIMALR_SEC_SHIFT) & + RTC_TIMALR_SEC_MASK; + timalr |= (rtc_bin2bcd(newalarm.tm_min) << RTC_TIMALR_MIN_SHIFT) & + RTC_TIMALR_MIN_MASK; + timalr |= (rtc_bin2bcd(newalarm.tm_hour) << RTC_TIMALR_HOUR_SHIFT) & + RTC_TIMALR_HOUR_MASK; timalr |= (RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN); /* Convert the struct tm format to RTC date register fields. @@ -615,8 +636,12 @@ int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) * **Day of the week is not supported */ - calalr = (rtc_bin2bcd(newalarm.tm_mday) << RTC_CALALR_DATE_SHIFT) & RTC_CALALR_DATE_MASK; - calalr |= (rtc_bin2bcd(newalarm.tm_mon+1) << RTC_CALALR_MONTH_SHIFT) & RTC_CALALR_MONTH_MASK; + calalr = (rtc_bin2bcd(newalarm.tm_mday) << + RTC_CALALR_DATE_SHIFT) & + RTC_CALALR_DATE_MASK; + calalr |= (rtc_bin2bcd(newalarm.tm_mon + 1) << + RTC_CALALR_MONTH_SHIFT) & + RTC_CALALR_MONTH_MASK; calalr |= (RTC_CALALR_MTHEN | RTC_CALALR_DATEEN); /* Set the new date */ diff --git a/arch/arm/src/sama5/sam_rtc.h b/arch/arm/src/sama5/sam_rtc.h index edbbf2148b3..5aeff34eeac 100644 --- a/arch/arm/src/sama5/sam_rtc.h +++ b/arch/arm/src/sama5/sam_rtc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_RTC_H #define __ARCH_ARM_SRC_SAMA5_SAM_RTC_H @@ -30,13 +30,13 @@ #include "chip.h" #include "hardware/sam_rtc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -44,9 +44,9 @@ typedef void (*alarmcb_t)(void); -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -57,11 +57,11 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_rtc_setalarm * * Description: @@ -74,7 +74,7 @@ extern "C" * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM struct timespec; diff --git a/arch/arm/src/sama5/sam_sckc.c b/arch/arm/src/sama5/sam_sckc.c index a1c2db9313a..bfc0860e98a 100644 --- a/arch/arm/src/sama5/sam_sckc.c +++ b/arch/arm/src/sama5/sam_sckc.c @@ -79,6 +79,7 @@ void sam_sckc_enable(bool enable) #ifdef ATSAMA5D3 /* REVISIT: Missing the logic that disables the external OSC32 */ + /* Enable external OSC 32 kHz */ regval = getreg32(SAM_SCKC_CR); diff --git a/arch/arm/src/sama5/sam_sckc.h b/arch/arm/src/sama5/sam_sckc.h index ef6ee1a5e9c..a0ca52291ab 100644 --- a/arch/arm/src/sama5/sam_sckc.h +++ b/arch/arm/src/sama5/sam_sckc.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/sama5/sam_spi.h b/arch/arm/src/sama5/sam_spi.h index 59013edcdf1..907f3712357 100644 --- a/arch/arm/src/sama5/sam_spi.h +++ b/arch/arm/src/sama5/sam_spi.h @@ -36,8 +36,9 @@ * Pre-processor Definitions ****************************************************************************/ -/* The SPI port number used as an input to sam_spibus_initialize encodes information - * about the SPI controller (0 or 1) and the SPI chip select (0-3) +/* The SPI port number used as an input to sam_spibus_initialize encodes + * information about the SPI controller (0 or 1) and the SPI chip select + * (0-3) */ #define __SPI_CS_SHIFT (0) /* Bits 0-1: SPI chip select number */ @@ -113,27 +114,29 @@ struct spi_dev_s *sam_spibus_initialize(int port); * These external functions must be provided by board-specific logic. They * include: * - * o sam_spi[0|1]select is a functions tomanage the board-specific chip selects - * o sam_spi[0|1]status and sam_spi[0|1]cmddata: Implementations of the status - * and cmddata methods of the SPI interface defined by struct spi_ops_ - * (see include/nuttx/spi/spi.h). All other methods including + * o sam_spi[0|1]select is a functions tomanage the board-specific chip + * selects + * o sam_spi[0|1]status and sam_spi[0|1]cmddata: Implementations of the + * status and cmddata methods of the SPI interface defined by struct + * spi_ops_ (see include/nuttx/spi/spi.h). All other methods including * sam_spibus_initialize()) are provided by common SAM3/4 logic. * * To use this common SPI logic on your board: * * 1. Provide logic in sam_boardinitialize() to configure SPI chip select * pins. - * 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in your board- - * specific logic. These functions will perform chip selection and - * status operations using PIOs in the way your board is configured. + * 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in + * your board- specific logic. These functions will perform chip + * selection and status operations using PIOs in the way your board is + * configured. * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide * sam_spi[0|1]cmddata() functions in your board-specific logic. This * function will perform cmd/data selection operations using PIOs in * the way your board is configured. * 3. Add a call to sam_spibus_initialize() in your low level application * initialization logic - * 4. The handle returned by sam_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by sam_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * diff --git a/arch/arm/src/sama5/sam_ssc.h b/arch/arm/src/sama5/sam_ssc.h index dbab7b8f8ee..17d9e609d76 100644 --- a/arch/arm/src/sama5/sam_ssc.h +++ b/arch/arm/src/sama5/sam_ssc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_ssc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_SSC_H #define __ARCH_ARM_SRC_SAMA5_SAM_SSC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -31,23 +31,23 @@ #include "chip.h" #include "hardware/sam_ssc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -58,9 +58,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_ssc_initialize diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c index 3842596f38d..ce3064cc56f 100644 --- a/arch/arm/src/sama5/sam_tc.c +++ b/arch/arm/src/sama5/sam_tc.c @@ -424,7 +424,9 @@ static struct sam_tc_s g_tc345; static struct sam_tc_s g_tc678; #endif -/* TC frequency data. This table provides the frequency for each selection of TCCLK */ +/* TC frequency data. + * This table provides the frequency for each selection of TCCLK + */ #define TC_NDIVIDERS 4 #define TC_NDIVOPTIONS 5 diff --git a/arch/arm/src/sama5/sam_tickless.c b/arch/arm/src/sama5/sam_tickless.c index 6ad3bb73925..0345a213c73 100644 --- a/arch/arm/src/sama5/sam_tickless.c +++ b/arch/arm/src/sama5/sam_tickless.c @@ -25,8 +25,8 @@ * is suppressed and the platform specific code is expected to provide the * following custom functions. * - * void up_timer_initialize(void): Initializes the timer facilities. Called - * early in the initialization sequence (by up_initialize()). + * void up_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_initialize()). * int up_timer_gettime(FAR struct timespec *ts): Returns the current * time from the platform specific time source. * int up_timer_cancel(void): Cancels the interval timer. @@ -40,6 +40,7 @@ * logic when the interval timer expires. * ****************************************************************************/ + /**************************************************************************** * SAMA5 Timer Usage * @@ -363,7 +364,8 @@ int up_timer_gettime(FAR struct timespec *ts) int up_timer_cancel(FAR struct timespec *ts) { - return ONESHOT_INITIALIZED(&g_tickless.oneshot) && FREERUN_INITIALIZED(&g_tickless.freerun) ? + return ONESHOT_INITIALIZED(&g_tickless.oneshot) && + FREERUN_INITIALIZED(&g_tickless.freerun) ? sam_oneshot_cancel(&g_tickless.oneshot, &g_tickless.freerun, ts) : -EAGAIN; } @@ -396,7 +398,7 @@ int up_timer_cancel(FAR struct timespec *ts) int up_timer_start(FAR const struct timespec *ts) { return ONESHOT_INITIALIZED(&g_tickless.oneshot) ? - sam_oneshot_start(&g_tickless.oneshot, &g_tickless.freerun, sam_oneshot_handler, NULL, ts) : - -EAGAIN; + sam_oneshot_start(&g_tickless.oneshot, &g_tickless.freerun, + sam_oneshot_handler, NULL, ts) : -EAGAIN; } #endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/sama5/sam_timerisr.c b/arch/arm/src/sama5/sam_timerisr.c index 7f6f20d4477..c75ee57e1bc 100644 --- a/arch/arm/src/sama5/sam_timerisr.c +++ b/arch/arm/src/sama5/sam_timerisr.c @@ -39,6 +39,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* The PIT counter runs at a rate of the main clock (MCK) divided by 16. * * On the SAMA5D4, the clocking to the PIC may be divided down from MCK. diff --git a/arch/arm/src/sama5/sam_trng.h b/arch/arm/src/sama5/sam_trng.h index 4693ce36446..bd044bb4ce4 100644 --- a/arch/arm/src/sama5/sam_trng.h +++ b/arch/arm/src/sama5/sam_trng.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #undef EXTERN diff --git a/arch/arm/src/sama5/sam_tsd.h b/arch/arm/src/sama5/sam_tsd.h index 73559d79269..bc63ed9473c 100644 --- a/arch/arm/src/sama5/sam_tsd.h +++ b/arch/arm/src/sama5/sam_tsd.h @@ -33,6 +33,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifdef CONFIG_SAMA_TSD_RXP @@ -72,7 +73,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** @@ -98,6 +99,7 @@ int sam_tsd_register(FAR struct sam_adc_s *adc, int minor); /**************************************************************************** * Interfaces exported from the touchscreen to the ADC driver ****************************************************************************/ + /**************************************************************************** * Name: sam_tsd_interrupt * diff --git a/arch/arm/src/sama5/sam_twi.h b/arch/arm/src/sama5/sam_twi.h index ef3bdeaaa5f..03ed1b66184 100644 --- a/arch/arm/src/sama5/sam_twi.h +++ b/arch/arm/src/sama5/sam_twi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_twi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_TWI_H #define __ARCH_ARM_SRC_SAMA5_SAM_TWI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include diff --git a/arch/arm/src/sama5/sam_udphs.h b/arch/arm/src/sama5/sam_udphs.h index 693cd2f75c7..27d1b0b2f1a 100644 --- a/arch/arm/src/sama5/sam_udphs.h +++ b/arch/arm/src/sama5/sam_udphs.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_udphs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_UDPHS_H #define __ARCH_ARM_SRC_SAMA5_SAM_UDPHS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -32,9 +32,9 @@ #include "chip.h" #include "hardware/sam_udphs.h" -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -47,16 +47,16 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_usbsuspend * * Description: - * Board logic must provide the sam_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the sam_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. * - ************************************************************************************/ + ****************************************************************************/ void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume); diff --git a/arch/arm/src/sama5/sam_usbhost.c b/arch/arm/src/sama5/sam_usbhost.c index 47c0d84753d..ef1728b284b 100644 --- a/arch/arm/src/sama5/sam_usbhost.c +++ b/arch/arm/src/sama5/sam_usbhost.c @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/sama5/sam_usbhost.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -34,9 +34,9 @@ #ifdef HAVE_USBHOST_TRACE -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ #define TR_OHCI false #define TR_EHCI true @@ -50,9 +50,9 @@ # define NULL ((FAR void *)0) #endif -/******************************************************************************************** +/**************************************************************************** * Private Types - ********************************************************************************************/ + ****************************************************************************/ struct sam_usbhost_trace_s { @@ -64,81 +64,197 @@ struct sam_usbhost_trace_s FAR const char *string; }; -/******************************************************************************************** +/**************************************************************************** * Private Data - ********************************************************************************************/ + ****************************************************************************/ static const struct sam_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = { #ifdef CONFIG_SAMA5_OHCI - TRENTRY(OHCI_TRACE1_DEVDISCONN, TR_OHCI, TR_FMT1, "OHCI ERROR: RHport%d Device disconnected\n"), - TRENTRY(OHCI_TRACE1_INTRUNRECOVERABLE, TR_OHCI, TR_FMT1, "OHCI ERROR: Unrecoverable error. pending: %06x\n"), - TRENTRY(OHCI_TRACE1_INTRUNHANDLED, TR_OHCI, TR_FMT1, "OHCI ERROR: Unhandled interrupts pending: %06x\n"), - TRENTRY(OHCI_TRACE1_EPLISTALLOC_FAILED, TR_OHCI, TR_FMT1, "OHCI ERROR: Failed to allocate EP list\n"), - TRENTRY(OHCI_TRACE1_EDALLOC_FAILED, TR_OHCI, TR_FMT1, "OHCI ERROR: Failed to allocate ED\n"), - TRENTRY(OHCI_TRACE1_TDALLOC_FAILED, TR_OHCI, TR_FMT1, "OHCI ERROR: Failed to allocate TD\n"), - TRENTRY(OHCI_TRACE1_IRQATTACH, TR_OHCI, TR_FMT1, "OHCI ERROR: Failed to attach IRQ%d\n"), + TRENTRY(OHCI_TRACE1_DEVDISCONN, + TR_OHCI, TR_FMT1, + "OHCI ERROR: RHport%d Device disconnected\n"), + TRENTRY(OHCI_TRACE1_INTRUNRECOVERABLE, + TR_OHCI, TR_FMT1, + "OHCI ERROR: Unrecoverable error. pending: %06x\n"), + TRENTRY(OHCI_TRACE1_INTRUNHANDLED, + TR_OHCI, TR_FMT1, + "OHCI ERROR: Unhandled interrupts pending: %06x\n"), + TRENTRY(OHCI_TRACE1_EPLISTALLOC_FAILED, + TR_OHCI, TR_FMT1, + "OHCI ERROR: Failed to allocate EP list\n"), + TRENTRY(OHCI_TRACE1_EDALLOC_FAILED, + TR_OHCI, TR_FMT1, + "OHCI ERROR: Failed to allocate ED\n"), + TRENTRY(OHCI_TRACE1_TDALLOC_FAILED, + TR_OHCI, TR_FMT1, + "OHCI ERROR: Failed to allocate TD\n"), + TRENTRY(OHCI_TRACE1_IRQATTACH, + TR_OHCI, TR_FMT1, + "OHCI ERROR: Failed to attach IRQ%d\n"), #ifdef CONFIG_USBHOST_ASYNCH - TRENTRY(OHCI_TRACE1_BADTDSTATUS, TR_OHCI, TR_FMT1, "OHCI ERROR: Bad asynch TD completion status: %d\n"), + TRENTRY(OHCI_TRACE1_BADTDSTATUS, + TR_OHCI, TR_FMT1, + "OHCI ERROR: Bad asynch TD completion status: %d\n"), #endif #ifdef HAVE_USBHOST_TRACE_VERBOSE - TRENTRY(OHCI_VTRACE1_PHYSED, TR_OHCI, TR_FMT1, "OHCI physed: %06x\n"), - TRENTRY(OHCI_VTRACE1_VIRTED, TR_OHCI, TR_FMT1, "OHCI ed: %06x\n"), - TRENTRY(OHCI_VTRACE1_CSC, TR_OHCI, TR_FMT1, "OHCI Connect Status Change, RHSTATUS: %06x\n"), - TRENTRY(OHCI_VTRACE1_DRWE, TR_OHCI, TR_FMT1, "OHCI DRWE: Remote wake-up, RHSTATUS: %06x\n"), - TRENTRY(OHCI_VTRACE1_ALREADYCONN, TR_OHCI, TR_FMT1, "OHCI Already connected, RHPORTST: %06x\n"), - TRENTRY(OHCI_VTRACE1_SPEED, TR_OHCI, TR_FMT1, "OHCI Port speed: %d\n"), - TRENTRY(OHCI_VTRACE1_ALREADYDISCONN, TR_OHCI, TR_FMT1, "OHCI Already disconnected, RHPORTST: %06x\n"), - TRENTRY(OHCI_VTRACE1_RHSC, TR_OHCI, TR_FMT1, "OHCI Root Hub Status Change. Pending: %06x\n"), - TRENTRY(OHCI_VTRACE1_WDHINTR, TR_OHCI, TR_FMT1, "OHCI Writeback Done Head interrupt. Pending: %06x\n"), - TRENTRY(OHCI_VTRACE1_CLASSENUM, TR_OHCI, TR_FMT1, "OHCI Hub port %d: Enumerate device\n"), - TRENTRY(OHCI_VTRACE1_ENUMDISCONN, TR_OHCI, TR_FMT1, "OHCI RHport%dNot connected\n"), - TRENTRY(OHCI_VTRACE1_INITIALIZING, TR_OHCI, TR_FMT1, "OHCI Initializing Stack\n"), - TRENTRY(OHCI_VTRACE1_INITIALIZED, TR_OHCI, TR_FMT1, "OHCI Initialized\n"), - TRENTRY(OHCI_VTRACE1_INTRPENDING, TR_OHCI, TR_FMT1, "OHCI Interrupts pending: %06x\n"), + TRENTRY(OHCI_VTRACE1_PHYSED, + TR_OHCI, TR_FMT1, + "OHCI physed: %06x\n"), + TRENTRY(OHCI_VTRACE1_VIRTED, + TR_OHCI, TR_FMT1, + "OHCI ed: %06x\n"), + TRENTRY(OHCI_VTRACE1_CSC, + TR_OHCI, TR_FMT1, + "OHCI Connect Status Change, RHSTATUS: %06x\n"), + TRENTRY(OHCI_VTRACE1_DRWE, + TR_OHCI, TR_FMT1, + "OHCI DRWE: Remote wake-up, RHSTATUS: %06x\n"), + TRENTRY(OHCI_VTRACE1_ALREADYCONN, + TR_OHCI, TR_FMT1, + "OHCI Already connected, RHPORTST: %06x\n"), + TRENTRY(OHCI_VTRACE1_SPEED, + TR_OHCI, TR_FMT1, + "OHCI Port speed: %d\n"), + TRENTRY(OHCI_VTRACE1_ALREADYDISCONN, + TR_OHCI, TR_FMT1, + "OHCI Already disconnected, RHPORTST: %06x\n"), + TRENTRY(OHCI_VTRACE1_RHSC, + TR_OHCI, TR_FMT1, + "OHCI Root Hub Status Change. Pending: %06x\n"), + TRENTRY(OHCI_VTRACE1_WDHINTR, + TR_OHCI, TR_FMT1, + "OHCI Writeback Done Head interrupt. Pending: %06x\n"), + TRENTRY(OHCI_VTRACE1_CLASSENUM, + TR_OHCI, TR_FMT1, + "OHCI Hub port %d: Enumerate device\n"), + TRENTRY(OHCI_VTRACE1_ENUMDISCONN, + TR_OHCI, TR_FMT1, + "OHCI RHport%dNot connected\n"), + TRENTRY(OHCI_VTRACE1_INITIALIZING, + TR_OHCI, TR_FMT1, + "OHCI Initializing Stack\n"), + TRENTRY(OHCI_VTRACE1_INITIALIZED, + TR_OHCI, TR_FMT1, + "OHCI Initialized\n"), + TRENTRY(OHCI_VTRACE1_INTRPENDING, + TR_OHCI, TR_FMT1, + "OHCI Interrupts pending: %06x\n"), #endif #endif #ifdef CONFIG_SAMA5_EHCI - TRENTRY(EHCI_TRACE1_SYSTEMERROR, TR_EHCI, TR_FMT1, "EHCI ERROR: System error: %06x\n"), - TRENTRY(EHCI_TRACE1_QTDFOREACH_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: sam_qtd_foreach failed: %d\n"), - TRENTRY(EHCI_TRACE1_QHALLOC_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Failed to allocate a QH\n"), - TRENTRY(EHCI_TRACE1_BUFTOOBIG, TR_EHCI, TR_FMT1, "EHCI ERROR: Buffer too big. Remaining %d\n"), - TRENTRY(EHCI_TRACE1_REQQTDALLOC_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Failed to allocate request qTD"), - TRENTRY(EHCI_TRACE1_ADDBPL_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: sam_qtd_addbpl failed: %d\n"), - TRENTRY(EHCI_TRACE1_DATAQTDALLOC_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Failed to allocate data buffer qTD, 0"), - TRENTRY(EHCI_TRACE1_DEVDISCONNECTED, TR_EHCI, TR_FMT1, "EHCI ERROR: Device disconnected %d\n"), - TRENTRY(EHCI_TRACE1_QHCREATE_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: sam_qh_create failed\n"), - TRENTRY(EHCI_TRACE1_QTDSETUP_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: sam_qtd_setupphase failed\n"), - TRENTRY(EHCI_TRACE1_QTDDATA_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: sam_qtd_dataphase failed\n"), - TRENTRY(EHCI_TRACE1_QTDSTATUS_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: sam_qtd_statusphase failed\n"), - TRENTRY(EHCI_TRACE1_TRANSFER_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Transfer failed %d\n"), - TRENTRY(EHCI_TRACE1_QHFOREACH_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: sam_qh_foreach failed: %d\n"), - TRENTRY(EHCI_TRACE1_SYSERR_INTR, TR_EHCI, TR_FMT1, "EHCI: Host System Error Interrupt\n"), - TRENTRY(EHCI_TRACE1_USBERR_INTR, TR_EHCI, TR_FMT1, "EHCI: USB Error Interrupt (USBERRINT) Interrupt: %06x\n"), - TRENTRY(EHCI_TRACE1_EPALLOC_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Failed to allocate EP info structure\n"), - TRENTRY(EHCI_TRACE1_BADXFRTYPE, TR_EHCI, TR_FMT1, "EHCI ERROR: Support for transfer type %d not implemented\n"), - TRENTRY(EHCI_TRACE1_HCHALTED_TIMEOUT, TR_EHCI, TR_FMT1, "EHCI ERROR: Timed out waiting for HCHalted. USBSTS: %06x\n"), - TRENTRY(EHCI_TRACE1_QHPOOLALLOC_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Failed to allocate the QH pool\n"), - TRENTRY(EHCI_TRACE1_QTDPOOLALLOC_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Failed to allocate the qTD pool\n"), - TRENTRY(EHCI_TRACE1_PERFLALLOC_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Failed to allocate the periodic frame list\n"), - TRENTRY(EHCI_TRACE1_RESET_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: sam_reset failed: %d\n"), - TRENTRY(EHCI_TRACE1_RUN_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: EHCI Failed to run: USBSTS=%06x\n"), - TRENTRY(EHCI_TRACE1_IRQATTACH_FAILED, TR_EHCI, TR_FMT1, "EHCI ERROR: Failed to attach IRQ%d\n"), + TRENTRY(EHCI_TRACE1_SYSTEMERROR, + TR_EHCI, TR_FMT1, + "EHCI ERROR: System error: %06x\n"), + TRENTRY(EHCI_TRACE1_QTDFOREACH_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: sam_qtd_foreach failed: %d\n"), + TRENTRY(EHCI_TRACE1_QHALLOC_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Failed to allocate a QH\n"), + TRENTRY(EHCI_TRACE1_BUFTOOBIG, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Buffer too big. Remaining %d\n"), + TRENTRY(EHCI_TRACE1_REQQTDALLOC_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Failed to allocate request qTD"), + TRENTRY(EHCI_TRACE1_ADDBPL_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: sam_qtd_addbpl failed: %d\n"), + TRENTRY(EHCI_TRACE1_DATAQTDALLOC_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Failed to allocate data buffer qTD, 0"), + TRENTRY(EHCI_TRACE1_DEVDISCONNECTED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Device disconnected %d\n"), + TRENTRY(EHCI_TRACE1_QHCREATE_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: sam_qh_create failed\n"), + TRENTRY(EHCI_TRACE1_QTDSETUP_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: sam_qtd_setupphase failed\n"), + TRENTRY(EHCI_TRACE1_QTDDATA_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: sam_qtd_dataphase failed\n"), + TRENTRY(EHCI_TRACE1_QTDSTATUS_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: sam_qtd_statusphase failed\n"), + TRENTRY(EHCI_TRACE1_TRANSFER_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Transfer failed %d\n"), + TRENTRY(EHCI_TRACE1_QHFOREACH_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: sam_qh_foreach failed: %d\n"), + TRENTRY(EHCI_TRACE1_SYSERR_INTR, + TR_EHCI, TR_FMT1, + "EHCI: Host System Error Interrupt\n"), + TRENTRY(EHCI_TRACE1_USBERR_INTR, + TR_EHCI, TR_FMT1, + "EHCI: USB Error Interrupt (USBERRINT) Interrupt: %06x\n"), + TRENTRY(EHCI_TRACE1_EPALLOC_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Failed to allocate EP info structure\n"), + TRENTRY(EHCI_TRACE1_BADXFRTYPE, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Support for transfer type %d not implemented\n"), + TRENTRY(EHCI_TRACE1_HCHALTED_TIMEOUT, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Timed out waiting for HCHalted. USBSTS: %06x\n"), + TRENTRY(EHCI_TRACE1_QHPOOLALLOC_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Failed to allocate the QH pool\n"), + TRENTRY(EHCI_TRACE1_QTDPOOLALLOC_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Failed to allocate the qTD pool\n"), + TRENTRY(EHCI_TRACE1_PERFLALLOC_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Failed to allocate the periodic frame list\n"), + TRENTRY(EHCI_TRACE1_RESET_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: sam_reset failed: %d\n"), + TRENTRY(EHCI_TRACE1_RUN_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: EHCI Failed to run: USBSTS=%06x\n"), + TRENTRY(EHCI_TRACE1_IRQATTACH_FAILED, + TR_EHCI, TR_FMT1, + "EHCI ERROR: Failed to attach IRQ%d\n"), #ifdef HAVE_USBHOST_TRACE_VERBOSE - TRENTRY(EHCI_VTRACE1_PORTSC_CSC, TR_EHCI, TR_FMT1, "EHCI Connect Status Change: %06x\n"), - TRENTRY(EHCI_VTRACE1_PORTSC_CONNALREADY, TR_EHCI, TR_FMT1, "EHCI Already connected: %06x\n"), - TRENTRY(EHCI_VTRACE1_PORTSC_DISCALREADY, TR_EHCI, TR_FMT1, "EHCI Already disconnected: %06x\n"), - TRENTRY(EHCI_VTRACE1_TOPHALF, TR_EHCI, TR_FMT1, "EHCI Interrupt: %06x\n"), - TRENTRY(EHCI_VTRACE1_AAINTR, TR_EHCI, TR_FMT1, "EHCI Async Advance Interrupt\n"), - TRENTRY(EHCI_VTRACE1_USBINTR, TR_EHCI, TR_FMT1, "EHCI USB Interrupt (USBINT) Interrupt: %06x\n"), - TRENTRY(EHCI_VTRACE1_CLASSENUM, TR_EHCI, TR_FMT1, "EHCI Hub port %d: Enumerate device\n"), - TRENTRY(EHCI_VTRACE1_ENUM_DISCONN, TR_EHCI, TR_FMT1, "EHCI Enumeration not connected\n"), - TRENTRY(EHCI_VTRACE1_INITIALIZING, TR_EHCI, TR_FMT1, "EHCI Initializing EHCI Stack\n"), - TRENTRY(EHCI_VTRACE1_HCCPARAMS, TR_EHCI, TR_FMT1, "EHCI HCCPARAMS=%06x\n"), - TRENTRY(EHCI_VTRACE1_INIITIALIZED, TR_EHCI, TR_FMT1, "EHCI USB EHCI Initialized\n"), + TRENTRY(EHCI_VTRACE1_PORTSC_CSC, + TR_EHCI, TR_FMT1, + "EHCI Connect Status Change: %06x\n"), + TRENTRY(EHCI_VTRACE1_PORTSC_CONNALREADY, + TR_EHCI, TR_FMT1, + "EHCI Already connected: %06x\n"), + TRENTRY(EHCI_VTRACE1_PORTSC_DISCALREADY, + TR_EHCI, TR_FMT1, + "EHCI Already disconnected: %06x\n"), + TRENTRY(EHCI_VTRACE1_TOPHALF, + TR_EHCI, TR_FMT1, + "EHCI Interrupt: %06x\n"), + TRENTRY(EHCI_VTRACE1_AAINTR, + TR_EHCI, TR_FMT1, + "EHCI Async Advance Interrupt\n"), + TRENTRY(EHCI_VTRACE1_USBINTR, + TR_EHCI, TR_FMT1, + "EHCI USB Interrupt (USBINT) Interrupt: %06x\n"), + TRENTRY(EHCI_VTRACE1_CLASSENUM, + TR_EHCI, TR_FMT1, + "EHCI Hub port %d: Enumerate device\n"), + TRENTRY(EHCI_VTRACE1_ENUM_DISCONN, + TR_EHCI, TR_FMT1, + "EHCI Enumeration not connected\n"), + TRENTRY(EHCI_VTRACE1_INITIALIZING, + TR_EHCI, TR_FMT1, + "EHCI Initializing EHCI Stack\n"), + TRENTRY(EHCI_VTRACE1_HCCPARAMS, + TR_EHCI, TR_FMT1, + "EHCI HCCPARAMS=%06x\n"), + TRENTRY(EHCI_VTRACE1_INIITIALIZED, + TR_EHCI, TR_FMT1, + "EHCI USB EHCI Initialized\n"), #endif #endif }; @@ -146,63 +262,131 @@ static const struct sam_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = static const struct sam_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = { #ifdef CONFIG_SAMA5_OHCI - TRENTRY(OHCI_TRACE2_BADTDSTATUS, TR_OHCI, TR_FMT2, "OHCI ERROR: RHport%d Bad TD completion status: %d\n"), - TRENTRY(OHCI_TRACE2_WHDTDSTATUS, TR_OHCI, TR_FMT2, "OHCI ERROR: WHD Bad TD completion status: %d xfrtype: %d\n"), - TRENTRY(OHCI_TRACE2_EP0ENQUEUE_FAILED, TR_OHCI, TR_FMT2, "OHCI ERROR: RHport%d Failed to enqueue EP0: %d\n"), - TRENTRY(OHCI_TRACE2_EDENQUEUE_FAILED, TR_OHCI, TR_FMT2, "OHCI ERROR: Failed to queue ED for transfer type %d: %d\n"), - TRENTRY(OHCI_TRACE2_CLASSENUM_FAILED, TR_OHCI, TR_FMT2, "OHCI Hub port %d usbhost_enumerate() failed: %d\n"), + TRENTRY(OHCI_TRACE2_BADTDSTATUS, + TR_OHCI, TR_FMT2, + "OHCI ERROR: RHport%d Bad TD completion status: %d\n"), + TRENTRY(OHCI_TRACE2_WHDTDSTATUS, + TR_OHCI, TR_FMT2, + "OHCI ERROR: WHD Bad TD completion status: %d xfrtype: %d\n"), + TRENTRY(OHCI_TRACE2_EP0ENQUEUE_FAILED, + TR_OHCI, TR_FMT2, + "OHCI ERROR: RHport%d Failed to enqueue EP0: %d\n"), + TRENTRY(OHCI_TRACE2_EDENQUEUE_FAILED, + TR_OHCI, TR_FMT2, + "OHCI ERROR: Failed to queue ED for transfer type %d: %d\n"), + TRENTRY(OHCI_TRACE2_CLASSENUM_FAILED, + TR_OHCI, TR_FMT2, + "OHCI Hub port %d usbhost_enumerate() failed: %d\n"), #ifdef HAVE_USBHOST_TRACE_VERBOSE - TRENTRY(OHCI_VTRACE2_EP0CONFIG, TR_OHCI, TR_FMT2, "OHCI EP0 configure speed=%d funcaddr=%d\n"), - TRENTRY(OHCI_VTRACE2_INTERVAL, TR_OHCI, TR_FMT2, "OHCI interval: %d->%d\n"), - TRENTRY(OHCI_VTRACE2_MININTERVAL, TR_OHCI, TR_FMT2, "OHCI MIN interval: %d offset: %d\n"), - TRENTRY(OHCI_VTRACE2_RHPORTST, TR_OHCI, TR_FMT2, "OHCI RHPORTST%d: %04x\n"), - TRENTRY(OHCI_VTRACE2_CONNECTED, TR_OHCI, TR_FMT2, "OHCI RHPort%d connected, rhswait: %d\n"), - TRENTRY(OHCI_VTRACE2_DISCONNECTED, TR_OHCI, TR_FMT2, "OHCI RHPort%d disconnected, rhswait: %d\n"), - TRENTRY(OHCI_VTRACE2_WAKEUP, TR_OHCI, TR_FMT2, "OHCI RHPort%d connected: %d\n"), - TRENTRY(OHCI_VTRACE2_EP0CTRLED, TR_OHCI, TR_FMT2, "OHCI RHPort%d EP0 CTRL: %04x\n"), - TRENTRY(OHCI_VTRACE2_EPALLOC, TR_OHCI, TR_FMT2, "OHCI EP%d CTRL: %04x\n"), - TRENTRY(OHCI_VTRACE2_CTRLIN, TR_OHCI, TR_FMT2, "OHCI CTRLIN RHPort%d req: %02x\n"), - TRENTRY(OHCI_VTRACE2_CTRLOUT, TR_OHCI, TR_FMT2, "OHCI CTRLOUT RHPort%d req: %02x\n"), - TRENTRY(OHCI_VTRACE2_TRANSFER, TR_OHCI, TR_FMT2, "OHCI EP%d buflen: %d\n"), - TRENTRY(OHCI_VTRACE2_INITCONNECTED, TR_OHCI, TR_FMT2, "OHCI RHPort%d Device connected: %d\n"), + TRENTRY(OHCI_VTRACE2_EP0CONFIG, + TR_OHCI, TR_FMT2, + "OHCI EP0 configure speed=%d funcaddr=%d\n"), + TRENTRY(OHCI_VTRACE2_INTERVAL, + TR_OHCI, TR_FMT2, + "OHCI interval: %d->%d\n"), + TRENTRY(OHCI_VTRACE2_MININTERVAL, + TR_OHCI, TR_FMT2, + "OHCI MIN interval: %d offset: %d\n"), + TRENTRY(OHCI_VTRACE2_RHPORTST, + TR_OHCI, TR_FMT2, + "OHCI RHPORTST%d: %04x\n"), + TRENTRY(OHCI_VTRACE2_CONNECTED, + TR_OHCI, TR_FMT2, + "OHCI RHPort%d connected, rhswait: %d\n"), + TRENTRY(OHCI_VTRACE2_DISCONNECTED, + TR_OHCI, TR_FMT2, + "OHCI RHPort%d disconnected, rhswait: %d\n"), + TRENTRY(OHCI_VTRACE2_WAKEUP, + TR_OHCI, TR_FMT2, + "OHCI RHPort%d connected: %d\n"), + TRENTRY(OHCI_VTRACE2_EP0CTRLED, + TR_OHCI, TR_FMT2, + "OHCI RHPort%d EP0 CTRL: %04x\n"), + TRENTRY(OHCI_VTRACE2_EPALLOC, + TR_OHCI, TR_FMT2, + "OHCI EP%d CTRL: %04x\n"), + TRENTRY(OHCI_VTRACE2_CTRLIN, + TR_OHCI, TR_FMT2, + "OHCI CTRLIN RHPort%d req: %02x\n"), + TRENTRY(OHCI_VTRACE2_CTRLOUT, + TR_OHCI, TR_FMT2, + "OHCI CTRLOUT RHPort%d req: %02x\n"), + TRENTRY(OHCI_VTRACE2_TRANSFER, + TR_OHCI, TR_FMT2, + "OHCI EP%d buflen: %d\n"), + TRENTRY(OHCI_VTRACE2_INITCONNECTED, + TR_OHCI, TR_FMT2, + "OHCI RHPort%d Device connected: %d\n"), #ifdef CONFIG_USBHOST_HUB - TRENTRY(OHCI_VTRACE2_HUBWAKEUP, TR_OHCI, TR_FMT2, "OHCI Hub Port%d connected: %d\n"), + TRENTRY(OHCI_VTRACE2_HUBWAKEUP, + TR_OHCI, TR_FMT2, + "OHCI Hub Port%d connected: %d\n"), #endif #endif #endif #ifdef CONFIG_SAMA5_EHCI - TRENTRY(EHCI_TRACE2_EPSTALLED, TR_EHCI, TR_FMT2, "EHCI EP%d Stalled: TOKEN=%04x\n"), - TRENTRY(EHCI_TRACE2_EPIOERROR, TR_EHCI, TR_FMT2, "EHCI ERROR: EP%d TOKEN=%04x\n"), - TRENTRY(EHCI_TRACE2_CLASSENUM_FAILED, TR_EHCI, TR_FMT2, "EHCI Hub port %d usbhost_enumerate() failed: %d\n"), + TRENTRY(EHCI_TRACE2_EPSTALLED, + TR_EHCI, TR_FMT2, + "EHCI EP%d Stalled: TOKEN=%04x\n"), + TRENTRY(EHCI_TRACE2_EPIOERROR, + TR_EHCI, TR_FMT2, + "EHCI ERROR: EP%d TOKEN=%04x\n"), + TRENTRY(EHCI_TRACE2_CLASSENUM_FAILED, + TR_EHCI, TR_FMT2, + "EHCI Hub port %d usbhost_enumerate() failed: %d\n"), #ifdef HAVE_USBHOST_TRACE_VERBOSE - TRENTRY(EHCI_VTRACE2_EP0CONFIG, TR_EHCI, TR_FMT2, "EHCI EP0 configure speed=%d funcaddr=%d\n"), - TRENTRY(EHCI_VTRACE2_ASYNCXFR, TR_EHCI, TR_FMT2, "EHCI Async transfer EP%d buflen=%d\n"), - TRENTRY(EHCI_VTRACE2_INTRXFR, TR_EHCI, TR_FMT2, "EHCI Intr Transfer EP%d buflen=%d\n"), - TRENTRY(EHCI_VTRACE2_IOCCHECK, TR_EHCI, TR_FMT2, "EHCI IOC EP%d TOKEN=%04x\n"), - TRENTRY(EHCI_VTRACE2_PORTSC, TR_EHCI, TR_FMT2, "EHCI PORTSC%d: %04x\n"), - TRENTRY(EHCI_VTRACE2_PORTSC_CONNECTED, TR_EHCI, TR_FMT2, "EHCI RHPort%d connected, pscwait: %d\n"), - TRENTRY(EHCI_VTRACE2_PORTSC_DISCONND, TR_EHCI, TR_FMT2, "EHCI RHport%d disconnected, pscwait: %d\n"), - TRENTRY(EHCI_VTRACE2_MONWAKEUP, TR_EHCI, TR_FMT2, "EHCI Hub port%d connected: %d\n"), - TRENTRY(EHCI_VTRACE2_EPALLOC, TR_EHCI, TR_FMT2, "EHCI EPALLOC: EP%d TYPE=%d\n"), - TRENTRY(EHCI_VTRACE2_CTRLINOUT, TR_EHCI, TR_FMT2, "EHCI CTRLIN/OUT: RHPort%d req: %02x\n"), - TRENTRY(EHCI_VTRACE2_HCIVERSION, TR_EHCI, TR_FMT2, "EHCI HCIVERSION %x.%02x\n"), - TRENTRY(EHCI_VTRACE2_HCSPARAMS, TR_EHCI, TR_FMT2, "EHCI nports=%d, HCSPARAMS=%04x\n"), + TRENTRY(EHCI_VTRACE2_EP0CONFIG, + TR_EHCI, TR_FMT2, + "EHCI EP0 configure speed=%d funcaddr=%d\n"), + TRENTRY(EHCI_VTRACE2_ASYNCXFR, + TR_EHCI, TR_FMT2, + "EHCI Async transfer EP%d buflen=%d\n"), + TRENTRY(EHCI_VTRACE2_INTRXFR, + TR_EHCI, TR_FMT2, + "EHCI Intr Transfer EP%d buflen=%d\n"), + TRENTRY(EHCI_VTRACE2_IOCCHECK, + TR_EHCI, TR_FMT2, + "EHCI IOC EP%d TOKEN=%04x\n"), + TRENTRY(EHCI_VTRACE2_PORTSC, + TR_EHCI, TR_FMT2, + "EHCI PORTSC%d: %04x\n"), + TRENTRY(EHCI_VTRACE2_PORTSC_CONNECTED, + TR_EHCI, TR_FMT2, + "EHCI RHPort%d connected, pscwait: %d\n"), + TRENTRY(EHCI_VTRACE2_PORTSC_DISCONND, + TR_EHCI, TR_FMT2, + "EHCI RHport%d disconnected, pscwait: %d\n"), + TRENTRY(EHCI_VTRACE2_MONWAKEUP, + TR_EHCI, TR_FMT2, + "EHCI Hub port%d connected: %d\n"), + TRENTRY(EHCI_VTRACE2_EPALLOC, + TR_EHCI, TR_FMT2, + "EHCI EPALLOC: EP%d TYPE=%d\n"), + TRENTRY(EHCI_VTRACE2_CTRLINOUT, + TR_EHCI, TR_FMT2, + "EHCI CTRLIN/OUT: RHPort%d req: %02x\n"), + TRENTRY(EHCI_VTRACE2_HCIVERSION, + TR_EHCI, TR_FMT2, + "EHCI HCIVERSION %x.%02x\n"), + TRENTRY(EHCI_VTRACE2_HCSPARAMS, + TR_EHCI, TR_FMT2, + "EHCI nports=%d, HCSPARAMS=%04x\n"), #endif #endif }; -/******************************************************************************************** +/**************************************************************************** * Private Function Prototypes - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Functions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Name: usbhost_trformat1 and usbhost_trformat2 * * Description: @@ -213,7 +397,7 @@ static const struct sam_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = * printf. The returned format is expected to handle two unsigned integer * values. * - ********************************************************************************************/ + ****************************************************************************/ FAR const char *usbhost_trformat1(uint16_t id) { diff --git a/arch/arm/src/sama5/sam_usbhost.h b/arch/arm/src/sama5/sam_usbhost.h index 8bbce95709b..d714db96447 100644 --- a/arch/arm/src/sama5/sam_usbhost.h +++ b/arch/arm/src/sama5/sam_usbhost.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sam_usbhost.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,46 +16,47 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAM_USBHOST_H #define __ARCH_ARM_SRC_SAMA5_SAM_USBHOST_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #ifdef CONFIG_USBHOST -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* This is the interface argument for call outs to board-specific functions which - * need to know which USB host interface is being used. + ****************************************************************************/ + +/* This is the interface argument for call outs to board-specific functions + * which need to know which USB host interface is being used. */ #define SAM_EHCI_IFACE 0 #define SAM_OHCI_IFACE 1 -/* This is the interface argument for call outs to board-specific functions which - * need to know which root hub port is being used. +/* This is the interface argument for call outs to board-specific functions + * which need to know which root hub port is being used. */ #define SAM_RHPORT1 0 #define SAM_RHPORT2 1 #define SAM_RHPORT3 2 -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_USBHOST_TRACE enum usbhost_trace1codes_e { - __TRACE1_BASEVALUE = 0, /* This will force the first value to be 1 */ + __TRACE1_BASEVALUE = 0, /* This will force the first value to be 1 */ #ifdef CONFIG_SAMA5_OHCI OHCI_TRACE1_DEVDISCONN, /* OHCI ERROR: RHport Device disconnected */ @@ -192,13 +193,13 @@ enum usbhost_trace1codes_e #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -211,20 +212,20 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_ohci_initialize * * Description: * Initialize USB OHCI host controller hardware. * * Input Parameters: - * controller -- If the device supports more than one USB OHCI interface, then - * this identifies which controller is being initializeed. Normally, this - * is just zero. + * controller -- If the device supports more than one USB OHCI interface, + * then this identifies which controller is being initializeed. + * Normally, this is just zero. * * Returned Value: * And instance of the USB host interface. The controlling task should @@ -238,28 +239,28 @@ extern "C" * - Class drivers should be initialized prior to calling this function. * Otherwise, there is a race condition if the device is already connected. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMA5_OHCI struct usbhost_connection_s; FAR struct usbhost_connection_s *sam_ohci_initialize(int controller); #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_ohci_tophalf * * Description: - * OHCI "Top Half" interrupt handler. If both EHCI and OHCI are enabled, then - * EHCI will manage the common UHPHS interrupt and will forward the interrupt - * event to this function. + * OHCI "Top Half" interrupt handler. If both EHCI and OHCI are enabled, + * then EHCI will manage the common UHPHS interrupt and will forward the + * interrupt event to this function. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMA5_OHCI int sam_ohci_tophalf(int irq, FAR void *context, FAR void *arg); #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_ehci_initialize * * Description: @@ -267,8 +268,8 @@ int sam_ohci_tophalf(int irq, FAR void *context, FAR void *arg); * * Input Parameters: * controller -- If the device supports more than one EHCI interface, then - * this identifies which controller is being initializeed. Normally, this - * is just zero. + * this identifies which controller is being initializeed. Normally, + * this is just zero. * * Returned Value: * And instance of the USB host interface. The controlling task should @@ -282,29 +283,30 @@ int sam_ohci_tophalf(int irq, FAR void *context, FAR void *arg); * - Class drivers should be initialized prior to calling this function. * Otherwise, there is a race condition if the device is already connected. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMA5_EHCI struct usbhost_connection_s; FAR struct usbhost_connection_s *sam_ehci_initialize(int controller); #endif -/*********************************************************************************** +/**************************************************************************** * Name: sam_usbhost_vbusdrive * * Description: - * Enable/disable driving of VBUS 5V output. This function must be provided by - * each platform that implements the OHCI or EHCI host interface + * Enable/disable driving of VBUS 5V output. This function must be + * provided by each platform that implements the OHCI or EHCI host + * interface * * Input Parameters: - * rhport - Selects root hub port to be powered host interface. See SAM_RHPORT_* - * definitions above. + * rhport - Selects root hub port to be powered host interface. + * See SAM_RHPORT_*definitions above. * enable - true: enable VBUS power; false: disable VBUS power * * Returned Value: * None * - ***********************************************************************************/ + ****************************************************************************/ void sam_usbhost_vbusdrive(int rhport, bool enable); diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index 9dca4d8ad63..b7773730514 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -41,6 +41,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_DEBUG_WATCHDOG_INFO @@ -73,6 +74,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * well-known watchdog_lowerhalf_s structure. @@ -92,6 +94,7 @@ struct sam_lowerhalf_s /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Register operations ******************************************************/ #ifdef CONFIG_SAMA5_WDT_REGDEBUG @@ -125,6 +128,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, /**************************************************************************** * Private Data ****************************************************************************/ + /* "Lower half" driver methods */ static const struct watchdog_ops_s g_wdgops = @@ -165,8 +169,8 @@ static uint32_t sam_getreg(uintptr_t regaddr) uint32_t regval = getreg32(regaddr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. */ if (regaddr == prevaddr && regval == preval) @@ -192,7 +196,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - wdinfo("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -272,8 +276,8 @@ static int sam_interrupt(int irq, FAR void *context, FAR void *arg) * Start the watchdog timer, resetting the time to the current timeout, * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -286,7 +290,8 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower) /* The watchdog timer is enabled or disabled by writing to the MR register. * - * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * NOTE: + * The Watchdog Mode Register (WDT_MR) can be written only once. Only * a processor reset resets it. Writing the WDT_MR register reloads the * timer with the newly programmed mode parameters. */ @@ -302,8 +307,8 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower) * Stop the watchdog timer * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -314,7 +319,8 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) { /* The watchdog timer is enabled or disabled by writing to the MR register. * - * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * NOTE: + * The Watchdog Mode Register (WDT_MR) can be written only once. Only * a processor reset resets it. Writing the WDT_MR register reloads the * timer with the newly programmed mode parameters. */ @@ -332,8 +338,8 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) * the atchdog timer or "petting the dog". * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -359,8 +365,8 @@ static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower) * Get the current watchdog timer status * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * stawtus - The location to return the watchdog status information. * * Returned Value: @@ -416,8 +422,8 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, * Set a new timeout value (and reset the watchdog timer) * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * timeout - The new timeout value in millisecnds. * * Returned Value: @@ -466,7 +472,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, * timeout = 1000 * (reload + 1) / Fwwdg */ - priv->timeout = (1000 * reload + WDT_FREQUENCY/2) / WDT_FREQUENCY; + priv->timeout = (1000 * reload + WDT_FREQUENCY / 2) / WDT_FREQUENCY; /* Remember the selected values */ @@ -477,7 +483,8 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, /* Set the WDT_MR according to calculated value * - * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * NOTE: + * The Watchdog Mode Register (WDT_MR) can be written only once. Only * a processor reset resets it. Writing the WDT_MR register reloads the * timer with the newly programmed mode parameters. */ @@ -533,8 +540,8 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, * behavior. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * newhandler - The new watchdog expiration function pointer. If this * function pointer is NULL, then the reset-on-expiration * behavior is restored, @@ -567,7 +574,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, /* Save the new handler */ - priv->handler = handler; + priv->handler = handler; /* Are we attaching or detaching the handler? */ @@ -597,8 +604,8 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, * are forwarded to the lower half driver through this method. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * cmd - The ioctol command value * arg - The optional argument that accompanies the 'cmd'. The * interpretation of this argument depends on the particular diff --git a/arch/arm/src/sama5/sam_wdt.h b/arch/arm/src/sama5/sam_wdt.h index a729c46da1c..8aba0fe1eae 100644 --- a/arch/arm/src/sama5/sam_wdt.h +++ b/arch/arm/src/sama5/sam_wdt.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/sama5/sama5d2x_memorymap.c b/arch/arm/src/sama5/sama5d2x_memorymap.c index 96b6786e56c..3e5ce8feb79 100644 --- a/arch/arm/src/sama5/sama5d2x_memorymap.c +++ b/arch/arm/src/sama5/sama5d2x_memorymap.c @@ -81,10 +81,10 @@ const struct section_mapping_s g_section_mapping[] = * If we are executing out of ISRAM, then the SAMA5 primary bootloader * probably copied us into ISRAM and set the AXI REMAP0 bit for us. * - * If we are executing from external SDRAM, then a secondary bootloader must - * have loaded us into SDRAM. In this case, simply set the VBAR register - * to the address of the vector table (not necessary at the beginning - * or SDRAM). + * If we are executing from external SDRAM, then a secondary bootloader + * must have loaded us into SDRAM. In this case, simply set the VBAR + * register to the address of the vector table (not necessary at the + * beginning or SDRAM). */ #ifdef CONFIG_ARCH_LOWVECTORS @@ -142,18 +142,19 @@ const struct section_mapping_s g_section_mapping[] = #endif /* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been - * initialized. If we are running out of SDRAM now, we can assume that some - * second level boot loader has properly configured SRAM for us. In that - * case, we set the MMU flags for the final, fully cache-able state. + * initialized. If we are running out of SDRAM now, we can assume that + * some second level boot loader has properly configured SRAM for us. + * In that case, we set the MMU flags for the final, fully cache-able + * state. * * Also, in this case, the mapping for the SDRAM was done in arm_head.S and * need not be repeated here. * - * If we are running from ISRAM or NOR flash, then we will need to configure - * the SDRAM ourselves. In this case, we set the MMU flags to the strongly - * ordered, non-cacheable state. We need this direct access to SDRAM in - * order to configure it. Once SDRAM has been initialized, it will be re- - * configured in its final state. + * If we are running from ISRAM or NOR flash, then we will need to + * configure the SDRAM ourselves. In this case, we set the MMU flags to + * the strongly ordered, non-cacheable state. We need this direct access + * to SDRAM in order to configure it. Once SDRAM has been initialized, it + * will be re- configured in its final state. */ #ifdef NEED_SDRAM_MAPPING @@ -239,9 +240,9 @@ const struct section_mapping_s g_section_mapping[] = /* LCDC Framebuffer. This entry reprograms a part of one of the above * regions, making it non-cacheable and non-buffereable. * - * If SDRAM will be reconfigured, then we will defer setup of the framebuffer - * until after the SDRAM remapping since the framebuffer probablyresides in - * SDRAM. + * If SDRAM will be reconfigured, then we will defer setup of the + * framebuffer until after the SDRAM remapping since the framebuffer + * probablyresides in SDRAM. */ #if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING) @@ -299,3 +300,7 @@ const struct section_mapping_s g_operational_mapping[] = const size_t g_num_opmappings = NREMAPPINGS; #endif /* NEED_SDRAM_REMAPPING */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/sama5/sama5d2x_periphclks.h b/arch/arm/src/sama5/sama5d2x_periphclks.h index 7c3c60783f2..df16fea3a37 100644 --- a/arch/arm/src/sama5/sama5d2x_periphclks.h +++ b/arch/arm/src/sama5/sama5d2x_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sama5d2x_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAMAD52X_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAMA5_SAMAD52X_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Helper macros */ @@ -253,19 +253,19 @@ #define sam_sfrbu_isenabled() (false) /* No peripheral clock */ #define sam_chipid_isenabled() (false) /* No peripheral clock */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -276,9 +276,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sama5/sama5d2x_pio.h b/arch/arm/src/sama5/sama5d2x_pio.h index 5541b4cda91..12a7bc81f39 100644 --- a/arch/arm/src/sama5/sama5d2x_pio.h +++ b/arch/arm/src/sama5/sama5d2x_pio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sama5d2x_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAMA5D2X_PIO_H #define __ARCH_ARM_SRC_SAMA5_SAMA5D2X_PIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -32,10 +32,11 @@ #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #if !defined(CONFIG_SAMA5_PIOA_IRQ) && !defined(CONFIG_SAMA5_PIOB_IRQ) && \ !defined(CONFIG_SAMA5_PIOC_IRQ) && !defined(CONFIG_SAMA5_PIOD_IRQ) @@ -49,7 +50,7 @@ #define SAM_NPIO 4 /* (4) PIOA-D */ -/* Bit-encoded input to sam_configpio() ********************************************/ +/* Bit-encoded input to sam_configpio() *************************************/ /* 32-bit Encoding: * @@ -123,7 +124,8 @@ #define PIO_INT_SECURE (1 << 9) /* Bit 9: Secure PIO */ #define PIO_INT_UNSECURE (0) -/* If the pin is an PIO output, then this identifies the initial output value: +/* If the pin is an PIO output, then this identifies the initial output + * value: * * .... .... .... .... .... ...V .... .... */ @@ -183,9 +185,9 @@ #define PIO_PIN30 (30 << PIO_PIN_SHIFT) #define PIO_PIN31 (31 << PIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 32-bit encoding */ diff --git a/arch/arm/src/sama5/sama5d3x4x_pio.c b/arch/arm/src/sama5/sama5d3x4x_pio.c index fe8064143ff..cf8848b9d15 100644 --- a/arch/arm/src/sama5/sama5d3x4x_pio.c +++ b/arch/arm/src/sama5/sama5d3x4x_pio.c @@ -77,6 +77,7 @@ const uintptr_t g_piobase[SAM_NPIO] = /**************************************************************************** * Private Data ****************************************************************************/ + /* Maps a port number to the standard port character */ #if defined(CONFIG_DEBUG_GPIO_INFO) && SAM_NPIO > 0 @@ -171,6 +172,7 @@ static uint32_t g_forced[SAM_NPIO]; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /**************************************************************************** * Name: sam_piobase * @@ -818,20 +820,22 @@ bool sam_pioread(pio_pinset_t pinset) return 0; } -/************************************************************************************ +/**************************************************************************** * Name: sam_pio_forceclk * * Description: - * Enable PIO clocking. This logic is overly conservative and does not enable PIO - * clocking unless necessary (PIO input selected, glitch/filtering enable, or PIO - * interrupts enabled). There are, however, certain conditions were we may want - * for force the PIO clock to be enabled. An example is reading the input value - * from an open drain output. + * Enable PIO clocking. + * This logic is overly conservative and does not enable PIO clocking + * unless necessary (PIO input selected, glitch/filtering enable, or PIO + * interrupts enabled). There are, however, certain conditions were we may + * want to force the PIO clock to be enabled. + * An example is reading the input value from an open drain output. * - * The PIO automatic enable/disable logic is not smart enough enough to know about - * these cases. For those cases, sam_pio_forceclk() is provided. + * The PIO automatic enable/disable logic is not smart enough enough to + * know about these cases. + * For those cases, sam_pio_forceclk() is provided. * - ************************************************************************************/ + ****************************************************************************/ void sam_pio_forceclk(pio_pinset_t pinset, bool enable) { @@ -868,13 +872,14 @@ void sam_pio_forceclk(pio_pinset_t pinset, bool enable) leave_critical_section(flags); } -/************************************************************************************ +/**************************************************************************** * Function: sam_dumppio * * Description: - * Dump all PIO registers associated with the base address of the provided pinset. + * Dump all PIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumppio(uint32_t pinset, const char *msg) @@ -897,36 +902,50 @@ int sam_dumppio(uint32_t pinset, const char *msg) #ifdef SAM_PIO_ISLR_OFFSET gpioinfo(" PSR: %08x ISLR: %08x OSR: %08x IFSR: %08x\n", - getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_ISLR_OFFSET), - getreg32(base + SAM_PIO_OSR_OFFSET), getreg32(base + SAM_PIO_IFSR_OFFSET)); + getreg32(base + SAM_PIO_PSR_OFFSET), + getreg32(base + SAM_PIO_ISLR_OFFSET), + getreg32(base + SAM_PIO_OSR_OFFSET), + getreg32(base + SAM_PIO_IFSR_OFFSET)); #else gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x\n", - getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET), + getreg32(base + SAM_PIO_PSR_OFFSET), + getreg32(base + SAM_PIO_OSR_OFFSET), getreg32(base + SAM_PIO_IFSR_OFFSET)); #endif gpioinfo(" ODSR: %08x PDSR: %08x IMR: %08x ISR: %08x\n", - getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_PDSR_OFFSET), - getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET)); + getreg32(base + SAM_PIO_ODSR_OFFSET), + getreg32(base + SAM_PIO_PDSR_OFFSET), + getreg32(base + SAM_PIO_IMR_OFFSET), + getreg32(base + SAM_PIO_ISR_OFFSET)); gpioinfo(" MDSR: %08x PUSR: %08x ABDCSR: %08x %08x\n", - getreg32(base + SAM_PIO_MDSR_OFFSET), getreg32(base + SAM_PIO_PUSR_OFFSET), - getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET)); + getreg32(base + SAM_PIO_MDSR_OFFSET), + getreg32(base + SAM_PIO_PUSR_OFFSET), + getreg32(base + SAM_PIO_ABCDSR1_OFFSET), + getreg32(base + SAM_PIO_ABCDSR2_OFFSET)); gpioinfo(" IFSCSR: %08x SCDR: %08x PPDSR: %08x OWSR: %08x\n", - getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), - getreg32(base + SAM_PIO_PPDSR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET)); + getreg32(base + SAM_PIO_IFSCSR_OFFSET), + getreg32(base + SAM_PIO_SCDR_OFFSET), + getreg32(base + SAM_PIO_PPDSR_OFFSET), + getreg32(base + SAM_PIO_OWSR_OFFSET)); #ifdef SAM_PIO_LOCKSR_OFFSET gpioinfo(" AIMMR: %08x ELSR: %08x FRLHSR: %08x LOCKSR: %08x\n", - getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET), - getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET)); + getreg32(base + SAM_PIO_AIMMR_OFFSET), + getreg32(base + SAM_PIO_ELSR_OFFSET), + getreg32(base + SAM_PIO_FRLHSR_OFFSET), + getreg32(base + SAM_PIO_LOCKSR_OFFSET)); #else gpioinfo(" AIMMR: %08x ELSR: %08x FRLHSR: %08x\n", - getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET), + getreg32(base + SAM_PIO_AIMMR_OFFSET), + getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FRLHSR_OFFSET)); #endif gpioinfo("SCHMITT: %08x DRIVER: %08x %08x\n", - getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER1_OFFSET), + getreg32(base + SAM_PIO_SCHMITT_OFFSET), + getreg32(base + SAM_PIO_DRIVER1_OFFSET), getreg32(base + SAM_PIO_DRIVER2_OFFSET)); gpioinfo(" WPMR: %08x WPSR: %08x\n", - getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); + getreg32(base + SAM_PIO_WPMR_OFFSET), + getreg32(base + SAM_PIO_WPSR_OFFSET)); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/sama5/sama5d3x4x_pio.h b/arch/arm/src/sama5/sama5d3x4x_pio.h index ab7aea08b01..24b7b407b3f 100644 --- a/arch/arm/src/sama5/sama5d3x4x_pio.h +++ b/arch/arm/src/sama5/sama5d3x4x_pio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sama5d3x4x_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,19 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAMA5D3X4X_PIO_H #define __ARCH_ARM_SRC_SAMA5_SAMA5D3X4X_PIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #if !defined(CONFIG_SAMA5_PIOA_IRQ) && !defined(CONFIG_SAMA5_PIOB_IRQ) && \ !defined(CONFIG_SAMA5_PIOC_IRQ) && !defined(CONFIG_SAMA5_PIOD_IRQ) && \ @@ -43,7 +44,7 @@ #define SAM_NPIO 5 /* (5) PIOA-E */ -/* Bit-encoded input to sam_configpio() ********************************************/ +/* Bit-encoded input to sam_configpio() *************************************/ /* 32-bit Encoding: * @@ -109,7 +110,8 @@ # define PIO_INT_FALLING (_PIO_INT_AIM | _PIO_INT_EDGE | _PIO_INT_FL) # define PIO_INT_BOTHEDGES (0) -/* If the pin is an interrupt, then this determines if the pin is a secure interrupt: +/* If the pin is an interrupt, then this determines if the pin is a secure + * interrupt: * * .... .... .... .... .... ..S. .... .... */ @@ -121,7 +123,8 @@ #endif #define PIO_INT_UNSECURE (0) -/* If the pin is an PIO output, then this identifies the initial output value: +/* If the pin is an PIO output, then this identifies the initial output + * value: * * .... .... .... .... .... ...V .... .... */ @@ -182,9 +185,9 @@ #define PIO_PIN30 (30 << PIO_PIN_SHIFT) #define PIO_PIN31 (31 << PIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* Must be big enough to hold the 32-bit encoding */ diff --git a/arch/arm/src/sama5/sama5d3x_memorymap.c b/arch/arm/src/sama5/sama5d3x_memorymap.c index 352f1bd9395..5916f0447bd 100644 --- a/arch/arm/src/sama5/sama5d3x_memorymap.c +++ b/arch/arm/src/sama5/sama5d3x_memorymap.c @@ -74,20 +74,22 @@ const struct section_mapping_s g_section_mapping[] = * This is the method used when booting from SDRAM. * * - When executing from NOR FLASH, the first level bootloader is supposed - * to provide the AXI MATRIX mapping for us at boot time base on the state - * of the BMS pin. However, I have found that in the test environments - * that I use, I cannot always be assured of that physical address mapping. + * to provide the AXI MATRIX mapping for us at boot time base on the + * state of the BMS pin. However, I have found that in the test + * environments that I use, I cannot always be assured of that physical + * address mapping. * - * So we do both here. If we are executing from NOR FLASH, then we provide - * the MMU to map the physical address of FLASH to address 0x0000:0000; + * So we do both here. If we are executing from NOR FLASH, then we + * provide the MMU to map the physical address of FLASH to address + * 0x0000:0000; * * - If we are executing out of ISRAM, then the SAMA5 primary bootloader * probably copied us into ISRAM and set the AXI REMAP bit for us. * - * - If we are executing from external SDRAM, then a secondary bootloader must - * have loaded us into SDRAM. In this case, simply set the VBAR register - * to the address of the vector table (not necessary at the beginning - * or SDRAM). + * - If we are executing from external SDRAM, then a secondary bootloader + * must have loaded us into SDRAM. In this case, simply set the VBAR + * register to the address of the vector table (not necessary at the + * beginning or SDRAM). */ #if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM) && \ @@ -142,18 +144,19 @@ const struct section_mapping_s g_section_mapping[] = #endif /* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been - * initialized. If we are running out of SDRAM now, we can assume that some - * second level boot loader has properly configured SRAM for us. In that - * case, we set the MMU flags for the final, fully cache-able state. + * initialized. If we are running out of SDRAM now, we can assume that + * some second level boot loader has properly configured SRAM for us. + * In that case, we set the MMU flags for the final, fully cache-able + * state. * - * Also, in this case, the mapping for the SDRAM was done in arm_head.S and - * need not be repeated here. + * Also, in this case, the mapping for the SDRAM was done in arm_head.S + * and need not be repeated here. * - * If we are running from ISRAM or NOR flash, then we will need to configure - * the SDRAM ourselves. In this case, we set the MMU flags to the strongly - * ordered, non-cacheable state. We need this direct access to SDRAM in - * order to configure it. Once SDRAM has been initialized, it will be re- - * configured in its final state. + * If we are running from ISRAM or NOR flash, then we will need to + * configure the SDRAM ourselves. In this case, we set the MMU flags to + * the strongly ordered, non-cacheable state. We need this direct access + * to SDRAM in order to configure it. Once SDRAM has been initialized, it + * will be reconfigured in its final state. */ #ifdef NEED_SDRAM_MAPPING @@ -208,9 +211,9 @@ const struct section_mapping_s g_section_mapping[] = /* LCDC Framebuffer. This entry reprograms a part of one of the above * regions, making it non-cacheable and non-buffereable. * - * If SDRAM will be reconfigured, then we will defer setup of the framebuffer - * until after the SDRAM remapping (since the framebuffer problem resides) in - * SDRAM. + * If SDRAM will be reconfigured, then we will defer setup of the + * framebuffer until after the SDRAM remapping (since the framebuffer + * problem resides) in SDRAM. */ #if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING) @@ -265,3 +268,7 @@ const struct section_mapping_s g_operational_mapping[] = const size_t g_num_opmappings = NREMAPPINGS; #endif /* NEED_SDRAM_REMAPPING */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/sama5/sama5d3x_periphclks.h b/arch/arm/src/sama5/sama5d3x_periphclks.h index d19858cee89..376e7a9609c 100644 --- a/arch/arm/src/sama5/sama5d3x_periphclks.h +++ b/arch/arm/src/sama5/sama5d3x_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sama5d3x_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAMAD53X_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAMA5_SAMAD53X_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) @@ -192,19 +193,19 @@ #define sam_fuse_isenabled() sam_isenabled1(SAM_PID_FUSE) #define sam_mpddrc_isenabled() sam_isenabled1(SAM_PID_MPDDRC) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -215,9 +216,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/sama5/sama5d4x_memorymap.c b/arch/arm/src/sama5/sama5d4x_memorymap.c index 0276a081398..914d3116827 100644 --- a/arch/arm/src/sama5/sama5d4x_memorymap.c +++ b/arch/arm/src/sama5/sama5d4x_memorymap.c @@ -74,20 +74,22 @@ const struct section_mapping_s g_section_mapping[] = * This is the method used when booting from SDRAM. * * - When executing from NOR FLASH, the first level bootloader is supposed - * to provide the AXI MATRIX mapping for us at boot time base on the state - * of the BMS pin. However, I have found that in the test environments - * that I use, I cannot always be assured of that physical address mapping. + * to provide the AXI MATRIX mapping for us at boot time base on the + * state of the BMS pin. However, I have found that in the test + * environments that I use, I cannot always be assured of that physical + * address mapping. * - * So we do both here. If we are executing from NOR FLASH, then we provide - * the MMU to map the physical address of FLASH to address 0x0000:0000; + * So we do both here. If we are executing from NOR FLASH, then we + * provide the MMU to map the physical address of FLASH to address + * 0x0000:0000; * * - If we are executing out of ISRAM, then the SAMA5 primary bootloader * probably copied us into ISRAM and set the AXI REMAP bit for us. * - * - If we are executing from external SDRAM, then a secondary bootloader must - * have loaded us into SDRAM. In this case, simply set the VBAR register - * to the address of the vector table (not necessary at the beginning - * or SDRAM). + * - If we are executing from external SDRAM, then a secondary bootloader + * must have loaded us into SDRAM. In this case, simply set the VBAR + * register to the address of the vector table (not necessary at the + * beginning or SDRAM). */ #if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM) && \ @@ -147,19 +149,20 @@ const struct section_mapping_s g_section_mapping[] = }, #endif - /* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been - * initialized. If we are running out of SDRAM now, we can assume that some - * second level boot loader has properly configured SRAM for us. In that - * case, we set the MMU flags for the final, fully cache-able state. + /* SAMA5 External SDRAM Memory. + * The SDRAM is not usable until it has been initialized. + * If we are running out of SDRAM now, we can assume that some second level + * boot loader has properly configured SRAM for us. In that case, + * we set the MMU flags for the final, fully cache-able state. * - * Also, in this case, the mapping for the SDRAM was done in arm_head.S and - * need not be repeated here. + * Also, in this case, the mapping for the SDRAM was done in arm_head.S + * and need not be repeated here. * - * If we are running from ISRAM or NOR flash, then we will need to configure - * the SDRAM ourselves. In this case, we set the MMU flags to the strongly - * ordered, non-cacheable state. We need this direct access to SDRAM in - * order to configure it. Once SDRAM has been initialized, it will be re- - * configured in its final state. + * If we are running from ISRAM or NOR flash, then we will need to + * configure the SDRAM ourselves. In this case, we set the MMU flags to + * the strongly ordered, non-cacheable state. We need this direct access + * to SDRAM in order to configure it. Once SDRAM has been initialized, it + * will be re- configured in its final state. */ #ifdef NEED_SDRAM_MAPPING @@ -212,9 +215,9 @@ const struct section_mapping_s g_section_mapping[] = /* LCDC Framebuffer. This entry reprograms a part of one of the above * regions, making it non-cacheable and non-buffereable. * - * If SDRAM will be reconfigured, then we will defer setup of the framebuffer - * until after the SDRAM remapping (since the framebuffer problem resides) in - * SDRAM. + * If SDRAM will be reconfigured, then we will defer setup of the + * framebuffer until after the SDRAM remapping (since the framebuffer + * problem resides) in SDRAM. */ #if defined(CONFIG_SAMA5_LCDC) && !defined(NEED_SDRAM_REMAPPING) @@ -269,3 +272,7 @@ const struct section_mapping_s g_operational_mapping[] = const size_t g_num_opmappings = NREMAPPINGS; #endif /* NEED_SDRAM_REMAPPING */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/sama5/sama5d4x_periphclks.h b/arch/arm/src/sama5/sama5d4x_periphclks.h index 29e043a7436..8eb43210206 100644 --- a/arch/arm/src/sama5/sama5d4x_periphclks.h +++ b/arch/arm/src/sama5/sama5d4x_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/sama5/sama5d4x_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) @@ -267,19 +268,19 @@ #define sam_saic_isenabled() (true) #define sam_l2cc_isenabled() (true) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -290,9 +291,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samd2l2/chip.h b/arch/arm/src/samd2l2/chip.h index 554875f4214..a7690018220 100644 --- a/arch/arm/src/samd2l2/chip.h +++ b/arch/arm/src/samd2l2/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_H #define __ARCH_ARM_SRC_SAMD2L2_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,12 +31,14 @@ #include -/* Define the number of interrupt vectors that need to be supported for this chip */ +/* Define the number of interrupt vectors that need to be supported for this + * chip + */ #define ARMV6M_PERIPHERAL_INTERRUPTS 25 -/* Include the memory map file. Other chip hardware files should then include - * this file for the proper setup. +/* Include the memory map file. Other chip hardware files should then + * include this file for the proper setup. */ #if defined(CONFIG_ARCH_FAMILY_SAMD20) @@ -49,20 +51,20 @@ # error Unrecognized SAMD/L architecture #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd20_memorymap.h b/arch/arm/src/samd2l2/hardware/samd20_memorymap.h index 3b2e6a019fd..cece10823e4 100644 --- a/arch/arm/src/samd2l2/hardware/samd20_memorymap.h +++ b/arch/arm/src/samd2l2/hardware/samd20_memorymap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd20_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -26,17 +26,18 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ + /* System Memory Map */ #define SAM_FLASH_BASE 0x00000000 /* Embedded FLASH memory space (<= 256KB) */ @@ -98,16 +99,16 @@ #define SAM_DAC_BASE 0x42004800 /* Digital-to-Analog Converter */ #define SAM_PTC_BASE 0x42004c00 /* Peripheral Touch Controller */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd20_pinmap.h b/arch/arm/src/samd2l2/hardware/samd20_pinmap.h index d8f28b3fc0a..23c990b0c16 100644 --- a/arch/arm/src/samd2l2/hardware/samd20_pinmap.h +++ b/arch/arm/src/samd2l2/hardware/samd20_pinmap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd20_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -26,35 +26,38 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* GPIO pin definitions *********************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the SERCOM0 PAD0 on PA8, then the following definition should appear in - * the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. + * For example, if we wanted the SERCOM0 PAD0 on PA8, then the following + * definition should appear in the board.h header file for that board: * * #define PORT_SERCOM0_PAD0 PORT_SERCOM0_PAD0_1 * - * The driver will then automatically configure PA8 as the SERCOM0 PAD0 pin. + * The driver will then automatically configure PA8 as the SERCOM0 PAD0 + * pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* Analog comparator */ @@ -336,16 +339,16 @@ #define PORT_PTC_Y14 (PORT_FUNCB | PORTB | PORT_PIN8) #define PORT_PTC_Y15 (PORT_FUNCB | PORTB | PORT_PIN9) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd21_memorymap.h b/arch/arm/src/samd2l2/hardware/samd21_memorymap.h index be21a5c0e22..6901392ca08 100644 --- a/arch/arm/src/samd2l2/hardware/samd21_memorymap.h +++ b/arch/arm/src/samd2l2/hardware/samd21_memorymap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd21_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller @@ -26,17 +26,18 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ + /* System Memory Map */ #define SAM_FLASH_BASE 0x00000000 /* Embedded FLASH memory space (<= 256KB) */ @@ -103,16 +104,16 @@ #define SAM_PTC_BASE 0x42004c00 /* Peripheral Touch Controller */ #define SAM_I2S_BASE 0x42005000 /* Inter IC Sound */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd21_pinmap.h b/arch/arm/src/samd2l2/hardware/samd21_pinmap.h index af723c3f870..4ae16a20660 100644 --- a/arch/arm/src/samd2l2/hardware/samd21_pinmap.h +++ b/arch/arm/src/samd2l2/hardware/samd21_pinmap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd21_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller @@ -26,35 +26,37 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* GPIO pin definitions *********************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the SERCOM0 PAD0 on PA8, then the following definition should appear in - * the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. + * For example, if we wanted the SERCOM0 PAD0 on PA8, then the following + * definition should appear in the board.h header file for that board: * * #define PORT_SERCOM0_PAD0 PORT_SERCOM0_PAD0_1 * * The driver will then automatically configure PA8 as the SERCOM0 PAD0 pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* Analog comparator */ @@ -387,16 +389,16 @@ #define PORT_PTC_Y14 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN8) #define PORT_PTC_Y15 (PORT_PTC_FUNCB | PORTB | PORT_PTC_PIN9) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_ac.h b/arch/arm/src/samd2l2/hardware/samd_ac.h index a4a7b616350..b26a25610d8 100644 --- a/arch/arm/src/samd2l2/hardware/samd_ac.h +++ b/arch/arm/src/samd2l2/hardware/samd_ac.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_ac.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -35,14 +35,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -50,10 +50,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAMD21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* AC register offsets **********************************************************************/ + ****************************************************************************/ + +/* AC register offsets ******************************************************/ #define SAM_AC_CTRLA_OFFSET 0x0000 /* Control A Register */ #define SAM_AC_CTRLB_OFFSET 0x0001 /* Control B Register */ @@ -70,7 +71,7 @@ #define SAM_AC_SCALER0_OFFSET 0x0020 /* Scaler 0 Register */ #define SAM_AC_SCALER1_OFFSET 0x0021 /* Scaler 1 Register */ -/* AC register addresses *******************************************************************/ +/* AC register addresses ****************************************************/ #define SAM_AC_CTRLA (SAM_AC_BASE+SAM_AC_CTRLA_OFFSET) #define SAM_AC_CTRLB (SAM_AC_BASE+SAM_AC_CTRLB_OFFSET) @@ -87,7 +88,7 @@ #define SAM_AC_SCALER0 (SAM_AC_BASE+SAM_AC_SCALER0_OFFSET) #define SAM_AC_SCALER1 (SAM_AC_BASE+SAM_AC_SCALER1_OFFSET) -/* AC register bit definitions ************************************************************/ +/* AC register bit definitions **********************************************/ /* Control A Register */ @@ -109,8 +110,8 @@ #define AC_EVCTRL_COMPEI0 (1 << 8) /* Bit 8: Comparator 0 Event Input enable */ #define AC_EVCTRL_COMPEI1 (1 << 9) /* Bit 9: Comparator 1 Event Input enable */ -/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set - * Register, and Interrupt Flag Status and Clear Register +/* Common bit definitions for Interrupt Enable Clear Register, Interrupt + * Enable Set Register, and Interrupt Flag Status and Clear Register */ #define AC_INT_COMP0 (1 << 0) /* Bit 0: Comparator 0 */ @@ -193,17 +194,17 @@ #define AC_COMPCTRL_SCALER_MASK (0x3f) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_adc.h b/arch/arm/src/samd2l2/hardware/samd_adc.h index 4cdba8819cb..cef587fc1fa 100644 --- a/arch/arm/src/samd2l2/hardware/samd_adc.h +++ b/arch/arm/src/samd2l2/hardware/samd_adc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_adc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -34,14 +34,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -49,10 +49,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAMD21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* ADC register offsets ********************************************************************/ + ****************************************************************************/ + +/* ADC register offsets *****************************************************/ #define SAM_ADC_CTRLA_OFFSET 0x0000 /* Control A Register */ #define SAM_ADC_REFCTL_OFFSET 0x0001 /* Reference Control Register */ @@ -75,7 +76,7 @@ #define SAM_ADC_CALIB_OFFSET 0x0028 /* Calibration Register */ #define SAM_ADC_DBGCTRL_OFFSET 0x002A /* Debug Control Register */ -/* ADC register addresses ******************************************************************/ +/* ADC register addresses ***************************************************/ #define SAM_ADC_CTRLA (SAM_ADC_BASE + SAM_ADC_CTRLA_OFFSET) #define SAM_ADC_REFCTL (SAM_ADC_BASE + SAM_ADC_REFCTL_OFFSET) @@ -98,7 +99,7 @@ #define SAM_ADC_CALIB (SAM_ADC_BASE + SAM_ADC_CALIB_OFFSET) #define SAM_ADC_ADC_DBGCTRL (SAM_ADC_BASE + SAM_ADC_DBGCTRL_OFFSET) -/* ADC register bit definitions ************************************************************/ +/* ADC register bit definitions *********************************************/ /* Control A Register */ @@ -115,6 +116,7 @@ # define ADC_REFCTRL_REFSEL_INTVCC1 (2 << ADC_REFCTRL_REFSEL_OFFSET) /* 1/2 VDDANA (only for VDDANA > 2.0V) */ # define ADC_REFCTRL_REFSEL_VREFA (3 << ADC_REFCTRL_REFSEL_OFFSET) /* External reference */ # define ADC_REFCTRL_REFSEL_VREFB (4 << ADC_REFCTRL_REFSEL_OFFSET) /* External reference */ + #define ADC_REFCTRL_REFCOMP (1 << 7) /* Bit 7: Reference buffer offset compensation enable */ /* Average Control Register */ @@ -146,12 +148,13 @@ #define ADC_CTRLB_LEFTADJ (1 << 1) /* Bit 1: Left-adjusted result */ #define ADC_CTRLB_FREERUN (1 << 2) /* Bit 2: Free running mode */ #define ADC_CTRLB_CORREN (1 << 3) /* Bit 3: Digital correction logic enabled */ -#define ADC_CTRLB_RESSEL_OFFSET (4) /* Bit 5:4: Conversion result resolution */ +#define ADC_CTRLB_RESSEL_OFFSET (4) /* Bit 5:4: Conversion result resolution */ #define ADC_CTRLB_RESSEL_MASK (3 << ADC_CTRLB_RESSEL_OFFSET) # define ADC_CTRLB_RESSEL_12BIT (0 << ADC_CTRLB_RESSEL_OFFSET) /* 12-bit result */ # define ADC_CTRLB_RESSEL_16BIT (1 << ADC_CTRLB_RESSEL_OFFSET) /* For averaging mode output */ # define ADC_CTRLB_RESSEL_10BIT (2 << ADC_CTRLB_RESSEL_OFFSET) /* 10-bit result */ # define ADC_CTRLB_RESSEL_8BIT (3 << ADC_CTRLB_RESSEL_OFFSET) /* 8-bit result */ + #define ADC_CTRLB_PRESCALER_OFFSET (8) /* Bit 10:8: Prescaler configuration */ #define ADC_CTRLB_PRESCALER_MASK (7 << ADC_CTRLB_PRESCALER_OFFSET) # define ADC_CTRLB_PRESCALER_DIV4 (0 << ADC_CTRLB_PRESCALER_OFFSET) @@ -206,6 +209,7 @@ # define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (0x1A << ADC_INPUTCTRL_MUXPOS_OFFSET) /* 1/4 scaled core voltage */ # define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (0x1B << ADC_INPUTCTRL_MUXPOS_OFFSET) /* 1/4 scaled I/) supplly */ # define ADC_INPUTCTRL_MUXPOS_DAC (0x1C << ADC_INPUTCTRL_MUXPOS_OFFSET) /* DAC output */ + #define ADC_INPUTCTRL_MUXNEG_OFFSET (8) /* Bit 12:8: Negative mux input selection */ #define ADC_INPUTCTRL_MUXNEG_MASK (0x1F << ADC_INPUTCTRL_MUXNEG_OFFSET) # define ADC_INPUTCTRL_MUXNEG_AIN0 (0 << ADC_INPUTCTRL_MUXNEG_OFFSET) @@ -216,8 +220,9 @@ # define ADC_INPUTCTRL_MUXNEG_AIN5 (5 << ADC_INPUTCTRL_MUXNEG_OFFSET) # define ADC_INPUTCTRL_MUXNEG_AIN6 (6 << ADC_INPUTCTRL_MUXNEG_OFFSET) # define ADC_INPUTCTRL_MUXNEG_AIN7 (7 << ADC_INPUTCTRL_MUXNEG_OFFSET) -# define ADC_INPUTCTRL_MUXNEG_GND (0x18 << ADC_INPUTCTRL_MUXNEG_OFFSET) /* Internal ground */ +# define ADC_INPUTCTRL_MUXNEG_GND (0x18 << ADC_INPUTCTRL_MUXNEG_OFFSET) /* Internal ground */ # define ADC_INPUTCTRL_MUXNEG_IOGND (0x19 << ADC_INPUTCTRL_MUXNEG_OFFSET) /* I/O ground */ + #define ADC_INPUTCTRL_INPUTSCAN_OFFSET (16) /* Bit 19:16: Number of input channels included in scan */ #define ADC_INPUTCTRL_INPUTSCAN_MASK (0x0F << ADC_INPUTCTRL_INPUTSCAN_OFFSET) #define ADC_INPUTCTRL_INPUTOFFSET_OFFSET (20) /* Bit 23:20: Positive mux setting offset */ @@ -238,8 +243,9 @@ #define ADC_EVCTRL_RESRDYEO (1 << 4) /* Bit 4: Result ready event out */ #define ADC_EVCTRL_WINMONEO (1 << 5) /* Bit 5: Window monitor event out */ -/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set - * Register, and Interrupt Flag Status and Clear Register +/* Common bit definitions for Interrupt Enable Clear Register, + * Interrupt Enable Set Register, and Interrupt Flag Status and Clear + * Register */ #define ADC_INT_RESRDY (1 << 0) /* Bit 0: Result ready */ @@ -261,17 +267,17 @@ #define ADC_DBGCTRL_DBGRUN (1) /* Bit 0: Debug run */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_dac.h b/arch/arm/src/samd2l2/hardware/samd_dac.h index 15e8f401e7d..966bb3f8eb5 100644 --- a/arch/arm/src/samd2l2/hardware/samd_dac.h +++ b/arch/arm/src/samd2l2/hardware/samd_dac.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_dac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAMD21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* DAC register offsets ********************************************************************/ + ****************************************************************************/ + +/* DAC register offsets *****************************************************/ #define SAM_DAC_CTRLA_OFFSET 0x0000 /* Control A Register */ #define SAM_DAC_CTRLB_OFFSET 0x0001 /* Control B Register */ @@ -53,7 +54,7 @@ #define SAM_DAC_DATABUF0_OFFSET 0x000C /* Data Buffer DAC0 Register */ #define SAM_DAC_DATABUF1_OFFSET 0x000D /* Data Buffer DAC1 Register */ -/* DAC register addresses ******************************************************************/ +/* DAC register addresses ***************************************************/ #define SAM_DAC_CTRLA (SAM_DAC_BASE+SAM_DAC_CTRLA_OFFSET) #define SAM_DAC_CTRLB (SAM_DAC_BASE+SAM_DAC_CTRLB_OFFSET) @@ -67,7 +68,7 @@ #define SAM_DAC_DATABUF0 (SAM_DAC_BASE+SAM_DAC_DATABUF0_OFFSET) #define SAM_DAC_DATABUF1 (SAM_DAC_BASE+SAM_DAC_DATABUF1_OFFSET) -/* DAC register bit definitions ************************************************************/ +/* DAC register bit definitions *********************************************/ /* Control A Register */ @@ -93,8 +94,9 @@ #define DAC_EVCTRL_STARTEI (1 << 0) /* Bit 0: Start conversion event input */ #define DAC_EVCTRL_EMPTYEO (1 << 1) /* Bit 1: Data buffer empty event output */ -/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set - * Register, and Interrupt Flag Status and Clear Register +/* Common bit definitions for Interrupt Enable Clear Register, + * Interrupt Enable Set Register, + * and Interrupt Flag Status and Clear Register */ #define DAC_INT_UNDERRUN (1 << 0) /* Bit 0: Underrun interrupt */ @@ -106,17 +108,17 @@ #define DAC_STATUS_SYNCBUSY (1 << 7) /* Bit 0: Sync busy */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_dmac.h b/arch/arm/src/samd2l2/hardware/samd_dmac.h index 04dfb52f1f7..4a117f49b2b 100644 --- a/arch/arm/src/samd2l2/hardware/samd_dmac.h +++ b/arch/arm/src/samd2l2/hardware/samd_dmac.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,18 +26,19 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* DMAC register offsets ********************************************************************/ + ****************************************************************************/ + +/* DMAC register offsets ****************************************************/ #define SAM_DMAC_CTRL_OFFSET 0x0000 /* Control Register */ #define SAM_DMAC_CRCCTRL_OFFSET 0x0002 /* CRC Control Register */ @@ -71,7 +72,7 @@ #define SAM_LPSRAM_DSTADDR_OFFSET 0x0008 /* Block Transfer Destination Address Register */ #define SAM_LPSRAM_DESCADDR_OFFSET 0x000c /* Next Address Descriptor Register */ -/* DMAC register addresses ******************************************************************/ +/* DMAC register addresses **************************************************/ #define SAM_DMAC_CTRL (SAM_DMAC_BASE+SAM_DMAC_CTRL_OFFSET) #define SAM_DMAC_CRCCTRL (SAM_DMAC_BASE+SAM_DMAC_CRCCTRL_OFFSET) @@ -97,7 +98,7 @@ #define SAM_DMAC_CHINTFLAG (SAM_DMAC_BASE+SAM_DMAC_CHINTFLAG_OFFSET) #define SAM_DMAC_CHSTATUS (SAM_DMAC_BASE+SAM_DMAC_CHSTATUS_OFFSET) -/* DMAC register bit definitions ************************************************************/ +/* DMAC register bit definitions ********************************************/ /* Control Register */ @@ -116,10 +117,12 @@ # define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (0 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 8-bit bus transfer */ # define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (1 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 16-bit bus transfer */ # define DMAC_CRCCTRL_CRCBEATSIZE_WORD (2 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 32-bit bus transfer */ + #define DMAC_CRCCTRL_CRCPOLY_SHIFT (2) /* Bits 2-3: CRC polynomial type */ #define DMAC_CRCCTRL_CRCPOLY_MASK (3 < DMAC_CRCCTRL_CRCPOLY_SHIFT) # define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */ # define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */ + #define DMAC_CRCCTRL_CRCSRC_SHIFT (8) /* Bits 8-13: CRC Input Source */ #define DMAC_CRCCTRL_CRCSRC_MASK (0x3f < DMAC_CRCCTRL_CRCSRC_SHIFT) # define DMAC_CRCCTRL_CRCSRC_NOACTION (0 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* No action */ @@ -127,6 +130,7 @@ # define DMAC_CRCCTRL_CRCSRC_CHAN(n) (((uint32_t)(n) + 0x20) < DMAC_CRCCTRL_CRCSRC_SHIFT) /* CRC Data Input Register (32-bit value) */ + /* CRC Checksum Register (32-bit value) */ /* CRC Status Register */ @@ -146,12 +150,14 @@ # define DMAC_QOSCTRL_WRBQOS_LOW (1 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive bandwidth */ # define DMAC_QOSCTRL_WRBQOS_MEDIUM (2 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive latency */ # define DMAC_QOSCTRL_WRBQOS_HIGH (3 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Critical latency */ + #define DMAC_QOSCTRL_FQOS_SHIFT (2) /* Bits 2-3: Fetch quality of service */ #define DMAC_QOSCTRL_FQOS_MASK (3 << DMAC_QOSCTRL_FQOS_SHIFT) # define DMAC_QOSCTRL_FQOS_DISABLE (0 << DMAC_QOSCTRL_FQOS_SHIFT) /* Background */ # define DMAC_QOSCTRL_FQOS_LOW (1 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive bandwidth */ # define DMAC_QOSCTRL_FQOS_MEDIUM (2 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive latency */ # define DMAC_QOSCTRL_FQOS_HIGH (3 << DMAC_QOSCTRL_FQOS_SHIFT) /* Critical latency */ + #define DMAC_QOSCTRL_DQOS_SHIFT (4) /* Bits 4-5: Data transfer quality of service */ #define DMAC_QOSCTRL_DQOS_MASK (3 << DMAC_QOSCTRL_DQOS_SHIFT) # define DMAC_QOSCTRL_DQOS_DISABLE (0 << DMAC_QOSCTRL_DQOS_SHIFT) /* Background */ @@ -159,8 +165,9 @@ # define DMAC_QOSCTRL_DQOS_MEDIUM (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */ # define DMAC_QOSCTRL_DQOS_HIGH (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */ -/* Common bit definitions for: Software Trigger Control Register, Interrupt Status Register, - * Busy Channels Register, and Pending Channels Register +/* Common bit definitions for: Software Trigger Control Register, + * Interrupt Status Register, Busy Channels Register, and Pending Channels + * Register */ #define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-11 */ @@ -196,7 +203,9 @@ #define DMAC_INTPEND_PEND (1 << 15) /* Bit 15: Pending */ /* Interrupt Status Register */ + /* Busy Channels Register */ + /* Pending Channels Register */ /* Active Channels and Levels Register */ @@ -212,6 +221,7 @@ #define DMAC_ACTIVE_BTCNT_MASK (0xffff << DMAC_ACTIVE_BTCNT_SHIFT) /* Descriptor Memory Section Base Address Register (32-bit address) */ + /* Write-Back Memory Section Base Address Register (31-bit address) */ /* Channel ID Register */ @@ -229,12 +239,13 @@ #define DMAC_CHCTRLB_EVACT_MASK (7 << DMAC_CHCTRLB_EVACT_SHIFT) # define DMAC_CHCTRLB_EVACT_NOACT (0 << DMAC_CHCTRLB_EVACT_SHIFT) /* No action */ # define DMAC_CHCTRLB_EVACT_TRIG (1 << DMAC_CHCTRLB_EVACT_SHIFT) /* Normal Transfer and Conditional Transfer on Strobe -trigger */ + * trigger */ # define DMAC_CHCTRLB_EVACT_CTRIG (2 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional transfer trigger */ # define DMAC_CHCTRLB_EVACT_CBLOCK (3 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional block transfer */ # define DMAC_CHCTRLB_EVACT_SUSPEND (4 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel suspend operation */ # define DMAC_CHCTRLB_EVACT_RESUME (5 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel resume operation */ # define DMAC_CHCTRLB_EVACT_SSKIP (6 << DMAC_CHCTRLB_EVACT_SHIFT) /* Skip next block suspend action */ + #define DMAC_CHCTRLB_EVIE (1 << 3) /* Bit 3: Channel event input enable */ #define DMAC_CHCTRLB_EVOE (1 << 4) /* Bit 4: Channel event output enable */ #define DMAC_CHCTRLB_LVL_SHIFT (5) /* Bits 5-6: Channel arbitration level */ @@ -244,14 +255,16 @@ trigger */ # define DMAC_CHCTRLB_LVL_LVL1 (1 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 1 */ # define DMAC_CHCTRLB_LVL_LVL2 (2 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 2 */ # define DMAC_CHCTRLB_LVL_LVL3 (3 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 3 */ + #define DMAC_CHCTRLB_TRIGSRC_SHIFT (8) /* Bits 8-13: Trigger source */ #define DMAC_CHCTRLB_TRIGSRC_MASK (0x3f << DMAC_CHCTRLB_TRIGSRC_SHIFT) - #define DMAC_CHCTRLB_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLB_TRIGSRC_SHIFT) +# define DMAC_CHCTRLB_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLB_TRIGSRC_SHIFT) #define DMAC_CHCTRLB_TRIGACT_SHIFT (22) /* Bits 22-23: Trigger action */ #define DMAC_CHCTRLB_TRIGACT_MASK (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) # define DMAC_CHCTRLB_TRIGACT_BLOCK (0 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each action */ # define DMAC_CHCTRLB_TRIGACT_BEAT (2 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for beat transfer */ # define DMAC_CHCTRLB_TRIGACT_TRANSACT (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each transaction */ + #define DMAC_CHCTRLB_CMD_SHIFT (24) /* Bits 24-25: Software command */ #define DMAC_CHCTRLB_CMD_MASK (3 << DMAC_CHCTRLB_CMD_SHIFT) # define DMAC_CHCTRLB_CMD_NOACTION (0 << DMAC_CHCTRLB_CMD_SHIFT) /* No action */ @@ -271,7 +284,7 @@ trigger */ #define DMAC_TRIGSRC_SERCOM3_TX (8) /* SERCOM3 TX Trigger */ #define DMAC_TRIGSRC_SERCOM4_RX (9) /* SERCOM4 RX Trigger */ #define DMAC_TRIGSRC_SERCOM4_TX (10) /* SERCOM4 TX Trigger */ -#define DMAC_TRIGSRC_SERCOM5_RX (11) /* SERCOM4 RX Trigger */ +#define DMAC_TRIGSRC_SERCOM5_RX (11) /* SERCOM4 RX Trigger */ #define DMAC_TRIGSRC_SERCOM5_TX (12) /* SERCOM4 TX Trigger */ #define DMAC_TRIGSRC_TCC0_OVF (13) /* TCC0 Overflow Trigger */ #define DMAC_TRIGSRC_TCC0_MC0 (14) /* TCC0 Match/Compare 0 Trigger */ @@ -306,8 +319,9 @@ trigger */ #define DMAC_TRIGSRC_I2S0_TX (43) /* I2S0 TX Trigger */ #define DMAC_TRIGSRC_I2S1_TX (44) /* I2S1 TX Trigger */ -/* Common register bit definitions: Channel Interrupt Enable Clear Register, Channel Interrupt - * Enable Set Register, and Channel Interrupt Flag Status and Clear Register +/* Common register bit definitions: Channel Interrupt Enable Clear Register, + * Channel Interrupt Enable Set Register, and Channel Interrupt Flag Status + * and Clear Register */ #define DMAC_INT_TERR (1 << 0) /* Bit 0: Transfer error interrupt */ @@ -324,26 +338,29 @@ trigger */ /* Block Transfer Control Register */ #define LPSRAM_BTCTRL_VALID (1 << 0) /* Bit 0: Descriptor valid */ -#define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */ +#define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */ #define LPSRAM_BTCTRL_EVOSEL_MASK (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) # define LPSRAM_BTCTRL_EVOSEL_DISABLE (0 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event generation disabled */ # define LPSRAM_BTCTRL_EVOSEL_BLOCK (1 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when block transfer complete */ # define LPSRAM_BTCTRL_EVOSEL_BEAT (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when beat transfer complete */ + #define LPSRAM_BTCTRL_BLOCKACT_SHIFT (3) /* Bits 3-4: Block action */ #define LPSRAM_BTCTRL_BLOCKACT_MASK (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) # define LPSRAM_BTCTRL_BLOCKACT_NOACT (0 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer */ # define LPSRAM_BTCTRL_BLOCKACT_INT (1 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer + block int */ # define LPSRAM_BTCTRL_BLOCKACT_SUSPEND (2 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel suspend operation is completed */ # define LPSRAM_BTCTRL_BLOCKACT_BOTH (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Both channel suspend operation + block int */ + #define LPSRAM_BTCTRL_BEATSIZE_SHIFT (8) /* Bits 8-9: Beat size */ #define LPSRAM_BTCTRL_BEATSIZE_MASK (3 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) # define LPSRAM_BTCTRL_BEATSIZE_BYTE (0 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 8-bit bus transfer */ # define LPSRAM_BTCTRL_BEATSIZE_HWORD (1 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 16-bit bus transfer */ # define LPSRAM_BTCTRL_BEATSIZE_WORD (2 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 32-bit bus transfer */ + #define LPSRAM_BTCTRL_SRCINC (1 << 10) /* Bit 10: Source address increment enable */ #define LPSRAM_BTCTRL_DSTINC (1 << 11) /* Bit 11: Destination address increment enable */ #define LPSRAM_BTCTRL_STEPSEL (1 << 12) /* Bit 12: Step selection */ -#define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */ +#define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */ #define LPSRAM_BTCTRL_STEPSIZE_MASK (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) # define LPSRAM_BTCTRL_STEPSIZE_X1 (0 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */ # define LPSRAM_BTCTRL_STEPSIZE_X2 (1 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */ @@ -355,13 +372,17 @@ trigger */ # define LPSRAM_BTCTRL_STEPSIZE_X128 (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */ /* Block Transfer Count Register (16-bit count) */ + /* Block Transfer Source Address Register (32-bit address) */ + /* Block Transfer Destination Address Register (32-bit address) */ + /* Next Address Descriptor Register (32-bit address) */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ + /* DMA descriptor */ struct dma_desc_s @@ -373,12 +394,12 @@ struct dma_desc_s uint32_t descaddr; /* Next Address Descriptor Register */ }; -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_eic.h b/arch/arm/src/samd2l2/hardware/samd_eic.h index 45dce0276f4..19ccb9aae84 100644 --- a/arch/arm/src/samd2l2/hardware/samd_eic.h +++ b/arch/arm/src/samd2l2/hardware/samd_eic.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_eic.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Microchip SAMD21 datasheet" @@ -25,9 +25,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -35,10 +35,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAMD21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* EIC register offsets *********************************************************************/ + ****************************************************************************/ + +/* EIC register offsets *****************************************************/ #define SAM_EIC_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_EIC_STATUS_OFFSET 0x0001 /* Status register */ @@ -53,7 +54,7 @@ #define SAM_EIC_CONFIG1_OFFSET 0x001c /* Configuration 1 register */ #define SAM_EIC_CONFIG2_OFFSET 0x0020 /* Configuration 2 register */ -/* EIC register addresses *******************************************************************/ +/* EIC register addresses ***************************************************/ #define SAM_EIC_CTRLA (SAM_EIC_BASE+SAM_EIC_CTRLA_OFFSET) #define SAM_EIC_STATUS (SAM_EIC_BASE+SAM_EIC_STATUS_OFFSET) @@ -68,7 +69,7 @@ #define SAM_EIC_CONFIG1 (SAM_EIC_BASE+SAM_EIC_CONFIG1_OFFSET) #define SAM_EIC_CONFIG2 (SAM_EIC_BASE+SAM_EIC_CONFIG2_OFFSET) -/* EIC register bit definitions *************************************************************/ +/* EIC register bit definitions *********************************************/ /* Control A register */ @@ -89,14 +90,16 @@ # define EIC_NMICTRL_NMISENSE_BOTH (3 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Both edge detection */ # define EIC_NMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */ # define EIC_NMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */ + #define EIC_NMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */ /* Non-maskable interrupt flas status and clear register */ #define EIC_NMIFLAG_NMI (1 << 0) /* Non-maskable interrupt */ -/* Event control, Interrupt enable clear, interrupt enable set register, interrupt flag - * status and clear, and external interrupt wakeup registers. +/* Event control, Interrupt enable clear, interrupt enable set register, + * interrupt flag status and clear, and external interrupt wakeup + * registers. */ #define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */ @@ -159,17 +162,17 @@ # define EIC_CONFIG2_SENSE_HIGH(n) (4 << EIC_CONFIG2_SENSE_SHIFT(n)) /* High level detection */ # define EIC_CONFIG2_SENSE_LOW(n) (5 << EIC_CONFIG2_SENSE_SHIFT(n)) /* Low level detection */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_evsys.h b/arch/arm/src/samd2l2/hardware/samd_evsys.h index 41b79f4b3b6..88e1f08a7e4 100644 --- a/arch/arm/src/samd2l2/hardware/samd_evsys.h +++ b/arch/arm/src/samd2l2/hardware/samd_evsys.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_evsys.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* EVSYS register offsets *******************************************************************/ + ****************************************************************************/ + +/* EVSYS register offsets ***************************************************/ #define SAM_EVSYS_CTRL_OFFSET 0x0000 /* Control register */ #define SAM_EVSYS_CHANNEL_OFFSET 0x0004 /* Channel register */ @@ -49,7 +50,7 @@ #define SAM_EVSYS_INTENSET_OFFSET 0x0014 /* Interrupt enable set register */ #define SAM_EVSYS_INTFLAG_OFFSET 0x0018 /* Interrupt flag status and clear register */ -/* EVSYS register addresses *****************************************************************/ +/* EVSYS register addresses *************************************************/ #define SAM_EVSYS_CTRL (SAM_EVSYS_BASE+SAM_EVSYS_CTRL_OFFSET) #define SAM_EVSYS_CHANNEL (SAM_EVSYS_BASE+SAM_EVSYS_CHANNEL_OFFSET) @@ -59,7 +60,7 @@ #define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET) #define SAM_EVSYS_INTFLAG (SAM_EVSYS_BASE+SAM_EVSYS_INTFLAG_OFFSET) -/* EVSYS register bit definitions ***********************************************************/ +/* EVSYS register bit definitions *******************************************/ /* Control register */ @@ -220,6 +221,7 @@ # define EVSYS_CHANNEL_PATH_SYNCH (0 << EVSYS_CHANNEL_PATH_SHIFT) /* Synchronous path */ # define EVSYS_CHANNEL_PATH_RESYNCH (1 << EVSYS_CHANNEL_PATH_SHIFT) /* Resynchronized path */ # define EVSYS_CHANNEL_PATH_ASYNCH (2 << EVSYS_CHANNEL_PATH_SHIFT) /* Asynchronous path */ + #define EVSYS_CHANNEL_EDGSEL_SHIFT (26) /* Bits 26-27: Edge Detection Selection */ #define EVSYS_CHANNEL_EDGSEL_MASK (3 << EVSYS_CHANNEL_EDGSEL_SHIFT) # define EVSYS_CHANNEL_EDGSEL_NOEVT (0 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* No event output */ @@ -306,7 +308,9 @@ # define EVSYS_CHSTATUS_CHBUSYH(n) (1 << ((n) + 16)) #endif -/* Interrupt enable clear, interrupt enable set, and interrupt flag status and clear registers */ +/* Interrupt enable clear, interrupt enable set, + * and interrupt flag status and clear registers + */ #ifdef CONFIG_ARCH_FAMILY_SAMD20 # define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n=0-7 */ @@ -326,17 +330,17 @@ # define EVSYS_INT_EVD(n) (1 << ((n) + 16)) #endif -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_fuses.h b/arch/arm/src/samd2l2/hardware/samd_fuses.h index 7efe168b58c..3c8c7eec9ed 100644 --- a/arch/arm/src/samd2l2/hardware/samd_fuses.h +++ b/arch/arm/src/samd2l2/hardware/samd_fuses.h @@ -1,40 +1,36 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_fuses.h * * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * References: - * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller - * Datasheet", 42129J–SAM–12/2013 - * "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller - * Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015 * * Some fuse-related definitions derive from Atmel sample code: * * Copyright (c) 2013 Atmel Corporation. All rights reserved. * * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * modification, are permitted provided that the following conditions + * are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. + * 3. The name of Atmel may not be used to endorse or promote products + * derived from this software without specific prior written permission. * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. + * 4. This software may only be redistributed and used in connection with + * an Atmel microcontroller product. * * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, @@ -42,14 +38,21 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ + +/* References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller + * Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015 + */ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -57,10 +60,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* Fuse definitions *************************************************************************/ + ****************************************************************************/ + +/* Fuse definitions *********************************************************/ #ifdef CONFIG_ARCH_FAMILY_SAMD20 # define NVMCTRL_FUSES_LOCKFIELD_ADDR (SAM_LOCKBIT_BASE + 0) @@ -282,17 +286,17 @@ # define SYSCTRL_FUSES_DFLL48MFINE(n) ((n) << SYSCTRL_FUSES_DFLL48MFINE_SHIFT) #endif -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_gclk.h b/arch/arm/src/samd2l2/hardware/samd_gclk.h index b076bc8f06c..75b30e78b35 100644 --- a/arch/arm/src/samd2l2/hardware/samd_gclk.h +++ b/arch/arm/src/samd2l2/hardware/samd_gclk.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_gclk.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -28,9 +28,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -38,10 +38,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* GCLK register offsets ********************************************************************/ + ****************************************************************************/ + +/* GCLK register offsets ****************************************************/ #define SAM_GCLK_CTRL_OFFSET 0x0000 /* Control register */ #define SAM_GCLK_STATUS_OFFSET 0x0001 /* Status register */ @@ -49,7 +50,7 @@ #define SAM_GCLK_GENCTRL_OFFSET 0x0004 /* Generic clock generator control register */ #define SAM_GCLK_GENDIV_OFFSET 0x0008 /* Generic clock generator division register */ -/* GCLK register addresses ******************************************************************/ +/* GCLK register addresses **************************************************/ #define SAM_GCLK_CTRL (SAM_GCLK_BASE+SAM_GCLK_CTRL_OFFSET) #define SAM_GCLK_STATUS (SAM_GCLK_BASE+SAM_GCLK_STATUS_OFFSET) @@ -57,7 +58,7 @@ #define SAM_GCLK_GENCTRL (SAM_GCLK_BASE+SAM_GCLK_GENCTRL_OFFSET) #define SAM_GCLK_GENDIV (SAM_GCLK_BASE+SAM_GCLK_GENDIV_OFFSET) -/* GCLK register bit definitions ************************************************************/ +/* GCLK register bit definitions ********************************************/ /* Control register */ @@ -229,17 +230,17 @@ #define GCLK_GENDIV_DIV_MASK (0xffff << GCLK_GENDIV_DIV_SHIFT) # define GCLK_GENDIV_DIV(n) ((n) << GCLK_GENDIV_DIV_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_i2c_master.h b/arch/arm/src/samd2l2/hardware/samd_i2c_master.h index 848ad034a99..642952cca1c 100644 --- a/arch/arm/src/samd2l2/hardware/samd_i2c_master.h +++ b/arch/arm/src/samd2l2/hardware/samd_i2c_master.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_i2c_master.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -37,10 +37,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* I2C register offsets *********************************************************************/ + ****************************************************************************/ + +/* I2C register offsets *****************************************************/ #define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -66,7 +67,7 @@ # define SAM_I2C_DBGCTRL_OFFSET 0x0030 /* Debug control register */ #endif -/* I2C register addresses *******************************************************************/ +/* I2C register addresses ***************************************************/ #define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET) #define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET) @@ -164,7 +165,7 @@ #define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET) #define SAM_I2C5_DBGCTRL (SAM_SERCOM5_BASE+SAM_I2C_DBGCTRL_OFFSET) -/* I2C register bit definitions *************************************************************/ +/* I2C register bit definitions *********************************************/ /* Control A register */ @@ -173,10 +174,13 @@ #define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */ #define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT) # define I2C_CTRLA_MODE_MASTER (5 << I2C_CTRLA_MODE_SHIFT) /* I2C master mode */ + #define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Transmit data pinout */ + # define I2C_CTRLA_1WIRE (0) /* 4-wire operation disable */ # define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enable */ + #define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */ #define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT) # define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */ @@ -192,6 +196,7 @@ # define I2C_CTRLA_SPEED_STANDARD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard-mode (<=100 kHz) and Fast-mode (<=400 kHz) */ # define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode Plus (<=1 MHz) */ # define I2C_CTRLA_SPEED_HIGHSPEED (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4 MHz) */ + # define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */ #endif @@ -201,6 +206,7 @@ # define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */ # define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */ # define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */ + #define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */ /* Control B register */ @@ -213,7 +219,9 @@ # define I2C_CTRLB_CMD_ACKREP (1 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by repeated START */ # define I2C_CTRLB_CMD_ACKREAD (2 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by read operation */ # define I2C_CTRLB_CMD_ACKSTOP (3 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by STOP */ + #define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */ + # define I2C_CTRLB_ACK (0) /* Send ACK */ # define I2C_CTRLB_NACK I2C_CTRLB_ACKACT /* Send NACK */ @@ -235,8 +243,8 @@ # define I2C_HSBAUDLOW(n) (uint16)(n) << I2C_HSBAUDLOW_SHIFT #endif -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define I2C_INT_MB (1 << 0) /* Bit 0: Master on bus interrupt */ @@ -260,6 +268,7 @@ # define I2C_STATUS_BUSSTATE_IDLE (1 << I2C_STATUS_BUSSTATE_SHIFT) /* Waiting for transaction */ # define I2C_STATUS_BUSSTATE_OWNER (2 << I2C_STATUS_BUSSTATE_SHIFT) /* Master of bus owner */ # define I2C_STATUS_BUSSTATE_BUSY (3 << I2C_STATUS_BUSSTATE_SHIFT) /* Other master owns */ + #define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */ #define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */ @@ -311,17 +320,17 @@ #define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h b/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h index 26367f21a0b..95e086462a6 100644 --- a/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h +++ b/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_i2c_slave.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -37,10 +37,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAMD20 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* I2C register offsets *********************************************************************/ + ****************************************************************************/ + +/* I2C register offsets *****************************************************/ #define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -62,7 +63,7 @@ # define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */ #endif -/* I2C register addresses *******************************************************************/ +/* I2C register addresses ***************************************************/ #define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET) #define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET) @@ -148,7 +149,7 @@ #define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET) #define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET) -/* I2C register bit definitions *************************************************************/ +/* I2C register bit definitions *********************************************/ /* Control A register */ @@ -157,10 +158,13 @@ #define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */ #define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT) # define I2C_CTRLA_MODE_SLAVE (4 << I2C_CTRLA_MODE_SHIFT) /* I2C slave mode */ + #define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Transmit data pinout */ + # define I2C_CTRLA_1WIRE (0) /* 4-wire operation disable */ # define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enable */ + #define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */ #define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT) # define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */ @@ -175,6 +179,7 @@ # define I2C_CTRLA_SPEED_STANDARD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard-mode (<=100 kHz) and Fast-mode (<=400 kHz) */ # define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode Plus (<=1 MHz) */ # define I2C_CTRLA_SPEED_HIGHSPEED (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4 MHz) */ + # define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */ #endif @@ -194,17 +199,20 @@ # define I2C_CRLB_AMODE_MASK (0 << I2C_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */ # define I2C_CRLB_AMODE_2ADDRS (1 << I2C_CRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */ # define I2C_CRLB_AMODE_RANGE (2 << I2C_CRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */ + #define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */ #define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT) # define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */ # define I2C_CTRLB_CMD_WAITSTART (2 << I2C_CTRLB_CMD_SHIFT) /* ACK (write) wait for START */ # define I2C_CTRLB_CMD_ACKREAD (3 << I2C_CTRLB_CMD_SHIFT) /* ACK with read (context dependent) */ + #define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */ + # define I2C_CTRLB_ACK (0) /* Send ACK */ # define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define I2C_INT_PREC (1 << 0) /* Bit 0: Stop received interrupt */ @@ -273,17 +281,17 @@ #define I2C_DATA_MASK (0xooff) /* Bits 0-7: Data */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_i2s.h b/arch/arm/src/samd2l2/hardware/samd_i2s.h index 572e38faf88..e753262c075 100644 --- a/arch/arm/src/samd2l2/hardware/samd_i2s.h +++ b/arch/arm/src/samd2l2/hardware/samd_i2s.h @@ -1,12 +1,9 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_i2s.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Matt Thompson * - * References: - * "Microchip SAMD21 datasheet" - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -34,14 +31,18 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ + +/* References: + * "Microchip SAMD21 datasheet" + */ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -49,10 +50,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAMD21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* I2S register offsets *********************************************************************/ + ****************************************************************************/ + +/* I2S register offsets *****************************************************/ #define SAM_I2S_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_I2S_CLKCTRL0_OFFSET 0x0004 /* Clock Control 0 register */ @@ -66,7 +68,7 @@ #define SAM_I2S_DATA0_OFFSET 0x0030 /* Data 0 register */ #define SAM_I2S_DATA1_OFFSET 0x0034 /* Data 1 register */ -/* I2S register addresses ******************************************************************/ +/* I2S register addresses ***************************************************/ #define SAM_I2S_CTRLA (SAM_I2S_BASE+SAM_I2S_CTRLA_OFFSET) #define SAM_I2S_CLKCTRL0 (SAM_I2S_BASE+SAM_I2S_CLKCTRL0_OFFSET) @@ -80,7 +82,7 @@ #define SAM_I2S_DATA0 (SAM_I2S_BASE+SAM_I2S_DATA0_OFFSET) #define SAM_I2S_DATA1 (SAM_I2S_BASE+SAM_I2S_DATA1_OFFSET) -/* I2S register bit definitions ************************************************************/ +/* I2S register bit definitions *********************************************/ /* Control A register */ @@ -187,17 +189,17 @@ #define I2S_SERCTRL_DMA (1 << 25) /* Bit 25: Single or Multiple DMA channels */ #define I2S_SERCTRL_RXLOOP (1 << 26) /* Bit 26: RX Loopback Test Mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h b/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h index 7f1af891d6e..00c6131ad2b 100644 --- a/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h +++ b/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_nvmctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -28,9 +28,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -38,10 +38,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* NVMCTRL register offsets *****************************************************************/ + ****************************************************************************/ + +/* NVMCTRL register offsets *************************************************/ #define SAM_NVMCTRL_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_NVMCTRL_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -53,7 +54,7 @@ #define SAM_NVMCTRL_ADDR_OFFSET 0x001c /* Address register */ #define SAM_NVMCTRL_LOCK_OFFSET 0x0020 /* Lock section register */ -/* NVMCTRL register addresses ***************************************************************/ +/* NVMCTRL register addresses ***********************************************/ #define SAM_NVMCTRL_CTRLA (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLA_OFFSET) #define SAM_NVMCTRL_CTRLB (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLB_OFFSET) @@ -65,7 +66,7 @@ #define SAM_NVMCTRL_ADDR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_ADDR_OFFSET) #define SAM_NVMCTRL_LOCK (SAM_NVMCTRL_BASE+SAM_NVMCTRL_LOCK_OFFSET) -/* NVMCTRL register bit definitions *********************************************************/ +/* NVMCTRL register bit definitions *****************************************/ /* Control A register */ @@ -90,6 +91,7 @@ # define NVMCTRL_CTRLA_CMD_PBC (0x44 << NVMCTRL_CTRLA_CMD_SHIFT) /* Page Buffer Clear */ # define NVMCTRL_CTRLA_CMD_SSB (0x45 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set Security Bit */ # define NVMCTRL_CTRLA_CMD_INVALL (0x46 << NVMCTRL_CTRLA_CMD_SHIFT) /* Invalidate all cache lines */ + #define NVMCTRL_CTRLA_CMDEX_SHIFT (8) /* Bits 8-15: Command Execution */ #define NVMCTRL_CTRLA_CMDEX_MASK (0xff << NVMCTRL_CTRLA_CMDEX_SHIFT) # define NVMCTRL_CTRLA_CMDEX (0xa5 << NVMCTRL_CTRLA_CMDEX_SHIFT) @@ -105,11 +107,13 @@ # define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (0 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power on first access */ # define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (1 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power when exit sleep */ # define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Auto power reduction disabled */ + #define NVMCTRL_CTRLB_READMODE_SHIFT (16) /* Bits 16-17: NVMCTRL Read Mode */ #define NVMCTRL_CTRLB_READMODE_MASK (3 << NVMCTRL_CTRLB_READMODE_SHIFT) # define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (0 << NVMCTRL_CTRLB_READMODE_SHIFT) /* No extra wait states on miss */ # define NVMCTRL_CTRLB_READMODE_LOW_POWER (1 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Insert wait/reduce power */ # define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (2 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Same wait on all access */ + #define NVMCTRL_CTRLB_CACHEDIS (1 << 18) /* Bit 18: Cache Disable */ /* NVM parameter register */ @@ -134,7 +138,9 @@ #endif /* Interrupt clear register */ + /* Interrupt set register */ + /* Interface flags status and clear register */ #define NVMCTRL_INT_READY (1 << 0) /* Bit 0: NVM Ready Interrupt */ @@ -157,17 +163,17 @@ #define NVMCTRL_LOCK_REGION(n) (1 << (n)) /* Region n is locked */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_pm.h b/arch/arm/src/samd2l2/hardware/samd_pm.h index 69ae1df01bd..7935af34914 100644 --- a/arch/arm/src/samd2l2/hardware/samd_pm.h +++ b/arch/arm/src/samd2l2/hardware/samd_pm.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_pm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -28,9 +28,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -38,10 +38,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* PM register offsets ********************************************************************/ + ****************************************************************************/ + +/* PM register offsets ******************************************************/ #define SAM_PM_CTRL_OFFSET 0x0000 /* Control register */ #define SAM_PM_SLEEP_OFFSET 0x0001 /* Sleep mode register */ @@ -58,7 +59,7 @@ #define SAM_PM_INTFLAG_OFFSET 0x0036 /* Interrupt flag status and clear register */ #define SAM_PM_RCAUSE_OFFSET 0x0038 /* Reset cause register */ -/* PM register addresses ******************************************************************/ +/* PM register addresses ****************************************************/ #define SAM_PM_CTRL (SAM_PM_BASE+SAM_PM_CTRL_OFFSET) #define SAM_PM_SLEEP (SAM_PM_BASE+SAM_PM_SLEEP_OFFSET) @@ -75,7 +76,7 @@ #define SAM_PM_INTFLAG (SAM_PM_BASE+SAM_PM_INTFLAG_OFFSET) #define SAM_PM_RCAUSE (SAM_PM_BASE+SAM_PM_RCAUSE_OFFSET) -/* PM register bit definitions ************************************************************/ +/* PM register bit definitions **********************************************/ /* Control register */ @@ -217,7 +218,9 @@ # define PM_APBCMASK_I2S (1 << 20) /* Bit 20: Inter IC Sound */ #endif -/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */ +/* Interrupt enable clear, Interrupt enable set, + * and Interrupt flag status and clear registers + */ #define PM_INT_CKRDY (1 << 0) /* Bit 0: Clock Ready Interrupt */ @@ -234,17 +237,17 @@ #define PM_RCAUSE_WDT (1 << 5) /* Bit 5: Watchdog Reset */ #define PM_RCAUSE_SYST (1 << 6) /* Bit 6: System Reset Request */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_port.h b/arch/arm/src/samd2l2/hardware/samd_port.h index 658182e3ad3..6f85a7822f5 100644 --- a/arch/arm/src/samd2l2/hardware/samd_port.h +++ b/arch/arm/src/samd2l2/hardware/samd_port.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_port.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -28,9 +28,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -38,10 +38,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* PORT register offsets ********************************************************************/ + ****************************************************************************/ + +/* PORT register offsets ****************************************************/ #define SAM_PORTA (0) #define SAM_PORTB (1) @@ -114,7 +115,7 @@ #define SAM_PORT_PINCFG30_OFFSET 0x005e /* Pin configuration register 30 */ #define SAM_PORT_PINCFG31_OFFSET 0x005f /* Pin configuration register 31 */ -/* PORT register addresses ******************************************************************/ +/* PORT register addresses **************************************************/ #define SAM_PORTN_BASE(n) (SAM_PORT_BASE+SAM_PORTN_OFFSET(n)) #define SAM_PORTA_BASE (SAM_PORT_BASE+SAM_PORTA_OFFSET) @@ -248,16 +249,16 @@ #define SAM_PORTB_PINCFG30 (SAM_PORTB_BASE+SAM_PORT_PINCFG30_OFFSET) #define SAM_PORTB_PINCFG31 (SAM_PORTB_BASE+SAM_PORT_PINCFG31_OFFSET) -/* PORT register bit definitions ************************************************************/ +/* PORT register bit definitions ********************************************/ -/* Data direction, data direction clear, data direction set, and data direction toggle - * registers +/* Data direction, data direction clear, data direction set, and data + * direction toggle registers */ #define PORT_DIR(n) (1 << n) /* Port data n, direction, n=0-31 */ -/* Data output value, data output value clear, data output value set, and data output - * value toggle registers +/* Data output value, data output value clear, data output value set, + * and data output value toggle registers */ #define PORT_OUT(n) (1 << n) /* Port data n output value, n=0-31 */ @@ -304,17 +305,17 @@ #define PORT_PINCFG_PULLEN (1 << 2) /* Bit 2: Pull Enable */ #define PORT_PINCFG_DRVSTR (1 << 6) /* Bit 6: Output Driver Strength Selection */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_sercom.h b/arch/arm/src/samd2l2/hardware/samd_sercom.h index e7ed3cc4b89..10d935c3ca2 100644 --- a/arch/arm/src/samd2l2/hardware/samd_sercom.h +++ b/arch/arm/src/samd2l2/hardware/samd_sercom.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_sercom.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -26,26 +26,29 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* Two generic clocks are used by the SERCOM: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The - * core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a - * master, while the slow clock (GCLK_SERCOM_SLOW) is only required for certain functions. + ****************************************************************************/ + +/* Two generic clocks are used by the SERCOM: GCLK_SERCOMx_CORE and + * GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to + * clock the SERCOM while operating as a master, while the slow clock + * (GCLK_SERCOM_SLOW) is only required for certain functions. * SERCOM modules must share the same slow GCLK channel ID. * - * The baud-rate generator runs off the GCLK_SERCOMx_CORE clock (or, optionally, external - * clock). + * The baud-rate generator runs off the GCLK_SERCOMx_CORE clock + * (or, optionally, external clock). * - * These definitions must match the GCLK_CLKCTRL_ID_* values defined in samd_gclk.c. + * These definitions must match the GCLK_CLKCTRL_ID_* values defined in + * samd_gclk.c. */ #ifdef CONFIG_ARCH_FAMILY_SAMD20 @@ -70,16 +73,16 @@ # define SERCOM5_GCLK_ID_CORE 25 #endif -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_spi.h b/arch/arm/src/samd2l2/hardware/samd_spi.h index 8a0d0c220e0..9b8b7fb5ab8 100644 --- a/arch/arm/src/samd2l2/hardware/samd_spi.h +++ b/arch/arm/src/samd2l2/hardware/samd_spi.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -37,10 +37,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* SPI register offsets *********************************************************************/ + ****************************************************************************/ + +/* SPI register offsets *****************************************************/ #define SAM_SPI_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_SPI_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -66,7 +67,7 @@ # define SAM_SPI_DBGCTRL_OFFSET 0x0030 /* Debug control register */ #endif -/* SPI register addresses *******************************************************************/ +/* SPI register addresses ***************************************************/ #define SAM_SPI0_CTRLA (SAM_SERCOM0_BASE+SAM_SPI_CTRLA_OFFSET) #define SAM_SPI0_CTRLB (SAM_SERCOM0_BASE+SAM_SPI_CTRLB_OFFSET) @@ -164,7 +165,7 @@ #define SAM_SPI5_DATA (SAM_SERCOM5_BASE+SAM_SPI_DATA_OFFSET) #define SAM_SPI4_DBGCTRL (SAM_SERCOM4_BASE+SAM_SPI_DBGCTRL_OFFSET) -/* SPI register bit definitions *************************************************************/ +/* SPI register bit definitions *********************************************/ /* Control A register */ @@ -174,24 +175,29 @@ #define SPI_CTRLA_MODE_MASK (7 << SPI_CTRLA_MODE_SHIFT) # define SPI_CTRLA_MODE_SLAVE (2 << SPI_CTRLA_MODE_SHIFT) /* SPI slave operation */ # define SPI_CTRLA_MODE_MASTER (3 << SPI_CTRLA_MODE_SHIFT) /* SPI master operation */ + #define SPI_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define SPI_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ #define SPI_CTRLA_DOPO_SHIFT (16) /* Bit 16-17: Data out pinout */ + #define SPI_CTRLA_DOPO_MASK (3 << SPI_CTRLA_DOPO_SHIFT) /* Bit 16-17: Data out pinout */ # define SPI_CTRLA_DOPO_DOPAD012 (0 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD1 SS=PAD2 */ # define SPI_CTRLA_DOPO_DOPAD231 (1 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD2 SCK=PAD3 SS=PAD1 */ # define SPI_CTRLA_DOPO_DOPAD312 (2 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD3 SCK=PAD1 SS=PAD2 */ # define SPI_CTRLA_DOPO_DOPAD031 (3 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD3 SS=PAD1 */ + #define SPI_CTRLA_DIPO_SHIFT (20) /* Bits 20-21: Data in pinout */ #define SPI_CTRLA_DIPO_MASK (3 << SPI_CTRLA_DIPO_SHIFT) # define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD0 for DI */ # define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD1 for DI */ # define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD2 for DI */ # define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD3 for DI */ + #define SPI_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */ #define SPI_CTRLA_FORM_MASK (7 << SPI_CTRLA_FORM_SHIFT) # define SPI_CTRLA_FORM_SPI (0 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (no address) */ # define SPI_CTRLA_FORM_ADDR (2 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (w/address) */ + #define SPI_CTRLA_CPHA (1 << 28) /* Bit 28: Clock phase */ #define SPI_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */ #define SPI_CTRLA_DORD (1 << 30) /* Bit 30: Data order */ @@ -204,6 +210,7 @@ #define SPI_CTRLB_CHSIZE_MASK (7 << SPI_CTRLB_CHSIZE_SHIFT) # define SPI_CTRLB_CHSIZE_8BITS (0 << SPI_CTRLB_CHSIZE_SHIFT) /* 8 bits */ # define SPI_CTRLB_CHSIZE_9BITS (1 << SPI_CTRLB_CHSIZE_SHIFT) /* 9 bits */ + #define SPI_CTRLB_PLOADEN (1 << 6) /* Bit 6: Slave Data Preload Enable */ #ifdef CONFIG_ARCH_FAMILY_SAMD21 @@ -216,12 +223,13 @@ # define SPI_CTRLB_AMODE_ADDRMASK (0 << SPI_CTRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */ # define SPI_CTRLB_AMODE_2ADDRS (1 << SPI_CTRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */ # define SPI_CTRLB_AMODE_RANGE (2 << SPI_CTRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */ + #define SPI_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */ /* Baud register (8-bit baud value) */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define SPI_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */ @@ -276,17 +284,17 @@ #define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_sysctrl.h b/arch/arm/src/samd2l2/hardware/samd_sysctrl.h index 22b49c65c40..20dd512b9e7 100644 --- a/arch/arm/src/samd2l2/hardware/samd_sysctrl.h +++ b/arch/arm/src/samd2l2/hardware/samd_sysctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_sysctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -28,9 +28,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -38,10 +38,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* SYSCTRL register offsets *****************************************************************/ + ****************************************************************************/ + +/* SYSCTRL register offsets *************************************************/ #define SAM_SYSCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */ #define SAM_SYSCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */ @@ -71,7 +72,7 @@ # define SAM_SYSCTRL_DPLLSTATUS_OFFSET 0x0050 /* DPLL status */ #endif -/* SYSCTRL register addresses ***************************************************************/ +/* SYSCTRL register addresses ***********************************************/ #define SAM_SYSCTRL_INTENCLR (SAM_SYSCTRL_BASE+SAM_SYSCTRL_INTENCLR_OFFSET) #define SAM_SYSCTRL_INTENSET (SAM_SYSCTRL_BASE+SAM_SYSCTRL_INTENSET_OFFSET) @@ -101,10 +102,10 @@ # define SAM_SYSCTRL_DPLLSTATUS (SAM_SYSCTRL_BASE+SAM_SYSCTRL_DPLLSTATUS_OFFSET) #endif -/* SYSCTRL register bit definitions *********************************************************/ +/* SYSCTRL register bit definitions *****************************************/ -/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and - * Power and clocks status registers. +/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and + * clear, and Power and clocks status registers. */ #define SYSCTRL_INT_XOSCRDY (1 << 0) /* Bit 0: XOSC ready interrupt */ @@ -148,6 +149,7 @@ # define SYSCTRL_XOSC_GAIN_8MHZ (2 << SYSCTRL_XOSC_GAIN_SHIFT) /* 8MHz */ # define SYSCTRL_XOSC_GAIN_16MHZ (3 << SYSCTRL_XOSC_GAIN_SHIFT) /* 16MHz */ # define SYSCTRL_XOSC_GAIN_30MHZ (4 << SYSCTRL_XOSC_GAIN_SHIFT) /* 30MHz */ + #define SYSCTRL_XOSC_AMPGC (1 << 11) /* Bit 11: Automatic amplitude gain control */ #define SYSCTRL_XOSC_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */ #define SYSCTRL_XOSC_STARTUP_MASK (15 << SYSCTRL_XOSC_STARTUP_SHIFT) @@ -189,6 +191,7 @@ # define SYSCTRL_XOSC32K_STARTUP_1S (5 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1000092µs */ # define SYSCTRL_XOSC32K_STARTUP_2S (6 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 2000092µs */ # define SYSCTRL_XOSC32K_STARTUP_4S (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 4000092µs */ + #define SYSCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */ /* 32kHz internal oscillator control register */ @@ -213,6 +216,7 @@ # define SYSCTRL_OSC32K_STARTUP_1MS (5 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */ # define SYSCTRL_OSC32K_STARTUP_2MS (6 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */ # define SYSCTRL_OSC32K_STARTUP_4MS (7 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */ + #define SYSCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */ #define SYSCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */ #define SYSCTRL_OSC32K_CALIB_MASK (0x7f << SYSCTRL_OSC32K_CALIB_SHIFT) @@ -237,6 +241,7 @@ # define SYSCTRL_OSC8M_PRESC_DIV2 (1 << SYSCTRL_OSC8M_PRESC_SHIFT) /* 2 */ # define SYSCTRL_OSC8M_PRESC_DIV3 (2 << SYSCTRL_OSC8M_PRESC_SHIFT) /* 4 */ # define SYSCTRL_OSC8M_PRESC_DIV8 (3 << SYSCTRL_OSC8M_PRESC_SHIFT) /* 8 */ + #define SYSCTRL_OSC8M_CALIB_SHIFT (16) /* Bits 16-27: Oscillator calibration */ #define SYSCTRL_OSC8M_CALIB_MASK (0xfff << SYSCTRL_OSC8M_CALIB_SHIFT) # define SYSCTRL_OSC8M_CALIB(n) ((n) << SYSCTRL_OSC8M_CALIB_SHIFT) @@ -307,6 +312,7 @@ # define SYSCTRL_BOD33_ACTION_NONE (0 << SYSCTRL_BOD33_ACTION_SHIFT) /* No action */ # define SYSCTRL_BOD33_ACTION_RESET (1 << SYSCTRL_BOD33_ACTION_SHIFT) /* BOD33 generates reset */ # define SYSCTRL_BOD33_ACTION_INTR (2 << SYSCTRL_BOD33_ACTION_SHIFT) /* BOD33 generates interrupt */ + #define SYSCTRL_BOD33_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define SYSCTRL_BOD33_MODE (1 << 8) /* Bit 8: Operation mode */ #define SYSCTRL_BOD33_CEN (1 << 9) /* Bit 9: Clock enable */ @@ -329,6 +335,7 @@ # define SYSCTRL_BOD33_PSEL_DIV16K (13 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 16384 */ # define SYSCTRL_BOD33_PSEL_DIV32K (14 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 32768 */ # define SYSCTRL_BOD33_PSEL_DIV64K (15 << SYSCTRL_BOD33_PSEL_SHIFT) /* Divide clock by 65536 */ + #define SYSCTRL_BOD33_LEVEL_SHIFT (16) /* Bits 16-21: BOD33 threshold level */ #define SYSCTRL_BOD33_LEVEL_MASK (0x3f << SYSCTRL_BOD33_LEVEL_SHIFT) # define SYSCTRL_BOD33_LEVEL(n) ((n) << SYSCTRL_BOD33_LEVEL_SHIFT) @@ -376,6 +383,7 @@ # define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (1 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* Low bandwidth filter */ # define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (2 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* High bandwidth filter */ # define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (3 << SYSCTRL_DPLLCTRLB_FILTER_SHIFT) /* High damping filter */ + # define SYSCTRL_DPLLCTRLB_LPEN (1 << 2) /* Bit 2: Low-Power Enable */ # define SYSCTRL_DPLLCTRLB_WUF (1 << 3) /* Bit 3: Wake Up Fast */ # define SYSCTRL_DPLLCTRLB_REFCLK_SHIFT (4) /* Bits 4-5: Reference Clock Selection */ @@ -383,6 +391,7 @@ # define SYSCTRL_DPLLCTRLB_REFCLK_XOSC32 (0 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* XOSC32 clock reference */ # define SYSCTRL_DPLLCTRLB_REFCLK_XOSC (1 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* XOSC clock reference */ # define SYSCTRL_DPLLCTRLB_REFCLK_GCLKDPLL (2 << SYSCTRL_DPLLCTRLB_REFCLK_SHIFT) /* GCLK_DPLL clock reference */ + # define SYSCTRL_DPLLCTRLB_LTIME_SHIFT (8) /* Bits 8-10: Lock Time */ # define SYSCTRL_DPLLCTRLB_LTIME_MASK (7 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) # define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (0 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* No time-out */ @@ -390,6 +399,7 @@ # define SYSCTRL_DPLLCTRLB_LTIME_9MS (5 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 9 ms */ # define SYSCTRL_DPLLCTRLB_LTIME_10MS (6 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 10 ms */ # define SYSCTRL_DPLLCTRLB_LTIME_11MS (7 << SYSCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no lock within 11 ms */ + # define SYSCTRL_DPLLCTRLB_LBYPASS (1 << 12) /* Bit 12: Lock Bypass */ # define SYSCTRL_DPLLCTRLB_DIV_SHIFT (16) /* Bits 16-26: */ # define SYSCTRL_DPLLCTRLB_DIV_MASK (0x7ff << SYSCTRL_DPLLCTRLB_DIV_SHIFT) @@ -405,17 +415,17 @@ # define SYSCTRL_DPLLSTATUS_DIV (1 << 3) /* Bit 3: Divider Enable */ #endif -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_tc.h b/arch/arm/src/samd2l2/hardware/samd_tc.h index 15fa1e2f144..4c1f47f90a9 100644 --- a/arch/arm/src/samd2l2/hardware/samd_tc.h +++ b/arch/arm/src/samd2l2/hardware/samd_tc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_tc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -34,14 +34,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -49,10 +49,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAMD21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* TC register offsets *********************************************************************/ + ****************************************************************************/ + +/* TC register offsets ******************************************************/ #define SAM_TC_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_TC_READREQ_OFFSET 0x0002 /* Read request register */ @@ -69,7 +70,7 @@ #define SAM_TC_CC0_OFFSET 0x0018 /* Capture Compare 0 register */ #define SAM_TC_CC1_OFFSET 0x001C /* Capture Compare 1 register */ -/* TC register addresses *******************************************************************/ +/* TC register addresses ****************************************************/ #define SAM_TC3_CTRLA (SAM_TC3_BASE+SAM_TC_CTRLA_OFFSET) #define SAM_TC3_READREQ (SAM_TC3_BASE+SAM_TC_READREQ_OFFSET) @@ -146,7 +147,7 @@ #define SAM_TC7_CC0 (SAM_TC7_BASE+SAM_TC_CC0_OFFSET) #define SAM_TC7_CC1 (SAM_TC7_BASE+SAM_TC_CC1_OFFSET) -/* TC register bit definitions *************************************************************/ +/* TC register bit definitions **********************************************/ /* Control A register */ @@ -238,17 +239,17 @@ #define TC_STATUS_SLAVE (1 << 4) #define TC_STATUS_SYNCBUSY (1 << 7) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_tcc.h b/arch/arm/src/samd2l2/hardware/samd_tcc.h index 7a9ebaa22f6..14895a73860 100644 --- a/arch/arm/src/samd2l2/hardware/samd_tcc.h +++ b/arch/arm/src/samd2l2/hardware/samd_tcc.h @@ -1,12 +1,9 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_tcc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Matt Thompson * - * References: - * "Microchip SAMD21 datasheet" - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -34,14 +31,18 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ + +/* References: + * "Microchip SAMD21 datasheet" + */ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -49,10 +50,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAMD21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* TCC register offsets *********************************************************************/ + ****************************************************************************/ + +/* TCC register offsets *****************************************************/ #define SAM_TCC_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_TCC_CTRLBCLR_OFFSET 0x0004 /* Control B clear register */ @@ -84,7 +86,7 @@ #define SAM_TCC_CCB2_OFFSET 0x0078 /* Capture Compare B0 register */ #define SAM_TCC_CCB3_OFFSET 0x007C /* Capture Compare B0 register */ -/* TC register addresses *******************************************************************/ +/* TC register addresses ****************************************************/ #define SAM_TCC0_CTRLA (SAM_TCC0_BASE+SAM_TCC_CTRLA_OFFSET) #define SAM_TCC0_CTRLBCLR (SAM_TCC0_BASE+SAM_TCC_CTRLBCLR_OFFSET) @@ -176,7 +178,7 @@ #define SAM_TCC2_CCB2 (SAM_TCC2_BASE+SAM_TCC_CCB2_OFFSET) #define SAM_TCC2_CCB3 (SAM_TCC2_BASE+SAM_TCC_CCB3_OFFSET) -/* TC register bit definitions *************************************************************/ +/* TC register bit definitions **********************************************/ /* Control A register */ @@ -447,17 +449,17 @@ #define TCC_VALUE_SHIFT (6) #define TCC_VALUE_MASK (0x3ff << TCC_VALUE_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_usart.h b/arch/arm/src/samd2l2/hardware/samd_usart.h index 61e64ed0ff7..4bad8d3a127 100644 --- a/arch/arm/src/samd2l2/hardware/samd_usart.h +++ b/arch/arm/src/samd2l2/hardware/samd_usart.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_usart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -28,9 +28,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -39,10 +39,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* USART register offsets *******************************************************************/ + ****************************************************************************/ + +/* USART register offsets ***************************************************/ #define SAM_USART_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_USART_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -67,8 +68,7 @@ # define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */ #endif - -/* USART register addresses *****************************************************************/ +/* USART register addresses *************************************************/ #define SAM_USART0_CTRLA (SAM_SERCOM0_BASE+SAM_USART_CTRLA_OFFSET) #define SAM_USART0_CTRLB (SAM_SERCOM0_BASE+SAM_USART_CTRLB_OFFSET) @@ -190,7 +190,7 @@ #define SAM_USART5_DATA (SAM_SERCOM5_BASE+SAM_USART_DATA_OFFSET) #define SAM_USART5_DBGCTRL (SAM_SERCOM5_BASE+SAM_USART_DBGCTRL_OFFSET) -/* USART register bit definitions ***********************************************************/ +/* USART register bit definitions *******************************************/ /* Control A register */ @@ -200,6 +200,7 @@ #define USART_CTRLA_MODE_MASK (7 << USART_CTRLA_MODE_SHIFT) # define USART_CTRLA_MODE_EXTUSART (0 << USART_CTRLA_MODE_SHIFT) /* USART with external clock */ # define USART_CTRLA_MODE_INTUSART (1 << USART_CTRLA_MODE_SHIFT) /* USART with internal clock */ + /* Bits 5-6: reserved */ #define USART_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ @@ -218,6 +219,7 @@ # define USART_CTRLA_SAMPR_8XA (2 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; arithmetic baud */ # define USART_CTRLA_SAMPR_8XF (3 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; fractional baud */ # define USART_CTRLA_SAMPR_3XA (4 << USART_CTRLA_SAMPR_SHIFT) /* 3x oversampling; arithmetic baud */ + # define USART_CTRLA_TXPO_SHIFT (16) /* Bits 16-17: Transmit data pinout */ # define USART_CTRLA_TXPO_MASK (3 << USART_CTRLA_TXPO_SHIFT) # define USART_CTRLA_TXPAD0_1 (0 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[0]; XCK=PAD[1] */ @@ -255,8 +257,10 @@ # define USART_CTRLA_ASYNCH (0) # define USART_CTRLA_SYNCH USART_CTRLA_CMODE #define USART_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */ + # define USART_CTRLA_CPOL_NORMAL (0) /* Rising XCK edge Falling XCK edge */ # define USART_CTRLA_CPOL_INVERTED USART_CTRLA_CPOL /* Falling XCK edge Rising XCK edge */ + #define USART_CTRLA_DORD (1 << 30) /* Bit 30: Data order */ # define USART_CTRLA_MSBFIRST (0) # define USART_CTRLA_LSBFIRST USART_CTRLA_DORD @@ -270,6 +274,7 @@ # define USART_CTRLB_CHSIZE_5BITS (5 << USART_CTRLB_CHSIZE_SHIFT) /* 5 bits */ # define USART_CTRLB_CHSIZE_6BITS (6 << USART_CTRLB_CHSIZE_SHIFT) /* 6 bits */ # define USART_CTRLB_CHSIZE_7BITS (7 << USART_CTRLB_CHSIZE_SHIFT) /* 7 bits */ + #define USART_CTRLB_SBMODE (1 << 6) /* Bit 6: Stop bit mode */ # define USART_CTRLB_SBMODE_1 (0) # define USART_CTRLB_SBMODE_2 USART_CTRLB_SBMODE @@ -293,6 +298,7 @@ #define USART_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */ /* Baud register (For SAMD20, this is a 16-bit baud value) */ + /* For SAMD20 or for SAMD21 with SAMPR[0]=0 */ #define USART_BAUD_SHIFT (0) /* Bits 0-15: Baud Value */ @@ -312,8 +318,8 @@ /* Receive pulse length register (8-bit value) */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define USART_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */ @@ -364,17 +370,17 @@ #define USART_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H */ diff --git a/arch/arm/src/samd2l2/hardware/samd_wdt.h b/arch/arm/src/samd2l2/hardware/samd_wdt.h index 9e5db78a169..52c2aed9df5 100644 --- a/arch/arm/src/samd2l2/hardware/samd_wdt.h +++ b/arch/arm/src/samd2l2/hardware/samd_wdt.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/samd_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* WDT register offsets *********************************************************************/ + ****************************************************************************/ + +/* WDT register offsets *****************************************************/ #define SAM_WDT_CTRL_OFFSET 0x0000 /* Control register */ #define SAM_WDT_CONFIG_OFFSET 0x0001 /* Configuration register */ @@ -50,7 +51,7 @@ #define SAM_WDT_STATUS_OFFSET 0x0007 /* Status register */ #define SAM_WDT_CLEAR_OFFSET 0x0008 /* Clear register */ -/* WDT register addresses *******************************************************************/ +/* WDT register addresses ***************************************************/ #define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET) #define SAM_WDT_CONFIG (SAM_WDT_BASE+SAM_WDT_CONFIG_OFFSET) @@ -61,7 +62,7 @@ #define SAM_WDT_STATUS (SAM_WDT_BASE+SAM_WDT_STATUS_OFFSET) #define SAM_WDT_CLEAR (SAM_WDT_BASE+SAM_WDT_CLEAR_OFFSET) -/* WDT register bit definitions *************************************************************/ +/* WDT register bit definitions *********************************************/ /* Control register */ @@ -73,30 +74,31 @@ #define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */ #define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT) -# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */ -# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */ -# define WDT_CONFIG_PER_32 (2 << WDT_CONFIG_PER_SHIFT) /* 32 clock cycles */ -# define WDT_CONFIG_PER_64 (3 << WDT_CONFIG_PER_SHIFT) /* 64 clock cycles */ -# define WDT_CONFIG_PER_128 (4 << WDT_CONFIG_PER_SHIFT) /* 128 clock cycles */ -# define WDT_CONFIG_PER_256 (5 << WDT_CONFIG_PER_SHIFT) /* 256 clocks cycles */ -# define WDT_CONFIG_PER_512 (6 << WDT_CONFIG_PER_SHIFT) /* 512 clocks cycles */ -# define WDT_CONFIG_PER_1K (7 << WDT_CONFIG_PER_SHIFT) /* 1024 clock cycles */ -# define WDT_CONFIG_PER_2K (8 << WDT_CONFIG_PER_SHIFT) /* 2048 clock cycles */ -# define WDT_CONFIG_PER_4K (9 << WDT_CONFIG_PER_SHIFT) /* 4096 clock cycles */ +# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */ +# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */ +# define WDT_CONFIG_PER_32 (2 << WDT_CONFIG_PER_SHIFT) /* 32 clock cycles */ +# define WDT_CONFIG_PER_64 (3 << WDT_CONFIG_PER_SHIFT) /* 64 clock cycles */ +# define WDT_CONFIG_PER_128 (4 << WDT_CONFIG_PER_SHIFT) /* 128 clock cycles */ +# define WDT_CONFIG_PER_256 (5 << WDT_CONFIG_PER_SHIFT) /* 256 clocks cycles */ +# define WDT_CONFIG_PER_512 (6 << WDT_CONFIG_PER_SHIFT) /* 512 clocks cycles */ +# define WDT_CONFIG_PER_1K (7 << WDT_CONFIG_PER_SHIFT) /* 1024 clock cycles */ +# define WDT_CONFIG_PER_2K (8 << WDT_CONFIG_PER_SHIFT) /* 2048 clock cycles */ +# define WDT_CONFIG_PER_4K (9 << WDT_CONFIG_PER_SHIFT) /* 4096 clock cycles */ # define WDT_CONFIG_PER_8k (10 << WDT_CONFIG_PER_SHIFT) /* 8192 clock cycles */ # define WDT_CONFIG_PER_16K (11 << WDT_CONFIG_PER_SHIFT) /* 16384 clock cycles */ + #define WDT_CONFIG_WINDOW_SHIFT (4) /* Bits 4-7: Window Mode Time-Out Period */ #define WDT_CONFIG_WINDOW_MASK (15 << WDT_CONFIG_WINDOW_SHIFT) -# define WDT_CONFIG_WINDOW_8 (0 << WDT_CONFIG_WINDOW_SHIFT) /* 8 clock cycles */ -# define WDT_CONFIG_WINDOW_16 (1 << WDT_CONFIG_WINDOW_SHIFT) /* 16 clock cycles */ -# define WDT_CONFIG_WINDOW_32 (2 << WDT_CONFIG_WINDOW_SHIFT) /* 32 clock cycles */ -# define WDT_CONFIG_WINDOW_64 (3 << WDT_CONFIG_WINDOW_SHIFT) /* 64 clock cycles */ -# define WDT_CONFIG_WINDOW_128 (4 << WDT_CONFIG_WINDOW_SHIFT) /* 128 clock cycles */ -# define WDT_CONFIG_WINDOW_256 (5 << WDT_CONFIG_WINDOW_SHIFT) /* 256 clocks cycles */ -# define WDT_CONFIG_WINDOW_512 (6 << WDT_CONFIG_WINDOW_SHIFT) /* 512 clocks cycles */ -# define WDT_CONFIG_WINDOW_1K (7 << WDT_CONFIG_WINDOW_SHIFT) /* 1024 clock cycles */ -# define WDT_CONFIG_WINDOW_2K (8 << WDT_CONFIG_WINDOW_SHIFT) /* 2048 clock cycles */ -# define WDT_CONFIG_WINDOW_4K (9 << WDT_CONFIG_WINDOW_SHIFT) /* 4096 clock cycles */ +# define WDT_CONFIG_WINDOW_8 (0 << WDT_CONFIG_WINDOW_SHIFT) /* 8 clock cycles */ +# define WDT_CONFIG_WINDOW_16 (1 << WDT_CONFIG_WINDOW_SHIFT) /* 16 clock cycles */ +# define WDT_CONFIG_WINDOW_32 (2 << WDT_CONFIG_WINDOW_SHIFT) /* 32 clock cycles */ +# define WDT_CONFIG_WINDOW_64 (3 << WDT_CONFIG_WINDOW_SHIFT) /* 64 clock cycles */ +# define WDT_CONFIG_WINDOW_128 (4 << WDT_CONFIG_WINDOW_SHIFT) /* 128 clock cycles */ +# define WDT_CONFIG_WINDOW_256 (5 << WDT_CONFIG_WINDOW_SHIFT) /* 256 clocks cycles */ +# define WDT_CONFIG_WINDOW_512 (6 << WDT_CONFIG_WINDOW_SHIFT) /* 512 clocks cycles */ +# define WDT_CONFIG_WINDOW_1K (7 << WDT_CONFIG_WINDOW_SHIFT) /* 1024 clock cycles */ +# define WDT_CONFIG_WINDOW_2K (8 << WDT_CONFIG_WINDOW_SHIFT) /* 2048 clock cycles */ +# define WDT_CONFIG_WINDOW_4K (9 << WDT_CONFIG_WINDOW_SHIFT) /* 4096 clock cycles */ # define WDT_CONFIG_WINDOW_8k (10 << WDT_CONFIG_WINDOW_SHIFT) /* 8192 clock cycles */ # define WDT_CONFIG_WINDOW_16K (11 << WDT_CONFIG_WINDOW_SHIFT) /* 16384 clock cycles */ @@ -104,20 +106,22 @@ #define WDT_EWCTRL_EWOFFSET_SHIFT (0) /* Bits 0-3: Early warning interrupt time offset */ #define WDT_EWCTRL_EWOFFSET_MASK (15 << WDT_EWCTRL_EWOFFSET_SHIFT) -# define WDT_EWCTRL_EWOFFSET_8 (0 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_16 (1 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_32 (2 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 32 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_64 (3 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 64 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_128 (4 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 128 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_256 (5 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 256 clocks cycles */ -# define WDT_EWCTRL_EWOFFSET_512 (6 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 512 clocks cycles */ -# define WDT_EWCTRL_EWOFFSET_1K (7 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 1024 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_2K (8 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 2048 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_4K (9 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 4096 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_8 (0 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_16 (1 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_32 (2 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 32 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_64 (3 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 64 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_128 (4 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 128 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_256 (5 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 256 clocks cycles */ +# define WDT_EWCTRL_EWOFFSET_512 (6 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 512 clocks cycles */ +# define WDT_EWCTRL_EWOFFSET_1K (7 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 1024 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_2K (8 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 2048 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_4K (9 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 4096 clock cycles */ # define WDT_EWCTRL_EWOFFSET_8k (10 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8192 clock cycles */ # define WDT_EWCTRL_EWOFFSET_16K (11 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16384 clock cycles */ -/* Interrupt enable clear, interrupt enable set register, interrupt flag status and clear registers */ +/* Interrupt enable clear, interrupt enable set register, + * interrupt flag status and clear registers + */ #define WDT_INT_EW (1 << 0) /* Bit 0: Early warning interrupt */ #define WDT_INT_All (0x01) @@ -132,17 +136,17 @@ #define WDT_CLEAR_CLEAR_MASK (0xff << WDT_CLEAR_CLEAR_SHIFT) # define WDT_CLEAR_CLEAR (0xa5 << WDT_CLEAR_CLEAR_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml21_memorymap.h b/arch/arm/src/samd2l2/hardware/saml21_memorymap.h index 7c0830fccab..3b1b47dabe8 100644 --- a/arch/arm/src/samd2l2/hardware/saml21_memorymap.h +++ b/arch/arm/src/samd2l2/hardware/saml21_memorymap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml21_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,17 +26,18 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ + /* System Memory Map */ #define SAM_FLASH_BASE 0x00000000 /* Embedded FLASH memory space (<= 256KB) */ @@ -113,16 +114,16 @@ #define SAM_PAC_BASE 0x44000000 /* Peripheral Access Controller */ #define SAM_DMAC_BASE 0x44000400 /* DMA Controller */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml21_pinmap.h b/arch/arm/src/samd2l2/hardware/saml21_pinmap.h index 4eebb298db1..3e3582c9cb7 100644 --- a/arch/arm/src/samd2l2/hardware/saml21_pinmap.h +++ b/arch/arm/src/samd2l2/hardware/saml21_pinmap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml21_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,35 +26,38 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* GPIO pin definitions *********************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the SERCOM0 PAD0 on PA8, then the following definition should appear in - * the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if we wanted the SERCOM0 PAD0 on PA8, then the following + * definition should appear in the board.h header file for that board: * * #define PORT_SERCOM0_PAD0 PORT_SERCOM0_PAD0_1 * - * The driver will then automatically configure PA8 as the SERCOM0 PAD0 pin. + * The driver will then automatically configure PA8 as the SERCOM0 PAD0 + * pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! + * Just the basics are defined for most pins in this file. */ /* Analog comparator */ @@ -440,16 +443,16 @@ #define PORT_USB_DP (PORT_FUNCG | PORTA | PORT_PIN25) #define PORT_USB_SOF (PORT_FUNCG | PORTA | PORT_PIN23) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_adc.h b/arch/arm/src/samd2l2/hardware/saml_adc.h index 48aaf7a3889..af3b2cd8539 100644 --- a/arch/arm/src/samd2l2/hardware/saml_adc.h +++ b/arch/arm/src/samd2l2/hardware/saml_adc.h @@ -1,12 +1,9 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_adc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Alexander Vasiljev * - * References: - * "Microchip SAM L21 Family Datasheet", Rev A - 02/2017 - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -34,14 +31,18 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ + +/* References: + * "Microchip SAM L21 Family Datasheet", Rev A - 02/2017 + */ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_ADC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_ADC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -49,10 +50,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* ADC register offsets ********************************************************************/ + ****************************************************************************/ + +/* ADC register offsets *****************************************************/ #define SAM_ADC_CTRLA_OFFSET 0x0000 /* Control A Register */ #define SAM_ADC_CTRLB_OFFSET 0x0001 /* Control B Register */ @@ -77,7 +79,7 @@ #define SAM_ADC_SEQCTRL_OFFSET 0x0028 /* Sequence Control Register */ #define SAM_ADC_CALIB_OFFSET 0x002C /* Calibration Register */ -/* ADC register addresses ******************************************************************/ +/* ADC register addresses ***************************************************/ #define SAM_ADC_CTRLA (SAM_ADC_BASE + SAM_ADC_CTRLA_OFFSET) #define SAM_ADC_CTRLB (SAM_ADC_BASE + SAM_ADC_CTRLB_OFFSET) diff --git a/arch/arm/src/samd2l2/hardware/saml_aes.h b/arch/arm/src/samd2l2/hardware/saml_aes.h index f82e453f9d1..6daee552fe7 100644 --- a/arch/arm/src/samd2l2/hardware/saml_aes.h +++ b/arch/arm/src/samd2l2/hardware/saml_aes.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_aes.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* AES register offsets ********************************************************************/ + ****************************************************************************/ + +/* AES register offsets *****************************************************/ #define SAM_AES_CTRLA_OFFSET 0x0000 /* Control A Register */ #define SAM_AES_CTRLB_OFFSET 0x0004 /* Control B Register */ @@ -75,7 +76,7 @@ #define SAM_AES_CIPLEN_OFFSET 0x0070 /* Cipher Length Register */ #define SAM_AES_RANDSEED_OFFSET 0x0074 /* Random Seed Register */ -/* AES register addresses ******************************************************************/ +/* AES register addresses ***************************************************/ #define SAM_AES_CTRLA (SAM_AES_BASE+SAM_AES_CTRLA_OFFSET) #define SAM_AES_CTRLB (SAM_AES_BASE+SAM_AES_CTRLB_OFFSET) @@ -111,7 +112,7 @@ #define SAM_AES_CIPLEN (SAM_AES_BASE+SAM_AES_CIPLEN_OFFSET) #define SAM_AES_RANDSEED (SAM_AES_BASE+SAM_AES_RANDSEED_OFFSET) -/* AES register bit definitions ************************************************************/ +/* AES register bit definitions *********************************************/ /* Control A Register */ @@ -126,6 +127,7 @@ # define AES_CTRLA_AESMODE_CNTR (4 << AES_CTRLA_AESMODE_SHIFT) /* Counter mode */ # define AES_CTRLA_AESMODE_CCM (5 << AES_CTRLA_AESMODE_SHIFT) /* CCM mode */ # define AES_CTRLA_AESMODE_GCM (6 << AES_CTRLA_AESMODE_SHIFT) /* Galois counter mode */ + #define AES_CTRLA_CFBS_SHIFT (5) /* Bits 5-7: Cipher feedback block size */ #define AES_CTRLA_CFBS_MASK (7 << AES_CTRLA_CFBS_SHIFT) # define AES_CTRLA_CFBS_128 (0 << AES_CTRLA_CFBS_SHIFT) /* 128-bit data block */ @@ -133,11 +135,13 @@ # define AES_CTRLA_CFBS_32 (2 << AES_CTRLA_CFBS_SHIFT) /* 32-bit data block */ # define AES_CTRLA_CFBS_16 (3 << AES_CTRLA_CFBS_SHIFT) /* 16-bit data block */ # define AES_CTRLA_CFBS_8 (4 << AES_CTRLA_CFBS_SHIFT) /* 8-bit data block */ + #define AES_CTRLA_KEYSIZE_SHIFT (8) /* Bits 8-9: Encryption key size */ #define AES_CTRLA_KEYSIZE_MASK (3 << AES_CTRLA_KEYSIZE_SHIFT) # define AES_CTRLA_KEYSIZE_128 (0 << AES_CTRLA_KEYSIZE_SHIFT) /* 128-bit key */ # define AES_CTRLA_KEYSIZE_192 (1 << AES_CTRLA_KEYSIZE_SHIFT) /* 192-bit key */ # define AES_CTRLA_KEYSIZE_256 (2 << AES_CTRLA_KEYSIZE_SHIFT) /* 256-bit key */ + #define AES_CTRLA_CIPHER (1 << 10) /* Bit 10: Cipher */ #define AES_CTRLA_STARTMODE (1 << 11) /* Bit 11: Start mode select */ #define AES_CTRLA_LOD (1 << 12) /* Bit 12: Last output data mode */ @@ -157,8 +161,8 @@ #define AES_CTRLB_EOM (1 << 2) /* Bit 2: End of message */ #define AES_CTRLB_GFMUL (1 << 3) /* Bit 3: GF multiplication */ -/* Common Bit Definitions for the Interrupt Enable Clear Register, Interrupt Enable Set - * Register, and Interrupt Flag Status and Clear Register +/* Common Bit Definitions for the Interrupt Enable Clear Register, Interrupt + * Enable Set Register, and Interrupt Flag Status and Clear Register */ #define AES_INT_ENCCMP (1 << 0) /* Bit 0: Encryption complete interrupt */ @@ -174,24 +178,30 @@ #define AES_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */ /* Keyword n Register, n = 0-7 (32-value) */ + /* Data Register (32-bit value) */ + /* Initialization Vector n Register, n=0-3 (32-bit value) */ + /* Hash Key n Register, n=0-3 (32-bit value) */ + /* Galois Hash n Register, n=0-3 (32-bit value) */ + /* Cipher Length Register (32-bit vaoue) */ + /* Random Seed Register (32-bit value) */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_dac.h b/arch/arm/src/samd2l2/hardware/saml_dac.h index 4261ddfb020..ab8b9287dbd 100644 --- a/arch/arm/src/samd2l2/hardware/saml_dac.h +++ b/arch/arm/src/samd2l2/hardware/saml_dac.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_dac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* DAC register offsets ********************************************************************/ + ****************************************************************************/ + +/* DAC register offsets *****************************************************/ #define SAM_DAC_CTRLA_OFFSET 0x0000 /* Control A Register */ #define SAM_DAC_CTRLB_OFFSET 0x0001 /* Control B Register */ @@ -57,7 +58,7 @@ #define SAM_DAC_DATABUF1_OFFSET 0x0016 /* Data Buffer DAC1 Register */ #define SAM_DAC_DBCTRL_OFFSET 0x0017 /* Debug Control Register */ -/* DAC register addresses ******************************************************************/ +/* DAC register addresses ***************************************************/ #define SAM_DAC_CTRLA (SAM_DAC_BASE+SAM_DAC_CTRLA_OFFSET) #define SAM_DAC_CTRLB (SAM_DAC_BASE+SAM_DAC_CTRLB_OFFSET) @@ -75,7 +76,7 @@ #define SAM_DAC_DATABUF1 (SAM_DAC_BASE+SAM_DAC_DATABUF1_OFFSET) #define SAM_DAC_DBCTRL (SAM_DAC_BASE+SAM_DAC_DBCTRL_OFFSET) -/* DAC register bit definitions ************************************************************/ +/* DAC register bit definitions *********************************************/ /* Control A Register */ @@ -101,8 +102,9 @@ #define DAC_EVCTRL_INVEI0 (1 << 4) /* Bit 4: Enable inversion of DAC0 input event */ #define DAC_EVCTRL_INVEI1 (1 << 5) /* Bit 5: Enable inversion of DAC1 input event */ -/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set - * Register, and Interrupt Flag Status and Clear Register +/* Common bit definitions for Interrupt Enable Clear Register, + * Interrupt Enable Set Register, + * and Interrupt Flag Status and Clear Register */ #define DAC_INT_UNDERRUN0 (1 << 0) /* Bit 0: Underrun interrupt for DAC2 */ @@ -136,6 +138,7 @@ # define DAC_DACCTRL_CCTRL_CC100K (0 << DAC_DACCTRL_CCTRL_SHIFT) /* GCLK_DAC <= 1.2MHz */ # define DAC_DACCTRL_CCTRL_CC1M (1 << DAC_DACCTRL_CCTRL_SHIFT) /* 1.2MHz < GCLK_DAC <= 6MHz */ # define DAC_DACCTRL_CCTRL_CC2M (2 << DAC_DACCTRL_CCTRL_SHIFT) /* 6MHz < GCLK_DAC <= 12MHz */ + #define DAC_DACCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define DAC_DACCTRL_DITHER (1 << 7) /* Bit 7: Dithering mode */ #define DAC_DACCTRL_REFRESH_SHIFT (8) /* Bit 8-11: Refresh period */ @@ -143,23 +146,24 @@ # define DAC_DACCTRL_REFRESH(n) ((uin16_t)(n) << DAC_DACCTRL_REFRESH_SHIFT) /* Data DAC0/1 Register (16-bit data) */ + /* Data Buffer DAC0/1 Register (16-bit data) */ /* Debug Control Register */ #define DAC_DBCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_dmac.h b/arch/arm/src/samd2l2/hardware/saml_dmac.h index e000f28be9d..bdbec2fbcfa 100644 --- a/arch/arm/src/samd2l2/hardware/saml_dmac.h +++ b/arch/arm/src/samd2l2/hardware/saml_dmac.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* DMAC register offsets ********************************************************************/ + ****************************************************************************/ + +/* DMAC register offsets ****************************************************/ #define SAM_DMAC_CTRL_OFFSET 0x0000 /* Control Register */ #define SAM_DMAC_CRCCTRL_OFFSET 0x0002 /* CRC Control Register */ @@ -73,7 +74,7 @@ #define SAM_LPSRAM_DSTADDR_OFFSET 0x0008 /* Block Transfer Destination Address Register */ #define SAM_LPSRAM_DESCADDR_OFFSET 0x000c /* Next Address Descriptor Register */ -/* DMAC register addresses ******************************************************************/ +/* DMAC register addresses **************************************************/ #define SAM_DMAC_CTRL (SAM_DMAC_BASE+SAM_DMAC_CTRL_OFFSET) #define SAM_DMAC_CRCCTRL (SAM_DMAC_BASE+SAM_DMAC_CRCCTRL_OFFSET) @@ -99,7 +100,7 @@ #define SAM_DMAC_CHINTFLAG (SAM_DMAC_BASE+SAM_DMAC_CHINTFLAG_OFFSET) #define SAM_DMAC_CHSTATUS (SAM_DMAC_BASE+SAM_DMAC_CHSTATUS_OFFSET) -/* DMAC register bit definitions ************************************************************/ +/* DMAC register bit definitions ********************************************/ /* Control Register */ @@ -117,10 +118,12 @@ # define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (0 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 8-bit bus transfer */ # define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (1 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 16-bit bus transfer */ # define DMAC_CRCCTRL_CRCBEATSIZE_WORD (2 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 32-bit bus transfer */ + #define DMAC_CRCCTRL_CRCPOLY_SHIFT (2) /* Bits 2-3: CRC polynomial type */ #define DMAC_CRCCTRL_CRCPOLY_MASK (3 < DMAC_CRCCTRL_CRCPOLY_SHIFT) # define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */ # define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */ + #define DMAC_CRCCTRL_CRCSRC_SHIFT (8) /* Bits 8-13: CRC Input Source */ #define DMAC_CRCCTRL_CRCSRC_MASK (0x3f < DMAC_CRCCTRL_CRCSRC_SHIFT) # define DMAC_CRCCTRL_CRCSRC_NOACTION (0 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* No action */ @@ -128,6 +131,7 @@ # define DMAC_CRCCTRL_CRCSRC_CHAN(n) (((uint32_t)(n) + 0x20) < DMAC_CRCCTRL_CRCSRC_SHIFT) /* CRC Data Input Register (32-bit value) */ + /* CRC Checksum Register (32-bit value) */ /* CRC Status Register */ @@ -147,12 +151,14 @@ # define DMAC_QOSCTRL_WRBQOS_LOW (1 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive bandwidth */ # define DMAC_QOSCTRL_WRBQOS_MEDIUM (2 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Sensitive latency */ # define DMAC_QOSCTRL_WRBQOS_HIGH (3 << DMAC_QOSCTRL_WRBQOS_SHIFT) /* Critical latency */ + #define DMAC_QOSCTRL_FQOS_SHIFT (2) /* Bits 2-3: Fetch quality of service */ #define DMAC_QOSCTRL_FQOS_MASK (3 << DMAC_QOSCTRL_FQOS_SHIFT) # define DMAC_QOSCTRL_FQOS_DISABLE (0 << DMAC_QOSCTRL_FQOS_SHIFT) /* Background */ # define DMAC_QOSCTRL_FQOS_LOW (1 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive bandwidth */ # define DMAC_QOSCTRL_FQOS_MEDIUM (2 << DMAC_QOSCTRL_FQOS_SHIFT) /* Sensitive latency */ # define DMAC_QOSCTRL_FQOS_HIGH (3 << DMAC_QOSCTRL_FQOS_SHIFT) /* Critical latency */ + #define DMAC_QOSCTRL_DQOS_SHIFT (4) /* Bits 4-5: Data transfer quality of service */ #define DMAC_QOSCTRL_DQOS_MASK (3 << DMAC_QOSCTRL_DQOS_SHIFT) # define DMAC_QOSCTRL_DQOS_DISABLE (0 << DMAC_QOSCTRL_DQOS_SHIFT) /* Background */ @@ -160,8 +166,9 @@ # define DMAC_QOSCTRL_DQOS_MEDIUM (2 << DMAC_QOSCTRL_DQOS_SHIFT) /* Sensitive latency */ # define DMAC_QOSCTRL_DQOS_HIGH (3 << DMAC_QOSCTRL_DQOS_SHIFT) /* Critical latency */ -/* Common bit definitions for: Software Trigger Control Register, Interrupt Status Register, - * Busy Channels Register, and Pending Channels Register +/* Common bit definitions for: Software Trigger Control Register, + * Interrupt Status Register, Busy Channels Register, and Pending Channels + * Register */ #define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-15 */ @@ -204,6 +211,7 @@ #define DMAC_ACTIVE_BTCNT_MASK (0xffff << DMAC_ACTIVE_BTCNT_SHIFT) /* Descriptor Memory Section Base Address Register (32-bit address) */ + /* Write-Back Memory Section Base Address Register (31-bit address) */ /* Channel ID Register */ @@ -222,12 +230,13 @@ #define DMAC_CHCTRLB_EVACT_MASK (7 << DMAC_CHCTRLB_EVACT_SHIFT) # define DMAC_CHCTRLB_EVACT_NOACT (0 << DMAC_CHCTRLB_EVACT_SHIFT) /* No action */ # define DMAC_CHCTRLB_EVACT_TRIG (1 << DMAC_CHCTRLB_EVACT_SHIFT) /* Normal Transfer and Conditional Transfer on Strobe -trigger */ + * trigger */ # define DMAC_CHCTRLB_EVACT_CTRIG (2 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional transfer trigger */ # define DMAC_CHCTRLB_EVACT_CBLOCK (3 << DMAC_CHCTRLB_EVACT_SHIFT) /* Conditional block transfer */ # define DMAC_CHCTRLB_EVACT_SUSPEND (4 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel suspend operation */ # define DMAC_CHCTRLB_EVACT_RESUME (5 << DMAC_CHCTRLB_EVACT_SHIFT) /* Channel resume operation */ # define DMAC_CHCTRLB_EVACT_SSKIP (6 << DMAC_CHCTRLB_EVACT_SHIFT) /* Skip next block suspend action */ + #define DMAC_CHCTRLB_EVIE (1 << 3) /* Bit 3: Channel event input enable */ #define DMAC_CHCTRLB_EVOE (1 << 4) /* Bit 4: Channel event output enable */ #define DMAC_CHCTRLB_LVL_SHIFT (5) /* Bits 5-6: Channel arbitration level */ @@ -237,14 +246,17 @@ trigger */ # define DMAC_CHCTRLB_LVL_LVL1 (1 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 1 */ # define DMAC_CHCTRLB_LVL_LVL2 (2 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 2 */ # define DMAC_CHCTRLB_LVL_LVL3 (3 << DMAC_CHCTRLB_LVL_SHIFT) /* Channel priority level 3 */ + #define DMAC_CHCTRLB_TRIGSRC_SHIFT (8) /* Bits 8-13: Trigger source */ #define DMAC_CHCTRLB_TRIGSRC_MASK (0x3f << DMAC_CHCTRLB_TRIGSRC_SHIFT) - #define DMAC_CHCTRLB_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLB_TRIGSRC_SHIFT) +# define DMAC_CHCTRLB_TRIGSRC(n) ((uint32_t)(n) << DMAC_CHCTRLB_TRIGSRC_SHIFT) + #define DMAC_CHCTRLB_TRIGACT_SHIFT (22) /* Bits 22-23: Trigger action */ #define DMAC_CHCTRLB_TRIGACT_MASK (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) # define DMAC_CHCTRLB_TRIGACT_BLOCK (0 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each action */ # define DMAC_CHCTRLB_TRIGACT_BEAT (2 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for beat transfer */ # define DMAC_CHCTRLB_TRIGACT_TRANSACT (3 << DMAC_CHCTRLB_TRIGACT_SHIFT) /* One trigger required for each transaction */ + #define DMAC_CHCTRLB_CMD_SHIFT (24) /* Bits 24-25: Software command */ #define DMAC_CHCTRLB_CMD_MASK (3 << DMAC_CHCTRLB_CMD_SHIFT) # define DMAC_CHCTRLB_CMD_NOACTION (0 << DMAC_CHCTRLB_CMD_SHIFT) /* No action */ @@ -296,8 +308,9 @@ trigger */ #define DMAC_TRIGSRC_AES_WR (44) /* AES Write Trigger */ #define DMAC_TRIGSRC_AES_RD (45) /* AES Read Trigger */ -/* Common register bit definitions: Channel Interrupt Enable Clear Register, Channel Interrupt - * Enable Set Register, and Channel Interrupt Flag Status and Clear Register +/* Common register bit definitions: Channel Interrupt Enable Clear Register, + * Channel Interrupt Enable Set Register, and Channel Interrupt Flag + * Status and Clear Register */ #define DMAC_INT_TERR (1 << 0) /* Bit 0: Transfer error interrupt */ @@ -313,26 +326,29 @@ trigger */ /* Block Transfer Control Register */ -#define LPSRAM_BTCTRL_VALID (1 << 0) /* Bit 0: Descriptor valid */ +#define LPSRAM_BTCTRL_VALID (1 << 0) /* Bit 0: Descriptor valid */ #define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */ #define LPSRAM_BTCTRL_EVOSEL_MASK (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) # define LPSRAM_BTCTRL_EVOSEL_DISABLE (0 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event generation disabled */ # define LPSRAM_BTCTRL_EVOSEL_BLOCK (1 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when block transfer complete */ # define LPSRAM_BTCTRL_EVOSEL_BEAT (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when beat transfer complete */ + #define LPSRAM_BTCTRL_BLOCKACT_SHIFT (3) /* Bits 3-4: Block action */ #define LPSRAM_BTCTRL_BLOCKACT_MASK (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) # define LPSRAM_BTCTRL_BLOCKACT_NOACT (0 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer */ # define LPSRAM_BTCTRL_BLOCKACT_INT (1 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer + block int */ # define LPSRAM_BTCTRL_BLOCKACT_SUSPEND (2 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel suspend operation is completed */ # define LPSRAM_BTCTRL_BLOCKACT_BOTH (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Both channel suspend operation + block int */ + #define LPSRAM_BTCTRL_BEATSIZE_SHIFT (8) /* Bits 8-9: Beat size */ #define LPSRAM_BTCTRL_BEATSIZE_MASK (3 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) # define LPSRAM_BTCTRL_BEATSIZE_BYTE (0 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 8-bit bus transfer */ # define LPSRAM_BTCTRL_BEATSIZE_HWORD (1 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 16-bit bus transfer */ # define LPSRAM_BTCTRL_BEATSIZE_WORD (2 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 32-bit bus transfer */ -#define LPSRAM_BTCTRL_SRCINC (1 << 10) /* Bit 10: Source address increment enable */ -#define LPSRAM_BTCTRL_DSTINC (1 << 11) /* Bit 11: Destination address increment enable */ -#define LPSRAM_BTCTRL_STEPSEL (1 << 12) /* Bit 12: Step selection */ + +#define LPSRAM_BTCTRL_SRCINC (1 << 10) /* Bit 10: Source address increment enable */ +#define LPSRAM_BTCTRL_DSTINC (1 << 11) /* Bit 11: Destination address increment enable */ +#define LPSRAM_BTCTRL_STEPSEL (1 << 12) /* Bit 12: Step selection */ #define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */ #define LPSRAM_BTCTRL_STEPSIZE_MASK (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) # define LPSRAM_BTCTRL_STEPSIZE_X1 (0 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */ @@ -345,13 +361,17 @@ trigger */ # define LPSRAM_BTCTRL_STEPSIZE_X128 (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */ /* Block Transfer Count Register (16-bit count) */ + /* Block Transfer Source Address Register (32-bit address) */ + /* Block Transfer Destination Address Register (32-bit address) */ + /* Next Address Descriptor Register (32-bit address) */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ + /* DMA descriptor */ struct dma_desc_s @@ -363,13 +383,13 @@ struct dma_desc_s uint32_t descaddr; /* Next Address Descriptor Register */ }; -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_eic.h b/arch/arm/src/samd2l2/hardware/saml_eic.h index 9810786aed6..3c40e45453b 100644 --- a/arch/arm/src/samd2l2/hardware/saml_eic.h +++ b/arch/arm/src/samd2l2/hardware/saml_eic.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_eic.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* EIC register offsets *********************************************************************/ + ****************************************************************************/ + +/* EIC register offsets *****************************************************/ #define SAM_EIC_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_EIC_NVMICTRL_OFFSET 0x0001 /* Non-maskable interrupt control register */ @@ -55,7 +56,7 @@ #define SAM_EIC_CONFIG2_OFFSET 0x0024 /* Configuration 2 register */ #define SAM_EIC_CONFIG3_OFFSET 0x0028 /* Configuration 3 register */ -/* EIC register addresses *******************************************************************/ +/* EIC register addresses ***************************************************/ #define SAM_EIC_CTRLA (SAM_EIC_BASE+SAM_EIC_CTRLA_OFFSET) #define SAM_EIC_NVMICTRL (SAM_EIC_BASE+SAM_EIC_NVMICTRL_OFFSET) @@ -71,13 +72,14 @@ #define SAM_EIC_CONFIG2 (SAM_EIC_BASE+SAM_EIC_CONFIG2_OFFSET) #define SAM_EIC_CONFIG3 (SAM_EIC_BASE+SAM_EIC_CONFIG3_OFFSET) -/* EIC register bit definitions *************************************************************/ +/* EIC register bit definitions *********************************************/ /* Control A register */ #define EIC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */ #define EIC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */ #define EIC_CTRLA_CKSEL (1 << 2) /* Bit 2: Clock selection */ + # define EIC_CTRLA_CKSEL_GCLK_EIC (0) /* 0=EIC clocked by GCLK_EIC */ # define EIC_CTRLA_CKSEL_CLK_ULP32K EIC_CTRLA_CKSEL /* 1=EIC clocked by CLK_ULP32K */ @@ -91,6 +93,7 @@ # define EIC_NVMICTRL_NMISENSE_BOTH (3 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Both edge detection */ # define EIC_NVMICTRL_NMISENSE_HIGH (4 << EIC_NVMICTRL_NMISENSE_SHIFT) /* High level detection */ # define EIC_NVMICTRL_NMISENSE_LOW (5 << EIC_NVMICTRL_NMISENSE_SHIFT) /* Low level detection */ + #define EIC_NVMICTRL_NMIFLTEN (1 << 3) /* Bit 3: Non-maskable interrupt filter enable */ #define EIC_NVMICTRL_ASYNC (1 << 4) /* Bit 4: Asynchronous edge detection mode */ @@ -103,8 +106,9 @@ #define EIC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset syncrhonization busy */ #define EIC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable syncrhonization busy */ -/* Event control, Interrupt enable clear, interrupt enable set register, interrupt flag - * status and clear, and External interrupt asynchronous mode registers. +/* Event control, Interrupt enable clear, interrupt enable set register, + * interrupt flag status and clear, and External interrupt asynchronous + * mode registers. */ #define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */ @@ -177,17 +181,17 @@ # define EIC_CONFIG3_SENSE_HIGH (4 << EIC_CONFIG3_SENSE_SHIFT(n)) /* High level detection */ # define EIC_CONFIG3_SENSE_LOW (5 << EIC_CONFIG3_SENSE_SHIFT(n)) /* Low level detection */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_evsys.h b/arch/arm/src/samd2l2/hardware/saml_evsys.h index 17c40d5a4c0..c53158d929b 100644 --- a/arch/arm/src/samd2l2/hardware/saml_evsys.h +++ b/arch/arm/src/samd2l2/hardware/saml_evsys.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_evsys.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* EVSYS register offsets *******************************************************************/ + ****************************************************************************/ + +/* EVSYS register offsets ***************************************************/ #define SAM_EVSYS_CTRLA_OFFSET 0x0000 /* Control register */ #define SAM_EVSYS_CHSTATUS_OFFSET 0x000c /* Channel status register */ @@ -47,10 +48,11 @@ #define SAM_EVSYS_INTENSET_OFFSET 0x0014 /* Interrupt enable set register */ #define SAM_EVSYS_INTFLAG_OFFSET 0x0018 /* Interrupt flag status and clear register */ #define SAM_EVSYS_SWEVT_OFFSET 0x001c /* Event user */ + #define SAM_EVSYS_CHANNEL_OFFSET(n) (0x0020 + ((n) << 2)) /* Channel registers */ #define SAM_EVSYS_USER_OFFSET(n) (0x0080 + ((m) << 2)) /* User registers */ -/* EVSYS register addresses *****************************************************************/ +/* EVSYS register addresses *************************************************/ #define SAM_EVSYS_CTRLA (SAM_EVSYS_BASE+SAM_EVSYS_CTRLA_OFFSET) #define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET @@ -61,7 +63,7 @@ #define SAM_EVSYS_CHANNEL_BASE(n) (SAM_EVSYS_BASE+SAM_EVSYS_CHANNEL_OFFSET(n)) #define SAM_EVSYS_USER_BASE(n) (SAM_EVSYS_BASE+SAM_EVSYS_USER_OFFSET(n)) -/* EVSYS register bit definitions ***********************************************************/ +/* EVSYS register bit definitions *******************************************/ /* Control register */ @@ -76,7 +78,9 @@ #define EVSYS_CHSTATUS_CHBUSY_MASK (0xfff << EVSYS_CHSTATUS_CHBUSY_SHIFT) # define EVSYS_CHSTATUS_CHBUSY(n) ((uint32_t)(n) << EVSYS_CHSTATUS_CHBUSY_SHIFT) -/* Interrupt enable clear, interrupt enable set, and interrupt flag status and clear registers */ +/* Interrupt enable clear, interrupt enable set, + * and interrupt flag status and clear registers + */ #define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n= 0-11 */ #define EVSYS_INT_OVR_MASK (0xfff << EVSYS_INT_OVR_SHIFT) @@ -178,17 +182,20 @@ # define EVSYS_CHANNEL_EVGEN_CCL_LUTOUT2 (0x50 << EVSYS_CHANNEL_EVGEN_SHIFT) /* CCL output 2 */ # define EVSYS_CHANNEL_EVGEN_CCL_LUTOUT3 (0x51 << EVSYS_CHANNEL_EVGEN_SHIFT) /* CCL output 3 */ # define EVSYS_CHANNEL_EVGEN_PAC_ACCERR (0x52 << EVSYS_CHANNEL_EVGEN_SHIFT) /* PAC access error */ + #define EVSYS_CHANNEL_PATH_SHIFT (8) /* Bits 8-9: Path selection */ #define EVSYS_CHANNEL_PATH_MASK (3 << EVSYS_CHANNEL_PATH_SHIFT) # define EVSYS_CHANNEL_PATH_SYNCH (0 << EVSYS_CHANNEL_PATH_SHIFT) /* Synchronized path */ # define EVSYS_CHANNEL_PATH_RESYNCH (1 << EVSYS_CHANNEL_PATH_SHIFT) /* Resynchronized path */ # define EVSYS_CHANNEL_PATH_ASYNCH (2 << EVSYS_CHANNEL_PATH_SHIFT) /* Asynchronous path */ + #define EVSYS_CHANNEL_EDGESEL_SHIFT (10) /* Bits 10-11: Edge dection selection */ #define EVSYS_CHANNEL_EDGESEL_MASK (3 << EVSYS_CHANNEL_EDGESEL_SHIFT) # define EVSYS_CHANNEL_EDGESEL_NONE (0 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* No event output */ # define EVSYS_CHANNEL_EDGESEL_RISING (1 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* Detect on rising edge */ # define EVSYS_CHANNEL_EDGESEL_FALLING (2 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* Detect on falling edge */ # define EVSYS_CHANNEL_EDGESEL_BOTH (3 << EVSYS_CHANNEL_EDGESEL_SHIFT) /* Detect on both edges */ + #define EVSYS_CHANNEL_RUNSTDBY (1 << 14) /* Bit 14: Run in standby */ #define EVSYS_CHANNEL_ONDEMAND (1 << 15) /* Bit 15: Generic clock on-demand */ @@ -197,9 +204,10 @@ #define EVSYS_USER_CHANNEL_SHIFT (0) /* Bits 0-5: Channel number */ #define EVSYS_USER_CHANNEL_MASK (63 << EVSYS_USER_CHANNEL_SHIFT) # define EVSYS_USER_CHANNEL_NONE (0 << EVSYS_USER_CHANNEL_SHIFT) /* No channel output selected */ + # define EVSYS_USER_CHANNEL(n) ((uint32_t)((n)+1) << EVSYS_USER_CHANNEL_SHIFT) /* Channel n */ -/* User multiplexer numbers ****************************************************************/ +/* User multiplexer numbers ************************************************/ #define EVSYS_USER_PORT_EV0 0 /* Event 0 */ #define EVSYS_USER_PORT_EV1 1 /* Event 1 */ @@ -230,17 +238,17 @@ #define EVSYS_USER_TC0 26 /* TC0 */ #define EVSYS_USER_TC1 27 /* TC1 */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_fuses.h b/arch/arm/src/samd2l2/hardware/saml_fuses.h index 1e3cd1b67c7..1030adb056a 100644 --- a/arch/arm/src/samd2l2/hardware/saml_fuses.h +++ b/arch/arm/src/samd2l2/hardware/saml_fuses.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_fuses.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* NVM Fuse addresses **********************************************************************/ + ****************************************************************************/ + +/* NVM Fuse addresses *******************************************************/ /* NVM user row bits */ @@ -53,7 +54,8 @@ #define SAM_NVMCALIB_AREA2 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 64-95 */ #define SAM_NVMCALIB_AREA3 (SAM_NVMCALIB_AREA + 0x0000) /* Bits 96-127 */ -/* Fuse bit-field definitions **************************************************************/ +/* Fuse bit-field definitions ***********************************************/ + /* NVM user row bits 0-31 */ #define SAM_FUSES_BOOTPROT_ADDR SAM_NVMUSER_ROW0 @@ -173,20 +175,22 @@ # define SAM_FUSES_DFLL48MCC(n) ((uint32_t)(n) << SAM_FUSES_DFLL48MCC_SHIFT) /* NVM Software Calibration Area bits 32-63 - Reserved */ + /* NVM Software Calibration Area bits 64-95 - Reserved */ + /* NVM Software Calibration Area bits 96-127 - Reserved */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_gclk.h b/arch/arm/src/samd2l2/hardware/saml_gclk.h index 40bac30b9c6..51eaed7033d 100644 --- a/arch/arm/src/samd2l2/hardware/saml_gclk.h +++ b/arch/arm/src/samd2l2/hardware/saml_gclk.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_gclk.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* GCLK register offsets ********************************************************************/ + ****************************************************************************/ + +/* GCLK register offsets ****************************************************/ #define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */ #define SAM_GCLK_SYNCHBUSY_OFFSET 0x0004 /* Status register */ @@ -47,7 +48,7 @@ #define SAM_GCLK_GENCTRL_OFFSET(n) (0x0020 + ((n) << 2)) /* General clock generator n */ #define SAM_GCLK_PCHCTRL_OFFSET(m) (0x0080 + ((m) << 2)) /* Peripheral channel control m */ -/* GCLK register addresses ******************************************************************/ +/* GCLK register addresses **************************************************/ #define SAM_GCLK_CTRLA (SAM_GCLK_BASE+SAM_GCLK_CTRLA_OFFSET) #define SAM_GCLK_SYNCHBUSY (SAM_GCLK_BASE+SAM_GCLK_SYNCHBUSY_OFFSET) @@ -55,7 +56,7 @@ #define SAM_GCLK_GENCTRL(n) (SAM_GCLK_BASE+SAM_GCLK_GENCTRL_OFFSET(n)) #define SAM_GCLK_PCHCTRL(m) (SAM_GCLK_BASE+SAM_GCLK_PCHCTRL_OFFSET(m)) -/* GCLK register bit definitions ************************************************************/ +/* GCLK register bit definitions ********************************************/ /* Control register */ @@ -64,7 +65,9 @@ /* Status register */ #define GCLK_SYNCHBUSY_SWRST (1 << 0) /* Bit 0: SWRST synchronization busy */ + #define GCLK_SYNCHBUSY_GENCTRL(n) (1 << ((n) + 2)) /* Bit n+2: Generator control n busy */ + # define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */ # define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */ # define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */ @@ -88,6 +91,7 @@ # define GCLK_GENCTRL_SRC_OSC16M (6 << GCLK_GENCTRL_SRC_SHIFT) /* OSC16M oscillator output */ # define GCLK_GENCTRL_SRC_DFLL48M (7 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL48M output */ # define GCLK_GENCTRL_SRC_DPLL96M (8 << GCLK_GENCTRL_SRC_SHIFT) /* DPLL96M output */ + #define GCLK_GENCTRL_GENEN (1 << 8) /* Bit 8: Generator enable */ #define GCLK_GENCTRL_IDC (1 << 9) /* Bit 9: Improve duty cycle */ #define GCLK_GENCTRL_OOV (1 << 10) /* Bit 10: Clock output selection */ @@ -118,7 +122,7 @@ #define GCLK_PCHCTRL_CHEN (1 << 6) /* Bit 6: Channel enable */ #define GCLK_PCHCTRL_WRTLOCK (1 << 7) /* Bit 7: Write lock */ -/* PCHCTRL channel mapping ******************************************************************/ +/* PCHCTRL channel mapping **************************************************/ #define GCLK_CHAN_DFLL48M_REF 0 /* DFLL48M Reference */ #define GCLK_CHAN_DPLL 1 /* FDPLL96M input clock source for reference */ @@ -164,17 +168,17 @@ #define GCLK_CHAN_PTC 33 /* PTC */ #define GCLK_CHAN_CCL 34 /* CCL */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_i2c_master.h b/arch/arm/src/samd2l2/hardware/saml_i2c_master.h index 62b07802f13..15fda6fc03c 100644 --- a/arch/arm/src/samd2l2/hardware/saml_i2c_master.h +++ b/arch/arm/src/samd2l2/hardware/saml_i2c_master.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_i2c_master.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -37,10 +37,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* I2C register offsets *********************************************************************/ + ****************************************************************************/ + +/* I2C register offsets *****************************************************/ #define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -54,7 +55,7 @@ #define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */ #define SAM_I2C_DBGCTRL_OFFSET 0x0030 /* Debug control register */ -/* I2C register addresses *******************************************************************/ +/* I2C register addresses ***************************************************/ #define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET) #define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET) @@ -128,7 +129,7 @@ #define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET) #define SAM_I2C5_DBGCTRL (SAM_SERCOM5_BASE+SAM_I2C_DBGCTRL_OFFSET) -/* I2C register bit definitions *************************************************************/ +/* I2C register bit definitions *********************************************/ /* Control A register */ @@ -137,16 +138,20 @@ #define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */ #define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT) # define I2C_CTRLA_MODE_MASTER (5 << I2C_CTRLA_MODE_SHIFT) /* I2C master mode */ + #define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Transmit data pinout */ + # define I2C_CTRLA_1WIRE (0) /* 4-wire operation disable */ # define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enable */ + #define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */ #define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT) # define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */ # define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */ # define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */ # define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */ + #define I2C_CTRLA_MEXTTOEN (1 << 22) /* Bit 22: Master SCL low extend time-out */ #define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */ #define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */ @@ -154,6 +159,7 @@ # define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) and fast (<=400KHz) */ # define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode plus (<=1MHz) */ # define I2C_CTRLA_SPEED_HIGH (2 << I2C_CTRLA_SPEED_SHIFT) /* High speed mode (<=3.4Mhz */ + #define I2C_CTRLA_SCLAM (1 << 27) /* Bit 27: CSL clock stretch mode */ #define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */ #define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT) @@ -161,6 +167,7 @@ # define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */ # define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */ # define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */ + #define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */ /* Control B register */ @@ -173,7 +180,9 @@ # define I2C_CTRLB_CMD_ACKREP (1 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by repeated START */ # define I2C_CTRLB_CMD_ACKREAD (2 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by read operation */ # define I2C_CTRLB_CMD_ACKSTOP (3 << I2C_CTRLB_CMD_SHIFT) /* ACK followed by STOP */ + #define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */ + # define I2C_CTRLB_ACK (0) /* Send ACK */ # define I2C_CTRLB_NACK I2C_CTRLB_ACKACT /* Send NACK */ @@ -192,8 +201,8 @@ #define I2C_HSBAUDLOW_MASK (0xff << I2C_HSBAUDLOW_SHIFT) # define I2C_HSBAUDLOW(n) (uint16)(n) << I2C_HSBAUDLOW_SHIFT) -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define I2C_INT_MB (1 << 0) /* Bit 0: Master on bus interrupt */ @@ -213,6 +222,7 @@ # define I2C_STATUS_BUSSTATE_IDLE (1 << I2C_STATUS_BUSSTATE_SHIFT) /* Waiting for transaction */ # define I2C_STATUS_BUSSTATE_OWNER (2 << I2C_STATUS_BUSSTATE_SHIFT) /* Master of bus owner */ # define I2C_STATUS_BUSSTATE_BUSY (3 << I2C_STATUS_BUSSTATE_SHIFT) /* Other master owns */ + #define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */ #define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */ #define I2C_STATUS_MEXTTOUT (1 << 8) /* Bit 8: Master SCL low extend time-out */ @@ -245,17 +255,17 @@ #define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h b/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h index 622965df6e3..875aedb1fac 100644 --- a/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h +++ b/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_i2c_slave.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -37,10 +37,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* I2C register offsets *********************************************************************/ + ****************************************************************************/ + +/* I2C register offsets *****************************************************/ #define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -51,7 +52,7 @@ #define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */ #define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */ -/* I2C register addresses *******************************************************************/ +/* I2C register addresses ***************************************************/ #define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET) #define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET) @@ -107,7 +108,7 @@ #define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET) #define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET) -/* I2C register bit definitions *************************************************************/ +/* I2C register bit definitions *********************************************/ /* Control A register */ @@ -116,22 +117,27 @@ #define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */ #define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT) # define I2C_CTRLA_MODE_SLAVE (4 << I2C_CTRLA_MODE_SHIFT) /* I2C slave mode */ + #define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Pin usage */ + # define I2C_CTRLA_1WIRE (0) /* 4-wire operation disabled */ # define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enabled */ + #define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */ #define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT) # define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */ # define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */ # define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */ # define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */ + #define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */ #define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Trnasfer speed */ #define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT) # define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) fast <=400KHz */ # define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode please (<=1MHz) */ # define I2C_CTRLA_SPEED_HIGH (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4Mhz */ + #define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */ #define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */ @@ -145,17 +151,20 @@ # define I2C_CRLB_AMODE_MASK (0 << I2C_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */ # define I2C_CRLB_AMODE_2ADDRS (1 << I2C_CRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */ # define I2C_CRLB_AMODE_RANGE (2 << I2C_CRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */ + #define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */ #define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT) # define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */ # define I2C_CTRLB_CMD_WAITSTART (2 << I2C_CTRLB_CMD_SHIFT) /* ACK (write) wait for START */ # define I2C_CTRLB_CMD_ACKREAD (3 << I2C_CTRLB_CMD_SHIFT) /* ACK with read (context dependent) */ + #define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */ + # define I2C_CTRLB_ACK (0) /* Send ACK */ # define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define I2C_INT_PREC (1 << 0) /* Bit 0: Stop received interrupt */ @@ -185,17 +194,17 @@ #define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_mclk.h b/arch/arm/src/samd2l2/hardware/saml_mclk.h index d5435e14715..0ca66f27068 100644 --- a/arch/arm/src/samd2l2/hardware/saml_mclk.h +++ b/arch/arm/src/samd2l2/hardware/saml_mclk.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_mclk.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* MCLK register offsets ************************************************************/ + ****************************************************************************/ + +/* MCLK register offsets ****************************************************/ #define SAM_MCLK_CTRLA_OFFSET 0x0000 /* CTRLA register */ #define SAM_MCLK_INTENCLR_OFFSET 0x0001 /* Interrupt enable clear */ @@ -56,7 +57,7 @@ #define SAM_MCLK_APBDMASK_OFFSET 0x0020 /* APBD mask */ #define SAM_MCLK_APBEMASK_OFFSET 0x0024 /* APBE mask */ -/* MCLK register addresses **********************************************************/ +/* MCLK register addresses **************************************************/ #define SAM_MCLK_CTRLA (SAM_MCLK_BASE+SAM_MCLK_CTRLA_OFFSET) #define SAM_MCLK_INTENCLR (SAM_MCLK_BASE+SAM_MCLK_INTENCLR_OFFSET) @@ -73,15 +74,15 @@ #define SAM_MCLK_APBDMASK (SAM_MCLK_BASE+SAM_MCLK_APBDMASK_OFFSET) #define SAM_MCLK_APBEMASK (SAM_MCLK_BASE+SAM_MCLK_APBEMASK_OFFSET) -/* MCLK register bit definitions ****************************************************/ +/* MCLK register bit definitions ********************************************/ /* CTRLA register */ #define MCLK_CTRLA_CFDEN (1 << 2) /* Bit 2: Clock Failure Detector Enable */ #define MCLK_CTRLA_EMCLK (1 << 4) /* Bit 4: Emergency Clock Select */ -/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and - * clear. +/* Interrupt enable clear, Interrupt enable set, + * and Interrupt flag status and clear. */ #define MCLK_INT_CKRDY (1 << 0) /* Bit 0: Clock ready */ @@ -155,6 +156,7 @@ /* APBC mask */ #define MCLK_APBCMASK_SERCOM(n) (1 << (n)) /* Bit n: SERCOMn APBC clock enable, n=0-4 */ + # define MCLK_APBCMASK_SERCOM0 (1 << 0) /* Bit 0: SERCOM0 APBC clock enable */ # define MCLK_APBCMASK_SERCOM1 (1 << 1) /* Bit 1: SERCOM1 APBC clock enable */ # define MCLK_APBCMASK_SERCOM2 (1 << 2) /* Bit 2: SERCOM2 APBC clock enable */ @@ -186,17 +188,17 @@ #define MCLK_APBEMASK_PAC (1 << 0) /* Bit 0: PAC APBE clock enable */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_nvmctrl.h b/arch/arm/src/samd2l2/hardware/saml_nvmctrl.h index b15d78bd7b4..407215ca014 100644 --- a/arch/arm/src/samd2l2/hardware/saml_nvmctrl.h +++ b/arch/arm/src/samd2l2/hardware/saml_nvmctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_nvmctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* NVMCTRL register offsets *****************************************************************/ + ****************************************************************************/ + +/* NVMCTRL register offsets *************************************************/ #define SAM_NVMCTRL_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_NVMCTRL_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -51,7 +52,7 @@ #define SAM_NVMCTRL_ADDR_OFFSET 0x001c /* Address register */ #define SAM_NVMCTRL_LOCK_OFFSET 0x0020 /* Lock section register */ -/* NVMCTRL register addresses ***************************************************************/ +/* NVMCTRL register addresses ***********************************************/ #define SAM_NVMCTRL_CTRLA (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLA_OFFSET) #define SAM_NVMCTRL_CTRLB (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLB_OFFSET) @@ -62,7 +63,7 @@ #define SAM_NVMCTRL_ADDR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_ADDR_OFFSET) #define SAM_NVMCTRL_LOCK (SAM_NVMCTRL_BASE+SAM_NVMCTRL_LOCK_OFFSET) -/* NVMCTRL register bit definitions *********************************************************/ +/* NVMCTRL register bit definitions *****************************************/ /* Control A register */ @@ -81,6 +82,7 @@ # define NVMCTRL_CTRLA_CMD_PBC (0x44 << NVMCTRL_CTRLA_CMD_SHIFT) /* Page Buffer Clear */ # define NVMCTRL_CTRLA_CMD_SSB (0x45 << NVMCTRL_CTRLA_CMD_SHIFT) /* Set Security Bit */ # define NVMCTRL_CTRLA_CMD_INVALL (0x46 << NVMCTRL_CTRLA_CMD_SHIFT) /* Invalidate all cache lines */ + #define NVMCTRL_CTRLA_CMDEX_SHIFT (8) /* Bits 8-15: Command Execution */ #define NVMCTRL_CTRLA_CMDEX_MASK (0xff << NVMCTRL_CTRLA_CMDEX_SHIFT) # define NVMCTRL_CTRLA_CMDEX (0xa5 << NVMCTRL_CTRLA_CMDEX_SHIFT) @@ -96,11 +98,13 @@ # define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (0 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power on first access */ # define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (1 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Exit low power when exit sleep */ # define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (3 << NVMCTRL_CTRLB_SLEEPPRM_SHIFT) /* Auto power reduction disabled */ + #define NVMCTRL_CTRLB_READMODE_SHIFT (16) /* Bits 16-17: NVMCTRL Read Mode */ #define NVMCTRL_CTRLB_READMODE_MASK (3 << NVMCTRL_CTRLB_READMODE_SHIFT) # define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (0 << NVMCTRL_CTRLB_READMODE_SHIFT) /* No extra wait states on miss */ # define NVMCTRL_CTRLB_READMODE_LOW_POWER (1 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Insert wait/reduce power */ # define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (2 << NVMCTRL_CTRLB_READMODE_SHIFT) /* Same wait on all access */ + #define NVMCTRL_CTRLB_CACHEDIS (1 << 18) /* Bit 18: Cache Disable */ /* NVM parameter register */ @@ -118,12 +122,15 @@ # define NVMCTRL_PARAM_PSZ_256B (5 << NVMCTRL_PARAM_PSZ_SHIFT) /* 256 bytes */ # define NVMCTRL_PARAM_PSZ_512B (6 << NVMCTRL_PARAM_PSZ_SHIFT) /* 512 bytes */ # define NVMCTRL_PARAM_PSZ_1KB (7 << NVMCTRL_PARAM_PSZ_SHIFT) /* 1024 bytes */ + #define NVMCTRL_PARAM_RWWEEP_SHIFT (20) /* Bits 20-31: Read while write EEPROM emulation area pages */ #define NVMCTRL_PARAM_RWWEEP_MASK (0xfff << NVMCTRL_PARAM_RWWEEP_SHIFT) # define NVMCTRL_PARAM_RWWEEP(n) ((uint32_t)(n) << NVMCTRL_PARAM_RWWEEP_SHIFT) /* Interrupt clear register */ + /* Interrupt set register */ + /* Interface flags status and clear register */ #define NVMCTRL_INT_READY (1 << 0) /* Bit 0: NVM Ready Interrupt */ @@ -146,17 +153,17 @@ #define NVMCTRL_LOCK_REGION(n) (1 << (n)) /* Region n is locked */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_opamp.h b/arch/arm/src/samd2l2/hardware/saml_opamp.h index 04ad1edba71..5f5e6759789 100644 --- a/arch/arm/src/samd2l2/hardware/saml_opamp.h +++ b/arch/arm/src/samd2l2/hardware/saml_opamp.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_opamp.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OPAMP_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OPAMP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* OPAMP register offsets ********************************************************************/ + ****************************************************************************/ + +/* OPAMP register offsets ***************************************************/ #define SAM_OPAMP_CTRLA_OFFSET 0x0000 /* Control A Register */ #define SAM_OPAMP_STATUS_OFFSET 0x0002 /* Status Register */ @@ -47,7 +48,7 @@ #define SAM_OPAMP_CTRL1_OFFSET 0x0008 /* OPAMP Control 1 Register */ #define SAM_OPAMP_CTRL2_OFFSET 0x000c /* OPAMP Control 2 Register */ -/* OPAMP register addresses ******************************************************************/ +/* OPAMP register addresses *************************************************/ #define SAM_OPAMP_CTRLA (SAM_OPAMP_BASE+SAM_OPAMP_CTRLA_OFFSET) #define SAM_OPAMP_STATUS (SAM_OPAMP_BASE+SAM_OPAMP_STATUS_OFFSET) @@ -55,7 +56,7 @@ #define SAM_OPAMP_CTRL1 (SAM_OPAMP_BASE+SAM_OPAMP_CTRL1_OFFSET) #define SAM_OPAMP_CTRL2 (SAM_OPAMP_BASE+SAM_OPAMP_CTRL2_OFFSET) -/* OPAMP register bit definitions ************************************************************/ +/* OPAMP register bit definitions *******************************************/ /* Control A Register */ @@ -73,17 +74,19 @@ #define OPAMP_CTRL_ENABLE (1 << 1) /* Bit 1: Operation amplifier enable */ #define OPAMP_CTRL_ANAOUT (1 << 2) /* Bit 2: Analog output */ -#define OPAMP_CTRL_BIAS_SHIFT (3) /* Bits 3-5: Bias selection */ +#define OPAMP_CTRL_BIAS_SHIFT (3) /* Bits 3-5: Bias selection */ #define OPAMP_CTRL_BIAS_MASK (7 << OPAMP_CTRL_BIAS_SHIFT) # define OPAMP_CTRL_BIAS_MODE0 (0 << OPAMP_CTRL_BIAS_SHIFT) /* Minimum current, slowest mode */ # define OPAMP_CTRL_BIAS_MODE1 (1 << OPAMP_CTRL_BIAS_SHIFT) /* Low current, slow */ # define OPAMP_CTRL_BIAS_MODE2 (2 << OPAMP_CTRL_BIAS_SHIFT) /* High current, fast */ # define OPAMP_CTRL_BIAS_MODE3 (3 << OPAMP_CTRL_BIAS_SHIFT) /* Maximum current, fastest mode */ -#define OPAMP_CTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ -#define OPAMP_CTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */ -#define OPAMP_CTRL_RES2OUT (1 << 8) /* Bit 8: Resistor ladder to output */ -#define OPAMP_CTRL_RES2VCC (1 << 9) /* Bit 9: Resistor ladder to VCC */ + +#define OPAMP_CTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ +#define OPAMP_CTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */ +#define OPAMP_CTRL_RES2OUT (1 << 8) /* Bit 8: Resistor ladder to output */ +#define OPAMP_CTRL_RES2VCC (1 << 9) /* Bit 9: Resistor ladder to VCC */ #define OPAMP_CTRL_RES1EN (1 << 10) /* Bit 10: Resistor 1 enable */ + #define OPAMP_CTRL_RES1MUX_SHIFT (11) /* Bits 11-12: Resistor 1 mux */ #define OPAMP_CTRL_RES1MUX_MASK (3 << OPAMP_CTRL_RES1MUX_MASK) # define OPAMP_CTRL_RES1MUX_OAxPOS (0 << OPAMP_CTRL_RES1MUX_MASK) /* Positive input of OPAMPn, n=0,1,2 */ @@ -92,6 +95,7 @@ # define OPAMP_CTRL_RES1MUX_OA0OUT_1 (2 << OPAMP_CTRL_RES1MUX_MASK) /* OPAMP0 output, OPAMP1 */ # define OPAMP_CTRL_RES1MUX_OA1OUT_2 (2 << OPAMP_CTRL_RES1MUX_MASK) /* OPAMP1 output, OPAMP2 */ # define OPAMP_CTRL_RES1MUX_GND (3 << OPAMP_CTRL_RES1MUX_MASK) /* Ground, OPAMPn, n=0,1,2 */ + #define OPAMP_CTRL_POTMUX_SHIFT (13) /* Bits 13-15: Potentiometer selection */ #define OPAMP_CTRL_POTMUX_MASK (7 << OPAMP_CTRL_POTMUX_SHIFT) # define OPAMP_CTRL_POTMUX_14R_2R (0 << OPAMP_CTRL_POTMUX_SHIFT) /* Gain 1/7 */ @@ -102,6 +106,7 @@ # define OPAMP_CTRL_POTMUX_3R_13R (5 << OPAMP_CTRL_POTMUX_SHIFT) /* Gain 4+1/3 */ # define OPAMP_CTRL_POTMUX_2R_14R (6 << OPAMP_CTRL_POTMUX_SHIFT) /* Gain 7 */ # define OPAMP_CTRL_POTMUX_R_15R (7 << OPAMP_CTRL_POTMUX_SHIFT) /* Gain 15 */ + #define OPAMP_CTRL_MUXPOS_SHIFT (16) /* Bits 16-18: Positive input mux selection */ #define OPAMP_CTRL_MUXPOS_MASK (7 << OPAMP_CTRL_MUXPOS_SHIFT) # define OPAMP_CTRL_MUXPOS_OAxPOS (0 << OPAMP_CTRL_MUXPOS_SHIFT) /* Positive I/O pin, OPAMPn, n=0,1,2 */ @@ -113,6 +118,7 @@ # define OPAMP_CTRL_MUXPOS_OA0POS_2 (4 << OPAMP_CTRL_MUXPOS_SHIFT) /* Positive I/O pin OPA0, OPAMP2 */ # define OPAMP_CTRL_MUXPOS_OA1POS_2 (5 << OPAMP_CTRL_MUXPOS_SHIFT) /* Positive I/O pin OPA1, OPAMP2 */ # define OPAMP_CTRL_MUXPOS_OA0TAP_2 (6 << OPAMP_CTRL_MUXPOS_SHIFT) /* Resistor ladder 0 taps, OPAMP2 */ + #define OPAMP_CTRL_MUXNEG_SHIFT (20) /* Bits 20-22: Negative input mux selection */ #define OPAMP_CTRL_MUXNEG_MASK (7 << OPAMP_CTRL_MUXNEG_SHIFT) # define OPAMP_CTRL_MUXNEG_OAxNEG (0 << OPAMP_CTRL_MUXNEG_SHIFT) /* Negative I/O pin OPAMP n, n=0,1,2 */ @@ -123,17 +129,17 @@ # define OPAMP_CTRL_MUXNEG_OA1NEG_2 (4 << OPAMP_CTRL_MUXNEG_SHIFT) /* Negative I/O OPA1, OPAMP2 */ # define OPAMP_CTRL_MUXNEG_DAC_2 (5 << OPAMP_CTRL_MUXNEG_SHIFT) /* DAC output, OPAMP2 */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OPAMP_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h b/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h index ebd8fd68e19..9bfbee3d380 100644 --- a/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h +++ b/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSC32KCTRL_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSC32KCTRL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* OSC32KCTRL register offsets **************************************************************/ + ****************************************************************************/ + +/* OSC32KCTRL register offsets **********************************************/ #define SAM_OSC32KCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */ #define SAM_OSC32KCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */ @@ -50,8 +51,7 @@ #define SAM_OSC32KCTRL_OSC32K_OFFSET 0x0018 /* 32kHz internal oscillator control */ #define SAM_OSC32KCTRL_OSCULP32K_OFFSET 0x001c /* 32kHz ultra low power internal oscillator control */ - -/* OSC32KCTRL register addresses ************************************************************/ +/* OSC32KCTRL register addresses ********************************************/ #define SAM_OSC32KCTRL_INTENCLR (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_INTENCLR_OFFSET) #define SAM_OSC32KCTRL_INTENSET (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_INTENSET_OFFSET) @@ -62,10 +62,10 @@ #define SAM_OSC32KCTRL_OSC32K (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_OSC32K_OFFSET) #define SAM_OSC32KCTRL_OSCULP32K (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_OSCULP32K_OFFSET) -/* OSC32KCTRL register bit definitions ******************************************************/ +/* OSC32KCTRL register bit definitions **************************************/ -/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and - * status registers. +/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and + * clear, and status registers. */ #define OSC32KCTRL_INT_XOSC32KRDY (1 << 0) /* Bit 0: XOSC32K ready interrupt */ @@ -92,7 +92,7 @@ #define OSC32KCTRL_XOSC32K_EN1K (1 << 4) /* Bit 4: 1kHz Output enable */ #define OSC32KCTRL_XOSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define OSC32KCTRL_XOSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */ -#define OSC32KCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */ +#define OSC32KCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */ #define OSC32KCTRL_XOSC32K_STARTUP_MASK (7 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) # define OSC32KCTRL_XOSC32K_STARTUP(n) ((n) << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) # define OSC32KCTRL_XOSC32K_STARTUP_63MS (0 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 62.592 msec */ @@ -102,6 +102,7 @@ # define OSC32KCTRL_XOSC32K_STARTUP_200MS (4 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 200.0092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_400MS (5 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 400.092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_800MS (6 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 800.0092 msec */ + #define OSC32KCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */ /* 32kHz internal oscillator control register */ @@ -122,6 +123,7 @@ # define OSC32KCTRL_OSC32K_STARTUP_1MS (5 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */ # define OSC32KCTRL_OSC32K_STARTUP_2MS (6 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */ # define OSC32KCTRL_OSC32K_STARTUP_4MS (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */ + #define OSC32KCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */ #define OSC32KCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */ #define OSC32KCTRL_OSC32K_CALIB_MASK (0x7f << OSC32KCTRL_OSC32K_CALIB_SHIFT) @@ -134,17 +136,17 @@ # define OSC32KCTRL_OSCULP32K_CALIB(n) ((n) << OSC32KCTRL_OSCULP32K_CALIB_SHIFT) #define OSC32KCTRL_OSCULP32K_WRTLOCK (1 << 7) /* Bit 7: Write Lock */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSC32KCTRL_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_oscctrl.h b/arch/arm/src/samd2l2/hardware/saml_oscctrl.h index 24976e75b16..f2b33db71ea 100644 --- a/arch/arm/src/samd2l2/hardware/saml_oscctrl.h +++ b/arch/arm/src/samd2l2/hardware/saml_oscctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_oscctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSCCTRL_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSCCTRL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* OSCCTRL register offsets *****************************************************************/ + ****************************************************************************/ + +/* OSCCTRL register offsets *************************************************/ #define SAM_OSCCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */ #define SAM_OSCCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */ @@ -58,7 +59,7 @@ #define SAM_OSCCTRL_DPLLSYNCBUSY_OFFSET 0x0038 /* DPLL synchronization busy */ #define SAM_OSCCTRL_DPLLSTATUS_OFFSET 0x003c /* DPLL status */ -/* OSCCTRL register addresses ***************************************************************/ +/* OSCCTRL register addresses ***********************************************/ #define SAM_OSCCTRL_INTENCLR (SAM_OSCCTRL_BASE+SAM_OSCCTRL_INTENCLR_OFFSET) #define SAM_OSCCTRL_INTENSET (SAM_OSCCTRL_BASE+SAM_OSCCTRL_INTENSET_OFFSET) @@ -77,10 +78,10 @@ #define SAM_OSCCTRL_DPLLSYNCBUSY (SAM_OSCCTRL_BASE+SAM_OSCCTRL_DPLLSYNCBUSY_OFFSET) #define SAM_OSCCTRL_DPLLSTATUS (SAM_OSCCTRL_BASE+SAM_OSCCTRL_DPLLSTATUS_OFFSET) -/* OSCCTRL register bit definitions *********************************************************/ +/* OSCCTRL register bit definitions *****************************************/ -/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and - * Status registers. +/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and + * clear, and Status registers. */ #define OSCCTRL_INT_XOSCRDY (1 << 0) /* Bit 0: XOSC ready */ @@ -111,6 +112,7 @@ # define OSCCTRL_XOSCCTRL_GAIN_8MHZ (2 << OSCCTRL_XOSCCTRL_GAIN_SHIFT) /* 8MHz */ # define OSCCTRL_XOSCCTRL_GAIN_16MHZ (3 << OSCCTRL_XOSCCTRL_GAIN_SHIFT) /* 16MHz */ # define OSCCTRL_XOSCCTRL_GAIN_30MHZ (4 << OSCCTRL_XOSCCTRL_GAIN_SHIFT) /* 30MHz */ + #define OSCCTRL_XOSCCTRL_AMPGC (1 << 11) /* Bit 11: Automatic amplitude gain control */ #define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */ #define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) @@ -141,6 +143,7 @@ # define OSCCTRL_OSC16MCTRL_FSEL_8MHZ (1 << OSCCTRL_OSC16MCTRL_FSEL_SHIFT) # define OSCCTRL_OSC16MCTRL_FSEL_12MHZ (2 << OSCCTRL_OSC16MCTRL_FSEL_SHIFT) # define OSCCTRL_OSC16MCTRL_FSEL_16MHZ (3 << OSCCTRL_OSC16MCTRL_FSEL_SHIFT) + #define OSCCTRL_OSC16MCTRL_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define OSCCTRL_OSC16MCTRL_ONDEMAND (1 << 7) /* Bit 7: On demand control */ #define OSCCTRL_OSC16MCTRL_GAIN_SHIFT (8) /* Bits 8-10: Oscillator gain */ @@ -151,6 +154,7 @@ # define OSCCTRL_OSC16MCTRL_GAIN_8MHZ (2 << OSCCTRL_OSC16MCTRL_GAIN_SHIFT) /* 8MHz */ # define OSCCTRL_OSC16MCTRL_GAIN_16MHZ (3 << OSCCTRL_OSC16MCTRL_GAIN_SHIFT) /* 16MHz */ # define OSCCTRL_OSC16MCTRL_GAIN_30MHZ (4 << OSCCTRL_OSC16MCTRL_GAIN_SHIFT) /* 30MHz */ + #define OSCCTRL_OSC16MCTRL_AMPGC (1 << 11) /* Bit 11: Automatic amplitude gain control */ #define OSCCTRL_OSC16MCTRL_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */ #define OSCCTRL_OSC16MCTRL_STARTUP_MASK (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) @@ -237,6 +241,7 @@ # define OSCCTRL_DPLLCTRLB_FILTER_LBFILT (1 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* Low bandwidth filter */ # define OSCCTRL_DPLLCTRLB_FILTER_HBFILT (2 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* High bandwidth filter */ # define OSCCTRL_DPLLCTRLB_FILTER_HDFILT (3 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* High damping filter */ + #define OSCCTRL_DPLLCTRLB_LPEN (1 << 2) /* Bit 2: Low-power enable */ #define OSCCTRL_DPLLCTRLB_WUF (1 << 3) /* Bit 3: Wake up fast */ #define OSCCTRL_DPLLCTRLB_REFLCK_SHIFT (4) /* Bits 4-5: Reference clock selection */ @@ -244,6 +249,7 @@ # define OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K (0 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC32K clock reference */ # define OSCCTRL_DPLLCTRLB_REFLCK_XOSC (1 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC clock reference */ # define OSCCTRL_DPLLCTRLB_REFLCK_GLCK (1 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* GCLK clock reference */ + #define OSCCTRL_DPLLCTRLB_LTIME_SHIFT (8) /* Bits 8-10: Lock time */ #define OSCCTRL_DPLLCTRLB_LTIME_MASK (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) # define OSCCTRL_DPLLCTRLB_LTIME_NONE (0 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* No time-out. Automatic lock */ @@ -251,6 +257,7 @@ # define OSCCTRL_DPLLCTRLB_LTIME_9MS (5 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 9MS */ # define OSCCTRL_DPLLCTRLB_LTIME_10MS (6 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 10MS */ # define OSCCTRL_DPLLCTRLB_LTIME_11MS (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 11MS */ + #define OSCCTRL_DPLLCTRLB_LBYPASS (1 << 12) /* Bit 12: Lock bypass */ #define OSCCTRL_DPLLCTRLB_DIV_SHIFT (16) /* Bits 16-26: Clock divider */ #define OSCCTRL_DPLLCTRLB_DIV_MASK (0x7ff << OSCCTRL_DPLLCTRLB_DIV_SHIFT) @@ -275,17 +282,17 @@ #define OSCCTRL_DPLLSTATUS_LOCK (1 << 0) /* Bit 0: DPLL lock status */ #define OSCCTRL_DPLLSTATUS_CLKRDY (1 << 1) /* Bit 1: Output clock ready */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSCCTRL_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_pm.h b/arch/arm/src/samd2l2/hardware/saml_pm.h index 4ab30692592..2d3ec88f2c1 100644 --- a/arch/arm/src/samd2l2/hardware/saml_pm.h +++ b/arch/arm/src/samd2l2/hardware/saml_pm.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_pm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PM_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PM_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ -/* PM register offsets ******************************************************************************/ + ****************************************************************************/ + +/* PM register offsets ******************************************************/ #define SAM_PM_CTRLA_OFFSET 0x0000 /* Control A */ #define SAM_PM_SLEEPCFG_OFFSET 0x0001 /* Sleep configuration */ @@ -49,7 +50,7 @@ #define SAM_PM_INTFLAG_OFFSET 0x0006 /* Interrupt flag status and clear register */ #define SAM_PM_STDBYCFG_OFFSET 0x0008 /* Standby configuration */ -/* PM register addresses ****************************************************************************/ +/* PM register addresses ****************************************************/ #define SAM_PM_CTRLA (SAM_PM_BASE+SAM_PM_CTRLA_OFFSET) #define SAM_PM_SLEEPCFG (SAM_PM_BASE+SAM_PM_SLEEPCFG_OFFSET) @@ -59,7 +60,7 @@ #define SAM_PM_INTFLAG (SAM_PM_BASE+SAM_PM_INTFLAG_OFFSET) #define SAM_PM_STDBYCFG (SAM_PM_BASE+SAM_PM_STDBYCFG_OFFSET) -/* PM register bit definitions **********************************************************************/ +/* PM register bit definitions **********************************************/ /* Control A register */ @@ -80,9 +81,12 @@ #define PM_PLCFG_PLSEL_MASK (3 << PM_PLCFG_PLSEL_SHIFT) # define PM_PLCFG_PLSEL_PL0 (0 << PM_PLCFG_PLSEL_SHIFT) /* Performance level 0 */ # define PM_PLCFG_PLSEL_PL2 (2 << PM_PLCFG_PLSEL_SHIFT) /* Performance level 2 */ + #define PM_PLCFG_PLDIS (1 << 7) /* Bit 7: Performance level disable */ -/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */ +/* Interrupt enable clear, Interrupt enable set, + * and Interrupt flag status and clear registers + */ #define PM_INT_PLRDY (1 << 0) /* Bit 0: Performanc level ready */ @@ -94,6 +98,7 @@ # define PM_STDBYCFG_PDCFG_PD01 (1 << PM_STDBYCFG_PDCFG_SHIFT) /* PD0 ACTIVE; PD1/2 handled by HW */ # define PM_STDBYCFG_PDCFG_PD12 (2 << PM_STDBYCFG_PDCFG_SHIFT) /* PD0/1 ACTIVE; PD2 handled by HW */ # define PM_STDBYCFG_PDCFG_PD012 (3 << PM_STDBYCFG_PDCFG_SHIFT) /* All power domains ACTIVE */ + #define PM_STDBYCFG_DPGPD0 (1 << 4) /* Bit 4: Dynamic power gating for power domain 0 */ #define PM_STDBYCFG_DPGPD1 (1 << 5) /* Bit 5: Dynamic power gating for power domain 1 */ #define PM_STDBYCFG_VREGSMOD_SHIFT (6) /* Bits 6-7: Linked power domain */ @@ -101,18 +106,21 @@ # define PM_STDBYCFG_VREGSMOD_AUTO (0 << PM_STDBYCFG_VREGSMOD_SHIFT) /* Automatic mode */ # define PM_STDBYCFG_VREGSMOD_PERFORMANCE (1 << PM_STDBYCFG_VREGSMOD_SHIFT) /* Performance oriented */ # define PM_STDBYCFG_VREGSMOD_LP (2 << PM_STDBYCFG_VREGSMOD_SHIFT) /* Low power consumption oriented */ + #define PM_STDBYCFG_LINKPD_SHIFT (8) /* Bits 8-9: */ #define PM_STDBYCFG_LINKPD_MASK (3 << PM_STDBYCFG_LINKPD_SHIFT) # define PM_STDBYCFG_LINKPD_DEFAULT (0 << PM_STDBYCFG_LINKPD_SHIFT) /* Power domains not linked */ # define PM_STDBYCFG_LINKPD_PD01 (1 << PM_STDBYCFG_LINKPD_SHIFT) /* Power domains P0/1 linked */ # define PM_STDBYCFG_LINKPD_PD12 (2 << PM_STDBYCFG_LINKPD_SHIFT) /* Power domains P1/P2 linked */ # define PM_STDBYCFG_LINKPD_PD012 (3 << PM_STDBYCFG_LINKPD_SHIFT) /* All power domains linked */ + #define PM_STDBYCFG_BBIASHS_SHIFT (10) /* Bits 10-11: Back bias for HMCRAMCHS */ #define PM_STDBYCFG_BBIASHS_MASK (3 << PM_STDBYCFG_BBIASHS_SHIFT) # define PM_STDBYCFG_BBIASHS_RETBACK (0 << PM_STDBYCFG_BBIASHS_SHIFT) /* Retention back biasing mode */ # define PM_STDBYCFG_BBIASHS_STDBYBACK (1 << PM_STDBYCFG_BBIASHS_SHIFT) /* Standby back biasing mode */ # define PM_STDBYCFG_BBIASHS_STDBYOFF (2 << PM_STDBYCFG_BBIASHS_SHIFT) /* Standby OFF mode */ # define PM_STDBYCFG_BBIASHS_OFF (3 << PM_STDBYCFG_BBIASHS_SHIFT) /* Always OFF mode */ + #define PM_STDBYCFG_BBIASLP_SHIFT (12) /* Bits 12-13: Back bias for HMCRAMCLP */ #define PM_STDBYCFG_BBIASLP_MASK (3 << PM_STDBYCFG_BBIASLP_SHIFT) # define PM_STDBYCFG_BBIASLP_RETBACK (0 << PM_STDBYCFG_BBIASLP_SHIFT) /* Retention back biasing mode */ @@ -120,17 +128,17 @@ # define PM_STDBYCFG_BBIASLP_STDBYOFF (2 << PM_STDBYCFG_BBIASLP_SHIFT) /* Standby OFF mode */ # define PM_STDBYCFG_BBIASLP_OFF (3 << PM_STDBYCFG_BBIASLP_SHIFT) /* Always OFF mode */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PM_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_port.h b/arch/arm/src/samd2l2/hardware/saml_port.h index 95aa3e0a29c..5999b08e9be 100644 --- a/arch/arm/src/samd2l2/hardware/saml_port.h +++ b/arch/arm/src/samd2l2/hardware/saml_port.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_port.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PORT_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PORT_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* PORT register offsets ********************************************************************/ + ****************************************************************************/ + +/* PORT register offsets ****************************************************/ #define SAM_PORTA (0) #define SAM_PORTB (1) @@ -115,7 +116,7 @@ # define SAM_PORT_PINCFG30_OFFSET 0x005e /* Pin configuration register 30 */ # define SAM_PORT_PINCFG31_OFFSET 0x005f /* Pin configuration register 31 */ -/* PORT register addresses ******************************************************************/ +/* PORT register addresses **************************************************/ #define SAM_PORTN_BASE(n) (SAM_PORT_BASE+SAM_PORTN_OFFSET(n)) # define SAM_PORTA_BASE (SAM_PORT_BASE+SAM_PORTA_OFFSET) @@ -315,16 +316,16 @@ # define SAM_PORTC_PINCFG30 (SAM_PORTC_BASE+SAM_PORT_PINCFG30_OFFSET) # define SAM_PORTC_PINCFG31 (SAM_PORTC_BASE+SAM_PORT_PINCFG31_OFFSET) -/* PORT register bit definitions ************************************************************/ +/* PORT register bit definitions ********************************************/ -/* Data direction, data direction clear, data direction set, and data direction toggle - * registers +/* Data direction, data direction clear, data direction set, + * and data direction toggle registers */ #define PORT_DIR(n) (1 << n) /* Port data n, direction, n=0-31 */ -/* Data output value, data output value clear, data output value set, and data output - * value toggle registers +/* Data output value, data output value clear, data output value set, + * and data output value toggle registers */ #define PORT_OUT(n) (1 << n) /* Port data n output value, n=0-31 */ @@ -405,6 +406,7 @@ # define PORT_PMUXE_PERIPHG (6 << PORT_PMUXE_SHIFT) /* Peripheral function G */ # define PORT_PMUXE_PERIPHH (7 << PORT_PMUXE_SHIFT) /* Peripheral function H */ # define PORT_PMUXE_PERIPHI (8 << PORT_PMUXE_SHIFT) /* Peripheral function I */ + #define PORT_PMUXO_SHIFT (4) /* Bits 4-7: Peripheral multiplexing odd */ #define PORT_PMUXO_MASK (15 << PORT_PMUXO_SHIFT) # define PORT_PMUXO_PERIPHA (0 << PORT_PMUXO_SHIFT) /* Peripheral function A */ @@ -424,17 +426,17 @@ #define PORT_PINCFG_PULLEN (1 << 2) /* Bit 2: Pull Enable */ #define PORT_PINCFG_DRVSTR (1 << 6) /* Bit 6: Output Driver Strength Selection */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PORT_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_rstc.h b/arch/arm/src/samd2l2/hardware/saml_rstc.h index 4503eca8597..43f3067e044 100644 --- a/arch/arm/src/samd2l2/hardware/saml_rstc.h +++ b/arch/arm/src/samd2l2/hardware/saml_rstc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_rstc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_RSTC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_RSTC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* RSTC register offsets *********************************************************************/ + ****************************************************************************/ + +/* RSTC register offsets ****************************************************/ #define SAM_RSTC_RCAUSE_OFFSET 0x0000 /* Reset cause */ #define SAM_RSTC_BKUPEXIT_OFFSET 0x0002 /* Backup exit source */ @@ -48,7 +49,7 @@ #define SAM_RSTC_WKEN_OFFSET 0x000c /* Wakeup enable */ #define SAM_RSTC_WKCAUSE_OFFSET 0x0010 /* Wakeup cause */ -/* RSTC register addresses *******************************************************************/ +/* RSTC register addresses **************************************************/ #define SAM_RSTC_RCAUSE (SAM_RSTC_BASE+SAM_RSTC_RCAUSE_OFFSET) #define SAM_RSTC_BKUPEXIT (SAM_RSTC_BASE+SAM_RSTC_BKUPEXIT_OFFSET) @@ -57,7 +58,7 @@ #define SAM_RSTC_WKEN (SAM_RSTC_BASE+SAM_RSTC_WKEN_OFFSET) #define SAM_RSTC_WKCAUSE (SAM_RSTC_BASE+SAM_RSTC_WKCAUSE_OFFSET) -/* RSTC register bit definitions *************************************************************/ +/* RSTC register bit definitions ********************************************/ /* Reset cause */ @@ -115,17 +116,17 @@ # define RSTC_WKCAUSE_PIN6 (1 << 6) /* Bit 6: WKCAUSE 6 active and enabled */ # define RSTC_WKCAUSE_PIN7 (1 << 7) /* Bit 7: WKCAUSE 7 active and enabled */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_RSTC_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_sercom.h b/arch/arm/src/samd2l2/hardware/saml_sercom.h index a4194c6fe92..fc3939dbea9 100644 --- a/arch/arm/src/samd2l2/hardware/saml_sercom.h +++ b/arch/arm/src/samd2l2/hardware/saml_sercom.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_sercom.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,28 +26,28 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SERCOM_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SERCOM_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SERCOM_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_spi.h b/arch/arm/src/samd2l2/hardware/saml_spi.h index 1c9ca65c374..94684a90c7b 100644 --- a/arch/arm/src/samd2l2/hardware/saml_spi.h +++ b/arch/arm/src/samd2l2/hardware/saml_spi.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SPI_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SPI_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -37,10 +37,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* SPI register offsets *********************************************************************/ + ****************************************************************************/ + +/* SPI register offsets *****************************************************/ #define SAM_SPI_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_SPI_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -54,7 +55,7 @@ #define SAM_SPI_DATA_OFFSET 0x0028 /* Data register */ #define SAM_SPI_DBGCTRL_OFFSET 0x0030 /* Debug control register */ -/* SPI register addresses *******************************************************************/ +/* SPI register addresses ***************************************************/ #define SAM_SPI0_CTRLA (SAM_SERCOM0_BASE+SAM_SPI_CTRLA_OFFSET) #define SAM_SPI0_CTRLB (SAM_SERCOM0_BASE+SAM_SPI_CTRLB_OFFSET) @@ -128,7 +129,7 @@ #define SAM_SPI5_DATA (SAM_SERCOM5_BASE+SAM_SPI_DATA_OFFSET) #define SAM_SPI5_DBGCTRL (SAM_SERCOM5_BASE+SAM_SPI_DBGCTRL_OFFSET) -/* SPI register bit definitions *************************************************************/ +/* SPI register bit definitions *********************************************/ /* Control A register */ @@ -138,24 +139,30 @@ #define SPI_CTRLA_MODE_MASK (7 << SPI_CTRLA_MODE_SHIFT) # define SPI_CTRLA_MODE_SLAVE (2 << SPI_CTRLA_MODE_SHIFT) /* SPI slave operation */ # define SPI_CTRLA_MODE_MASTER (3 << SPI_CTRLA_MODE_SHIFT) /* SPI master operation */ + #define SPI_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define SPI_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ #define SPI_CTRLA_DOPO_SHIFT (16) /* Bit 16-17: Data out pinout */ + #define SPI_CTRLA_DOPO_MASK (3 << SPI_CTRLA_DOPO_SHIFT) /* Bit 16-17: Data out pinout */ + # define SPI_CTRLA_DOPO_DOPAD012 (0 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD1 SS=PAD2 */ # define SPI_CTRLA_DOPO_DOPAD231 (1 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD2 SCK=PAD3 SS=PAD1 */ # define SPI_CTRLA_DOPO_DOPAD312 (2 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD3 SCK=PAD1 SS=PAD2 */ # define SPI_CTRLA_DOPO_DOPAD031 (3 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD3 SS=PAD1 */ + #define SPI_CTRLA_DIPO_SHIFT (20) /* Bits 20-21: Data in pinout */ #define SPI_CTRLA_DIPO_MASK (3 << SPI_CTRLA_DIPO_SHIFT) # define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD0 for DI */ # define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD1 for DI */ # define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD2 for DI */ # define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD3 for DI */ + #define SPI_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */ #define SPI_CTRLA_FORM_MASK (7 << SPI_CTRLA_FORM_SHIFT) # define SPI_CTRLA_FORM_SPI (0 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (no address) */ # define SPI_CTRLA_FORM_ADDR (2 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (w/address) */ + #define SPI_CTRLA_CPHA (1 << 28) /* Bit 28: Clock phase */ #define SPI_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */ #define SPI_CTRLA_DORD (1 << 30) /* Bit 30: Data order */ @@ -168,6 +175,7 @@ #define SPI_CTRLB_CHSIZE_MASK (7 << SPI_CTRLB_CHSIZE_SHIFT) # define SPI_CTRLB_CHSIZE_8BITS (0 << SPI_CTRLB_CHSIZE_SHIFT) /* 8 bits */ # define SPI_CTRLB_CHSIZE_9BITS (1 << SPI_CTRLB_CHSIZE_SHIFT) /* 9 bits */ + #define SPI_CTRLB_PLOADEN (1 << 6) /* Bit 6: Slave Data Preload Enable */ #define SPI_CTRLB_SSDE (1 << 9) /* Bit 9: Slave select low detect enable */ #define SPI_CTRLB_MSSEN (1 << 13) /* Bit 13: Master slave select enable */ @@ -176,12 +184,13 @@ # define SPI_CTRLB_AMODE_ADDRMASK (0 << SPI_CTRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */ # define SPI_CTRLB_AMODE_2ADDRS (1 << SPI_CTRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */ # define SPI_CTRLB_AMODE_RANGE (2 << SPI_CTRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */ + #define SPI_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */ /* Baud register (8-bit baud value) */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define SPI_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */ @@ -221,17 +230,17 @@ #define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SPI_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_supc.h b/arch/arm/src/samd2l2/hardware/saml_supc.h index 658171da484..e51dee5ae8f 100644 --- a/arch/arm/src/samd2l2/hardware/saml_supc.h +++ b/arch/arm/src/samd2l2/hardware/saml_supc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_supc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SUPC_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SUPC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* SUPC register offsets *********************************************************************/ + ****************************************************************************/ + +/* SUPC register offsets ****************************************************/ #define SAM_SUPC_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */ #define SAM_SUPC_INTENSET_OFFSET 0x0004 /* Interrupt enable set */ @@ -56,7 +57,7 @@ #define SAM_SUPC_BKOUT_OFFSET 0x0024 /* Backup output control */ #define SAM_SUPC_BKIN_OFFSET 0x0028 /* Backup input value */ -/* SUPC register addresses *******************************************************************/ +/* SUPC register addresses **************************************************/ #define SAM_SUPC_INTENCLR (SAM_SUPC_BASE+SAM_SUPC_INTENCLR_OFFSET) #define SAM_SUPC_INTENSET (SAM_SUPC_BASE+SAM_SUPC_INTENSET_OFFSET) @@ -70,10 +71,10 @@ #define SAM_SUPC_BKOUT (SAM_SUPC_BASE+SAM_SUPC_BKOUT_OFFSET) #define SAM_SUPC_BKIN (SAM_SUPC_BASE+SAM_SUPC_BKIN_OFFSET) -/* SUPC register bit definitions *************************************************************/ +/* SUPC register bit definitions ********************************************/ -/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and - * Status registers. +/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and + * clear, and Status registers. */ #define SUPC_INT_BOD33RDY (1 << 0) /* Bit 0: BOD33 ready interrupt */ @@ -99,6 +100,7 @@ # define SUPC_BOD33_ACTION_RESET (1 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 generates reset */ # define SUPC_BOD33_ACTION_INTR (2 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 generates interrupt */ # define SUPC_BOD33_ACTION_BKUP (3 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 backup sleep mode */ + #define SUPC_BOD33_STDBYCFG (1 << 5) /* Bit 5: BOD33 configuration in standby sleep mode */ #define SUPC_BOD33_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define SUPC_BOD33_RUNBKUP (1 << 7) /* Bit 7: BOD33 configuration in backup sleep */ @@ -123,6 +125,7 @@ # define SUPC_BOD33_PSEL_DIV16K (13 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 16384 */ # define SUPC_BOD33_PSEL_DIV32K (14 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 32768 */ # define SUPC_BOD33_PSEL_DIV64K (15 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 65536 */ + #define SUPC_BOD33_LEVEL_SHIFT (16) /* Bits 16-21: BOD33 threshold level VDD */ #define SUPC_BOD33_LEVEL_MASK (0x3f << SUPC_BOD33_LEVEL_SHIFT) # define SUPC_BOD33_LEVEL(n) ((uint32_t)(n) << SUPC_BOD33_LEVEL_SHIFT) @@ -140,6 +143,7 @@ # define SUPC_BOD12_ACTION_NONE (0 << SUPC_BOD12_ACTION_SHIFT) /* No action */ # define SUPC_BOD12_ACTION_RESET (1 << SUPC_BOD12_ACTION_SHIFT) /* BOD12 generates reset */ # define SUPC_BOD12_ACTION_INTR (2 << SUPC_BOD12_ACTION_SHIFT) /* BOD12 generates interrupt */ + #define SUPC_BOD12_STDBYCFG (1 << 5) /* Bit 5: BOD12 configuration in standby sleep mode */ #define SUPC_BOD12_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define SUPC_BOD12_ACTCFG (1 << 8) /* Bit 8: BOD12 configuration in active sleep */ @@ -162,6 +166,7 @@ # define SUPC_BOD12_PSEL_DIV16K (13 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 16384 */ # define SUPC_BOD12_PSEL_DIV32K (14 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 32768 */ # define SUPC_BOD12_PSEL_DIV64K (15 << SUPC_BOD12_PSEL_SHIFT) /* Divide clock by 65536 */ + #define SUPC_BOD12_LEVEL_SHIFT (16) /* Bits 16-21: BOD12 threshold level */ #define SUPC_BOD12_LEVEL_MASK (0x3f << SUPC_BOD12_LEVEL_SHIFT) # define SUPC_BOD12_LEVEL(n) ((uint32_t)(n) << SUPC_BOD12_LEVEL_SHIFT) @@ -196,7 +201,6 @@ # define SUPC_VREF_SEL_2V4 (6 << SUPC_VREF_SEL_SHIFT) /* 2.4V voltage reference typical value */ # define SUPC_VREF_SEL_2V5 (7 << SUPC_VREF_SEL_SHIFT) /* 5.5V voltage reference typical value */ - /* Battery backup power switch control */ #define SUPC_BBPS_CONFIG_SHIFT (0) /* Bits 0-1: Battery backup power switch configuration */ @@ -205,6 +209,7 @@ # define SUPC_BBPS_CONFIG_APWS (1 << SUPC_BBPS_CONFIG_SHIFT) /* Automatic power switch */ # define SUPC_BBPS_CONFIG_FORCED (2 << SUPC_BBPS_CONFIG_SHIFT) /* Backup domain from batter backup power */ # define SUPC_BBPS_CONFIG_BOD33 (3 << SUPC_BBPS_CONFIG_SHIFT) /* Power switch handled by BOD33 */ + #define SUPC_BBPS_WAKEEN (1 << 2) /* Bit 2: Wake enable */ #define SUPC_BBPS_PSOKEN (1 << 3) /* Bit 3: Power supply OK enable */ @@ -233,17 +238,17 @@ # define SUPC_BKIN_OUT0 (2 << SUPC_BKIN_SHIFT) /* Input value of OUT[0] pin */ # define SUPC_BKIN_OUT1 (4 << SUPC_BKIN_SHIFT) /* Input value of OUT[1] pin */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SUPC_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_trng.h b/arch/arm/src/samd2l2/hardware/saml_trng.h index e02310d8621..4e2206ae000 100644 --- a/arch/arm/src/samd2l2/hardware/saml_trng.h +++ b/arch/arm/src/samd2l2/hardware/saml_trng.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_trng.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_TRNG_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_TRNG_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* TRNG register offsets ********************************************************************/ + ****************************************************************************/ + +/* TRNG register offsets ****************************************************/ #define SAM_TRNG_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_TRNG_EVCTRL_OFFSET 0x0004 /* Event control register */ @@ -48,7 +49,7 @@ #define SAM_TRNG_INTFLAG_OFFSET 0x000a /* Interrupt flag and status clear register */ #define SAM_TRNG_DATA_OFFSET 0x0020 /* Output data register */ -/* TRNG register addresses ******************************************************************/ +/* TRNG register addresses **************************************************/ #define SAM_TRNG_CTRLA (SAM_TRNG_BASE+SAM_TRNG_CTRLA_OFFSET) #define SAM_TRNG_EVCTRL (SAM_TRNG_BASE+SAM_TRNG_EVCTRL_OFFSET) @@ -57,32 +58,32 @@ #define SAM_TRNG_INTFLAG (SAM_TRNG_BASE+SAM_TRNG_INTFLAG_OFFSET) #define SAM_TRNG_DATA (SAM_TRNG_BASE+SAM_TRNG_DATA_OFFSET) -/* TRNG register bit definitions ************************************************************/ +/* TRNG register bit definitions ********************************************/ /* Control register */ #define TRNG_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */ #define TRNG_CTRLA_WEN (1 << 6) /* Bit 6: Run in standby */ -/* Event control register, Interrupt enable clear, interrupt enable set register, interrupt - * flag status registers. +/* Event control register, Interrupt enable clear, interrupt enable set + * register, interrupt flag status registers. */ #define TRNG_EVCTRL_DATARDY (1 << 0) /* Bit 0: Data ready */ /* Data register (32-bit data) */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_TRNG_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_usart.h b/arch/arm/src/samd2l2/hardware/saml_usart.h index 84685e82802..dc78accbc64 100644 --- a/arch/arm/src/samd2l2/hardware/saml_usart.h +++ b/arch/arm/src/samd2l2/hardware/saml_usart.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_usart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USART_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USART_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -37,24 +37,25 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* USART register offsets *******************************************************************/ + ****************************************************************************/ + +/* USART register offsets ***************************************************/ #define SAM_USART_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_USART_CTRLB_OFFSET 0x0004 /* Control B register */ #define SAM_USART_BAUD_OFFSET 0x000c /* Baud register */ -#define SAM_USART_RXPL_OFFSET 0x000e /* Receive pulse length register */ +#define SAM_USART_RXPL_OFFSET 0x000e /* Receive pulse length register */ #define SAM_USART_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */ #define SAM_USART_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */ #define SAM_USART_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */ #define SAM_USART_STATUS_OFFSET 0x001a /* Status register */ -#define SAM_USART_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */ +#define SAM_USART_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */ #define SAM_USART_DATA_OFFSET 0x0028 /* Data register */ #define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */ -/* USART register addresses *****************************************************************/ +/* USART register addresses *************************************************/ #define SAM_USART0_CTRLA (SAM_SERCOM0_BASE+SAM_USART_CTRLA_OFFSET) #define SAM_USART0_CTRLB (SAM_SERCOM0_BASE+SAM_USART_CTRLB_OFFSET) @@ -128,7 +129,7 @@ #define SAM_USART5_DATA (SAM_SERCOM5_BASE+SAM_USART_DATA_OFFSET) #define SAM_USART5_DBGCTRL (SAM_SERCOM5_BASE+SAM_USART_DBGCTRL_OFFSET) -/* USART register bit definitions ***********************************************************/ +/* USART register bit definitions *******************************************/ /* Control A register */ @@ -138,6 +139,7 @@ #define USART_CTRLA_MODE_MASK (7 << USART_CTRLA_MODE_SHIFT) # define USART_CTRLA_MODE_EXTUSART (0 << USART_CTRLA_MODE_SHIFT) /* USART with external clock */ # define USART_CTRLA_MODE_INTUSART (1 << USART_CTRLA_MODE_SHIFT) /* USART with internal clock */ + #define USART_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ #define USART_CTRLA_SAMPR_SHIFT (11) /* Bits 11-12: Sample rate */ @@ -147,17 +149,20 @@ # define USART_CTRLA_SAMPR_8XA (2 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; arithmetic baud */ # define USART_CTRLA_SAMPR_8XF (3 << USART_CTRLA_SAMPR_SHIFT) /* 8x oversampling; fractional baud */ # define USART_CTRLA_SAMPR_3XA (4 << USART_CTRLA_SAMPR_SHIFT) /* 3x oversampling; arithmetic baud */ + #define USART_CTRLA_TXPO_SHIFT (16) /* Bits 16-17: Transmit data pinout */ #define USART_CTRLA_TXPO_MASK (3 << USART_CTRLA_TXPO_SHIFT) # define USART_CTRLA_TXPAD0_1 (0 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[0]; XCK=PAD[1] */ # define USART_CTRLA_TXPAD2 (1 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[2]; XCK=PAD[3] */ # define USART_CTRLA_TXPAD0_2 (2 << USART_CTRLA_TXPO_SHIFT) /* TxD=SERCOM PAD[0]; RTS=PAD[2]; CTS=PAD[3] */ + #define USART_CTRLA_RXPO_SHIFT (20) /* Bits 20-21: Receive data pinout */ #define USART_CTRLA_RXPO_MASK (3 << USART_CTRLA_RXPO_SHIFT) # define USART_CTRLA_RXPAD0 (0 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD[0] */ # define USART_CTRLA_RXPAD1 (1 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD[1] */ # define USART_CTRLA_RXPAD2 (2 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD[2] */ # define USART_CTRLA_RXPAD3 (3 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD[3] */ + #define USART_CTRLA_SAMPA_SHIFT (22) /* Bits 22-23: Sample adjustment */ #define USART_CTRLA_SAMPA_MASK (3 << USART_CTRLA_SAMPA_SHIFT) # define USART_CTRLA_SAMPA_789 (0 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 7-8-9 */ @@ -168,18 +173,22 @@ # define USART_CTRLA_SAMPA_456 (1 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 4-5-6 */ # define USART_CTRLA_SAMPA_567 (2 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 5-6-7 */ # define USART_CTRLA_SAMPA_678 (3 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 6-7-8 */ + #define USART_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */ #define USART_CTRLA_FORM_MASK (7 << USART_CTRLA_FORM_SHIFT) # define USART_CTRLA_FORM_NOPARITY (0 << USART_CTRLA_FORM_SHIFT) /* USART frame (no parity) */ # define USART_CTRLA_FORM_PARITY (1 << USART_CTRLA_FORM_SHIFT) /* USART frame (w/parity) */ # define USART_CTRLA_FORM_AUTOBAUD (4 << USART_CTRLA_FORM_SHIFT) /* Auto-baud (no parity) */ # define USART_CTRLA_FORM_AUTOBAUDP (5 << USART_CTRLA_FORM_SHIFT) /* Auto-baud (w/ parity) */ + #define USART_CTRLA_CMODE (1 << 28) /* Bit 28: Communication mode */ # define USART_CTRLA_ASYNCH (0) # define USART_CTRLA_SYNCH USART_CTRLA_CMODE #define USART_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */ + # define USART_CTRLA_CPOL_NORMAL (0) /* Rising XCK edge Falling XCK edge */ # define USART_CTRLA_CPOL_INVERTED USART_CTRLA_CPOL /* Falling XCK edge Rising XCK edge */ + #define USART_CTRLA_DORD (1 << 30) /* Bit 30: Data order */ # define USART_CTRLA_MSBFIRST (0) # define USART_CTRLA_LSBFIRST USART_CTRLA_DORD @@ -193,6 +202,7 @@ # define USART_CTRLB_CHSIZE_5BITS (5 << USART_CTRLB_CHSIZE_SHIFT) /* 5 bits */ # define USART_CTRLB_CHSIZE_6BITS (6 << USART_CTRLB_CHSIZE_SHIFT) /* 6 bits */ # define USART_CTRLB_CHSIZE_7BITS (7 << USART_CTRLB_CHSIZE_SHIFT) /* 7 bits */ + #define USART_CTRLB_SBMODE (1 << 6) /* Bit 6: Stop bit mode */ # define USART_CTRLB_SBMODE_1 (0) # define USART_CTRLB_SBMODE_2 USART_CTRLB_SBMODE @@ -208,10 +218,11 @@ #define USART_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */ /* Baud register (16-bit baud value) */ + /* Receive pulse length register (8-bit value) */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define USART_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */ @@ -249,17 +260,17 @@ #define USART_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USART_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_usb.h b/arch/arm/src/samd2l2/hardware/saml_usb.h index ada15dd111f..77f2067ae2b 100644 --- a/arch/arm/src/samd2l2/hardware/saml_usb.h +++ b/arch/arm/src/samd2l2/hardware/saml_usb.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_usb.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USB_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USB_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,11 +36,11 @@ #if defined(CONFIG_ARCH_FAMILY_SAML21) || defined(CONFIG_ARCH_FAMILY_SAMD21) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Capabilities and characteristics of endpoints ********************************************/ +/* Capabilities and characteristics of endpoints ****************************/ /* EP EP BANKS EP SIZE EP TYPE * --- --------- --------- --------- @@ -62,7 +62,7 @@ #define SAM_USB_ISOCHRONOUS(ep) (true) #define SAM_USB_INTERRUPT(ep) (true) -/* USB register offsets ********************************************************************/ +/* USB register offsets *****************************************************/ /* Common USB Device/Host Register Offsets */ @@ -158,7 +158,7 @@ #define SAM_USBHOST_CTRLPIPE_OFFSET 0x000c /* Host control pipe (Bank 0 only) */ #define SAM_USBHOST_STATUSPIPE_OFFSET 0x000e /* Host status pipe (Both banks) */ -/* USB register addresses ******************************************************************/ +/* USB register addresses ***************************************************/ /* Common USB Device/Host Register Addresses */ @@ -221,7 +221,7 @@ #define SAM_USBHOST_PINTENCLR(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PINTENCLR_OFFSET) #define SAM_USBHOST_PINTENSET(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PINTENSET_OFFSET) -/* USB register bit definitions ************************************************************/ +/* USB register bit definitions *********************************************/ /* Common USB Device/Host Register Offsets */ @@ -286,6 +286,7 @@ # define USBDEV_CTRLB_SPDCONF_LOW (1 << USBDEV_CTRLB_SPDCONF_SHIFT) /* Low speed */ # define USBDEV_CTRLB_SPDCONF_HIGH (2 << USBDEV_CTRLB_SPDCONF_SHIFT) /* High speed capable */ # define USBDEV_CTRLB_SPDCONF_HIGH_TM (3 << USBDEV_CTRLB_SPDCONF_SHIFT) /* High speed Test Mode */ + #define USBDEV_CTRLB_NREPLY (1 << 4) /* Bit 4: No reply except SETUP token */ #define USBDEV_CTRLB_GNAK (1 << 9) /* Bit 9: Global NAK */ #define USBDEV_CTRLB_LPMHDSK_SHIFT (10) /* Bits 10-11: Link power management handshake */ @@ -307,6 +308,7 @@ #define USBDEV_STATUS_SPEED_MASK (3 << USBDEV_STATUS_SPEED_SHIFT) # define USBDEV_STATUS_SPEED_LOW (0 << USBDEV_STATUS_SPEED_SHIFT) /* Low speed */ # define USBDEV_STATUS_SPEED_FULL (1 << USBDEV_STATUS_SPEED_SHIFT) /* Full speed */ + #define USBDEV_STATUS_LNSTATE_SHIFT (6) /* Bits 6-7: USB line status */ #define USBDEV_STATUS_LNSTATE_MASK (3 << USBDEV_STATUS_LNSTATE_SHIFT) # define USBDEV_STATUS_LNSTATE_SE0 (0 << USBDEV_STATUS_LNSTATE_SHIFT) /* SE0/RESET */ @@ -321,8 +323,8 @@ #define USBDEV_FNUM_MASK (0x7ff << USBDEV_FNUM_SHIFT) #define USBDEV_FNUM_FNCERR (1 << 15) /* Bit 15: Frame number CRC error */ -/* Common definitions for Device Interrupt Enable Clear Register, Device interrupt - * Enable Set Register, and SAM_USBDEV_INTFLAG_OFFSET +/* Common definitions for Device Interrupt Enable Clear Register, Device + * interrupt Enable Set Register, and SAM_USBDEV_INTFLAG_OFFSET */ #define USBDEV_INT_SUSPEND (1 << 0) /* Bit 0: Suspend interrupt */ @@ -349,6 +351,7 @@ # define USBDEV_EPCCFG_EPTYPE0_BULKOUT (3 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 bulk OUT */ # define USBDEV_EPCCFG_EPTYPE0_INTOUT (4 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 interrupt OUT */ # define USBDEV_EPCCFG_EPTYPE0_DBIN (5 << USBDEV_EPCFG_EPTYPE0_SHIFT) /* Bank 0 dual bank IN */ + #define USBDEV_EPCFG_EPTYPE1_SHIFT (4) /* Bits 4-6: Endpoint type for IN direction */ #define USBDEV_EPCFG_EPTYPE1_MASK (7 << USBDEV_EPCFG_EPTYPE1_SHIFT) # define USBDEV_EPCCFG_EPTYPE1_DISABLED (0 << USBDEV_EPCFG_EPTYPE1_SHIFT) /* Bank 1 disabled */ @@ -370,8 +373,9 @@ #define USBDEV_EPSTATUS_BK0RDY (1 << 6) /* Bit 6: Bank 0 ready */ #define USBDEV_EPSTATUS_BK1RDY (1 << 7) /* Bit 7: Bank 1 ready */ -/* Common definitions for Device Endpoint Interrupt Flag Register, Device Endpoint - * Interrupt Enable Register, and Device Endpoint Interrupt Set Register +/* Common definitions for Device Endpoint Interrupt Flag Register, Device + * Endpoint Interrupt Enable Register, and Device Endpoint Interrupt Set + * Register */ #define USBDEV_EPINT_TRCPT0 (1 << 0) /* Bit 0: Transmit complete 0 interrupt */ @@ -404,6 +408,7 @@ # define USBDEV_PKTSIZE_SIZE_256B (5 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 256 bytes (isoc only) */ # define USBDEV_PKTSIZE_SIZE_512B (6 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 512 bytes (isoc only) */ # define USBDEV_PKTSIZE_SIZE_1023B (7 << USBDEV_PKTSIZE_SIZE_SHIFT) /* 1023 bytes (isoc only) */ + #define USBDEV_PKTSIZE_AUTOZLP (1 << 31) /* Bit 31: Automatic zero length packet */ /* Extended Register (Bank 0 only) */ @@ -428,6 +433,7 @@ #define USBHOST_CTRLB_SPDCONF_SHIFT (2) /* Bits 2-3: Host speed configuration */ #define USBHOST_CTRLB_SPDCONF_MASK (3 << USBHOST_CTRLB_SPDCONF_SHIFT) # define USBHOST_CTRLB_SPDCONF_LF (0 << USBHOST_CTRLB_SPDCONF_SHIFT) /* Low and full capable */ + #define USBHOST_CTRLB_TSTJ (1 << 5) /* Bit 5: TSTJ */ #define USBHOST_CTRLB_TSTK (1 << 6) /* Bit 6: TSTK */ #define USBHOST_CTRLB_SOFE (1 << 8) /* Bit 8: Start of frame generation enable */ @@ -448,6 +454,7 @@ #define USBHOST_STATUS_SPEED_MASK (3 << USBHOST_STATUS_SPEED_SHIFT) # define USBHOST_STATUS_SPEED_LOW (0 << USBHOST_STATUS_SPEED_SHIFT) /* Full speed mode */ # define USBHOST_STATUS_SPEED_FULL (2 << USBHOST_STATUS_SPEED_SHIFT) /* Low speed mode */ + #define USBHOST_STATUS_LNSTATE_SHIFT (6) /* Bits 6-7: USB line status */ #define USBHOST_STATUS_LNSTATE_MASK (3 << USBHOST_STATUS_LNSTATE_SHIFT) # define USBHOST_STATUS_LNSTATE_SE0 (0 << USBHOST_STATUS_LNSTATE_SHIFT) /* SE0/RESET */ @@ -461,8 +468,9 @@ /* Host Frame Length Register (8-bit data) */ -/* Common definitions for Host Interrupt Enable Clear Register, Host Interrupt Enable - * Set Register, and Host Interrupt Flag Status and Clear Register +/* Common definitions for Host Interrupt Enable Clear Register, Host + * Interrupt Enable Set Register, and Host Interrupt Flag Status and + * Clear Register */ #define USBHOST_INT_HSOF (1 << 2) /* Bit 2: Host start of frame interrupt */ @@ -486,8 +494,8 @@ # define USBHOST_PCFG_PTOKEN_IN (1 << USBHOST_PCFG_PTOKEN_SHIFT) # define USBHOST_PCFG_PTOKEN_OUT (2 << USBHOST_PCFG_PTOKEN_SHIFT) #define USBHOST_PCFG_BK (1 << 2) /* Bit 2: Pipe bank */ - #define USBHOST_PCFG_BK_SINGLE (0) /* 0=Single bank endpoint */ - #define USBHOST_PCFG_BK_DUAL (1 << 2) /* 1=Dual bank endpoint */ +# define USBHOST_PCFG_BK_SINGLE (0) /* 0=Single bank endpoint */ +# define USBHOST_PCFG_BK_DUAL (1 << 2) /* 1=Dual bank endpoint */ #define USBHOST_PCFG_PTYPE_SHIFT (3) /* Bits 3-5: Type of pipe */ #define USBHOST_PCFG_PTYPE_MASK (7 << USBHOST_PCFG_PTYPE_SHIFT) # define USBHOST_PCFG_PTYPE_DISABLED (0 << USBHOST_PCFG_PTYPE_SHIFT) /* Disabled */ @@ -499,8 +507,8 @@ /* Interval for Bulk-OUT/Ping Transaction Register (8-bit data) */ -/* Common definitions for Pipe Status Clear Register, Pipe Status Set Register, and - * Pipe Status Register +/* Common definitions for Pipe Status Clear Register, Pipe Status Set + * Register, and Pipe Status Register */ #define USBHOST_PSTATUS_DTGL (1 << 0) /* Bit 0: Data toggle sequence */ @@ -509,8 +517,8 @@ #define USBHOST_PSTATUS_BK0RDY (1 << 6) /* Bit 6: Bank 0 ready */ #define USBHOST_PSTATUS_BK1RDY (1 << 7) /* Bit 7: Bank 1 ready */ -/* Common definitions for Host Pipe Interrupt Flag Register, Host Pipe Interrupt Clear - * Register, and Host Pipe Interrupt Set Register +/* Common definitions for Host Pipe Interrupt Flag Register, Host Pipe + * Interrupt Clear Register, and Host Pipe Interrupt Set Register */ #define USBHOST_PINTFLAG_TRCPT0 (1 << 0) /* Bit 0: Transfer complete 0 interrupt */ @@ -542,6 +550,7 @@ # define USBHOST_PKTSIZE_SIZE_256B (5 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 256 bytes (isoc only) */ # define USBHOST_PKTSIZE_SIZE_512B (6 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 512 bytes (isoc only) */ # define USBHOST_PKTSIZE_SIZE_1023B (7 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 1023 bytes (isoc only) */ + #define USBHOST_PKTSIZE_AUTOZLP (1 << 31) /* Bit 31: Automatic zero length packet */ /* Extended register (Bank 0 only) */ @@ -581,9 +590,9 @@ #define USBHOST_STATUSPIPE_ERCNT_MASK (7 << USBHOST_STATUSPIPE_ERCNT_SHIFT) # define USBHOST_STATUSPIPE_ERCNT(n) ((uint16_t)(n) << USBHOST_STATUSPIPE_ERCNT_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ /* Device Endpoint Descriptor. See USBDEV_* bit definitions above. */ @@ -609,13 +618,13 @@ struct usbhost_pipedesc_s uint16_t statuspipe; /* 0x000e-0x000f: Host status pipe (Both banks) */ }; -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USB_H */ diff --git a/arch/arm/src/samd2l2/hardware/saml_wdt.h b/arch/arm/src/samd2l2/hardware/saml_wdt.h index a0de8a08bc1..7d6d32f95e9 100644 --- a/arch/arm/src/samd2l2/hardware/saml_wdt.h +++ b/arch/arm/src/samd2l2/hardware/saml_wdt.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/hardware/saml_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ /* References: * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller @@ -26,9 +26,9 @@ #ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_WDT_H #define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_WDT_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -36,10 +36,11 @@ #ifdef CONFIG_ARCH_FAMILY_SAML21 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* WDT register offsets *********************************************************************/ + ****************************************************************************/ + +/* WDT register offsets *****************************************************/ #define SAM_WDT_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_WDT_CONFIG_OFFSET 0x0001 /* Configuration register */ @@ -50,7 +51,7 @@ #define SAM_WDT_SYNCBUSY_OFFSET 0x0008 /* Synchronization busy register */ #define SAM_WDT_CLEAR_OFFSET 0x000c /* Clear register */ -/* WDT register addresses *******************************************************************/ +/* WDT register addresses ***************************************************/ #define SAM_WDT_CTRLA (SAM_WDT_BASE+SAM_WDT_CTRLA_OFFSET) #define SAM_WDT_CONFIG (SAM_WDT_BASE+SAM_WDT_CONFIG_OFFSET) @@ -61,7 +62,7 @@ #define SAM_WDT_SYNCBUSY (SAM_WDT_BASE+SAM_WDT_SYNCBUSY_OFFSET) #define SAM_WDT_CLEAR (SAM_WDT_BASE+SAM_WDT_CLEAR_OFFSET) -/* WDT register bit definitions *************************************************************/ +/* WDT register bit definitions *********************************************/ /* Control register */ @@ -73,30 +74,31 @@ #define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */ #define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT) -# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */ -# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */ -# define WDT_CONFIG_PER_32 (2 << WDT_CONFIG_PER_SHIFT) /* 32 clock cycles */ -# define WDT_CONFIG_PER_64 (3 << WDT_CONFIG_PER_SHIFT) /* 64 clock cycles */ -# define WDT_CONFIG_PER_128 (4 << WDT_CONFIG_PER_SHIFT) /* 128 clock cycles */ -# define WDT_CONFIG_PER_256 (5 << WDT_CONFIG_PER_SHIFT) /* 256 clocks cycles */ -# define WDT_CONFIG_PER_512 (6 << WDT_CONFIG_PER_SHIFT) /* 512 clocks cycles */ -# define WDT_CONFIG_PER_1K (7 << WDT_CONFIG_PER_SHIFT) /* 1024 clock cycles */ -# define WDT_CONFIG_PER_2K (8 << WDT_CONFIG_PER_SHIFT) /* 2048 clock cycles */ -# define WDT_CONFIG_PER_4K (9 << WDT_CONFIG_PER_SHIFT) /* 4096 clock cycles */ +# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */ +# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */ +# define WDT_CONFIG_PER_32 (2 << WDT_CONFIG_PER_SHIFT) /* 32 clock cycles */ +# define WDT_CONFIG_PER_64 (3 << WDT_CONFIG_PER_SHIFT) /* 64 clock cycles */ +# define WDT_CONFIG_PER_128 (4 << WDT_CONFIG_PER_SHIFT) /* 128 clock cycles */ +# define WDT_CONFIG_PER_256 (5 << WDT_CONFIG_PER_SHIFT) /* 256 clocks cycles */ +# define WDT_CONFIG_PER_512 (6 << WDT_CONFIG_PER_SHIFT) /* 512 clocks cycles */ +# define WDT_CONFIG_PER_1K (7 << WDT_CONFIG_PER_SHIFT) /* 1024 clock cycles */ +# define WDT_CONFIG_PER_2K (8 << WDT_CONFIG_PER_SHIFT) /* 2048 clock cycles */ +# define WDT_CONFIG_PER_4K (9 << WDT_CONFIG_PER_SHIFT) /* 4096 clock cycles */ # define WDT_CONFIG_PER_8k (10 << WDT_CONFIG_PER_SHIFT) /* 8192 clock cycles */ # define WDT_CONFIG_PER_16K (11 << WDT_CONFIG_PER_SHIFT) /* 16384 clock cycles */ + #define WDT_CONFIG_WINDOW_SHIFT (4) /* Bits 4-7: Window Mode Time-Out Period */ #define WDT_CONFIG_WINDOW_MASK (15 << WDT_CONFIG_WINDOW_SHIFT) -# define WDT_CONFIG_WINDOW_8 (0 << WDT_CONFIG_WINDOW_SHIFT) /* 8 clock cycles */ -# define WDT_CONFIG_WINDOW_16 (1 << WDT_CONFIG_WINDOW_SHIFT) /* 16 clock cycles */ -# define WDT_CONFIG_WINDOW_32 (2 << WDT_CONFIG_WINDOW_SHIFT) /* 32 clock cycles */ -# define WDT_CONFIG_WINDOW_64 (3 << WDT_CONFIG_WINDOW_SHIFT) /* 64 clock cycles */ -# define WDT_CONFIG_WINDOW_128 (4 << WDT_CONFIG_WINDOW_SHIFT) /* 128 clock cycles */ -# define WDT_CONFIG_WINDOW_256 (5 << WDT_CONFIG_WINDOW_SHIFT) /* 256 clocks cycles */ -# define WDT_CONFIG_WINDOW_512 (6 << WDT_CONFIG_WINDOW_SHIFT) /* 512 clocks cycles */ -# define WDT_CONFIG_WINDOW_1K (7 << WDT_CONFIG_WINDOW_SHIFT) /* 1024 clock cycles */ -# define WDT_CONFIG_WINDOW_2K (8 << WDT_CONFIG_WINDOW_SHIFT) /* 2048 clock cycles */ -# define WDT_CONFIG_WINDOW_4K (9 << WDT_CONFIG_WINDOW_SHIFT) /* 4096 clock cycles */ +# define WDT_CONFIG_WINDOW_8 (0 << WDT_CONFIG_WINDOW_SHIFT) /* 8 clock cycles */ +# define WDT_CONFIG_WINDOW_16 (1 << WDT_CONFIG_WINDOW_SHIFT) /* 16 clock cycles */ +# define WDT_CONFIG_WINDOW_32 (2 << WDT_CONFIG_WINDOW_SHIFT) /* 32 clock cycles */ +# define WDT_CONFIG_WINDOW_64 (3 << WDT_CONFIG_WINDOW_SHIFT) /* 64 clock cycles */ +# define WDT_CONFIG_WINDOW_128 (4 << WDT_CONFIG_WINDOW_SHIFT) /* 128 clock cycles */ +# define WDT_CONFIG_WINDOW_256 (5 << WDT_CONFIG_WINDOW_SHIFT) /* 256 clocks cycles */ +# define WDT_CONFIG_WINDOW_512 (6 << WDT_CONFIG_WINDOW_SHIFT) /* 512 clocks cycles */ +# define WDT_CONFIG_WINDOW_1K (7 << WDT_CONFIG_WINDOW_SHIFT) /* 1024 clock cycles */ +# define WDT_CONFIG_WINDOW_2K (8 << WDT_CONFIG_WINDOW_SHIFT) /* 2048 clock cycles */ +# define WDT_CONFIG_WINDOW_4K (9 << WDT_CONFIG_WINDOW_SHIFT) /* 4096 clock cycles */ # define WDT_CONFIG_WINDOW_8k (10 << WDT_CONFIG_WINDOW_SHIFT) /* 8192 clock cycles */ # define WDT_CONFIG_WINDOW_16K (11 << WDT_CONFIG_WINDOW_SHIFT) /* 16384 clock cycles */ @@ -104,20 +106,22 @@ #define WDT_EWCTRL_EWOFFSET_SHIFT (0) /* Bits 0-3: Early warning interrupt time offset */ #define WDT_EWCTRL_EWOFFSET_MASK (15 << WDT_EWCTRL_EWOFFSET_SHIFT) -# define WDT_EWCTRL_EWOFFSET_8 (0 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_16 (1 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_32 (2 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 32 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_64 (3 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 64 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_128 (4 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 128 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_256 (5 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 256 clocks cycles */ -# define WDT_EWCTRL_EWOFFSET_512 (6 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 512 clocks cycles */ -# define WDT_EWCTRL_EWOFFSET_1K (7 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 1024 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_2K (8 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 2048 clock cycles */ -# define WDT_EWCTRL_EWOFFSET_4K (9 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 4096 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_8 (0 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_16 (1 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_32 (2 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 32 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_64 (3 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 64 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_128 (4 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 128 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_256 (5 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 256 clocks cycles */ +# define WDT_EWCTRL_EWOFFSET_512 (6 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 512 clocks cycles */ +# define WDT_EWCTRL_EWOFFSET_1K (7 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 1024 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_2K (8 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 2048 clock cycles */ +# define WDT_EWCTRL_EWOFFSET_4K (9 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 4096 clock cycles */ # define WDT_EWCTRL_EWOFFSET_8k (10 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8192 clock cycles */ # define WDT_EWCTRL_EWOFFSET_16K (11 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16384 clock cycles */ -/* Interrupt enable clear, interrupt enable set register, interrupt flag status and clear registers */ +/* Interrupt enable clear, interrupt enable set register, interrupt + * flag status and clear registers + */ #define WDT_INT_EW (1 << 0) /* Bit 0: Early warning interrupt */ #define WDT_INT_All (0x01) @@ -135,17 +139,17 @@ #define WDT_CLEAR_CLEAR_MASK (0xff << WDT_CLEAR_CLEAR_SHIFT) # define WDT_CLEAR_CLEAR (0xa5 << WDT_CLEAR_CLEAR_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_WDT_H */ diff --git a/arch/arm/src/samd2l2/sam_ac.c b/arch/arm/src/samd2l2/sam_ac.c index 018e47cfa6f..0a60a25b94b 100644 --- a/arch/arm/src/samd2l2/sam_ac.c +++ b/arch/arm/src/samd2l2/sam_ac.c @@ -109,12 +109,16 @@ int sam_ac_initialize(uint8_t gclkgen) /* Enable comparator digital GCLK which provides the sampling rate */ - regval = GCLK_CLKCTRL_ID_ACDIG | GCLK_CLKCTRL_GEN(gclkgen) | GCLK_CLKCTRL_CLKEN; + regval = GCLK_CLKCTRL_ID_ACDIG | + GCLK_CLKCTRL_GEN(gclkgen) | + GCLK_CLKCTRL_CLKEN; putreg16(regval, SAM_GCLK_CLKCTRL); /* Enable comparator analog GCLK */ - regval = GCLK_CLKCTRL_ID_ACANA | GCLK_CLKCTRL_GEN(gclkgen) | GCLK_CLKCTRL_CLKEN; + regval = GCLK_CLKCTRL_ID_ACANA | + GCLK_CLKCTRL_GEN(gclkgen) | + GCLK_CLKCTRL_CLKEN; putreg16(regval, SAM_GCLK_CLKCTRL); putreg8(AC_CTRLA_ENABLE, SAM_AC_CTRLA); diff --git a/arch/arm/src/samd2l2/sam_ac.h b/arch/arm/src/samd2l2/sam_ac.h index 96793bb3581..3863a764854 100644 --- a/arch/arm/src/samd2l2/sam_ac.h +++ b/arch/arm/src/samd2l2/sam_ac.h @@ -73,7 +73,6 @@ extern "C" #define EXTERN extern #endif - #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/samd2l2/sam_adc.c b/arch/arm/src/samd2l2/sam_adc.c index 33fefcbf170..9654470c42a 100644 --- a/arch/arm/src/samd2l2/sam_adc.c +++ b/arch/arm/src/samd2l2/sam_adc.c @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/sam_adc.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -32,7 +32,7 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Included Files @@ -99,16 +99,16 @@ static int sam_adc_ioctl(FAR struct adc_dev_s *dev, int cmd, struct sam_adc_priv { - int genclk; /* clock generator */ + int genclk; /* clock generator */ const struct adc_callback_s *adc_callback; /* callback for upper driver */ - int cur_channel; /* current channel in progress */ - int num_channels; /* number of channels */ - int *channels; /* channels to process */ - uint8_t ref; /* reference selection */ - uint32_t neg; /* negative input selection */ - uint8_t samplen; /* sampling time length */ - uint32_t prescaler; /* prescaler configuration */ - uint8_t averaging; /* number of samples to be collected */ + int cur_channel; /* current channel in progress */ + int num_channels; /* number of channels */ + int *channels; /* channels to process */ + uint8_t ref; /* reference selection */ + uint32_t neg; /* negative input selection */ + uint8_t samplen; /* sampling time length */ + uint32_t prescaler; /* prescaler configuration */ + uint8_t averaging; /* number of samples to be collected */ }; /**************************************************************************** @@ -127,9 +127,9 @@ static const struct adc_ops_s sam_adc_ops = static struct adc_dev_s g_sam_adc_dev; -/******************************************************************************* +/**************************************************************************** * Private Functions - *******************************************************************************/ + ****************************************************************************/ static void sam_adc_synchronization(void) { @@ -147,7 +147,8 @@ static int sam_adc_interrupt(int irq, FAR void *context, FAR void *arg) ainfo("ADC Result = %d:\n", result); - priv->adc_callback->au_receive(dev, priv->channels[priv->cur_channel], result); + priv->adc_callback->au_receive(dev, priv->channels[priv->cur_channel], + result); putreg8(ADC_INT_RESRDY, SAM_ADC_INTFLAG); @@ -216,8 +217,8 @@ static int sam_adc_calibrate(struct adc_dev_s *dev) return 0; } -/* Bind the upper-half driver callbacks to the lower-half implementation. This - * must be called early in order to receive ADC event notifications. +/* Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. */ static int sam_adc_bind(FAR struct adc_dev_s *dev, @@ -394,7 +395,8 @@ static void sam_adc_rxint(FAR struct adc_dev_s *dev, bool enable) * ****************************************************************************/ -static int sam_adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) +static int sam_adc_ioctl(FAR struct adc_dev_s *dev, + int cmd, unsigned long arg) { int ret = 0; struct sam_adc_priv *priv = (struct sam_adc_priv *)dev->ad_priv; @@ -434,9 +436,9 @@ static int sam_adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -/******************************************************************************* +/**************************************************************************** * Public Functions - *******************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_adcinitialize diff --git a/arch/arm/src/samd2l2/sam_clockconfig.h b/arch/arm/src/samd2l2/sam_clockconfig.h index e644a60d1e6..c89492c65fc 100644 --- a/arch/arm/src/samd2l2/sam_clockconfig.h +++ b/arch/arm/src/samd2l2/sam_clockconfig.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/sam_clockconfig.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_CLOCKCONFIG_H #define __ARCH_ARM_SRC_SAMD2L2_SAM_CLOCKCONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -50,11 +50,11 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_clockconfig * * Description: @@ -66,7 +66,7 @@ extern "C" * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_clockconfig(void); diff --git a/arch/arm/src/samd2l2/sam_config.h b/arch/arm/src/samd2l2/sam_config.h index 9441f48bdd1..758d5bd1074 100644 --- a/arch/arm/src/samd2l2/sam_config.h +++ b/arch/arm/src/samd2l2/sam_config.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/sam_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_CONFIG_H #define __ARCH_ARM_SRC_SAMD2L2_SAM_CONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* How many SERCOM peripherals are configured as USART peripherals? */ #define SAMD2L2_HAVE_USART0 1 @@ -109,8 +110,9 @@ # define SAMD2L2_HAVE_USART 1 #endif -/* Is there a serial console? There should be at most one defined. It could be on - * any USARTn, n=0-5 - OR - there might not be any serial console at all. +/* Is there a serial console? There should be at most one defined. + * It could be on any USARTn, n=0-5 - OR - there might not be any + * serial console at all. */ #if defined(CONFIG_USART0_SERIAL_CONSOLE) @@ -310,16 +312,16 @@ # define SAMD2L2_HAVE_I2C 1 #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_SAM_CONFIG_H */ diff --git a/arch/arm/src/samd2l2/sam_dac.h b/arch/arm/src/samd2l2/sam_dac.h index be4c76e082c..4f433acf3af 100644 --- a/arch/arm/src/samd2l2/sam_dac.h +++ b/arch/arm/src/samd2l2/sam_dac.h @@ -69,7 +69,6 @@ extern "C" #define EXTERN extern #endif - #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/samd2l2/sam_dmac.h b/arch/arm/src/samd2l2/sam_dmac.h index d45c373b03e..be53bde320a 100644 --- a/arch/arm/src/samd2l2/sam_dmac.h +++ b/arch/arm/src/samd2l2/sam_dmac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/sam_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_DMAC_H #define __ARCH_ARM_SRC_SAMD2L2_SAM_DMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -43,22 +43,26 @@ # error Unrecognized SAMD/L architecture #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* DMA ******************************************************************************/ +/* DMA **********************************************************************/ -/* Flags used to characterize the desired DMA channel. The naming convention is that - * one side is the peripheral and the other is memory (however, the interface could still - * be used if, for example, both sides were memory although the naming would be awkward) +/* Flags used to characterize the desired DMA channel. The naming convention + * is that one side is the peripheral and the other is memory (however, the + * interface could still be used if, for example, both sides were memory + * although the naming would be awkward) */ /* Common characteristics * - * BEATSIZE - The size of one bus transfer or "beat". 8-, 16-, or 32-bits - * STEPSIZE - When the address is incremented, it is increments by how many "beats"? - * STEPSEL - The STEPSIZE may be applied only to the memory to the peripheral. + * BEATSIZE - The size of one bus transfer or "beat". 8-, 16-, + * or 32-bits + * STEPSIZE - When the address is incremented, it is increments + * by how many "beats"? + * STEPSEL - The STEPSIZE may be applied only to the memory to + * the peripheral. */ #define DMACH_FLAG_BEATSIZE_SHIFT (0) /* Bits 0-1: Beat size */ @@ -66,6 +70,7 @@ # define DMACH_FLAG_BEATSIZE_BYTE (0 << DMACH_FLAG_BEATSIZE_SHIFT) /* 8-bit bus transfer */ # define DMACH_FLAG_BEATSIZE_HWORD (1 << DMACH_FLAG_BEATSIZE_SHIFT) /* 16-bit bus transfer */ # define DMACH_FLAG_BEATSIZE_WORD (2 << DMACH_FLAG_BEATSIZE_SHIFT) /* 32-bit bus transfer */ + #define DMACH_FLAG_STEPSEL (1 << 2) /* Bit 2: Step selection */ # define DMACH_FLAG_STEPSEL_MEM (0) /* 0=Step size applies to memory */ # define DMACH_FLAG_STEPSEL_PERIPH (1 << 2) /* 1=Step size applies to peripheral */ @@ -79,6 +84,7 @@ # define DMACH_FLAG_STEPSIZE_X32 (5 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */ # define DMACH_FLAG_STEPSIZE_X64 (6 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */ # define DMACH_FLAG_STEPSIZE_X128 (7 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */ + #define DMACH_FLAG_PRIORITY_SHIFT (6) /* Bit 6-7: Arbitration priority */ #define DMACH_FLAG_PRIORITY_MASK (3 << DMACH_FLAG_PRIORITY_SHIFT) # define DMACH_FLAG_PRIORITY(n) ((uint32_t)(n) << DMACH_FLAG_PRIORITY_SHIFT) @@ -86,14 +92,18 @@ /* Peripheral endpoint characteristics. * - * PERIPH_TXTRIG - The TX ID of the peripheral that provides the DMA trigger. This - * is one of the DMA_TRIGSRC_*[_TX] definitions. This trigger source - * is selected when sam_dmatxsetup() is called. - * PERIPH_RXTRIG - The RX ID of the peripheral that provides the DMA trigger. This - * is one of the DMA_TRIGSRC_*[_RX] definitions. This trigger source - * is selected when sam_dmarxsetup() is called. - * PERIPH_INCREMENT - Indicates that the peripheral address should be incremented on - * each "beat" + * PERIPH_TXTRIG - The TX ID of the peripheral that provides the DMA + * trigger. + * This is one of the DMA_TRIGSRC_*[_TX] definitions. + * This trigger source is selected when sam_dmatxsetup() + * is called. + * PERIPH_RXTRIG - The RX ID of the peripheral that provides the DMA + * trigger. + * This is one of the DMA_TRIGSRC_*[_RX] definitions. + * This trigger source is selected when sam_dmarxsetup() + * is called. + * PERIPH_INCREMENT - Indicates that the peripheral address should be + * incremented on each "beat" * PERIPH_QOS - Quality of service for peripheral accesses */ @@ -113,8 +123,8 @@ /* Memory endpoint characteristics * - * MEM_INCREMENT - Indicates that the memory address should be incremented on each - * "beat" + * MEM_INCREMENT - Indicates that the memory address should be incremented on + * each "beat" * MEM_QOS - Quality of service for memory accesses */ @@ -125,16 +135,19 @@ # define DMACH_FLAG_MEM_QOS_LOW (1 << DMACH_FLAG_MEM_QOS_SHIFT) /* Sensitive bandwidth */ # define DMACH_FLAG_MEM_QOS_MEDIUM (2 << DMACH_FLAG_MEM_QOS_SHIFT) /* Sensitive latency */ # define DMACH_FLAG_MEM_QOS_HIGH (3 << DMACH_FLAG_MEM_QOS_SHIFT) /* Critical latency */ + /* Bits 27-31: Not used */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA + * is selected + */ #ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s @@ -167,15 +180,15 @@ struct sam_dmaregs_s }; #endif -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -186,119 +199,124 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_dmachannel * * Description: - * Allocate a DMA channel. This function sets aside a DMA channel and gives the - * caller exclusive access to the DMA channel. + * Allocate a DMA channel. + * This function sets aside a DMA channel and gives the caller exclusive + * access to the DMA channel. * - * The naming convention in all of the DMA interfaces is that one side is the - * 'peripheral' and the other is 'memory'. However, the interface could still be - * used if, for example, both sides were memory although the naming would be - * awkward. + * The naming convention in all of the DMA interfaces is that one side is + * the 'peripheral' and the other is 'memory'. However, the interface + * could still be used if, for example, both sides were memory although + * the naming would be awkward. * * Returned Value: - * If a DMA channel if the required FIFO size is available, this function returns - * a non-NULL, void* DMA channel handle. NULL is returned on any failure. + * If a DMA channel if the required FIFO size is available, this function + * returns a non-NULL, void* DMA channel handle. + * NULL is returned on any failure. * - ************************************************************************************/ + ****************************************************************************/ DMA_HANDLE sam_dmachannel(uint32_t chflags); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmaconfig * * Description: * There are two channel usage models: (1) The channel is allocated and - * configured in one step. This is the typical case where a DMA channel performs - * a constant role. The alternative is (2) where the DMA channel is reconfigured - * on the fly. In this case, the chflags provided to sam_dmachannel are not used - * and sam_dmaconfig() is called before each DMA to configure the DMA channel - * appropriately. + * configured in one step. This is the typical case where a DMA channel + * performs a constant role. The alternative is (2) where the DMA channel + * is reconfigured on the fly. In this case, the chflags provided to + * sam_dmachannel are not used and sam_dmaconfig() is called before each + * DMA to configure the DMA channel appropriately. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmafree * * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must NEVER be - * used again until sam_dmachannel() is called again to re-gain a valid handle. + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again until + * sam_dmachannel() is called again to re-gain a valid handle. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_dmafree(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmatxsetup * * Description: - * Configure DMA for transmit of one buffer (memory to peripheral). This function - * may be called multiple times to handle large and/or non-contiguous transfers. - * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the - * same transfer, however. + * Configure DMA for transmit of one buffer (memory to peripheral). + * This function may be called multiple times to handle large and/or + * non-contiguous transfers. + * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed + * on the same transfer, however. * - ************************************************************************************/ + ****************************************************************************/ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmarxsetup * * Description: - * Configure DMA for receipt of one buffer (peripheral to memory). This function - * may be called multiple times to handle large and/or non-contiguous transfers. - * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the - * same transfer, however. + * Configure DMA for receipt of one buffer (peripheral to memory). + * This function may be called multiple times to handle large and/or + * non-contiguous transfers. + * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed + * on the same transfer, however. * - ************************************************************************************/ + ****************************************************************************/ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmastart * * Description: * Start the DMA transfer * - ************************************************************************************/ + ****************************************************************************/ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmastop * * Description: * Cancel the DMA. After sam_dmastop() is called, the DMA channel is - * reset and sam_dmarx/txsetup() must be called before sam_dmastart() can be - * called again + * reset and sam_dmarx/txsetup() must be called before sam_dmastart() + * can be called again * - ************************************************************************************/ + ****************************************************************************/ void sam_dmastop(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmasample * * Description: * Sample DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); @@ -306,13 +324,13 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); # define sam_dmasample(handle,regs) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_dmadump * * Description: * Dump previously sampled DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, diff --git a/arch/arm/src/samd2l2/sam_i2c_master.c b/arch/arm/src/samd2l2/sam_i2c_master.c index 588b355336b..114200e7617 100644 --- a/arch/arm/src/samd2l2/sam_i2c_master.c +++ b/arch/arm/src/samd2l2/sam_i2c_master.c @@ -1,4 +1,4 @@ -/******************************************************************************* +/**************************************************************************** * arch/arm/src/samd2l2/sam_i2c_master.c * * Copyright (C) 2013-2014, 2017 Gregory Nutt. All rights reserved. @@ -43,11 +43,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************/ + ****************************************************************************/ #include @@ -80,11 +80,11 @@ defined(SAMD2L2_HAVE_I2C2) || defined(SAMD2L2_HAVE_I2C3) || \ defined(SAMD2L2_HAVE_I2C4) || defined(SAMD2L2_HAVE_I2C5) -/******************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************/ + ****************************************************************************/ -/* Configuration ***************************************************************/ +/* Configuration ************************************************************/ #ifndef CONFIG_SAM_I2C0_FREQUENCY # define CONFIG_SAM_I2C0_FREQUENCY 100000 @@ -110,13 +110,14 @@ # define CONFIG_SAM_I2C5_FREQUENCY 100000 #endif -/* Driver internal definitions *************************************************/ +/* Driver internal definitions **********************************************/ -/* If verbose I2C debug output is enable, then allow more time before we declare - * a timeout. The debug output from i2c_interrupt will really slow things down! +/* If verbose I2C debug output is enable, then allow more time before we + * declare a timeout. The debug output from i2c_interrupt will really slow + * things down! * - * With a very slow clock (say 100,000 Hz), less than 100 usec would be required - * to transfer on byte. So these define a "long" timeout. + * With a very slow clock (say 100,000 Hz), less than 100 usec would be + * required to transfer on byte. So these define a "long" timeout. */ #ifdef CONFIG_DEBUG_I2C_INFO @@ -131,9 +132,9 @@ #define I2C_MAX_FREQUENCY 66000000 /* Maximum I2C frequency */ -/******************************************************************************* +/**************************************************************************** * Private Types - *******************************************************************************/ + ****************************************************************************/ /* Invariant attributes of a I2C bus */ @@ -185,19 +186,22 @@ struct sam_i2c_dev_s #endif }; -/******************************************************************************* +/**************************************************************************** * Private Function Prototypes - *******************************************************************************/ + ****************************************************************************/ /* Low-level helper functions */ -static uint8_t i2c_getreg8(struct sam_i2c_dev_s *priv, unsigned int offset); +static uint8_t i2c_getreg8(struct sam_i2c_dev_s *priv, + unsigned int offset); static void i2c_putreg8(struct sam_i2c_dev_s *priv, uint8_t regval, unsigned int offset); -static uint16_t i2c_getreg16(struct sam_i2c_dev_s *priv, unsigned int offset); +static uint16_t i2c_getreg16(struct sam_i2c_dev_s *priv, + unsigned int offset); static void i2c_putreg16(struct sam_i2c_dev_s *priv, uint16_t regval, unsigned int offset); -static uint32_t i2c_getreg32(struct sam_i2c_dev_s *priv, unsigned int offset); +static uint32_t i2c_getreg32(struct sam_i2c_dev_s *priv, + unsigned int offset); static void i2c_putreg32(struct sam_i2c_dev_s *priv, uint32_t regval, unsigned int offset); @@ -219,19 +223,24 @@ static void i2c_putabs(struct sam_i2c_dev_s *priv, uintptr_t address, static inline uint32_t i2c_getrel(struct sam_i2c_dev_s *priv, unsigned int offset); -static inline void i2c_putrel(struct sam_i2c_dev_s *priv, unsigned int offset, +static inline void i2c_putrel(struct sam_i2c_dev_s *priv, + unsigned int offset, uint32_t value); /* I2C transfer helper functions */ -static int i2c_wait_for_bus(struct sam_i2c_dev_s *priv, unsigned int size); +static int i2c_wait_for_bus(struct sam_i2c_dev_s *priv, + unsigned int size); static void i2c_wakeup(struct sam_i2c_dev_s *priv, int result); static int i2c_interrupt(int irq, FAR void *context, void *arg); -static void i2c_startread(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg); -static void i2c_startwrite(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg); -static void i2c_startmessage(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg); +static void i2c_startread(struct sam_i2c_dev_s *priv, + struct i2c_msg_s *msg); +static void i2c_startwrite(struct sam_i2c_dev_s *priv, + struct i2c_msg_s *msg); +static void i2c_startmessage(struct sam_i2c_dev_s *priv, + struct i2c_msg_s *msg); static int sam_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count); @@ -240,13 +249,14 @@ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, static uint32_t sam_i2c_setfrequency(struct sam_i2c_dev_s *priv, uint32_t frequency); -static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency); +static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, + uint32_t frequency); static void i2c_wait_synchronization(struct sam_i2c_dev_s *priv); static void i2c_pad_configure(struct sam_i2c_dev_s *priv); -/******************************************************************************* +/**************************************************************************** * Private Data - *******************************************************************************/ + ****************************************************************************/ #ifdef SAMD2L2_HAVE_I2C0 static const struct i2c_attr_s g_i2c0attr = @@ -363,30 +373,30 @@ struct i2c_ops_s g_i2cops = #endif }; -/******************************************************************************* +/**************************************************************************** * Private Functions - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: i2c_getreg8 * * Description: * Get a 8-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static uint8_t i2c_getreg8(struct sam_i2c_dev_s *priv, unsigned int offset) { return getreg8(priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_putreg8 * * Description: * Put a 8-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static void i2c_putreg8(struct sam_i2c_dev_s *priv, uint8_t regval, unsigned int offset) @@ -394,26 +404,26 @@ static void i2c_putreg8(struct sam_i2c_dev_s *priv, uint8_t regval, putreg8(regval, priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_getreg16 * * Description: * Get a 16-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static uint16_t i2c_getreg16(struct sam_i2c_dev_s *priv, unsigned int offset) { return getreg16(priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_putreg16 * * Description: * Put a 16-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static void i2c_putreg16(struct sam_i2c_dev_s *priv, uint16_t regval, unsigned int offset) @@ -421,26 +431,26 @@ static void i2c_putreg16(struct sam_i2c_dev_s *priv, uint16_t regval, putreg16(regval, priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_getreg32 * * Description: * Get a 32-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static uint32_t i2c_getreg32(struct sam_i2c_dev_s *priv, unsigned int offset) { return getreg32(priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_putreg32 * * Description: * Put a 32-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static void i2c_putreg32(struct sam_i2c_dev_s *priv, uint32_t regval, unsigned int offset) @@ -448,7 +458,7 @@ static void i2c_putreg32(struct sam_i2c_dev_s *priv, uint32_t regval, putreg32(regval, priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_takesem * * Description: @@ -460,19 +470,19 @@ static void i2c_putreg32(struct sam_i2c_dev_s *priv, uint32_t regval, * Returned Value: * None * - *******************************************************************************/ + ****************************************************************************/ static int i2c_takesem(sem_t *sem) { return nxsem_wait(sem); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_takesem_noncancelable * * Description: - * Take the wait semaphore (handling false alarm wake-ups due to the receipt - * of signals). May be interrupted by a signal. + * Take the wait semaphore (handling false alarm wake-ups due to the + * receipt of signals). May be interrupted by a signal. * * Input Parameters: * dev - Instance of the SDIO device driver state structure. @@ -480,14 +490,14 @@ static int i2c_takesem(sem_t *sem) * Returned Value: * None * - *******************************************************************************/ + ****************************************************************************/ static int i2c_takesem_noncancelable(sem_t *sem) { return nxsem_wait_uninterruptible(sem); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_checkreg * * Description: @@ -501,7 +511,7 @@ static int i2c_takesem_noncancelable(sem_t *sem) * true: This is the first register access of this type. * false: This is the same as the preceding register access. * - *******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM_I2C_REGDEBUG static bool i2c_checkreg(struct sam_i2c_dev_s *priv, bool wr, uint32_t value, @@ -541,13 +551,13 @@ static bool i2c_checkreg(struct sam_i2c_dev_s *priv, bool wr, uint32_t value, } #endif -/******************************************************************************* +/**************************************************************************** * Name: i2c_getabs * * Description: * Read any 32-bit register using an absolute * - *******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM_I2C_REGDEBUG static uint32_t i2c_getabs(struct sam_i2c_dev_s *priv, uintptr_t address) @@ -563,13 +573,13 @@ static uint32_t i2c_getabs(struct sam_i2c_dev_s *priv, uintptr_t address) } #endif -/******************************************************************************* +/**************************************************************************** * Name: i2c_putabs * * Description: * Write to any 32-bit register using an absolute address * - *******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAM_I2C_REGDEBUG static void i2c_putabs(struct sam_i2c_dev_s *priv, uintptr_t address, @@ -584,13 +594,13 @@ static void i2c_putabs(struct sam_i2c_dev_s *priv, uintptr_t address, } #endif -/******************************************************************************* +/**************************************************************************** * Name: i2c_getrel * * Description: * Read a I2C register using an offset relative to the I2C base address * - *******************************************************************************/ + ****************************************************************************/ static inline uint32_t i2c_getrel(struct sam_i2c_dev_s *priv, unsigned int offset) @@ -598,26 +608,27 @@ static inline uint32_t i2c_getrel(struct sam_i2c_dev_s *priv, return i2c_getabs(priv, priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_putrel * * Description: * Write a value to a I2C register using an offset relative to the I2C base * address. * - *******************************************************************************/ + ****************************************************************************/ -static inline void i2c_putrel(struct sam_i2c_dev_s *priv, unsigned int offset, +static inline void i2c_putrel(struct sam_i2c_dev_s *priv, + unsigned int offset, uint32_t value) { i2c_putabs(priv, priv->attr->base + offset, value); } -/******************************************************************************* +/**************************************************************************** * I2C transfer helper functions - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: i2c_wait_for_bus * * Description: @@ -627,7 +638,7 @@ static inline void i2c_putrel(struct sam_i2c_dev_s *priv, unsigned int offset, * Assumptions: * Interrupts are disabled * - *******************************************************************************/ + ****************************************************************************/ static int i2c_wait_for_bus(struct sam_i2c_dev_s *priv, unsigned int size) { @@ -656,13 +667,13 @@ static int i2c_wait_for_bus(struct sam_i2c_dev_s *priv, unsigned int size) return priv->result; } -/******************************************************************************* +/**************************************************************************** * Name: i2c_wakeup * * Description: * A terminal event has occurred. Wake-up the waiting thread * - *******************************************************************************/ + ****************************************************************************/ static void i2c_wakeup(struct sam_i2c_dev_s *priv, int result) { @@ -676,13 +687,13 @@ static void i2c_wakeup(struct sam_i2c_dev_s *priv, int result) nxsem_post(&priv->waitsem); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_interrupt * * Description: * The I2C Interrupt Handler * - *******************************************************************************/ + ****************************************************************************/ static int i2c_interrupt(int irq, FAR void *context, FAR void *arg) { @@ -808,13 +819,13 @@ static int i2c_interrupt(int irq, FAR void *context, FAR void *arg) return OK; } -/******************************************************************************* +/**************************************************************************** * Name: i2c_startread * * Description: * Start the next read message * - *******************************************************************************/ + ****************************************************************************/ static void i2c_startread(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) { @@ -857,13 +868,13 @@ static void i2c_startread(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) i2c_wait_synchronization(priv); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_startwrite * * Description: * Start the next write message * - *******************************************************************************/ + ****************************************************************************/ static void i2c_startwrite(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) { @@ -918,15 +929,16 @@ static void i2c_startwrite(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) i2c_wait_synchronization(priv); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_startmessage * * Description: * Start the next write message * - *******************************************************************************/ + ****************************************************************************/ -static void i2c_startmessage(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) +static void i2c_startmessage(struct sam_i2c_dev_s *priv, + struct i2c_msg_s *msg) { if ((msg->flags & I2C_M_READ) != 0) { @@ -938,11 +950,11 @@ static void i2c_startmessage(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) } } -/******************************************************************************* +/**************************************************************************** * I2C device operations - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_transfer * * Description: @@ -952,7 +964,7 @@ static void i2c_startmessage(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) * Returned Value: * Returns zero on success; a negated errno value on failure. * - *******************************************************************************/ + ****************************************************************************/ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count) @@ -1012,8 +1024,8 @@ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, flags = enter_critical_section(); i2c_startmessage(priv, msgs); - /* And wait for the transfers to complete. Interrupts will be re-enabled - * while we are waiting. + /* And wait for the transfers to complete. + * Interrupts will be re-enabled while we are waiting. */ ret = i2c_wait_for_bus(priv, msgs->length); @@ -1028,7 +1040,8 @@ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, #endif /* Disable any further I2C interrupts */ - i2c_putreg8(priv, I2C_INT_MB | I2C_INT_SB, SAM_I2C_INTENCLR_OFFSET); + i2c_putreg8(priv, I2C_INT_MB | I2C_INT_SB, + SAM_I2C_INTENCLR_OFFSET); leave_critical_section(flags); i2c_givesem(&priv->exclsem); @@ -1046,17 +1059,17 @@ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, return ret; } -/******************************************************************************* +/**************************************************************************** * Initialization - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_setfrequency * * Description: * Set the frequency for the next transfer * - *******************************************************************************/ + ****************************************************************************/ static uint32_t sam_i2c_setfrequency(struct sam_i2c_dev_s *priv, uint32_t frequency) @@ -1077,7 +1090,9 @@ static uint32_t sam_i2c_setfrequency(struct sam_i2c_dev_s *priv, frequency = maxfreq; } - /* Check if the requested frequency is the same as the frequency selection */ + /* Check if the requested frequency is the same as the frequency + * selection + */ if (priv->frequency == frequency) { @@ -1147,15 +1162,15 @@ static uint32_t sam_i2c_setfrequency(struct sam_i2c_dev_s *priv, return priv->frequency; } -/******************************************************************************* +/**************************************************************************** * Name: i2c_hw_initialize * * Description: * Initialize/Re-initialize the I2C peripheral. This logic performs only - * repeatable initialization after either (1) the one-time initialization, or - * (2) after each bus reset. + * repeatable initialization after either (1) the one-time initialization, + * or (2) after each bus reset. * - *******************************************************************************/ + ****************************************************************************/ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency) { @@ -1181,7 +1196,7 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency) if (regval & I2C_CTRLA_ENABLE) { i2cerr - ("ERROR: Cannot initialize I2C because it is already initialized!\n"); + ("ERROR: Cannot initialize I2C because it is already initialized!\n"); return; } @@ -1233,26 +1248,26 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency) leave_critical_section(flags); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_wait_synchronization * * Description: * Wait until the SERCOM I2C reports that it is synchronized. * - *******************************************************************************/ + ****************************************************************************/ static void i2c_wait_synchronization(struct sam_i2c_dev_s *priv) { while ((i2c_getreg16(priv, SAM_I2C_SYNCBUSY_OFFSET) & 0x7) != 0); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_pad_configure * * Description: * Configure the SERCOM I2C pads. * - *******************************************************************************/ + ****************************************************************************/ static void i2c_pad_configure(struct sam_i2c_dev_s *priv) { @@ -1269,17 +1284,17 @@ static void i2c_pad_configure(struct sam_i2c_dev_s *priv) } } -/******************************************************************************* +/**************************************************************************** * Public Functions - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_master_initialize * * Description: * Initialize a I2C device for I2C operation * - *******************************************************************************/ + ****************************************************************************/ struct i2c_master_s *sam_i2c_master_initialize(int bus) { @@ -1406,13 +1421,13 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) return &priv->dev; } -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_uninitialize * * Description: * Uninitialize an I2C device * - *******************************************************************************/ + ****************************************************************************/ int sam_i2c_uninitialize(FAR struct i2c_master_s *dev) { @@ -1435,13 +1450,13 @@ int sam_i2c_uninitialize(FAR struct i2c_master_s *dev) return OK; } -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_reset * * Description: * Reset an I2C bus * - *******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_I2C_RESET int sam_i2c_reset(FAR struct i2c_master_s *dev) diff --git a/arch/arm/src/samd2l2/sam_i2c_master.h b/arch/arm/src/samd2l2/sam_i2c_master.h index d72443363b7..c8fa93c6088 100644 --- a/arch/arm/src/samd2l2/sam_i2c_master.h +++ b/arch/arm/src/samd2l2/sam_i2c_master.h @@ -66,13 +66,13 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_master_initialize * * Description: * Initialize a I2C device for I2C operation * - *******************************************************************************/ + ****************************************************************************/ struct i2c_master_s; /* Forward reference */ struct i2c_master_s *sam_i2c_master_initialize(int bus); diff --git a/arch/arm/src/samd2l2/sam_lowputc.c b/arch/arm/src/samd2l2/sam_lowputc.c index a8e2295ff99..68c4932cdd3 100644 --- a/arch/arm/src/samd2l2/sam_lowputc.c +++ b/arch/arm/src/samd2l2/sam_lowputc.c @@ -196,6 +196,7 @@ sam_usart_configure(const struct sam_usart_config_s *const config) case 1: /* Odd */ ctrlb |= USART_CTRLB_PODD; + /* Fall through */ case 2: /* Even */ diff --git a/arch/arm/src/samd2l2/sam_pinmap.h b/arch/arm/src/samd2l2/sam_pinmap.h index 8118f7a2036..6a5ea652cf9 100644 --- a/arch/arm/src/samd2l2/sam_pinmap.h +++ b/arch/arm/src/samd2l2/sam_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/sam_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_PINMAP_H #define __ARCH_ARM_SRC_SAMD2L2_SAM_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/samd2l2/sam_port.c b/arch/arm/src/samd2l2/sam_port.c index 9dee95db01c..a443075bdd3 100644 --- a/arch/arm/src/samd2l2/sam_port.c +++ b/arch/arm/src/samd2l2/sam_port.c @@ -50,12 +50,16 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO -static const char g_portchar[2] = { 'A', 'B' }; +static const char g_portchar[2] = +{ + 'A', 'B' +}; #endif /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /**************************************************************************** * Name: sam_portbase * @@ -109,6 +113,7 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset) bit = (1 << pin); /* Direction bit is already zero (input) */ + /* Enable the I/O synchronizer? */ if ((pinset & PORT_SYNCHRONIZER_MASK) == PORT_SYNCHRONIZER_ON) @@ -120,7 +125,8 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset) /* Set the pin configuration */ - regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_INEN); + regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | + PORT_WRCONFIG_INEN); if (pin >= 16) { /* Select the upper half word and adjust the bit setting */ @@ -143,6 +149,7 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset) putreg32(bit, base + SAM_PORT_OUTSET_OFFSET); } + /* Fall through */ case PORT_PULL_DOWN: @@ -192,7 +199,9 @@ static inline void sam_configinterrupt(uintptr_t base, port_pinset_t pinset) putreg32(regval, base + SAM_PORT_WRCONFIG_OFFSET); - /* Configure the interrupt edge sensitivity in CONFIGn register of the EIC */ + /* Configure the interrupt edge sensitivity in CONFIGn register of + * the EIC + */ sam_eic_config(pin, pinset); @@ -240,7 +249,8 @@ static inline void sam_configoutput(uintptr_t base, port_pinset_t pinset) * buffer enabled. */ - regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_INEN); + regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | + PORT_WRCONFIG_INEN); if (pin > 16) { /* Select the upper half word and adjust the bit setting */ @@ -263,6 +273,7 @@ static inline void sam_configoutput(uintptr_t base, port_pinset_t pinset) putreg32(bit, base + SAM_PORT_OUTSET_OFFSET); } + /* Fall through */ case PORT_PULL_DOWN: @@ -324,7 +335,8 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset) * selected function. */ - regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_PMUXEN); + regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | + PORT_WRCONFIG_PMUXEN); /* If pin is output with readback then enable the input buffer */ @@ -360,6 +372,7 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset) putreg32(bit, base + SAM_PORT_OUTSET_OFFSET); } + /* Fall through */ case PORT_PULL_DOWN: @@ -523,13 +536,14 @@ bool sam_portread(port_pinset_t pinset) return (getreg32(base + SAM_PORT_IN_OFFSET) & pin) != 0; } -/************************************************************************************ +/**************************************************************************** * Function: sam_dumpport * * Description: - * Dump all PORT registers associated with the base address of the provided pinset. + * Dump all PORT registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpport(uint32_t pinset, const char *msg) diff --git a/arch/arm/src/samd2l2/sam_port.h b/arch/arm/src/samd2l2/sam_port.h index 86ee1cedfc2..c955135b807 100644 --- a/arch/arm/src/samd2l2/sam_port.h +++ b/arch/arm/src/samd2l2/sam_port.h @@ -50,9 +50,9 @@ /* Bit-encoded input to sam_configport() */ -/* 24-bit Encoding. This could be compacted into 16-bits by making the bit usage - * mode specific. However, by giving each bit field a unique position, we handle - * bad combinations of properties safely. +/* 24-bit Encoding. This could be compacted into 16-bits by making the bit + * usage mode specific. However, by giving each bit field a unique position, + * we handle bad combinations of properties safely. * * MODE BITFIELDS * ------------ ----------------------------- @@ -198,7 +198,8 @@ # define PORT_SYNCHRONIZER_OFF (0 << PORT_SYNCHRONIZER_SHIFT) # define PORT_SYNCHRONIZER_ON (1 << PORT_SYNCHRONIZER_SHIFT) -/* If the pin is an PORT output, then this identifies the initial output value: +/* If the pin is an PORT output, then this identifies the initial output + * value: * * MODE BITFIELDS * ------------ ----------------------------- diff --git a/arch/arm/src/samd2l2/sam_sercom.c b/arch/arm/src/samd2l2/sam_sercom.c index fe28848bc92..93f97ba20ac 100644 --- a/arch/arm/src/samd2l2/sam_sercom.c +++ b/arch/arm/src/samd2l2/sam_sercom.c @@ -275,8 +275,8 @@ void sercom_slowclk_configure(int sercom, int gclkgen) * generic clock generator pointed by CLKCTRL.GEN and the GENDIV.DIV * will also be locked. * - * We lock the SERCOM slow clock because it is common to all SERCOM modules - * and, once set, should not be changed again. + * We lock the SERCOM slow clock because it is common to all SERCOM + * modules and, once set, should not be changed again. */ regval |= (/* GCLK_CLKCTRL_WRTLOCK | */ GCLK_CLKCTRL_CLKEN); diff --git a/arch/arm/src/samd2l2/sam_sercom.h b/arch/arm/src/samd2l2/sam_sercom.h index 9370195885f..eb7a84290e9 100644 --- a/arch/arm/src/samd2l2/sam_sercom.h +++ b/arch/arm/src/samd2l2/sam_sercom.h @@ -98,6 +98,7 @@ static inline void sercom_enable(int sercom) /**************************************************************************** * Public Function Prototypes ****************************************************************************/ + /**************************************************************************** * Name: sercom_coreclk_configure * diff --git a/arch/arm/src/samd2l2/sam_serial.h b/arch/arm/src/samd2l2/sam_serial.h index fbc927af245..36dc5d9bb5e 100644 --- a/arch/arm/src/samd2l2/sam_serial.h +++ b/arch/arm/src/samd2l2/sam_serial.h @@ -46,7 +46,7 @@ ****************************************************************************/ /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD2L2_SAM_SERIAL_H */ diff --git a/arch/arm/src/samd2l2/sam_spi.h b/arch/arm/src/samd2l2/sam_spi.h index a21fa3d8037..3af3898e633 100644 --- a/arch/arm/src/samd2l2/sam_spi.h +++ b/arch/arm/src/samd2l2/sam_spi.h @@ -111,15 +111,16 @@ struct spi_dev_s *sam_spibus_initialize(int port); * pins. * 2. Provide sam_spi[n]select() and sam_spi[n]status() functions in your * board-specific logic. These functions will perform chip selection - * and status operations using GPIOs in the way your board is configured. + * and status operations using GPIOs in the way your board is + * configured. * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide * sam_spi[n]cmddata() functions in your board-specific logic. This * function will perform cmd/data selection operations using GPIOs in * the way your board is configured. * 3. Add a call to sam_spibus_initialize() in your low level application * initialization logic - * 4. The handle returned by sam_spibus_initialize() may then be used to bind - * the SPI driver to higher level logic (e.g., calling + * 4. The handle returned by sam_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * diff --git a/arch/arm/src/samd2l2/sam_start.h b/arch/arm/src/samd2l2/sam_start.h index ab0a48a0173..e3ea3293469 100644 --- a/arch/arm/src/samd2l2/sam_start.h +++ b/arch/arm/src/samd2l2/sam_start.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/sam_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_START_H #define __ARCH_ARM_SRC_SAMD2L2_SAM_START_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_boardinitialize * * Description: - * All SAMD/L architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * All SAMD/L architectures must provide the following entry point. + * This entry point is called early in the initialization -- after + * clocking and memory have been configured but before caches have been + * enabled and before any devices have been initialized. * - ************************************************************************************/ + ****************************************************************************/ void sam_boardinitialize(void); diff --git a/arch/arm/src/samd2l2/sam_usart.h b/arch/arm/src/samd2l2/sam_usart.h index 474a9a136e7..585876e1c6f 100644 --- a/arch/arm/src/samd2l2/sam_usart.h +++ b/arch/arm/src/samd2l2/sam_usart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/sam_usart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_USART_H #define __ARCH_ARM_SRC_SAMD2L2_SAM_USART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -43,9 +43,10 @@ #include "sam_config.h" #include "sam_port.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Pick the console USART configuration */ #if defined(CONFIG_USART0_SERIAL_CONSOLE) @@ -78,9 +79,10 @@ # define USART_TX_INTS (USART_INT_DRE) #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* This structure describes the static configuration of a USART */ struct sam_usart_config_s @@ -102,25 +104,30 @@ struct sam_usart_config_s uintptr_t base; /* SERCOM base address */ }; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ -/************************************************************************************ + ****************************************************************************/ + +/**************************************************************************** * Name: sam_wait_synchronization * * Description: - * Return true is the SERCOM USART reports that it is synchronizing. This inline - * function hides register differences between the SAMD20 and SAML21. + * Return true is the SERCOM USART reports that it is synchronizing. + * This inline function hides register differences between the SAMD20 + * and SAML21. * - ***********************************************************************************/ + ****************************************************************************/ #ifdef SAMD2L2_HAVE_USART -static inline bool usart_syncbusy(const struct sam_usart_config_s * const config) +static inline +bool usart_syncbusy(const struct sam_usart_config_s * const config) { #if defined(CONFIG_ARCH_FAMILY_SAMD20) - return ((getreg16(config->base + SAM_USART_STATUS_OFFSET) & USART_STATUS_SYNCBUSY) != 0); + return ((getreg16(config->base + SAM_USART_STATUS_OFFSET) & + USART_STATUS_SYNCBUSY) != 0); #elif defined(CONFIG_ARCH_FAMILY_SAMD21) || defined(CONFIG_ARCH_FAMILY_SAML21) - return ((getreg16(config->base + SAM_USART_SYNCBUSY_OFFSET) & USART_SYNCBUSY_ALL) != 0); + return ((getreg16(config->base + SAM_USART_SYNCBUSY_OFFSET) & + USART_SYNCBUSY_ALL) != 0); #else # error Unrecognized SAMD/L family return false; @@ -128,9 +135,9 @@ static inline bool usart_syncbusy(const struct sam_usart_config_s * const config } #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -169,9 +176,9 @@ EXTERN const struct sam_usart_config_s g_usart5config; EXTERN const struct sam_usart_config_s *g_usartconfig[SAMD2L2_NSERCOM]; -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samd2l2/sam_usb.h b/arch/arm/src/samd2l2/sam_usb.h index 9fdc48809f9..9b45144170b 100644 --- a/arch/arm/src/samd2l2/sam_usb.h +++ b/arch/arm/src/samd2l2/sam_usb.h @@ -1,4 +1,4 @@ -/****************************************************************************** +/**************************************************************************** * arch/arm/src/samd2l2/sam_usb.h * * Copyright (C) 2015 Filament - www.filament.com @@ -36,12 +36,12 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_USB_H #define __ARCH_ARM_SRC_SAMD2L2_SAM_USB_H -/***************************************************************************** +/**************************************************************************** * Included Files ****************************************************************************/ @@ -52,7 +52,7 @@ #include "chip.h" #include "hardware/saml_usb.h" -/***************************************************************************** +/**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -67,7 +67,7 @@ extern "C" #define EXTERN extern #endif -/***************************************************************************** +/**************************************************************************** * Name: sam_usb_suspend * * Description: @@ -76,17 +76,18 @@ extern "C" * suspend mode. * * When 'resume' is false, this function call provides an opportunity to - * perform board-specific power-saving actions so that less power is consumed - * while the USB is suspended. + * perform board-specific power-saving actions so that less power is + * consumed while the USB is suspended. * * XXX: * Certain power-saving operations are performed by the UDP driver when it - * enters suspend mode: The USB device peripheral clocks are be switched off. - * MCK and UDPCK are switched off and the USB transceiver is disabled. + * enters suspend mode: The USB device peripheral clocks are be switched + * off. MCK and UDPCK are switched off and the USB transceiver is disabled. * - * When 'resume' is true, normal clocking and operations must all be restored. + * When 'resume' is true, normal clocking and operations must all be + * restored. * - *****************************************************************************/ + ****************************************************************************/ void sam_usb_suspend(FAR struct usbdev_s *dev, bool resume); diff --git a/arch/arm/src/samd2l2/sam_userspace.h b/arch/arm/src/samd2l2/sam_userspace.h index cb64029578f..a93d74a3330 100644 --- a/arch/arm/src/samd2l2/sam_userspace.h +++ b/arch/arm/src/samd2l2/sam_userspace.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd2l2/sam_userspace.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,32 +16,32 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_USERSPACE_H #define __ARCH_ARM_SRC_SAMD2L2_SAM_USERSPACE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ /**************************************************************************** * Name: sam_userspace diff --git a/arch/arm/src/samd2l2/samd_clockconfig.c b/arch/arm/src/samd2l2/samd_clockconfig.c index 1f9c9cadbf0..678e8bfb1eb 100644 --- a/arch/arm/src/samd2l2/samd_clockconfig.c +++ b/arch/arm/src/samd2l2/samd_clockconfig.c @@ -67,6 +67,7 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* This structure describes the configuration of every enabled GCLK */ #ifdef BOARD_GCLK_ENABLE @@ -83,7 +84,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK0_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK0_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK0_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } /* GCLK generator 1 */ @@ -99,7 +101,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK1_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK1_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK1_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -116,7 +119,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK2_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK2_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK2_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -133,7 +137,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK3_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK3_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK3_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -150,7 +155,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK4_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK4_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK4_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -167,7 +173,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK5_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK5_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK5_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -184,7 +191,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK6_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK6_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK6_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -201,7 +209,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK7_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK7_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK7_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -218,7 +227,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK8_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK8_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK8_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif }; @@ -438,7 +448,8 @@ static inline void sam_osc32k_config(void) /* Recover OSC32K calibration data from OTP "fuse" memory */ regval = getreg32(SYSCTRL_FUSES_OSC32KCAL_ADDR); - calib = (regval & SYSCTRL_FUSES_OSC32KCAL_MASK) >> SYSCTRL_FUSES_OSC32KCAL_SHIFT; + calib = (regval & SYSCTRL_FUSES_OSC32KCAL_MASK) >> + SYSCTRL_FUSES_OSC32KCAL_SHIFT; /* Configure OSC32K */ @@ -595,7 +606,8 @@ static inline void sam_dpll_config(void) if (BOARD_DPLL_REFCLK == SYSCTRL_DPLLCTRLB_REFCLK_GCLKDPLL) { - putreg16(GCLK_CLKCTRL_ID_DPLL | GCLK_CLKCTRL_GEN(2) | GCLK_CLKCTRL_CLKEN, SAM_GCLK_CLKCTRL); + putreg16(GCLK_CLKCTRL_ID_DPLL | GCLK_CLKCTRL_GEN(2) | + GCLK_CLKCTRL_CLKEN, SAM_GCLK_CLKCTRL); } putreg32(ratio, SAM_SYSCTRL_DPLLRATIO); @@ -896,7 +908,9 @@ static inline void sam_dividers(void) uint8_t regval; #endif - /* Set the CPU divider using the divider value from the board.h header file */ + /* Set the CPU divider using the divider value from the board.h header + * file + */ putreg8(BOARD_CPU_DIVIDER, SAM_PM_CPUSEL); diff --git a/arch/arm/src/samd2l2/saml_clockconfig.c b/arch/arm/src/samd2l2/saml_clockconfig.c index a4e8d03b3e5..dbcb17d902a 100644 --- a/arch/arm/src/samd2l2/saml_clockconfig.c +++ b/arch/arm/src/samd2l2/saml_clockconfig.c @@ -144,7 +144,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true, #endif .prescaler = BOARD_GCLK0_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK0_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK0_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } /* GCLK generator 1 */ @@ -160,7 +161,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true; #endif .prescaler = BOARD_GCLK1_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK1_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK1_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -177,7 +179,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true; #endif .prescaler = BOARD_GCLK2_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK2_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK2_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -194,7 +197,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true; #endif .prescaler = BOARD_GCLK3_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK3_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK3_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -211,7 +215,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true; #endif .prescaler = BOARD_GCLK4_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK4_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK4_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -228,7 +233,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true; #endif .prescaler = BOARD_GCLK5_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK5_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK5_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -245,7 +251,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true; #endif .prescaler = BOARD_GCLK6_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK6_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK6_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -262,7 +269,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true; #endif .prescaler = BOARD_GCLK7_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK7_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK7_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif @@ -279,7 +287,8 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = .output = true; #endif .prescaler = BOARD_GCLK8_PRESCALER, - .clksrc = (uint8_t)(BOARD_GCLK8_CLOCK_SOURCE >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(BOARD_GCLK8_CLOCK_SOURCE >> + GCLK_GENCTRL_SRC_SHIFT), } #endif }; @@ -287,20 +296,24 @@ static const struct sam_gclkconfig_s g_gclkconfig[] = #define NGCLKS_ENABLED (sizeof(g_gclkconfig) / sizeof(struct sam_gclkconfig_s)) #endif -/* These are temporary GLCK0 configuration that may be needed at power up */ +/* These are temporary GLCK0 configuration that may be needed at + * power up + */ static const struct sam_gclkconfig_s g_gclk0_default = { .gclk = 0, .prescaler = 1, - .clksrc = (uint8_t)(GCLK_GENCTRL_SRC_OSC16M >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(GCLK_GENCTRL_SRC_OSC16M >> + GCLK_GENCTRL_SRC_SHIFT), }; static const struct sam_gclkconfig_s g_gclk0_ulp32kconfig = { .gclk = 0, .prescaler = 1, - .clksrc = (uint8_t)(GCLK_GENCTRL_SRC_OSCULP32K >> GCLK_GENCTRL_SRC_SHIFT), + .clksrc = (uint8_t)(GCLK_GENCTRL_SRC_OSCULP32K >> + GCLK_GENCTRL_SRC_SHIFT), }; /**************************************************************************** @@ -471,7 +484,8 @@ static inline void sam_xosc_config(void) * * BOARD_XOSC32K_ENABLE - Boolean (defined / not defined) * BOARD_XOSC32K_FREQUENCY - In Hz - * BOARD_XOSC32K_STARTUPTIME - See OSC32KCTRL_XOSC32K_STARTUP_* definitions + * BOARD_XOSC32K_STARTUPTIME - See OSC32KCTRL_XOSC32K_STARTUP_* + * definitions * BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined) * BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined) * BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined) @@ -556,7 +570,8 @@ static inline void sam_xosc32k_config(void) * * BOARD_OSC32K_ENABLE - Boolean (defined / not defined) * BOARD_OSC32K_FREQUENCY - In Hz - * BOARD_OSC32K_STARTUPTIME - See OSC32KCTRL_OSC32K_STARTUP_* definitions + * BOARD_OSC32K_STARTUPTIME - See OSC32KCTRL_OSC32K_STARTUP_* + * definitions * BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined) * BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined) * BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined) @@ -692,9 +707,11 @@ static inline void sam_osc16m_config(void) */ enabled = ((regval & OSCCTRL_OSC16MCTRL_ENABLE) != 0); - if (enabled && (regval & OSCCTRL_OSC16MCTRL_FSEL_MASK) == BOARD_OSC16M_FSEL) + if (enabled && (regval & OSCCTRL_OSC16MCTRL_FSEL_MASK) == + BOARD_OSC16M_FSEL) { - regval &= ~(OSCCTRL_OSC16MCTRL_ONDEMAND | OSCCTRL_OSC16MCTRL_RUNSTDBY); + regval &= ~(OSCCTRL_OSC16MCTRL_ONDEMAND | + OSCCTRL_OSC16MCTRL_RUNSTDBY); #ifdef BOARD_OSC16M_ONDEMAND /* Select on-demand oscillator controls */ @@ -736,7 +753,8 @@ static inline void sam_osc16m_config(void) /* Set the new OSC16M configuration */ - regval &= ~(OSCCTRL_OSC16MCTRL_FSEL_MASK | OSCCTRL_OSC16MCTRL_RUNSTDBY | + regval &= ~(OSCCTRL_OSC16MCTRL_FSEL_MASK | + OSCCTRL_OSC16MCTRL_RUNSTDBY | OSCCTRL_OSC16MCTRL_ONDEMAND); regval |= BOARD_OSC16M_FSEL; @@ -979,9 +997,12 @@ static inline void sam_dfll48m_refclk(void) * BOARD_FDPLL96M_LBYPASS - Boolean (defined / not defined) * BOARD_FDPLL96M_WUF - Boolean (defined / not defined) * BOARD_FDPLL96M_LPEN - Boolean (defined / not defined) - * BOARD_FDPLL96M_FILTER - See OSCCTRL_DPLLCTRLB_FILTER_* definitions - * BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions - * BOARD_FDPLL96M_LOCKTIME - See OSCCTRL_DPLLCTRLB_LTIME_* definitions + * BOARD_FDPLL96M_FILTER - See OSCCTRL_DPLLCTRLB_FILTER_* + * definitions + * BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* + * definitions + * BOARD_FDPLL96M_LOCKTIME - See OSCCTRL_DPLLCTRLB_LTIME_* + * definitions * BOARD_FDPLL96M_REFDIV - Numeric value, 1 - 2047 * BOARD_FDPLL96M_PRESCALER - See OSCCTRL_DPLLPRESC_* definitions * BOARD_FDPLL96M_REFFREQ - Numeric value @@ -1037,7 +1058,8 @@ static inline void sam_fdpll96m_config(void) /* Wait for synchronization */ - while ((getreg8(SAM_OSCCTRL_DPLLSYNCBUSY) & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) != 0); + while ((getreg8(SAM_OSCCTRL_DPLLSYNCBUSY) & + OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) != 0); /* Set DPLLCTRLB configuration */ @@ -1063,7 +1085,8 @@ static inline void sam_fdpll96m_config(void) /* Wait for synchronization */ - while ((getreg8(SAM_OSCCTRL_DPLLSYNCBUSY) & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) != 0); + while ((getreg8(SAM_OSCCTRL_DPLLSYNCBUSY) & + OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) != 0); /* Enable the FDPLL96M output */ @@ -1072,7 +1095,8 @@ static inline void sam_fdpll96m_config(void) /* Wait for synchronization */ - while ((getreg8(SAM_OSCCTRL_DPLLSYNCBUSY) & OSCCTRL_DPLLSYNCBUSY_ENABLE) != 0); + while ((getreg8(SAM_OSCCTRL_DPLLSYNCBUSY) & + OSCCTRL_DPLLSYNCBUSY_ENABLE) != 0); /* Wait for the FPDLL96M to become locked and ready */ @@ -1099,7 +1123,8 @@ static inline void sam_fdpll96m_config(void) * Depends on: * * BOARD_FDPLL96M_ENABLE - Boolean (defined / not defined) - * BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions + * BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* + * definitions * BOARD_FDPLL96M_REFCLK_CLKGEN - GCLK index in the range {0..8} * BOARD_FDPLL96M_LOCKTIME_ENABLE - Boolean (defined / not defined) * BOARD_FDPLL96M_LOCKTIME_CLKGEN - GCLK index in the range {0..8} diff --git a/arch/arm/src/samd5e5/chip.h b/arch/arm/src/samd5e5/chip.h index 22e470a43fb..e556a318eee 100644 --- a/arch/arm/src/samd5e5/chip.h +++ b/arch/arm/src/samd5e5/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_H #define __ARCH_ARM_SRC_SAMD5E5_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,27 +31,27 @@ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Provide the required number of peripheral interrupt vector definitions as well. - * The definition SAM_IRQ_NEXTINT simply comes from the chip-specific IRQ header - * file included by arch/sam34/irq.h. +/* Provide the required number of peripheral interrupt vector definitions as + * well. The definition SAM_IRQ_NEXTINT simply comes from the chip-specific + * IRQ header file included by arch/sam34/irq.h. */ #define ARMV7M_PERIPHERAL_INTERRUPTS SAM_IRQ_NEXTINT -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_aes.h b/arch/arm/src/samd5e5/hardware/sam_aes.h index cb581470421..0e52c4e34cf 100644 --- a/arch/arm/src/samd5e5/hardware/sam_aes.h +++ b/arch/arm/src/samd5e5/hardware/sam_aes.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_aes.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_AES_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_AES_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* AES register offsets ********************************************************************/ +/* AES register offsets *****************************************************/ #define SAM_AES_CTRLA_OFFSET 0x0000 /* Control A Register */ #define SAM_AES_CTRLB_OFFSET 0x0004 /* Control B Register */ @@ -70,7 +70,7 @@ #define SAM_AES_CIPLEN_OFFSET 0x0080 /* Cipher Length Register */ #define SAM_AES_RANDSEED_OFFSET 0x0084 /* Random Seed Register */ -/* AES register addresses ******************************************************************/ +/* AES register addresses ***************************************************/ #define SAM_AES_CTRLA (SAM_AES_BASE+SAM_AES_CTRLA_OFFSET) #define SAM_AES_CTRLB (SAM_AES_BASE+SAM_AES_CTRLB_OFFSET) @@ -107,7 +107,7 @@ #define SAM_AES_CIPLEN (SAM_AES_BASE+SAM_AES_CIPLEN_OFFSET) #define SAM_AES_RANDSEED (SAM_AES_BASE+SAM_AES_RANDSEED_OFFSET) -/* AES register bit definitions ************************************************************/ +/* AES register bit definitions *********************************************/ /* Control A Register */ @@ -122,6 +122,7 @@ # define AES_CTRLA_AESMODE_CNTR (4 << AES_CTRLA_AESMODE_SHIFT) /* Counter mode */ # define AES_CTRLA_AESMODE_CCM (5 << AES_CTRLA_AESMODE_SHIFT) /* CCM mode */ # define AES_CTRLA_AESMODE_GCM (6 << AES_CTRLA_AESMODE_SHIFT) /* Galois counter mode */ + #define AES_CTRLA_CFBS_SHIFT (5) /* Bits 5-7: Cipher feedback block size */ #define AES_CTRLA_CFBS_MASK (7 << AES_CTRLA_CFBS_SHIFT) # define AES_CTRLA_CFBS_128 (0 << AES_CTRLA_CFBS_SHIFT) /* 128-bit data block */ @@ -129,11 +130,13 @@ # define AES_CTRLA_CFBS_32 (2 << AES_CTRLA_CFBS_SHIFT) /* 32-bit data block */ # define AES_CTRLA_CFBS_16 (3 << AES_CTRLA_CFBS_SHIFT) /* 16-bit data block */ # define AES_CTRLA_CFBS_8 (4 << AES_CTRLA_CFBS_SHIFT) /* 8-bit data block */ + #define AES_CTRLA_KEYSIZE_SHIFT (8) /* Bits 8-9: Encryption key size */ #define AES_CTRLA_KEYSIZE_MASK (3 << AES_CTRLA_KEYSIZE_SHIFT) # define AES_CTRLA_KEYSIZE_128 (0 << AES_CTRLA_KEYSIZE_SHIFT) /* 128-bit key */ # define AES_CTRLA_KEYSIZE_192 (1 << AES_CTRLA_KEYSIZE_SHIFT) /* 192-bit key */ # define AES_CTRLA_KEYSIZE_256 (2 << AES_CTRLA_KEYSIZE_SHIFT) /* 256-bit key */ + #define AES_CTRLA_CIPHER (1 << 10) /* Bit 10: Cipher */ #define AES_CTRLA_STARTMODE (1 << 11) /* Bit 11: Start mode select */ #define AES_CTRLA_LOD (1 << 12) /* Bit 12: Last output data mode */ @@ -157,8 +160,8 @@ #define AES_CTRLB_EOM (1 << 2) /* Bit 2: End of message */ #define AES_CTRLB_GFMUL (1 << 3) /* Bit 3: GF multiplication */ -/* Common Bit Definitions for the Interrupt Enable Clear Register, Interrupt Enable Set - * Register, and Interrupt Flag Status and Clear Register +/* Common Bit Definitions for the Interrupt Enable Clear Register, Interrupt + * Enable Set Register, and Interrupt Flag Status and Clear Register */ #define AES_INT_ENCCMP (1 << 0) /* Bit 0: Encryption complete interrupt */ @@ -174,23 +177,29 @@ #define AES_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */ /* Keyword n Register, n = 0-7 (32-value) */ + /* Data Register (32-bit value) */ + /* Initialization Vector n Register, n=0-3 (32-bit value) */ + /* Hash Key n Register, n=0-3 (32-bit value) */ + /* Galois Hash n Register, n=0-3 (32-bit value) */ + /* Cipher Length Register (32-bit value) */ + /* Random Seed Register (32-bit value) */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_AES_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_cmcc.h b/arch/arm/src/samd5e5/hardware/sam_cmcc.h index a18d069ebc6..02310b398aa 100644 --- a/arch/arm/src/samd5e5/hardware/sam_cmcc.h +++ b/arch/arm/src/samd5e5/hardware/sam_cmcc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_cmcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_CMCC_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_CMCC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* This information is available in the Cache Type Register. How every, it is more - * efficient if we do not to do the decoding on each cache access. + ****************************************************************************/ + +/* This information is available in the Cache Type Register. How every, it + * is more efficient if we do not to do the decoding on each cache access. * * CacheSize = CacheLineSize * NCacheLines * NWays * CacheAddressRange = CacheLineSize * NCacheLines = CacheSize / NWays @@ -43,7 +44,7 @@ #define CMCC_CACHE_LINE_SIZE 16 /* 16 byte cache line size */ #define CMCC_NWAYS 4 /* 4 ways */ -/* CMCC register offsets ****************************************************************/ +/* CMCC register offsets ****************************************************/ #define SAM_CMCC_TYPE_OFFSET 0x0000 /* Cache Type Register */ #define SAM_CMCC_CFG_OFFSET 0x0004 /* Cache Configuration Register */ @@ -59,7 +60,7 @@ #define SAM_CMCC_MSR_OFFSET 0x0034 /* Cache Monitor Status Register */ /* 0x0038-0x00fc Reserved */ -/* CMCC register addresses **************************************************************/ +/* CMCC register addresses **************************************************/ #define SAM_CMCC_TYPE (SAM_CMCC_BASE + SAM_CMCC_TYPE_OFFSET) #define SAM_CMCC_CFG (SAM_CMCC_BASE + SAM_CMCC_CFG_OFFSET) @@ -72,7 +73,7 @@ #define SAM_CMCC_MCTRL (SAM_CMCC_BASE + SAM_CMCC_MCTRL_OFFSET) #define SAM_CMCC_MSR (SAM_CMCC_BASE + SAM_CMCC_MSR_OFFSET) -/* CMCC register bit definitions ********************************************************/ +/* CMCC register bit definitions ********************************************/ /* Cache Type Register */ @@ -87,6 +88,7 @@ # define CMCC_TYPE_WAYNUM_ARCH2WAY (1 << CMCC_TYPE_WAYNUM_SHIFT) /* 2-WAY set associative */ # define CMCC_TYPE_WAYNUM_ARCH4WAY (2 << CMCC_TYPE_WAYNUM_SHIFT) /* 4-WAY set associative */ # define CMCC_TYPE_WAYNUM_ARCH8WAY (3 << CMCC_TYPE_WAYNUM_SHIFT) /* 8-WAY set associative */ + #define CMCC_TYPE_LCKDOWN (1 << 7) /* Bit 7: Lock Down Supported */ #define CMCC_TYPE_CSIZE_SHIFT (8) /* Bits 8-10: Cache Size */ #define CMCC_TYPE_CSIZE_MASK (7 << CMCC_TYPE_CSIZE_SHIFT) @@ -94,6 +96,7 @@ # define CMCC_TYPE_CSIZE_2KB (1 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 2 Kbytes */ # define CMCC_TYPE_CSIZE_4KB (2 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 4 Kbytes */ # define CMCC_TYPE_CSIZE_8KB (3 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 8 Kbytes */ + #define CMCC_TYPE_CLSIZE_SHIFT (11) /* Bits 11-13: Cache Line Size */ #define CMCC_TYPE_CLSIZE_MASK (7 << CMCC_TYPE_CLSIZE_SHIFT) # define CMCC_TYPE_CLSIZE_4B (0 << CMCC_TYPE_CLSIZE_SHIFT) /* 4 Bytes */ @@ -165,16 +168,16 @@ /* Cache Monitor Status Register -- 32-bit event count */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_CMCC_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_dmac.h b/arch/arm/src/samd5e5/hardware/sam_dmac.h index c95ad19ca4c..56a63320b2f 100644 --- a/arch/arm/src/samd5e5/hardware/sam_dmac.h +++ b/arch/arm/src/samd5e5/hardware/sam_dmac.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_DMAC_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_DMAC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* DMAC register offsets ********************************************************************/ +/* DMAC register offsets ****************************************************/ #define SAM_DMAC_CTRL_OFFSET 0x0000 /* Control Register */ #define SAM_DMAC_CRCCTRL_OFFSET 0x0002 /* CRC Control Register */ @@ -69,7 +69,7 @@ #define SAM_LPSRAM_DSTADDR_OFFSET 0x0008 /* Block Transfer Destination Address Register */ #define SAM_LPSRAM_DESCADDR_OFFSET 0x000c /* Next Address Descriptor Register */ -/* DMAC register addresses ******************************************************************/ +/* DMAC register addresses **************************************************/ #define SAM_DMAC_CTRL (SAM_DMAC_BASE + SAM_DMAC_CTRL_OFFSET) #define SAM_DMAC_CRCCTRL (SAM_DMAC_BASE + SAM_DMAC_CRCCTRL_OFFSET) @@ -97,7 +97,7 @@ #define SAM_DMAC_CHINTFLAG(n) (SAM_DMAC_CHAN_BASE(n) + SAM_DMAC_CHINTFLAG_OFFSET) #define SAM_DMAC_CHSTATUS(n) (SAM_DMAC_CHAN_BASE(n) + SAM_DMAC_CHSTATUS_OFFSET) -/* DMAC register bit definitions ************************************************************/ +/* DMAC register bit definitions ********************************************/ /* Control Register */ @@ -115,15 +115,18 @@ # define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (0 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 8-bit bus transfer */ # define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (1 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 16-bit bus transfer */ # define DMAC_CRCCTRL_CRCBEATSIZE_WORD (2 < DMAC_CRCCTRL_CRCBEATSIZE_SHIFT) /* 32-bit bus transfer */ + #define DMAC_CRCCTRL_CRCPOLY_SHIFT (2) /* Bits 2-3: CRC polynomial type */ #define DMAC_CRCCTRL_CRCPOLY_MASK (3 < DMAC_CRCCTRL_CRCPOLY_SHIFT) # define DMAC_CRCCTRL_CRCPOLY_CRC16 (0 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC-16 (CRC-CCITT) */ # define DMAC_CRCCTRL_CRCPOLY_CRC32 (1 < DMAC_CRCCTRL_CRCPOLY_SHIFT) /* CRC32 (IEEE 802.3) */ + #define DMAC_CRCCTRL_CRCSRC_SHIFT (8) /* Bits 8-13: CRC Input Source */ #define DMAC_CRCCTRL_CRCSRC_MASK (0x3f < DMAC_CRCCTRL_CRCSRC_SHIFT) # define DMAC_CRCCTRL_CRCSRC_NOACTION (0 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* No action */ # define DMAC_CRCCTRL_CRCSRC_IO (1 < DMAC_CRCCTRL_CRCSRC_SHIFT) /* I/O interface */ # define DMAC_CRCCTRL_CRCSRC_CHAN(n) (((uint32_t)(n) + 0x20) < DMAC_CRCCTRL_CRCSRC_SHIFT) + #define DMAC_CRCCTRL_CRCMODE_SHIFT (14) /* Bits 14-15: CRC Operating Mode */ #define DMAC_CRCCTRL_CRCMODE_MASK (3 < DMAC_CRCCTRL_CRCMODE_SHIFT) # define DMAC_CRCCTRL_CRCMODE_DEFAULT (0 < DMAC_CRCCTRL_CRCMODE_SHIFT) /* Default operating mode */ @@ -131,6 +134,7 @@ # define DMAC_CRCCTRL_CRCMODE_CRCGEN (3 < DMAC_CRCCTRL_CRCMODE_SHIFT) /* Memory CRC generation mode */ /* CRC Data Input Register (32-bit value) */ + /* CRC Checksum Register (32-bit value) */ /* CRC Status Register */ @@ -143,8 +147,8 @@ #define DMAC_DBGCTRL_DBGRUN (1 << 0) /* Bit 0: Debug run */ -/* Common bit definitions for: Software Trigger Control Register, Interrupt Status Register, - * Busy Channels Register, and Pending Channels Register +/* Common bit definitions for: Software Trigger Control Register, Interrupt + * Status Register, Busy Channels Register, and Pending Channels Register */ #define DMAC_CHAN(n) (1 << (n)) /* DMAC Channel n, n=0-15 */ @@ -160,6 +164,7 @@ # define DMAC_PRICTRL0_QOS00_LOW (1 << DMAC_PRICTRL0_QOS00_SHIFT) /* Low bandwidth sensitivity */ # define DMAC_PRICTRL0_QOS00_MEDIUM (2 << DMAC_PRICTRL0_QOS00_SHIFT) /* Sensitive to latency */ # define DMAC_PRICTRL0_QOS00_CRITICAL (3 << DMAC_PRICTRL0_QOS00_SHIFT) /* Latency critical */ + #define DMAC_PRICTRL0_RRLVLEN0 (1 << 7) /* Bit 7: Level 0 round-robin arbitrarion enable */ #define DMAC_PRICTRL0_LVLPRI1_SHIFT (8) /* Bits 8-12: Level 1 channel priority number */ #define DMAC_PRICTRL0_LVLPRI1_MASK (31 << DMAC_PRICTRL0_LVLPRI1_SHIFT) @@ -170,6 +175,7 @@ # define DMAC_PRICTRL0_QOS01_LOW (1 << DMAC_PRICTRL0_QOS01_SHIFT) /* Low bandwidth sensitivity */ # define DMAC_PRICTRL0_QOS01_MEDIUM (2 << DMAC_PRICTRL0_QOS01_SHIFT) /* Sensitive to latency */ # define DMAC_PRICTRL0_QOS01_CRITICAL (3 << DMAC_PRICTRL0_QOS01_SHIFT) /* Latency critical */ + #define DMAC_PRICTRL0_RRLVLEN1 (1 << 15) /* Bit 15: Level 1 round-robin arbitrarion enable */ #define DMAC_PRICTRL0_LVLPRI2_SHIFT (16) /* Bits 16-20: Level 2 channel priority number */ #define DMAC_PRICTRL0_LVLPRI2_MASK (31 << DMAC_PRICTRL0_LVLPRI2_SHIFT) @@ -180,6 +186,7 @@ # define DMAC_PRICTRL0_QOS02_LOW (1 << DMAC_PRICTRL0_QOS02_SHIFT) /* Low bandwidth sensitivity */ # define DMAC_PRICTRL0_QOS02_MEDIUM (2 << DMAC_PRICTRL0_QOS02_SHIFT) /* Sensitive to latency */ # define DMAC_PRICTRL0_QOS02_CRITICAL (3 << DMAC_PRICTRL0_QOS02_SHIFT) /* Latency critical */ + #define DMAC_PRICTRL0_RRLVLEN2 (1 << 23) /* Bit 23: Level 2 round-robin arbitrarion enable */ #define DMAC_PRICTRL0_LVLPRI3_SHIFT (24) /* Bits 24-28: Level 2 channel priority number */ #define DMAC_PRICTRL0_LVLPRI3_MASK (31 << DMAC_PRICTRL0_LVLPRI3_SHIFT) @@ -190,6 +197,7 @@ # define DMAC_PRICTRL0_QOS03_LOW (1 << DMAC_PRICTRL0_QOS03_SHIFT) /* Low bandwidth sensitivity */ # define DMAC_PRICTRL0_QOS03_MEDIUM (2 << DMAC_PRICTRL0_QOS03_SHIFT) /* Sensitive to latency */ # define DMAC_PRICTRL0_QOS03_CRITICAL (3 << DMAC_PRICTRL0_QOS03_SHIFT) /* Latency critical */ + #define DMAC_PRICTRL0_RRLVLEN3 (1 << 23) /* Bit 21: Level 3 round-robin arbitrarion enable */ /* Interrupt Pending Register */ @@ -217,6 +225,7 @@ #define DMAC_ACTIVE_BTCNT_MASK (0xffff << DMAC_ACTIVE_BTCNT_SHIFT) /* Descriptor Memory Section Base Address Register (32-bit address) */ + /* Write-Back Memory Section Base Address Register (32-bit address) */ /* Channel Control A Register */ @@ -233,6 +242,7 @@ # define DMAC_CHCTRLA_TRIGACT_BLOCK (0 << DMAC_CHCTRLA_TRIGACT_SHIFT) /* Trigger per block transfer */ # define DMAC_CHCTRLA_TRIGACT_BURST (2 << DMAC_CHCTRLA_TRIGACT_SHIFT) /* Trigger per burst transfer */ # define DMAC_CHCTRLA_TRIGACT_TRANS (3 << DMAC_CHCTRLA_TRIGACT_SHIFT) /* Trigger for each transaction */ + #define DMAC_CHCTRLA_BURSTLEN_SHIFT (24) /* Bits 24-27: Burst Length (beats-1) */ #define DMAC_CHCTRLA_BURSTLEN_MASK (15 << DMAC_CHCTRLA_BURSTLEN_SHIFT) # define DMAC_CHCTRLA_BURSTLEN(n) ((uint32_t)((n) - 1) << DMAC_CHCTRLA_BURSTLEN_SHIFT) @@ -252,6 +262,7 @@ # define DMAC_CHCTRLA_BURSTLEN_14BEATS (13 << DMAC_CHCTRLA_BURSTLEN_SHIFT) /* 14-beats burst length */ # define DMAC_CHCTRLA_BURSTLEN_15BEATS (14 << DMAC_CHCTRLA_BURSTLEN_SHIFT) /* 15-beats burst length */ # define DMAC_CHCTRLA_BURSTLEN_16BEATS (15 << DMAC_CHCTRLA_BURSTLEN_SHIFT) /* 16-beats burst length */ + #define DMAC_CHCTRLA_THRESHOLD_SHIFT (28) /* Bits 28-29: FIFO Threshold (log2 beats) */ #define DMAC_CHCTRLA_THRESHOLD_MASK (3 << DMAC_CHCTRLA_THRESHOLD_SHIFT) # define DMAC_CHCTRLA_THRESHOLD(n) ((uint32_t)(n) << DMAC_CHCTRLA_THRESHOLD_SHIFT) @@ -373,15 +384,18 @@ # define DMAC_CHEVCTRL_EVACT_RESUME (5 << DMAC_CHEVCTRL_EVACT_SHIFT) /* Channel resume operation */ # define DMAC_CHEVCTRL_EVACT_SSKIP (6 << DMAC_CHEVCTRL_EVACT_SHIFT) /* Skip next block suspend action */ # define DMAC_CHEVCTRL_EVACT_INCPRI (7 << DMAC_CHEVCTRL_EVACT_SHIFT) /* Increase priority */ + #define DMAC_CHEVCTRL_EVOMODE_SHIFT (4) /* Bits 4-5: Channel event output mode */ #define DMAC_CHEVCTRL_EVOMODE_MASK (3 << DMAC_CHEVCTRL_EVOMODE_SHIFT) # define DMAC_CHEVCTRL_EVOMODE_DEFAULT (0 << DMAC_CHEVCTRL_EVOMODE_SHIFT) /* Block event output selection */ # define DMAC_CHEVCTRL_EVOMODE_TRIGACT (1 << DMAC_CHEVCTRL_EVOMODE_SHIFT) /* Ongoing trigger action */ + #define DMAC_CHEVCTRL_EVIE (1 << 6) /* Bit 6 – Channel Event Input Enable */ #define DMAC_CHEVCTRL_EVOE (1 << 7) /* Bit 7 – Channel Event Output Enable */ -/* Common register bit definitions: Channel Interrupt Enable Clear Register, Channel Interrupt - * Enable Set Register, and Channel Interrupt Flag Status and Clear Register +/* Common register bit definitions: Channel Interrupt Enable Clear Register, + * Channel Interrupt Enable Set Register, and Channel Interrupt Flag Status + * and Clear Register */ #define DMAC_INT_TERR (1 << 0) /* Bit 0: Transfer error interrupt */ @@ -399,26 +413,29 @@ /* Block Transfer Control Register */ #define LPSRAM_BTCTRL_VALID (1 << 0) /* Bit 0: Descriptor valid */ -#define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */ +#define LPSRAM_BTCTRL_EVOSEL_SHIFT (1) /* Bits 1-2: Event output selection */ #define LPSRAM_BTCTRL_EVOSEL_MASK (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) # define LPSRAM_BTCTRL_EVOSEL_DISABLE (0 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event generation disabled */ # define LPSRAM_BTCTRL_EVOSEL_BLOCK (1 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when block transfer complete */ # define LPSRAM_BTCTRL_EVOSEL_BEAT (3 << LPSRAM_BTCTRL_EVOSEL_SHIFT) /* Event strobe when beat transfer complete */ + #define LPSRAM_BTCTRL_BLOCKACT_SHIFT (3) /* Bits 3-4: Block action */ #define LPSRAM_BTCTRL_BLOCKACT_MASK (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) # define LPSRAM_BTCTRL_BLOCKACT_NOACT (0 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer */ # define LPSRAM_BTCTRL_BLOCKACT_INT (1 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel disabled if last block transfer + block int */ # define LPSRAM_BTCTRL_BLOCKACT_SUSPEND (2 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Channel suspend operation is completed */ # define LPSRAM_BTCTRL_BLOCKACT_BOTH (3 << LPSRAM_BTCTRL_BLOCKACT_SHIFT) /* Both channel suspend operation + block int */ + #define LPSRAM_BTCTRL_BEATSIZE_SHIFT (8) /* Bits 8-9: Beat size */ #define LPSRAM_BTCTRL_BEATSIZE_MASK (3 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) # define LPSRAM_BTCTRL_BEATSIZE_BYTE (0 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 8-bit bus transfer */ # define LPSRAM_BTCTRL_BEATSIZE_HWORD (1 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 16-bit bus transfer */ # define LPSRAM_BTCTRL_BEATSIZE_WORD (2 << LPSRAM_BTCTRL_BEATSIZE_SHIFT) /* 32-bit bus transfer */ + #define LPSRAM_BTCTRL_SRCINC (1 << 10) /* Bit 10: Source address increment enable */ #define LPSRAM_BTCTRL_DSTINC (1 << 11) /* Bit 11: Destination address increment enable */ #define LPSRAM_BTCTRL_STEPSEL (1 << 12) /* Bit 12: Step selection */ -#define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */ +#define LPSRAM_BTCTRL_STEPSIZE_SHIFT (13) /* Bits 13-15: Address increment step */ #define LPSRAM_BTCTRL_STEPSIZE_MASK (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) # define LPSRAM_BTCTRL_STEPSIZE_X1 (0 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 1 */ # define LPSRAM_BTCTRL_STEPSIZE_X2 (1 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 2 */ @@ -430,13 +447,17 @@ # define LPSRAM_BTCTRL_STEPSIZE_X128 (7 << LPSRAM_BTCTRL_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */ /* Block Transfer Count Register (16-bit count) */ + /* Block Transfer Source Address Register (32-bit address) */ + /* Block Transfer Destination Address Register (32-bit address) */ + /* Next Address Descriptor Register (32-bit address) */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ + /* DMA descriptor */ struct dma_desc_s @@ -448,12 +469,12 @@ struct dma_desc_s uint32_t descaddr; /* Next Address Descriptor Register */ }; -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_DMAC_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_eic.h b/arch/arm/src/samd5e5/hardware/sam_eic.h index ed0656a2595..75fb1df5a27 100644 --- a/arch/arm/src/samd5e5/hardware/sam_eic.h +++ b/arch/arm/src/samd5e5/hardware/sam_eic.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_eic.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EIC_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EIC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* EIC register offsets *********************************************************************/ +/* EIC register offsets *****************************************************/ #define SAM_EIC_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_EIC_NMICTRL_OFFSET 0x0001 /* Non-maskable interrupt control register */ @@ -50,7 +50,7 @@ #define SAM_EIC_DPRESCALER_OFFSET 0x0034 /* Debouncer prescaler */ #define SAM_EIC_PINSTATE_OFFSET 0x0038 /* Pin state */ -/* EIC register addresses *******************************************************************/ +/* EIC register addresses ***************************************************/ #define SAM_EIC_CTRLA (SAM_EIC_BASE + SAM_EIC_CTRLA_OFFSET) #define SAM_EIC_NMICTRL (SAM_EIC_BASE + SAM_EIC_NMICTRL_OFFSET) @@ -67,7 +67,7 @@ #define SAM_EIC_DPRESCALER (SAM_EIC_BASE + SAM_EIC_DPRESCALER_OFFSET) #define SAM_EIC_PINSTATE (SAM_EIC_BASE + SAM_EIC_PINSTATE_OFFSET) -/* EIC register bit definitions *************************************************************/ +/* EIC register bit definitions *********************************************/ /* Control A register */ @@ -99,8 +99,9 @@ #define EIC_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset syncrhonization busy */ #define EIC_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable synchronization busy */ -/* Event control, Interrupt enable clear, interrupt enable set register, interrupt flag - * status and clear, and External interrupt asynchronous mode registers. +/* Event control, Interrupt enable clear, interrupt enable set register, + * interrupt flag status and clear, and External interrupt asynchronous mode + * registers. */ #define EIC_EXTINT_SHIFT (0) /* Bits 0-15: External interrupt n */ @@ -225,16 +226,16 @@ # define EIC_PINSTATE_14 (1 << 14) /* Bit 14: EXTINT 14 pin state */ # define EIC_PINSTATE_15 (1 << 15) /* Bit 15: EXTINT 15 pin state */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Functions Prototypes - ********************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EIC_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_evsys.h b/arch/arm/src/samd5e5/hardware/sam_evsys.h index 6c7ffb74af7..9f8b0e9dc04 100644 --- a/arch/arm/src/samd5e5/hardware/sam_evsys.h +++ b/arch/arm/src/samd5e5/hardware/sam_evsys.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_evsys.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,27 +16,27 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EVSYS_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EVSYS_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ #define SAM_EVSYS_NCHANNELS 32 /* 0-31 */ #define SAM_EVSYS_NUSER 67 /* 0-66 */ -/* EVSYS register offsets *******************************************************************/ +/* EVSYS register offsets ***************************************************/ #define SAM_EVSYS_CTRLA_OFFSET 0x0000 /* Control register */ #define SAM_EVSYS_SWEVT_OFFSET 0x0004 /* Software event register */ @@ -47,6 +47,7 @@ #define SAM_EVSYS_READYUSR_OFFSET 0x001c /* Busy channels register */ #define SAM_EVSYS_CHOFFSET(n) (0x0020 + ((n) << 3)) /* Channel registers */ + # define SAM_EVSYS_CHANNEL_OFFSET 0x0000 /* Channel control register */ # define SAM_EVSYS_CHINTENCLR_OFFSET 0x0004 /* Channel interrupt clear register */ # define SAM_EVSYS_CHINTENSET_OFFSET 0x0005 /* Channel interrupt enable register */ @@ -55,7 +56,7 @@ #define SAM_EVSYS_USER_OFFSET(n) (0x0120 + ((m)) /* User registers */ -/* EVSYS register addresses *****************************************************************/ +/* EVSYS register addresses *************************************************/ #define SAM_EVSYS_CTRLA (SAM_EVSYS_BASE + SAM_EVSYS_CTRLA_OFFSET) #define SAM_EVSYS_SWEVT (SAM_EVSYS_BASE + SAM_EVSYS_SWEVT_OFFSET) @@ -74,7 +75,7 @@ #define SAM_EVSYS_USER(n) (SAM_EVSYS_BASE + SAM_EVSYS_USER_OFFSET(n)) -/* EVSYS register bit definitions ***********************************************************/ +/* EVSYS register bit definitions *******************************************/ /* Control register */ @@ -123,17 +124,19 @@ # define EVSYS_CHANNEL_PATH_SYNCH (0 << EVSYS_CHANNEL_PATH_SHIFT) /* Synchronous path */ # define EVSYS_CHANNEL_PATH_RESYNCH (1 << EVSYS_CHANNEL_PATH_SHIFT) /* Resynchronized path */ # define EVSYS_CHANNEL_PATH_ASYNCH (2 << EVSYS_CHANNEL_PATH_SHIFT) /* Asynchronous path */ + #define EVSYS_CHANNEL_EDGSEL_SHIFT (10) /* Bits 10-11: Edge detection selection */ #define EVSYS_CHANNEL_EDGSEL_MASK (3 << EVSYS_CHANNEL_EDGSEL_SHIFT) # define EVSYS_CHANNEL_EDGSEL_NONE (0 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* No event output */ # define EVSYS_CHANNEL_EDGSEL_ RISING (1 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event on rising edge */ # define EVSYS_CHANNEL_EDGSEL_FALLING (2 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event on falling edge */ # define EVSYS_CHANNEL_EDGSEL_BOTH (3 << EVSYS_CHANNEL_EDGSEL_SHIFT) /* Event on both edges */ + #define EVSYS_CHANNEL_RUNSTDBY (1 << 14) /* Bit 14: Run in standby */ #define EVSYS_CHANNEL_ONDEMAND (1 << 15) /* Bit 15: Generic clock on demand */ -/* Channel interrupt clear register, Channel interrupt enable register, and Channel interrupt - * status register +/* Channel interrupt clear register, Channel interrupt enable register, + * and Channel interrupt status register */ #define EVSYS_CHINT_OVR (1 << 0) /* Bit 0: Channel overrun */ @@ -144,9 +147,11 @@ #define EVSYS_CHSTATUS_RDYUSR (1 << 0) /* Bit 0: Ready user */ #define EVSYS_CHSTATUS_BUSYCH (1 << 1) /* Bit 1: Busy channel */ -/* User registers (8-bit channel number. See user multiplexor numbers below */ +/* User registers (8-bit channel number. + * See user multiplexor numbers below + */ -/* Event generator channel event selection **************************************************/ +/* Event generator channel event selection **********************************/ #define EVSYS_EVENT_NONE 0x00 /* No event generator selected */ #define EVSYS_EVENT_OSCCTRL_XOSC_FAIL0 0x01 /* XOSC fail detection 0 */ @@ -267,9 +272,10 @@ #define EVSYS_EVENT_CCL_LUTOUT2 0x76 /* CCL LUTOUT 2 */ #define EVSYS_EVENT_CCL_LUTOUT3 0x77 /* CCL LUTOUT 3 */ -/* User multiplexer numbers ****************************************************************/ -/* These are indices that may be used with the SAM_EVSYS_USER(n) macro to get the address of - * the correct user register. +/* User multiplexer numbers ************************************************/ + +/* These are indices that may be used with the SAM_EVSYS_USER(n) macro to get + * the address of the correct user register. */ #define EVSYS_USER_RTC_TAMPER 0 /* RTC Tamper A */ @@ -339,16 +345,16 @@ #define EVSYS_USER_CCL_LUTIN2 65 /* CCL input 2 */ #define EVSYS_USER_CCL_LUTIN3 66 /* CCL input 3 */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EVSYS_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_fuses.h b/arch/arm/src/samd5e5/hardware/sam_fuses.h index 55fa936e672..998a5dd5c4f 100644 --- a/arch/arm/src/samd5e5/hardware/sam_fuses.h +++ b/arch/arm/src/samd5e5/hardware/sam_fuses.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_fuses.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,27 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_FUSES_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_FUSES_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* NVM Fuse addresses **********************************************************************/ + ****************************************************************************/ -/* NVM user row bits. The first eight 32-bit words contains calibration information that - * are automatically read at device power-on. The remaining 480 bytes can be used for - * storing custom parameters. +/* NVM Fuse addresses *******************************************************/ + +/* NVM user row bits. The first eight 32-bit words contains calibration + * information that are automatically read at device power-on. + * The remaining 480 bytes can be used for storing custom parameters. */ #define SAM_NVMUSER_ROW0 (SAM_NVM_USERPAGE + 0x0000) /* Bits 0-31 */ @@ -60,7 +61,8 @@ #define SAM_NVM_CALIBTEMP2 (SAM_NVM_CALIBAREA + 0x0080) /* Bits 64-95 */ #define SAM_NVM_CALIBTEMP3 (SAM_NVM_CALIBAREA + 0x0080) /* Bits 96-127 */ -/* Fuse bit-field definitions **************************************************************/ +/* Fuse bit-field definitions ***********************************************/ + /* NVM user pages */ #define SAM_FUSES_BOD33_DIS_ADDR SAM_NVMUSER_ROW0 @@ -89,7 +91,7 @@ #define SAM_FUSES_NVM_BOOT_MASK (15 << SAM_FUSES_NVM_BOOT_SHIFT) # define SAM_FUSES_NVM_BOOT(n) (((uint32_t)n) << SAM_FUSES_NVM_BOOT_SHIFT) - /* Bits 30-31: Factor settings */ + /* Bits 30-31: Factor settings */ #define SAM_FUSES_SEESBLK_ADDR SAM_NVMUSER_ROW1 #define SAM_FUSES_SEESBLK_SHIFT (0) /* Bits 32-35: NVM Bootloader Size */ @@ -105,7 +107,7 @@ #define SAM_FUSES_RAM_ECCDIS_SHIFT (7) /* Bit 39: SmartEEPROM Page Size */ #define SAM_FUSES_RAM_ECCDIS_MASK (1 << SAM_FUSES_RAM_ECCDIS_SHIFT) - /* Bits 40-47: Factor settings */ + /* Bits 40-47: Factor settings */ #define SAM_FUSES_WDT_ENA_ADDR SAM_NVMUSER_ROW1 #define SAM_FUSES_WDT_ENA_SHIFT (16) /* Bit 48: WDT Enable */ @@ -133,16 +135,18 @@ #define SAM_FUSES_WDT_WEN_SHIFT (30) /* Bit 62: WDT Window Mode Enable*/ #define SAM_FUSES_WDT_WEN_MASK (1 << SAM_FUSES_WDT_WEN_SHIFT) - /* Bit 63: Reserved */ + /* Bit 63: Reserved */ #define SAM_FUSES_LOCK_ADDR SAM_NVMUSER_ROW2 #define SAM_FUSES_LOCK_SHIFT (0) /* Bits 64-95: NVM Region Lock bits */ #define SAM_FUSES_LOCK_MASK (0xffffffff << SAM_FUSES_LOCK_SHIFT) # define SAM_FUSES_LOCK(n) ((uint32_t)(n) << SAM_FUSES_LOCK_SHIFT) - /* Bits 96-127: Usage page */ - /* Bits 128-159: Reserved */ - /* Bits 160-255: User pages */ + /* Bits 96-127: Usage page */ + + /* Bits 128-159: Reserved */ + + /* Bits 160-255: User pages */ /* NVM Calibration Area */ @@ -166,7 +170,7 @@ #define SAM_FUSES_ADC0_BIASR2R_MASK (7 << SAM_FUSES_ADC0_BIASR2R_SHIFT) # define SAM_FUSES_ADC0_BIASR2R(n) ((uint32_t)(n) << SAM_FUSES_ADC0_BIASR2R_SHIFT) - /* Bits 11-15: Reserved */ + /* Bits 11-15: Reserved */ #define SAM_FUSES_ADC1_BIASCOMP_ADDR SAM_NVM_CALIBAREA0 #define SAM_FUSES_ADC1_BIASCOMP_SHIFT (16) /* Bits 16-18: ADC1 Bias comparator scaling */ @@ -183,7 +187,7 @@ #define SAM_FUSES_ADC1_BIASR2R_MASK (7 << SAM_FUSES_ADC1_BIASR2R_SHIFT) # define SAM_FUSES_ADC1_BIASR2R(n) ((uint32_t)(n) << SAM_FUSES_ADC1_BIASR2R_SHIFT) - /* Bits 25-35: Reserved */ + /* Bits 25-35: Reserved */ #define SAM_FUSES_USBTRANSN_ADDR SAM_NVM_CALIBAREA1 #define SAM_FUSES_USBTRANSN_SHIFT (0) /* Bits 32-36: USB TRNSN Calibration */ @@ -246,16 +250,16 @@ /* 88-127: Reserved */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_FUSES_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_gclk.h b/arch/arm/src/samd5e5/hardware/sam_gclk.h index 4073581ff4a..76fe78d6003 100644 --- a/arch/arm/src/samd5e5/hardware/sam_gclk.h +++ b/arch/arm/src/samd5e5/hardware/sam_gclk.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_gclk.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,27 +16,27 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_GCLK_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_GCLK_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ #define SAM_NGCLK 12 /* 12 Clock generators, 0-11 */ #define SAM_NCHANNELS 48 /* 48 Clock generators, 0..47 */ -/* GCLK register offsets ********************************************************************/ +/* GCLK register offsets ****************************************************/ #define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */ #define SAM_GCLK_SYNCHBUSY_OFFSET 0x0004 /* Status register */ @@ -44,7 +44,7 @@ #define SAM_GCLK_GENCTRL_OFFSET(n) (0x0020 + ((n) << 2)) /* General clock generator n */ #define SAM_GCLK_PCHCTRL_OFFSET(m) (0x0080 + ((m) << 2)) /* Peripheral channel control m */ -/* GCLK register addresses ******************************************************************/ +/* GCLK register addresses **************************************************/ #define SAM_GCLK_CTRLA (SAM_GCLK_BASE + SAM_GCLK_CTRLA_OFFSET) #define SAM_GCLK_SYNCHBUSY (SAM_GCLK_BASE + SAM_GCLK_SYNCHBUSY_OFFSET) @@ -52,7 +52,7 @@ #define SAM_GCLK_GENCTRL(n) (SAM_GCLK_BASE + SAM_GCLK_GENCTRL_OFFSET(n)) #define SAM_GCLK_PCHCTRL(n) (SAM_GCLK_BASE + SAM_GCLK_PCHCTRL_OFFSET(n)) -/* GCLK register bit definitions ************************************************************/ +/* GCLK register bit definitions ********************************************/ /* Control register */ @@ -61,7 +61,9 @@ /* Status register */ #define GCLK_SYNCHBUSY_SWRST (1 << 0) /* Bit 0: SWRST synchronization busy */ + #define GCLK_SYNCHBUSY_GENCTRL(n) (1 << ((n) + 2)) /* Bit n+2: Generator control n busy */ + # define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */ # define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */ # define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */ @@ -89,6 +91,7 @@ # define GCLK_GENCTRL_SRC_DFLL (6 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL oscillator output */ # define GCLK_GENCTRL_SRC_DPLL0 (7 << GCLK_GENCTRL_SRC_SHIFT) /* DPLL0 output */ # define GCLK_GENCTRL_SRC_DPLL1 (8 << GCLK_GENCTRL_SRC_SHIFT) /* DPLL1 output */ + #define GCLK_GENCTRL_GENEN (1 << 8) /* Bit 8: Generator enable */ #define GCLK_GENCTRL_IDC (1 << 9) /* Bit 9: Improve duty cycle */ #define GCLK_GENCTRL_OOV (1 << 10) /* Bit 10: Clock output selection */ @@ -122,7 +125,7 @@ #define GCLK_PCHCTRL_CHEN (1 << 6) /* Bit 6: Channel enable */ #define GCLK_PCHCTRL_WRTLOCK (1 << 7) /* Bit 7: Write lock */ -/* PCHCTRL channel mapping ******************************************************************/ +/* PCHCTRL channel mapping **************************************************/ #define GCLK_CHAN_OSCCTRL_DFLL 0 /* DFLL input clock source */ #define GCLK_CHAN_OSCCTRL_DPLL0 1 /* Reference clock for DPLL0 */ @@ -193,16 +196,16 @@ #define GCLK_CHAN_SDHC1 46 /* SDHC1 */ #define GCLK_CHAN_CM4_TRACE 47 /* CM4 Trace */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_GCLK_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_gmac.h b/arch/arm/src/samd5e5/hardware/sam_gmac.h index f7f454f9696..bd2e40fa0c1 100644 --- a/arch/arm/src/samd5e5/hardware/sam_gmac.h +++ b/arch/arm/src/samd5e5/hardware/sam_gmac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_gmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GMAC_H #define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* GMAC Register Offsets ************************************************************/ + ****************************************************************************/ + +/* GMAC Register Offsets ****************************************************/ #define SAM_GMAC_NCR_OFFSET 0x0000 /* Network Control Register */ #define SAM_GMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */ @@ -54,8 +55,10 @@ /* 0x0048-0x007c Reserved */ #define SAM_GMAC_HRB_OFFSET 0x0080 /* Hash Register Bottom [31:0] */ #define SAM_GMAC_HRT_OFFSET 0x0084 /* Hash Register Top [63:32] */ + #define SAM_GMAC_SAB_OFFSET(n) (0x0088 + (((n)-1) << 3)) /* n=1..4 */ #define SAM_GMAC_SAT_OFFSET(n) (0x008c + (((n)-1) << 3)) /* n=1..4 */ + #define SAM_GMAC_SAB1_OFFSET 0x0088 /* Specific Address 1 Bottom [31:0] Register */ #define SAM_GMAC_SAT1_OFFSET 0x008c /* Specific Address 1 Top [47:32] Register */ #define SAM_GMAC_SAB2_OFFSET 0x0090 /* Specific Address 2 Bottom [31:0] Register */ @@ -64,7 +67,9 @@ #define SAM_GMAC_SAT3_OFFSET 0x009c /* Specific Address 3 Top [47:32] Register */ #define SAM_GMAC_SAB4_OFFSET 0x00a0 /* Specific Address 4 Bottom [31:0] Register */ #define SAM_GMAC_SAT4_OFFSET 0x00a4 /* Specific Address 4 Top [47:32] Register */ + #define SAM_GMAC_TIDM_OFFSET(n) (0x00a8 + (((n)-1) << 2)) /* n=1..4 */ + #define SAM_GMAC_TIDM1_OFFSET 0x00a8 /* Type ID Match 1 Register */ #define SAM_GMAC_TIDM2_OFFSET 0x00ac /* Type ID Match 2 Register */ #define SAM_GMAC_TIDM3_OFFSET 0x00b0 /* Type ID Match 3 Register */ @@ -137,7 +142,9 @@ #define SAM_GMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */ /* 0x0200-0x023c Reserved */ /* 0x0280-0x0298 Reserved */ + #define SAM_GMAC_ISRPQ_OFFSET(n) (0x400 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_ISRPQ0_OFFSET 0x400 /* Interrupt Status Register Priority Queue 0 */ #define SAM_GMAC_ISRPQ1_OFFSET 0x404 /* Interrupt Status Register Priority Queue 1 */ #define SAM_GMAC_ISRPQ2_OFFSET 0x408 /* Interrupt Status Register Priority Queue 2 */ @@ -145,7 +152,9 @@ #define SAM_GMAC_ISRPQ4_OFFSET 0x410 /* Interrupt Status Register Priority Queue 4 */ #define SAM_GMAC_ISRPQ5_OFFSET 0x414 /* Interrupt Status Register Priority Queue 5 */ #define SAM_GMAC_ISRPQ6_OFFSET 0x418 /* Interrupt Status Register Priority Queue 6 */ + #define SAM_GMAC_TBQBAPQ_OFFSET(n) (0x440 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_TBQBAPQ0_OFFSET 0x440 /* Transmit Buffer Queue Base Address Priority Queue 0 */ #define SAM_GMAC_TBQBAPQ1_OFFSET 0x444 /* Transmit Buffer Queue Base Address Priority Queue 1 */ #define SAM_GMAC_TBQBAPQ2_OFFSET 0x448 /* Transmit Buffer Queue Base Address Priority Queue 2 */ @@ -153,7 +162,9 @@ #define SAM_GMAC_TBQBAPQ4_OFFSET 0x450 /* Transmit Buffer Queue Base Address Priority Queue 4 */ #define SAM_GMAC_TBQBAPQ5_OFFSET 0x454 /* Transmit Buffer Queue Base Address Priority Queue 5 */ #define SAM_GMAC_TBQBAPQ6_OFFSET 0x458 /* Transmit Buffer Queue Base Address Priority Queue 6 */ + #define SAM_GMAC_RBQBAPQ_OFFSET(n) (0x480 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_RBQBAPQ0_OFFSET 0x480 /* Receive Buffer Queue Base Address Priority Queue 0 */ #define SAM_GMAC_RBQBAPQ1_OFFSET 0x484 /* Receive Buffer Queue Base Address Priority Queue 1 */ #define SAM_GMAC_RBQBAPQ2_OFFSET 0x488 /* Receive Buffer Queue Base Address Priority Queue 2 */ @@ -161,7 +172,9 @@ #define SAM_GMAC_RBQBAPQ4_OFFSET 0x490 /* Receive Buffer Queue Base Address Priority Queue 4 */ #define SAM_GMAC_RBQBAPQ5_OFFSET 0x494 /* Receive Buffer Queue Base Address Priority Queue 5 */ #define SAM_GMAC_RBQBAPQ6_OFFSET 0x498 /* Receive Buffer Queue Base Address Priority Queue 6 */ + #define SAM_GMAC_RBSRPQ_OFFSET(n) (0x4a0 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_RBSRPQ0_OFFSET 0x4a0 /* Receive Buffer Size Register Priority Queue 0 */ #define SAM_GMAC_RBSRPQ1_OFFSET 0x4a4 /* Receive Buffer Size Register Priority Queue 1 */ #define SAM_GMAC_RBSRPQ2_OFFSET 0x4a8 /* Receive Buffer Size Register Priority Queue 2 */ @@ -169,7 +182,9 @@ #define SAM_GMAC_RBSRPQ4_OFFSET 0x4b0 /* Receive Buffer Size Register Priority Queue 4 */ #define SAM_GMAC_RBSRPQ5_OFFSET 0x4b4 /* Receive Buffer Size Register Priority Queue 5 */ #define SAM_GMAC_RBSRPQ6_OFFSET 0x4b8 /* Receive Buffer Size Register Priority Queue 6 */ + #define SAM_GMAC_ST1RPQ_OFFSET(n) (0x500 + ((n) << 2)) /* n=0..15 */ + #define SAM_GMAC_ST1RPQ0_OFFSET 0x500 /* Screening Type1 Register Priority Queue 0 */ #define SAM_GMAC_ST1RPQ1_OFFSET 0x504 /* Screening Type1 Register Priority Queue 1 */ #define SAM_GMAC_ST1RPQ2_OFFSET 0x508 /* Screening Type1 Register Priority Queue 2 */ @@ -186,7 +201,9 @@ #define SAM_GMAC_ST1RPQ13_OFFSET 0x534 /* Screening Type1 Register Priority Queue 13 */ #define SAM_GMAC_ST1RPQ14_OFFSET 0x538 /* Screening Type1 Register Priority Queue 14 */ #define SAM_GMAC_ST1RPQ15_OFFSET 0x53c /* Screening Type1 Register Priority Queue 15 */ + #define SAM_GMAC_ST2RPQ_OFFSET(n) (0x540 + ((n) << 2)) /* n=0..15 */ + #define SAM_GMAC_ST2RPQ0_OFFSET 0x540 /* Screening Type2 Register Priority Queue 0 */ #define SAM_GMAC_ST2RPQ1_OFFSET 0x544 /* Screening Type2 Register Priority Queue 1 */ #define SAM_GMAC_ST2RPQ2_OFFSET 0x548 /* Screening Type2 Register Priority Queue 2 */ @@ -203,7 +220,9 @@ #define SAM_GMAC_ST2RPQ13_OFFSET 0x574 /* Screening Type2 Register Priority Queue 13 */ #define SAM_GMAC_ST2RPQ14_OFFSET 0x578 /* Screening Type2 Register Priority Queue 14 */ #define SAM_GMAC_ST2RPQ15_OFFSET 0x57c /* Screening Type2 Register Priority Queue 15 */ + #define SAM_GMAC_IERPQ_OFFSET(n) (0x600 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_IERPQ0_OFFSET 0x600 /* Interrupt Enable Register Priority Queue 0 */ #define SAM_GMAC_IERPQ1_OFFSET 0x604 /* Interrupt Enable Register Priority Queue 1 */ #define SAM_GMAC_IERPQ2_OFFSET 0x608 /* Interrupt Enable Register Priority Queue 2 */ @@ -211,7 +230,9 @@ #define SAM_GMAC_IERPQ4_OFFSET 0x610 /* Interrupt Enable Register Priority Queue 4 */ #define SAM_GMAC_IERPQ5_OFFSET 0x614 /* Interrupt Enable Register Priority Queue 5 */ #define SAM_GMAC_IERPQ6_OFFSET 0x618 /* Interrupt Enable Register Priority Queue 6 */ + #define SAM_GMAC_IDRPQ_OFFSET(n) (0x620 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_IDRPQ0_OFFSET 0x620 /* Interrupt Disable Register Priority Queue 0 */ #define SAM_GMAC_IDRPQ1_OFFSET 0x624 /* Interrupt Disable Register Priority Queue 1 */ #define SAM_GMAC_IDRPQ2_OFFSET 0x628 /* Interrupt Disable Register Priority Queue 2 */ @@ -219,7 +240,9 @@ #define SAM_GMAC_IDRPQ4_OFFSET 0x630 /* Interrupt Disable Register Priority Queue 4 */ #define SAM_GMAC_IDRPQ5_OFFSET 0x630 /* Interrupt Disable Register Priority Queue 5 */ #define SAM_GMAC_IDRPQ6_OFFSET 0x638 /* Interrupt Disable Register Priority Queue 6 */ + #define SAM_GMAC_IMRPQ_OFFSET(n) (0x640 + ((n) << 2)) /* n=0..6 */ + #define SAM_GMAC_IMRPQ0_OFFSET 0x640 /* Interrupt Mask Register Priority Queue 0 */ #define SAM_GMAC_IMRPQ1_OFFSET 0x644 /* Interrupt Mask Register Priority Queue 1 */ #define SAM_GMAC_IMRPQ2_OFFSET 0x648 /* Interrupt Mask Register Priority Queue 2 */ @@ -228,7 +251,7 @@ #define SAM_GMAC_IMRPQ5_OFFSET 0x654 /* Interrupt Mask Register Priority Queue 5 */ #define SAM_GMAC_IMRPQ6_OFFSET 0x658 /* Interrupt Mask Register Priority Queue 6 */ -/* GMAC Register Addresses *********************************************************/ +/* GMAC Register Addresses **************************************************/ #define SAM_GMAC_NCR (SAM_GMAC_BASE+SAM_GMAC_NCR_OFFSET) #define SAM_GMAC_NCFGR (SAM_GMAC_BASE+SAM_GMAC_NCFGR_OFFSET) @@ -421,7 +444,7 @@ #define SAM_GMAC_IMRPQ5 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ5_OFFSET) #define SAM_GMAC_IMRPQ6 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ6_OFFSET) -/* GMAC Register Bit Definitions ***************************************************/ +/* GMAC Register Bit Definitions ********************************************/ /* Network Control Register */ @@ -468,10 +491,12 @@ # define GMAC_NCFGR_CLK_DIV48 (3 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */ # define GMAC_NCFGR_CLK_DIV64 (4 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */ # define GMAC_NCFGR_CLK_DIV96 (5 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */ + #define GMAC_NCFGR_DBW_SHIFT (21) /* Bits 21-22: Data Bus Width */ #define GMAC_NCFGR_DBW_MASK (3 << GMAC_NCFGR_DBW_SHIFT) # define GMAC_NCFGR_DBW_32 (0 << GMAC_NCFGR_DBW_SHIFT) /* 32-bit data bus width */ # define GMAC_NCFGR_DBW_64 (1 << GMAC_NCFGR_DBW_SHIFT) /* 64-bit data bus width */ + #define GMAC_NCFGR_DCPF (1 << 23) /* Bit 23: Disable Copy of Pause Frames */ #define GMAC_NCFGR_RXCOEN (1 << 24) /* Bit 24: Receive Checksum Offload Enable */ #define GMAC_NCFGR_EFRHD (1 << 25) /* Bit 25: Enable Frames Received in Half Duplex */ @@ -497,6 +522,7 @@ # define GMAC_DCFGR_FBLDO_INCR4 (4 << GMAC_DCFGR_FBLDO_SHIFT) /* 001xx: Attempt to use INCR4 AHB bursts */ # define GMAC_DCFGR_FBLDO_INCR8 (8 << GMAC_DCFGR_FBLDO_SHIFT) /* 01xxx: Attempt to use INCR8 AHB bursts */ # define GMAC_DCFGR_FBLDO_INCR16 (16 << GMAC_DCFGR_FBLDO_SHIFT) /* 1xxxx: Attempt to use INCR16 AHB bursts */ + #define GMAC_DCFGR_ESMA (1 << 6) /* Bit 6: Endian Swap Mode Enable for Management Descriptor Accesses */ #define GMAC_DCFGR_ESPA (1 << 7) /* Bit 7: Endian Swap Mode Enable for Packet Data Accesses */ #define GMAC_DCFGR_RXBMS_SHIFT (8) /* Bits 8-9: Receiver Packet Buffer Memory Size Select */ @@ -505,6 +531,7 @@ # define GMAC_DCFGR_RXBMS_QTR (1 << GMAC_DCFGR_RXBMS_SHIFT) /* 1Kbyte Memory Size */ # define GMAC_DCFGR_RXBMS_HALF (2 << GMAC_DCFGR_RXBMS_SHIFT) /* 2 Kbytes Memory Size */ # define GMAC_DCFGR_RXBMS_FULL (3 << GMAC_DCFGR_RXBMS_SHIFT) /* 4 Kbytes Memory Size */ + #define GMAC_DCFGR_TXPBMS (1 << 10) /* Bit 10: Transmitter Packet Buffer Memory Size Select */ #define GMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */ #define GMAC_DCFGR_DRBS_SHIFT (16) /* Bits 16-23: DMA Receive Buffer Size */ @@ -539,7 +566,9 @@ #define GMAC_RSR_RXOVR (1 << 2) /* Bit 2: Receive Overrun */ #define GMAC_RSR_HNO (1 << 3) /* Bit 3: HRESP Not OK */ -/* Interrupt Status Register, Interrupt Enable Register, Interrupt Disable Register */ +/* Interrupt Status Register, Interrupt Enable Register, + * Interrupt Disable Register + */ #define GMAC_INT_MFS (1 << 0) /* Bit 0: Management Frame Sent */ #define GMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */ @@ -613,24 +642,29 @@ #define GMAC_RPSF_ENRXP (1 << 31) /* Bit 31: Enable RX Partial Store and Forward Operation */ /* Hash Register Bottom [31:0] (32-bit value) */ + /* Hash Register Top [63:32] (32-bit value) */ /* Specific Address 1 Bottom [31:0] Register (32-bit value) */ + /* Specific Address 1 Top [47:32] Register */ #define GMAC_SAT1_MASK (0x0000ffff) /* Bits 0-15: Specific Address 1 [47:32] */ /* Specific Address 2 Bottom [31:0] Register (32-bit value) */ + /* Specific Address 2 Top [47:32] Register */ #define GMAC_SAT2_MASK (0x0000ffff) /* Bits 0-15: Specific Address 2 [47:32] */ /* Specific Address 3 Bottom [31:0] Register (32-bit value) */ + /* Specific Address 3 Top [47:32] Register */ #define GMAC_SAT3_MASK (0x0000ffff) /* Bits 0-15: Specific Address 3 [47:32] */ /* Specific Address 4 Bottom [31:0] Register (32-bit value) */ + /* Specific Address 4 Top [47:32] Register */ #define GMAC_SAT4_MASK (0x0000ffff) /* Bits 0-15: Specific Address 4 [47:32] */ @@ -679,17 +713,21 @@ #define GMAC_TPFCP_PQ_MASK (0xff << GMAC_TPFCP_PQ_SHIFT) /* Specific Address 1 Mask Bottom [31:0] Register (32-bit mask) */ + /* Specific Address 1 Mask Top [47:32] Register */ #define GMAC_SAMT1_MASK (0x0000ffff) /* Bits 0-15: Specific Address 1 Mask [47:32] */ /* Octets Transmitted [31:0] Register (32-bit value) */ + /* Octets Transmitted [47:32] Register */ #define GMAC_OTHI_MASK (0x0000ffff) /* Bits 0-15: Transmitted Octets [47:32] */ /* Frames Transmitted Register (32-bit value) */ + /* Broadcast Frames Transmitted Register (32-bit value) */ + /* Multicast Frames Transmitted Register (32-bit value) */ /* Pause Frames Transmitted Register */ @@ -697,11 +735,17 @@ #define GMAC_PFT_MASK (0x0000ffff) /* Bits 0-15: Pause Frames Transmitted */ /* 64 Byte Frames Transmitted Register (32-bit value) */ + /* 65 to 127 Byte Frames Transmitted Register (32-bit value) */ + /* 128 to 255 Byte Frames Transmitted Register (32-bit value) */ + /* 256 to 511 Byte Frames Transmitted Register (32-bit value) */ + /* 512 to 1023 Byte Frames Transmitted Register (32-bit value) */ + /* 1024 to 1518 Byte Frames Transmitted Register (32-bit value) */ + /* Greater Than 1518 Byte Frames Transmitted Register (32-bit value) */ /* Transmit Under Runs Register */ @@ -733,23 +777,33 @@ #define GMAC_CSE_MASK (0x000003ff) /* Bits 0-9: Carrier Sense Error */ /* Octets Received [31:0] Received (32-bit value) */ + /* Octets Received [47:32] Received */ #define GMAC_ORHI_MASK (0x0000ffff) /* Bits 0-15: Received Octets [47:32] */ /* Frames Received Register (32-bit value) */ + /* Broadcast Frames Received Register (32-bit value) */ + /* Multicast Frames Received Register (32-bit value) */ + /* Pause Frames Received Register */ #define GMAC_PFR_MASK (0x0000ffff) /* Bits 0-15: Pause Frames Received */ /* 64 Byte Frames Received Register (32-bit value) */ + /* 65 to 127 Byte Frames Received Register (32-bit value) */ + /* 128 to 255 Byte Frames Received Register (32-bit value) */ + /* 256 to 511Byte Frames Received Register (32-bit value) */ + /* 512 to 1023 Byte Frames Received Register (32-bit value) */ + /* 1024 to 1518 Byte Frames Received Register (32-bit value) */ + /* 1519 to Maximum Byte Frames Received Register (32-bit value) */ /* Undersize Frames Received Register */ @@ -801,11 +855,13 @@ #define GMAC_UCE_MASK (0x000000ff) /* Bits 0-7: UDP Header Checksum Errors */ /* 1588 Timer Sync Strobe Seconds Register (32-bit value) */ + /* 1588 Timer Sync Strobe Nanoseconds Register */ #define GMAC_TSSN_MASK (0x3fffffff) /* Bits 0-29: Value Timer Nanoseconds Register Capture */ /* 1588 Timer Seconds Register (32-bit value) */ + /* 1588 Timer Nanoseconds Register */ #define GMAC_TN_MASK (0x3fffffff) /* Bits 0-29: Timer Count in Nanoseconds */ @@ -829,21 +885,25 @@ # define GMAC_TI_NIT(n) ((uint32_t)(n) << GMAC_TI_NIT_SHIFT) /* PTP Event Frame Transmitted Seconds (32-bit value) */ + /* PTP Event Frame Transmitted Nanoseconds */ #define GMAC_EFTN_MASK (0x3fffffff) /* Bits 0-29: Register Update */ /* PTP Event Frame Received Seconds (32-bit value) */ + /* PTP Event Frame Received Nanoseconds */ #define GMAC_EFRN_MASK (0x3fffffff) /* Bits 0-29: Register Update */ /* PTP Peer Event Frame Transmitted Seconds (32-bit value) */ + /* PTP Peer Event Frame Transmitted Nanoseconds */ #define GMAC_PEFTN_MASK (0x3fffffff) /* Bits 0-29: Register Update */ /* PTP Peer Event Frame Received Seconds (32-bit value) */ + /* PTP Peer Event Frame Received Nanoseconds */ #define GMAC_PEFRS_MASK (0x3fffffff) /* Bits 0-29: Register Update */ @@ -855,15 +915,15 @@ * * Use these definitions: * - * GMAC_INT_RCOMP Bit 1: Receive Complete - * GMAC_INT_RXUBR Bit 2: Receive Used Bit Read - * GMAC_INT_RLEX Bit 5: Retry Limit Exceeded or - * Late Collision - * GMAC_INT_TFC Bit 6: Transmit Frame Corruption - * due to AHB error - * GMAC_INT_TCOMP Bit 7: Transmit Complete - * GMAC_INT_ROVR Bit 10: Receive Overrun - * GMAC_INT_HRESP Bit 11: HRESP not OK + * GMAC_INT_RCOMP Bit 1: Receive Complete + * GMAC_INT_RXUBR Bit 2: Receive Used Bit Read + * GMAC_INT_RLEX Bit 5: Retry Limit Exceeded or + * Late Collision + * GMAC_INT_TFC Bit 6: Transmit Frame Corruption + * due to AHB error + * GMAC_INT_TCOMP Bit 7: Transmit Complete + * GMAC_INT_ROVR Bit 10: Receive Overrun + * GMAC_INT_HRESP Bit 11: HRESP not OK */ /* Transmit Buffer Queue Base Address Priority Queue 0-6 */ @@ -902,12 +962,12 @@ # define GMAC_ST2RPQ0_VLANP(n) ((uint32_t)(n) << GMAC_ST2RPQ0_VLANP_SHIFT) #define GMAC_ST2RPQ0_VLANE (1 << 8) /* Bit 8: VLAN Enable */ -/* Descriptors **********************************************************************/ +/* Descriptors **************************************************************/ /* Receive buffer descriptor: Address word */ -#define GMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=GMAC owns */ -#define GMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ +#define GMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=GMAC owns */ +#define GMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ #define GMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */ /* Receive buffer descriptor: Control word */ @@ -924,18 +984,21 @@ #define GMACRXD_STA_VLPRIO_MASK (7 << GMACRXD_STA_VLANPRIO_SHIFT) #define GMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */ #define GMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */ -#define GMACRXD_STA_TYPID_SHIFT (22) /* Bits 22-23: Type ID register match */ + +#define GMACRXD_STA_TYPID_SHIFT (22) /* Bits 22-23: Type ID register match */ #define GMACRXD_STA_TYPID_MASK (3 << GMACRXD_STA_TYPID_SHIFT) # define GMACRXD_STA_TYPID1 (0 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 1 match */ # define GMACRXD_STA_TYPID2 (1 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 2 match */ # define GMACRXD_STA_TYPID3 (2 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 3 match */ # define GMACRXD_STA_TYPID4 (3 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 4 match */ + #define GMACRXD_STA_SNAP_SHIFT (22) /* Bits 22-23: Specific Address Register match */ #define GMACRXD_STA_SNAP_MASK (3 << GMACRXD_STA_SNAP_SHIFT) # define GMACRXD_STA_SNAP_NOCHK (0 << GMACRXD_STA_SNAP_SHIFT) /* Checksum not checked */ # define GMACRXD_STA_SNAP_IPCHK (1 << GMACRXD_STA_SNAP_SHIFT) /* IP header checksum checked */ # define GMACRXD_STA_SNAP_TCPCHK (2 << GMACRXD_STA_SNAP_SHIFT) /* IP header and TCP checksum checked */ # define GMACRXD_STA_SNAP_UDPCHK (3 << GMACRXD_STA_SNAP_SHIFT) /* IP header and UDP checksum checked */ + #define GMACRXD_STA_TYPID (1 << 24) /* Bit 24: Type ID match found */ #define GMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */ #define GMACRXD_STA_ADDR_SHIFT (25) /* Bits 25-26: Specific Address Register match */ @@ -944,6 +1007,7 @@ # define GMACRXD_STA_ADDR2_MATCH (1 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ # define GMACRXD_STA_ADDR3_MATCH (2 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ # define GMACRXD_STA_ADDR4_MATCH (3 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ + #define GMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific Address Register match found */ /* Bit 28: Reserved */ #define GMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */ @@ -970,6 +1034,7 @@ # define GMACTXD_STA_CKERR_FRAG (5 << GMACTXD_STA_CKERR_SHIFT) /* Bad packet fragmentation */ # define GMACTXD_STA_CKERR_PROTO (6 << GMACTXD_STA_CKERR_SHIFT) /* Not TCP or UDP */ # define GMACTXD_STA_CKERR_END (7 << GMACTXD_STA_CKERR_SHIFT) /* Premature end of packet */ + /* Bits 23-25: Reserved */ #define GMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision */ #define GMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit Frame Corruption due to AHB error */ @@ -978,9 +1043,10 @@ #define GMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */ #define GMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the GMAC to read from buffer */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* Receive buffer descriptor */ struct gmac_rxdesc_s diff --git a/arch/arm/src/samd5e5/hardware/sam_i2c_master.h b/arch/arm/src/samd5e5/hardware/sam_i2c_master.h index 84a3e9c33aa..f836d883bce 100644 --- a/arch/arm/src/samd5e5/hardware/sam_i2c_master.h +++ b/arch/arm/src/samd5e5/hardware/sam_i2c_master.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_i2c_master.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_MASTER_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_MASTER_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* I2C register offsets *********************************************************************/ +/* I2C register offsets *****************************************************/ #define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -48,7 +48,7 @@ #define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */ #define SAM_I2C_DBGCTRL_OFFSET 0x0030 /* Debug control register */ -/* I2C register addresses *******************************************************************/ +/* I2C register addresses ***************************************************/ #define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE + SAM_I2C_CTRLA_OFFSET) #define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE + SAM_I2C_CTRLB_OFFSET) @@ -154,7 +154,7 @@ #define SAM_I2C7_DATA (SAM_SERCOM7_BASE + SAM_I2C_DATA_OFFSET) #define SAM_I2C7_DBGCTRL (SAM_SERCOM7_BASE + SAM_I2C_DBGCTRL_OFFSET) -/* I2C register bit definitions *************************************************************/ +/* I2C register bit definitions *********************************************/ /* Control A register */ @@ -224,8 +224,8 @@ #define I2C_HSBAUDLOW_MASK (0xff << I2C_HSBAUDLOW_SHIFT) # define I2C_HSBAUDLOW(n) ((uint16)(n) << I2C_HSBAUDLOW_SHIFT) -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define I2C_INT_MB (1 << 0) /* Bit 0: Master on bus interrupt */ @@ -277,16 +277,16 @@ #define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Functions Prototypes - ********************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_MASTER_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h b/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h index 62ddcb20f45..49664d42e4c 100644 --- a/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h +++ b/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_i2c_slave.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_SLAVE_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_SLAVE_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* I2C register offsets *********************************************************************/ +/* I2C register offsets *****************************************************/ #define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -47,7 +47,7 @@ #define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */ #define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */ -/* I2C register addresses *******************************************************************/ +/* I2C register addresses ***************************************************/ #define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE + SAM_I2C_CTRLA_OFFSET) #define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE + SAM_I2C_CTRLB_OFFSET) @@ -145,7 +145,7 @@ #define SAM_I2C7_ADDR (SAM_SERCOM7_BASE + SAM_I2C_ADDR_OFFSET) #define SAM_I2C7_DATA (SAM_SERCOM7_BASE + SAM_I2C_DATA_OFFSET) -/* I2C register bit definitions *************************************************************/ +/* I2C register bit definitions *********************************************/ /* Control A register */ @@ -154,22 +154,27 @@ #define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */ #define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT) # define I2C_CTRLA_MODE_SLAVE (4 << I2C_CTRLA_MODE_SHIFT) /* I2C slave mode */ + #define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Pin usage */ + # define I2C_CTRLA_1WIRE (0) /* 4-wire operation disabled */ # define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enabled */ + #define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */ #define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT) # define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */ # define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */ # define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */ # define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */ + #define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */ #define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Trnasfer speed */ #define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT) # define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) fast <=400KHz */ # define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode please (<=1MHz) */ # define I2C_CTRLA_SPEED_HIGH (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4Mhz */ + #define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */ #define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */ @@ -183,12 +188,15 @@ # define I2C_CRLB_AMODE_MASK (0 << I2C_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */ # define I2C_CRLB_AMODE_2ADDRS (1 << I2C_CRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */ # define I2C_CRLB_AMODE_RANGE (2 << I2C_CRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */ + #define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */ #define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT) # define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */ # define I2C_CTRLB_CMD_WAITSTART (2 << I2C_CTRLB_CMD_SHIFT) /* ACK (write) wait for START */ # define I2C_CTRLB_CMD_ACKREAD (3 << I2C_CTRLB_CMD_SHIFT) /* ACK with read (context dependent) */ + #define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */ + # define I2C_CTRLB_ACK (0) /* Send ACK */ # define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */ @@ -198,11 +206,12 @@ #define I2C_CTRLC_SDASETUP_MASK (15 << I2C_CTRLC_SDASETUP_SHIFT) # define I2C_CTRLC_SDASETUP(n) ((uint32_t)(n) << I2C_CTRLC_SDASETUP_SHIFT) #define I2C_CTRLC_DATA32B (1 << 24) /* Bit 24: Data 32 Bit */ + # define I2C_CTRLC_DATA32B_8BIT (0) /* DATA register is 8-bit */ # define I2C_CTRLC_DATA32B_32BIT I2C_CTRLC_DATA32B /* DATA register is 32-bit */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define I2C_INT_PREC (1 << 0) /* Bit 0: Stop received interrupt */ @@ -253,16 +262,16 @@ #define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_SLAVE_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_mclk.h b/arch/arm/src/samd5e5/hardware/sam_mclk.h index 4efc59dbcde..9edc733b2d4 100644 --- a/arch/arm/src/samd5e5/hardware/sam_mclk.h +++ b/arch/arm/src/samd5e5/hardware/sam_mclk.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_mclk.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MCLK_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MCLK_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* MCLK register offsets ************************************************************/ + ****************************************************************************/ + +/* MCLK register offsets ****************************************************/ #define SAM_MCLK_CTRLA_OFFSET 0x0000 /* CTRLA register */ #define SAM_MCLK_INTENCLR_OFFSET 0x0001 /* Interrupt enable clear */ @@ -47,7 +48,7 @@ #define SAM_MCLK_APBCMASK_OFFSET 0x001c /* APBC mask */ #define SAM_MCLK_APBDMASK_OFFSET 0x0020 /* APBD mask */ -/* MCLK register addresses **********************************************************/ +/* MCLK register addresses **************************************************/ #define SAM_MCLK_CTRLA (SAM_MCLK_BASE + SAM_MCLK_CTRLA_OFFSET) #define SAM_MCLK_INTENCLR (SAM_MCLK_BASE + SAM_MCLK_INTENCLR_OFFSET) @@ -61,12 +62,12 @@ #define SAM_MCLK_APBCMASK (SAM_MCLK_BASE + SAM_MCLK_APBCMASK_OFFSET) #define SAM_MCLK_APBDMASK (SAM_MCLK_BASE + SAM_MCLK_APBDMASK_OFFSET) -/* MCLK register bit definitions ****************************************************/ +/* MCLK register bit definitions ********************************************/ /* CTRLA register -- All bits are reserved (?) */ -/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and - * clear. +/* Interrupt enable clear, Interrupt enable set, + * and Interrupt flag status and clear. */ #define MCLK_INT_CKRDY (1 << 0) /* Bit 0: Clock ready */ @@ -86,30 +87,30 @@ /* AHB mask */ -#define MCLK_AHBMASK_HPB0 (1 << 0) /* Bit 0: AHB HPB0 clock for enable */ -#define MCLK_AHBMASK_HPB1 (1 << 1) /* Bit 1: AHB HPB1 clock enable */ -#define MCLK_AHBMASK_HPB2 (1 << 2) /* Bit 2: AHB HPB2 clock enable */ -#define MCLK_AHBMASK_HPB3 (1 << 3) /* Bit 3: AHB HPB3 clock enable */ -#define MCLK_AHBMASK_DSU (1 << 4) /* Bit 4: DSU AHB clock enable */ - /* Bit 5: Reserved */ -#define MCLK_AHBMASK_NVMCTRL (1 << 6) /* Bit 6: NVMCTRL AHB clock enable */ - /* Bit 7: Reserved */ -#define MCLK_AHBMASK_CMCC (1 << 8) /* Bit 8: CMCC AHB Clock Enable */ -#define MCLK_AHBMASK_DMAC (1 << 9) /* Bit 9: DMAC AHB clock enable */ -#define MCLK_AHBMASK_USB (1 << 10) /* Bit 10: USB AHB clock enable */ - /* Bit 11: Reserved */ -#define MCLK_AHBMASK_PAC (1 << 12) /* Bit 12: PAC AHB clock enable */ -#define MCLK_AHBMASK_QSPI (1 << 13) /* Bit 13: QSPI AHB Clock Enable */ -#define MCLK_AHBMASK_GMAC (1 << 14) /* Bit 14: GMAC AHB Clock Enable */ -#define MCLK_AHBMASK_SDHC0 (1 << 15) /* Bit 15: SDHC0 HB Clock Enable */ -#define MCLK_AHBMASK_SDHC1 (1 << 16) /* Bit 16: SDHC1 HB Clock Enable */ -#define MCLK_AHBMASK_CAN0 (1 << 17) /* Bit 17: CAN0 AHB Clock Enable */ -#define MCLK_AHBMASK_CAN1 (1 << 18) /* Bit 18: CAN1 AHB Clock Enable */ -#define MCLK_AHBMASK_ICM (1 << 19) /* Bit 19: ICM AHB Clock Enable */ -#define MCLK_AHBMASK_PUKCC (1 << 20) /* Bit 20: PUKCC AHB Clock Enable */ -#define MCLK_AHBMASK_QSPI2X (1 << 21) /* Bit 21: QSPI_2X AHB Clock Enable */ +#define MCLK_AHBMASK_HPB0 (1 << 0) /* Bit 0: AHB HPB0 clock for enable */ +#define MCLK_AHBMASK_HPB1 (1 << 1) /* Bit 1: AHB HPB1 clock enable */ +#define MCLK_AHBMASK_HPB2 (1 << 2) /* Bit 2: AHB HPB2 clock enable */ +#define MCLK_AHBMASK_HPB3 (1 << 3) /* Bit 3: AHB HPB3 clock enable */ +#define MCLK_AHBMASK_DSU (1 << 4) /* Bit 4: DSU AHB clock enable */ + /* Bit 5: Reserved */ +#define MCLK_AHBMASK_NVMCTRL (1 << 6) /* Bit 6: NVMCTRL AHB clock enable */ + /* Bit 7: Reserved */ +#define MCLK_AHBMASK_CMCC (1 << 8) /* Bit 8: CMCC AHB Clock Enable */ +#define MCLK_AHBMASK_DMAC (1 << 9) /* Bit 9: DMAC AHB clock enable */ +#define MCLK_AHBMASK_USB (1 << 10) /* Bit 10: USB AHB clock enable */ + /* Bit 11: Reserved */ +#define MCLK_AHBMASK_PAC (1 << 12) /* Bit 12: PAC AHB clock enable */ +#define MCLK_AHBMASK_QSPI (1 << 13) /* Bit 13: QSPI AHB Clock Enable */ +#define MCLK_AHBMASK_GMAC (1 << 14) /* Bit 14: GMAC AHB Clock Enable */ +#define MCLK_AHBMASK_SDHC0 (1 << 15) /* Bit 15: SDHC0 HB Clock Enable */ +#define MCLK_AHBMASK_SDHC1 (1 << 16) /* Bit 16: SDHC1 HB Clock Enable */ +#define MCLK_AHBMASK_CAN0 (1 << 17) /* Bit 17: CAN0 AHB Clock Enable */ +#define MCLK_AHBMASK_CAN1 (1 << 18) /* Bit 18: CAN1 AHB Clock Enable */ +#define MCLK_AHBMASK_ICM (1 << 19) /* Bit 19: ICM AHB Clock Enable */ +#define MCLK_AHBMASK_PUKCC (1 << 20) /* Bit 20: PUKCC AHB Clock Enable */ +#define MCLK_AHBMASK_QSPI2X (1 << 21) /* Bit 21: QSPI_2X AHB Clock Enable */ #define MCLK_AHBMASK_NVMCTRL_SMEEPROM (1 << 22) /* Bit 22: NVMCTRL_SMEEPROM AHB Clock Enable */ -#define MCLK_AHBMASK_NVMCTRL_CACHE (1 << 23) /* Bit 23: NVMCTRL_CACHE AHB Clock Enable */ +#define MCLK_AHBMASK_NVMCTRL_CACHE (1 << 23) /* Bit 23: NVMCTRL_CACHE AHB Clock Enable */ /* APBA mask */ @@ -175,16 +176,16 @@ #define MCLK_APBDMASK_I2C (1 << 10) /* Bit 10: I2S APBD clock enable */ #define MCLK_APBDMASK_PCC (1 << 11) /* Bit 11: PCC APBD clock enable */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MCLK_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_memorymap.h b/arch/arm/src/samd5e5/hardware/sam_memorymap.h index 4d459c8441b..78d4e22ff6f 100644 --- a/arch/arm/src/samd5e5/hardware/sam_memorymap.h +++ b/arch/arm/src/samd5e5/hardware/sam_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/samd5e5/hardware/sam_nvmctrl.h b/arch/arm/src/samd5e5/hardware/sam_nvmctrl.h index a720f8b4d36..d973d2106d1 100644 --- a/arch/arm/src/samd5e5/hardware/sam_nvmctrl.h +++ b/arch/arm/src/samd5e5/hardware/sam_nvmctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_nvmctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_NVMCTRL_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_NVMCTRL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* NVMCTRL register offsets *****************************************************************/ +/* NVMCTRL register offsets *************************************************/ #define SAM_NVMCTRL_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_NVMCTRL_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -51,7 +51,7 @@ #define SAM_NVMCTRL_SEECFG_OFFSET 0x002a /* SmartEEPROM configuration register */ #define SAM_NVMCTRL_SEESTAT_OFFSET 0x002c /* SmartEEPROM status register */ -/* NVMCTRL register addresses ***************************************************************/ +/* NVMCTRL register addresses ***********************************************/ #define SAM_NVMCTRL_CTRLA (SAM_NVMCTRL_BASE + SAM_NVMCTRL_CTRLA_OFFSET) #define SAM_NVMCTRL_CTRLB (SAM_NVMCTRL_BASE + SAM_NVMCTRL_CTRLB_OFFSET) @@ -69,7 +69,7 @@ #define SAM_NVMCTRL_SEECFG (SAM_NVMCTRL_BASE + SAM_NVMCTRL_SEECFG_OFFSET) #define SAM_NVMCTRL_SEESTAT (SAM_NVMCTRL_BASE + SAM_NVMCTRL_SEESTAT_OFFSET) -/* NVMCTRL register bit definitions *********************************************************/ +/* NVMCTRL register bit definitions *****************************************/ /* Control A register */ @@ -224,16 +224,16 @@ #define NVMCTRL_SEESTAT_PSZ_MASK (7 << NVMCTRL_SEESTAT_PSZ_SHIFT) # define NVMCTRL_SEESTAT_PSZ(n) ((uint32_t)(n) << NVMCTRL_SEESTAT_PSZ_SHIFT) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Functions Prototypes - ********************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_NVMCTRL_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h b/arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h index 90f9ec12f5f..b09f46e4a63 100644 --- a/arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h +++ b/arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSC32KCTRL_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSC32KCTRL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* OSC32KCTRL register offsets **************************************************************/ + ****************************************************************************/ + +/* OSC32KCTRL register offsets **********************************************/ #define SAM_OSC32KCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */ #define SAM_OSC32KCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */ @@ -44,8 +45,7 @@ #define SAM_OSC32KCTRL_EVCTRL_OFFSET 0x0017 /* Event Control */ #define SAM_OSC32KCTRL_OSCULP32K_OFFSET 0x001c /* 32kHz ultra low power internal oscillator control */ - -/* OSC32KCTRL register addresses ************************************************************/ +/* OSC32KCTRL register addresses ********************************************/ #define SAM_OSC32KCTRL_INTENCLR (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_INTENCLR_OFFSET) #define SAM_OSC32KCTRL_INTENSET (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_INTENSET_OFFSET) @@ -57,10 +57,10 @@ #define SAM_OSC32KCTRL_EVCTRL (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_EVCTRL_OFFSET ) #define SAM_OSC32KCTRL_OSCULP32K (SAM_OSC32KCTRL_BASE + SAM_OSC32KCTRL_OSCULP32K_OFFSET) -/* OSC32KCTRL register bit definitions ******************************************************/ +/* OSC32KCTRL register bit definitions **************************************/ -/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and - * status registers. +/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and + * clear, and status registers. */ #define OSC32KCTRL_INT_XOSC32KRDY (1 << 0) /* Bit 0: XOSC32K ready interrupt */ @@ -87,7 +87,7 @@ #define OSC32KCTRL_XOSC32K_EN1K (1 << 4) /* Bit 4: 1kHz Output enable */ #define OSC32KCTRL_XOSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define OSC32KCTRL_XOSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */ -#define OSC32KCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */ +#define OSC32KCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */ #define OSC32KCTRL_XOSC32K_STARTUP_MASK (7 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) # define OSC32KCTRL_XOSC32K_STARTUP(n) ((n) << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) # define OSC32KCTRL_XOSC32K_STARTUP_63MS (0 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 62.592 msec */ @@ -97,6 +97,7 @@ # define OSC32KCTRL_XOSC32K_STARTUP_2S (4 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 2000.0092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_4S (5 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 4000.092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_8S (6 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 8000.0092 msec */ + #define OSC32KCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */ #define OSC32KCTRL_XOSC32K_GCM_SHIFT (13) /* Bits 13-14: Control Gain Mode */ #define OSC32KCTRL_XOSC32K_GCM_MASK (3 << OSC32KCTRL_XOSC32K_GCM_SHIFT) @@ -122,16 +123,16 @@ # define OSC32KCTRL_OSCULP32K_CALIB(n) ((uint16_t)(n) << OSC32KCTRL_OSCULP32K_CALIB_SHIFT) #define OSC32KCTRL_OSCULP32K_WRTLOCK (1 << 15) /* Bit 15: Write Lock */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSC32KCTRL_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_oscctrl.h b/arch/arm/src/samd5e5/hardware/sam_oscctrl.h index 29b851f5c1f..553dd85c67b 100644 --- a/arch/arm/src/samd5e5/hardware/sam_oscctrl.h +++ b/arch/arm/src/samd5e5/hardware/sam_oscctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_oscctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSCCTRL_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSCCTRL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* OSCCTRL register offsets *****************************************************************/ +/* OSCCTRL register offsets *************************************************/ #define SAM_OSCCTRL_EVCTRL_OFFSET 0x0000 /* Event Control */ #define SAM_OSCCTRL_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear */ @@ -69,7 +69,7 @@ #define SAM_OSCCTRL_DPLL1SYNCBUSY_OFFSET 0x0050 /* DPLL1 synchronization busy */ #define SAM_OSCCTRL_DPLL1STATUS_OFFSET 0x0054 /* DPLL1 status */ -/* OSCCTRL register addresses ***************************************************************/ +/* OSCCTRL register addresses ***********************************************/ #define SAM_OSCCTRL_EVCTRL (SAM_OSCCTRL_BASE + SAM_OSCCTRL_EVCTRL_OFFSET) #define SAM_OSCCTRL_INTENCLR (SAM_OSCCTRL_BASE + SAM_OSCCTRL_INTENCLR_OFFSET) @@ -101,15 +101,15 @@ #define SAM_OSCCTRL_DPLL1SYNCBUSY (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1SYNCBUSY_OFFSET) #define SAM_OSCCTRL_DPLL1STATUS (SAM_OSCCTRL_BASE + SAM_OSCCTRL_DPLL1STATUS_OFFSET) -/* OSCCTRL register bit definitions *********************************************************/ +/* OSCCTRL register bit definitions *****************************************/ /* Event Control */ #define OSCCTRL_EVCTRL_CFDEO0 (1 << 0) /* Bit 0: Clock 0 failure detector event output enable */ #define OSCCTRL_EVCTRL_CFDEO1 (1 << 1) /* Bit 1: Clock 1 failure detector event output enable */ -/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and - * Status registers. +/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and + * clear, and Status registers. */ #define OSCCTRL_INT_XOSCRDY0 (1 << 0) /* Bit 0: XOSC 0 ready interrupt */ @@ -169,6 +169,7 @@ # define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */ # define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */ # define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */ + #define OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT (24) /* Bits 24-27: Clock Failure Detector Prescaler */ #define OSCCTRL_XOSCCTRL_CFDPRESC_MASK (15 << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT) # define OSCCTRL_XOSCCTRL_CFDPRESC(n) ((uint32_t)(n) << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT) @@ -219,7 +220,7 @@ #define OSCCTRL_DFLLSYNC_ENABLE (1 << 1) /* Bit 1: ENABLE Synchronization Busy */ #define OSCCTRL_DFLLSYNC_DFLLCTRLB (1 << 2) /* Bit 2: DFLLCTRLB Synchronization Busy */ #define OSCCTRL_DFLLSYNC_DFLLVAL (1 << 3) /* Bit 3: DFLLVAL Synchronization Busy */ -#define OSCCTRL_DFLLSYNC_DFLLMUL (1 << 4) /* Bit 4: DFLLMUL Synchronization Busy */ +#define OSCCTRL_DFLLSYNC_DFLLMUL (1 << 4) /* Bit 4: DFLLMUL Synchronization Busy */ /* DPLL0/1 control A */ @@ -241,7 +242,7 @@ #define OSCCTRL_DPLLCTRLB_FILTER_SHIFT (0) /* Bits 0-3: Proportional integer filter selection */ #define OSCCTRL_DPLLCTRLB_FILTER_MASK (15 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) # define OSCCTRL_DPLLCTRLB_FILTER(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) - /* PLL BW Damping */ + /* PLL BW Damping */ # define OSCCTRL_DPLLCTRLB_FILTER0 (0 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 0.76 */ # define OSCCTRL_DPLLCTRLB_FILTER1 (1 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 131 kHz 1.08 */ # define OSCCTRL_DPLLCTRLB_FILTER2 (2 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 0.38 */ @@ -258,6 +259,7 @@ # define OSCCTRL_DPLLCTRLB_FILTER13 (13 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 92.7 kHz 1.51 */ # define OSCCTRL_DPLLCTRLB_FILTER14 (14 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 32.8 kHz 0.53 */ # define OSCCTRL_DPLLCTRLB_FILTER15 (15 << OSCCTRL_DPLLCTRLB_FILTER_SHIFT) /* 46.4 kHz 0.75 */ + #define OSCCTRL_DPLLCTRLB_WUF (1 << 4) /* Bit 4: Wake up fast */ #define OSCCTRL_DPLLCTRLB_REFLCK_SHIFT (5) /* Bits 5-7: Reference clock selection */ #define OSCCTRL_DPLLCTRLB_REFLCK_MASK (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) @@ -266,6 +268,7 @@ # define OSCCTRL_DPLLCTRLB_REFLCK_XOSC32 (1 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC32K clock reference (default) */ # define OSCCTRL_DPLLCTRLB_REFLCK_XOSC0 (2 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC0 clock reference */ # define OSCCTRL_DPLLCTRLB_REFLCK_XOSC1 (3 << OSCCTRL_DPLLCTRLB_REFLCK_SHIFT) /* XOSC2 clock reference */ + #define OSCCTRL_DPLLCTRLB_LTIME_SHIFT (8) /* Bits 8-10: Lock time */ #define OSCCTRL_DPLLCTRLB_LTIME_MASK (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) # define OSCCTRL_DPLLCTRLB_LTIME(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) @@ -274,11 +277,12 @@ # define OSCCTRL_DPLLCTRLB_LTIME_900US (5 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 900 us */ # define OSCCTRL_DPLLCTRLB_LTIME_1MS (6 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 1MS */ # define OSCCTRL_DPLLCTRLB_LTIME_1p1MS (7 << OSCCTRL_DPLLCTRLB_LTIME_SHIFT) /* Time-out if no locka within 1.1MS */ + #define OSCCTRL_DPLLCTRLB_LBYPASS (1 << 11) /* Bit 11: Lock bypass */ -#define OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT (12) /* Bits 12-14: Sigma-Delta DCO Filter Selection */ +#define OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT (12) /* Bits 12-14: Sigma-Delta DCO Filter Selection */ #define OSCCTRL_DPLLCTRLB_DCOFILTER_MASK (7 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) # define OSCCTRL_DPLLCTRLB_DCOFILTER(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) - /* Capa pF BW MHz */ + /* Capa pF BW MHz */ # define OSCCTRL_DPLLCTRLB_DCOFILTER0 (0 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 0.5 3.21 */ # define OSCCTRL_DPLLCTRLB_DCOFILTER1 (1 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 1 1.6 */ # define OSCCTRL_DPLLCTRLB_DCOFILTER2 (2 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 1.5 1.1 */ @@ -287,6 +291,7 @@ # define OSCCTRL_DPLLCTRLB_DCOFILTER5 (5 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 3 0.55 */ # define OSCCTRL_DPLLCTRLB_DCOFILTER6 (6 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 3.5 0.45 */ # define OSCCTRL_DPLLCTRLB_DCOFILTER7 (7 << OSCCTRL_DPLLCTRLB_DCOFILTER_SHIFT) /* 4 0.4 */ + #define OSCCTRL_DPLLCTRLB_DCOEN (1 << 15) /* Bit 15: DCO Filter Enable */ #define OSCCTRL_DPLLCTRLB_DIV_SHIFT (16) /* Bits 16-26: Clock divider */ #define OSCCTRL_DPLLCTRLB_DIV_MASK (0x7ff << OSCCTRL_DPLLCTRLB_DIV_SHIFT) @@ -302,16 +307,16 @@ #define OSCCTRL_DPLLSTATUS_LOCK (1 << 0) /* Bit 0: DPLL lock status */ #define OSCCTRL_DPLLSTATUS_CLKRDY (1 << 1) /* Bit 1: Output clock ready */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSCCTRL_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_pac.h b/arch/arm/src/samd5e5/hardware/sam_pac.h index a6db66e8432..49d3fee86fd 100644 --- a/arch/arm/src/samd5e5/hardware/sam_pac.h +++ b/arch/arm/src/samd5e5/hardware/sam_pac.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_pac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PAC_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PAC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* PAC register offsets *********************************************************************/ +/* PAC register offsets *****************************************************/ #define SAM_PAC_WRCTRL_OFFSET 0x0000 /* Write control */ #define SAM_PAC_EVCTRL_OFFSET 0x0004 /* Event control */ @@ -49,7 +49,7 @@ #define SAM_PAC_STATUSC_OFFSET 0x003c /* Write protection status bridge C */ #define SAM_PAC_STATUSD_OFFSET 0x0040 /* Write protection status bridge D */ -/* PAC register addresses *******************************************************************/ +/* PAC register addresses ***************************************************/ #define SAM_PAC_WRCTRL (SAM_PAC_BASE + SAM_PAC_WRCTRL_OFFSET) #define SAM_PAC_EVCTRL (SAM_PAC_BASE + SAM_PAC_EVCTRL_OFFSET) @@ -65,7 +65,7 @@ #define SAM_PAC_STATUSC (SAM_PAC_BASE + SAM_PAC_STATUSC_OFFSET) #define SAM_PAC_STATUSD (SAM_PAC_BASE + SAM_PAC_STATUSD_OFFSET) -/* PAC register bit definitions *************************************************************/ +/* PAC register bit definitions *********************************************/ /* Write control */ @@ -238,16 +238,16 @@ #define SAM_I2S_PERID ((3 << 5) + 10) #define SAM_PCC_PERID ((3 << 5) + 11) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PAC_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_pinmap.h b/arch/arm/src/samd5e5/hardware/sam_pinmap.h index ed064a16aed..51b0a2a6ade 100644 --- a/arch/arm/src/samd5e5/hardware/sam_pinmap.h +++ b/arch/arm/src/samd5e5/hardware/sam_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PINMAP_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/samd5e5/hardware/sam_pm.h b/arch/arm/src/samd5e5/hardware/sam_pm.h index b0a1c793dcc..83296bc0e10 100644 --- a/arch/arm/src/samd5e5/hardware/sam_pm.h +++ b/arch/arm/src/samd5e5/hardware/sam_pm.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_pm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PM_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PM_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* PM register offsets ******************************************************************************/ +/* PM register offsets ******************************************************/ #define SAM_PM_CTRLA_OFFSET 0x0000 /* Control A */ #define SAM_PM_SLEEPCFG_OFFSET 0x0001 /* Sleep configuration */ @@ -44,7 +44,7 @@ #define SAM_PM_HIBCFG_OFFSET 0x0009 /* Hibernate configuration */ #define SAM_PM_BKUPCFG_OFFSET 0x000a /* Backup configuration */ -/* PM register addresses ****************************************************************************/ +/* PM register addresses ****************************************************/ #define SAM_PM_CTRLA (SAM_PM_BASE + SAM_PM_CTRLA_OFFSET) #define SAM_PM_SLEEPCFG (SAM_PM_BASE + SAM_PM_SLEEPCFG_OFFSET) @@ -55,7 +55,7 @@ #define SAM_PM_HIBCFG (SAM_PM_BASE + SAM_PM_HIBCFG_OFFSET) #define SAM_PM_BKUPCFG (SAM_PM_BASE + SAM_PM_BKUPCFG_OFFSET) -/* PM register bit definitions **********************************************************************/ +/* PM register bit definitions **********************************************/ /* Control A register */ @@ -74,7 +74,9 @@ # define PM_SLEEPCFG_MODE_OFF (7 << PM_SLEEPCFG_MODE_SHIFT) /* All power domains are * powered OFF */ -/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */ +/* Interrupt enable clear, Interrupt enable set, + * and Interrupt flag status and clear registers + */ #define PM_INT_SLEEPRDY (1 << 0) /* Bit 0: Sleep mode entry ready interrupt */ @@ -86,6 +88,7 @@ # define PM_STDBYCFG_RAMCFG_PARTIAL (1 << PM_STDBYCFG_RAMCFG_SHIFT) /* PD0 ACTIVE; PD1/2 handled by HW */ # define PM_STDBYCFG_RAMCFG_OFF (2 << PM_STDBYCFG_RAMCFG_SHIFT) /* Only the first 32Kb of system * RAM is retained */ + #define PM_STDBYCFG_FASTWKUP_SHIFT (4) /* Bits 4-5: Fast Wakeup */ #define PM_STDBYCFG_FASTWKUP_MASK (3 << PM_STDBYCFG_FASTWKUP_SHIFT) # define PM_STDBYCFG_FASTWKUP_NO (0 << PM_STDBYCFG_FASTWKUP_SHIFT) /* Disabled */ @@ -101,6 +104,7 @@ # define PM_HIBCFG_RAMCFG_PARTIAL (1 << PM_HIBCFG_RAMCFG_SHIFT) /* PD0 ACTIVE; PD1/2 handled by HW */ # define PM_HIBCFG_RAMCFG_OFF (2 << PM_HIBCFG_RAMCFG_SHIFT) /* Only the first 32Kb of system * RAM is retained */ + #define PM_HIBCFG_BRAMCFG_SHIFT (0) /* Bits 0-1: Backup RAM Configuration */ #define PM_HIBCFG_BRAMCFG_MASK (3 << PM_HIBCFG_BRAMCFG_SHIFT) # define PM_HIBCFG_BRAMCFG_RET (0 << PM_HIBCFG_BRAMCFG_SHIFT) /* System RAM is retained */ @@ -117,16 +121,16 @@ # define PM_BKUPCFG_BRAMCFG_OFF (2 << PM_BKUPCFG_BRAMCFG_SHIFT) /* Only the first 32Kb of system * RAM is retained */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** - * Public Functions - ****************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PM_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_port.h b/arch/arm/src/samd5e5/hardware/sam_port.h index 8de53cb4e6d..65ea0e89ce6 100644 --- a/arch/arm/src/samd5e5/hardware/sam_port.h +++ b/arch/arm/src/samd5e5/hardware/sam_port.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_port.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PORT_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PORT_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* PORT register offsets ********************************************************************/ +/* PORT register offsets ****************************************************/ #define SAM_PORTA (0) #define SAM_PORTB (1) @@ -112,7 +112,7 @@ # define SAM_PORT_PINCFG30_OFFSET 0x005e /* Pin configuration register 30 */ # define SAM_PORT_PINCFG31_OFFSET 0x005f /* Pin configuration register 31 */ -/* PORT register addresses ******************************************************************/ +/* PORT register addresses **************************************************/ #define SAM_PORTN_BASE(n) (SAM_PORT_BASE + SAM_PORTN_OFFSET(n)) # define SAM_PORTA_BASE (SAM_PORT_BASE + SAM_PORTA_OFFSET) @@ -377,16 +377,16 @@ # define SAM_PORTD_PINCFG30 (SAM_PORTD_BASE + SAM_PORT_PINCFG30_OFFSET) # define SAM_PORTD_PINCFG31 (SAM_PORTD_BASE + SAM_PORT_PINCFG31_OFFSET) -/* PORT register bit definitions ************************************************************/ +/* PORT register bit definitions ********************************************/ -/* Data direction, data direction clear, data direction set, and data direction toggle - * registers +/* Data direction, data direction clear, data direction set, and data + * direction toggle registers */ #define PORT_DIR(n) (1 << n) /* Port data n, direction, n=0-31 */ -/* Data output value, data output value clear, data output value set, and data output - * value toggle registers +/* Data output value, data output value clear, data output value set, and + * data output value toggle registers */ #define PORT_OUT(n) (1 << n) /* Port data n output value, n=0-31 */ @@ -472,6 +472,7 @@ # define PORT_PMUXE_PERIPHL (11 << PORT_PMUXE_SHIFT) /* Peripheral function L */ # define PORT_PMUXE_PERIPHM (12 << PORT_PMUXE_SHIFT) /* Peripheral function M */ # define PORT_PMUXE_PERIPHN (13 << PORT_PMUXE_SHIFT) /* Peripheral function N */ + #define PORT_PMUXO_SHIFT (4) /* Bits 4-7: Peripheral multiplexing odd */ #define PORT_PMUXO_MASK (15 << PORT_PMUXO_SHIFT) # define PORT_PMUXO_PERIPHA (0 << PORT_PMUXO_SHIFT) /* Peripheral function A */ @@ -496,16 +497,16 @@ #define PORT_PINCFG_PULLEN (1 << 2) /* Bit 2: Pull Enable */ #define PORT_PINCFG_DRVSTR (1 << 6) /* Bit 6: Output Driver Strength Selection */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PORT_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_rstc.h b/arch/arm/src/samd5e5/hardware/sam_rstc.h index d0c48be7425..2019991f32c 100644 --- a/arch/arm/src/samd5e5/hardware/sam_rstc.h +++ b/arch/arm/src/samd5e5/hardware/sam_rstc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_rstc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,33 +16,34 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_RSTC_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_RSTC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* RSTC register offsets ********************************************************************/ + ****************************************************************************/ + +/* RSTC register offsets ****************************************************/ #define SAM_RSTC_RCAUSE_OFFSET 0x0000 /* Reset cause */ #define SAM_RSTC_BKUPEXIT_OFFSET 0x0002 /* Backup exit source */ -/* RSTC register addresses ******************************************************************/ +/* RSTC register addresses **************************************************/ #define SAM_RSTC_RCAUSE (SAM_RSTC_BASE + SAM_RSTC_RCAUSE_OFFSET) #define SAM_RSTC_BKUPEXIT (SAM_RSTC_BASE + SAM_RSTC_BKUPEXIT_OFFSET) -/* RSTC register bit definitions ************************************************************/ +/* RSTC register bit definitions ********************************************/ /* Reset cause */ @@ -61,16 +62,16 @@ #define RSTC_BKUPEXIT_BBPS (1 << 2) /* Bit 2: Battery backup power switch */ #define RSTC_BKUPEXIT_HIB (1 << 7) /* Bit 7: Hibernate */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_RSTC_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_spi.h b/arch/arm/src/samd5e5/hardware/sam_spi.h index 5488a354817..ffef303d8bc 100644 --- a/arch/arm/src/samd5e5/hardware/sam_spi.h +++ b/arch/arm/src/samd5e5/hardware/sam_spi.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SPI_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SPI_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* SPI register offsets *********************************************************************/ +/* SPI register offsets *****************************************************/ #define SAM_SPI_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_SPI_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -49,7 +49,7 @@ #define SAM_SPI_DATA_OFFSET 0x0028 /* Data register */ #define SAM_SPI_DBGCTRL_OFFSET 0x0030 /* Debug control register */ -/* SPI register addresses *******************************************************************/ +/* SPI register addresses ***************************************************/ #define SAM_SPI0_CTRLA (SAM_SERCOM0_BASE + SAM_SPI_CTRLA_OFFSET) #define SAM_SPI0_CTRLB (SAM_SERCOM0_BASE + SAM_SPI_CTRLB_OFFSET) @@ -163,7 +163,7 @@ #define SAM_SPI7_DATA (SAM_SERCOM7_BASE + SAM_SPI_DATA_OFFSET) #define SAM_SPI7_DBGCTRL (SAM_SERCOM7_BASE + SAM_SPI_DBGCTRL_OFFSET) -/* SPI register bit definitions *************************************************************/ +/* SPI register bit definitions *********************************************/ /* Control A register */ @@ -173,22 +173,27 @@ #define SPI_CTRLA_MODE_MASK (7 << SPI_CTRLA_MODE_SHIFT) # define SPI_CTRLA_MODE_SLAVE (2 << SPI_CTRLA_MODE_SHIFT) /* SPI slave operation */ # define SPI_CTRLA_MODE_MASTER (3 << SPI_CTRLA_MODE_SHIFT) /* SPI master operation */ + #define SPI_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define SPI_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ #define SPI_CTRLA_DOPO_SHIFT (16) /* Bit 16-17: Data out pinout */ + #define SPI_CTRLA_DOPO_MASK (3 << SPI_CTRLA_DOPO_SHIFT) /* Bit 16-17: Data out pinout */ # define SPI_CTRLA_DOPO_DOPAD012 (0 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD1 SS=PAD2 */ # define SPI_CTRLA_DOPO_DOPAD312 (2 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD3 SCK=PAD1 SS=PAD2 */ + #define SPI_CTRLA_DIPO_SHIFT (20) /* Bits 20-21: Data in pinout */ #define SPI_CTRLA_DIPO_MASK (3 << SPI_CTRLA_DIPO_SHIFT) # define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD0 for DI */ # define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD1 for DI */ # define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD2 for DI */ # define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD3 for DI */ + #define SPI_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */ #define SPI_CTRLA_FORM_MASK (7 << SPI_CTRLA_FORM_SHIFT) # define SPI_CTRLA_FORM_SPI (0 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (no address) */ # define SPI_CTRLA_FORM_ADDR (2 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (w/address) */ + #define SPI_CTRLA_CPHA (1 << 28) /* Bit 28: Clock phase */ #define SPI_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */ #define SPI_CTRLA_DORD (1 << 30) /* Bit 30: Data order */ @@ -201,6 +206,7 @@ #define SPI_CTRLB_CHSIZE_MASK (7 << SPI_CTRLB_CHSIZE_SHIFT) # define SPI_CTRLB_CHSIZE_8BITS (0 << SPI_CTRLB_CHSIZE_SHIFT) /* 8 bits */ # define SPI_CTRLB_CHSIZE_9BITS (1 << SPI_CTRLB_CHSIZE_SHIFT) /* 9 bits */ + #define SPI_CTRLB_PLOADEN (1 << 6) /* Bit 6: Slave Data Preload Enable */ #define SPI_CTRLB_SSDE (1 << 9) /* Bit 9: Slave select low detect enable */ #define SPI_CTRLB_MSSEN (1 << 13) /* Bit 13: Master slave select enable */ @@ -209,22 +215,24 @@ # define SPI_CTRLB_AMODE_ADDRMASK (0 << SPI_CTRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */ # define SPI_CTRLB_AMODE_2ADDRS (1 << SPI_CTRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */ # define SPI_CTRLB_AMODE_RANGE (2 << SPI_CTRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */ + #define SPI_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */ /* Control C register */ # -#define SPI_CTRLC_ICSPACE_SHIFT (0) /* Bits 0-2: Inter-Character Spacing */ +#define SPI_CTRLC_ICSPACE_SHIFT (0) /* Bits 0-2: Inter-Character Spacing */ #define SPI_CTRLC_ICSPACE_MASK (7 << SPI_CTRLC_ICSPACE_SHIFT) # define SPI_CTRLC_ICSPACE_DISABLE (0 << SPI_CTRLC_ICSPACE_SHIFT) # define SPI_CTRLC_ICSPACE(n) ((uint32_t)(n) << SPI_CTRLC_ICSPACE_SHIFT) -#define SPI_CTRLC_DATA32B (1 << 24 /* Bit 24: Data 32 Bit */ +#define SPI_CTRLC_DATA32B (1 << 24 /* Bit 24: Data 32 Bit */ + # define SPI_CTRLC_DATA32B_8BIT (0) /* DATA register is 8-bit */ # define SPI_CTRLC_DATA32B_32BIT SPI_CTRLC_DATA32B /* DATA register is 32-bit */ /* Baud register (8-bit baud value) */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define SPI_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */ @@ -275,16 +283,16 @@ #define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SPI_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_supc.h b/arch/arm/src/samd5e5/hardware/sam_supc.h index d2a1311e636..99dbb58ab56 100644 --- a/arch/arm/src/samd5e5/hardware/sam_supc.h +++ b/arch/arm/src/samd5e5/hardware/sam_supc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_supc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SUPC_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SUPC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* SUPC register offsets *********************************************************************/ + ****************************************************************************/ + +/* SUPC register offsets ****************************************************/ #define SAM_SUPC_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */ #define SAM_SUPC_INTENSET_OFFSET 0x0004 /* Interrupt enable set */ @@ -46,7 +47,7 @@ #define SAM_SUPC_BKOUT_OFFSET 0x0024 /* Backup output control */ #define SAM_SUPC_BKIN_OFFSET 0x0028 /* Backup input value */ -/* SUPC register addresses *******************************************************************/ +/* SUPC register addresses **************************************************/ #define SAM_SUPC_INTENCLR (SAM_SUPC_BASE + SAM_SUPC_INTENCLR_OFFSET) #define SAM_SUPC_INTENSET (SAM_SUPC_BASE + SAM_SUPC_INTENSET_OFFSET) @@ -60,10 +61,10 @@ #define SAM_SUPC_BKOUT (SAM_SUPC_BASE + SAM_SUPC_BKOUT_OFFSET) #define SAM_SUPC_BKIN (SAM_SUPC_BASE + SAM_SUPC_BKIN_OFFSET) -/* SUPC register bit definitions *************************************************************/ +/* SUPC register bit definitions ********************************************/ -/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and - * Status registers. +/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and + * clear, and Status registers. */ #define SUPC_INT_BOD33RDY (1 << 0) /* Bit 0: BOD33 ready interrupt */ @@ -87,6 +88,7 @@ # define SUPC_BOD33_ACTION_RESET (1 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 generates reset */ # define SUPC_BOD33_ACTION_INTR (2 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 generates interrupt */ # define SUPC_BOD33_ACTION_BKUP (3 << SUPC_BOD33_ACTION_SHIFT) /* BOD33 backup sleep mode */ + #define SUPC_BOD33_STDBYCFG (1 << 4) /* Bit 4: BOD33 configuration in standby sleep mode */ #define SUPC_BOD33_RUNSTDBY (1 << 5) /* Bit 5: Run in standby */ #define SUPC_BOD33_RUNHIB (1 << 6) /* Bit 6: BOD33 configuration in hibernate sleep mode */ @@ -106,6 +108,7 @@ # define SUPC_BOD33_PSEL_DIV64 (5 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 64 */ # define SUPC_BOD33_PSEL_DIV128 (6 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 128 */ # define SUPC_BOD33_PSEL_DIV256 (7 << SUPC_BOD33_PSEL_SHIFT) /* Divide clock by 256 */ + #define SUPC_BOD33_LEVEL_SHIFT (16) /* Bits 16-23: BOD33 threshold level VDD */ #define SUPC_BOD33_LEVEL_MASK (0xff << SUPC_BOD33_LEVEL_SHIFT) # define SUPC_BOD33_LEVEL(n) ((uint32_t)(n) << SUPC_BOD33_LEVEL_SHIFT) @@ -123,6 +126,7 @@ # define SUPC_BOD12_ACTION_NONE (0 << SUPC_BOD12_ACTION_SHIFT) /* No action */ # define SUPC_BOD12_ACTION_RESET (1 << SUPC_BOD12_ACTION_SHIFT) /* BOD12 generates reset */ # define SUPC_BOD12_ACTION_INTR (2 << SUPC_BOD12_ACTION_SHIFT) /* BOD12 generates interrupt */ + #define SUPC_BOD12_STDBYCFG (1 << 5) /* Bit 5: BOD12 configuration in standby sleep mode */ #define SUPC_BOD12_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define SUPC_BOD12_ACTCFG (1 << 8) /* Bit 8: BOD12 configuration in active sleep */ @@ -201,16 +205,16 @@ # define SUPC_BKIN_OUT0 (1 << SUPC_BKIN_SHIFT) /* Input value of OUT[0] pin */ # define SUPC_BKIN_OUT1 (2 << SUPC_BKIN_SHIFT) /* Input value of OUT[1] pin */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SUPC_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_trng.h b/arch/arm/src/samd5e5/hardware/sam_trng.h index dc85c1df0a1..6ab881293a6 100644 --- a/arch/arm/src/samd5e5/hardware/sam_trng.h +++ b/arch/arm/src/samd5e5/hardware/sam_trng.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_trng.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_TRNG_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_TRNG_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* TRNG register offsets ********************************************************************/ +/* TRNG register offsets ****************************************************/ #define SAM_TRNG_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_TRNG_EVCTRL_OFFSET 0x0004 /* Event control register */ @@ -42,7 +42,7 @@ #define SAM_TRNG_INTFLAG_OFFSET 0x000a /* Interrupt flag and status clear register */ #define SAM_TRNG_DATA_OFFSET 0x0020 /* Output data register */ -/* TRNG register addresses ******************************************************************/ +/* TRNG register addresses **************************************************/ #define SAM_TRNG_CTRLA (SAM_TRNG_BASE+SAM_TRNG_CTRLA_OFFSET) #define SAM_TRNG_EVCTRL (SAM_TRNG_BASE+SAM_TRNG_EVCTRL_OFFSET) @@ -51,31 +51,31 @@ #define SAM_TRNG_INTFLAG (SAM_TRNG_BASE+SAM_TRNG_INTFLAG_OFFSET) #define SAM_TRNG_DATA (SAM_TRNG_BASE+SAM_TRNG_DATA_OFFSET) -/* TRNG register bit definitions ************************************************************/ +/* TRNG register bit definitions ********************************************/ /* Control register */ #define TRNG_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */ #define TRNG_CTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ -/* Event control register, Interrupt enable clear, interrupt enable set register, interrupt - * flag status registers. +/* Event control register, Interrupt enable clear, interrupt enable set + * register, interrupt flag status registers. */ #define TRNG_EVCTRL_DATARDYEO (1 << 0) /* Bit 0: Data ready event output */ /* Data register (32-bit data) */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_TRNG_H */ diff --git a/arch/arm/src/samd5e5/hardware/sam_usart.h b/arch/arm/src/samd5e5/hardware/sam_usart.h index 3f03a1c08f6..727a696b4c3 100644 --- a/arch/arm/src/samd5e5/hardware/sam_usart.h +++ b/arch/arm/src/samd5e5/hardware/sam_usart.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/sam_usart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USART_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USART_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* USART register offsets *******************************************************************/ +/* USART register offsets ***************************************************/ #define SAM_USART_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_USART_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -50,7 +50,7 @@ #define SAM_USART_DATA_OFFSET 0x0028 /* Data register */ #define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */ -/* USART register addresses *****************************************************************/ +/* USART register addresses *************************************************/ #define SAM_USART0_CTRLA (SAM_SERCOM0_BASE + SAM_USART_CTRLA_OFFSET) #define SAM_USART0_CTRLB (SAM_SERCOM0_BASE + SAM_USART_CTRLB_OFFSET) @@ -172,7 +172,7 @@ #define SAM_USART7_DATA (SAM_SERCOM7_BASE + SAM_USART_DATA_OFFSET) #define SAM_USART7_DBGCTRL (SAM_SERCOM7_BASE + SAM_USART_DBGCTRL_OFFSET) -/* USART register bit definitions ***********************************************************/ +/* USART register bit definitions *******************************************/ /* Control A register */ @@ -184,6 +184,7 @@ * clock */ # define USART_CTRLA_MODE_INTUSART (1 << USART_CTRLA_MODE_SHIFT) /* USART with internal * clock */ + #define USART_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */ #define USART_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */ #define USART_CTRLA_TXINV (1 << 9) /* Bit 9: Transmit Data Invert */ @@ -200,6 +201,7 @@ * fractional baud */ # define USART_CTRLA_SAMPR_3XA (4 << USART_CTRLA_SAMPR_SHIFT) /* 3x oversampling; * arithmetic baud */ + #define USART_CTRLA_TXPO_SHIFT (16) /* Bits 16-17: Transmit data pinout */ #define USART_CTRLA_TXPO_MASK (3 << USART_CTRLA_TXPO_SHIFT) # define USART_CTRLA_TXPAD0_1 (0 << USART_CTRLA_TXPO_SHIFT) /* TxD=PAD0 XCK=PAD1 @@ -208,12 +210,14 @@ * RTS/TE=PAD2 CTS=PAD3 */ # define USART_CTRLA_TXPAD0_3 (3 << USART_CTRLA_TXPO_SHIFT) /* TxD=PAD0 RTS=PAD1 * RTS/PAD2 CTS=N/A */ + #define USART_CTRLA_RXPO_SHIFT (20) /* Bits 20-21: Receive data pinout */ #define USART_CTRLA_RXPO_MASK (3 << USART_CTRLA_RXPO_SHIFT) # define USART_CTRLA_RXPAD0 (0 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD0 */ # define USART_CTRLA_RXPAD1 (1 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD1 */ # define USART_CTRLA_RXPAD2 (2 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD2 */ # define USART_CTRLA_RXPAD3 (3 << USART_CTRLA_RXPO_SHIFT) /* RxD=SERCOM PAD3 */ + #define USART_CTRLA_SAMPA_SHIFT (22) /* Bits 22-23: Sample adjustment */ #define USART_CTRLA_SAMPA_MASK (3 << USART_CTRLA_SAMPA_SHIFT) # define USART_CTRLA_SAMPA_789 (0 << USART_CTRLA_SAMPA_SHIFT) /* 16x oversampling 7-8-9 */ @@ -224,6 +228,7 @@ # define USART_CTRLA_SAMPA_456 (1 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 4-5-6 */ # define USART_CTRLA_SAMPA_567 (2 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 5-6-7 */ # define USART_CTRLA_SAMPA_678 (3 << USART_CTRLA_SAMPA_SHIFT) /* 8x oversampling 6-7-8 */ + #define USART_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */ #define USART_CTRLA_FORM_MASK (7 << USART_CTRLA_FORM_SHIFT) # define USART_CTRLA_FORM_NOPARITY (0 << USART_CTRLA_FORM_SHIFT) /* USART frame (no parity) */ @@ -232,12 +237,15 @@ # define USART_CTRLA_FORM_AUTOBAUD (4 << USART_CTRLA_FORM_SHIFT) /* Lin slave; Auto-baud (no parity) */ # define USART_CTRLA_FORM_AUTOBAUDP (5 << USART_CTRLA_FORM_SHIFT) /* Auto-baud (w/ parity) */ # define USART_CTRLA_FORM_ISO7816 (7 << USART_CTRLA_FORM_SHIFT) /* ISO 7816 */ + #define USART_CTRLA_CMODE (1 << 28) /* Bit 28: Communication mode */ # define USART_CTRLA_ASYNCH (0) # define USART_CTRLA_SYNCH USART_CTRLA_CMODE #define USART_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */ + # define USART_CTRLA_CPOL_NORMAL (0) /* Rising XCK edge Falling XCK edge */ # define USART_CTRLA_CPOL_INVERTED USART_CTRLA_CPOL /* Falling XCK edge Rising XCK edge */ + #define USART_CTRLA_DORD (1 << 30) /* Bit 30: Data order */ # define USART_CTRLA_MSBFIRST (0) # define USART_CTRLA_LSBFIRST USART_CTRLA_DORD @@ -251,6 +259,7 @@ # define USART_CTRLB_CHSIZE_5BITS (5 << USART_CTRLB_CHSIZE_SHIFT) /* 5 bits */ # define USART_CTRLB_CHSIZE_6BITS (6 << USART_CTRLB_CHSIZE_SHIFT) /* 6 bits */ # define USART_CTRLB_CHSIZE_7BITS (7 << USART_CTRLB_CHSIZE_SHIFT) /* 7 bits */ + #define USART_CTRLB_SBMODE (1 << 6) /* Bit 6: Stop bit mode */ # define USART_CTRLB_SBMODE_1 (0) # define USART_CTRLB_SBMODE_2 USART_CTRLB_SBMODE @@ -282,15 +291,19 @@ # define USART_CTRLC_BRKLEN_17BITS (1 << USART_CTRLC_BRKLEN_SHIFT) /* 17 bit times */ # define USART_CTRLC_BRKLEN_21BITS (2 << USART_CTRLC_BRKLEN_SHIFT) /* 21 bit times */ # define USART_CTRLC_BRKLEN_26BITS (3 << USART_CTRLC_BRKLEN_SHIFT) /* 26 bit times */ + #define USART_CTRLC_HDRDLY_SHIFT (10) /* Bits 10-11: LIN Master Header Delay */ #define USART_CTRLC_HDRDLY_MASK (3 << USART_CTRLC_HDRDLY_SHIFT) # define USART_CTRLC_HDRDLY_1_1 (0 << USART_CTRLC_HDRDLY_SHIFT) /* 1, 1 bit times */ # define USART_CTRLC_HDRDLY_4_4 (1 << USART_CTRLC_HDRDLY_SHIFT) /* 4, 4 bit times */ # define USART_CTRLC_HDRDLY_8_4 (2 << USART_CTRLC_HDRDLY_SHIFT) /* 8, 4 bit times */ # define USART_CTRLC_HDRDLY_14_4 (3 << USART_CTRLC_HDRDLY_SHIFT) /* 14, 4 bit times */ + #define USART_CTRLC_INACK (1 << 16) /* Bit 16: Inhibit Not Acknowledge */ + # define USART_CTRLC_NACK (0) /* 0=NACK transmitted */ # define USART_CTRLC_NONACK USART_CTRLC_INACK /* 1=NACK not ransmitted */ + #define USART_CTRLC_DSNACK (1 << 17) /* Bit 17: Disable Successive Not Acknowledge */ #define USART_CTRLC_MAXITER_SHIFT (20) /* Bits 20-22: Data 32 Bit */ #define USART_CTRLC_MAXITER_MASK (7 << USART_CTRLC_MAXITER_SHIFT) @@ -303,10 +316,11 @@ # define USART_CTRLC_DATA32B_BOTH (3 << USART_CTRLC_DATA32B_SHIFT) /* Both per 32-bit extension */ /* Baud register (16-bit baud value) */ + /* Receive pulse length register (8-bit value) */ -/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and - * status clear registers. +/* Interrupt enable clear, interrupt enable set, interrupt enable set, + * interrupt flag and status clear registers. */ #define USART_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */ @@ -361,16 +375,16 @@ #define USART_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USART_H */ diff --git a/arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h b/arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h index a7d3ed74090..f18976e1eac 100644 --- a/arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h +++ b/arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_MEMORYMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ /* System Memory Map */ @@ -136,16 +136,16 @@ #define SAM_PCC_BASE 0x44002c00 /* Parallel Capture Controller (PCC) */ /* Reserved */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_MEMORYMAP_H */ diff --git a/arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h b/arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h index 36c52e791d0..c06843e9ed7 100644 --- a/arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h +++ b/arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,38 +16,41 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_PINMAP_H #define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_PINMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* GPIO pin definitions *********************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the SERCOM0 PAD0 on PA8, then the following definition should appear in - * the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if we wanted the SERCOM0 PAD0 on PA8, then the following + * definition should appear in the board.h header file for that board: * * #define PORT_SERCOM0_PAD0 PORT_SERCOM0_PAD0_1 * - * The driver will then automatically configure PA8 as the SERCOM0 PAD0 pin. + * The driver will then automatically configure PA8 as the SERCOM0 PAD0 + * pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* Analog comparator (AC) */ @@ -760,16 +763,16 @@ #define PORT_USB_SOF_1KHZ_1 (PORT_FUNCH | PORTA | PORT_PIN23) #define PORT_USB_SOF_1KHZ_2 (PORT_FUNCH | PORTB | PORT_PIN22) -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_PINMAP_H */ diff --git a/arch/arm/src/samd5e5/sam_clockconfig.h b/arch/arm/src/samd5e5/sam_clockconfig.h index 6754cad384e..6096395b407 100644 --- a/arch/arm/src/samd5e5/sam_clockconfig.h +++ b/arch/arm/src/samd5e5/sam_clockconfig.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/sam_clockconfig.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_CLOCKCONFIG_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_CLOCKCONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "sam_gclk.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* This structure defines the configuration of the 32.768KHz XOSC32 */ @@ -191,15 +191,15 @@ struct sam_clockconfig_s struct sam_gclk_config_s gclk[12]; /* GCLK configurations */ }; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -210,32 +210,32 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_clock_configure * * Description: * Configure the clock sub-system per the provided configuration data. * - * This should be called only (1) early in the initialization sequence, or (2) - * later but within a critical section. + * This should be called only (1) early in the initialization sequence, + * or (2) later but within a critical section. * - ************************************************************************************/ + ****************************************************************************/ struct sam_clockconfig_s; void sam_clock_configure(const struct sam_clockconfig_s *config); -/************************************************************************************ +/**************************************************************************** * Name: sam_clock_initialize * * Description: * Configure the initial power-up clocking. This function may be called * only once by the power-up reset logic. * - ************************************************************************************/ + ****************************************************************************/ void sam_clock_initialize(void); diff --git a/arch/arm/src/samd5e5/sam_cmcc.c b/arch/arm/src/samd5e5/sam_cmcc.c index 0a402b1f4d6..974f2a000af 100644 --- a/arch/arm/src/samd5e5/sam_cmcc.c +++ b/arch/arm/src/samd5e5/sam_cmcc.c @@ -78,16 +78,16 @@ void sam_cmcc_enable(void) { /* "On reset, the cache controller data entries are all invalidated and the - * cache is disabled. The cache is transparent to processor operations. The - * cache controller is activated with its configuration registers. The + * cache is disabled. The cache is transparent to processor operations. + * The cache controller is activated with its configuration registers. The * configuration interface is memory mapped in the private peripheral bus. * * "Use the following sequence to enable the cache controller. * - * "1. Verify that the cache controller is disabled, reading the value of the - * CSTS (cache status) field of the CMCC_SR register. - * "2. Enable the cache controller, writing 1 to the CEN (cache enable) field - * of the CMCC_CTRL register." + * "1. Verify that the cache controller is disabled, reading the value of + * the CSTS (cache status) field of the CMCC_SR register. + * "2. Enable the cache controller, writing 1 to the CEN (cache enable) + * field of the CMCC_CTRL register." */ if ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) == 0) @@ -160,9 +160,9 @@ void sam_cmcc_invalidate(uintptr_t start, uintptr_t end) return; } - /* "When an invalidate by line command is issued the cache controller resets - * the valid bit information of the decoded cache line. As the line is no - * longer valid the replacement counter points to that line. + /* "When an invalidate by line command is issued the cache controller + * resets the valid bit information of the decoded cache line. As the + * line is no longer valid the replacement counter points to that line. * * "Use the following sequence to invalidate one line of cache. * diff --git a/arch/arm/src/samd5e5/sam_cmcc.h b/arch/arm/src/samd5e5/sam_cmcc.h index fd3eb801fe8..06f1b610c37 100644 --- a/arch/arm/src/samd5e5/sam_cmcc.h +++ b/arch/arm/src/samd5e5/sam_cmcc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/sam_cmcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_CMCC_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_CMCC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,23 +31,23 @@ #ifdef CONFIG_SAMD5E5_CMCC -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -58,9 +58,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_cmcc_enable @@ -112,7 +112,9 @@ void sam_cmcc_invalidateall(void); #endif /* __ASSEMBLY__ */ #else /* CONFIG_SAMD5E5_CMCC */ -/* Stubs so that we don't have to put condition compilation in driver source */ +/* Stubs so that we don't have to put condition compilation in driver + * source + */ # define sam_cmcc_invalidate(start, end) # define sam_cmcc_invalidateall() diff --git a/arch/arm/src/samd5e5/sam_config.h b/arch/arm/src/samd5e5/sam_config.h index d72ee91b034..8a5403547ea 100644 --- a/arch/arm/src/samd5e5/sam_config.h +++ b/arch/arm/src/samd5e5/sam_config.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/sam_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* How many SERCOM peripherals are configured as USART peripherals? */ @@ -132,8 +132,9 @@ # define SAMD5E5_HAVE_USART 1 #endif -/* Is there a serial console? There should be at most one defined. It could be on - * any USARTn, n=0-5 - OR - there might not be any serial console at all. +/* Is there a serial console? There should be at most one defined. + * It could be on any USARTn, n=0-5 - OR - there might not be any + * serial console at all. */ #if defined(CONFIG_USART0_SERIAL_CONSOLE) @@ -342,16 +343,16 @@ # define SAMD5E5_HAVE_I2C_MASTER 1 #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_CONFIG_H */ diff --git a/arch/arm/src/samd5e5/sam_dmac.h b/arch/arm/src/samd5e5/sam_dmac.h index 01a46a99d7e..ea6fe14f857 100644 --- a/arch/arm/src/samd5e5/sam_dmac.h +++ b/arch/arm/src/samd5e5/sam_dmac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/sam_dmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_DMAC_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_DMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,26 +31,31 @@ #include "hardware/sam_dmac.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* DMA ******************************************************************************/ +/* DMA **********************************************************************/ -/* Flags used to characterize the desired DMA channel. The naming convention is that - * one side is the peripheral and the other is memory (however, the interface could still - * be used if, for example, both sides were memory although the naming would be awkward) +/* Flags used to characterize the desired DMA channel. The naming convention + * is that one side is the peripheral and the other is memory (however, the + * interface could still be used if, for example, both sides were memory + * although the naming would be awkward) */ /* Common characteristics * - * BEATSIZE - The size of one bus transfer or "beat". 8-, 16-, or 32-bits - * STEPSEL - The STEPSIZE may be applied only to the memory to the peripheral. - * STEPSIZE - When the address is incremented, it is increments by how many "beats"? + * BEATSIZE - The size of one bus transfer or "beat". + * 8-, 16-, or 32-bits + * STEPSEL - The STEPSIZE may be applied only to the memory to the + * peripheral. + * STEPSIZE - When the address is incremented, it is increments by + * how many "beats"? * PRIORITY - DMA transfer priority * RUNSTDBY - DMA runs in standby mode * BURSTLEN - Burst length. - * THRESHOLD - Threshold at which DMA starts to write (multi-BEAT transfers only) + * THRESHOLD - Threshold at which DMA starts to write + * (multi-BEAT transfers only) */ #define DMACH_FLAG_BEATSIZE_SHIFT (0) /* Bits 0-1: Beat size */ @@ -58,6 +63,7 @@ # define DMACH_FLAG_BEATSIZE_BYTE (0 << DMACH_FLAG_BEATSIZE_SHIFT) /* 8-bit bus transfer */ # define DMACH_FLAG_BEATSIZE_HWORD (1 << DMACH_FLAG_BEATSIZE_SHIFT) /* 16-bit bus transfer */ # define DMACH_FLAG_BEATSIZE_WORD (2 << DMACH_FLAG_BEATSIZE_SHIFT) /* 32-bit bus transfer */ + #define DMACH_FLAG_STEPSEL (1 << 2) /* Bit 2: Step selection */ # define DMACH_FLAG_STEPSEL_MEM (0) /* 0=Step size applies to memory */ # define DMACH_FLAG_STEPSEL_PERIPH (1 << 2) /* 1=Step size applies to peripheral */ @@ -71,13 +77,15 @@ # define DMACH_FLAG_STEPSIZE_X32 (5 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 32 */ # define DMACH_FLAG_STEPSIZE_X64 (6 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 64 */ # define DMACH_FLAG_STEPSIZE_X128 (7 << DMACH_FLAG_STEPSIZE_SHIFT) /* Next ADDR = ADDR + (BEATSIZE+1) * 128 */ + #define DMACH_FLAG_PRIORITY_SHIFT (6) /* Bit 6-7: Arbitration priority */ #define DMACH_FLAG_PRIORITY_MASK (3 << DMACH_FLAG_PRIORITY_SHIFT) # define DMACH_FLAG_PRIORITY(n) ((uint32_t)(n) << DMACH_FLAG_PRIORITY_SHIFT) #define DMACH_FLAG_RUNINSTDBY (1 << 8) /* Bit 8: Run in standby */ -#define DMACH_FLAG_BURSTLEN_SHIFT (9) /* Bits 9-12: Burst length */ +#define DMACH_FLAG_BURSTLEN_SHIFT (9) /* Bits 9-12: Burst length */ #define DMACH_FLAG_BURSTLEN_MASK (15 << DMACH_FLAG_BURSTLEN_SHIFT) # define DMACH_FLAG_BURSTLEN(n) ((uint32_t)(n) << DMACH_FLAG_BURSTLEN_SHIFT) /* n=1-16 */ + #define DMACH_FLAG_THRESHOLD_SHIFT (13) /* Bits 13-14: Threshold */ #define DMACH_FLAG_THRESHOLD_MASK (15 << DMACH_FLAG_THRESHOLD_SHIFT) # define DMACH_FLAG_THRESHOLD_1BEAT (0 << DMACH_FLAG_THRESHOLD_SHIFT) /* Write after 1 beat */ @@ -87,12 +95,14 @@ /* Peripheral endpoint characteristics. * - * PERIPH_TRIGSRC - The TX ID of the peripheral that provides the DMA trigger. This - * is one of the DMAC_CHCTRLA_TRIGSRC_*[_TX] definitions. This trigger source - * is selected when sam_dmatxsetup() is called. + * PERIPH_TRIGSRC - The TX ID of the peripheral that provides the DMA + * trigger. + * This is one of the DMAC_CHCTRLA_TRIGSRC_*[_TX] + * definitions. This trigger source is selected when + * sam_dmatxsetup() is called. * PERIPH_TRIGACT - Trigger action - * PERIPH_INCREMENT - Indicates that the peripheral address should be incremented on - * each "beat" + * PERIPH_INCREMENT - Indicates that the peripheral address should be + * incremented on each "beat" */ #define DMACH_FLAG_PERIPH_TRIGSRC_SHIFT (15) /* Bits 15-21: See DMAC_CHCTRLA_TRIGSRC_* */ @@ -103,25 +113,28 @@ # define DMACH_FLAG_PERIPH_TRIGACT_BLOCK (0 << DMACH_FLAG_PERIPH_TRIGACT_SHIFT) /* Trigger per block transfer */ # define DMACH_FLAG_PERIPH_TRIGACT_BURST (2 << DMACH_FLAG_PERIPH_TRIGACT_SHIFT) /* Trigger per burst transfer */ # define DMACH_FLAG_PERIPH_TRIGACT_TRANS (3 << DMACH_FLAG_PERIPH_TRIGACT_SHIFT) /* Trigger for each transaction */ + #define DMACH_FLAG_PERIPH_INCREMENT (1 << 24) /* Bit 24: Autoincrement peripheral address */ /* Memory endpoint characteristics * - * MEM_INCREMENT - Indicates that the memory address should be incremented on each - * "beat" + * MEM_INCREMENT - Indicates that the memory address should be incremented + * on each "beat" */ #define DMACH_FLAG_MEM_INCREMENT (1 << 25) /* Bit 25: Autoincrement memory address */ /* Bits 26-31: Not used */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA + * is selected + */ #ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s @@ -157,15 +170,15 @@ struct sam_dmaregs_s }; #endif -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -176,119 +189,121 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_dmachannel * * Description: - * Allocate a DMA channel. This function sets aside a DMA channel and gives the - * caller exclusive access to the DMA channel. + * Allocate a DMA channel. This function sets aside a DMA channel and + * gives the caller exclusive access to the DMA channel. * - * The naming convention in all of the DMA interfaces is that one side is the - * 'peripheral' and the other is 'memory'. However, the interface could still be - * used if, for example, both sides were memory although the naming would be - * awkward. + * The naming convention in all of the DMA interfaces is that one side is + * the 'peripheral' and the other is 'memory'. However, the interface + * could still be used if, for example, both sides were memory although + * the naming would be awkward. * * Returned Value: - * If a DMA channel if the required FIFO size is available, this function returns - * a non-NULL, void* DMA channel handle. NULL is returned on any failure. + * If a DMA channel if the required FIFO size is available, this function + * returns a non-NULL, void* DMA channel handle. NULL is returned on any + * failure. * - ************************************************************************************/ + ****************************************************************************/ DMA_HANDLE sam_dmachannel(uint32_t txflags, uint32_t rxflags); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmaconfig * * Description: * There are two channel usage models: (1) The channel is allocated and - * configured in one step. This is the typical case where a DMA channel performs - * a constant role. The alternative is (2) where the DMA channel is reconfigured - * on the fly. In this case, the chflags provided to sam_dmachannel are not used - * and sam_dmaconfig() is called before each DMA to configure the DMA channel - * appropriately. + * configured in one step. This is the typical case where a DMA channel + * performs a constant role. The alternative is (2) where the DMA channel + * is reconfigured on the fly. In this case, the chflags provided to + * sam_dmachannel are not used and sam_dmaconfig() is called before each + * DMA to configure the DMA channel appropriately. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_dmaconfig(DMA_HANDLE handle, uint32_t txflags, uint32_t rxflags); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmafree * * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must NEVER be - * used again until sam_dmachannel() is called again to re-gain a valid handle. + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again + * until sam_dmachannel() is called again to re-gain a valid handle. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_dmafree(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmatxsetup * * Description: - * Configure DMA for transmit of one buffer (memory to peripheral). This function - * may be called multiple times to handle large and/or non-contiguous transfers. - * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the - * same transfer, however. + * Configure DMA for transmit of one buffer (memory to peripheral). This + * function may be called multiple times to handle large and/or + * non-contiguous transfers. Calls to sam_dmatxsetup() and sam_dmarxsetup() + * must not be intermixed on the same transfer, however. * - ************************************************************************************/ + ****************************************************************************/ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmarxsetup * * Description: - * Configure DMA for receipt of one buffer (peripheral to memory). This function - * may be called multiple times to handle large and/or non-contiguous transfers. - * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the - * same transfer, however. + * Configure DMA for receipt of one buffer (peripheral to memory). This + * function may be called multiple times to handle large and/or + * non-contiguous transfers. Calls to sam_dmatxsetup() and sam_dmarxsetup() + * must not be intermixed on the same transfer, however. * - ************************************************************************************/ + ****************************************************************************/ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmastart * * Description: * Start the DMA transfer * - ************************************************************************************/ + ****************************************************************************/ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmastop * * Description: * Cancel the DMA. After sam_dmastop() is called, the DMA channel is - * reset and sam_dmarx/txsetup() must be called before sam_dmastart() can be - * called again + * reset and sam_dmarx/txsetup() must be called before sam_dmastart() + * can be called again * - ************************************************************************************/ + ****************************************************************************/ void sam_dmastop(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmasample * * Description: * Sample DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); @@ -296,13 +311,13 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); # define sam_dmasample(handle,regs) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_dmadump * * Description: * Dump previously sampled DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, diff --git a/arch/arm/src/samd5e5/sam_ethernet.h b/arch/arm/src/samd5e5/sam_ethernet.h index 898253f4044..fb69ac8f04d 100644 --- a/arch/arm/src/samd5e5/sam_ethernet.h +++ b/arch/arm/src/samd5e5/sam_ethernet.h @@ -64,7 +64,7 @@ # endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -118,7 +118,7 @@ int sam_gmac_initialize(void); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMD5E5_GMAC_PHYINIT int sam_phy_boardinitialize(int intf); diff --git a/arch/arm/src/samd5e5/sam_gclk.c b/arch/arm/src/samd5e5/sam_gclk.c index 11b3e945357..2dcf00a425e 100644 --- a/arch/arm/src/samd5e5/sam_gclk.c +++ b/arch/arm/src/samd5e5/sam_gclk.c @@ -151,7 +151,9 @@ void sam_gclk_configure(int gclk, FAR const struct sam_gclk_config_s *config) regval |= GCLK_GENCTRL1_DIV((uint32_t)config->div); - /* Enable non-binary division with increased duty cycle accuracy */ + /* Enable non-binary division with increased duty cycle + * accuracy + */ regval |= GCLK_GENCTRL_IDC; } diff --git a/arch/arm/src/samd5e5/sam_gclk.h b/arch/arm/src/samd5e5/sam_gclk.h index 07b2b6edb86..b107cccf2ac 100644 --- a/arch/arm/src/samd5e5/sam_gclk.h +++ b/arch/arm/src/samd5e5/sam_gclk.h @@ -102,7 +102,8 @@ extern "C" * ****************************************************************************/ -void sam_gclk_configure(int gclk, FAR const struct sam_gclk_config_s *config); +void sam_gclk_configure(int gclk, + FAR const struct sam_gclk_config_s *config); /**************************************************************************** * Name: sam_gclk_chan_enable diff --git a/arch/arm/src/samd5e5/sam_i2c_master.c b/arch/arm/src/samd5e5/sam_i2c_master.c index b0a1fdccc8a..138047225ec 100644 --- a/arch/arm/src/samd5e5/sam_i2c_master.c +++ b/arch/arm/src/samd5e5/sam_i2c_master.c @@ -1,4 +1,4 @@ -/******************************************************************************* +/**************************************************************************** * arch/arm/src/samd5e5/sam_i2c_master.c * * Copyright (C) 2013-2014, 2018 Gregory Nutt. All rights reserved. @@ -37,11 +37,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Included Files - *******************************************************************************/ + ****************************************************************************/ #include @@ -71,11 +71,11 @@ #if defined(SAMD5E5_HAVE_I2C_MASTER) -/******************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *******************************************************************************/ + ****************************************************************************/ -/* Configuration ***************************************************************/ +/* Configuration ************************************************************/ #ifndef CONFIG_SAM_I2C0_FREQUENCY # define CONFIG_SAM_I2C0_FREQUENCY 100000 @@ -101,13 +101,14 @@ # define CONFIG_SAM_I2C5_FREQUENCY 100000 #endif -/* Driver internal definitions *************************************************/ +/* Driver internal definitions **********************************************/ -/* If verbose I2C debug output is enable, then allow more time before we declare - * a timeout. The debug output from i2c_interrupt will really slow things down! +/* If verbose I2C debug output is enable, then allow more time before we + * declare a timeout. + * The debug output from i2c_interrupt will really slow things down! * - * With a very slow clock (say 100,000 Hz), less than 100 usec would be required - * to transfer on byte. So these define a "long" timeout. + * With a very slow clock (say 100,000 Hz), less than 100 usec would be + * required to transfer on byte. So these define a "long" timeout. */ #ifdef CONFIG_DEBUG_I2C_INFO @@ -122,9 +123,9 @@ #define I2C_MAX_FREQUENCY 66000000 /* Maximum I2C frequency */ -/******************************************************************************* +/**************************************************************************** * Private Types - *******************************************************************************/ + ****************************************************************************/ /* Invariant attributes of a I2C bus */ @@ -176,19 +177,22 @@ struct sam_i2c_dev_s #endif }; -/******************************************************************************* +/**************************************************************************** * Private Function Prototypes - *******************************************************************************/ + ****************************************************************************/ /* Low-level helper functions */ -static uint8_t i2c_getreg8(struct sam_i2c_dev_s *priv, unsigned int offset); +static uint8_t i2c_getreg8(struct sam_i2c_dev_s *priv, + unsigned int offset); static void i2c_putreg8(struct sam_i2c_dev_s *priv, uint8_t regval, unsigned int offset); -static uint16_t i2c_getreg16(struct sam_i2c_dev_s *priv, unsigned int offset); +static uint16_t i2c_getreg16(struct sam_i2c_dev_s *priv, + unsigned int offset); static void i2c_putreg16(struct sam_i2c_dev_s *priv, uint16_t regval, unsigned int offset); -static uint32_t i2c_getreg32(struct sam_i2c_dev_s *priv, unsigned int offset); +static uint32_t i2c_getreg32(struct sam_i2c_dev_s *priv, + unsigned int offset); static void i2c_putreg32(struct sam_i2c_dev_s *priv, uint32_t regval, unsigned int offset); @@ -209,7 +213,8 @@ static void i2c_putabs(struct sam_i2c_dev_s *priv, uintptr_t address, static inline uint32_t i2c_getrel(struct sam_i2c_dev_s *priv, unsigned int offset); -static inline void i2c_putrel(struct sam_i2c_dev_s *priv, unsigned int offset, +static inline void i2c_putrel(struct sam_i2c_dev_s *priv, + unsigned int offset, uint32_t value); /* I2C transfer helper functions */ @@ -220,8 +225,10 @@ static void i2c_wakeup(struct sam_i2c_dev_s *priv, int result); static int i2c_interrupt(int irq, FAR void *context, void *arg); static void i2c_startread(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg); -static void i2c_startwrite(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg); -static void i2c_startmessage(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg); +static void i2c_startwrite(struct sam_i2c_dev_s *priv, + struct i2c_msg_s *msg); +static void i2c_startmessage(struct sam_i2c_dev_s *priv, + struct i2c_msg_s *msg); static int sam_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count); @@ -230,13 +237,14 @@ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, static uint32_t sam_i2c_setfrequency(struct sam_i2c_dev_s *priv, uint32_t frequency); -static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency); +static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, + uint32_t frequency); static void i2c_wait_synchronization(struct sam_i2c_dev_s *priv); static void i2c_pad_configure(struct sam_i2c_dev_s *priv); -/******************************************************************************* +/**************************************************************************** * Private Data - *******************************************************************************/ + ****************************************************************************/ #ifdef SAMD5E5_HAVE_I2C0_MASTER static const struct i2c_attr_s g_i2c0attr = @@ -390,30 +398,30 @@ struct i2c_ops_s g_i2cops = #endif }; -/******************************************************************************* +/**************************************************************************** * Low-level Helpers - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: i2c_getreg8 * * Description: * Get a 8-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static uint8_t i2c_getreg8(struct sam_i2c_dev_s *priv, unsigned int offset) { return getreg8(priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_putreg8 * * Description: * Put a 8-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static void i2c_putreg8(struct sam_i2c_dev_s *priv, uint8_t regval, unsigned int offset) @@ -421,26 +429,26 @@ static void i2c_putreg8(struct sam_i2c_dev_s *priv, uint8_t regval, putreg8(regval, priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_getreg16 * * Description: * Get a 16-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static uint16_t i2c_getreg16(struct sam_i2c_dev_s *priv, unsigned int offset) { return getreg16(priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_putreg16 * * Description: * Put a 16-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static void i2c_putreg16(struct sam_i2c_dev_s *priv, uint16_t regval, unsigned int offset) @@ -448,26 +456,26 @@ static void i2c_putreg16(struct sam_i2c_dev_s *priv, uint16_t regval, putreg16(regval, priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_getreg32 * * Description: * Get a 32-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static uint32_t i2c_getreg32(struct sam_i2c_dev_s *priv, unsigned int offset) { return getreg32(priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_putreg32 * * Description: * Put a 32-bit register value by offset * - *******************************************************************************/ + ****************************************************************************/ static void i2c_putreg32(struct sam_i2c_dev_s *priv, uint32_t regval, unsigned int offset) @@ -475,7 +483,7 @@ static void i2c_putreg32(struct sam_i2c_dev_s *priv, uint32_t regval, putreg32(regval, priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_takesem * * Description: @@ -487,7 +495,7 @@ static void i2c_putreg32(struct sam_i2c_dev_s *priv, uint32_t regval, * Returned Value: * None * - *******************************************************************************/ + ****************************************************************************/ static void i2c_takesem(sem_t *sem) { @@ -508,7 +516,7 @@ static void i2c_takesem(sem_t *sem) while (ret == -EINTR); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_checkreg * * Description: @@ -522,7 +530,7 @@ static void i2c_takesem(sem_t *sem) * true: This is the first register access of this type. * false: This is the same as the preceding register access. * - *******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMD5E5_I2C_REGDEBUG static bool i2c_checkreg(struct sam_i2c_dev_s *priv, bool wr, uint32_t value, @@ -562,13 +570,13 @@ static bool i2c_checkreg(struct sam_i2c_dev_s *priv, bool wr, uint32_t value, } #endif -/******************************************************************************* +/**************************************************************************** * Name: i2c_getabs * * Description: * Read any 32-bit register using an absolute * - *******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMD5E5_I2C_REGDEBUG static uint32_t i2c_getabs(struct sam_i2c_dev_s *priv, uintptr_t address) @@ -584,13 +592,13 @@ static uint32_t i2c_getabs(struct sam_i2c_dev_s *priv, uintptr_t address) } #endif -/******************************************************************************* +/**************************************************************************** * Name: i2c_putabs * * Description: * Write to any 32-bit register using an absolute address * - *******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMD5E5_I2C_REGDEBUG static void i2c_putabs(struct sam_i2c_dev_s *priv, uintptr_t address, @@ -605,13 +613,13 @@ static void i2c_putabs(struct sam_i2c_dev_s *priv, uintptr_t address, } #endif -/******************************************************************************* +/**************************************************************************** * Name: i2c_getrel * * Description: * Read a I2C register using an offset relative to the I2C base address * - *******************************************************************************/ + ****************************************************************************/ static inline uint32_t i2c_getrel(struct sam_i2c_dev_s *priv, unsigned int offset) @@ -619,26 +627,27 @@ static inline uint32_t i2c_getrel(struct sam_i2c_dev_s *priv, return i2c_getabs(priv, priv->attr->base + offset); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_putrel * * Description: * Write a value to a I2C register using an offset relative to the I2C base * address. * - *******************************************************************************/ + ****************************************************************************/ -static inline void i2c_putrel(struct sam_i2c_dev_s *priv, unsigned int offset, +static inline void i2c_putrel(struct sam_i2c_dev_s *priv, + unsigned int offset, uint32_t value) { i2c_putabs(priv, priv->attr->base + offset, value); } -/******************************************************************************* +/**************************************************************************** * I2C transfer helper functions - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: i2c_wait_for_bus * * Description: @@ -648,7 +657,7 @@ static inline void i2c_putrel(struct sam_i2c_dev_s *priv, unsigned int offset, * Assumptions: * Interrupts are disabled * - *******************************************************************************/ + ****************************************************************************/ static int i2c_wait_for_bus(struct sam_i2c_dev_s *priv, unsigned int size) { @@ -677,13 +686,13 @@ static int i2c_wait_for_bus(struct sam_i2c_dev_s *priv, unsigned int size) return priv->result; } -/******************************************************************************* +/**************************************************************************** * Name: i2c_wakeup * * Description: * A terminal event has occurred. Wake-up the waiting thread * - *******************************************************************************/ + ****************************************************************************/ static void i2c_wakeup(struct sam_i2c_dev_s *priv, int result) { @@ -697,13 +706,13 @@ static void i2c_wakeup(struct sam_i2c_dev_s *priv, int result) nxsem_post(&priv->waitsem); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_interrupt * * Description: * The I2C Interrupt Handler * - *******************************************************************************/ + ****************************************************************************/ static int i2c_interrupt(int irq, FAR void *context, FAR void *arg) { @@ -830,13 +839,13 @@ static int i2c_interrupt(int irq, FAR void *context, FAR void *arg) return OK; } -/******************************************************************************* +/**************************************************************************** * Name: i2c_startread * * Description: * Start the next read message * - *******************************************************************************/ + ****************************************************************************/ static void i2c_startread(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) { @@ -880,13 +889,13 @@ static void i2c_startread(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) i2c_wait_synchronization(priv); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_startwrite * * Description: * Start the next write message * - *******************************************************************************/ + ****************************************************************************/ static void i2c_startwrite(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) { @@ -943,15 +952,16 @@ static void i2c_startwrite(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) i2c_wait_synchronization(priv); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_startmessage * * Description: * Start the next write message * - *******************************************************************************/ + ****************************************************************************/ -static void i2c_startmessage(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) +static void i2c_startmessage(struct sam_i2c_dev_s *priv, + struct i2c_msg_s *msg) { if ((msg->flags & I2C_M_READ) != 0) { @@ -965,11 +975,11 @@ static void i2c_startmessage(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) } } -/******************************************************************************* +/**************************************************************************** * I2C device operations - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_transfer * * Description: @@ -979,7 +989,7 @@ static void i2c_startmessage(struct sam_i2c_dev_s *priv, struct i2c_msg_s *msg) * Returned Value: * Returns zero on success; a negated errno value on failure. * - *******************************************************************************/ + ****************************************************************************/ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count) @@ -1036,8 +1046,8 @@ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, flags = enter_critical_section(); i2c_startmessage(priv, msgs); - /* And wait for the transfers to complete. Interrupts will be re-enabled - * while we are waiting. + /* And wait for the transfers to complete. + * Interrupts will be re-enabled while we are waiting. */ ret = i2c_wait_for_bus(priv, msgs->length); @@ -1059,17 +1069,17 @@ static int sam_i2c_transfer(FAR struct i2c_master_s *dev, return ret; } -/******************************************************************************* +/**************************************************************************** * Initialization - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_setfrequency * * Description: * Set the frequency for the next transfer * - *******************************************************************************/ + ****************************************************************************/ static uint32_t sam_i2c_setfrequency(struct sam_i2c_dev_s *priv, uint32_t frequency) @@ -1092,7 +1102,9 @@ static uint32_t sam_i2c_setfrequency(struct sam_i2c_dev_s *priv, frequency = maxfreq; } - /* Check if the requested frequency is the same as the frequency selection */ + /* Check if the requested frequency is the same as the frequency + * selection + */ if (priv->frequency == frequency) { @@ -1162,15 +1174,15 @@ static uint32_t sam_i2c_setfrequency(struct sam_i2c_dev_s *priv, return priv->frequency; } -/******************************************************************************* +/**************************************************************************** * Name: i2c_hw_initialize * * Description: * Initialize/Re-initialize the I2C peripheral. This logic performs only - * repeatable initialization after either (1) the one-time initialization, or - * (2) after each bus reset. + * repeatable initialization after either (1) the one-time initialization, + * or (2) after each bus reset. * - *******************************************************************************/ + ****************************************************************************/ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency) { @@ -1252,26 +1264,26 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency) leave_critical_section(flags); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_wait_synchronization * * Description: * Wait until the SERCOM I2C reports that it is synchronized. * - *******************************************************************************/ + ****************************************************************************/ static void i2c_wait_synchronization(struct sam_i2c_dev_s *priv) { while ((i2c_getreg16(priv, SAM_I2C_SYNCBUSY_OFFSET) & 0x7) != 0); } -/******************************************************************************* +/**************************************************************************** * Name: i2c_pad_configure * * Description: * Configure the SERCOM I2C pads. * - *******************************************************************************/ + ****************************************************************************/ static void i2c_pad_configure(struct sam_i2c_dev_s *priv) { @@ -1288,17 +1300,17 @@ static void i2c_pad_configure(struct sam_i2c_dev_s *priv) } } -/******************************************************************************* +/**************************************************************************** * Public Functions - *******************************************************************************/ + ****************************************************************************/ -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_master_initialize * * Description: * Initialize a I2C device for I2C operation * - *******************************************************************************/ + ****************************************************************************/ struct i2c_master_s *sam_i2c_master_initialize(int bus) { @@ -1461,13 +1473,13 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus) return &priv->dev; } -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_uninitialize * * Description: * Uninitialize an I2C device * - *******************************************************************************/ + ****************************************************************************/ int sam_i2c_uninitialize(FAR struct i2c_master_s *dev) { @@ -1491,13 +1503,13 @@ int sam_i2c_uninitialize(FAR struct i2c_master_s *dev) return OK; } -/******************************************************************************* +/**************************************************************************** * Name: sam_i2c_reset * * Description: * Reset an I2C bus * - *******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_I2C_RESET int sam_i2c_reset(FAR struct i2c_master_s *dev) diff --git a/arch/arm/src/samd5e5/sam_mpuinit.h b/arch/arm/src/samd5e5/sam_mpuinit.h index e5102669364..8fec2ca694a 100644 --- a/arch/arm/src/samd5e5/sam_mpuinit.h +++ b/arch/arm/src/samd5e5/sam_mpuinit.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/sam_mpuinit.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,37 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_MPUINIT_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_MPUINIT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -57,16 +57,16 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_mpuinitialize * * Description: - * Configure the MPU to permit user-space access to only unrestricted SAM3/4 - * resources. + * Configure the MPU to permit user-space access to only unrestricted + * SAM3/4 resources. * ****************************************************************************/ diff --git a/arch/arm/src/samd5e5/sam_port.c b/arch/arm/src/samd5e5/sam_port.c index 02dc10ec562..2c340e4e652 100644 --- a/arch/arm/src/samd5e5/sam_port.c +++ b/arch/arm/src/samd5e5/sam_port.c @@ -44,12 +44,16 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO -static const char g_portchar[SAM_NPORTS] = { 'A', 'B', 'C', 'D' }; +static const char g_portchar[SAM_NPORTS] = +{ + 'A', 'B', 'C', 'D' +}; #endif /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /**************************************************************************** * Name: sam_portbase * @@ -103,6 +107,7 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset) bit = (1 << pin); /* Direction bit is already zero (input) */ + /* Enable the I/O synchronizer? */ if ((pinset & PORT_SYNCHRONIZER_MASK) == PORT_SYNCHRONIZER_ON) @@ -114,7 +119,8 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset) /* Set the pin configuration */ - regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_INEN); + regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | + PORT_WRCONFIG_INEN); if (pin >= 16) { /* Select the upper half word and adjust the bit setting */ @@ -137,6 +143,7 @@ static inline void sam_configinput(uintptr_t base, port_pinset_t pinset) putreg32(bit, base + SAM_PORT_OUTSET_OFFSET); } + /* Fall through */ case PORT_PULL_DOWN: @@ -186,7 +193,9 @@ static inline void sam_configinterrupt(uintptr_t base, port_pinset_t pinset) putreg32(regval, base + SAM_PORT_WRCONFIG_OFFSET); - /* Configure the interrupt edge sensitivity in CONFIGn register of the EIC */ + /* Configure the interrupt edge sensitivity in CONFIGn register of + * the EIC + */ sam_eic_configure(pin, pinset); @@ -234,7 +243,8 @@ static inline void sam_configoutput(uintptr_t base, port_pinset_t pinset) * buffer enabled. */ - regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_INEN); + regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | + PORT_WRCONFIG_INEN); if (pin > 16) { /* Select the upper half word and adjust the bit setting */ @@ -257,6 +267,7 @@ static inline void sam_configoutput(uintptr_t base, port_pinset_t pinset) putreg32(bit, base + SAM_PORT_OUTSET_OFFSET); } + /* Fall through */ case PORT_PULL_DOWN: @@ -318,7 +329,8 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset) * selected function. */ - regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_PMUXEN); + regval = (PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_WRPMUX | + PORT_WRCONFIG_PMUXEN); /* If pin is output with readback then enable the input buffer */ @@ -354,6 +366,7 @@ static inline void sam_configperiph(uintptr_t base, port_pinset_t pinset) putreg32(bit, base + SAM_PORT_OUTSET_OFFSET); } + /* Fall through */ case PORT_PULL_DOWN: @@ -517,13 +530,14 @@ bool sam_portread(port_pinset_t pinset) return (getreg32(base + SAM_PORT_IN_OFFSET) & pin) != 0; } -/************************************************************************************ +/**************************************************************************** * Function: sam_dumpport * * Description: - * Dump all PORT registers associated with the base address of the provided pinset. + * Dump all PORT registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpport(uint32_t pinset, const char *msg) diff --git a/arch/arm/src/samd5e5/sam_serial.h b/arch/arm/src/samd5e5/sam_serial.h index 4f30c5880a8..bf9ae9a2d6a 100644 --- a/arch/arm/src/samd5e5/sam_serial.h +++ b/arch/arm/src/samd5e5/sam_serial.h @@ -46,7 +46,7 @@ ****************************************************************************/ /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_SERIAL_H */ diff --git a/arch/arm/src/samd5e5/sam_spi.h b/arch/arm/src/samd5e5/sam_spi.h index 71e3e5fbe41..4d48f660481 100644 --- a/arch/arm/src/samd5e5/sam_spi.h +++ b/arch/arm/src/samd5e5/sam_spi.h @@ -104,15 +104,16 @@ struct spi_dev_s *sam_spibus_initialize(int port); * pins. * 2. Provide sam_spi[n]select() and sam_spi[n]status() functions in your * board-specific logic. These functions will perform chip selection - * and status operations using GPIOs in the way your board is configured. + * and status operations using GPIOs in the way your board is + * configured. * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide * sam_spi[n]cmddata() functions in your board-specific logic. This * function will perform cmd/data selection operations using GPIOs in * the way your board is configured. * 3. Add a call to sam_spibus_initialize() in your low level application * initialization logic - * 4. The handle returned by sam_spibus_initialize() may then be used to bind - * the SPI driver to higher level logic (e.g., calling + * 4. The handle returned by sam_spibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * diff --git a/arch/arm/src/samd5e5/sam_start.h b/arch/arm/src/samd5e5/sam_start.h index e93f6b2910d..e2b84d8de79 100644 --- a/arch/arm/src/samd5e5/sam_start.h +++ b/arch/arm/src/samd5e5/sam_start.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/sam_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_START_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_START_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_board_initialize * * Description: - * All SAMD5/E5 architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * All SAMD5/E5 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after clocking + * and memory have been configured but before caches have been enabled and + * before any devices have been initialized. * - ************************************************************************************/ + ****************************************************************************/ void sam_board_initialize(void); diff --git a/arch/arm/src/samd5e5/sam_usart.h b/arch/arm/src/samd5e5/sam_usart.h index 16246c5f99f..2e69f600319 100644 --- a/arch/arm/src/samd5e5/sam_usart.h +++ b/arch/arm/src/samd5e5/sam_usart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/sam_usart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_USART_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_USART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -38,9 +38,9 @@ #include "sam_config.h" #include "sam_port.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Pick the console USART configuration */ @@ -64,9 +64,10 @@ # undef g_consoleconfig #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* This structure describes the static configuration of a USART */ struct sam_usart_config_s @@ -90,28 +91,29 @@ struct sam_usart_config_s uintptr_t base; /* SERCOM base address */ }; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_wait_synchronization * * Description: * Return true is the SERCOM USART reports that it is synchronizing. * - ***********************************************************************************/ + ****************************************************************************/ #ifdef SAMD5E5_HAVE_USART -static inline bool usart_syncbusy(const struct sam_usart_config_s * const config) +static inline +bool usart_syncbusy(const struct sam_usart_config_s * const config) { return false; } #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -158,9 +160,9 @@ EXTERN const struct sam_usart_config_s g_usart7config; EXTERN const struct sam_usart_config_s *g_usartconfig[SAMD5E5_NSERCOM]; -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samd5e5/sam_userspace.h b/arch/arm/src/samd5e5/sam_userspace.h index a97acac007f..b6d3f53910d 100644 --- a/arch/arm/src/samd5e5/sam_userspace.h +++ b/arch/arm/src/samd5e5/sam_userspace.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samd5e5/sam_userspace.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_USERSPACE_H #define __ARCH_ARM_SRC_SAMD5E5_SAM_USERSPACE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -34,23 +34,23 @@ #include "arm_internal.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -61,9 +61,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_userspace diff --git a/arch/arm/src/samv7/chip.h b/arch/arm/src/samv7/chip.h index 96eb970b02d..0becd1ca0ed 100644 --- a/arch/arm/src/samv7/chip.h +++ b/arch/arm/src/samv7/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,19 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_CHIP_H #define __ARCH_ARM_SRC_SAMV7_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the memory map and the chip definitions file. Other chip hardware files - * should then include this file for the proper setup. +/* Include the memory map and the chip definitions file. + * Other chip hardware files should then include this file for the proper + * setup. */ #include @@ -48,20 +49,20 @@ #define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */ #define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_CHIP_H */ diff --git a/arch/arm/src/samv7/hardware/sam_afec.h b/arch/arm/src/samv7/hardware/sam_afec.h index 4e1b896af83..10764b33ae0 100644 --- a/arch/arm/src/samv7/hardware/sam_afec.h +++ b/arch/arm/src/samv7/hardware/sam_afec.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_afec.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_AFEC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_AFEC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General definitions ******************************************************************/ + ****************************************************************************/ + +/* General definitions ******************************************************/ #define SAM_ADC_NCHANNELS 12 /* 12 ADC Channels */ -/* AFEC register offsets ****************************************************************/ +/* AFEC register offsets ****************************************************/ #define SAM_AFEC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_AFEC_MR_OFFSET 0x0004 /* Mode Register */ @@ -78,7 +79,7 @@ /* 0x00ec-0x00f8 Reserved */ /* 0x0fc Reserved */ -/* AFEC register addresses **************************************************************/ +/* AFEC register addresses **************************************************/ #define SAM_AFEC0_CR (SAM_AFEC0_BASE+SAM_AFEC_CR_OFFSET) #define SAM_AFEC0_MR (SAM_AFEC0_BASE+SAM_AFEC_MR_OFFSET) @@ -142,7 +143,7 @@ #define SAM_AFEC1_WPMR (SAM_AFEC1_BASE+SAM_AFEC_WPMR_OFFSET) #define SAM_AFEC1_WPSR (SAM_AFEC1_BASE+SAM_AFEC_WPSR_OFFSET) -/* AFEC register bit definitions *******************************************************/ +/* AFEC register bit definitions ********************************************/ /* Control Register */ @@ -161,6 +162,7 @@ # define AFEC_MR_TRGSEL_PWM0 (4 << AFEC_MR_TRGSEL_SHIFT) /* PWM Event Line 0 */ # define AFEC_MR_TRGSEL_PWM1 (5 << AFEC_MR_TRGSEL_SHIFT) /* PWM Event Line 1 */ # define AFEC_MR_TRGSEL_ACMP (6 << AFEC_MR_TRGSEL_SHIFT) /* Analog comparator */ + #define AFEC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ #define AFEC_MR_FWUP (1 << 6) /* Bit 6: Fast Wake Up */ #define AFEC_MR_FREERUN (1 << 7) /* Bit 7: Free Run Mode */ @@ -185,12 +187,14 @@ # define AFEC_MR_STARTUP_832 (13 << AFEC_MR_STARTUP_SHIFT) /* 832 periods of ADCClock */ # define AFEC_MR_STARTUP_896 (14 << AFEC_MR_STARTUP_SHIFT) /* 896 periods of ADCClock */ # define AFEC_MR_STARTUP_960 (15 << AFEC_MR_STARTUP_SHIFT) /* 960 periods of ADCClock */ + #define AFEC_MR_SETTLING_SHIFT (20) /* Bits 20-21: Analog Settling Time */ #define AFEC_MR_SETTLING_MASK (15 << AFEC_MR_SETTLING_SHIFT) # define AFEC_MR_SETTLING_3 (0 << AFEC_MR_SETTLING_SHIFT) /* 3 periods of ADCClock */ # define AFEC_MR_SETTLING_5 (1 << AFEC_MR_SETTLING_SHIFT) /* 5 periods of ADCClock */ # define AFEC_MR_SETTLING_9 (2 << AFEC_MR_SETTLING_SHIFT) /* 9 periods of ADCClock */ # define AFEC_MR_SETTLING_17 (3 << AFEC_MR_SETTLING_SHIFT) /* 17 periods of ADCClock */ + #define AFEC_MR_ONE (1 << 23) /* Bit 23: Must be one */ #define AFEC_MR_TRACKTIM_SHIFT (24) /* Bits 24-27: Tracking Time */ #define AFEC_MR_TRACKTIM_MASK (15 << AFEC_MR_TRACKTIM_SHIFT) @@ -208,6 +212,7 @@ # define AFEC_EMR_CMPMODE_HIGH (1 << AFEC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */ # define AFEC_EMR_CMPMODE_IN (2 << AFEC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */ # define AFEC_EMR_CMPMODE_OUT (3 << AFEC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */ + #define AFEC_EMR_CMPSEL_SHIFT (3) /* Bit 3-7: Comparison Selected Channel */ #define AFEC_EMR_CMPSEL_MASK (31 << AFEC_EMR_CMPSEL_SHIFT) # define AFEC_EMR_CMPSEL(n) ((uint32_t)(n) << AFEC_EMR_CMPSEL_SHIFT) @@ -222,6 +227,7 @@ # define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */ # define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */ # define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */ + #define AFEC_EMR_TAG (1 << 24) /* Bit 24: TAG of the AFEC_LDCR register */ #define AFEC_EMR_STM (1 << 25) /* Bit 25: Single Trigger Mode */ #define AFEC_EMR_SIGNMODE_SHIFT (28) /* Bits 28-29: Sign mode */ @@ -317,7 +323,9 @@ #define AFEC_LCDR_CHANB_SHIFT (24) /* Bits 24-27: Channel number */ #define AFEC_LCDR_CHANB_MASK (15 << AFEC_LCDR_CHANB_SHIFT) -/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Registers */ +/* Interrupt Enable, Interrupt Disable, Interrupt Mask, + * and Interrupt Status Registers + */ #define AFEC_INT_EOC(n) (1 << (n)) # define AFEC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */ @@ -408,7 +416,9 @@ #define AFEC_CGR_GAIN11_MASK (3 << AFEC_CGR_GAIN11_SHIFT) # define AFEC_CGR_GAIN11(v) ((uint32_t)(v) << AFEC_CGR_GAIN11_SHIFT) -/* Channel Calibration DC Offset Register (Used in Automatic Calibration Procedure) */ +/* Channel Calibration DC Offset Register + * (Used in Automatic Calibration Procedure) + */ #define AFEC_CDOR_OFF(n) (1 << (n)) # define AFEC_CDOR_OFF0 (1 << 0) /* Bit 0: Offset for channel 0 */ @@ -539,16 +549,16 @@ #define AFEC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define AFEC_WPSR_WPVSRC_MASK (0x0000ffff << AFEC_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_AFEC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_chipid.h b/arch/arm/src/samv7/hardware/sam_chipid.h index 3379e86869b..cda948bae7b 100644 --- a/arch/arm/src/samv7/hardware/sam_chipid.h +++ b/arch/arm/src/samv7/hardware/sam_chipid.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_chipid.h * CHIPID Register Definitions for the SAMV7 * @@ -32,34 +32,34 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_CHIPID_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_CHIPID_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* CHIPID register offsets **************************************************************/ +/* CHIPID register offsets **************************************************/ #define SAM_CHIPID_CIDR_OFFSET 0x00 /* Chip ID Register */ #define SAM_CHIPID_EXID_OFFSET 0x04 /* Chip ID Extension Register */ -/* CHIPID register addresses ************************************************************/ +/* CHIPID register addresses ************************************************/ #define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR_OFFSET) #define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID_OFFSET) -/* CHIPID register bit definitions ******************************************************/ +/* CHIPID register bit definitions ******************************************/ #define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */ #define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT) @@ -73,6 +73,7 @@ # define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */ # define CHIPID_CIDR_EPROC_CORTEXA5 (6 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-A5 */ # define CHIPID_CIDR_EPROC_CORTEXM4 (7 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M4 */ + #define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */ #define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) # define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ @@ -85,6 +86,7 @@ # define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ # define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ # define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ + #define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */ #define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) # define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ @@ -97,6 +99,7 @@ # define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ # define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ # define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ + #define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */ #define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) # define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ @@ -115,6 +118,7 @@ # define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */ # define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */ # define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */ + #define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */ #define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT) # define CHIPID_CIDR_ARCH_SAME70 (0x10 << CHIPID_CIDR_ARCH_SHIFT) /* SAM E70 Series */ @@ -162,6 +166,7 @@ # define CHIPID_CIDR_ARCH_SAM4LB (0xb1 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxB Series */ # define CHIPID_CIDR_ARCH_SAM4LC (0xb2 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxC Series */ # define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ + #define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ #define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) # define CHIPID_CIDR_NVPTYP_ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ @@ -169,18 +174,19 @@ # define CHIPID_CIDR_NVPTYP_SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ # define CHIPID_CIDR_NVPTYP_EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ # define CHIPID_CIDR_NVPTYP_REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ + #define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_CHIPID_H */ diff --git a/arch/arm/src/samv7/hardware/sam_dacc.h b/arch/arm/src/samv7/hardware/sam_dacc.h index 46ca3065c35..f67a976ce6f 100644 --- a/arch/arm/src/samv7/hardware/sam_dacc.h +++ b/arch/arm/src/samv7/hardware/sam_dacc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_dacc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_DACC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_DACC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* DACC register offsets *****************************************************************/ +/* DACC register offsets ****************************************************/ #define SAM_DACC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_DACC_MR_OFFSET 0x0004 /* Mode Register */ @@ -52,7 +52,7 @@ #define SAM_DACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode register */ #define SAM_DACC_WPSR_OFFSET 0x00e8 /* Write Protect Status register */ -/* DACC register addresses **************************************************************/ +/* DACC register addresses **************************************************/ #define SAM_DACC_CR (SAM_DACC_BASE+SAM_DACC_CR_OFFSET) #define SAM_DACC_MR (SAM_DACC_BASE+SAM_DACC_MR_OFFSET) @@ -70,7 +70,7 @@ #define SAM_DACC_WPMR (SAM_DACC_BASE+SAM_DACC_WPMR_OFFSET) #define SAM_DACC_WPSR (SAM_DACC_BASE+SAM_DACC_WPSR_OFFSET) -/* DACC register bit definitions ********************************************************/ +/* DACC register bit definitions ********************************************/ /* Control Register */ @@ -78,16 +78,16 @@ /* Mode Register */ -#define DACC_MR_MAXS0 (1 << 0) /* Max Speed Mode for Channel 0 */ -# define DACC_MR_MAXS0_TRIG_EVENT (0 << 0) /* External trigger mode or Free-running mode enabled */ -# define DACC_MR_MAXS0_MAXIMUM (1 << 0) /* Max speed mode enabled */ -#define DACC_MR_MAXS1 (1 << 1) /* Max Speed Mode for Channel 1 */ -# define DACC_MR_MAXS1_TRIG_EVENT (0 << 1) /* External trigger mode or Free-running mode enabled */ -# define DACC_MR_MAXS1_MAXIMUM (1 << 1) /* Max speed mode enabled */ -#define DACC_MR_WORD (1 << 4) /* Word Transfer Mode */ -# define DACC_MR_WORD_DISABLED (0 << 4) /* One data to convert is written to the FIFO per access to DACC */ -# define DACC_MR_WORD_ENABLED (1 << 4) /* Two data to convert are written to the FIFO per access to DACC */ -#define DACC_MR_ZERO (1 << 5) /* Must always be written to 0 */ +#define DACC_MR_MAXS0 (1 << 0) /* Max Speed Mode for Channel 0 */ +# define DACC_MR_MAXS0_TRIG_EVENT (0 << 0) /* External trigger mode or Free-running mode enabled */ +# define DACC_MR_MAXS0_MAXIMUM (1 << 0) /* Max speed mode enabled */ +#define DACC_MR_MAXS1 (1 << 1) /* Max Speed Mode for Channel 1 */ +# define DACC_MR_MAXS1_TRIG_EVENT (0 << 1) /* External trigger mode or Free-running mode enabled */ +# define DACC_MR_MAXS1_MAXIMUM (1 << 1) /* Max speed mode enabled */ +#define DACC_MR_WORD (1 << 4) /* Word Transfer Mode */ +# define DACC_MR_WORD_DISABLED (0 << 4) /* One data to convert is written to the FIFO per access to DACC */ +# define DACC_MR_WORD_ENABLED (1 << 4) /* Two data to convert are written to the FIFO per access to DACC */ +#define DACC_MR_ZERO (1 << 5) /* Must always be written to 0 */ #define DACC_MR_DIFF (1 << 23) /* Differential Mode */ # define DACC_MR_DIFF_DISABLED (0 << 23) /* DAC0 and DAC1 are single-ended outputs */ # define DACC_MR_DIFF_ENABLED (1 << 23) /* DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ @@ -176,12 +176,14 @@ #define DACC_CDR_DATA1_MASK (0xffffu << DACC_CDR_DATA1_SHIFT) /* Data to Convert for channel 1 */ #define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_MASK & ((value) << DACC_CDR_DATA1_SHIFT))) -/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */ +/* Interrupt Enable, Interrupt Disable, + * Interrupt Mask, and Interrupt Status Register + */ -#define DACC_INT_TXRDY0 (1 << 0) /* Transmit Ready Interrupt of channel 0 */ -#define DACC_INT_TXRDY1 (1 << 1) /* Transmit Ready Interrupt of channel 1 */ -#define DACC_INT_EOC0 (1 << 4) /* End of Conversion Interrupt of channel 0 */ -#define DACC_INT_EOC1 (1 << 5) /* End of Conversion Interrupt of channel 1 */ +#define DACC_INT_TXRDY0 (1 << 0) /* Transmit Ready Interrupt of channel 0 */ +#define DACC_INT_TXRDY1 (1 << 1) /* Transmit Ready Interrupt of channel 1 */ +#define DACC_INT_EOC0 (1 << 4) /* End of Conversion Interrupt of channel 0 */ +#define DACC_INT_EOC1 (1 << 5) /* End of Conversion Interrupt of channel 1 */ #define DACC_INT_ALL (0xffffffffu) /* All interrupts */ /* Analog Current Register */ diff --git a/arch/arm/src/samv7/hardware/sam_eefc.h b/arch/arm/src/samv7/hardware/sam_eefc.h index c43606a99a7..8aa8a80370b 100644 --- a/arch/arm/src/samv7/hardware/sam_eefc.h +++ b/arch/arm/src/samv7/hardware/sam_eefc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_eefc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EEFC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EEFC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* EEFC register offsets ****************************************************************/ +/* EEFC register offsets ****************************************************/ #define SAM_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */ #define SAM_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */ @@ -42,7 +42,7 @@ #define SAM_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */ #define SAM_EEFC_WPMR_OFFSET 0xec /* EEFC Write Protection Mode Register */ -/* EEFC register addresses **************************************************************/ +/* EEFC register addresses **************************************************/ #define SAM_EEFC_FMR (SAM_EEFC_BASE+SAM_EEFC_FMR_OFFSET) #define SAM_EEFC_FCR (SAM_EEFC_BASE+SAM_EEFC_FCR_OFFSET) @@ -50,7 +50,8 @@ #define SAM_EEFC_FRR (SAM_EEFC_BASE+SAM_EEFC_FRR_OFFSET) #define SAM_EEFC_WPMR (SAM_EEFC_BASE+SAM_EEFC_WPMR_OFFSET) -/* EEFC register bit definitions ********************************************************/ +/* EEFC register bit definitions ********************************************/ + /* EEFC Flash Mode Register */ #define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ @@ -108,6 +109,7 @@ # define EEFC_FCR_FCMD_EUS (19 << EEFC_FCR_FCMD_SHIFT) /* Erase User Signature */ # define EEFC_FCR_FCMD_STUS (20 << EEFC_FCR_FCMD_SHIFT) /* Start Read User Signature */ # define EEFC_FCR_FCMD_SPUS (21 << EEFC_FCR_FCMD_SHIFT) /* Stop Read User Signature */ + #define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */ #define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) # define EEFC_FCR_FARG(arg) ((uint32_t)(arg) << EEFC_FCR_FARG_SHIFT) @@ -135,16 +137,16 @@ #define EEFC_WPMR_WPKEY_MASK (0x00ffffff << EEFC_WPMR_WPKEY_SHIFT) # define EEFC_WPMR_WPKEY (0x00454643 << EEFC_WPMR_WPKEY_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EEFC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_emac.h b/arch/arm/src/samv7/hardware/sam_emac.h index 04d25aa8a0a..c9664036c5c 100644 --- a/arch/arm/src/samv7/hardware/sam_emac.h +++ b/arch/arm/src/samv7/hardware/sam_emac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_emac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,19 +16,19 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* This is the form of the EMAC interface used the SAMV7. - * This is referred as GMAC in the documentation even though it does not support - * Gibabit Ethernet. + * This is referred as GMAC in the documentation even though it does not + * support Gibabit Ethernet. */ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EMAC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -37,10 +37,11 @@ #if SAMV7_NEMAC > 0 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* EMAC Register Offsets ************************************************************/ + ****************************************************************************/ + +/* EMAC Register Offsets ****************************************************/ #define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */ #define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */ @@ -83,6 +84,7 @@ #define SAM_EMAC_SAMB1_OFFSET 0x00c8 /* Specific Address 1 Mask Bottom [31:0] Register */ #define SAM_EMAC_SAMT1_OFFSET 0x00cc /* Specific Address 1 Mask Top [47:32] Register */ /* 0x00d0-0xd8: Reserved */ + /* PTP/1588 Timer Registers */ #define SAM_EMAC_NSC_OFFSET 0x00dc /* 1588 Timer Nanosecond Comparison Register */ @@ -92,7 +94,8 @@ #define SAM_EMAC_EFRSH_OFFSET 0x00ec /* PTP Event Frame Received Seconds High Register */ #define SAM_EMAC_PEFTSH_OFFSET 0x00f0 /* PTP Peer Event Frame Transmitted Seconds High Register */ #define SAM_EMAC_PEFRSH_OFFSET 0x00f4 /* PTP Peer Event Frame Received Seconds High Register */ - /*0x00f8-0x00fc: Reserved */ + /* 0x00f8-0x00fc: Reserved */ + /* Statistics registers */ #define SAM_EMAC_OTLO_OFFSET 0x0100 /* Octets Transmitted [31:0] Register */ @@ -141,6 +144,7 @@ #define SAM_EMAC_TCE_OFFSET 0x01ac /* TCP Checksum Errors Register */ #define SAM_EMAC_UCE_OFFSET 0x01b0 /* UDP Checksum Errors Register */ /* 0x01b4-0x01b8: Reserved */ + /* PTP/1588 Timer Registers */ #define SAM_EMAC_TISUBN_OFFSET 0x01bc /* 1588 Timer Increment Sub-nanoseconds Register */ @@ -158,15 +162,16 @@ #define SAM_EMAC_PEFRSL_OFFSET 0x01f8 /* PTP Peer Event Frame Received Seconds Low */ #define SAM_EMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */ /* 0x0200-0x03fc: Reserved */ + /* Priority Queue */ #define SAM_EMAC_ISRPQ_ISRPQ_OFFSET(n) (0x03fc+((n)<<2)) /* Interrupt Status Register Priority Queue, n=1-3 */ #define SAM_EMAC_ISRPQ_TBQBAPQ_OFFSET(n) (0x043c+((n)<<2)) /* Transmit Buffer Queue Base Address Register Priority Queue, n=1-3 */ #define SAM_EMAC_ISRPQ_RBQBAPQ_OFFSET(n) (0x047c+((n)<<2)) /* Receive Buffer Queue Base Address Register Priority Queue, n=1-3 */ #define SAM_EMAC_ISRPQ_RBSRPQ_OFFSET(n) (0x049c+((n)<<2)) /* Receive Buffer Size Register Priority Queue, n=1-3 */ -#define SAM_EMAC_ISRPQ_CBSCR_OFFSET 0x04bc /* Credit-Based Shaping Control Register */ -#define SAM_EMAC_ISRPQ_CBSISQA_OFFSET 0x04c0 /* Credit-Based Shaping IdleSlope Register for Queue A */ -#define SAM_EMAC_ISRPQ_CBSISQB_OFFSET 0x04c4 /* Credit-Based Shaping IdleSlope Register for Queue B */ +#define SAM_EMAC_ISRPQ_CBSCR_OFFSET 0x04bc /* Credit-Based Shaping Control Register */ +#define SAM_EMAC_ISRPQ_CBSISQA_OFFSET 0x04c0 /* Credit-Based Shaping IdleSlope Register for Queue A */ +#define SAM_EMAC_ISRPQ_CBSISQB_OFFSET 0x04c4 /* Credit-Based Shaping IdleSlope Register for Queue B */ #define SAM_EMAC_ISRPQ_ST1RPQ_OFFSET(n) (0x0500+((n)<<2)) /* Screening Type 1 Register Priority Queue, 0=1-3 */ #define SAM_EMAC_ISRPQ_ST2RPQ_OFFSET(n) (0x0540+((n)<<2)) /* Screening Type 2 Register Priority Queue, 0=1-7 */ #define SAM_EMAC_ISRPQ_IERPQ_OFFSET(n) (0x05fc+((n)<<2)) /* Interrupt Enable Register Priority Queue, n=1-3 */ @@ -176,7 +181,7 @@ #define SAM_EMAC_ISRPQ_ST2CW0_OFFSET(n) (0x0700+((n)<<3)) /* Screening Type 2 Compare Word 0 Registerm, n=0-23 */ #define SAM_EMAC_ISRPQ_ST2CW1_OFFSET(n) (0x0704+((n)<<3)) /* Screening Type 2 Compare Word 1 Register, n=0-23 */ -/* EMAC Register Addresses **********************************************************/ +/* EMAC Register Addresses **************************************************/ /* EMAC0 base addresses */ @@ -448,7 +453,7 @@ # define SAM_EMAC1_ISRPQ_ST2CW1(n) (SAM_EMAC1_BASE+SAM_EMAC_ISRPQ_ST2CW1_OFFSET(n)) #endif -/* EMAC Register Bit Definitions ****************************************************/ +/* EMAC Register Bit Definitions ********************************************/ /* Network Control Register */ @@ -489,6 +494,7 @@ # define EMAC_NCFGR_RXBUFO_1 (1 << EMAC_NCFGR_RXBUFO_SHIFT) /* One-byte offset from RX buffer start */ # define EMAC_NCFGR_RXBUFO_2 (2 << EMAC_NCFGR_RXBUFO_SHIFT) /* Two-byte offset from RX buffer start */ # define EMAC_NCFGR_RXBUFO_3 (3 << EMAC_NCFGR_RXBUFO_SHIFT) /* Three-byte offset fromRX buffer start */ + #define EMAC_NCFGR_LFERD (1 << 16) /* Bit 16: Length Field Error Frame Discard */ #define EMAC_NCFGR_RFCS (1 << 17) /* Bit 17: Remove FCS */ #define EMAC_NCFGR_CLK_SHIFT (18) /* Bits 18-20: MDC clock divider */ @@ -499,9 +505,11 @@ # define EMAC_NCFGR_CLK_DIV48 (3 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */ # define EMAC_NCFGR_CLK_DIV64 (4 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */ # define EMAC_NCFGR_CLK_DIV96 (5 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */ + #define EMAC_NCFGR_DBW_SHIFT (21) /* Bit 21-22: Data Bus Width */ #define EMAC_NCFGR_DBW_MASK (3 << EMAC_NCFGR_DBW_SHIFT) # define EMAC_NCFGR_DBW_ZERO (0 << EMAC_NCFGR_DBW_SHIFT) /* Must be zero */ + #define EMAC_NCFGR_DCPF (1 << 23) /* Bit 23: Disable Copy of Pause Frames */ #define EMAC_NCFGR_RXCOEN (1 << 24) /* Bit 24: Receive Checksum Offload Enable */ #define EMAC_NCFGR_EFRHD (1 << 25) /* Bit 25: Enable Frames Received in Half Duplex */ @@ -523,10 +531,11 @@ #define EMAC_DCFGR_FBLDO_SHIFT (0) /* Bits 0-4: Fixed Burst Length for DMA Data Operations */ #define EMAC_DCFGR_FBLDO_MASK (31 << EMAC_DCFGR_FBLDO_SHIFT) -# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */ -# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */ -# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */ +# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */ +# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */ +# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */ # define EMAC_DCFGR_FBLDO_INCR16 (16 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR16 AHB bursts */ + #define EMAC_DCFGR_ESMA (1 << 6) /* Bit 6: Endian Swap Mode Enable for Management Descriptor Accesses */ #define EMAC_DCFGR_ESPA (1 << 7) /* Bit 7: Endian Swap Mode Enable for Packet Data Accesses */ #define EMAC_DCFGR_RXBMS_SHIFT (8) /* Bits 8-9: Receiver Packet Buffer Memory Size Select */ @@ -535,6 +544,7 @@ # define EMAC_DCFGR_RXBMS_4TH (1 << EMAC_DCFGR_RXBMS_SHIFT) /* 4/4 Kbytes Memory Size */ # define EMAC_DCFGR_RXBMS_HALF (2 << EMAC_DCFGR_RXBMS_SHIFT) /* 4/2 Kbytes Memory Size */ # define EMAC_DCFGR_RXBMS_FULL (3 << EMAC_DCFGR_RXBMS_SHIFT) /* 4 Kbytes Memory Size */ + #define EMAC_DCFGR_TXPBMS (1 << 10) /* Bit 10: Transmitter Packet Buffer Memory Size Select */ #define EMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */ #define EMAC_DCFGR_DRBS_SHIFT (16) /* Bits 16-23: DMA Receive Buffer Size */ @@ -567,7 +577,9 @@ #define EMAC_RSR_RXOVR (1 << 2) /* Bit 2: Receive Overrun */ #define EMAC_RSR_HNO (1 << 3) /* Bit 3: HRESP Not OK */ -/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) */ +/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), + * Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) + */ #define EMAC_INT_MFS (1 << 0) /* Bit 0: Management Frame Sent */ #define EMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */ @@ -645,24 +657,29 @@ #define EMAC_RJFML_MASK 0x00003fff /* Bits 0-13: Frame Max Length */ /* Hash Register Bottom [31:0] Register (LS 32-bit hash address) */ + /* Hash Register Top [63:32] Register (MS 32-bit hash address) */ /* Specific Address 1 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 1 Top [47:32] Register */ #define EMAC_SAT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 2 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 2 Top [47:32] Register */ #define EMAC_SAT2_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 3 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 3 Top [47:32] Register */ #define EMAC_SAT3_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ /* Specific Address 4 Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 4 Top [47:32] Register */ #define EMAC_SAT4_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */ @@ -709,6 +726,7 @@ # define EMAC_TPFCP_PQ(n) ((uint32_t)(n) << EMAC_TPFCP_PQ_SHIFT) /* Specific Address 1 Mask Bottom [31:0] Register (LS 32-bit address) */ + /* Specific Address 1 Mask Top [47:32] Register (MS 16-bit address) */ #define EMAC_SAMT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of Specific Address 1 Mask */ @@ -718,6 +736,7 @@ #define EMAC_NSC_MASK (0x00cfffff) /* Bits 0-21: 1588 Timer Nanosecond Comparison Value */ /* 1588 Timer Second Comparison Low Register (32-bit value) */ + /* 1588 Timer Second Comparison High Register */ #define EMAC_SCH_MASK (0x0000ffff) /* Bits 0-15: 1588 Timer Second Comparison Value */ @@ -794,7 +813,9 @@ #define EMAC_TISUBN_MASK (0x0000ffff) /* Bits 0-15: LS Bits of Timer Increment Register */ /* 1588 Timer Seconds High Register (32-bit timer value) */ + /* 1588 Timer Seconds Low Register (32-bit timer value) */ + /* 1588 Timer Nanoseconds Register (30-bit timer value) */ #define EMAC_TN_MASK (0x3fffffff) /* Bit 0-29: Timer Count in Nanoseconds */ @@ -819,27 +840,33 @@ # define EMAC_TI_NIT(n) ((uint32_t)(n) << EMAC_TI_NIT_SHIFT) /* PTP Event Frame Transmitted Seconds Low (32-bit timer value) */ + /* PTP Event Frame Transmitted Nanoseconds (30-bit timer value) */ #define EMAC_EFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Event Frame Received Seconds Low (32-bit timer value) */ + /* PTP Event Frame Received Nanoseconds (30-bit timer value) */ #define EMAC_EFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Peer Event Frame Transmitted Seconds Low (32-bit timer value) */ + /* PTP Peer Event Frame Transmitted Nanoseconds (30-bit timer value) */ #define EMAC_PEFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ /* PTP Peer Event Frame Received Seconds Low (32-bit timer value) */ + /* PTP Peer Event Frame Received Nanoseconds (30-bit timer value) */ #define EMAC_PEFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */ -/* Interrupt Status Register Priority Queue, Interrupt Enable Register Priority Queue, - * Interrupt Disable Register Priority Queue, and Interrupt Mask Register Priority Queue, +/* Interrupt Status Register Priority Queue, + * Interrupt Enable Register Priority Queue, + * Interrupt Disable Register Priority Queue, + * and Interrupt Mask Register Priority Queue, * n=1-3 * * This register uses a subset of the standard interrupt definitions: @@ -847,7 +874,8 @@ * EMAC_INT_RCOMP Bit 1: Receive Complete * EMAC_INT_RXUBR Bit 2: Receive Used Bit Read * EMAC_INT_RLEX Bit 5: Retry Limit Exceeded - * EMAC_INT_TFC Bit 6: Transmit Frame Corruption due to AHB error + * EMAC_INT_TFC Bit 6: Transmit Frame Corruption due + * to AHB error * EMAC_INT_TCOMP Bit 7: Transmit Complete * EMAC_INT_ROVR Bit 10: Receive Overrun * EMAC_INT_HRESP Bit 11: Hresp not OK @@ -874,6 +902,7 @@ #define EMAC_ISRPQ_CBSCR_QBE (1 << 1) /* Bit 1: Queue B CBS Enable */ /* Credit-Based Shaping IdleSlope Register for Queue A (32-bit value) */ + /* Credit-Based Shaping IdleSlope Register for Queue B (32-bit value) */ /* Screening Type 1 Register Priority Queue, 0=1-3 */ @@ -941,12 +970,12 @@ # define EMAC_ISRPQ_ST2CW1_STRT_IP (2 << EMAC_ISRPQ_ST2CW1_STRT_SHIFT) /* Offset from the byte after the IP header field */ # define EMAC_ISRPQ_ST2CW1_STRT_TCPUDP (3 << EMAC_ISRPQ_ST2CW1_STRT_SHIFT) /* Offset from the byte after the TCP/UDP header field */ -/* Descriptors **********************************************************************/ +/* Descriptors **************************************************************/ /* Receive buffer descriptor: Address word */ -#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */ -#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ +#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */ +#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */ #define EMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */ /* Receive buffer descriptor: Control word */ @@ -963,20 +992,22 @@ #define EMACRXD_STA_VLPRIO_MASK (7 << EMACRXD_STA_VLANPRIO_SHIFT) #define EMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */ #define EMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */ -#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */ +#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */ #define EMACRXD_STA_TYPEID_MASK (3 << EMACRXD_STA_TYPEID_SHIFT) # define EMACRXD_STA_TYPEID1 (0 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 1 match */ # define EMACRXD_STA_TYPEID2 (1 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 2 match */ # define EMACRXD_STA_TYPEID3 (2 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 3 match */ # define EMACRXD_STA_TYPEID4 (3 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 4 match */ + #define EMACRXD_STA_TYPEIDMATCH (1 << 24) /* Bit 24: Type ID register match found */ #define EMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */ -#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */ +#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */ #define EMACRXD_STA_ADDR_MASK (3 << EMACRXD_STA_ADDR_SHIFT) # define EMACRXD_STA_ADDR1 (0 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */ # define EMACRXD_STA_ADDR2 (1 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ # define EMACRXD_STA_ADDR3 (2 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ # define EMACRXD_STA_ADDR4 (3 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ + #define EMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific address match found */ /* Bit 28: Reserved */ #define EMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */ @@ -984,6 +1015,7 @@ #define EMACRXD_STA_BCAST (1 << 31) /* Bit 31: Global all ones broadcast address detected */ /* Transmit buffer descriptor: Address word (un-aligned, 32-bit address */ + /* Transmit buffer descriptor: Control word */ #define EMACTXD_STA_BUFLEN_SHIFT (0) /* Bits 0-13: Length of buffer */ @@ -1002,6 +1034,7 @@ # define EMACTXD_STA_CHKERR_BADFRAG (5 << EMACTXD_STA_CHKERR_SHIFT) /* Unsupported fragmentation */ # define EMACTXD_STA_CHKERR_PKTTYPE (6 << EMACTXD_STA_CHKERR_SHIFT) /* Not TCP or UDP */ # define EMACTXD_STA_CHKERR_EPKT (7 << EMACTXD_STA_CHKERR_SHIFT) /* Premature end of packet */ + /* Bits 23-25: Reserved */ #define EMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision, transmit error detected */ #define EMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit frame corruption due to AHB error */ @@ -1010,9 +1043,10 @@ #define EMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */ #define EMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the EMAC to read from buffer */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* Receive buffer descriptor */ struct emac_rxdesc_s diff --git a/arch/arm/src/samv7/hardware/sam_hsmci.h b/arch/arm/src/samv7/hardware/sam_hsmci.h index e15df7d2f90..129706ea536 100644 --- a/arch/arm/src/samv7/hardware/sam_hsmci.h +++ b/arch/arm/src/samv7/hardware/sam_hsmci.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_hsmci.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_HSMCI_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_HSMCI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include @@ -32,11 +32,11 @@ #if SAMV7_NHSMCI4 > 0 -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* HSMCI register offsets ***************************************************************/ +/* HSMCI register offsets ***************************************************/ #define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */ @@ -66,7 +66,7 @@ /* 0x0100-0x0124: Reserved for PCD registers */ #define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x05fc FIFO Memory Aperture */ -/* HSMCI register addresses *************************************************************/ +/* HSMCI register addresses *************************************************/ #define SAM_HSMCI0_CR (SAM_HSMCI0_BASE+SAM_HSMCI_CR_OFFSET) #define SAM_HSMCI0_MR (SAM_HSMCI0_BASE+SAM_HSMCI_MR_OFFSET) @@ -144,7 +144,7 @@ # define SAM_HSMCI2_FIFO (SAM_HSMCI2_BASE+SAM_HSMCI_FIFO_OFFSET) #endif -/* HSMCI register bit definitions *******************************************************/ +/* HSMCI register bit definitions *******************************************/ /* HSMCI Control Register */ @@ -188,11 +188,13 @@ /* HSMCI SDCard/SDIO Register */ #define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */ + #define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT) /* Slot A is selected */ # define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */ # define HSMCI_SDCR_SDCSEL_SLOTB (1 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */ # define HSMCI_SDCR_SDCSEL_SLOTC (2 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */ # define HSMCI_SDCR_SDCSEL_SLOTD (3 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */ + #define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */ #define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT) # define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT) @@ -211,6 +213,7 @@ # define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */ # define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */ # define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */ + #define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */ #define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT) # define HSMCI_CMDR_SPCMD_STD (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */ @@ -221,6 +224,7 @@ # define HSMCI_CMDR_SPCMD_ITRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */ # define HSMCI_CMDR_SPCMD_BOR (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */ # define HSMCI_CMDR_SPCMD_EBO (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */ + #define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */ #define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */ #define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */ @@ -228,6 +232,7 @@ # define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */ # define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */ # define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */ + #define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */ # define HSMCI_CMDR_TRDIR_WRITE (0 << 18) # define HSMCI_CMDR_TRDIR_READ (1 << 18) @@ -238,11 +243,13 @@ # define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */ # define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */ # define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */ + #define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */ #define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT) # define HSMCI_CMDR_IOSPCMD_STD (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */ # define HSMCI_CMDR_IOSPCMD_SUSPEND (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ # define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ + #define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ #define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */ @@ -272,11 +279,14 @@ # define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) /* HSMCI Response Registers (32-bit data) */ + /* HSMCI Receive Data Registers (32-bit data) */ + /* HSMCI Transmit Data Registers (32-bit data) */ -/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable - * Register, and HSMCI Interrupt Mask Register common bit-field definitions +/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt + * Disable Register, and HSMCI Interrupt Mask Register common bit-field + * definitions */ #define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */ @@ -313,6 +323,7 @@ # define HSMCI_DMA_CHKSIZE_8 (2 << HSMCI_DMA_CHKSIZE_SHIFT) /* 8 data available */ # define HSMCI_DMA_CHKSIZE_16 (3 << HSMCI_DMA_CHKSIZE_SHIFT) /* 16 data available */ # define HSMCI_DMA_CHKSIZE_32 (4 << HSMCI_DMA_CHKSIZE_SHIFT) /* 32 data available */ + #define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ /* HSMCI Configuration Register */ @@ -335,17 +346,17 @@ #define HSMCI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ #define HSMCI_WPSR_WPVSRC_MASK (0xffff << HSMCI_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* SAMV7_NHSMCI4 > 0 */ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_HSMCI_H */ diff --git a/arch/arm/src/samv7/hardware/sam_matrix.h b/arch/arm/src/samv7/hardware/sam_matrix.h index f1727de87d8..65e5016c64a 100644 --- a/arch/arm/src/samv7/hardware/sam_matrix.h +++ b/arch/arm/src/samv7/hardware/sam_matrix.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_matrix.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MATRIX_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MATRIX_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* MATRIX register offsets **************************************************************/ +/* MATRIX register offsets **************************************************/ #define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2) # define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ @@ -94,7 +94,7 @@ #define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ /* 0x0110-0x01fc: Reserved */ -/* MATRIX register addresses ************************************************************/ +/* MATRIX register addresses ************************************************/ #define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n)) # define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET) @@ -150,7 +150,8 @@ #define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET) #define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET) -/* MATRIX register bit definitions ******************************************************/ +/* MATRIX register bit definitions ******************************************/ + /* Master Configuration Registers */ #define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ @@ -211,6 +212,7 @@ #define MATRIX_PRBS_MPR_SHIFT(x) (((n)-8) << 2) /* n = 8-11 */ #define MATRIX_PRBS_MPR_MASK(x) (3 << MATRIX_PRBS_MPR_SHIFT(x)) + # define MATRIX_PRBS_M8PR_SHIFT (0) /* Bits 0-1: Master 8 Priority */ # define MATRIX_PRBS_M8PR_MASK (3 << MATRIX_PRBS_M8PR_SHIFT) # define MATRIX_PRBS_M8PR(n) ((uint32_t)(n) << MATRIX_PRBS_M8PR_SHIFT) @@ -227,6 +229,7 @@ /* Master Remap Control Register */ #define MATRIX_MRCR_RCB(n) (1 << (n)) /* n=0-11 */ + # define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ # define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ # define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ @@ -253,6 +256,7 @@ # define MATRIX_CCFG_SYSIO_SYSIO6 (1 << 6) /* Bit 6: PB6 or TMS/SWDIO Assignment */ # define MATRIX_CCFG_SYSIO_SYSIO7 (1 << 7) /* Bit 7: PB7 or TCK/SWCLK Assignment */ # define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PB12 or ERASE Assignment */ + #define MATRIX_CCFG_CAN1DMABA_MASK 0xffff0000 /* Bits 16-31: CAN1 DMA Base Address */ /* SMC Chip Select NAND Flash Assignment Register */ @@ -277,7 +281,7 @@ #define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT) -/* Masters ******************************************************************************/ +/* Masters ******************************************************************/ #define MATRIX_MSTR_CORTEXM7_1 0 /* Cortex-M7 */ #define MATRIX_MSTR_CORTEXM7_2 1 /* Cortex-M7 */ @@ -292,7 +296,7 @@ #define MATRIX_MSTR_CAN0 10 /* CAN0 DMA */ #define MATRIX_MSTR_CAN1 11 /* CAN1 DMA */ -/* Slaves *******************************************************************************/ +/* Slaves *******************************************************************/ #define MATRIX_SLAVE_ISRAM_1 0 /* Internal SRAM */ #define MATRIX_SLAVE_ISRAM_2 1 /* Internal SRAM */ @@ -304,16 +308,16 @@ #define MATRIX_SLAVE_PB 7 /* Peripheral Bridge */ #define MATRIX_SLAVE_AHB 8 /* AHB Slave */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MATRIX_H */ diff --git a/arch/arm/src/samv7/hardware/sam_mcan.h b/arch/arm/src/samv7/hardware/sam_mcan.h index ca3106898b7..28ff965c626 100644 --- a/arch/arm/src/samv7/hardware/sam_mcan.h +++ b/arch/arm/src/samv7/hardware/sam_mcan.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_mcan.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MCAN_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MCAN_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* MCAN register offsets ****************************************************************/ +/* MCAN register offsets ****************************************************/ /* 0x0000-0x0004 Reserved */ #define SAM_MCAN_CUST_OFFSET 0x0008 /* Customer Register */ @@ -88,7 +88,7 @@ #define SAM_MCAN_TXEFA_OFFSET 0x00f8 /* Transmit Event FIFO Acknowledge Register */ /* 0x00fc Reserved */ -/* MCAN register addresses **************************************************************/ +/* MCAN register addresses **************************************************/ #define SAM_MCAN0_CUST (SAM_MCAN0_BASE+SAM_MCAN_CUST_OFFSET) #define SAM_MCAN0_FBTP (SAM_MCAN0_BASE+SAM_MCAN_FBTP_OFFSET) @@ -180,9 +180,9 @@ #define SAM_MCAN1_TXEFS (SAM_MCAN1_BASE+SAM_MCAN_TXEFS_OFFSET) #define SAM_MCAN1_TXEFA (SAM_MCAN1_BASE+SAM_MCAN_TXEFA_OFFSET) -/* MCAN register bit definitions ********************************************************/ +/* MCAN register bit definitions ********************************************/ -/* Customer Register (32-bit value)*/ +/* Customer Register (32-bit value) */ /* Fast Bit Timing and Prescaler Register */ @@ -212,6 +212,7 @@ # define MCAN_TEST_TX_SPMON (1 << MCAN_TEST_TX_SHIFT) /* Sample Point can be monitored at CANTX */ # define MCAN_TEST_TX_DOMINANT (2 << MCAN_TEST_TX_SHIFT) /* Dominant (0) level at CANTX. */ # define MCAN_TEST_TX_RECESSIVE (3 << MCAN_TEST_TX_SHIFT) /* Recessive (1) at CANTX. */ + #define MCAN_TEST_RX (1 << 7) /* Bit 7: Receive Pin */ #define MCAN_TEST_TDCV_SHIFT (8) /* Bits 8-13: Transceiver Delay Compensation Value */ #define MCAN_TEST_TDCV_MASK (0x3f << MCAN_TEST_TDCV_SHIFT) @@ -241,12 +242,14 @@ # define MCAN_CCCR_CME_ISO11898_1 (0 << MCAN_CCCR_CME_SHIFT) /* CAN operation according to ISO11898-1 enabled */ # define MCAN_CCCR_CME_FD (1 << MCAN_CCCR_CME_SHIFT) /* CAN FD operation enabled */ # define MCAN_CCCR_CME_FD_BSW (2 << MCAN_CCCR_CME_SHIFT) /* CAN FD operation with bit rate switching enabled */ + #define MCAN_CCCR_CMR_SHIFT (10) /* Bits 10-11: CAN Mode Request */ #define MCAN_CCCR_CMR_MASK (3 << MCAN_CCCR_CMR_SHIFT) # define MCAN_CCCR_CMR_NOCHG (0 << MCAN_CCCR_CMR_SHIFT) /* No mode change */ # define MCAN_CCCR_CMR_FD (1 << MCAN_CCCR_CMR_SHIFT) /* Request CAN FD operation */ # define MCAN_CCCR_CMR_FD_BSW (2 << MCAN_CCCR_CMR_SHIFT) /* Request CAN FD operation with bit rate switching */ # define MCAN_CCCR_CMR_ISO11898_1 (3 << MCAN_CCCR_CMR_SHIFT) /* Request CAN operation according ISO11898-1 */ + #define MCAN_CCCR_FDO (1 << 12) /* Bit 12: CAN FD Operation */ #define MCAN_CCCR_FDBS (1 << 13) /* Bit 13: CAN FD Bit Rate Switching */ #define MCAN_CCCR_TXP (1 << 14) /* Bit 14: Transmit Pause */ @@ -273,6 +276,7 @@ # define MCAN_TSCC_TSS_ ZERO (0 << MCAN_TSCC_TSS_SHIFT) /* Timestamp counter value always 0x0000 */ # define MCAN_TSCC_TSS_TCP_INC (1 << MCAN_TSCC_TSS_SHIFT) /* Timestamp counter value incremented according to TCP */ # define MCAN_TSCC_TSS_EXT_TS (2 << MCAN_TSCC_TSS_SHIFT) /* External timestamp counter value used */ + #define MCAN_TSCC_TCP_SHIFT (16) /* Bits 16-19: Timestamp Counter Prescaler */ #define MCAN_TSCC_TCP_MASK (15 << MCAN_TSCC_TCP_SHIFT) # define MCAN_TSCC_TCP(n) ((uint32_t)(n) << MCAN_TSCC_TCP_SHIFT) @@ -290,6 +294,7 @@ # define MCAN_TOCC_TOS_TX_TIMEOUT (1 << MCAN_TOCC_TOS_SHIFT) /* Timeout controlled by Tx Event FIFO */ # define MCAN_TOCC_TOS_RX0_TIMEOUT (2 << MCAN_TOCC_TOS_SHIFT) /* Timeout controlled by Receive FIFO 0 */ # define MCAN_TOCC_TOS_RX1_TIMEOUT (3 << MCAN_TOCC_TOS_SHIFT) /* Timeout controlled by Receive FIFO 1 */ + #define MCAN_TOCC_TOP_SHIFT (16) /* Bits 16-31: Timeout Period */ #define MCAN_TOCC_TOP_MASK (0xffff << MCAN_TOCC_TOP_SHIFT) # define MCAN_TOCC_TOP(n) ((uint32_t)(n) << MCAN_TOCC_TOP_SHIFT) @@ -312,6 +317,7 @@ # define MCAN_ECR_CEL(n) ((uint32_t)(n) << MCAN_ECR_CEL_SHIFT) /* Protocol Status Register */ + /* Error codes */ #define MCAN_PSR_EC_NO_ERROR (0) /* No error occurred since LEC has been reset */ @@ -326,24 +332,27 @@ #define MCAN_PSR_LEC_SHIFT (0) /* Bits 0-2: Last Error Code */ #define MCAN_PSR_LEC_MASK (7 << MCAN_PSR_LEC_SHIFT) # define MCAN_PSR_LEC(n) ((uint32_t)(n) << MCAN_PSR_LEC_SHIFT) /* See error codes above */ + #define MCAN_PSR_ACT_SHIFT (3) /* Bits 3-4: Activity */ #define MCAN_PSR_ACT_MASK (3 << MCAN_PSR_ACT_SHIFT) # define MCAN_PSR_ACT_SYNCHING (0 << MCAN_PSR_ACT_SHIFT) /* Node is synchronizing on CAN communication */ # define MCAN_PSR_ACT_IDLE (1 << MCAN_PSR_ACT_SHIFT) /* Node is neither receiver nor transmitter */ # define MCAN_PSR_ACT_RECEIVER (2 << MCAN_PSR_ACT_SHIFT) /* Node is operating as receiver */ # define MCAN_PSR_ACT_TRANSMITTER (3 << MCAN_PSR_ACT_SHIFT) /* Node is operating as transmitter */ + #define MCAN_PSR_EP (1 << 5) /* Bit 5: Error Passive */ #define MCAN_PSR_EW (1 << 6) /* Bit 6: Warning Status */ #define MCAN_PSR_BO (1 << 7) /* Bit 7: Bus_Off Status */ #define MCAN_PSR_FLEC_SHIFT (8) /* Bits 8-10: Fast Last Error Code */ #define MCAN_PSR_FLEC_MASK (7 << MCAN_PSR_FLEC_SHIFT) # define MCAN_PSR_FLEC(n) ((uint32_t)(n) << MCAN_PSR_FLEC_SHIFT) /* See error codes above */ + #define MCAN_PSR_RESI (1 << 11) /* Bit 11: ESI Flag of Last Received CAN FD Message */ #define MCAN_PSR_RBRS (1 << 12) /* Bit 12: BRS Flag of Last Received CAN FD Message */ #define MCAN_PSR_REDL (1 << 13) /* Bit 13: Received a CAN FD Message */ -/* Common bit definitions for Interrupt Register, Interrupt Enable Register, Interrupt - * Line Select Register +/* Common bit definitions for Interrupt Register, Interrupt Enable Register, + * Interrupt Line Select Register */ #define MCAN_INT_RF0N (1 << 0) /* Bit 0: Receive FIFO 0 New Message */ @@ -393,6 +402,7 @@ # define MCAN_GFC_ANFE_RX_FIFO0 (0 << MCAN_GFC_ANFE_SHIFT) /* Message stored in Receive FIFO 0 */ # define MCAN_GFC_ANFE_RX_FIFO1 (1 << MCAN_GFC_ANFE_SHIFT) /* Message stored in Receive FIFO 1 */ # define MCAN_GFC_ANFE_REJECTED (2 << MCAN_GFC_ANFE_SHIFT) /* 2-3 Message rejected */ + #define MCAN_GFC_ANFS_SHIFT (4) /* Bits 4-5: Accept Non-matching Frames Standard */ #define MCAN_GFC_ANFS_MASK (3 << MCAN_GFC_ANFS_SHIFT) # define MCAN_GFC_ANFS_RX_FIFO0 (0 << MCAN_GFC_ANFS_SHIFT) /* Message stored in Receive FIFO 0 */ @@ -432,6 +442,7 @@ # define MCAN_HPMS_MSI_LOST (1 << MCAN_HPMS_MSI_SHIFT) /* FIFO message. */ # define MCAN_HPMS_MSI_FIFO0 (2 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 0. */ # define MCAN_HPMS_MSI_FIFO1 (3 << MCAN_HPMS_MSI_SHIFT) /* Message stored in FIFO 1. */ + #define MCAN_HPMS_FIDX_SHIFT (8) /* Bits 8-14: Filter Index */ #define MCAN_HPMS_FIDX_MASK (0x7f << MCAN_HPMS_FIDX_SHIFT) # define MCAN_HPMS_FIDX(n) ((uint32_t)(n) << MCAN_HPMS_FIDX_SHIFT) @@ -530,6 +541,7 @@ # define MCAN_RXESC_F0DS_32B (5 << MCAN_RXESC_F0DS_SHIFT) /* 32-byte data field */ # define MCAN_RXESC_F0DS_48B (6 << MCAN_RXESC_F0DS_SHIFT) /* 48-byte data field */ # define MCAN_RXESC_F0DS_64B (7 << MCAN_RXESC_F0DS_SHIFT) /* 64-byte data field */ + #define MCAN_RXESC_F1DS_SHIFT (4) /* Bits 4-6: Receive FIFO 1 Data Field Size */ #define MCAN_RXESC_F1DS_MASK (7 << MCAN_RXESC_F1DS_SHIFT) # define MCAN_RXESC_F1DS(n) ((uint32_t)(n) << MCAN_RXESC_F1DS_SHIFT) @@ -541,6 +553,7 @@ # define MCAN_RXESC_F1DS_32B (5 << MCAN_RXESC_F1DS_SHIFT) /* 32-byte data field */ # define MCAN_RXESC_F1DS_48B (6 << MCAN_RXESC_F1DS_SHIFT) /* 48-byte data field */ # define MCAN_RXESC_F1DS_64B (7 << MCAN_RXESC_F1DS_SHIFT) /* 64-byte data field */ + #define MCAN_RXESC_RBDS_SHIFT (8) /* Bits 8-10: Receive Buffer Data Field Size */ #define MCAN_RXESC_RBDS_MASK (7 << MCAN_RXESC_RBDS_SHIFT) # define MCAN_RXESC_RBDS(n) ((uint32_t)(n) << MCAN_RXESC_RBDS_SHIFT) @@ -651,7 +664,8 @@ #define MCAN_TXEFA_MASK 0x0000001f /* Event fifo acknowledge index mask */ -/* Message RAM Definitions **************************************************************/ +/* Message RAM Definitions **************************************************/ + /* Common Buffer and FIFO element bit definitions: * * --------------- ------------------- -------------------------------- @@ -728,6 +742,7 @@ # define STDFILTER_S0_DEBUGA (1 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message A */ # define STDFILTER_S0_DEBUGB (2 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message B */ # define STDFILTER_S0_DEBUGC (3 << STDFILTER_S0_ACTION_SHIFT) /* Debug Message C */ + #define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */ #define STDFILTER_S0_SFID1_MASK (0x3ff << STDFILTER_S0_SFID1_SHIFT) # define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT) @@ -741,6 +756,7 @@ # define STDFILTER_S0_SFEC_PRIOFIFO0 (5 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 0 on match */ # define STDFILTER_S0_SFEC_PRIOFIFO1 (6 << STDFILTER_S0_SFEC_SHIFT) /* Set priority and store in FIFO 1 on match */ # define STDFILTER_S0_SFEC_BUFFER (7 << STDFILTER_S0_SFEC_SHIFT) /* Store into Rx Buffer or as debug message */ + #define STDFILTER_S0_SFT_SHIFT (30) /* Bits 30-31: Standard Filter Type */ #define STDFILTER_S0_SFT_MASK (3 << STDFILTER_S0_SFT_SHIFT) # define STDFILTER_S0_SFT_RANGE (0 << STDFILTER_S0_SFT_SHIFT) /* Range filter from SF1ID to SF2ID */ @@ -775,6 +791,7 @@ # define EXTFILTER_F1_DEBUGA (1 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message A */ # define EXTFILTER_F1_DEBUGB (2 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message B */ # define EXTFILTER_F1_DEBUGC (3 << EXTFILTER_F1_ACTION_SHIFT) /* Debug Message C */ + #define EXTFILTER_F1_EFT_SHIFT (30) /* Bits 30-31: Extended Filter Type */ #define EXTFILTER_F1_EFT_MASK (3 << EXTFILTER_F1_EFT_SHIFT) # define EXTFILTER_F1_EFT_RANGE (0 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from SF1ID to SF2ID */ @@ -782,16 +799,16 @@ # define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ # define EXTFILTER_F1_EFT_NOXIDAM (2 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MCAN_H */ diff --git a/arch/arm/src/samv7/hardware/sam_memorymap.h b/arch/arm/src/samv7/hardware/sam_memorymap.h index 6d51c3456f8..e858ec5360f 100644 --- a/arch/arm/src/samv7/hardware/sam_memorymap.h +++ b/arch/arm/src/samv7/hardware/sam_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/samv7/hardware/sam_pinmap.h b/arch/arm/src/samv7/hardware/sam_pinmap.h index b019cf52043..c07220874b2 100644 --- a/arch/arm/src/samv7/hardware/sam_pinmap.h +++ b/arch/arm/src/samv7/hardware/sam_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PINMAP_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/samv7/hardware/sam_pio.h b/arch/arm/src/samv7/hardware/sam_pio.h index 3919c7600a1..88852e59feb 100644 --- a/arch/arm/src/samv7/hardware/sam_pio.h +++ b/arch/arm/src/samv7/hardware/sam_pio.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_pio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM4E_PIO_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM4E_PIO_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include @@ -32,10 +32,11 @@ #if SAMV7_NPIO > 0 -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* Configuration ************************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ #define GPIO_HAVE_PULLDOWN 1 #define GPIO_HAVE_PERIPHCD 1 @@ -44,7 +45,7 @@ #define GPIO_HAVE_DRIVER 1 #define GPIO_HAVE_KEYPAD 1 -/* Misc Helper Definitions **************************************************************/ +/* Misc Helper Definitions **************************************************/ #define PIOA (0) #define PIOB (1) @@ -52,7 +53,7 @@ #define PIOD (3) #define PIOE (4) -/* PIO register offsets *****************************************************************/ +/* PIO register offsets *****************************************************/ #define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ #define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ @@ -135,8 +136,7 @@ #define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */ /* 0x0168-0x018c: Reserved for PDC registers */ -/* PIO register addresses ***************************************************************/ - +/* PIO register addresses ***************************************************/ #define SAM_PIOA_PER (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET) #define SAM_PIOA_PDR (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET) @@ -471,7 +471,7 @@ # define SAM_PIOE_PCRHR (SAM_PIOE_BASE+SAM_PIO_PCRHR_OFFSET #endif -/* PIO register bit definitions *********************************************************/ +/* PIO register bit definitions *********************************************/ /* Common bit definitions for ALMOST all IO registers (exceptions follow) */ @@ -551,28 +551,31 @@ # define PIO_PCMR_DSIZE_BYTE (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */ # define PIO_PCMR_DSIZE_HWORD (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */ # define PIO_PCMR_DSIZE_WORD (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */ + #define PIO_PCMR_ALWYS (1 << 9) /* Bit 9: Parallel Capture Mode Always Sampling */ #define PIO_PCMR_HALFS (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */ #define PIO_PCMR_FRSTS (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */ -/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */ +/* PIO Parallel Capture Interrupt Enable, Disable, Mask, + * and Status Registers + */ #define PIOC_PCINT_DRDY (1 << 0) /* Bit 0: Parallel Capture Mode Data Ready Interrupt */ #define PIOC_PCINT_OVRE (1 << 1) /* Bit 1: Parallel Capture Mode Overrun Error Interrupt */ #define PIOC_PCINT_ENDRX (1 << 2) /* Bit 2: End of Reception Transfer Interrupt */ #define PIOC_PCINT_RXBUFF (1 << 3) /* Bit 3: Reception Buffer Full Interrupt */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* SAMV7_NPIO > 0 */ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM4E_PIO_H */ diff --git a/arch/arm/src/samv7/hardware/sam_pmc.h b/arch/arm/src/samv7/hardware/sam_pmc.h index 0a114633cf2..516a77222e8 100644 --- a/arch/arm/src/samv7/hardware/sam_pmc.h +++ b/arch/arm/src/samv7/hardware/sam_pmc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_pmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PMC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PMC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* PMC register offsets *********************************************************************/ +/* PMC register offsets *****************************************************/ #define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ #define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ @@ -89,7 +89,7 @@ #define SAM_PMC_SLPWK_ASR1_OFFSET 0x0140 /* SleepWalking Activity Status Register 1 */ #define SAM_PMC_SLPWK_AIPR_OFFSET 0x0144 /* SleepWalking Activity In Progress Register */ -/* PMC register addresses *******************************************************************/ +/* PMC register addresses ***************************************************/ #define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) #define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) @@ -140,10 +140,10 @@ #define SAM_PMC_SLPWK_ASR1 (SAM_PMC_BASE+SAM_PMC_SLPWK_ASR1_OFFSET) #define SAM_PMC_SLPWK_AIPR (SAM_PMC_BASE+SAM_PMC_SLPWK_AIPR_OFFSET) -/* PMC register bit definitions *************************************************************/ +/* PMC register bit definitions *********************************************/ -/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System - * Clock Status Register common bit-field definitions +/* PMC System Clock Enable Register, PMC System Clock Disable Register, and + * PMC System Clock Status Register common bit-field definitions */ #define PMC_USBCLK (1 << 5) /* Bit 5: Enable USB FS Clock */ @@ -156,8 +156,9 @@ # define PMC_PCK5 (1 << 13) /* Bit 13: Programmable Clock 5 Output Enable */ # define PMC_PCK6 (1 << 14) /* Bit 14: Programmable Clock 6 Output Enable */ -/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC - * Peripheral Clock Status Register common bit-field definitions. +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable + * Register, and PMC Peripheral Clock Status Register common bit-field + * definitions. */ #define PMC_PIDL(n) (1 << (n)) @@ -206,6 +207,7 @@ # define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */ # define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */ # define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */ + #define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */ #define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT) # define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT) @@ -234,6 +236,7 @@ # define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */ # define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ # define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ + #define PMC_CKGR_PLLAR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ #define PMC_CKGR_PLLAR_COUNT_MASK (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) #define PMC_CKGR_PLLAR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ @@ -249,6 +252,7 @@ # define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ # define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ # define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* Divided UPLL Clock */ + #define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ #define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) # define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ @@ -259,12 +263,14 @@ # define PMC_MCKR_PRES_DIV32 (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ # define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ # define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ + #define PMC_MCKR_MDIV_SHIFT (8) /* Bits 8-9: Master Clock Division */ #define PMC_MCKR_MDIV_MASK (3 << PMC_MCKR_MDIV_SHIFT) # define PMC_MCKR_MDIV_DIV1 (0 << PMC_MCKR_MDIV_SHIFT) /* Master Clock is Prescaler Output Clock / 1 */ # define PMC_MCKR_MDIV_DIV2 (1 << PMC_MCKR_MDIV_SHIFT) /* Master Clock = Prescaler Output Clock / 2 */ # define PMC_MCKR_MDIV_DIV4 (2 << PMC_MCKR_MDIV_SHIFT) /* Master Clock = Prescaler Output Clock / 4 */ # define PMC_MCKR_MDIV_DIV3 (3 << PMC_MCKR_MDIV_SHIFT) /* Master Clock = Prescaler Output Clock / 3 */ + #define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */ /* USB Clock Register PMC_USB */ @@ -285,12 +291,13 @@ # define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_SHIFT) /* PLLA Clock */ # define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_SHIFT) /* Divided UPLL Clock */ # define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_SHIFT) /* Master Clock */ + #define PMC_PCK_PRES_SHIFT (4) /* Bits 4-11: Programmable Clock Prescaler */ #define PMC_PCK_PRES_MASK (0xff << PMC_PCK_PRES_SHIFT) # define PMC_PCK_PRES(n) ((uint32_t)(n) << PMC_PCK_PRES_SHIFT) /* n=0..255 */ -/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, - * and PMC Interrupt Mask Register common bit-field definitions +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status + * Register, and PMC Interrupt Mask Register common bit-field definitions */ #define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ @@ -312,8 +319,8 @@ #define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ #define PMC_INT_XT32KERR (1 << 21) /* Bit 21: Slow Crystal Oscillator Error Interrupt */ -/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field - * definitions +/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register + * common bit-field definitions */ #define PMC_FSTI(n) (1 << (n)) @@ -342,6 +349,7 @@ # define PMC_FSMR_FLPM_STANDBY (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */ # define PMC_FSMR_FLPM_PWRDOWN (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */ # define PMC_FSMR_FLPM_IDLE (2 << PMC_FSMR_FLPM_SHIFT) /* Idle mode */ + #define PMC_FSMR_FFLPM (1 << 23) /* Bit 20: Force Flash Low-power Mode (MR only) */ /* PMC Fault Output Clear Register */ @@ -361,8 +369,8 @@ #define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) -/* Peripheral Clock Enable Register 1, Peripheral Clock Disable Register 1, and Peripheral - * Clock Status Register 1 +/* Peripheral Clock Enable Register 1, Peripheral Clock Disable Register 1, + * and Peripheral Clock Status Register 1 */ #define PMC_PIDH(n) (1 << ((n) - 32)) @@ -404,6 +412,7 @@ # define PMC_PCR_DIV2 (1 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */ # define PMC_PCR_DIV4 (2 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */ # define PMC_PCR_DIV8 (3 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/8 */ + #define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */ /* Oscillator Calibration Register */ @@ -422,29 +431,35 @@ #define PMC_OCR_SEL12 (1 << 23) /* Bit 23: Select 12MHz RC Oscillator Calibration */ /* SleepWalking Enable Register 0: Use PMC_PIDL definitions */ + /* SleepWalking Disable Register 0: Use PMC_PIDL definitions */ + /* SleepWalking Status Register 0: Use PMC_PIDL definitions */ + /* SleepWalking Activity Status Register 0: Use PMC_PIDL definitions */ /* SleepWalking Enable Register 1: Use PMC_PIDH definitions */ + /* SleepWalking Disable Register 1: Use PMC_PIDH definitions */ + /* SleepWalking Status Register 1: Use PMC_PIDH definitions */ + /* SleepWalking Activity Status Register 1: Use PMC_PIDH definitions */ /* SleepWalking Activity In Progress Register */ #define PMC_SLPWK_AIPR_AIP (0) /* Bit 0: Activity in progress */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PMC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_qspi.h b/arch/arm/src/samv7/hardware/sam_qspi.h index b8b13acb659..cc39cb2b573 100644 --- a/arch/arm/src/samv7/hardware/sam_qspi.h +++ b/arch/arm/src/samv7/hardware/sam_qspi.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_qspi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_QSPI_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_QSPI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include @@ -32,15 +32,16 @@ #if SAMV7_NQSPI > 0 -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General Characteristics **************************************************************/ + ****************************************************************************/ + +/* General Characteristics **************************************************/ #define SAM_QSPI_MINBITS 8 /* Minimum word width */ #define SAM_QSPI_MAXBITS 16 /* Maximum word width */ -/* QSPI register offsets ****************************************************************/ +/* QSPI register offsets ****************************************************/ #define SAM_QSPI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_QSPI_MR_OFFSET 0x0004 /* Mode Register */ @@ -60,9 +61,9 @@ /* 0x0048–0x00e0 Reserved */ #define SAM_QSPI_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */ #define SAM_QSPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ - /* 0xec-0xfc: Reserved */ + /* 0xec-0xfc: Reserved */ -/* QSPI register addresses **************************************************************/ +/* QSPI register addresses **************************************************/ #define SAM_QSPI0_CR (SAM_QSPI0_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */ #define SAM_QSPI0_MR (SAM_QSPI0_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */ @@ -100,7 +101,7 @@ # define SAM_QSPI1_WPSR (SAM_QSPI1_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */ #endif -/* QSPI register bit definitions ********************************************************/ +/* QSPI register bit definitions ********************************************/ /* QSPI Control Register */ @@ -119,6 +120,7 @@ # define QSPI_MR_CSMODE_NRELOAD (0 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted if TD not reloaded */ # define QSPI_MR_CSMODE_LASTXFER (1 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted when LASTXFER transferred */ # define QSPI_MR_CSMODE_SYSTEM (2 << QSPI_MR_CSMODE_SHIFT) /* CS deasserted after each transfer */ + #define QSPI_MR_NBBITS_SHIFT (8) /* Bits 8-11: Number Of Bits Per Transfer */ #define QSPI_MR_NBBITS_MASK (15 << QSPI_MR_NBBITS_SHIFT) # define QSPI_MR_NBBITS(n) ((uint32_t)((n)-SAM_QSPI_MINBITS) << QSPI_MR_NBBITS_SHIFT) @@ -131,6 +133,7 @@ # define QSPI_MR_NBBITS_14BIT (6 << QSPI_MR_NBBITS_SHIFT) /* 14 bits for transfer */ # define QSPI_MR_NBBITS_15BIT (7 << QSPI_MR_NBBITS_SHIFT) /* 15 bits for transfer */ # define QSPI_MR_NBBITS_16BIT (8 << QSPI_MR_NBBITS_SHIFT) /* 16 bits for transfer */ + #define QSPI_MR_DLYBCT_SHIFT (16) /* Bits 16-23: Delay Between Consecutive Transfers */ #define QSPI_MR_DLYBCT_MASK (0xff << QSPI_MR_DLYBCT_SHIFT) # define QSPI_MR_DLYBCT(n) ((uint32_t)(n) << QSPI_MR_DLYBCT_SHIFT) @@ -148,7 +151,8 @@ #define QSPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */ #define QSPI_TDR_TD_MASK (0xffff << QSPI_TDR_TD_SHIFT) -/* QSPI Status Register, QSPI Interrupt Enable Register, QSPI Interrupt Disable Register, +/* QSPI Status Register, QSPI Interrupt Enable Register, + * QSPI Interrupt Disable Register, * and QSPI Interrupt Mask Register (common bit fields) */ @@ -198,6 +202,7 @@ # define QSPI_IFR_WIDTH_QUADIO (4 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Quad Quad */ # define QSPI_IFR_WIDTH_DUALCMD (5 << QSPI_IFR_WIDTH_SHIFT) /* Dual Dual Dual */ # define QSPI_IFR_WIDTH_QUADCMD (6 << QSPI_IFR_WIDTH_SHIFT) /* Quad Quad Quad */ + #define QSPI_IFR_INSTEN (1 << 4) /* Bit 4: Instruction Enable */ #define QSPI_IFR_ADDREN (1 << 5) /* Bit 5: Address Enable */ #define QSPI_IFR_OPTEN (1 << 6) /* Bit 6: Option Enable */ @@ -208,6 +213,7 @@ # define QSPI_IFR_OPTL_2BIT (1 << QSPI_IFR_OPTL_SHIFT) /* Option is 2 bits */ # define QSPI_IFR_OPTL_4BIT (2 << QSPI_IFR_OPTL_SHIFT) /* Option is 4 bits */ # define QSPI_IFR_OPTL_8BIT (3 << QSPI_IFR_OPTL_SHIFT) /* Option is 8 bits */ + #define QSPI_IFR_ADDRL (1 << 10) /* Bit 10: Address Length */ # define QSPI_IFR_ADDRL_24BIT (0 << 10) /* 0=24-bit */ # define QSPI_IFR_ADDRL_32BIT (1 << 10) /* 1=32-bit */ @@ -217,6 +223,7 @@ # define QSPI_IFR_TFRTYP_RDMEM (1 << QSPI_IFR_TFRTYP_SHIFT) /* Read data transfer from serial memory */ # define QSPI_IFR_TFRTYP_WRITE (2 << QSPI_IFR_TFRTYP_SHIFT) /* Write transfer into serial memory */ # define QSPI_IFR_TFRTYP_WRMEM (3 << QSPI_IFR_TFRTYP_SHIFT) /* Write data transfer the serial memory */ + #define QSPI_IFR_CRM (1 << 14) /* Bit 14: Continuous Read Mode */ #define QSPI_IFR_NBDUM_SHIFT (16) /* Bits 16-20: Number Of Dummy Cycles */ #define QSPI_IFR_NBDUM_MASK (31 << QSPI_IFR_NBDUM_SHIFT) @@ -242,17 +249,17 @@ #define QSPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: QSPI Write Protection Violation Source */ #define QSPI_WPSR_WPVSRC_MASK (0xff << QSPI_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* SAMV7_NQSPI > 0 */ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_QSPI_H */ diff --git a/arch/arm/src/samv7/hardware/sam_rstc.h b/arch/arm/src/samv7/hardware/sam_rstc.h index 6b6cb9a111b..6a6acf3edfa 100644 --- a/arch/arm/src/samv7/hardware/sam_rstc.h +++ b/arch/arm/src/samv7/hardware/sam_rstc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_rstc.h * Reset Controller (RSTC) definitions for the SAMV71 * @@ -32,36 +32,36 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RSTC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RSTC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* RSTC register offsets ****************************************************************/ +/* RSTC register offsets ****************************************************/ #define SAM_RSTC_CR_OFFSET 0x00 /* Control Register */ #define SAM_RSTC_SR_OFFSET 0x04 /* Status Register */ #define SAM_RSTC_MR_OFFSET 0x08 /* Mode Register */ -/* RSTC register addresses **************************************************************/ +/* RSTC register addresses **************************************************/ #define SAM_RSTC_CR (SAM_RSTC_BASE+SAM_RSTC_CR_OFFSET) #define SAM_RSTC_SR (SAM_RSTC_BASE+SAM_RSTC_SR_OFFSET) #define SAM_RSTC_MR (SAM_RSTC_BASE+SAM_RSTC_MR_OFFSET) -/* RSTC register bit definitions ********************************************************/ +/* RSTC register bit definitions ********************************************/ /* Reset Controller Control Register */ @@ -81,6 +81,7 @@ # define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */ # define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */ # define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */ + #define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */ #define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */ @@ -95,16 +96,16 @@ #define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) # define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RSTC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_rtc.h b/arch/arm/src/samv7/hardware/sam_rtc.h index 1ae4058e294..ec1f518c14d 100644 --- a/arch/arm/src/samv7/hardware/sam_rtc.h +++ b/arch/arm/src/samv7/hardware/sam_rtc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RTC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RTC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* RTC register offsets *****************************************************************/ +/* RTC register offsets *****************************************************/ #define SAM_RTC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_RTC_MR_OFFSET 0x0004 /* Mode Register */ @@ -49,7 +49,7 @@ #define SAM_RTC_IMR_OFFSET 0x0028 /* Interrupt Mask Register */ #define SAM_RTC_VER_OFFSET 0x002c /* Valid Entry Register */ -/* RTC register addresses ***************************************************************/ +/* RTC register addresses ***************************************************/ #define SAM_RTC_CR (SAM_RTCC_VBASE+SAM_RTC_CR_OFFSET) #define SAM_RTC_MR (SAM_RTCC_VBASE+SAM_RTC_MR_OFFSET) @@ -64,7 +64,7 @@ #define SAM_RTC_IMR (SAM_RTCC_VBASE+SAM_RTC_IMR_OFFSET) #define SAM_RTC_VER (SAM_RTCC_VBASE+SAM_RTC_VER_OFFSET) -/* RTC register bit definitions *********************************************************/ +/* RTC register bit definitions *********************************************/ /* RTC Control Register */ @@ -102,6 +102,7 @@ # define RTC_MR_OUT0_ALARM_TOGGLE (5 << RTC_MR_OUT0_SHIFT) /* Output toggles when alarm flag rises */ # define RTC_MR_OUT0_ALARM_FLAG (6 << RTC_MR_OUT0_SHIFT) /* Output is a copy of the alarm flag */ # define RTC_MR_OUT0_PROG_PULSE (7 << RTC_MR_OUT0_SHIFT) /* Duty cycle programmable pulse */ + #define RTC_MR_OUT1_SHIFT (10) /* Bits 20-22: RTCOUT1 Output Source Selection */ #define RTC_MR_OUT1_MASK (7 << RTC_MR_OUT1_SHIFT) # define RTC_MR_OUT1_NO_WAVE (0 << RTC_MR_OUT1_SHIFT) /* No waveform, stuck at 0 */ @@ -112,6 +113,7 @@ # define RTC_MR_OUT1_ALARM_TOGGLE (5 << RTC_MR_OUT1_SHIFT) /* Output toggles when alarm flag rises */ # define RTC_MR_OUT1_ALARM_FLAG (6 << RTC_MR_OUT1_SHIFT) /* Output is a copy of the alarm flag */ # define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */ + #define RTC_MR_THIGH_SHIFT (24) /* Bits 24-16: High Duration of the Output Pulse */ #define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT) # define RTC_MR_THIGH_31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */ @@ -122,6 +124,7 @@ # define RTC_MR_THIGH_122US (5 << RTC_MR_THIGH_SHIFT) /* 122 μs */ # define RTC_MR_THIGH_30US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 μs */ # define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 μs */ + #define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */ #define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT) # define RTC_MR_TPERIOD_ 1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */ @@ -239,16 +242,16 @@ #define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */ #define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RTC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_sdramc.h b/arch/arm/src/samv7/hardware/sam_sdramc.h index 5215eeda5ea..ac6956e460c 100644 --- a/arch/arm/src/samv7/hardware/sam_sdramc.h +++ b/arch/arm/src/samv7/hardware/sam_sdramc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_sdramc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SDRAMC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SDRAMC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SDRAMC register offsets **************************************************************/ +/* SDRAMC register offsets **************************************************/ #define SAM_SDRAMC_MR_OFFSET 0x0000 /* SDRAMC Mode Register */ #define SAM_SDRAMC_TR_OFFSET 0x0004 /* SDRAMC Refresh Timer Register */ @@ -50,7 +50,7 @@ #define SAM_SDRAMC_OCMS_KEY1_OFFSET 0x0030 /* SDRAMC OCMS KEY1 Register */ #define SAM_SDRAMC_OCMS_KEY2_OFFSET 0x0034 /* SDRAMC OCMS KEY2 Register */ -/* SDRAMC register addresses ************************************************************/ +/* SDRAMC register addresses ************************************************/ #define SAM_SDRAMC_MR (SAM_SDRAMC_BASE+SAM_SDRAMC_MR_OFFSET) #define SAM_SDRAMC_TR (SAM_SDRAMC_BASE+SAM_SDRAMC_TR_OFFSET) @@ -66,7 +66,7 @@ #define SAM_SDRAMC_OCMS_KEY1 (SAM_SDRAMC_BASE+SAM_SDRAMC_OCMS_KEY1_OFFSET) #define SAM_SDRAMC_OCMS_KEY2 (SAM_SDRAMC_BASE+SAM_SDRAMC_OCMS_KEY2_OFFSET) -/* SDRAMC register bit definitions ******************************************************/ +/* SDRAMC register bit definitions ******************************************/ /* SDRAMC Mode Register */ @@ -92,11 +92,13 @@ # define SDRAMC_CR_NC_COL9 (1 << SDRAMC_CR_NC_SHIFT) /* 9 column bits */ # define SDRAMC_CR_NC_COL10 (2 << SDRAMC_CR_NC_SHIFT) /* 10 column bits */ # define SDRAMC_CR_NC_COL11 (3 << SDRAMC_CR_NC_SHIFT) /* 11 column bits */ + #define SDRAMC_CR_NR_SHIFT (2) /* Bits 2-3: Number of Row Bits */ #define SDRAMC_CR_NR_MASK (3 << SDRAMC_CR_NR_SHIFT) # define SDRAMC_CR_NR_ROW11 (0 << SDRAMC_CR_NR_SHIFT) /* 11 row bits */ # define SDRAMC_CR_NR_ROW12 (1 << SDRAMC_CR_NR_SHIFT) /* 12 row bits */ # define SDRAMC_CR_NR_ROW13 (2 << SDRAMC_CR_NR_SHIFT) /* 13 row bits */ + #define SDRAMC_CR_NB (1 << 4) /* Bit 4: Number of Banks */ # define SDRAMC_CR_NB_BANK2 (0 << 4) /* 0=2 banks */ # define SDRAMC_CR_NB_BANK4 (1 << 4) /* 1=4 banks */ @@ -105,6 +107,7 @@ # define SDRAMC_CR_CAS_LATENCY1 (0 << SDRAMC_CR_CAS_SHIFT) /* 1 cycle CAS latency */ # define SDRAMC_CR_CAS_LATENCY2 (1 << SDRAMC_CR_CAS_SHIFT) /* 2 cycle CAS latency */ # define SDRAMC_CR_CAS_LATENCY3 (2 << SDRAMC_CR_CAS_SHIFT) /* 3 cycle CAS latency */ + #define SDRAMC_CR_DBW (1 << 7) /* Bit 7: Data Bus Width */ #define SDRAMC_CR_TWR_SHIFT (8) /* Bits 8-11: Write Recovery Delay */ #define SDRAMC_CR_TWR_MASK (15 << SDRAMC_CR_TWR_SHIFT) @@ -133,6 +136,7 @@ # define SDRAMC_LPR_LPCB_REFRESH (1 << SDRAMC_LPR_LPCB_SHIFT) /* Self-refresh to SDRAM device */ # define SDRAMC_LPR_LPCB_PWRDOWN (2 << SDRAMC_LPR_LPCB_SHIFT) /* Power-down to SDRAM after accesses */ # define SDRAMC_LPR_LPCB_DPPWRDOWN (3 << SDRAMC_LPR_LPCB_SHIFT) /* Deep Power-down the SDRAM device */ + #define SDRAMC_LPR_PASR_SHIFT (4) /* Bits 4-6: Partial Array Self-refresh */ #define SDRAMC_LPR_PASR_MASK (7 << SDRAMC_LPR_PASR_SHIFT) #define SDRAMC_LPR_TCSR_SHIFT (8) /* Bits 8-9: Temperature Compensated Self-Refresh */ @@ -147,8 +151,8 @@ # define SDRAMC_LPR_TIMEOUT_LP64 (1 << SDRAMC_LPR_TIMEOUT_SHIFT) /* SDRAM low-power mode after 64 cycles */ # define SDRAMC_LPR_TIMEOUT_LP128 (2 << SDRAMC_LPR_TIMEOUT_SHIFT) /* SDRAM low-power mode 128 cycles */ -/* SDRAMC Interrupt Enable Register, SDRAMC Interrupt Disable Register, SDRAMC - * Interrupt Mask Register, and SDRAMC Interrupt Status Register. +/* SDRAMC Interrupt Enable Register, SDRAMC Interrupt Disable Register, + * SDRAMC Interrupt Mask Register, and SDRAMC Interrupt Status Register. */ #define SDRAMC_INT_RES (1 << 0) /* Bit 0: Refresh Error */ @@ -174,18 +178,19 @@ #define SDRAMC_OCMS_SDRSE (1 << 0) /* Bit 9: SDRAM Memory Controller Scrambling Enable */ /* SDRAMC OCMS KEY1 Register (32-bit value) */ + /* SDRAMC OCMS KEY2 Register (32-bit value) */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SDRAMC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_smc.h b/arch/arm/src/samv7/hardware/sam_smc.h index f6429657cad..173e15582ac 100644 --- a/arch/arm/src/samv7/hardware/sam_smc.h +++ b/arch/arm/src/samv7/hardware/sam_smc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_smc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SMC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SMC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SMC register offsets *****************************************************************/ +/* SMC register offsets *****************************************************/ #define SAM_SMCCS_OFFSET(n) ((n) << 4) # define SAM_SMCCS0_OFFSET 0x0000 /* SMC CS0 offset */ @@ -53,7 +53,7 @@ #define SAM_SMC_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */ #define SAM_SMC_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ -/* SMC register addresses ***************************************************************/ +/* SMC register addresses ***************************************************/ #define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n)) # define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS0_OFFSET) @@ -92,7 +92,7 @@ #define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET) #define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET) -/* SMC register bit definitions *********************************************************/ +/* SMC register bit definitions *********************************************/ /* SMC Setup Register */ @@ -151,6 +151,7 @@ # define SMCCS_MODE_TDFCYCLES(n) ((uint32_t)(n) << SMCCS_MODE_TDFCYCLES_SHIFT) #define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ #define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ + #define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ #define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) # define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ @@ -161,7 +162,9 @@ /* SMC OCMS Mode Register */ #define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ + #define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */ + # define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */ # define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */ # define SMC_OCMS_CS2SE (1 << 18) /* Bit 18: Chip Select 2 Scrambling Enable */ @@ -182,16 +185,16 @@ #define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ #define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SMC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_spi.h b/arch/arm/src/samv7/hardware/sam_spi.h index 0f3e0df608b..f1336ee1dea 100644 --- a/arch/arm/src/samv7/hardware/sam_spi.h +++ b/arch/arm/src/samv7/hardware/sam_spi.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_spi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SPI_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SPI_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include @@ -32,14 +32,15 @@ #if SAMV7_NSPI > 0 -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ -/* General definitions ******************************************************************/ + ****************************************************************************/ + +/* General definitions ******************************************************/ #define SAM_SPI_NCS 4 /* Four chip selects */ -/* SPI register offsets *****************************************************************/ +/* SPI register offsets *****************************************************/ #define SAM_SPI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_SPI_MR_OFFSET 0x0004 /* Mode Register */ @@ -59,7 +60,7 @@ #define SAM_SPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ /* 0xec-0xfc: Reserved */ -/* SPI register addresses ***************************************************************/ +/* SPI register addresses ***************************************************/ #define SAM_SPI0_CR (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ #define SAM_SPI0_MR (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ @@ -93,7 +94,7 @@ # define SAM_SPI1_WPSR (SAM_SPI1_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */ #endif -/* SPI register bit definitions *********************************************************/ +/* SPI register bit definitions *********************************************/ /* SPI Control Register */ @@ -117,6 +118,7 @@ # define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ # define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ # define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ + #define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */ #define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT) # define SPI_MR_DLYBCS(n) ((uint32_t)(n) << SPI_MR_DLYBCS_SHIFT) @@ -142,9 +144,11 @@ # define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ # define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ # define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ + #define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ -/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register, +/* SPI Status Register, SPI Interrupt Enable Register, + * SPI Interrupt Disable Register, * and SPI Interrupt Mask Register (common bit fields) */ @@ -168,6 +172,7 @@ #define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */ #define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT) # define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */ + # define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */ # define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */ # define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */ @@ -177,6 +182,7 @@ # define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */ # define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */ # define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */ + #define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */ #define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT) # define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT) @@ -200,17 +206,17 @@ #define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ #define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* SAMV7_NSPI > 0 */ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SPI_H */ diff --git a/arch/arm/src/samv7/hardware/sam_ssc.h b/arch/arm/src/samv7/hardware/sam_ssc.h index eb43c42459b..9fb205d443a 100644 --- a/arch/arm/src/samv7/hardware/sam_ssc.h +++ b/arch/arm/src/samv7/hardware/sam_ssc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_ssc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SSC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SSC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -32,17 +32,17 @@ #if SAMV7_NSSC > 0 -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ - /* The maximum clock speed allowed on the TK and RK pins is the peripheral clock - * divided by 2. - */ +/* The maximum clock speed allowed on the TK and RK pins is the + * peripheral clock divided by 2. + */ #define SAM_SSC_MAXPERCLK (BOARD_MCK_FREQUENCY >> 1) -/* SSC Register Offsets *************************************************************/ +/* SSC Register Offsets *****************************************************/ #define SAM_SSC_CR_OFFSET 0x0000 /* Control Register */ #define SAM_SSC_CMR_OFFSET 0x0004 /* Clock Mode Register */ @@ -67,7 +67,7 @@ #define SAM_SSC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ /* 0x00ec-0x0124 Reserved */ -/* SSC Register Addresses ***********************************************************/ +/* SSC Register Addresses ***************************************************/ #define SAM_SSC0_CR (SAM_SSC0_BASE+SAM_SSC_CR_OFFSET) #define SAM_SSC0_CMR (SAM_SSC0_BASE+SAM_SSC_CMR_OFFSET) @@ -109,7 +109,7 @@ # define SAM_SSC1_WPSR (SAM_SSC1_BASE+SAM_SSC_WPSR_OFFSET) #endif -/* SSC Register Bit Definitions *****************************************************/ +/* SSC Register Bit Definitions *********************************************/ /* Control Register */ @@ -130,17 +130,20 @@ # define SSC_RCMR_CKS_MCK (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */ # define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */ # define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ + #define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ #define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) # define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None, RK pin is an input */ # define SSC_RCMR_CKO_CONT (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock, RK pin is an output */ # define SSC_RCMR_CKO_TRANSFER (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock during transfers, RK pin is an output */ + #define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ #define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */ #define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT) # define SSC_RCMR_CKG_CONT (0 << SSC_RCMR_CKG_SHIFT) /* None */ # define SSC_RCMR_CKG_ENRFLOW (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Pin is Low */ # define SSC_RCMR_CKG_ENRFHIGH (3 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Pin is High */ + #define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */ #define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT) # define SSC_RCMR_START_CONT (0 << SSC_RCMR_START_SHIFT) /* Continuous */ @@ -152,6 +155,7 @@ # define SSC_RCMR_START_LEVEL (6 << SSC_RCMR_START_SHIFT) /* Detection of any level change on RF signal */ # define SSC_RCMR_START_EDGE (7 << SSC_RCMR_START_SHIFT) /* Detection of any edge on RF signal */ # define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ + #define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Selection */ #define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */ #define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) @@ -181,6 +185,7 @@ # define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* Low during transfer, RF pin is an output */ # define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* High during transfer, RF pin is an output */ # define SSC_RFMR_FSOS_TOGGLING (5 << SSC_RFMR_FSOS_SHIFT) /* Toggling each transfer, RF pin is an output */ + #define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ # define SSC_RFMR_FSEDGE_POS (0) /* Bit 24: 0=Positive Edge Detection */ # define SSC_RFMR_FSEDGE_NEG (1 << 24) /* Bit 24: 1=Negative Edge Detection */ @@ -195,17 +200,20 @@ # define SSC_TCMR_CKS_MCK (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ # define SSC_TCMR_CKS_RK (1 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */ # define SSC_TCMR_CKS_TK (2 << SSC_TCMR_CKS_SHIFT) /* TK pin */ + #define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ #define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) # define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None, TK pin is an input */ # define SSC_TCMR_CKO_CONT (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock, TK pin is an output */ # define SSC_TCMR_CKO_TRANSFER (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock during transfers, TK pin is an output */ + #define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ #define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */ #define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT) # define SSC_TCMR_CKG_CONT (0 << SSC_TCMR_CKG_SHIFT) /* None */ # define SSC_TCMR_CKG_ENTFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Transmit Clock enabled only if TF pin is Low */ -# define SSC_TCMR_CKG_ENTFHIGH (2 << SSC_TCMR_CKG_SHIFT) /*Transmit Clock enabled only if TF pin is High */ +# define SSC_TCMR_CKG_ENTFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Transmit Clock enabled only if TF pin is High */ + #define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */ #define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT) # define SSC_TCMR_START_CONT (0 << SSC_TCMR_START_SHIFT) /* Continuous */ @@ -216,6 +224,7 @@ # define SSC_TCMR_START_RISING (5 << SSC_TCMR_START_SHIFT) /* Detection of a rising edge on TF signal */ # define SSC_TCMR_START_LEVEL (6 << SSC_TCMR_START_SHIFT) /* Detection of any level change on TF signal */ # define SSC_TCMR_START_EDGE (7 << SSC_TCMR_START_SHIFT) /* Detection of any edge on TF signal */ + #define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 15-23: Transmit Start Delay */ #define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT) # define SSC_TCMR_STTDLY(n) ((uint32_t)(n) << SSC_TCMR_STTDLY_SHIFT) @@ -244,6 +253,7 @@ # define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* TF pin Driven Low during data transfer */ # define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* TF pin Driven High during data transfer */ # define SSC_TFMR_FSOS_TOGGLING (5 << SSC_TFMR_FSOS_SHIFT) /* TF pin Toggles at each start of data transfer */ + #define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */ #define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ # define SSC_TFMR_FSEDGE_POS (0) /* Bit 24: 0=Positive Edge Detection */ @@ -253,6 +263,7 @@ # define SSC_TFMR_FSLENEXT(n) ((uint32_t)(n) << SSC_TFMR_FSLENEXT_SHIFT) /* Receive Holding Register (32-bit data value) */ + /* Transmit Holding Register (32-bit data value) */ /* Receive Sync. Holding Register */ @@ -271,8 +282,8 @@ #define SSC_RC1R_MASK (0x0000ffff) /* Bit 0-15: Receive Compare Data 1 */ -/* Status Register , Interrupt Enable Register, Interrupt Disable Register, and - * Interrupt Mask Register +/* Status Register, Interrupt Enable Register, + * Interrupt Disable Register, and Interrupt Mask Register */ #define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */ diff --git a/arch/arm/src/samv7/hardware/sam_supc.h b/arch/arm/src/samv7/hardware/sam_supc.h index aecf16d07f8..c5cc74c7e72 100644 --- a/arch/arm/src/samv7/hardware/sam_supc.h +++ b/arch/arm/src/samv7/hardware/sam_supc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_supc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SUPC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SUPC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SUPC register offsets ****************************************************************/ +/* SUPC register offsets ****************************************************/ #define SAM_SUPC_CR_OFFSET 0x0000 /* Supply Controller Control Register */ #define SAM_SUPC_SMMR_OFFSET 0x0004 /* Supply Controller Supply Monitor Mode Register */ @@ -43,7 +43,7 @@ #define SAM_SUPC_WUIR_OFFSET 0x0010 /* Supply Controller Wake Up Inputs Register */ #define SAM_SUPC_SR_OFFSET 0x0014 /* Supply Controller Status Register */ -/* SUPC register addresses **************************************************************/ +/* SUPC register addresses **************************************************/ #define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) #define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) @@ -52,7 +52,8 @@ #define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) #define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) -/* SUPC register bit definitions ********************************************************/ +/* SUPC register bit definitions ********************************************/ + /* Supply Controller Control Register */ #define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ @@ -82,6 +83,7 @@ # define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.12 < 3.16 < 3.20 */ # define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.24 < 3.28 < 3.32 */ # define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.36 < 3.40 < 3.44 */ + #define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ #define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) # define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ @@ -89,6 +91,7 @@ # define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ # define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ # define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ + #define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ #define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ @@ -119,6 +122,7 @@ # define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ # define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ # define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ + #define SUPC_WUMR_LPDBC_SHIFT (16) /* Bits 16-18: Low Power Debouncer Period */ #define SUPC_WUMR_LPDBC_MASK (7 << SUPC_WUMR_LPDBC_SHIFT) # define SUPC_WUMR_LPDBC_DISABLE (0 << SUPC_WUMR_LPDBC_SHIFT) /* Disable low power debouncer */ @@ -154,16 +158,16 @@ #define SUPC_SR_WKUPIS_MASK (0x3fff << SUPC_SR_WKUPIS_SHIFT) # define SUPC_SR_WKUPIS(n) (1 << (SUPC_SR_WKUPIS_SHIFT+(n))) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SUPC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_sysc.h b/arch/arm/src/samv7/hardware/sam_sysc.h index 4126e8cc31d..dda27a6e3b1 100644 --- a/arch/arm/src/samv7/hardware/sam_sysc.h +++ b/arch/arm/src/samv7/hardware/sam_sysc.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_sysc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,33 +16,34 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SYSC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SYSC_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* SYSC register offsets ****************************************************************/ +/* SYSC register offsets ****************************************************/ #define SAM_SYSC_WPMR_OFFSET 0x0004 /* Write Protection Mode Register */ -/* SYSC register addresses **************************************************************/ +/* SYSC register addresses **************************************************/ #define SAM_SYSC_WPMR (SAM_SYSC_BASE+SAM_SYSC_WPMR_OFFSET) -/* SYSC register bit definitions ********************************************************/ +/* SYSC register bit definitions ********************************************/ + /* System Controller Write Protect Mode Register */ #define SYSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ @@ -50,16 +51,16 @@ #define SYSC_WPMR_WPKEY_MASK (0x00ffffff << SYSC_WPMR_WPKEY_SHIFT) # define SYSC_WPMR_WPKEY (0x00525443 << SYSC_WPMR_WPKEY_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SYSC_H */ diff --git a/arch/arm/src/samv7/hardware/sam_tc.h b/arch/arm/src/samv7/hardware/sam_tc.h index 6ff16b305f3..d4322fd317f 100644 --- a/arch/arm/src/samv7/hardware/sam_tc.h +++ b/arch/arm/src/samv7/hardware/sam_tc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_tc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define SAM_TC_NCHANNELS 3 /* Number of channels per TC peripheral */ -/* TC Register Offsets **************************************************************/ +/* TC Register Offsets ******************************************************/ #define SAM_TC_CHAN_OFFSET(n) ((n) << 6) /* Channel n offset */ #define SAM_TC_CCR_OFFSET 0x0000 /* Channel Control Register */ @@ -116,7 +116,7 @@ #define SAM_TC_FMR_OFFSET 0x00d8 /* Fault Mode Register */ #define SAM_TC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ -/* TC Register Addresses ************************************************************/ +/* TC Register Addresses ****************************************************/ #define SAM_TC012_CHAN_BASE(n) (SAM_TC012_BASE+SAM_TC_CHAN_OFFSET(n)) @@ -386,7 +386,7 @@ #define SAM_TC901_FMR (SAM_TC901_BASE+SAM_TC_FMR_OFFSET) #define SAM_TC901_WPMR (SAM_TC901_BASE+SAM_TC_WPMR_OFFSET) -/* TC Register Bit Definitions ******************************************************/ +/* TC Register Bit Definitions **********************************************/ /* Channel Control Register */ @@ -412,6 +412,7 @@ # define TC_CMR_TCCLKS_XC0 (5 << TC_CMR_TCCLKS_SHIFT) /* XC0 Clock selected */ # define TC_CMR_TCCLKS_XC1 (6 << TC_CMR_TCCLKS_SHIFT) /* XC1 Clock selected */ # define TC_CMR_TCCLKS_XC2 (7 << TC_CMR_TCCLKS_SHIFT) /* XC2 Clock selected */ + #define TC_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert */ #define TC_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection */ #define TC_CMR_BURST_MASK (3 << TC_CMR_BURST_SHIFT) @@ -430,6 +431,7 @@ # define TC_CMR_ETRGEDG_RISING (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */ # define TC_CMR_ETRGEDG_FALLING (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */ # define TC_CMR_ETRGEDG_BOTH (3 << TC_CMR_ETRGEDG_SHIFT) /* EDGE Each edge */ + #define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */ #define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */ #define TC_CMR_CAPTURE (0) /* Bit 15: 0=Capture Mode */ @@ -439,12 +441,14 @@ # define TC_CMR_LDRA_RISING (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ # define TC_CMR_LDRA_FALLING (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ # define TC_CMR_LDRA_BOTH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */ + #define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Edge Selection */ #define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT) # define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */ # define TC_CMR_LDRB_RISING (1 << TC_CMR_LDRB_SHIFT) /* Rising edge of TIOA */ # define TC_CMR_LDRB_FALLING (2 << TC_CMR_LDRB_SHIFT) /* Falling edge of TIOA */ # define TC_CMR_LDRB_BOTH (3 << TC_CMR_LDRB_SHIFT) /* Each edge of TIOA */ + #define TC_CMR_SBSMPLR_SHIFT (20) /* Bits 20-22: Loading Edge Subsampling Ratio */ #define TC_CMR_SBSMPLR_MASK (7 << TC_CMR_SBSMPLR_SHIFT) # define TC_CMR_SBSMPLR_ONE (0 << TC_CMR_SBSMPLR_SHIFT) /* Load on each selected edge */ @@ -463,12 +467,14 @@ # define TC_CMR_EEVTEDG_RISING (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */ # define TC_CMR_EEVTEDG_FALLING (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */ # define TC_CMR_EEVTEDG_BOTH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */ + #define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection */ #define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT) # define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB(1) input */ # define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 output */ # define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 output */ # define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 output */ + #define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable */ #define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection */ #define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT) @@ -476,6 +482,7 @@ # define TC_CMR_WAVSEL_UPDOWN (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o trigger on RC Compare */ # define TC_CMR_WAVSEL_UPRC (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode w/ trigger on RC Compare */ # define TC_CMR_WAVSEL_UPDOWNRC (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN w/ with trigger on RC Compare */ + #define TC_CMR_WAVE (1 << 15) /* Bit 15: 1=Waveform Mode */ #define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA */ #define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT) @@ -483,42 +490,49 @@ # define TC_CMR_ACPA_SET (1 << TC_CMR_ACPA_SHIFT) /* Set */ # define TC_CMR_ACPA_CLEAR (2 << TC_CMR_ACPA_SHIFT) /* Clear */ # define TC_CMR_ACPA_TOGGLE (3 << TC_CMR_ACPA_SHIFT) /* Toggle */ + #define TC_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA */ #define TC_CMR_ACPC_MASK (3 << TC_CMR_ACPC_SHIFT) # define TC_CMR_ACPC_NONE (0 << TC_CMR_ACPC_SHIFT) /* None */ # define TC_CMR_ACPC_SET (1 << TC_CMR_ACPC_SHIFT) /* Set */ # define TC_CMR_ACPC_CLEAR (2 << TC_CMR_ACPC_SHIFT) /* Clear */ # define TC_CMR_ACPC_TOGGLE (3 << TC_CMR_ACPC_SHIFT) /* Toggle */ + #define TC_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA */ #define TC_CMR_AEEVT_MASK (3 << TC_CMR_AEEVT_SHIFT) # define TC_CMR_AEEVT_NONE (0 << TC_CMR_AEEVT_SHIFT) /* None */ # define TC_CMR_AEEVT_SET (1 << TC_CMR_AEEVT_SHIFT) /* Set */ # define TC_CMR_AEEVT_CLEAR (2 << TC_CMR_AEEVT_SHIFT) /* Clear */ # define TC_CMR_AEEVT_TOGGLE (3 << TC_CMR_AEEVT_SHIFT) /* Toggle */ + #define TC_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA */ #define TC_CMR_ASWTRG_MASK (3 << TC_CMR_ASWTRG_SHIFT) # define TC_CMR_ASWTRG_NONE (0 << TC_CMR_ASWTRG_SHIFT) /* None */ # define TC_CMR_ASWTRG_SET (1 << TC_CMR_ASWTRG_SHIFT) /* Set */ # define TC_CMR_ASWTRG_CLEAR (2 << TC_CMR_ASWTRG_SHIFT) /* Clear */ # define TC_CMR_ASWTRG_TOGGLE (3 << TC_CMR_ASWTRG_SHIFT) /* Toggle */ + #define TC_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB */ #define TC_CMR_BCPB_MASK (3 << TC_CMR_BCPB_SHIFT) # define TC_CMR_BCPB_NONE (0 << TC_CMR_BCPB_SHIFT) /* None */ # define TC_CMR_BCPB_SET (1 << TC_CMR_BCPB_SHIFT) /* Set */ # define TC_CMR_BCPB_CLEAR (2 << TC_CMR_BCPB_SHIFT) /* Clear */ # define TC_CMR_BCPB_TOGGLE (3 << TC_CMR_BCPB_SHIFT) /* Toggle */ + #define TC_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB */ #define TC_CMR_BCPC_MASK (3 << TC_CMR_BCPC_SHIFT) # define TC_CMR_BCPC_NONE (0 << TC_CMR_BCPC_SHIFT) /* None */ # define TC_CMR_BCPC_SET (1 << TC_CMR_BCPC_SHIFT) /* Set */ # define TC_CMR_BCPC_CLEAR (2 << TC_CMR_BCPC_SHIFT) /* Clear */ # define TC_CMR_BCPC_TOGGLE (3 << TC_CMR_BCPC_SHIFT) /* Toggle */ + #define TC_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB */ #define TC_CMR_BEEVT_MASK (3 << TC_CMR_BEEVT_SHIFT) # define TC_CMR_BEEVT_NONE (0 << TC_CMR_BEEVT_SHIFT) /* None */ # define TC_CMR_BEEVT_SET (1 << TC_CMR_BEEVT_SHIFT) /* Set */ # define TC_CMR_BEEVT_CLEAR (2 << TC_CMR_BEEVT_SHIFT) /* Clear */ # define TC_CMR_BEEVT_TOGGLE (3 << TC_CMR_BEEVT_SHIFT) /* Toggle */ + #define TC_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB */ #define TC_CMR_BSWTRG_MASK (3 << TC_CMR_BSWTRG_SHIFT) # define TC_CMR_BSWTRG_NONE (0 << TC_CMR_BSWTRG_SHIFT) /* None */ @@ -532,13 +546,17 @@ #define TC_SMMR_DOWN (1 << 1) /* Bit 1: DOWN Count */ /* Register AB (32-bit capture value) */ + /* Counter Value (32-bit counter value) */ + /* Register A (32-bit value) */ + /* Register B (32-bit value) */ + /* Register C (32-bit value) */ -/* Status Register, Interrupt Enable Register, Interrupt Disable Register, and - * Interrupt Mask Register +/* Status Register, Interrupt Enable Register, + * Interrupt Disable Register, and Interrupt Mask Register */ #define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow Status */ @@ -561,10 +579,12 @@ #define TC_EMR_TRIGSRCA_MASK (3 << TC_EMR_TRIGSRCA_SHIFT) # define TC_EMR_TRIGSRCA_TIOA (0 << TC_EMR_TRIGSRCA_SHIFT) /* Trigger/capture input A driven by TIOAx */ # define TC_EMR_TRIGSRCA_PWM (1 << TC_EMR_TRIGSRCA_SHIFT) /* Trigger/capture input A driven by PWMx */ + #define TC_EMR_TRIGSRCB_SHIFT (4) /* Bits 4-5: Trigger source for input B */ #define TC_EMR_TRIGSRCB_MASK (3 << TC_EMR_TRIGSRCB_SHIFT) # define TC_EMR_TRIGSRCB_TIOB (0 << TC_EMR_TRIGSRCB_SHIFT) /* Trigger/capture input B driven by TIOBx */ # define TC_EMR_TRIGSRCB_PWM (1 << TC_EMR_TRIGSRCB_SHIFT) /* Trigger/capture input B driven PWMx */ + #define TC_EMR_NODIVCLK (1 << 8) /* Bit 8: No divided clock */ /* Block Control Register */ @@ -578,16 +598,19 @@ # define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT) /* TCLK0 Signal to XC0 */ # define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT) /* TIOA1 Signal to XC0 */ # define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT) /* TIOA2 Signal to XC0 */ + #define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */ #define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_SHIFT) # define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT) /* TCLK1 Signal to XC1 */ # define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT) /* TIOA0 Signal to XC1 */ # define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) /* TIOA2 Signal to XC1 */ + #define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */ #define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) # define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) /* TCLK2 Signal to XC2 */ # define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) /* TIOA0 Signal to XC2 */ # define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) /* TIOA1 Signal to XC2 */ + #define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder ENabled */ #define TC_BMR_POSEN (1 << 9) /* Bit 9: POSition ENabled */ #define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: SPEED ENabled */ @@ -602,7 +625,8 @@ #define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT) # define TC_BMR_MAXFILT(n) ((uint32_t)(n) << TC_BMR_MAXFILT_SHIFT) -/* QDEC Interrupt Enable Register, QDEC Interrupt Disable Register, QDEC Interrupt Mask Register, and QDEC Interrupt Status Register. +/* QDEC Interrupt Enable Register, QDEC Interrupt Disable Register, + * QDEC Interrupt Mask Register, and QDEC Interrupt Status Register. */ #define TC_QINT_IDX (1 << 0) /* Bit 0: Index */ diff --git a/arch/arm/src/samv7/hardware/sam_trng.h b/arch/arm/src/samv7/hardware/sam_trng.h index ca08d3d8dc6..c80f4fec3e1 100644 --- a/arch/arm/src/samv7/hardware/sam_trng.h +++ b/arch/arm/src/samv7/hardware/sam_trng.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_trng.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TRNG_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TRNG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/sam_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* TRNG Register Offsets ************************************************************/ + ****************************************************************************/ + +/* TRNG Register Offsets ****************************************************/ #define SAM_TRNG_CR_OFFSET 0x0000 /* Control Register */ #define SAM_TRNG_IER_OFFSET 0x0010 /* Interrupt Enable Register */ @@ -40,7 +41,7 @@ #define SAM_TRNG_ISR_OFFSET 0x001c /* Interrupt Status Register */ #define SAM_TRNG_ODATA_OFFSET 0x0050 /* Output Data Register */ -/* TRNG Register Addresses **********************************************************/ +/* TRNG Register Addresses **************************************************/ #define SAM_TRNG_CR (SAM_TRNG_BASE+SAM_TRNG_CR_OFFSET) #define SAM_TRNG_IER (SAM_TRNG_BASE+SAM_TRNG_IER_OFFSET) @@ -49,7 +50,7 @@ #define SAM_TRNG_ISR (SAM_TRNG_BASE+SAM_TRNG_ISR_OFFSET) #define SAM_TRNG_ODATA (SAM_TRNG_BASE+SAM_TRNG_ODATA_OFFSET) -/* TRNG Register Bit Definitions ****************************************************/ +/* TRNG Register Bit Definitions ********************************************/ /* Control Register */ @@ -59,8 +60,8 @@ #define TRNG_CR_KEY_MASK (0xffffff << TRNG_CR_KEY_SHIFT) # define TRNG_CR_KEY (0x524e47 << TRNG_CR_KEY_SHIFT) /* RNG in ASCII */ -/* Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, - * and Interrupt Status Register +/* Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Interrupt Status Register */ #define TRNG_INT_DATRDY (1 << 0) /* Bit 0: Data ready */ diff --git a/arch/arm/src/samv7/hardware/sam_twihs.h b/arch/arm/src/samv7/hardware/sam_twihs.h index 0370ba8827d..07051a77ac0 100644 --- a/arch/arm/src/samv7/hardware/sam_twihs.h +++ b/arch/arm/src/samv7/hardware/sam_twihs.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_twihs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TWIHS_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TWIHS_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include @@ -32,11 +32,11 @@ #if SAMV7_NTWIHS > 0 -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* TWIHS register offsets *****************************************************************/ +/* TWIHS register offsets ***************************************************/ #define SAM_TWIHS_CR_OFFSET 0x0000 /* Control Register */ #define SAM_TWIHS_MMR_OFFSET 0x0004 /* Master Mode Register */ @@ -57,7 +57,7 @@ #define SAM_TWIHS_WPMR_OFFSET 0x00e4 /* Protection Mode Register */ #define SAM_TWIHS_WPSR_OFFSET 0x00e8 /* Protection Status Register */ -/* TWIHS register addresses ***************************************************************/ +/* TWIHS register addresses *************************************************/ #define SAM_TWIHS0_CR (SAM_TWIHS0_BASE+SAM_TWIHS_CR_OFFSET) #define SAM_TWIHS0_MMR (SAM_TWIHS0_BASE+SAM_TWIHS_MMR_OFFSET) @@ -114,7 +114,8 @@ # define SAM_TWIHS2_WPSR (SAM_TWIHS2_BASE)+SAM_TWIHS_WPSR_OFFSET) #endif -/* TWIHS register bit definitions *********************************************************/ +/* TWIHS register bit definitions *******************************************/ + /* TWIHS Control Register */ #define TWIHS_CR_START (1 << 0) /* Bit 0: Send SAMV7_NTWIHS START Condition */ @@ -142,6 +143,7 @@ # define TWIHS_MMR_IADRSZ_1BYTE (1 << TWIHS_MMR_IADRSZ_SHIFT) /* One-byte internal device address */ # define TWIHS_MMR_IADRSZ_2BYTE (2 << TWIHS_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ # define TWIHS_MMR_IADRSZ_3BYTE (3 << TWIHS_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ + #define TWIHS_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ #define TWIHS_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */ #define TWIHS_MMR_DADR_MASK (0x7f << TWIHS_MMR_DADR_SHIFT) @@ -184,8 +186,8 @@ #define TWIHS_CWGR_HOLD_MASK (31 << TWIHS_CWGR_HOLD_SHIFT) # define TWIHS_CWGR_HOLD(n) ((uint32_t)(n) << TWIHS_CWGR_HOLD_SHIFT) -/* TWIHS Status Register, TWIHS Interrupt Enable Register, TWIHS Interrupt Disable - * Register, and TWIHS Interrupt Mask Register common bit fields. +/* TWIHS Status Register, TWIHS Interrupt Enable Register, TWIHS Interrupt + * Disable Register, and TWIHS Interrupt Mask Register common bit fields. */ #define TWIHS_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed */ @@ -221,7 +223,6 @@ #define TWIHS_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */ #define TWIHS_THR_TXDATA_MASK (0xff << TWIHS_THR_TXDATA_SHIFT) - /* SMBus Timing Register */ #define TWIHS_SMBTR_PRESC_SHIFT (0) /* Bits 0-3: SMBus Clock Prescaler */ @@ -274,17 +275,17 @@ #define TWIHS_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ #define TWIHS_WPSR_WPVSRC_MASK (0xffff << TWIHS_WPSR_WPVSRC_SHIFT) -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* SAMV7_NTWIHS > 0 */ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TWIHS_H */ diff --git a/arch/arm/src/samv7/hardware/sam_uart.h b/arch/arm/src/samv7/hardware/sam_uart.h index 8d58890193a..7c3e9cdc9e7 100644 --- a/arch/arm/src/samv7/hardware/sam_uart.h +++ b/arch/arm/src/samv7/hardware/sam_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UART_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UART_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "arch/samv7/chip.h" #include "hardware/sam_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* UART register offsets ************************************************************************/ +/* UART register offsets ****************************************************/ #define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ #define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ @@ -71,7 +71,7 @@ #define SAM_UART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ /* 0x00ec-0x00fc: Reserved (USART) */ -/* UART register addresses **********************************************************************/ +/* UART register addresses **************************************************/ #if SAMV7_NUART > 0 # define SAM_UART0_CR (SAM_UART0_BASE+SAM_UART_CR_OFFSET) @@ -234,7 +234,7 @@ # define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_UART_WPSR_OFFSET) #endif -/* UART register bit definitions ****************************************************************/ +/* UART register bit definitions ********************************************/ /* UART Control Register */ @@ -268,6 +268,7 @@ # define UART_MR_MODE_LON (9 << UART_MR_MODE_SHIFT) /* LON */ # define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master (SPI mode only) */ # define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave (SPI mode only) */ + #define UART_MR_DFILTER (1 << 4) /* Bit 4: Receiver Digital Filter (UART only) */ #define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ #define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) @@ -275,12 +276,14 @@ # define UART_MR_USCLKS_MCKDIV (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ # define UART_MR_USCLKS_PCK (2 << UART_MR_USCLKS_SHIFT) /* PMC programmable clock (PCK), UART mode */ # define UART_MR_USCLKS_SCK (3 << UART_MR_USCLKS_SHIFT) /* SCK */ + #define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ #define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) # define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits), UART mode only */ # define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits), UART mode only */ # define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits), UART mode only */ # define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */ + #define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART, UART mode only) */ #define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART, SPI mode only) */ #define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common, UART mode) */ @@ -291,18 +294,21 @@ # define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ # define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ # define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ + #define UART_MR_BRSRCCK (1 << 12) /* Bit 12: Baud Rate Source Clock (UART only) */ #define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART, UART mode only) */ #define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT) # define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ # define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ # define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ + #define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common, UART mode) */ #define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) # define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ # define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ # define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ # define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ + #define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first (USART, UART mode only) */ #define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity (USART, SPI mode only) */ #define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART, UART mode only) */ @@ -315,8 +321,10 @@ #define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ #define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ -/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask - * Register, and UART Status Register common bit field definitions +/* UART Interrupt Enable Register, + * UART Interrupt Disable Register, + * UART Interrupt Mask Register, + * and UART Status Register common bit field definitions */ #define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ @@ -403,7 +411,8 @@ #define UART_TTGR_PCYCLE_MASK (0xffffff << UART_TTGR_PCYCLE_SHIFT) /* USART FI DI RATIO Register (LON_MODE) - * REVISIT: In the preliminary datasheet, these bit fields are identified, but there no no + * REVISIT: In the preliminary datasheet, + * these bit fields are identified, but there no no * defined address for the FIDL register. */ @@ -421,6 +430,7 @@ # define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */ # define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */ + #define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ #define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ #define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT) @@ -431,6 +441,7 @@ # define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */ # define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */ # define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */ + #define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ #define UART_MAN_ONE (1 << 29) /* Bit 29: Must Be Set to 1 */ #define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ @@ -443,6 +454,7 @@ # define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */ # define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */ # define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does not transmit or receive response */ + #define UART_LINMR_PARDIS (1 << 2) /* Bit 2: Parity Disable */ #define UART_LINMR_CHKDIS (1 << 3) /* Bit 3: Checksum Disable */ #define UART_LINMR_CHKTYP (1 << 4) /* Bit 4: Checksum Type */ @@ -542,16 +554,16 @@ #define UART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ #define UART_WPSR_WPVSRC_MASK (0xffff << UART_WPSR_WPVSRC_SHIFT) -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UART_H */ diff --git a/arch/arm/src/samv7/hardware/sam_usbhs.h b/arch/arm/src/samv7/hardware/sam_usbhs.h index 7648f84de6f..c017e82fdeb 100644 --- a/arch/arm/src/samv7/hardware/sam_usbhs.h +++ b/arch/arm/src/samv7/hardware/sam_usbhs.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_usbhs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************************/ + ****************************************************************************/ /* References: * SAMV7D3 Series Data Sheet @@ -25,19 +25,21 @@ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_USBHS_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_USBHS_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ -/* General Definitions **************************************************************************************/ + ****************************************************************************/ + +/* General Definitions ******************************************************/ + /* Number of endpoints and DMA channels */ #define SAM_USBHS_NENDPOINTS 10 /* EP0-9 */ @@ -49,7 +51,8 @@ #define SAM_USBHS_NBANKS(ep) (((unsigned)(ep) < 1) ? 1 : (((unsigned)(ep) < 3) ? 3 : 2)) #define SAM_USBHS_DMA(ep) (((unsigned)(ep) < 1) ? false : (((unsigned)(ep) < 8) ? true : false)) -/* Register offsets *****************************************************************************************/ +/* Register offsets *********************************************************/ + /* USBHS Device Controller Register Offsets */ #define SAM_USBHS_DEVCTRL_OFFSET 0x0000 /* Device General Control Register */ @@ -113,7 +116,7 @@ #define SAM_USBHS_SFR_OFFSET 0x080c /* General Status Set Register */ /* 0x0810-0x082c: Reserved */ -/* Register addresses ***************************************************************************************/ +/* Register addresses *******************************************************/ /* USBHS Device Controller Register Addresses */ @@ -177,9 +180,10 @@ #define SAM_USBHS_SCR (SAM_USBHS_BASE+SAM_USBHS_SCR_OFFSET) #define SAM_USBHS_SFR (SAM_USBHS_BASE+SAM_USBHS_SFR_OFFSET) -/* Register bit-field definitions ***************************************************************************/ +/* Register bit-field definitions *******************************************/ /* USBHS Device Controller Register Bit Field Definitions */ + /* Device General Control Register */ #define USBHS_DEVCTRL_UADD_SHIFT (0) /* Bits 0-6: USBHS Address */ @@ -288,6 +292,7 @@ # define USBHS_DEVEPTCFG_EPBK_1BANK (0 << USBHS_DEVEPTCFG_EPBK_SHIFT) /* Single-bank endpoint */ # define USBHS_DEVEPTCFG_EPBK_2BANK (1 << USBHS_DEVEPTCFG_EPBK_SHIFT) /* Double-bank endpoint */ # define USBHS_DEVEPTCFG_EPBK_3BANK (2 << USBHS_DEVEPTCFG_EPBK_SHIFT) /* Triple-bank endpoint */ + #define USBHS_DEVEPTCFG_EPSIZE_SHIFT (4) /* Bits 4-6: Endpoint Size */ #define USBHS_DEVEPTCFG_EPSIZE_MASK (7 << USBHS_DEVEPTCFG_EPSIZE_SHIFT) # define USBHS_DEVEPTCFG_EPSIZE_8 (0 << USBHS_DEVEPTCFG_EPSIZE_SHIFT) /* 8 bytes */ @@ -298,6 +303,7 @@ # define USBHS_DEVEPTCFG_EPSIZE_256 (5 << USBHS_DEVEPTCFG_EPSIZE_SHIFT) /* 256 bytes */ # define USBHS_DEVEPTCFG_EPSIZE_512 (6 << USBHS_DEVEPTCFG_EPSIZE_SHIFT) /* 512 bytes */ # define USBHS_DEVEPTCFG_EPSIZE_1024 (7 << USBHS_DEVEPTCFG_EPSIZE_SHIFT) /* 1024 bytes */ + #define USBHS_DEVEPTCFG_EPDIR_SHIFT (8) /* Bit 8: Endpoint Direction */ #define USBHS_DEVEPTCFG_EPDIR_MASK (1 << 8) /* Bit 8: Endpoint Direction */ # define USBHS_DEVEPTCFG_EPDIR(n) ((uint32_t)(n) << 8) @@ -309,6 +315,7 @@ # define USBHS_DEVEPTCFG_EPTYPE_ISO (1 << USBHS_DEVEPTCFG_EPTYPE_SHIFT) /* Isochronous endpoint */ # define USBHS_DEVEPTCFG_EPTYPE_BLK (2 << USBHS_DEVEPTCFG_EPTYPE_SHIFT) /* Bulk endpoint */ # define USBHS_DEVEPTCFG_EPTYPE_INTRPT (3 << USBHS_DEVEPTCFG_EPTYPE_SHIFT) /* Interrupt endpoint */ + #define USBHS_DEVEPTCFG_NBTRANS_SHIFT (13) /* Bits 13-14: Number Transaction per uframe */ #define USBHS_DEVEPTCFG_NBTRANS_MASK (3 << USBHS_DEVEPTCFG_NBTRANS_SHIFT) # define USBHS_DEVEPTCFG_NBTRANS(n) ((uint32_t)(n) << USBHS_DEVEPTCFG_NBTRANS_SHIFT) @@ -338,14 +345,16 @@ #define USBHS_DEVEPTINT_CRCERRI (1 << 6) /* Bit 6: CRC Error Interrupt (3) */ #define USBHS_DEVEPTINT_SHRTPCKTI (1 << 7) /* Bit 7: Short Packet Interrupt */ -/* Device Endpoint Mask, Device Endpoint Disable, and Device Endpoint Enable Registers only */ +/* Device Endpoint Mask, Device Endpoint Disable, + * and Device Endpoint Enable Registers only + */ #define USBHS_DEVEPTINT_MDATAI (1 << 8) /* Bit 8: MData Interrupt (2) */ #define USBHS_DEVEPTINT_DATAXI (1 << 9) /* Bit 9: DataX Interrupt (2) */ #define USBHS_DEVEPTINT_ERRORTRANSI (1 << 10) /* Bit 10: Transaction Error Interrupt (2) */ -/* Device Endpoint Set, Device Endpoint Mask, Device Endpoint Disable, and Device Endpoint Enable - * Registers only +/* Device Endpoint Set, Device Endpoint Mask, Device Endpoint Disable, + * and Device Endpoint Enable Registers only */ #define USBHS_DEVEPTINT_NBUSYBKI (1 << 12) /* Bit 12: Number of Busy Banks Interrupt */ @@ -354,7 +363,9 @@ #define USBHS_DEVEPTINT_KILLBKI (1 << 13) /* Bit 13: Kill IN Bank */ -/* Device Endpoint Mask, Device Endpoint Disable, and Device Endpoint Enable Registers only */ +/* Device Endpoint Mask, Device Endpoint Disable, + * and Device Endpoint Enable Registers only + */ #define USBHS_DEVEPTINT_FIFOCONI (1 << 14) /* Bit 14: FIFO Control */ #define USBHS_DEVEPTINT_EPDISHDMAI (1 << 16) /* Bit 16: Endpoint Interrupts Disable HDMA Request */ @@ -375,6 +386,7 @@ # define USBHS_DEVEPTISR_DTSEQ_DATA1 (1 << USBHS_DEVEPTISR_DTSEQ_SHIFT) /* Data1 toggle sequence */ # define USBHS_DEVEPTISR_DTSEQ_DATA2 (2 << USBHS_DEVEPTISR_DTSEQ_SHIFT) /* Data1 toggle sequence (2) */ # define USBHS_DEVEPTISR_DTSEQ_MDATA (3 << USBHS_DEVEPTISR_DTSEQ_SHIFT) /* MData toggle sequence (2) */ + #define USBHS_DEVEPTISR_ERRORTRANS (1 << 10) /* Bit 10: High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt (2) */ #define USBHS_DEVEPTISR_NBUSYBK_SHIFT (12) /* Bits 12-13: Number of Busy Banks */ #define USBHS_DEVEPTISR_NBUSYBK_MASK (3 << USBHS_DEVEPTISR_NBUSYBK_SHIFT) @@ -382,11 +394,13 @@ # define USBHS_DEVEPTISR_NBUSYBK_1BUSY (1 << USBHS_DEVEPTISR_NBUSYBK_SHIFT) /* 1 busy bank */ # define USBHS_DEVEPTISR_NBUSYBK_2BUSY (2 << USBHS_DEVEPTISR_NBUSYBK_SHIFT) /* 2 busy banks */ # define USBHS_DEVEPTISR_NBUSYBK_3BUSY (3 << USBHS_DEVEPTISR_NBUSYBK_SHIFT) /* 3 busy banks */ + #define USBHS_DEVEPTISR_CURRBK_SHIFT (14) /* Bits 14-15: Current Bank */ #define USBHS_DEVEPTISR_CURRBK_MASK (3 << USBHS_DEVEPTISR_CURRBK_SHIFT) # define USBHS_DEVEPTISR_CURRBK_BANK0 (0 << USBHS_DEVEPTISR_CURRBK_SHIFT) /* Current bank is bank0 */ # define USBHS_DEVEPTISR_CURRBK_BANK1 (1 << USBHS_DEVEPTISR_CURRBK_SHIFT) /* Current bank is bank1 */ # define USBHS_DEVEPTISR_CURRBK_BANK2 (2 << USBHS_DEVEPTISR_CURRBK_SHIFT) /* Current bank is bank2 */ + #define USBHS_DEVEPTISR_RWALL (1 << 16) /* Bit 16: Read/Write Allowed */ #define USBHS_DEVEPTISR_CTRLDIR (1 << 17) /* Bit 17: Control Direction (1) */ # define USBHS_DEVEPTISR_CTRLDIR_OUT (0 << 17) /* 0=Following packet is an OUT packet */ @@ -395,7 +409,10 @@ #define USBHS_DEVEPTISR_BYCT_SHIFT (20) /* Bits 20-30: USBHS Byte Count */ #define USBHS_DEVEPTISR_BYCT_MASK (0x7ff << USBHS_DEVEPTISR_BYCT_SHIFT) -/* Device DMA Channel Next Descriptor Address Register (32-bit, 16 byte aligned address) */ +/* Device DMA Channel Next Descriptor Address Register + * (32-bit, 16 byte aligned address) + */ + /* Device DMA Channel Address Register (32-bit address) */ /* Device DMA Channel Control Register */ @@ -404,10 +421,12 @@ #define USBHS_DEVDMACTRL_CMD_MASK (3 << USBHS_DEVDMACTRL_CMD_SHIFT) # define USBHS_DEVDMACTRL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */ # define USBHS_DEVDMACTRL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Transfer Descriptor Enable Command */ + # define USBHS_DEVDMACTRL_STOPNOW (0 << USBHS_DEVDMACTRL_CMD_SHIFT) /* Stop now */ # define USBHS_DEVDMACTRL_RUNSTOP (1 << USBHS_DEVDMACTRL_CMD_SHIFT) /* Run and stop at end of buffer */ # define USBHS_DEVDMACTRL_LOADNEXT (2 << USBHS_DEVDMACTRL_CMD_SHIFT) /* Load next descriptor now */ # define USBHS_DEVDMACTRL_RUNLINK (3 << USBHS_DEVDMACTRL_CMD_SHIFT) /* Run and link at end of buffer */ + #define USBHS_DEVDMACTRL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable Control */ #define USBHS_DEVDMACTRL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable Control */ #define USBHS_DEVDMACTRL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */ @@ -430,6 +449,7 @@ # define USBHS_DEVDMASTA_BUFCNT(n) ((uint32_t)(n) << USBHS_DEVDMASTA_BUFCNT_SHIFT) /* USBHS Mini-Host Controller Register Bit Field Definitions */ + /* Host General Control Register */ #define USBHS_HSTCTRL_SOFE (1 << 8) /* Bit 8: Start of Frame Generation Enable */ @@ -582,6 +602,7 @@ # define USBHS_HSTPIPCFG_PBK_1BANK (0 << USBHS_HSTPIPCFG_PBK_SHIFT) /* Single-bank pipe */ # define USBHS_HSTPIPCFG_PBK_2BANK (1 << USBHS_HSTPIPCFG_PBK_SHIFT) /* Double-bank pipe */ # define USBHS_HSTPIPCFG_PBK_3BANK (2 << USBHS_HSTPIPCFG_PBK_SHIFT) /* Triple-bank pipe */ + #define USBHS_HSTPIPCFG_PSIZE_SHIFT (4) /* Bits 4-6: Pipe Size */ #define USBHS_HSTPIPCFG_PSIZE_MASK (7 << USBHS_HSTPIPCFG_PSIZE_SHIFT) # define USBHS_HSTPIPCFG_PSIZE_8 (0 << USBHS_HSTPIPCFG_PSIZE_SHIFT) /* 8 bytes */ @@ -592,6 +613,7 @@ # define USBHS_HSTPIPCFG_PSIZE_256 (5 << USBHS_HSTPIPCFG_PSIZE_SHIFT) /* 256 bytes */ # define USBHS_HSTPIPCFG_PSIZE_512 (6 << USBHS_HSTPIPCFG_PSIZE_SHIFT) /* 512 bytes */ # define USBHS_HSTPIPCFG_PSIZE_1024 (7 << USBHS_HSTPIPCFG_PSIZE_SHIFT) /* 1024 bytes */ + #define USBHS_HSTPIPCFG_PTOKEN_SHIFT (8) /* Bits 8-9: Pipe Token */ #define USBHS_HSTPIPCFG_PTOKEN_MASK (3 << USBHS_HSTPIPCFG_PTOKEN_SHIFT) # define USBHS_HSTPIPCFG_PTOKEN_SETUP (0 << USBHS_HSTPIPCFG_PTOKEN_SHIFT) @@ -604,6 +626,7 @@ # define USBHS_HSTPIPCFG_PTYPE_ISO (1 << USBHS_HSTPIPCFG_PTYPE_SHIFT) /* Isochronous pipe */ # define USBHS_HSTPIPCFG_PTYPE_BLK (2 << USBHS_HSTPIPCFG_PTYPE_SHIFT) /* Bulk pipe */ # define USBHS_HSTPIPCFG_PTYPE_INTRPT (3 << USBHS_HSTPIPCFG_PTYPE_SHIFT) /* Interrupt pipe */ + #define USBHS_HSTPIPCFG_PEPNUM_SHIFT (16) /* Bits 16-19: Pipe Endpoint Number */ #define USBHS_HSTPIPCFG_PEPNUM_MASK (15 << USBHS_HSTPIPCFG_PEPNUM_SHIFT) # define USBHS_HSTPIPCFG_PEPNUM(n) ((uint32_t)(n) << USBHS_HSTPIPCFG_PEPNUM_SHIFT) @@ -629,7 +652,7 @@ * (3) Isochronous pipes */ - /* All registers */ +/* All registers */ #define USBHS_HSTPIPINT_RXINI (1 << 0) /* Bit 0: Received IN Data Interrupt */ #define USBHS_HSTPIPINT_TXOUTI (1 << 1) /* Bit 1: Transmitted OUT Data Interrupt */ @@ -659,17 +682,20 @@ #define USBHS_HSTPIPISR_DTSEQ_MASK (3 << USBHS_HSTPIPISR_DTSEQ_SHIFT) # define USBHS_HSTPIPISR_DTSEQ_DATA0 (0 << USBHS_HSTPIPISR_DTSEQ_SHIFT) /* Data0 toggle sequence */ # define USBHS_HSTPIPISR_DTSEQ_DATA1 (1 << USBHS_HSTPIPISR_DTSEQ_SHIFT) /* Data1 toggle sequence */ + #define USBHS_HSTPIPISR_NBUSYBK_SHIFT (12) /* Bits 12-13: Number of Busy Banks */ #define USBHS_HSTPIPISR_NBUSYBK_MASK (3 << USBHS_HSTPIPISR_NBUSYBK_SHIFT) # define USBHS_HSTPIPISR_NBUSYBK_0BUSY (0 << USBHS_HSTPIPISR_NBUSYBK_SHIFT) /* 0 busy bank (all banks free) */ # define USBHS_HSTPIPISR_NBUSYBK_1BUSY (1 << USBHS_HSTPIPISR_NBUSYBK_SHIFT) /* 1 busy bank */ # define USBHS_HSTPIPISR_NBUSYBK_2BUSY (2 << USBHS_HSTPIPISR_NBUSYBK_SHIFT) /* 2 busy banks */ # define USBHS_HSTPIPISR_NBUSYBK_3BUSY (3 << USBHS_HSTPIPISR_NBUSYBK_SHIFT) /* 3 busy banks */ + #define USBHS_HSTPIPISR_CURRBK_SHIFT (14) /* Bits 14-15: Current Bank */ #define USBHS_HSTPIPISR_CURRBK_MASK (3 << USBHS_HSTPIPISR_CURRBK_SHIFT) # define USBHS_HSTPIPISR_CURRBK_BANK0 (0 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank0 */ # define USBHS_HSTPIPISR_CURRBK_BANK1 (1 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank1 */ # define USBHS_HSTPIPISR_CURRBK_BANK2 (2 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank2 */ + #define USBHS_HSTPIPISR_RWALL (1 << 16) /* Bit 16: Read/Write Allowed */ #define USBHS_HSTPIPISR_CFGOK (1 << 18) /* Bit 18: Configuration OK Status */ #define USBHS_HSTPIPISR_PBYCT_SHIFT (20) /* Bits 20-30: Pipe Byte Count */ @@ -694,6 +720,7 @@ # define USBHS_HSTPIPERR_COUNTER(n) ((uint32_t)(n) << USBHS_HSTPIPERR_COUNTER_SHIFT) /* Host DMA Channel Next Descriptor Address Register (32-bit address) */ + /* Host DMA Channel Address Register (32-bit address) */ /* Host DMA Channel Control Register */ @@ -702,10 +729,12 @@ #define USBHS_HSTDMACTRL_CMD_MASK (3 << USBHS_HSTDMACTRL_CMD_SHIFT) # define USBHS_HSTDMACTRL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */ # define USBHS_HSTDMACTRL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Transfer Descriptor Enable Command */ + # define USBHS_HSTDMACTRL_STOPNOW (0 << USBHS_HSTDMACTRL_CMD_SHIFT) /* Stop now */ # define USBHS_HSTDMACTRL_RUNSTOP (1 << USBHS_HSTDMACTRL_CMD_SHIFT) /* Run and stop at end of buffer */ # define USBHS_HSTDMACTRL_LOADNEXT (2 << USBHS_HSTDMACTRL_CMD_SHIFT) /* Load next descriptor now */ # define USBHS_HSTDMACTRL_RUNLINK (3 << USBHS_HSTDMACTRL_CMD_SHIFT) /* Run and link at end of buffer */ + #define USBHS_HSTDMACTRL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable Control */ #define USBHS_HSTDMACTRL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable Control */ #define USBHS_HSTDMACTRL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */ @@ -727,6 +756,7 @@ # define USBHS_HSTDMASTA_BUFCNT(n) ((uint32_t)(n) << USBHS_HSTDMASTA_BUFCNT_SHIFT) /* USBHS General Register Bit Field Definitions */ + /* General Control Register */ #define USBHS_CTRL_RDERRE (1 << 4) /* Bit 4: Remote Device Connection Error Interrupt Enable */ @@ -748,6 +778,7 @@ # define USBHS_SR_SPEED_FULL (0 << USBHS_SR_SPEED_SHIFT) /* Full-Speed mode */ # define USBHS_SR_SPEED_HIGH (1 << USBHS_SR_SPEED_SHIFT) /* High-Speed mode */ # define USBHS_SR_SPEED_LOW (2 << USBHS_SR_SPEED_SHIFT) /* Low-Speed mode */ + #define USBHS_SR_CLKUSABLE (1 << 14) /* Bit 14: UTMI Clock Usable */ /* General Status Clear Register */ @@ -760,16 +791,17 @@ #define USBHS_SFR_RDERRIS (1 << 4) /* Bit 4: Remote Device Connection Error Interrupt Set */ #define USBHS_SFR_VBUSRQS (1 << 9) /* Bit 9: VBus Request Set */ -/************************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************************/ + ****************************************************************************/ -/* This structure defines the USBHS DMA Transfer Descriptor. Instances of DMA transfer - * descriptors must by aligned to 16-byte address boundaries. +/* This structure defines the USBHS DMA Transfer Descriptor. + * Instances of DMA transfer descriptors must by aligned to 16-byte address + * boundaries. * - * Each value contains the next value of each of three USBHS DMA registers. The first - * register value (USBHS_xxxDMANXTDSCx) is a link that can be used to chain sequences of - * DMA transfers. + * Each value contains the next value of each of three USBHS DMA registers. + * The first register value (USBHS_xxxDMANXTDSCx) is a link that can be + * used to chain sequences of DMA transfers. */ struct usbhs_dtd_s @@ -780,12 +812,12 @@ struct usbhs_dtd_s }; #define SIZEOF_USPHS_DTD_S 12 -/************************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************************ - * Public Functions - ************************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_USBHS_H */ diff --git a/arch/arm/src/samv7/hardware/sam_utmi.h b/arch/arm/src/samv7/hardware/sam_utmi.h index 313456fecc1..fb27b2bcb63 100644 --- a/arch/arm/src/samv7/hardware/sam_utmi.h +++ b/arch/arm/src/samv7/hardware/sam_utmi.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_utmi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************************/ + ****************************************************************************/ /* References: * SAMV7D3 Series Data Sheet @@ -25,29 +25,30 @@ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UTMI_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UTMI_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ -/* Register offsets *****************************************************************************************/ + ****************************************************************************/ + +/* Register offsets *********************************************************/ #define SAM_UTMI_OHCIICR_OFFSET 0x0010 /* OHCI Interrupt Configuration Register */ #define SAM_UTMI_CKTRIM_OFFSET 0x0030 /* UTMI Clock Trimming Register */ -/* Register addresses ***************************************************************************************/ +/* Register addresses *******************************************************/ #define SAM_UTMI_OHCIICR (SAM_UTMI_BASE+SAM_UTMI_OHCIICR_OFFSET) #define SAM_UTMI_CKTRIM (SAM_UTMI_BASE+SAM_UTMI_CKTRIM_OFFSET) -/* Register bit-field definitions ***************************************************************************/ +/* Register bit-field definitions *******************************************/ /* OHCI Interrupt Configuration Register */ @@ -63,16 +64,16 @@ # define UTMI_CKTRIM_FREQ_XTAL12 (0 << UTMI_CKTRIM_FREQ_SHIFT) /* 12 MHz reference clock */ # define UTMI_CKTRIM_FREQ_XTAL16 (1 << UTMI_CKTRIM_FREQ_SHIFT) /* 16 MHz reference clock */ -/************************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************************ - * Public Functions - ************************************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UTMI_H */ diff --git a/arch/arm/src/samv7/hardware/sam_wdt.h b/arch/arm/src/samv7/hardware/sam_wdt.h index 0056a0ed6d8..43d5dc1cd39 100644 --- a/arch/arm/src/samv7/hardware/sam_wdt.h +++ b/arch/arm/src/samv7/hardware/sam_wdt.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_WDT_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_WDT_H -/**************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_memorymap.h" -/**************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + ****************************************************************************/ -/* WDT register offsets *****************************************************************/ +/* WDT register offsets *****************************************************/ #define SAM_WDT_CR_OFFSET 0x00 /* Control Register */ #define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */ #define SAM_WDT_SR_OFFSET 0x08 /* Status Register */ -/* WDT register addresses ***************************************************************/ +/* WDT register addresses ***************************************************/ /* WDT: Legacy Watchdog Timer */ @@ -54,7 +54,8 @@ #define SAM_RSWDT_MR (SAM_RSWDT_BASE+SAM_WDT_MR_OFFSET) #define SAM_RSWDT_SR (SAM_RSWDT_BASE+SAM_WDT_SR_OFFSET) -/* WDT register bit definitions *********************************************************/ +/* WDT register bit definitions *********************************************/ + /* Watchdog Timer Control Register */ #define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ @@ -86,16 +87,16 @@ #define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ #define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error (WDT only) */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_WDT_H */ diff --git a/arch/arm/src/samv7/hardware/sam_xdmac.h b/arch/arm/src/samv7/hardware/sam_xdmac.h index 09432ecc7c3..d0010fe3ce3 100644 --- a/arch/arm/src/samv7/hardware/sam_xdmac.h +++ b/arch/arm/src/samv7/hardware/sam_xdmac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/sam_xdmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_XDMAC_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_XDMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ -/* XDMAC Register Offsets ***********************************************************/ + ****************************************************************************/ + +/* XDMAC Register Offsets ***************************************************/ #define SAM_XDMAC_GTYPE_OFFSET 0x0000 /* Global Type Register */ #define SAM_XDMAC_GCFG_OFFSET 0x0004 /* Global Configuration Register */ @@ -80,7 +81,9 @@ # define SAM_XDMACH22_OFFSET 0x05d0 # define SAM_XDMACH23_OFFSET 0x0610 -/* Offsets to channel registers relative to the base of the DMA channel registers */ +/* Offsets to channel registers relative to the base of the DMA channel + * registers + */ #define SAM_XDMACH_CIE_OFFSET 0x0000 /* Channel Interrupt Enable Register */ #define SAM_XDMACH_CID_OFFSET 0x0004 /* Channel Interrupt Disable Register */ @@ -99,7 +102,7 @@ /* 0x0038-0x003c Reserved */ /* 0x0fec–0x0ffc Reserved */ -/* XDMAC Register Addresses *********************************************************/ +/* XDMAC Register Addresses *************************************************/ #define SAM_XDMAC_GTYPE (SAM_XDMAC_BASE+SAM_XDMAC_GTYPE_OFFSET) #define SAM_XDMAC_GCFG (SAM_XDMAC_BASE+SAM_XDMAC_GCFG_OFFSET) @@ -164,13 +167,13 @@ #define SAM_XDMACH_CSUS(n) (SAM_XDMACH_BASE(n)+SAM_XDMACH_CSUS_OFFSET) #define SAM_XDMACH_CDUS(n) (SAM_XDMACH_BASE(n)+SAM_XDMACH_CDUS_OFFSET) -/* XDMAC Register Bit Definitions ***************************************************/ +/* XDMAC Register Bit Definitions *******************************************/ /* Global Type Register */ #define XDMAC_GTYPE_NB_CH_SHIFT (0) /* Bits 0-4: Number of Channels Minus One */ #define XDMAC_GTYPE_NB_CH_MASK (31 << XDMAC_GTYPE_NB_CH_SHIFT) - #define XDMAC_GTYPE_NB_CH(n) ((uint32_t)(n) << XDMAC_GTYPE_NB_CH_SHIFT) +# define XDMAC_GTYPE_NB_CH(n) ((uint32_t)(n) << XDMAC_GTYPE_NB_CH_SHIFT) #define XDMAC_GTYPE_FIFO_SZ_SHIFT (5) /* Bits 5-15: Number of Bytes */ #define XDMAC_GTYPE_FIFO_SZ_MASK (0x7ff << XDMAC_GTYPE_FIFO_SZ_SHIFT) # define XDMAC_GTYPE_FIFO_SZ(n) ((uint32_t)(n) << XDMAC_GTYPE_FIFO_SZ_SHIFT) @@ -203,25 +206,26 @@ /* All of these registers have the same layout: * - * - Global Interrupt Enable Register, Global Interrupt Disable Register, Interrupt - * Mask Register, and Global Interrupt Status Register. + * - Global Interrupt Enable Register, Global Interrupt Disable Register, + * Interrupt Mask Register, and Global Interrupt Status Register. * - * - Global Channel Enable Register, Global Channel Disable Register, and Global - * Channel Status Register + * - Global Channel Enable Register, Global Channel Disable Register, and + * Global Channel Status Register * - * - Global Channel Read Suspend Register, Global Channel Write Suspend Register, - * Channel Read Write Suspend Register, and Global Channel Read Write Resume + * - Global Channel Read Suspend Register, Global Channel Write Suspend + * Register, Channel Read Write Suspend Register, and Global Channel + * Read Write Resume Register + * + * - Global Channel Software Request Register, Global Channel Software + * Request Status Register, and Global Channel Software Flush Request * Register - * - * - Global Channel Software Request Register, Global Channel Software Request - * Status Register, and Global Channel Software Flush Request Register */ #define XDMAC_CHAN(n) (1 << (n)) #define XDMAC_CHAN_ALL (0x0000ffff) -/* Channel Interrupt Enable Register, Channel Interrupt Disable Register, Channel - * Interrupt Mask Register, and Channel Interrupt Status Register. +/* Channel Interrupt Enable Register, Channel Interrupt Disable Register, + * Channel Interrupt Mask Register, and Channel Interrupt Status Register. */ #define XDMAC_CHINT_BI (1 << 0) /* Bit 0: End of Block Interrupt */ @@ -236,11 +240,14 @@ #define XDMAC_CHINT_ALL (0x0000007f) /* Channel Source Address (SA) Register (aligned 32-bit address) */ + /* Channel Destination Address (DA) Register (aligned 32-bit address) */ -/* Channel Next Descriptor Address (CNDA) Register (aligned 32-bit address) */ +/* Channel Next Descriptor Address (CNDA) Register + * (aligned 32-bit address) + */ -#define XDMACH_CNDA_NDAIF (1 << 0) /* Bit 0: Channel Next Descriptor Interface */ +#define XDMACH_CNDA_NDAIF (1 << 0) /* Bit 0: Channel Next Descriptor Interface */ #define XDMACH_CNDA_NDA_MASK (0xfffffffc) /* Bit 2-31: Channel Next Descriptor Address */ /* Channel Next Descriptor Control Register */ @@ -271,10 +278,12 @@ #define XDMACH_CC_MBSIZE_SHIFT (1) /* Bits 1-2: Channel Memory Burst Size */ #define XDMACH_CC_MBSIZE_MASK (3 << XDMACH_CC_MBSIZE_SHIFT) # define XDMACH_CC_MBSIZE(n) ((uint32_t)(n) << XDMACH_CC_MBSIZE_SHIFT) /* n=0-3 */ + # define XDMACH_CC_MBSIZE_1 (0 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to one */ # define XDMACH_CC_MBSIZE_4 (1 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to four */ # define XDMACH_CC_MBSIZE_8 (2 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to eight */ # define XDMACH_CC_MBSIZE_16 (3 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to sixteen */ + #define XDMACH_CC_DSYNC (1 << 4) /* Bit 4: Channel Synchronization */ #define XDMACH_CC_PROT (1 << 5) /* Bit 5: Channel Protection */ #define XDMACH_CC_SWREQ (1 << 6) /* Bit 6: Channel Software Request Trigger */ @@ -286,11 +295,13 @@ # define XDMACH_CC_CSIZE_4 (2 << XDMACH_CC_CSIZE_SHIFT) /* 4 data transferred */ # define XDMACH_CC_CSIZE_8 (3 << XDMACH_CC_CSIZE_SHIFT) /* 8 data transferred */ # define XDMACH_CC_CSIZE_16 (4 << XDMACH_CC_CSIZE_SHIFT) /* 16 data transferred */ + #define XDMACH_CC_DWIDTH_SHIFT (11) /* Bits 11-12: Channel Data Width */ #define XDMACH_CC_DWIDTH_MASK (3 << XDMACH_CC_DWIDTH_SHIFT) # define XDMACH_CC_DWIDTH_BYTE (0 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 8 bits */ # define XDMACH_CC_DWIDTH_HWORD (1 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 16 bits */ # define XDMACH_CC_DWIDTH_WORD (2 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 32 bits */ + #define XDMACH_CC_SIF (1 << 13) /* Bit 13: Channel Source Interface Identifier */ #define XDMACH_CC_DIF (1 << 14) /* Bit 14: Channel Destination Interface Identifier */ #define XDMACH_CC_SAM_SHIFT (16) /* Bits 16-17: Channel Source Addressing Mode */ @@ -299,12 +310,14 @@ # define XDMACH_CC_SAM_INCR (1 << XDMACH_CC_SAM_SHIFT) /* Address is incremented */ # define XDMACH_CC_SAM_UBS (2 << XDMACH_CC_SAM_SHIFT) /* Microblock stride is added */ # define XDMACH_CC_SAM_UBSDS (3 << XDMACH_CC_SAM_SHIFT) /* Microblock stride and data stride is added */ + #define XDMACH_CC_DAM_SHIFT (18) /* Bits 18-19: Channel Destination Addressing Mode */ #define XDMACH_CC_DAM_MASK (3 << XDMACH_CC_DAM_SHIFT) # define XDMACH_CC_DAM_FIXED (0 << XDMACH_CC_DAM_SHIFT) /* The address remains unchanged */ # define XDMACH_CC_DAM_INCR (1 << XDMACH_CC_DAM_SHIFT) /* Address is incremented */ # define XDMACH_CC_DAM_UBS (2 << XDMACH_CC_DAM_SHIFT) /* Microblock stride is added */ # define XDMACH_CC_DAM_UBSDS (3 << XDMACH_CC_DAM_SHIFT) /* Microblock stride and data stride is added */ + #define XDMACH_CC_INITD (1 << 21) /* Bit 21: Channel Initialization Terminated */ #define XDMACH_CC_RDIP (1 << 22) /* Bit 22: Read in Progress */ #define XDMACH_CC_WRIP (1 << 23) /* Bit 23: Write in Progress */ @@ -329,7 +342,7 @@ #define XDMACH_CDUS_DUBS_MASK (0x00ffffff) /* Bits 0-23: Channel Destination Microblock Stride */ -/* XDMA Channel Definitions *************************************************************/ +/* XDMA Channel Definitions *************************************************/ #define XDMACH_HSMCI 0 #define XDMACH_SPI0_TX 1 @@ -375,7 +388,7 @@ #define XDMACH_TC2_RX 42 #define XDMACH_TC3_RX 43 -/* Descriptor structure member definitions **********************************************/ +/* Descriptor structure member definitions **********************************/ /* Next Descriptor Address (32-bit address) */ @@ -395,18 +408,22 @@ # define CHNEXT_UBC_NVIEW_3 (3 << CHNEXT_UBC_NVIEW_SHIFT) /* Next Descriptor View 3 */ /* Source Address (32-bit address) */ + /* Destination Address (32-bit address) */ /* Configuration Register */ + /* Block Control */ /* Data Stride (32-bit value) */ + /* Source Microblock Stride (32-bit value) */ + /* Destination Microblock Stride (32-bit value) */ -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ struct chnext_view0_s { diff --git a/arch/arm/src/samv7/hardware/same70_memorymap.h b/arch/arm/src/samv7/hardware/same70_memorymap.h index f30a3a6b2ab..03d5057031e 100644 --- a/arch/arm/src/samv7/hardware/same70_memorymap.h +++ b/arch/arm/src/samv7/hardware/same70_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/same70_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_MEMORYMAP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ /* Address regions */ @@ -50,11 +50,13 @@ #define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */ #define SAM_INTROM_BASE 0x00800000 /* 0x00800000-0x00bfffff: Internal ROM */ /* 0x00c00000-0x1fffffff: Reserved */ + /* Internal SRAM memory region */ #define SAM_DTCM_BASE 0x20000000 /* 0x20000000-0x203fffff: DTCM */ #define SAM_SRAM_BASE 0x20400000 /* 0x20400000-0x20bfffff: SRAM */ /* 0x20c00000-0x3fffffff: Reserved */ + /* Peripherals address region */ #define SAM_HSMCI0_BASE 0x40000000 /* 0x40000000-0x40003fff: High Speed Multimedia Card Interface */ @@ -134,6 +136,7 @@ #define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */ #define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */ /* 0x400e2000-0x5fffffff: Reserved */ + /* External RAM memory region */ #define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x7fffffff: EBI Chip selects */ @@ -153,15 +156,15 @@ #define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ #define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -172,9 +175,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samv7/hardware/same70_pinmap.h b/arch/arm/src/samv7/hardware/same70_pinmap.h index a2be636bfa6..116329cd924 100644 --- a/arch/arm/src/samv7/hardware/same70_pinmap.h +++ b/arch/arm/src/samv7/hardware/same70_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/same70_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_PINMAP_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ -/* GPIO pin definitions *************************************************************/ /* Alternate Pin Functions * * These are mostly for reference and are not in pin configuration. @@ -115,21 +116,21 @@ /* Peripheral Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the UART1 TX output PCK0 on PA4, then the following definition - * should appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if we wanted the UART1 TX output PCK0 on PA4, then the following + * definition should appear in the board.h header file for that board: * * #define GPIO_UART1_TXD GPIO_UART1_TXD_1 * * The driver will then automatically configure PA6 as the PCK0 pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* Analog Front End (AFE) */ @@ -519,19 +520,19 @@ #define GPIO_USART2_SCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN17) #define GPIO_USART2_TXD (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN16) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -542,9 +543,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samv7/hardware/samv71_memorymap.h b/arch/arm/src/samv7/hardware/samv71_memorymap.h index 613f0e713dd..cb75d154cb8 100644 --- a/arch/arm/src/samv7/hardware/samv71_memorymap.h +++ b/arch/arm/src/samv7/hardware/samv71_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/samv71_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_MEMORYMAP_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_MEMORYMAP_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ /* Address regions */ @@ -50,11 +50,13 @@ #define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */ #define SAM_INTROM_BASE 0x00800000 /* 0x00800000-0x00bfffff: Internal ROM */ /* 0x00c00000-0x1fffffff: Reserved */ + /* Internal SRAM memory region */ #define SAM_DTCM_BASE 0x20000000 /* 0x20000000-0x203fffff: DTCM */ #define SAM_SRAM_BASE 0x20400000 /* 0x20400000-0x20bfffff: SRAM */ /* 0x20c00000-0x3fffffff: Reserved */ + /* Peripherals address region */ #define SAM_HSMCI0_BASE 0x40000000 /* 0x40000000-0x40003fff: High Speed Multimedia Card Interface */ @@ -134,6 +136,7 @@ #define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */ #define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */ /* 0x400e2000-0x5fffffff: Reserved */ + /* External RAM memory region */ #define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x7fffffff: EBI Chip selects */ @@ -153,15 +156,15 @@ #define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */ #define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */ -/************************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -172,9 +175,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samv7/hardware/samv71_pinmap.h b/arch/arm/src/samv7/hardware/samv71_pinmap.h index edbb87bb64a..bbfbfceee24 100644 --- a/arch/arm/src/samv7/hardware/samv71_pinmap.h +++ b/arch/arm/src/samv7/hardware/samv71_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/hardware/samv71_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_PINMAP_H #define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "sam_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* GPIO pin definitions *****************************************************/ -/* GPIO pin definitions *************************************************************/ /* Alternate Pin Functions * * These are mostly for reference and are not in pin configuration. @@ -115,21 +116,21 @@ /* Peripheral Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if we - * wanted the UART1 TX output PCK0 on PA4, then the following definition - * should appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if we wanted the UART1 TX output PCK0 on PA4, then the following + * definition should appear in the board.h header file for that board: * * #define GPIO_UART1_TXD GPIO_UART1_TXD_1 * * The driver will then automatically configure PA6 as the PCK0 pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ /* Analog Front End (AFE) */ @@ -525,19 +526,19 @@ #define GPIO_USART2_SCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN17) #define GPIO_USART2_TXD (GPIO_PERIPHB | GPIO_CFG_DEFAULT | GPIO_PORT_PIOD | GPIO_PIN16) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -548,9 +549,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samv7/sam_allocateheap.c b/arch/arm/src/samv7/sam_allocateheap.c index 25068f9686e..9dc861a3f4e 100644 --- a/arch/arm/src/samv7/sam_allocateheap.c +++ b/arch/arm/src/samv7/sam_allocateheap.c @@ -179,7 +179,8 @@ * * Kernel .data region. Size determined at link time. * Kernel .bss region Size determined at link time. - * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Kernel IDLE thread stack. Size determined by + * CONFIG_IDLETHREAD_STACKSIZE. * Padding for alignment * User .data region. Size determined at link time. * User .bss region Size determined at link time. @@ -196,7 +197,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; int log2; @@ -221,7 +223,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - sam_mpu_uheap((uintptr_t)ubase, usize); + sam_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -250,7 +252,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = CONFIG_RAM_END - ubase; int log2; diff --git a/arch/arm/src/samv7/sam_clockconfig.c b/arch/arm/src/samv7/sam_clockconfig.c index a19ab54a170..ac50a493274 100644 --- a/arch/arm/src/samv7/sam_clockconfig.c +++ b/arch/arm/src/samv7/sam_clockconfig.c @@ -44,7 +44,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Board Settings **********************************************************/ + +/* Board Settings ***********************************************************/ + /* PMC register settings based on the board configuration values defined * in board.h */ @@ -128,7 +130,8 @@ static inline void sam_supcsetup(void) putreg32((SUPC_CR_XTALSEL | SUPR_CR_KEY), SAM_SUPC_CR); for (delay = 0; - (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX; + (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && + delay < UINT32_MAX; delay++); } #endif @@ -169,10 +172,10 @@ static inline void sam_pmcsetup(void) { /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to * enable the main oscillator, the MOSCXTS bit in the Power Management - * Controller Status Register (PMC_SR) is cleared and the counter starts - * counting down on the slow clock divided by 8 from the MOSCXTCNT - * value. ... When the counter reaches 0, the MOSCXTS bit is set, - * indicating that the main clock is valid." + * Controller Status Register (PMC_SR) is cleared and the counter + * starts counting down on the slow clock divided by 8 from the + * MOSCXTCNT value. ... When the counter reaches 0, the MOSCXTS bit + * is set, indicating that the main clock is valid." */ putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR); @@ -182,9 +185,9 @@ static inline void sam_pmcsetup(void) /* "Switch to the main oscillator. The selection is made by writing the * MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of * the Main Clock source is glitch free, so there is no need to run out - * of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS - * bit of the power Management Controller Status Register (PMC_SR) allows - * knowing when the switch sequence is done." + * of SLCK, PLLACK or UPLLCK in order to change the selection. The + * MOSCSELS bit of the power Management Controller Status Register + * (PMC_SR) allows knowing when the switch sequence is done." * * MOSCSELS: Main Oscillator Selection Status * 0 = Selection is done @@ -195,12 +198,12 @@ static inline void sam_pmcsetup(void) sam_pmcwait(PMC_INT_MOSCSELS); /* "Select the master clock. "The Master Clock selection is made by writing - * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). - * The prescaler supports the division by a power of 2 of the selected clock - * between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs - * the prescaler. Each time PMC_MCKR is written to define a new Master Clock, - * the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is - * established. + * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock + * Register). The prescaler supports the division by a power of 2 of the + * selected clock between 1 and 64, and the division by 3. The PRES field + * in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to + * define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. + * It reads 0 until the Master Clock is established. */ regval = getreg32(SAM_PMC_MCKR); @@ -215,7 +218,9 @@ static inline void sam_pmcsetup(void) sam_pmcwait(PMC_INT_LOCKA); #ifdef CONFIG_SAMV7_USBDEVHS - /* UTMI configuration: Enable port0, select 12/16 MHz MAINOSC crystal source */ + /* UTMI configuration: + * Enable port0, select 12/16 MHz MAINOSC crystal source + */ #if BOARD_MAINOSC_FREQUENCY == 12000000 putreg32(UTMI_CKTRIM_FREQ_XTAL12, SAM_UTMI_CKTRIM); diff --git a/arch/arm/src/samv7/sam_clockconfig.h b/arch/arm/src/samv7/sam_clockconfig.h index c41549ecb70..7e24f2d4a32 100644 --- a/arch/arm/src/samv7/sam_clockconfig.h +++ b/arch/arm/src/samv7/sam_clockconfig.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_clockconfig.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,34 +16,34 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_CLOCKCONFIG_H #define __ARCH_ARM_SRC_SAMV7_SAM_CLOCKCONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -54,19 +54,20 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_clockconfig * * Description: - * Called to initialize the SAMV7. This does whatever setup is needed to put the - * SoC in a usable state. This includes the initialization of clocking using the - * settings in board.h. + * Called to initialize the SAMV7. + * This does whatever setup is needed to put the SoC in a usable state. + * This includes the initialization of clocking using the settings in + * board.h. * - ************************************************************************************/ + ****************************************************************************/ void sam_clockconfig(void); diff --git a/arch/arm/src/samv7/sam_config.h b/arch/arm/src/samv7/sam_config.h index dfcf782f332..0a69f35e57e 100644 --- a/arch/arm/src/samv7/sam_config.h +++ b/arch/arm/src/samv7/sam_config.h @@ -33,6 +33,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* GPIO IRQs ****************************************************************/ #ifndef CONFIG_SAMV7_GPIO_IRQ @@ -60,6 +61,7 @@ #endif /* UARTs ********************************************************************/ + /* Don't enable UARTs not supported by the chip. */ #if SAMV7_NUART < 1 @@ -94,6 +96,7 @@ #endif /* USARTs *******************************************************************/ + /* If the USART is not being used as a UART or for SPI, then it really isn't * enabled for our purposes. */ @@ -142,6 +145,7 @@ #endif /* UART Flow Control ********************************************************/ + /* UARTs do not support flow control */ #undef CONFIG_UART0_IFLOWCONTROL @@ -161,6 +165,7 @@ #endif /* Serial Console ***********************************************************/ + /* Is there a serial console? There should be no more than one defined. It * could be on any UARTn, n=1,..,SAMV7_NUART, or USARTn, n=1,.., SAMV7_NUSART */ @@ -249,7 +254,8 @@ # undef CONFIG_USART2_SERIAL_CONSOLE #endif -/* SPI ******************************************************************************/ +/* SPI **********************************************************************/ + /* Don't enable SPI peripherals not supported by the chip. */ #if SAMV7_NSPI < 1 @@ -321,7 +327,7 @@ ****************************************************************************/ /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #endif /* __ARCH_ARM_SRC_SAMV7_SAMV7_CONFIG_H */ diff --git a/arch/arm/src/samv7/sam_dac.c b/arch/arm/src/samv7/sam_dac.c index ba1530b7b8a..15ab4f7799e 100644 --- a/arch/arm/src/samv7/sam_dac.c +++ b/arch/arm/src/samv7/sam_dac.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_dac.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Included Files @@ -63,7 +63,9 @@ * Private Types ****************************************************************************/ -/* This structure represents the internal state of a single SAMV7 DAC module */ +/* This structure represents the internal state of a single SAMV7 DAC + * module + */ struct sam_dac_s { @@ -134,7 +136,9 @@ static struct sam_chan_s g_dac1priv = .dro = SAM_DACC_CDR0, #ifdef CONFIG_SAMV7_DAC_TRIGGER .reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL0_MASK, - .reg_dacc_trigr_set = DACC_TRIGR_TRGSEL0(CONFIG_SAMV7_DAC_TRIGGER_SELECT) | DACC_TRIGR_TRGEN0, + .reg_dacc_trigr_set = DACC_TRIGR_TRGSEL0( + CONFIG_SAMV7_DAC_TRIGGER_SELECT) | + DACC_TRIGR_TRGEN0, #endif }; @@ -152,7 +156,9 @@ static struct sam_chan_s g_dac2priv = .dro = SAM_DACC_CDR1, #ifdef CONFIG_SAMV7_DAC_TRIGGER .reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL1_MASK, - .reg_dacc_trigr_set = DACC_TRIGR_TRGSEL1(CONFIG_SAMV7_DAC_TRIGGER_SELECT) | DACC_TRIGR_TRGEN1, + .reg_dacc_trigr_set = DACC_TRIGR_TRGSEL1( + CONFIG_SAMV7_DAC_TRIGGER_SELECT) | + DACC_TRIGR_TRGEN1, #endif }; @@ -237,8 +243,8 @@ static void dac_reset(FAR struct dac_dev_s *dev) * Description: * Configure the DAC. This method is called the first time that the DAC * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching DAC interrupts. Interrupts - * are all disabled upon return. + * This setup includes configuring and attaching DAC interrupts. + * Interrupts are all disabled upon return. * * Input Parameters: * @@ -365,9 +371,9 @@ static int dac_timer_init(struct sam_dac_s *priv, uint32_t freq_required, DEBUGASSERT(priv && (freq_required > 0) && (channel >= 0 && channel <= 2)); /* Set the timer/counter waveform mode the clock input. Use smallest - * MCK divisor of 8 to have highest clock resolution thus smallest frequency - * error. With 32 bit counter the lowest possible frequency of 1 Hz is easily - * supported. + * MCK divisor of 8 to have highest clock resolution thus smallest + * frequency error. With 32 bit counter the lowest possible frequency of + * 1 Hz is easily supported. */ /* TODO Add support for TC_CMR_TCCLKS_PCK6 to reduce frequency error */ @@ -383,7 +389,8 @@ static int dac_timer_init(struct sam_dac_s *priv, uint32_t freq_required, priv->tc = sam_tc_allocate(channel, mode); if (!priv->tc) { - aerr("ERROR: Failed to allocate channel %d mode %08x\n", channel, mode); + aerr("ERROR: Failed to allocate channel %d mode %08x\n", + channel, mode); return -EINVAL; } @@ -618,7 +625,8 @@ FAR struct dac_dev_s *sam_dac_initialize(int intf) ret = dac_module_init(); if (ret < 0) { - aerr("ERROR: Failed to initialize the DAC peripheral module: %d\n", ret); + aerr("ERROR: Failed to initialize the DAC peripheral module: %d\n", + ret); return NULL; } diff --git a/arch/arm/src/samv7/sam_dac.h b/arch/arm/src/samv7/sam_dac.h index 2ed618c2e6c..cafc5ffe07a 100644 --- a/arch/arm/src/samv7/sam_dac.h +++ b/arch/arm/src/samv7/sam_dac.h @@ -34,8 +34,9 @@ /**************************************************************************** * Pre-processor definitions ****************************************************************************/ -/* Default configuration settings may be overridden in the board configuration - * file. + +/* Default configuration settings may be overridden in the board + * configuration file. */ #if !defined(CONFIG_SAMV7_DAC_DMA_BUFFER_SIZE) diff --git a/arch/arm/src/samv7/sam_ethernet.h b/arch/arm/src/samv7/sam_ethernet.h index 9c55ac8fa45..29c7b6efd7a 100644 --- a/arch/arm/src/samv7/sam_ethernet.h +++ b/arch/arm/src/samv7/sam_ethernet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_ethernet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_ETHERNET_H #define __ARCH_ARM_SRC_SAMV7_SAM_ETHERNET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_emac.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Understood PHY types */ #define SAMV7_PHY_DM9161 0 @@ -150,9 +151,9 @@ # endif #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -220,15 +221,16 @@ int sam_emac_initialize(int intf); int sam_emac_setmacaddr(int intf, uint8_t mac[6]); #endif -/************************************************************************************ +/**************************************************************************** * Function: sam_phy_boardinitialize * * Description: - * Some boards require specialized initialization of the PHY before it can be used. - * This may include such things as configuring GPIOs, resetting the PHY, etc. If - * CONFIG_SAMV7_PHYINIT is defined in the configuration then the board specific - * logic must provide sam_phyinitialize(); The SAMV7 Ethernet driver will call - * this function one time before it first uses the PHY. + * Some boards require specialized initialization of the PHY before it can + * be used. This may include such things as configuring GPIOs, resetting + * the PHY, etc. If CONFIG_SAMV7_PHYINIT is defined in the configuration + * then the board specific logic must provide sam_phyinitialize(); + * The SAMV7 Ethernet driver will call this function one time before it + * first uses the PHY. * * Input Parameters: * intf - Always zero for now. @@ -238,7 +240,7 @@ int sam_emac_setmacaddr(int intf, uint8_t mac[6]); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMV7_PHYINIT int sam_phy_boardinitialize(int intf); diff --git a/arch/arm/src/samv7/sam_freerun.c b/arch/arm/src/samv7/sam_freerun.c index 9c27d9d2457..d21250bb951 100644 --- a/arch/arm/src/samv7/sam_freerun.c +++ b/arch/arm/src/samv7/sam_freerun.c @@ -67,7 +67,7 @@ * Private Functions ****************************************************************************/ - /**************************************************************************** +/**************************************************************************** * Name: sam_freerun_handler * * Description: @@ -229,8 +229,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) DEBUGASSERT(freerun && freerun->tch && ts); - /* Temporarily disable the overflow counter. NOTE that we have to be careful - * here because sam_tc_getpending() will reset the pending interrupt status. + /* Temporarily disable the overflow counter. + * NOTE that we have to be careful here because sam_tc_getpending() + * will reset the pending interrupt status. * If we do not handle the overflow here then, it will be lost. */ diff --git a/arch/arm/src/samv7/sam_gpio.c b/arch/arm/src/samv7/sam_gpio.c index 11895ba2cdc..cf762020e00 100644 --- a/arch/arm/src/samv7/sam_gpio.c +++ b/arch/arm/src/samv7/sam_gpio.c @@ -113,6 +113,7 @@ const uintptr_t g_portbase[SAMV7_NPIO] = /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /**************************************************************************** * Name: sam_configinput * @@ -577,13 +578,14 @@ bool sam_gpioread(gpio_pinset_t pinset) return (regval & pin) != 0; } -/************************************************************************************ +/**************************************************************************** * Function: sam_dumpgpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpgpio(uint32_t pinset, const char *msg) @@ -604,37 +606,57 @@ int sam_dumpgpio(uint32_t pinset, const char *msg) gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n", - getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET), - getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET)); + getreg32(base + SAM_PIO_PSR_OFFSET), + getreg32(base + SAM_PIO_OSR_OFFSET), + getreg32(base + SAM_PIO_IFSR_OFFSET), + getreg32(base + SAM_PIO_ODSR_OFFSET)); gpioinfo(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n", - getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET), - getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET)); + getreg32(base + SAM_PIO_PDSR_OFFSET), + getreg32(base + SAM_PIO_IMR_OFFSET), + getreg32(base + SAM_PIO_ISR_OFFSET), + getreg32(base + SAM_PIO_MDSR_OFFSET)); gpioinfo(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n", - getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET), - getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET)); + getreg32(base + SAM_PIO_ABCDSR1_OFFSET), + getreg32(base + SAM_PIO_ABCDSR2_OFFSET), + getreg32(base + SAM_PIO_IFSCSR_OFFSET), + getreg32(base + SAM_PIO_PPDSR_OFFSET)); gpioinfo(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n", - getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET), - getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET)); + getreg32(base + SAM_PIO_PUSR_OFFSET), + getreg32(base + SAM_PIO_SCDR_OFFSET), + getreg32(base + SAM_PIO_OWSR_OFFSET), + getreg32(base + SAM_PIO_AIMMR_OFFSET)); gpioinfo(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n", - getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET), - getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET)); + getreg32(base + SAM_PIO_ESR_OFFSET), + getreg32(base + SAM_PIO_LSR_OFFSET), + getreg32(base + SAM_PIO_ELSR_OFFSET), + getreg32(base + SAM_PIO_FELLSR_OFFSET)); gpioinfo(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n", - getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET), - getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET)); + getreg32(base + SAM_PIO_FRLHSR_OFFSET), + getreg32(base + SAM_PIO_LOCKSR_OFFSET), + getreg32(base + SAM_PIO_WPMR_OFFSET), + getreg32(base + SAM_PIO_WPSR_OFFSET)); gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n", - getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET), - getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET)); + getreg32(base + SAM_PIO_PCMR_OFFSET), + getreg32(base + SAM_PIO_PCIMR_OFFSET), + getreg32(base + SAM_PIO_PCISR_OFFSET), + getreg32(base + SAM_PIO_PCRHR_OFFSET)); gpioinfo("SCHMITT: %08x DRIVER:%08x\n", - getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER_OFFSET)); + getreg32(base + SAM_PIO_SCHMITT_OFFSET), + getreg32(base + SAM_PIO_DRIVER_OFFSET)); gpioinfo(" KER: %08x KRCR: %08x KDR: %08x KIMR: %08x\n", - getreg32(base + SAM_PIO_KER_OFFSET), getreg32(base + SAM_PIO_KRCR_OFFSET), - getreg32(base + SAM_PIO_KDR_OFFSET), getreg32(base + SAM_PIO_KIMR_OFFSET)); + getreg32(base + SAM_PIO_KER_OFFSET), + getreg32(base + SAM_PIO_KRCR_OFFSET), + getreg32(base + SAM_PIO_KDR_OFFSET), + getreg32(base + SAM_PIO_KIMR_OFFSET)); gpioinfo(" KSR: %08x KKPR: %08x KKRR: %08x\n", - getreg32(base + SAM_PIO_KSR_OFFSET), getreg32(base + SAM_PIO_KKPR_OFFSET), + getreg32(base + SAM_PIO_KSR_OFFSET), + getreg32(base + SAM_PIO_KKPR_OFFSET), getreg32(base + SAM_PIO_KKRR_OFFSET)); gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n", - getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET), - getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET)); + getreg32(base + SAM_PIO_PCMR_OFFSET), + getreg32(base + SAM_PIO_PCIMR_OFFSET), + getreg32(base + SAM_PIO_PCISR_OFFSET), + getreg32(base + SAM_PIO_PCRHR_OFFSET)); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/samv7/sam_gpio.h b/arch/arm/src/samv7/sam_gpio.h index a4d14fd7dc9..3da6508b8ff 100644 --- a/arch/arm/src/samv7/sam_gpio.h +++ b/arch/arm/src/samv7/sam_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_GPIO_H #define __ARCH_ARM_SRC_SAMV7_SAM_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,11 +33,11 @@ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Bit-encoded input to sam_configgpio() ********************************************/ +/* Bit-encoded input to sam_configgpio() ************************************/ /* 32-bit Encoding: * @@ -93,7 +93,8 @@ # define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL) # define GPIO_INT_BOTHEDGES (0) -/* If the pin is an GPIO output, then this identifies the initial output value: +/* If the pin is an GPIO output, then this identifies the initial output + * value: * * .... .... .... .... ...V .... .... .... */ @@ -101,14 +102,15 @@ #define GPIO_OUTPUT_SET (1 << 12) /* Bit 12: Initial value of output */ #define GPIO_OUTPUT_CLEAR (0) -/* If the pin is an GPIO output, then this identifies the output drive strength: +/* If the pin is an GPIO output, then this identifies the output drive + * strength: * * .... .... .... .... .... D... .... .... */ #define GPIO_OUTPUT_DRIVE (1 << 11) /* Bit 11: Initial value of output */ # define GPIO_OUTPUT_HIGH_DRIVE (1 << 11) - #define GPIO_OUTPUT_LOW_DRIVE (0) +# define GPIO_OUTPUT_LOW_DRIVE (0) /* This identifies the GPIO port: * @@ -163,9 +165,9 @@ #define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) #define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -173,9 +175,9 @@ typedef uint32_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -188,9 +190,9 @@ extern "C" EXTERN const uintptr_t g_portbase[SAMV7_NPIO]; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_gpio_base @@ -203,7 +205,7 @@ EXTERN const uintptr_t g_portbase[SAMV7_NPIO]; static inline uintptr_t sam_gpio_base(gpio_pinset_t cfgset) { int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - DEBUGASSERT(port > GPIO_PIN_SHIFT); } -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Function: sam_gpioinit * * Description: @@ -259,7 +261,7 @@ static inline int sam_gpio_pinmask(gpio_pinset_t cfgset) * * Typically called from sam_start(). * - ************************************************************************************/ + ****************************************************************************/ #if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \ !defined(CONFIG_SAMV7_JTAG_FULL_ENABLE) @@ -268,13 +270,14 @@ void sam_gpioinit(void); # define sam_gpioinit() #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqinitialize * * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMV7_GPIO_IRQ void sam_gpioirqinitialize(void); @@ -282,43 +285,43 @@ void sam_gpioirqinitialize(void); # define sam_gpioirqinitialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int sam_configgpio(gpio_pinset_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: sam_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void sam_gpiowrite(gpio_pinset_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioread * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool sam_gpioread(gpio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirq * * Description: * Configure an interrupt for the specified GPIO pin. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMV7_GPIO_IRQ void sam_gpioirq(gpio_pinset_t pinset); @@ -326,13 +329,13 @@ void sam_gpioirq(gpio_pinset_t pinset); # define sam_gpioirq(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqenable * * Description: * Enable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMV7_GPIO_IRQ void sam_gpioirqenable(int irq); @@ -340,13 +343,13 @@ void sam_gpioirqenable(int irq); # define sam_gpioirqenable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqdisable * * Description: * Disable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SAMV7_GPIO_IRQ void sam_gpioirqdisable(int irq); @@ -354,13 +357,14 @@ void sam_gpioirqdisable(int irq); # define sam_gpioirqdisable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Function: sam_dumpgpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpgpio(uint32_t pinset, const char *msg); diff --git a/arch/arm/src/samv7/sam_gpioirq.c b/arch/arm/src/samv7/sam_gpioirq.c index c484bd51e4e..67f8189b2fd 100644 --- a/arch/arm/src/samv7/sam_gpioirq.c +++ b/arch/arm/src/samv7/sam_gpioirq.c @@ -108,6 +108,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAMV7_GPIOB_IRQ if (irq <= SAM_IRQ_PB31) { @@ -116,6 +117,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAMV7_GPIOC_IRQ if (irq <= SAM_IRQ_PC31) { @@ -124,6 +126,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAMV7_GPIOD_IRQ if (irq <= SAM_IRQ_PD31) { @@ -132,6 +135,7 @@ static int sam_irqbase(int irq, uint32_t *base, int *pin) return OK; } #endif + #ifdef CONFIG_SAMV7_GPIOE_IRQ if (irq <= SAM_IRQ_PE31) { @@ -159,7 +163,8 @@ static int sam_gpiointerrupt(uint32_t base, int irq0, void *context) uint32_t bit; int irq; - pending = getreg32(base + SAM_PIO_ISR_OFFSET) & getreg32(base + SAM_PIO_IMR_OFFSET); + pending = getreg32(base + SAM_PIO_ISR_OFFSET) & + getreg32(base + SAM_PIO_IMR_OFFSET); for (bit = 1, irq = irq0; pending != 0; bit <<= 1, irq++) { if ((pending & bit) != 0) @@ -173,6 +178,7 @@ static int sam_gpiointerrupt(uint32_t base, int irq0, void *context) pending &= ~bit; } } + return OK; } @@ -317,13 +323,13 @@ void sam_gpioirqinitialize(void) #endif } -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirq * * Description: * Configure an interrupt for the specified GPIO pin. * - ************************************************************************************/ + ****************************************************************************/ void sam_gpioirq(gpio_pinset_t pinset) { @@ -360,7 +366,7 @@ void sam_gpioirq(gpio_pinset_t pinset) putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */ } } - else + else { /* No.. Disable additional interrupt mode */ @@ -368,13 +374,13 @@ void sam_gpioirq(gpio_pinset_t pinset) } } -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqenable * * Description: * Enable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void sam_gpioirqenable(int irq) { @@ -385,18 +391,19 @@ void sam_gpioirqenable(int irq) { /* Clear (all) pending interrupts and enable this pin interrupt */ - //(void)getreg32(base + SAM_PIO_ISR_OFFSET); + /* (void)getreg32(base + SAM_PIO_ISR_OFFSET); */ + putreg32((1 << pin), base + SAM_PIO_IER_OFFSET); } } -/************************************************************************************ +/**************************************************************************** * Name: sam_gpioirqdisable * * Description: * Disable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ void sam_gpioirqdisable(int irq) { diff --git a/arch/arm/src/samv7/sam_hsmci.h b/arch/arm/src/samv7/sam_hsmci.h index dd60bcf127f..a2b476f04e5 100644 --- a/arch/arm/src/samv7/sam_hsmci.h +++ b/arch/arm/src/samv7/sam_hsmci.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_hsmci.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,37 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_HSMCI_H #define __ARCH_ARM_SRC_SAMV7_SAM_HSMCI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -57,9 +57,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sdio_initialize @@ -71,7 +71,8 @@ extern "C" * slotno - Not used. * * Returned Value: - * A reference to an SDIO interface structure. NULL is returned on failures. + * A reference to an SDIO interface structure. + * NULL is returned on failures. * ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_lowputc.c b/arch/arm/src/samv7/sam_lowputc.c index 234fbfb0742..50d208ffa7e 100644 --- a/arch/arm/src/samv7/sam_lowputc.c +++ b/arch/arm/src/samv7/sam_lowputc.c @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Configuration **********************************************************/ +/* Configuration ************************************************************/ #ifdef HAVE_SERIAL_CONSOLE diff --git a/arch/arm/src/samv7/sam_lowputc.h b/arch/arm/src/samv7/sam_lowputc.h index 524734c688c..0849fbe67f1 100644 --- a/arch/arm/src/samv7/sam_lowputc.h +++ b/arch/arm/src/samv7/sam_lowputc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_lowputc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_LOWPUTC_H #define __ARCH_ARM_SRC_SAMV7_SAM_LOWPUTC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,23 +35,23 @@ #include "arm_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -62,31 +62,33 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. + * Called at the very beginning of _start. + * Performs low level initialization including setup of the console UART. + * This UART done early so that the serial console is available for + * debugging very early in the boot sequence. * - ************************************************************************************/ + ****************************************************************************/ void sam_lowsetup(void); -/************************************************************************************ +/**************************************************************************** * Name: sam_boardinitialize * * Description: - * All SAMV7 architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. + * All SAMV7 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * - ************************************************************************************/ + ****************************************************************************/ void sam_boardinitialize(void); diff --git a/arch/arm/src/samv7/sam_mcan.h b/arch/arm/src/samv7/sam_mcan.h index c2c56e26f99..6b7efcf47e4 100644 --- a/arch/arm/src/samv7/sam_mcan.h +++ b/arch/arm/src/samv7/sam_mcan.h @@ -64,7 +64,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/samv7/sam_oneshot.c b/arch/arm/src/samv7/sam_oneshot.c index b2313937790..b13c129eb51 100644 --- a/arch/arm/src/samv7/sam_oneshot.c +++ b/arch/arm/src/samv7/sam_oneshot.c @@ -245,7 +245,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); - *usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch); + *usec = (0xffffull * USEC_PER_SEC) / + (uint64_t)sam_tc_divfreq(oneshot->tch); return OK; } @@ -279,7 +280,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, irqstate_t flags; tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", - handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + handler, arg, (unsigned long)ts->tv_sec, + (unsigned long)ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); /* Was the oneshot already running? */ @@ -300,7 +302,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, /* Express the delay in microseconds */ - usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); + usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); /* Get the timer counter frequency and determine the number of counts * needed to achieve the requested delay. diff --git a/arch/arm/src/samv7/sam_oneshot_lowerhalf.c b/arch/arm/src/samv7/sam_oneshot_lowerhalf.c index c6544c594b6..ff8d2d60060 100644 --- a/arch/arm/src/samv7/sam_oneshot_lowerhalf.c +++ b/arch/arm/src/samv7/sam_oneshot_lowerhalf.c @@ -39,7 +39,9 @@ * Private Types ****************************************************************************/ -/* This structure describes the state of the oneshot timer lower-half driver */ +/* This structure describes the state of the oneshot timer lower-half + * driver + */ struct sam_oneshot_lowerhalf_s { diff --git a/arch/arm/src/samv7/sam_pck.c b/arch/arm/src/samv7/sam_pck.c index d8c3d27f60a..ed53dfa4c81 100644 --- a/arch/arm/src/samv7/sam_pck.c +++ b/arch/arm/src/samv7/sam_pck.c @@ -76,7 +76,7 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc, * MAINCK,or SCK are supported here. */ - switch (clksrc) + switch (clksrc) { case PCKSRC_MCK: /* Source clock = MCK or PLLACK */ { @@ -117,7 +117,9 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc, return 0; } - /* Programmable Clock frequency is selected clock frequency divided by PRES + 1 */ + /* Programmable Clock frequency is selected clock frequency divided by + * PRES + 1 + */ pres = clkin / frequency; if (pres < 1) @@ -320,7 +322,9 @@ bool sam_pck_isenabled(enum pckid_e pckid) { uint32_t mask; - /* Select the bit in the PMC_SCSR corresponding to the programmable clock. */ + /* Select the bit in the PMC_SCSR corresponding to the programmable + * clock. + */ mask = PMC_PCK(pckid); diff --git a/arch/arm/src/samv7/sam_pck.h b/arch/arm/src/samv7/sam_pck.h index fdd38ba5cfa..64aafb8bad9 100644 --- a/arch/arm/src/samv7/sam_pck.h +++ b/arch/arm/src/samv7/sam_pck.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_pck.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,27 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_PCK_H #define __ARCH_ARM_SRC_SAMV7_SAM_PCK_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ + /* Identifies the programmable clock */ enum pckid_e @@ -57,9 +58,9 @@ enum pckid_clksrc_e PCKSRC_SCK /* Source clock is the slow clock (SCK) */ }; -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ diff --git a/arch/arm/src/samv7/sam_periphclks.h b/arch/arm/src/samv7/sam_periphclks.h index 3650fa14f05..feb0afb3601 100644 --- a/arch/arm/src/samv7/sam_periphclks.h +++ b/arch/arm/src/samv7/sam_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAMV7_SAM_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -35,23 +35,23 @@ # error Unrecognized SAMV7 architecture #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -62,9 +62,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index 3489ecc9a03..a670f0bbc3d 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -41,6 +41,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_DEBUG_WATCHDOG_INFO @@ -73,6 +74,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * well-known watchdog_lowerhalf_s structure. @@ -92,6 +94,7 @@ struct sam_lowerhalf_s /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Register operations ******************************************************/ #ifdef CONFIG_SAMV7_RSWDT_REGDEBUG @@ -125,6 +128,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, /**************************************************************************** * Private Data ****************************************************************************/ + /* "Lower half" driver methods */ static const struct watchdog_ops_s g_wdgops = @@ -165,8 +169,8 @@ static uint32_t sam_getreg(uintptr_t regaddr) uint32_t regval = getreg32(regaddr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. */ if (regaddr == prevaddr && regval == preval) @@ -192,7 +196,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - wdinfo("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -272,8 +276,8 @@ static int sam_interrupt(int irq, FAR void *context, FAR void *arg) * Start the watchdog timer, resetting the time to the current timeout, * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -286,9 +290,10 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower) /* The watchdog timer is enabled or disabled by writing to the MR register. * - * NOTE: The Watchdog Mode Register (RSWDT_MR) can be written only once. Only - * a processor reset resets it. Writing the RSWDT_MR register reloads the - * timer with the newly programmed mode parameters. + * NOTE: + * The Watchdog Mode Register (RSWDT_MR) can be written only once. Only + * a processor reset resets it. Writing the RSWDT_MR register reloads + * the timer with the newly programmed mode parameters. */ wdinfo("Entry\n"); @@ -302,8 +307,8 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower) * Stop the watchdog timer * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -314,9 +319,10 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) { /* The watchdog timer is enabled or disabled by writing to the MR register. * - * NOTE: The Watchdog Mode Register (RSWDT_MR) can be written only once. Only - * a processor reset resets it. Writing the RSWDT_MR register reloads the - * timer with the newly programmed mode parameters. + * NOTE: + * The Watchdog Mode Register (RSWDT_MR) can be written only once. Only + * a processor reset resets it. Writing the RSWDT_MR register reloads + * the timer with the newly programmed mode parameters. */ wdinfo("Entry\n"); @@ -332,8 +338,8 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) * the atchdog timer or "petting the dog". * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -344,7 +350,8 @@ static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower) { wdinfo("Entry\n"); - /* Write RSWDT_CR_WDRSTT to the RSWDT CR register (along with the KEY value) + /* Write RSWDT_CR_WDRSTT to the RSWDT CR register + * (along with the KEY value) * will restart the watchdog timer. */ @@ -359,8 +366,8 @@ static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower) * Get the current watchdog timer status * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * stawtus - The location to return the watchdog status information. * * Returned Value: @@ -416,8 +423,8 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, * Set a new timeout value (and reset the watchdog timer) * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * timeout - The new timeout value in millisecnds. * * Returned Value: @@ -466,7 +473,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, * timeout = 1000 * (reload + 1) / Fwwdg */ - priv->timeout = (1000 * reload + RSWDT_FREQUENCY/2) / RSWDT_FREQUENCY; + priv->timeout = (1000 * reload + RSWDT_FREQUENCY / 2) / RSWDT_FREQUENCY; /* Remember the selected values */ @@ -477,9 +484,9 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, /* Set the RSWDT_MR according to calculated value * - * NOTE: The Watchdog Mode Register (RSWDT_MR) can be written only once. Only - * a processor reset resets it. Writing the RSWDT_MR register reloads the - * timer with the newly programmed mode parameters. + * NOTE: The Watchdog Mode Register (RSWDT_MR) can be written only once. + * Only a processor reset resets it. Writing the RSWDT_MR register + * reloads the timer with the newly programmed mode parameters. */ regval = WDT_MR_WDV(reload) | RSWDT_MR_WDD_ALLONES; @@ -533,8 +540,8 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, * behavior. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * newhandler - The new watchdog expiration function pointer. If this * function pointer is NULL, then the reset-on-expiration * behavior is restored, @@ -567,7 +574,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, /* Save the new handler */ - priv->handler = handler; + priv->handler = handler; /* Are we attaching or detaching the handler? */ @@ -597,8 +604,8 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, * are forwarded to the lower half driver through this method. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * cmd - The ioctol command value * arg - The optional argument that accompanies the 'cmd'. The * interpretation of this argument depends on the particular @@ -627,8 +634,8 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, * Name: sam_rswdt_initialize * * Description: - * Initialize the RSWDT watchdog time. The watchdog timer is initialized and - * registered as 'devpath. The initial state of the watchdog time is + * Initialize the RSWDT watchdog time. The watchdog timer is initialized + * and registered as 'devpath. The initial state of the watchdog time is * disabled. * * Input Parameters: diff --git a/arch/arm/src/samv7/sam_spi.h b/arch/arm/src/samv7/sam_spi.h index 85096d62eda..22374e2f2cf 100644 --- a/arch/arm/src/samv7/sam_spi.h +++ b/arch/arm/src/samv7/sam_spi.h @@ -197,16 +197,17 @@ FAR struct spi_sctrlr_s *sam_spi_slave_initialize(int port); * 1. Provide logic in sam_boardinitialize() to configure SPI chip select * pins. * 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in - * our board-specific logic. These functions will perform chip selection - * and status operations using PIOs in the way your board is configured. + * our board-specific logic. These functions will perform chip + * selection and status operations using PIOs in the way your board is + * configured. * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide * sam_spi[0|1]cmddata() functions in your board-specific logic. This * function will perform cmd/data selection operations using PIOs in * the way your board is configured. * 3. Add a call to sam_spibus_initialize() in your low level application * initialization logic - * 4. The handle returned by sam_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by sam_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * diff --git a/arch/arm/src/samv7/sam_ssc.h b/arch/arm/src/samv7/sam_ssc.h index d75e1139c2f..128ec90cb27 100644 --- a/arch/arm/src/samv7/sam_ssc.h +++ b/arch/arm/src/samv7/sam_ssc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_ssc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,37 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_SSC_H #define __ARCH_ARM_SRC_SAMV7_SAM_SSC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/sam_ssc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -57,9 +57,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_ssc_initialize diff --git a/arch/arm/src/samv7/sam_start.h b/arch/arm/src/samv7/sam_start.h index 4e564d3e9c1..4a7085d8d3a 100644 --- a/arch/arm/src/samv7/sam_start.h +++ b/arch/arm/src/samv7/sam_start.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_START_H #define __ARCH_ARM_SRC_SAMV7_SAM_START_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -46,32 +46,33 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. * - ************************************************************************************/ + ****************************************************************************/ void sam_lowsetup(void); -/************************************************************************************ +/**************************************************************************** * Name: sam_boardinitialize * * Description: - * All SAMV7 architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * All SAMV7 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. * - ************************************************************************************/ + ****************************************************************************/ void sam_boardinitialize(void); diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index b3f09371e3f..d2daac81343 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -562,7 +562,9 @@ static struct sam_tc_s g_tc678; static struct sam_tc_s g_tc901; #endif -/* TC frequency data. This table provides the frequency for each selection of TCCLK */ +/* TC frequency data. This table provides the frequency for each + * selection of TCCLK + */ #define TC_NDIVIDERS 3 #define TC_NDIVOPTIONS 4 diff --git a/arch/arm/src/samv7/sam_tc.h b/arch/arm/src/samv7/sam_tc.h index a63355b1a4a..52926b21695 100644 --- a/arch/arm/src/samv7/sam_tc.h +++ b/arch/arm/src/samv7/sam_tc.h @@ -71,6 +71,7 @@ /**************************************************************************** * Public Types ****************************************************************************/ + /* An opaque handle used to represent a timer channel */ typedef void *TC_HANDLE; diff --git a/arch/arm/src/samv7/sam_tickless.c b/arch/arm/src/samv7/sam_tickless.c index 0b2346cd97e..a47d3de8802 100644 --- a/arch/arm/src/samv7/sam_tickless.c +++ b/arch/arm/src/samv7/sam_tickless.c @@ -25,8 +25,8 @@ * is suppressed and the platform specific code is expected to provide the * following custom functions. * - * void up_timer_initialize(void): Initializes the timer facilities. Called - * early in the initialization sequence (by up_initialize()). + * void up_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_initialize()). * int up_timer_gettime(FAR struct timespec *ts): Returns the current * time from the platform specific time source. * int up_timer_cancel(void): Cancels the interval timer. @@ -40,6 +40,7 @@ * logic when the interval timer expires. * ****************************************************************************/ + /**************************************************************************** * SAMV7 Timer Usage * @@ -349,9 +350,10 @@ int up_timer_gettime(FAR struct timespec *ts) int up_timer_cancel(FAR struct timespec *ts) { - return ONESHOT_INITIALIZED(&g_tickless.oneshot) && FREERUN_INITIALIZED(&g_tickless.freerun) ? - sam_oneshot_cancel(&g_tickless.oneshot, &g_tickless.freerun, ts) : - -EAGAIN; + return ONESHOT_INITIALIZED(&g_tickless.oneshot) && + FREERUN_INITIALIZED(&g_tickless.freerun) ? + sam_oneshot_cancel(&g_tickless.oneshot, + &g_tickless.freerun, ts) : -EAGAIN; } /**************************************************************************** @@ -382,7 +384,7 @@ int up_timer_cancel(FAR struct timespec *ts) int up_timer_start(FAR const struct timespec *ts) { return ONESHOT_INITIALIZED(&g_tickless.oneshot) ? - sam_oneshot_start(&g_tickless.oneshot, &g_tickless.freerun, sam_oneshot_handler, NULL, ts) : - -EAGAIN; + sam_oneshot_start(&g_tickless.oneshot, + &g_tickless.freerun, sam_oneshot_handler, NULL, ts) : -EAGAIN; } #endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/samv7/sam_timerisr.c b/arch/arm/src/samv7/sam_timerisr.c index d7298889710..546f40a54d2 100644 --- a/arch/arm/src/samv7/sam_timerisr.c +++ b/arch/arm/src/samv7/sam_timerisr.c @@ -47,9 +47,9 @@ * prescaler output (i.e., the MDIV output divider is not applied so that * the driving frequency is the same as the CPU frequency). * - * The SysTick calibration value is fixed to 37500 which allows the generation - * of a time base of 1 ms with SysTick clock to the maximum frequency on - * MCK divided by 8. (?) + * The SysTick calibration value is fixed to 37500 which allows the + * generation of a time base of 1 ms with SysTick clock to the maximum + * frequency on MCK divided by 8. (?) */ #define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY diff --git a/arch/arm/src/samv7/sam_trng.h b/arch/arm/src/samv7/sam_trng.h index f392dcb2181..3b8df6471cb 100644 --- a/arch/arm/src/samv7/sam_trng.h +++ b/arch/arm/src/samv7/sam_trng.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #undef EXTERN diff --git a/arch/arm/src/samv7/sam_twihs.h b/arch/arm/src/samv7/sam_twihs.h index 8c91ac04559..a6bf3c51535 100644 --- a/arch/arm/src/samv7/sam_twihs.h +++ b/arch/arm/src/samv7/sam_twihs.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_twihs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_TWIHS_H #define __ARCH_ARM_SRC_SAMV7_SAM_TWIHS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include diff --git a/arch/arm/src/samv7/sam_usbdev.h b/arch/arm/src/samv7/sam_usbdev.h index 4250d5bddd5..15386181f05 100644 --- a/arch/arm/src/samv7/sam_usbdev.h +++ b/arch/arm/src/samv7/sam_usbdev.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_usbdev.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_USBDEV_H #define __ARCH_ARM_SRC_SAMV7_SAM_USBDEV_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -34,9 +34,9 @@ #include "hardware/sam_usbhs.h" -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -49,16 +49,17 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_usbsuspend * * Description: - * Board logic must provide the sam_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the sam_usbsuspend logic if the USBDEV driver + * is used. + * This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. * - ************************************************************************************/ + ****************************************************************************/ void sam_usbsuspend(FAR struct usbdev_s *dev, bool resume); diff --git a/arch/arm/src/samv7/sam_userspace.h b/arch/arm/src/samv7/sam_userspace.h index fe21d53cba2..c500e5265c5 100644 --- a/arch/arm/src/samv7/sam_userspace.h +++ b/arch/arm/src/samv7/sam_userspace.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_userspace.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_USERSPACE_H #define __ARCH_ARM_SRC_SAMV7_SAM_USERSPACE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,23 +35,23 @@ #include "arm_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -62,9 +62,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: sam_userspace diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index bd592fcfdcd..9898134a057 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -41,6 +41,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_DEBUG_WATCHDOG_INFO @@ -73,6 +74,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * well-known watchdog_lowerhalf_s structure. @@ -92,6 +94,7 @@ struct sam_lowerhalf_s /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Register operations ******************************************************/ #ifdef CONFIG_SAMV7_WDT_REGDEBUG @@ -125,6 +128,7 @@ static int sam_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, /**************************************************************************** * Private Data ****************************************************************************/ + /* "Lower half" driver methods */ static const struct watchdog_ops_s g_wdgops = @@ -165,8 +169,8 @@ static uint32_t sam_getreg(uintptr_t regaddr) uint32_t regval = getreg32(regaddr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. */ if (regaddr == prevaddr && regval == preval) @@ -192,7 +196,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - wdinfo("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ @@ -272,8 +276,8 @@ static int sam_interrupt(int irq, FAR void *context, FAR void *arg) * Start the watchdog timer, resetting the time to the current timeout, * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -286,7 +290,8 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower) /* The watchdog timer is enabled or disabled by writing to the MR register. * - * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only + * NOTE: + * The Watchdog Mode Register (WDT_MR) can be written only once. Only * a processor reset resets it. Writing the WDT_MR register reloads the * timer with the newly programmed mode parameters. */ @@ -302,8 +307,8 @@ static int sam_start(FAR struct watchdog_lowerhalf_s *lower) * Stop the watchdog timer * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -314,9 +319,9 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) { /* The watchdog timer is enabled or disabled by writing to the MR register. * - * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only - * a processor reset resets it. Writing the WDT_MR register reloads the - * timer with the newly programmed mode parameters. + * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. + * Only a processor reset resets it. Writing the WDT_MR register reloads + * the timer with the newly programmed mode parameters. */ wdinfo("Entry\n"); @@ -332,8 +337,8 @@ static int sam_stop(FAR struct watchdog_lowerhalf_s *lower) * the atchdog timer or "petting the dog". * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -359,8 +364,8 @@ static int sam_keepalive(FAR struct watchdog_lowerhalf_s *lower) * Get the current watchdog timer status * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * stawtus - The location to return the watchdog status information. * * Returned Value: @@ -416,8 +421,8 @@ static int sam_getstatus(FAR struct watchdog_lowerhalf_s *lower, * Set a new timeout value (and reset the watchdog timer) * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * timeout - The new timeout value in millisecnds. * * Returned Value: @@ -466,7 +471,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, * timeout = 1000 * (reload + 1) / Fwwdg */ - priv->timeout = (1000 * reload + WDT_FREQUENCY/2) / WDT_FREQUENCY; + priv->timeout = (1000 * reload + WDT_FREQUENCY / 2) / WDT_FREQUENCY; /* Remember the selected values */ @@ -477,22 +482,22 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, /* Set the WDT_MR according to calculated value * - * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. Only - * a processor reset resets it. Writing the WDT_MR register reloads the - * timer with the newly programmed mode parameters. + * NOTE: The Watchdog Mode Register (WDT_MR) can be written only once. + * Only a processor reset resets it. Writing the WDT_MR register + * reloads the timer with the newly programmed mode parameters. * - * NOTE: The WDD Value is the lower bound of a so called Forbidden Window - * (see Datasheet for further Information). To disable this Forbidden - * Window we have to set the WDD Value greater than or equal to WDV - * (according the Datasheet). + * NOTE: The WDD Value is the lower bound of a so called Forbidden + * Window (see Datasheet for further Information). To disable this + * Forbidden Window we have to set the WDD Value greater than or equal + * to WDV (according the Datasheet). * - * When setting the WDD Value equal to WDV we have to wait at least one clock - * pulse of the (very slow) watchdog clock source between two resets (or the - * configuration and the first reset) of the watchdog. + * When setting the WDD Value equal to WDV we have to wait at least one + * clock pulse of the (very slow) watchdog clock source between two resets + * (or the configuration and the first reset) of the watchdog. * - * On fast systems this can lead to a direct hit of the WDD boundary and - * thus to a reset of the system. This is why we program the WDD Value to - * WDT_MR_WDD_MAX to truly disable this Forbidden Window Feature. + * On fast systems this can lead to a direct hit of the WDD boundary + * and thus to a reset of the system. This is why we program the WDD + * Value to WDT_MR_WDD_MAX to truly disable this Forbidden Window Feature. */ regval = WDT_MR_WDV(reload) | WDT_MR_WDD(WDT_MR_WDD_MAX); @@ -546,8 +551,8 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, * behavior. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * newhandler - The new watchdog expiration function pointer. If this * function pointer is NULL, then the reset-on-expiration * behavior is restored, @@ -580,7 +585,7 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, /* Save the new handler */ - priv->handler = handler; + priv->handler = handler; /* Are we attaching or detaching the handler? */ @@ -610,8 +615,8 @@ static xcpt_t sam_capture(FAR struct watchdog_lowerhalf_s *lower, * are forwarded to the lower half driver through this method. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * cmd - The ioctol command value * arg - The optional argument that accompanies the 'cmd'. The * interpretation of this argument depends on the particular diff --git a/arch/arm/src/samv7/sam_wdt.h b/arch/arm/src/samv7/sam_wdt.h index 91f0e5e8831..676e4ad0c3e 100644 --- a/arch/arm/src/samv7/sam_wdt.h +++ b/arch/arm/src/samv7/sam_wdt.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/samv7/sam_xdmac.h b/arch/arm/src/samv7/sam_xdmac.h index 56c654f38fc..adccb3e32a7 100644 --- a/arch/arm/src/samv7/sam_xdmac.h +++ b/arch/arm/src/samv7/sam_xdmac.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/sam_xdmac.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAM_XDMAC_H #define __ARCH_ARM_SRC_SAMV7_SAM_XDMAC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,28 +31,31 @@ #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* DMA ******************************************************************************/ +/* DMA **********************************************************************/ -/* Flags used to characterize the DMA channel. The naming convention is that one - * side is the peripheral and the other is memory (however, the interface could still - * be used if, for example, both sides were memory although the naming would be - * awkward) +/* Flags used to characterize the DMA channel. + * The naming convention is that one side is the peripheral and the other is + * memory (however, the interface could still be used if, for example, both + * sides were memory although the naming would be awkward) * * Encoding: * * .... .... .... MMMM .PPP PPPP PPPP PPPP - * .... .... .... .... .... .... .... .... Configurable properties of the channel - * .... .... .... .... .PPP PPPP PPPP PPPP Peripheral endpoint characteristics + * .... .... .... .... .... .... .... .... Configurable properties of the + * channel + * .... .... .... .... .PPP PPPP PPPP PPPP Peripheral endpoint + * characteristics * .... .... .... MMMM .... .... .... .... Memory endpoint characteristics */ /* Bits 0-1: Configurable properties of the channel * - * .... .... .... .... .... .... .... .... Configurable properties of the channel + * .... .... .... .... .... .... .... .... Configurable properties of the + * channel * * NOTE: Many "peripheral" attributes are really "channel" attributes for * the samv7D4's XDMAC since it does not support peripheral-to-peripheral @@ -65,7 +68,8 @@ /* Bits 0-15: Peripheral endpoint characteristics * - * .... .... .... .... .PPP PPPP PPPP PPPP Peripheral endpoint characteristics + * .... .... .... .... .PPP PPPP PPPP PPPP Peripheral endpoint + * characteristics * .... .... .... .... .... .... .III IIII Peripheral ID, range 0-67 * .... .... .... .... .... .... .... .... No HW Handshaking * .... .... .... .... .... .... P... .... 0=memory; 1=peripheral @@ -92,6 +96,7 @@ # define DMACH_FLAG_PERIPHWIDTH_16BITS (1 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 16 bits */ # define DMACH_FLAG_PERIPHWIDTH_32BITS (2 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 32 bits */ # define DMACH_FLAG_PERIPHWIDTH_64BITS (3 << DMACH_FLAG_PERIPHWIDTH_SHIFT) /* 64 bits */ + #define DMACH_FLAG_PERIPHINCREMENT (1 << 11) /* Bit 11: Auto-increment peripheral address */ #define DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT (12) /* Bits 12-14: Peripheral chunk size */ #define DMACH_FLAG_PERIPHCHUNKSIZE_MASK (7 << DMACH_FLAG_PERIPHCHUNKSIZE_SHIFT) @@ -104,7 +109,8 @@ /* Bits 16-19: Memory endpoint characteristics * * .... .... .... MMMM .... .... .... .... Memory endpoint characteristics - * .... .... .... .... .... .... .... .... No memory peripheral ID, range 0-49 + * .... .... .... .... .... .... .... .... No memory peripheral ID, + * range 0-49 * .... .... .... .... .... .... .... .... No HW Handshaking * .... .... .... .... .... .... .... .... No peripheral-to-peripheral * .... .... .... ...N .... .... .... .... Memory ABH layer number @@ -142,14 +148,16 @@ # define DMACH_FLAG_MEMBURST_8 (2 << DMACH_FLAG_MEMBURST_SHIFT) # define DMACH_FLAG_MEMBURST_16 (3 << DMACH_FLAG_MEMBURST_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is + * selected + */ #ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s @@ -191,15 +199,15 @@ struct sam_dmaregs_s }; #endif /* CONFIG_DEBUG_DMA_INFO */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -210,116 +218,122 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_dmachannel * * Description: - * Allocate a DMA channel. This function sets aside a DMA channel then gives the - * caller exclusive access to the DMA channel. + * Allocate a DMA channel. This function sets aside a DMA channel then + * gives the caller exclusive access to the DMA channel. * - * The naming convention in all of the DMA interfaces is that one side is the - * 'peripheral' and the other is 'memory'. However, the interface could still - * be used if, for example, both sides were memory although the naming would be - * awkward. + * The naming convention in all of the DMA interfaces is that one side is + * the 'peripheral' and the other is 'memory'. However, the interface + * could still be used if, for example, both sides were memory although + * the naming would be awkward. * * Returned Value: - * If a DMA channel is available, this function returns a non-NULL, void* DMA - * channel handle. NULL is returned on any failure. + * If a DMA channel is available, this function returns a non-NULL, + * void* DMA channel handle. NULL is returned on any failure. * - ************************************************************************************/ + ****************************************************************************/ DMA_HANDLE sam_dmachannel(uint8_t dmacno, uint32_t chflags); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmaconfig * * Description: - * There are two channel usage models: (1) The channel is allocated and configured - * in one step. This is the typical case where a DMA channel performs a constant - * role. The alternative is (2) where the DMA channel is reconfigured on the fly. - * In this case, the chflags provided to sam_dmachannel are not used and - * sam_dmaconfig() is called before each DMA to configure the DMA channel - * appropriately. + * There are two channel usage models: (1) The channel is allocated and + * configured in one step. This is the typical case where a DMA channel + * performs a constant role. The alternative is (2) where the DMA channel + * is reconfigured on the fly. In this case, the chflags provided to + * sam_dmachannel are not used and sam_dmaconfig() is called before each + * DMA to configure the DMA channel appropriately. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_dmaconfig(DMA_HANDLE handle, uint32_t chflags); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmafree * * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must NEVER be - * used again until sam_dmachannel() is called again to re-gain a valid handle. + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again until + * sam_dmachannel() is called again to re-gain a valid handle. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void sam_dmafree(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmatxsetup * * Description: - * Configure DMA for transmit of one buffer (memory to peripheral). This function - * may be called multiple times to handle large and/or discontinuous transfers. - * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the - * same transfer, however. + * Configure DMA for transmit of one buffer (memory to peripheral). + * This function may be called multiple times to handle large and/or + * discontinuous transfers. + * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed + * on the same transfer, however. * - ************************************************************************************/ + ****************************************************************************/ -int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes); +int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, + uint32_t maddr, size_t nbytes); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmarxsetup * * Description: - * Configure DMA for receipt of one buffer (peripheral to memory). This function - * may be called multiple times to handle large and/or discontinuous transfers. - * Calls to sam_dmatxsetup() and sam_dmarxsetup() must not be intermixed on the - * same transfer, however. + * Configure DMA for receipt of one buffer (peripheral to memory). This + * function may be called multiple times to handle large and/or + * discontinuous transfers. Calls to sam_dmatxsetup() and sam_dmarxsetup() + * must not be intermixed on the same transfer, however. * - ************************************************************************************/ + ****************************************************************************/ -int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t nbytes); +int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, + uint32_t maddr, size_t nbytes); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmastart * * Description: * Start the DMA transfer * - ************************************************************************************/ + ****************************************************************************/ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmastop * * Description: - * Cancel the DMA. After sam_dmastop() is called, the DMA channel is reset and - * sam_dmarx/txsetup() must be called before sam_dmastart() can be called again + * Cancel the DMA. + * After sam_dmastop() is called, the DMA channel is reset and + * sam_dmarx/txsetup() must be called before sam_dmastart() can be + * called again * - ************************************************************************************/ + ****************************************************************************/ void sam_dmastop(DMA_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: sam_dmasample * * Description: * Sample DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); @@ -327,16 +341,17 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); # define sam_dmasample(handle,regs) #endif -/************************************************************************************ +/**************************************************************************** * Name: sam_dmadump * * Description: * Dump previously sampled DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg); +void sam_dmadump(DMA_HANDLE handle, + const struct sam_dmaregs_s *regs, const char *msg); #else # define sam_dmadump(handle,regs,msg) #endif diff --git a/arch/arm/src/samv7/same70_periphclks.h b/arch/arm/src/samv7/same70_periphclks.h index c59a6fbb31e..4e6dfdca226 100644 --- a/arch/arm/src/samv7/same70_periphclks.h +++ b/arch/arm/src/samv7/same70_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/same70_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAME70_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAMV7_SAME70_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) @@ -172,19 +173,19 @@ #define sam_ccw_disableclk() -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -195,9 +196,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/samv7/samv71_periphclks.h b/arch/arm/src/samv7/samv71_periphclks.h index 4eeb9bb77ec..76851e90e32 100644 --- a/arch/arm/src/samv7/samv71_periphclks.h +++ b/arch/arm/src/samv7/samv71_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/samv7/samv71_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_SAMV7_SAMV71_PERIPHCLKS_H #define __ARCH_ARM_SRC_SAMV7_SAMV71_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include #include "hardware/sam_pmc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* Helper macros */ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) @@ -176,19 +177,19 @@ #define sam_ccw_disableclk() -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -199,9 +200,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus)