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SAMA5D3/4: UPLL divisor to generate 48MHz for OHCI is different from the two families. No idea why.

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This commit is contained in:
Gregory Nutt
2014-07-03 12:28:11 -06:00
parent 73ed49fe06
commit 5ba0617e9c
9 changed files with 39 additions and 0 deletions
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configs/sama5d3-xplained/include/board_396mhz.h
+6
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@@ -162,6 +162,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking
configs/sama5d3-xplained/include/board_528mhz.h
+6
View File
@@ -161,6 +161,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking
configs/sama5d3-xplained/include/board_sdram.h
+6
View File
@@ -100,6 +100,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* ADC Configuration
configs/sama5d3x-ek/include/board_396mhz.h
+6
View File
@@ -162,6 +162,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking
configs/sama5d3x-ek/include/board_528mhz.h
+6
View File
@@ -160,6 +160,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking
configs/sama5d3x-ek/include/board_sdram.h
+6
View File
@@ -100,6 +100,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* ADC Configuration
configs/sama5d4-ek/include/board_396mhz.h
+1
View File
@@ -161,6 +161,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* HSMCI clocking
configs/sama5d4-ek/include/board_528mhz.h
+1
View File
@@ -160,6 +160,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* HSMCI clocking
configs/sama5d4-ek/include/board_sdram.h
+1
View File
@@ -101,6 +101,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* ADC Configuration