diff --git a/configs/sama5d3-xplained/include/board_396mhz.h b/configs/sama5d3-xplained/include/board_396mhz.h
index 7293956a50e..88369eb4942 100644
--- a/configs/sama5d3-xplained/include/board_396mhz.h
+++ b/configs/sama5d3-xplained/include/board_396mhz.h
@@ -162,6 +162,12 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+
+/* REVISIT:  The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine.  No idea why?
+ */
+
+#  define BOARD_UPLL_OHCI_DIV        (5)   /* Divide by 5 */
 #endif
 
 /* HSMCI clocking
diff --git a/configs/sama5d3-xplained/include/board_528mhz.h b/configs/sama5d3-xplained/include/board_528mhz.h
index dc857bee4b1..78be010cabd 100644
--- a/configs/sama5d3-xplained/include/board_528mhz.h
+++ b/configs/sama5d3-xplained/include/board_528mhz.h
@@ -161,6 +161,12 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+
+/* REVISIT:  The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine.  No idea why?
+ */
+
+#  define BOARD_UPLL_OHCI_DIV        (5)   /* Divide by 5 */
 #endif
 
 /* HSMCI clocking
diff --git a/configs/sama5d3-xplained/include/board_sdram.h b/configs/sama5d3-xplained/include/board_sdram.h
index 4f2e5f971f1..cd5a5b5dfce 100644
--- a/configs/sama5d3-xplained/include/board_sdram.h
+++ b/configs/sama5d3-xplained/include/board_sdram.h
@@ -100,6 +100,12 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+
+/* REVISIT:  The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine.  No idea why?
+ */
+
+#  define BOARD_UPLL_OHCI_DIV        (5)   /* Divide by 5 */
 #endif
 
 /* ADC Configuration
diff --git a/configs/sama5d3x-ek/include/board_396mhz.h b/configs/sama5d3x-ek/include/board_396mhz.h
index ef850fda8fa..3fbe75b17e2 100644
--- a/configs/sama5d3x-ek/include/board_396mhz.h
+++ b/configs/sama5d3x-ek/include/board_396mhz.h
@@ -162,6 +162,12 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+
+/* REVISIT:  The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine.  No idea why?
+ */
+
+#  define BOARD_UPLL_OHCI_DIV        (5)   /* Divide by 5 */
 #endif
 
 /* HSMCI clocking
diff --git a/configs/sama5d3x-ek/include/board_528mhz.h b/configs/sama5d3x-ek/include/board_528mhz.h
index 0b2744030d8..08a6fba26b2 100644
--- a/configs/sama5d3x-ek/include/board_528mhz.h
+++ b/configs/sama5d3x-ek/include/board_528mhz.h
@@ -160,6 +160,12 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+
+/* REVISIT:  The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine.  No idea why?
+ */
+
+#  define BOARD_UPLL_OHCI_DIV        (5)   /* Divide by 5 */
 #endif
 
 /* HSMCI clocking
diff --git a/configs/sama5d3x-ek/include/board_sdram.h b/configs/sama5d3x-ek/include/board_sdram.h
index 9e4b6046904..990673aaaed 100644
--- a/configs/sama5d3x-ek/include/board_sdram.h
+++ b/configs/sama5d3x-ek/include/board_sdram.h
@@ -100,6 +100,12 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+
+/* REVISIT:  The divisor of 10 produces a rate that is too high. Division
+ * by 5, however, seems to work just fine.  No idea why?
+ */
+
+#  define BOARD_UPLL_OHCI_DIV        (5)   /* Divide by 5 */
 #endif
 
 /* ADC Configuration
diff --git a/configs/sama5d4-ek/include/board_396mhz.h b/configs/sama5d4-ek/include/board_396mhz.h
index 11af935ed3a..34441910ffe 100644
--- a/configs/sama5d4-ek/include/board_396mhz.h
+++ b/configs/sama5d4-ek/include/board_396mhz.h
@@ -161,6 +161,7 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+#  define BOARD_UPLL_OHCI_DIV        (10)  /* Divide by 10 */
 #endif
 
 /* HSMCI clocking
diff --git a/configs/sama5d4-ek/include/board_528mhz.h b/configs/sama5d4-ek/include/board_528mhz.h
index aa6a336e85d..7b34f09b488 100644
--- a/configs/sama5d4-ek/include/board_528mhz.h
+++ b/configs/sama5d4-ek/include/board_528mhz.h
@@ -160,6 +160,7 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+#  define BOARD_UPLL_OHCI_DIV        (10)  /* Divide by 10 */
 #endif
 
 /* HSMCI clocking
diff --git a/configs/sama5d4-ek/include/board_sdram.h b/configs/sama5d4-ek/include/board_sdram.h
index 5b113d17eed..f86d2827dc7 100644
--- a/configs/sama5d4-ek/include/board_sdram.h
+++ b/configs/sama5d4-ek/include/board_sdram.h
@@ -101,6 +101,7 @@
 #  define BOARD_USE_UPLL             1     /* Use UPLL for clock source */
 #  define BOARD_CKGR_UCKR_UPLLCOUNT  (15)  /* Maximum value */
 #  define BOARD_CKGR_UCKR_BIASCOUNT  (15)  /* Maximum value */
+#  define BOARD_UPLL_OHCI_DIV        (10)  /* Divide by 10 */
 #endif
 
 /* ADC Configuration