arm/fpu: FPU is supported when the TEE is enabled

Summary:
1. Support armv7-a armv7-r armv8-r
2. The NSACR is read-only in Non-secure PL1 and PL2 modes.
3. The NSACR is read/write in Secure PL1 modes.
4. When the NSACR.{CP11,CP10} bit is set to 1,
   Non-secure access to coprocessor 11,10 enable

Signed-off-by: wangming9 <wangming9@xiaomi.com>
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>

arch/arm/src/armv7-a/arm_fpuconfig.S

@@ -75,6 +75,13 @@ arm_fpuconfig:
 	mcr		CP15_CPACR(r0)
 
 	/* Enable access to CP10 and CP11 in CP15.NSACR */
+
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
+	mrc		CP15_NSACR(r0)
+	orr		r0, r0, #0xc00
+	mcr		CP15_NSACR(r0)
+#endif
+
 	/* REVISIT: Do we need to do this? */
 
 	/* Set FPEXC.EN (B30) */

arch/arm/src/armv7-r/arm_fpuconfig.S

@@ -75,6 +75,13 @@ arm_fpuconfig:
 	mcr		CP15_CPACR(r0)
 
 	/* Enable access to CP10 and CP11 in CP15.NSACR */
+
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
+	mrc		CP15_NSACR(r0)
+	orr		r0, r0, #0xc00
+	mcr		CP15_NSACR(r0)
+#endif
+
 	/* REVISIT: Do we need to do this? */
 
 	/* Set FPEXC.EN (B30) */

arch/arm/src/armv8-r/arm_fpuconfig.S

@@ -75,6 +75,13 @@ arm_fpuconfig:
 	mcr		CP15_CPACR(r0)
 
 	/* Enable access to CP10 and CP11 in CP15.NSACR */
+
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
+	mrc		CP15_NSACR(r0)
+	orr		r0, r0, #0xc00
+	mcr		CP15_NSACR(r0)
+#endif
+
 	/* REVISIT: Do we need to do this? */
 
 	/* Set FPEXC.EN (B30) */