mirror of
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Add STM32 FLASH driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3573 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -45,8 +45,9 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
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CHIP_ASRCS =
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CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_idle.c \
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CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_flash.c \
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stm32_irq.c stm32_timerisr.c stm32_dma.c stm32_lowputc.c \
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stm32_serial.c stm32_spi.c stm32_usbdev.c stm32_sdio.c \
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stm32_tim.c stm32_i2c.c stm32_pwr.c stm32_rtc.c stm32_waste.c
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stm32_tim.c stm32_i2c.c stm32_pwr.c stm32_rtc.c \
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stm32_idle.c stm32_waste.c
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Executable
+115
@@ -0,0 +1,115 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_flash.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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||||
* 3. Neither the name NuttX nor the names of its contributors may be
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||||
* used to endorse or promote products derived from this software
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||||
* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifdef CONFIG_STM32_LOWDENSITY
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# define STM32_FLASH_NPAGES 32
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# define STM32_FLASH_PAGESIZE 1024
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#elif CONFIG_STM32_MEDIUMDENSITY
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# define STM32_FLASH_NPAGES 128
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# define STM32_FLASH_PAGESIZE 1024
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#elif CONFIG_STM32_CONNECTIVITYLINE
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# define STM32_FLASH_NPAGES 128
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# define STM32_FLASH_PAGESIZE 2048
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#elif CONFIG_STM32_HIGHDENSITY
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# define STM32_FLASH_NPAGES 256
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# define STM32_FLASH_PAGESIZE 2048
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#endif
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#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
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/* Register Offsets *****************************************************************/
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#define STM32_FLASH_ACR_OFFSET 0x0000
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#define STM32_FLASH_KEYR_OFFSET 0x0004
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#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
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#define STM32_FLASH_SR_OFFSET 0x000c
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#define STM32_FLASH_CR_OFFSET 0x0010
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#define STM32_FLASH_AR_OFFSET 0x0014
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#define STM32_FLASH_OBR_OFFSET 0x001c
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#define STM32_FLASH_WRPR_OFFSET 0x0020
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/* Register Addresses ***************************************************************/
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#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
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#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
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#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
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#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
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#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
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#define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
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#define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
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#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* TODO: Complete FLASH details from the STM32F10xxx Flash programming manual. */
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/* Flash Status Register (SR) */
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#define FLASH_SR_BSY (1 << 0) /* Busy */
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#define FLASH_SR_PGERR (1 << 2) /* Programming Error */
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#define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */
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#define FLASH_SR_EOP (1 << 5) /* End of Operation */
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/* Flash Control Register (CR) */
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#define FLASH_CR_PG (1 << 0) /* Program Page */
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#define FLASH_CR_PER (1 << 1) /* Page Erase */
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#define FLASH_CR_MER (1 << 2) /* Mass Erase */
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#define FLASH_CR_OPTPG (1 << 4) /* Option Byte Programming */
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#define FLASH_CR_OPTER (1 << 5) /* Option Byte Erase */
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#define FLASH_CR_STRT (1 << 6) /* Start Erase */
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#define FLASH_CR_LOCK (1 << 7) /* Page Locked or Lock Page */
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#define FLASH_CR_OPTWRE (1 << 9) /* Option Bytes Write Enable */
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#define FLASH_CR_ERRIE (1 << 10) /* Error Interrupt Enable */
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#define FLASH_CR_EOPIE (1 << 12) /* End of Program Interrupt Enable */
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/* Flash Access Control Register (ACR) */
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#define FLASH_ACR_LATENCY_SHIFT (0)
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#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
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# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* FLASH Zero Latency cycle */
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# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* FLASH One Latency cycle */
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# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* FLASH Two Latency cycles */
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#define FLASH_ACR_HLFCYA (1 << 3) /* FLASH half cycle access */
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#define FLASH_ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H */
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@@ -0,0 +1,228 @@
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/************************************************************************************
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* arch/arm/src/stm32/stm32_flash.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Author: Uros Platise <uros.platise@isotel.eu>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
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||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/** \file
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* \author Uros Platise
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* \brief STM32 Flash - Program and Data Memory
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*
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* Provides standard flash access function, to be used also by the
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* drivers/mtd/progmem.c program memory flash mtd driver.
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* The interface is to be defined in the include/nuttx/progmem.h
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*
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* Requirements:
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* - During write/erase operatoins on FLASH, HSI must be ON.
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* - Low Power Modes are not permitted during write/erase
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*/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <errno.h>
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#include "stm32_flash.h"
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#include "stm32_rcc.h"
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#include "stm32_waste.h"
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#include "up_arch.h"
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/************************************************************************************
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* Declarations
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************************************************************************************/
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#define FLASH_KEY1 0x45670123
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#define FLASH_KEY2 0xCDEF89AB
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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void stm32_flash_unlock(void)
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{
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while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste();
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if ( getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK ) {
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/* Unlock sequence */
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putreg32(FLASH_KEY1, STM32_FLASH_KEYR);
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putreg32(FLASH_KEY2, STM32_FLASH_KEYR);
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}
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}
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void stm32_flash_lock(void)
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{
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modifyreg16(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
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}
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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uint16_t up_progmem_npages(void)
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{
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return STM32_FLASH_NPAGES;
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}
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bool up_progmem_isuniform(void)
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{
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return TRUE;
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}
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uint16_t up_progmem_pagesize(uint16_t page)
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{
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return STM32_FLASH_PAGESIZE;
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}
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int up_progmem_getpage(uint32_t addr)
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{
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if (addr >= STM32_FLASH_SIZE)
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return -EFAULT;
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return addr / STM32_FLASH_PAGESIZE;
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}
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int up_progmem_erasepage(uint16_t page)
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{
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uint32_t addr;
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uint16_t count;
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if (page >= STM32_FLASH_NPAGES)
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return -EFAULT;
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/* Get flash ready and begin erasing single page */
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if ( !(getreg32(STM32_RCC_CR) & RCC_CR_HSION) )
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return -EPERM;
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stm32_flash_unlock();
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modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PER);
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putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR);
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modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT);
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while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste();
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modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0);
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/* Verify */
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for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE;
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count; count-=4, addr += 4) {
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if (getreg32(addr) != 0xFFFFFFFF)
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return -EIO;
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}
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return STM32_FLASH_PAGESIZE;
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}
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int up_progmem_ispageerased(uint16_t page)
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{
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uint32_t addr;
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uint16_t count;
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uint16_t bwritten = 0;
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uint16_t hword;
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if (page >= STM32_FLASH_NPAGES)
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return -EFAULT;
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/* Verify */
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for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE;
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count; count--, addr++) {
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if (getreg8(addr) != 0xFF) bwritten++;
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}
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return bwritten;
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}
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int up_progmem_write(uint32_t addr, const void *buf, size_t count)
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{
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uint16_t *hword = (uint16_t *)buf;
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size_t written = count;
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/* STM32 requires half-word access */
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if (count & 1)
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return -EINVAL;
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/* Check for valid address range */
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if ( (addr+count) >= STM32_FLASH_SIZE)
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return -EFAULT;
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/* Get flash ready and begin flashing */
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if ( !(getreg32(STM32_RCC_CR) & RCC_CR_HSION) )
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return -EPERM;
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stm32_flash_unlock();
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modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
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for (addr += STM32_FLASH_BASE; count; count--, hword++, addr+=2) {
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/* Write half-word and wait to complete */
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putreg16(*hword, addr);
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while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste();
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/* Verify */
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if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRPRT_ERR) {
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modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
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return -EROFS;
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}
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if (getreg16(addr) != *hword) {
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modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
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return -EIO;
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}
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}
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modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
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return written;
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}
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@@ -1,8 +1,8 @@
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/************************************************************************************
|
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* arch/arm/src/stm32/stm32_flash.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Author: Uros Platise <uros.platise@isotel.eu>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -36,64 +36,10 @@
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H
|
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#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H
|
||||
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/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/progmem.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0004
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
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#define STM32_FLASH_SR_OFFSET 0x000c
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||||
#define STM32_FLASH_CR_OFFSET 0x0010
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#define STM32_FLASH_AR_OFFSET 0x0014
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#define STM32_FLASH_OBR_OFFSET 0x001c
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||||
#define STM32_FLASH_WRPR_OFFSET 0x0020
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||||
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/* Register Addresses ***************************************************************/
|
||||
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#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
|
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#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
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#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
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#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
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#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
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#define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
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||||
#define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
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||||
#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
/* TODO: FLASH details from the STM32F10xxx Flash programming manual. */
|
||||
|
||||
/* Flash Access Control Register (ACR) */
|
||||
|
||||
#define ACR_LATENCY_SHIFT (0)
|
||||
#define ACR_LATENCY_MASK (7 << ACR_LATENCY_SHIFT)
|
||||
# define ACR_LATENCY_0 (0 << ACR_LATENCY_SHIFT) /* FLASH Zero Latency cycle */
|
||||
# define ACR_LATENCY_1 (1 << ACR_LATENCY_SHIFT) /* FLASH One Latency cycle */
|
||||
# define ACR_LATENCY_2 (2 << ACR_LATENCY_SHIFT) /* FLASH Two Latency cycles */
|
||||
#define ACR_HLFCYA (1 << 3) /* FLASH half cycle access */
|
||||
#define ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
#include "chip/stm32_flash.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */
|
||||
|
||||
|
||||
@@ -413,8 +413,8 @@ static inline void stm32_stdclockconfig(void)
|
||||
/* Enable FLASH prefetch buffer and 2 wait states */
|
||||
|
||||
regval = getreg32(STM32_FLASH_ACR);
|
||||
regval &= ~ACR_LATENCY_MASK;
|
||||
regval |= (ACR_LATENCY_2|ACR_PRTFBE);
|
||||
regval &= ~FLASH_ACR_LATENCY_MASK;
|
||||
regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
Reference in New Issue
Block a user