diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 6b0114dcb7f..1a969347206 100755 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -45,8 +45,9 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_usestack.c up_doirq.c up_hardfault.c up_svcall.c CHIP_ASRCS = -CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_idle.c \ +CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_flash.c \ stm32_irq.c stm32_timerisr.c stm32_dma.c stm32_lowputc.c \ stm32_serial.c stm32_spi.c stm32_usbdev.c stm32_sdio.c \ - stm32_tim.c stm32_i2c.c stm32_pwr.c stm32_rtc.c stm32_waste.c + stm32_tim.c stm32_i2c.c stm32_pwr.c stm32_rtc.c \ + stm32_idle.c stm32_waste.c diff --git a/arch/arm/src/stm32/chip/stm32_flash.h b/arch/arm/src/stm32/chip/stm32_flash.h new file mode 100755 index 00000000000..018d3e8abd2 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32_flash.h @@ -0,0 +1,115 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_flash.h + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifdef CONFIG_STM32_LOWDENSITY +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 1024 +#elif CONFIG_STM32_MEDIUMDENSITY +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 1024 +#elif CONFIG_STM32_CONNECTIVITYLINE +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 +#elif CONFIG_STM32_HIGHDENSITY +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 +#endif + +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) + +/* Register Offsets *****************************************************************/ + +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_KEYR_OFFSET 0x0004 +#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 +#define STM32_FLASH_SR_OFFSET 0x000c +#define STM32_FLASH_CR_OFFSET 0x0010 +#define STM32_FLASH_AR_OFFSET 0x0014 +#define STM32_FLASH_OBR_OFFSET 0x001c +#define STM32_FLASH_WRPR_OFFSET 0x0020 + +/* Register Addresses ***************************************************************/ + +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) +#define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) +#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ +/* TODO: Complete FLASH details from the STM32F10xxx Flash programming manual. */ + +/* Flash Status Register (SR) */ + +#define FLASH_SR_BSY (1 << 0) /* Busy */ +#define FLASH_SR_PGERR (1 << 2) /* Programming Error */ +#define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */ +#define FLASH_SR_EOP (1 << 5) /* End of Operation */ + +/* Flash Control Register (CR) */ + +#define FLASH_CR_PG (1 << 0) /* Program Page */ +#define FLASH_CR_PER (1 << 1) /* Page Erase */ +#define FLASH_CR_MER (1 << 2) /* Mass Erase */ +#define FLASH_CR_OPTPG (1 << 4) /* Option Byte Programming */ +#define FLASH_CR_OPTER (1 << 5) /* Option Byte Erase */ +#define FLASH_CR_STRT (1 << 6) /* Start Erase */ +#define FLASH_CR_LOCK (1 << 7) /* Page Locked or Lock Page */ +#define FLASH_CR_OPTWRE (1 << 9) /* Option Bytes Write Enable */ +#define FLASH_CR_ERRIE (1 << 10) /* Error Interrupt Enable */ +#define FLASH_CR_EOPIE (1 << 12) /* End of Program Interrupt Enable */ + +/* Flash Access Control Register (ACR) */ + +#define FLASH_ACR_LATENCY_SHIFT (0) +#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* FLASH Zero Latency cycle */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* FLASH One Latency cycle */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* FLASH Two Latency cycles */ +#define FLASH_ACR_HLFCYA (1 << 3) /* FLASH half cycle access */ +#define FLASH_ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H */ + diff --git a/arch/arm/src/stm32/stm32_flash.c b/arch/arm/src/stm32/stm32_flash.c new file mode 100644 index 00000000000..7c63ca2c17a --- /dev/null +++ b/arch/arm/src/stm32/stm32_flash.c @@ -0,0 +1,228 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_flash.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/** \file + * \author Uros Platise + * \brief STM32 Flash - Program and Data Memory + * + * Provides standard flash access function, to be used also by the + * drivers/mtd/progmem.c program memory flash mtd driver. + * The interface is to be defined in the include/nuttx/progmem.h + * + * Requirements: + * - During write/erase operatoins on FLASH, HSI must be ON. + * - Low Power Modes are not permitted during write/erase + */ + +#include +#include +#include + +#include "stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_waste.h" +#include "up_arch.h" + + +/************************************************************************************ + * Declarations + ************************************************************************************/ + +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xCDEF89AB + + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +void stm32_flash_unlock(void) +{ + while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste(); + + if ( getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK ) { + + /* Unlock sequence */ + + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); + } +} + + +void stm32_flash_lock(void) +{ + modifyreg16(STM32_FLASH_CR, 0, FLASH_CR_LOCK); +} + + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +uint16_t up_progmem_npages(void) +{ + return STM32_FLASH_NPAGES; +} + + +bool up_progmem_isuniform(void) +{ + return TRUE; +} + + +uint16_t up_progmem_pagesize(uint16_t page) +{ + return STM32_FLASH_PAGESIZE; +} + + +int up_progmem_getpage(uint32_t addr) +{ + if (addr >= STM32_FLASH_SIZE) + return -EFAULT; + + return addr / STM32_FLASH_PAGESIZE; +} + + +int up_progmem_erasepage(uint16_t page) +{ + uint32_t addr; + uint16_t count; + + if (page >= STM32_FLASH_NPAGES) + return -EFAULT; + + /* Get flash ready and begin erasing single page */ + + if ( !(getreg32(STM32_RCC_CR) & RCC_CR_HSION) ) + return -EPERM; + + stm32_flash_unlock(); + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PER); + putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); + + while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste(); + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0); + + /* Verify */ + + for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; + count; count-=4, addr += 4) { + + if (getreg32(addr) != 0xFFFFFFFF) + return -EIO; + } + + return STM32_FLASH_PAGESIZE; +} + + +int up_progmem_ispageerased(uint16_t page) +{ + uint32_t addr; + uint16_t count; + uint16_t bwritten = 0; + uint16_t hword; + + if (page >= STM32_FLASH_NPAGES) + return -EFAULT; + + /* Verify */ + + for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; + count; count--, addr++) { + + if (getreg8(addr) != 0xFF) bwritten++; + } + + return bwritten; +} + + +int up_progmem_write(uint32_t addr, const void *buf, size_t count) +{ + uint16_t *hword = (uint16_t *)buf; + size_t written = count; + + /* STM32 requires half-word access */ + + if (count & 1) + return -EINVAL; + + /* Check for valid address range */ + + if ( (addr+count) >= STM32_FLASH_SIZE) + return -EFAULT; + + /* Get flash ready and begin flashing */ + + if ( !(getreg32(STM32_RCC_CR) & RCC_CR_HSION) ) + return -EPERM; + + stm32_flash_unlock(); + + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); + + for (addr += STM32_FLASH_BASE; count; count--, hword++, addr+=2) { + + /* Write half-word and wait to complete */ + + putreg16(*hword, addr); + + while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste(); + + /* Verify */ + + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRPRT_ERR) { + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); + return -EROFS; + } + + if (getreg16(addr) != *hword) { + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); + return -EIO; + } + + } + + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); + return written; +} diff --git a/arch/arm/src/stm32/stm32_flash.h b/arch/arm/src/stm32/stm32_flash.h index 1203d777edf..6f286bf2c56 100755 --- a/arch/arm/src/stm32/stm32_flash.h +++ b/arch/arm/src/stm32/stm32_flash.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32/stm32_flash.h * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,64 +36,10 @@ #ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H #define __ARCH_ARM_SRC_STM32_STM32_FLASH_H -/************************************************************************************ - * Included Files - ************************************************************************************/ - #include +#include #include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STM32_FLASH_ACR_OFFSET 0x0000 -#define STM32_FLASH_KEYR_OFFSET 0x0004 -#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 -#define STM32_FLASH_SR_OFFSET 0x000c -#define STM32_FLASH_CR_OFFSET 0x0010 -#define STM32_FLASH_AR_OFFSET 0x0014 -#define STM32_FLASH_OBR_OFFSET 0x001c -#define STM32_FLASH_WRPR_OFFSET 0x0020 - -/* Register Addresses ***************************************************************/ - -#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) -#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) -#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) -#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) -#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) -#define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) -#define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) -#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ -/* TODO: FLASH details from the STM32F10xxx Flash programming manual. */ - -/* Flash Access Control Register (ACR) */ - -#define ACR_LATENCY_SHIFT (0) -#define ACR_LATENCY_MASK (7 << ACR_LATENCY_SHIFT) -# define ACR_LATENCY_0 (0 << ACR_LATENCY_SHIFT) /* FLASH Zero Latency cycle */ -# define ACR_LATENCY_1 (1 << ACR_LATENCY_SHIFT) /* FLASH One Latency cycle */ -# define ACR_LATENCY_2 (2 << ACR_LATENCY_SHIFT) /* FLASH Two Latency cycles */ -#define ACR_HLFCYA (1 << 3) /* FLASH half cycle access */ -#define ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ +#include "chip/stm32_flash.h" #endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */ - diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 480345938e9..f39aa0d4292 100755 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -413,8 +413,8 @@ static inline void stm32_stdclockconfig(void) /* Enable FLASH prefetch buffer and 2 wait states */ regval = getreg32(STM32_FLASH_ACR); - regval &= ~ACR_LATENCY_MASK; - regval |= (ACR_LATENCY_2|ACR_PRTFBE); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE); putreg32(regval, STM32_FLASH_ACR); /* Set the HCLK source/divider */