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Misc updates to SAM3U register definition files for SAM4S compatibility

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This commit is contained in:
Gregory Nutt
2013-06-12 12:35:48 -06:00
parent fa45b86b4d
commit 535dc49dea
9 changed files with 602 additions and 306 deletions
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arch/arm/src/sam34/chip/sam_pwm.h
+14
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@@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_pwm.h
* Pulse Width Modulation Controller (PWM) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -83,6 +84,9 @@
#define SAM_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */
#define SAM_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */
/* 0x084-0x0ac: Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */
#endif
/* 0x0b4-0x0e0: Reserved */
#define SAM_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */
#define SAM_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */
@@ -215,6 +219,10 @@
#define SAM_PWM_FPE (SAM_PWM_BASE+SAM_PWM_FPE_OFFSET)
#define SAM_PWM_EL0MR (SAM_PWM_BASE+SAM_PWM_EL0MR_OFFSET)
#define SAM_PWM_EL1MR (SAM_PWM_BASE+SAM_PWM_EL1MR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */
# define SAM_PWM_SMMR_OFFSET 0x0b0 /* PWM Stepper Motor Mode Register */
#endif
#define SAM_PWM_WPCR (SAM_PWM_BASE+SAM_PWM_WPCR_OFFSET)
#define SAM_PWM_WPSR (SAM_PWM_BASE+SAM_PWM_WPSR_OFFSET)
@@ -518,6 +526,12 @@
#define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */
#define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */
/* PWM Stepper Motor Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# warning SAM4S not yet integrated
#endif
/* PWM Write Protect Control Register */
#define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */
arch/arm/src/sam34/chip/sam_rstc.h
+3
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@@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_rstc.h
* Reset Controller (RSTC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -68,6 +69,7 @@
#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */
#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
# define RSTC_CR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */
#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */
@@ -86,6 +88,7 @@
#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT)
#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
# define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
/****************************************************************************************
* Public Types
arch/arm/src/sam34/chip/sam_rtc.h
+86 -1
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@@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_rtc.h
* Real-time Clock (RTC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -81,6 +82,8 @@
/* RTC register bit definitions *********************************************************/
/* RTC Control Register */
#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */
#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */
#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */
@@ -95,8 +98,56 @@
# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT)
# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT)
/* RTC Mode Register */
#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_MR_PERSIAN (1 << 1) /* Bit 1: PERSIAN Calendar */
# define RTC_MR_NEGPPM (1 << 4) /* Bit 4: Negative PPM Correction */
# define RTC_MR_CORRECTION_SHIFT (8) /* Bits 8-14: Slow Clock Correction */
# define RTC_MR_CORRECTION_
# define RTC_MR_HIGHPPM (1 << 15) /* Bit 15: HIGH PPM Correction */
# define RTC_MR_OUT0_SHIFT (16) /* Bits 16-18: RTCOUT0 Output Source Selection */
# define RTC_MR_OUT0_MASK (7 << RTC_MR_OUT0_SHIFT)
# define RTC_MR_OUT0_NOWAVE (0 << RTC_MR_OUT0_SHIFT) /* No waveform, stuck at 0 */
# define RTC_MR_OUT0_FREQ1HZ (1 << RTC_MR_OUT0_SHIFT) /* 1Hz square wave */
# define RTC_MR_OUT0_FREQ32HZ (2 << RTC_MR_OUT0_SHIFT) /* 32Hz square wave */
# define RTC_MR_OUT0_FREQ64HZ (3 << RTC_MR_OUT0_SHIFT) /* 64Hz square wave */
# define RTC_MR_OUT0_FREQ512HZ (4 << RTC_MR_OUT0_SHIFT) /* 512Hz square wave */
# define RTC_MR_OUT0_ALARM_TOGGLE (5 << RTC_MR_OUT0_SHIFT) /* Output toggles when alarm flag rises */
# define RTC_MR_OUT0_ALARM_FLAG (6 << RTC_MR_OUT0_SHIFT) /* Output is a copy of the alarm flag */
# define RTC_MR_OUT0_PROG_PULSE (7 << RTC_MR_OUT0_SHIFT) /* Duty cycle programmable pulse */
# define RTC_MR_OUT1_SHIFT (20) /* Bits 20-22: RTCOUT1 Output Source Selection */
# define RTC_MR_OUT1_MASK (7 << RTC_MR_OUT1_SHIFT)
# define RTC_MR_OUT1_NOWAVE (0 << RTC_MR_OUT1_SHIFT) /* No waveform, stuck at 0 */
# define RTC_MR_OUT1_FREQ1HZ (1 << RTC_MR_OUT1_SHIFT) /* 1Hz square wave */
# define RTC_MR_OUT1_FREQ32HZ (2 << RTC_MR_OUT1_SHIFT) /* 32Hz square wave */
# define RTC_MR_OUT1_FREQ64HZ (3 << RTC_MR_OUT1_SHIFT) /* 64Hz square wave */
# define RTC_MR_OUT1_FREQ512HZ (4 << RTC_MR_OUT1_SHIFT) /* 512Hz square wave */
# define RTC_MR_OUT1_ALARM_TOGGLE (5 << RTC_MR_OUT1_SHIFT) /* Output toggles when alarm flag rises */
# define RTC_MR_OUT1_ALARM_FLAG (6 << RTC_MR_OUT1_SHIFT) /* Output is a copy of the alarm flag */
# define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */
# define RTC_MR_THIGH_SHIFT (24) /* Bits 24-26: High Duration of the Output Pulse */
# define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT)
# define RTC_MR_THIGH_ 31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
# define RTC_MR_THIGH_ 16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
# define RTC_MR_THIGH_ 4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
# define RTC_MR_THIGH_ 976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
# define RTC_MR_THIGH_ 488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
# define RTC_MR_THIGH_ 22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
# define RTC_MR_THIGH_ 0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
# define RTC_MR_THIGH_ 15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */
# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT)
# define RTC_MR_TPERIOD_ 1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */
# define RTC_MR_TPERIOD_ 500MS (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */
# define RTC_MR_TPERIOD_ 250MS (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */
# define RTC_MR_TPERIOD_ 125MS (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */
#endif
/* RTC Time Register */
#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */
#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT)
#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */
@@ -105,6 +156,8 @@
#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT)
#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */
/* RTC Calendar Register */
#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */
#define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT)
#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */
@@ -116,6 +169,8 @@
#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */
#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT)
/* RTC Time Alarm Register */
#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */
#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT)
#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */
@@ -127,43 +182,73 @@
#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */
#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */
/* RTC Calendar Alarm Register */
#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */
#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT)
#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */
#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */
#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT)
#define RTC_CALALR_DATE_MASK (0x3f << RTC_CALALR_DATE_SHIFT)
#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */
/* RTC Status Register */
#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */
#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */
#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */
#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */
#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_SR_TDERR (1 << 5) /* Bit 5: Time and/or Date Free Running Error */
#endif
/* RTC Status Clear Command Register */
#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */
#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */
#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */
#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */
#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_SR_TDERRCLR (1 << 5) /* Bit 5: Time and/or Date Free Running Error Clear */
#endif
/* RTC Interrupt Enable Register */
#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */
#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */
#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */
#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */
#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_SR_TDERREN (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Enable */
#endif
/* RTC Interrupt Disable Register */
#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */
#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */
#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */
#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */
#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTC_SR_TDERRDIS (1 << 5) /* Bit 5: Time and/or Date Error Interrupt Disable */
#endif
/* RTC Interrupt Mask Register */
#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */
#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */
#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */
#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */
#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */
/* RTC Valid Entry Register */
#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */
#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */
#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */
arch/arm/src/sam34/chip/sam_rtt.h
+13
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@@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_rtt.h
* Real-time Timer (RTT) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -65,12 +66,24 @@
/* RTT register bit definitions ********************************************************/
/* Real-time Timer Mode Register */
#define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */
#define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT)
#define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */
#define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */
#define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define RTT_MR_RTTDIS (1 << 20) /* Bit 20: Real-time Timer Disable */
# define RTT_MR_RTC1HZ (1 << 24) /* Bit 24: Real-Time Clock 1Hz Clock Selection */
#endif
/* Real-time Timer Alarm Register (32-bit alarm value) */
/* Real-time Timer Value Register (32-bit timer value) */
/* Real-time Timer Status Register */
#define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */
#define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */
arch/arm/src/sam34/chip/sam_smc.h
+358 -289
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File diff suppressed because it is too large Load Diff
arch/arm/src/sam34/chip/sam_spi.h
+1
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@@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_spi.h
* Serial Peripheral Interface (SPI) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/sam34/chip/sam_ssc.h
+12 -9
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@@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_ssc.h
* Synchronous Serial Controller (SSC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -74,7 +75,7 @@
#define SAM_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */
#define SAM_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */
/* 0x050-0x0fc: Reserved */
/* 0x100-0x124: Reserved */
/* 0x100-0x124: Reserved for PDC registers */
/* SSC register adresses ****************************************************************/
@@ -121,7 +122,7 @@
# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */
#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */
#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT)
# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */
# define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */
# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */
# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */
#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */
@@ -142,12 +143,11 @@
# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */
# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */
#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */
#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */
#define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */
#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT)
#define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */
#define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT)
/* SSC Receive Frame Mode Register */
#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */
@@ -162,7 +162,7 @@
#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT)
# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */
# define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */
# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_RFMR_FSOS_POS (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
@@ -175,11 +175,11 @@
#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */
#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT)
# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */
# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */
# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */
# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */
# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Pin */
#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */
#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT)
# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */
# define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */
# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */
# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */
#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
@@ -217,7 +217,7 @@
#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT)
# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */
# define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */
# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_TFMR_FSOS_POS (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
@@ -226,6 +226,8 @@
#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */
#define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT)
/* SSC Receive/Transmit Holding Registers (32-bit data) */
/* SSC Receive Synchronization Holding Register */
#define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */
@@ -270,6 +272,7 @@
#define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT)
# define SSC_WPMR_WPKEY (0x00535343 << SSC_WPMR_WPKEY_SHIFT)
/* SSC Write Protect Status Register */
arch/arm/src/sam34/chip/sam_tc.h
+110 -3
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@@ -1,5 +1,6 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam_tc.h
* Timer Counter (TC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -56,7 +57,10 @@
#define SAM_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */
#define SAM_TCN_CCR_OFFSET 0x00 /* Channel Control Register */
#define SAM_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */
/* 0x08 Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#define SAM_TCN_SMMR_OFFSET 0x08 /* Stepper Motor Mode Register */
#endif
/* 0x0c Reserved */
#define SAM_TCN_CV_OFFSET 0x10 /* Counter Value */
#define SAM_TCN_RA_OFFSET 0x14 /* Register A */
@@ -75,8 +79,11 @@
#define SAM_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */
#define SAM_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */
#define SAM_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */
/* 0xd8 Reserved */
/* 0xe4 Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TCN_FMR_OFFSET 0xd8 /* Fault Mode Register */
# define SAM_TCN_WPMR_OFFSET 0xe4 /* Write Protect Mode Register */
#endif
/* TC register adresses *************************************************************************/
@@ -84,6 +91,9 @@
#define SAM_TC_CCR(n) (SAM_TCN_BASE(n)+SAM_TCN_CCR_OFFSET)
#define SAM_TC_CMR(n) (SAM_TCN_BASE(n)+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TCN_SMMR(n) (SAM_TCN_BASE(n)+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC_CV(n) (SAM_TCN_BASE(n)+SAM_TCN_CV_OFFSET)
#define SAM_TC_RA(n) (SAM_TCN_BASE(n)+SAM_TCN_RA_OFFSET)
#define SAM_TC_RB(n) (SAM_TCN_BASE(n)+SAM_TCN_RB_OFFSET)
@@ -92,9 +102,16 @@
#define SAM_TC_IER(n) (SAM_TCN_BASE(n)+SAM_TCN_IER_OFFSET)
#define SAM_TC_IDR(n) (SAM_TCN_BASE(n)+SAM_TCN_IDR_OFFSET)
#define SAM_TC_IMR(n) (SAM_TCN_BASE(n)+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TCN_FMR(n) (SAM_TCN_BASE(n)+SAM_TCN_FMR_OFFSET)
# define SAM_TCN_WPMR(n) (SAM_TCN_BASE(n)+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC0_SMMR (SAM_TC0_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC0_CV (SAM_TC0_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC0_RA (SAM_TC0_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC0_RB (SAM_TC0_BASE+SAM_TCN_RB_OFFSET)
@@ -103,9 +120,16 @@
#define SAM_TC0_IER (SAM_TC0_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC0_IDR (SAM_TC0_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC0_IMR (SAM_TC0_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC1_CCR (SAM_TC1_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC1_CMR (SAM_TC1_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC1_SMMR (SAM_TC1_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC1_CV (SAM_TC1_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC1_RA (SAM_TC1_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC1_RB (SAM_TC1_BASE+SAM_TCN_RB_OFFSET)
@@ -114,9 +138,16 @@
#define SAM_TC1_IER (SAM_TC1_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC1_IDR (SAM_TC1_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC1_IMR (SAM_TC1_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC1_FMR (SAM_TC1_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC1_WPMR (SAM_TC1_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC2_SMMR (SAM_TC2_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC2_CV (SAM_TC2_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC2_RA (SAM_TC2_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC2_RB (SAM_TC2_BASE+SAM_TCN_RB_OFFSET)
@@ -125,6 +156,64 @@
#define SAM_TC2_IER (SAM_TC2_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC2_IDR (SAM_TC2_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC2_IMR (SAM_TC2_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC2_FMR (SAM_TC2_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC2_WPMR (SAM_TC2_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC3_CCR (SAM_TC3_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC3_CMR (SAM_TC3_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC3_SMMR (SAM_TC3_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC3_CV (SAM_TC3_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC3_RA (SAM_TC3_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC3_RB (SAM_TC3_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC3_RC (SAM_TC3_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC3_SR (SAM_TC3_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC3_IER (SAM_TC3_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC3_IDR (SAM_TC3_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC3_IMR (SAM_TC3_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC3_FMR (SAM_TC3_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC3_WPMR (SAM_TC3_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC4_CCR (SAM_TC4_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC4_CMR (SAM_TC4_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC4_SMMR (SAM_TC4_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC4_CV (SAM_TC4_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC4_RA (SAM_TC4_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC4_RB (SAM_TC4_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC4_RC (SAM_TC4_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC4_SR (SAM_TC4_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC4_IER (SAM_TC4_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC4_IDR (SAM_TC4_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC4_IMR (SAM_TC4_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC4_FMR (SAM_TC4_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC4_WPMR (SAM_TC4_BASE+SAM_TCN_WPMR_OFFSET)
#endif
#define SAM_TC5_CCR (SAM_TC5_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC5_CMR (SAM_TC5_BASE+SAM_TCN_CMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC5_SMMR (SAM_TC5_BASE+SAM_TCN_SMMR_OFFSET)
#endif
#define SAM_TC5_CV (SAM_TC5_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC5_RA (SAM_TC5_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC5_RB (SAM_TC5_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC5_RC (SAM_TC5_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC5_SR (SAM_TC5_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC5_IER (SAM_TC5_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC5_IDR (SAM_TC5_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC5_IMR (SAM_TC5_BASE+SAM_TCN_IMR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_TC5_FMR (SAM_TC5_BASE+SAM_TCN_FMR_OFFSET)
# define SAM_TC5_WPMR (SAM_TC5_BASE+SAM_TCN_WPMR_OFFSET)
#endif
/* Timer common registers */
@@ -308,6 +397,12 @@
# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT)
# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT)
/* Stepper Motor Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# warning SAM4S not yet integrated
#endif
/* TC Counter Value Register */
#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */
@@ -332,6 +427,18 @@
#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */
#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/
/* Fault Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# warning SAM4S not yet integrated
#endif
/* Write Protect Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# warning SAM4S not yet integrated
#endif
/************************************************************************************************
* Public Types
************************************************************************************************/
arch/arm/src/sam34/chip/sam_twi.h
+5 -4
View File
@@ -1,5 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_twi.h
* Two-wire Interface (TWI) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -125,13 +126,13 @@
# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */
# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */
#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */
#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT)
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */
#define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT)
/* TWI Slave Mode Register */
#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */
#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT)
#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-22: Slave Address */
#define TWI_SMR_SADR_MASK (0x7f << TWI_SMR_SADR_SHIFT)
/* TWI Internal Address Register */