stm32h7: Initialize CSI and HSI48 clocks as needed based on enabled peripherals.

This commit is contained in:
Anthony Merlino
2021-04-10 20:07:21 -04:00
committed by David Sidrane
parent 05b889457e
commit 4c8d70dd2e
3 changed files with 38 additions and 2 deletions
+10
View File
@@ -410,6 +410,14 @@ config STM32H7_RTC
default n
select RTC
config STM32H7_CSI
bool "CSI Low-speed internal oscillator (4MHz)"
default n
config STM32H7_HSI48
bool "HSI48 High-speed 48MHz internal oscillator"
default n
config STM32H7_PWR
bool "PWR"
default n
@@ -493,12 +501,14 @@ config STM32H7_OTGFS
bool "OTG FS"
default n
select USBHOST_HAVE_ASYNCH if USBHOST
select STM32H7_HSI48
config STM32H7_OTGHS
bool "OTG HS"
default n
depends on EXPERIMENTAL
select USBHOST_HAVE_ASYNCH if USBHOST
select STM32H7_HSI48
config STM32H7_OTG_SOFOUTPUT
bool "OTG SOF output"
+14 -1
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@@ -623,7 +623,6 @@ void stm32_stdclockconfig(void)
}
#endif
#define CONFIG_STM32H7_HSI48
#ifdef CONFIG_STM32H7_HSI48
/* Enable HSI48 */
@@ -638,6 +637,20 @@ void stm32_stdclockconfig(void)
}
#endif
#ifdef CONFIG_STM32H7_CSI
/* Enable CSI */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_CSION;
putreg32(regval, STM32_RCC_CR);
/* Wait until the CSI is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_CSIRDY) == 0)
{
}
#endif
/* Check for a timeout. If this timeout occurs, then we are hosed. We
* have no real back-up plan, although the following logic makes it look
* as though we do.
+14 -1
View File
@@ -637,7 +637,6 @@ void stm32_stdclockconfig(void)
}
#endif
#define CONFIG_STM32H7_HSI48
#ifdef CONFIG_STM32H7_HSI48
/* Enable HSI48 */
@@ -652,6 +651,20 @@ void stm32_stdclockconfig(void)
}
#endif
#ifdef CONFIG_STM32H7_CSI
/* Enable CSI */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_CSION;
putreg32(regval, STM32_RCC_CR);
/* Wait until the CSI is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_CSIRDY) == 0)
{
}
#endif
/* Check for a timeout. If this timeout occurs, then we are hosed. We
* have no real back-up plan, although the following logic makes it look
* as though we do.