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stm32h7: Initialize CSI and HSI48 clocks as needed based on enabled peripherals.
This commit is contained in:
committed by
David Sidrane
parent
05b889457e
commit
4c8d70dd2e
@@ -410,6 +410,14 @@ config STM32H7_RTC
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default n
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select RTC
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config STM32H7_CSI
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bool "CSI Low-speed internal oscillator (4MHz)"
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default n
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config STM32H7_HSI48
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bool "HSI48 High-speed 48MHz internal oscillator"
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default n
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config STM32H7_PWR
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bool "PWR"
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default n
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@@ -493,12 +501,14 @@ config STM32H7_OTGFS
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bool "OTG FS"
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default n
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select USBHOST_HAVE_ASYNCH if USBHOST
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select STM32H7_HSI48
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config STM32H7_OTGHS
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bool "OTG HS"
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default n
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depends on EXPERIMENTAL
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select USBHOST_HAVE_ASYNCH if USBHOST
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select STM32H7_HSI48
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config STM32H7_OTG_SOFOUTPUT
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bool "OTG SOF output"
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@@ -623,7 +623,6 @@ void stm32_stdclockconfig(void)
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}
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#endif
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#define CONFIG_STM32H7_HSI48
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#ifdef CONFIG_STM32H7_HSI48
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/* Enable HSI48 */
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@@ -638,6 +637,20 @@ void stm32_stdclockconfig(void)
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}
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#endif
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#ifdef CONFIG_STM32H7_CSI
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/* Enable CSI */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_CSION;
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the CSI is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_CSIRDY) == 0)
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{
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}
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#endif
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/* Check for a timeout. If this timeout occurs, then we are hosed. We
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* have no real back-up plan, although the following logic makes it look
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* as though we do.
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@@ -637,7 +637,6 @@ void stm32_stdclockconfig(void)
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}
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#endif
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#define CONFIG_STM32H7_HSI48
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#ifdef CONFIG_STM32H7_HSI48
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/* Enable HSI48 */
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@@ -652,6 +651,20 @@ void stm32_stdclockconfig(void)
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}
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#endif
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#ifdef CONFIG_STM32H7_CSI
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/* Enable CSI */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_CSION;
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the CSI is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_CSIRDY) == 0)
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{
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}
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#endif
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/* Check for a timeout. If this timeout occurs, then we are hosed. We
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* have no real back-up plan, although the following logic makes it look
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* as though we do.
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