diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index d84a2e843c7..7ac7bf552b4 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -410,6 +410,14 @@ config STM32H7_RTC
 	default n
 	select RTC
 
+config STM32H7_CSI
+	bool "CSI Low-speed internal oscillator (4MHz)"
+	default n
+
+config STM32H7_HSI48
+	bool "HSI48 High-speed 48MHz internal oscillator"
+	default n
+
 config STM32H7_PWR
 	bool "PWR"
 	default n
@@ -493,12 +501,14 @@ config STM32H7_OTGFS
 	bool "OTG FS"
 	default n
 	select USBHOST_HAVE_ASYNCH if USBHOST
+	select STM32H7_HSI48
 
 config STM32H7_OTGHS
 	bool "OTG HS"
 	default n
 	depends on EXPERIMENTAL
 	select USBHOST_HAVE_ASYNCH if USBHOST
+	select STM32H7_HSI48
 
 config STM32H7_OTG_SOFOUTPUT
 	bool "OTG SOF output"
diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
index bf682f4bad6..d416f165ebf 100644
--- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
@@ -623,7 +623,6 @@ void stm32_stdclockconfig(void)
     }
 #endif
 
-#define CONFIG_STM32H7_HSI48
 #ifdef CONFIG_STM32H7_HSI48
   /* Enable HSI48 */
 
@@ -638,6 +637,20 @@ void stm32_stdclockconfig(void)
     }
 #endif
 
+#ifdef CONFIG_STM32H7_CSI
+  /* Enable CSI */
+
+  regval  = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_CSION;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the CSI is ready */
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_CSIRDY) == 0)
+    {
+    }
+#endif
+
   /* Check for a timeout.  If this timeout occurs, then we are hosed.  We
    * have no real back-up plan, although the following logic makes it look
    * as though we do.
diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
index 9dae6a344c2..58bdee80832 100644
--- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
@@ -637,7 +637,6 @@ void stm32_stdclockconfig(void)
     }
 #endif
 
-#define CONFIG_STM32H7_HSI48
 #ifdef CONFIG_STM32H7_HSI48
   /* Enable HSI48 */
 
@@ -652,6 +651,20 @@ void stm32_stdclockconfig(void)
     }
 #endif
 
+#ifdef CONFIG_STM32H7_CSI
+  /* Enable CSI */
+
+  regval  = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_CSION;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the CSI is ready */
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_CSIRDY) == 0)
+    {
+    }
+#endif
+
   /* Check for a timeout.  If this timeout occurs, then we are hosed.  We
    * have no real back-up plan, although the following logic makes it look
    * as though we do.