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arch/mips/*: Run nxstyle on the arch/mips directory.

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This commit is contained in:
Ouss4
2019-12-08 08:09:11 -06:00
committed by Gregory Nutt
parent c9b4da61b0
commit 47129b36bd
32 changed files with 699 additions and 527 deletions
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arch/mips/include/mips32/cp0.h
+14 -14
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/include/mips32/cp0.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
@@ -31,21 +31,21 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_INCLUDE_MIPS32_CP0_H
#define __ARCH_MIPS_INCLUDE_MIPS32_CP0_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* CP0 Register Addresses *******************************************************************/
****************************************************************************/
/* CP0 Register Addresses ***************************************************/
#ifdef __ASSEMBLY__
# define MIPS32_CP0_INDEX1 $0,0 /* Index into the TLB array */
@@ -82,7 +82,7 @@
# define MIPS32_CP0_DESAVE3 $31,0 /* Debug handler scratchpad register */
#endif
/* CP0 Registers ****************************************************************************/
/* CP0 Registers ************************************************************/
/* Register Number: 0 Sel: 0 Name: Index
* Function: Index into the TLB array
@@ -574,19 +574,19 @@
* register.
*/
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
arch/mips/include/mips32/syscall.h
+14 -14
View File
@@ -56,11 +56,11 @@
#define SYS_syscall 0x00
/* Configuration ********************************************************************/
/* Configuration ************************************************************/
/* SYS call 1 and 2 are defined for internal use by the PIC32MX port (see
* arch/mips/include/mips32/syscall.h). In addition, SYS call 3 is the return from
* a SYS call in kernel mode. The first four syscall values must, therefore, be
* reserved (0 is not used).
* arch/mips/include/mips32/syscall.h). In addition, SYS call 3 is the
* return from a SYS call in kernel mode. The first four syscall values must,
* therefore, be reserved (0 is not used).
*/
#ifdef CONFIG_BUILD_KERNEL
@@ -71,16 +71,16 @@
# endif
#endif
/* sys_call macros ******************************************************************/
/* System calls with 3 parameters and fewer are handled by sys_call0 (sys_call1,
* sys_call2, and sys_call3 are aliases for sys_call0). This is because the
* parmeters are passed in a0-a3. a0 is reserved for the syscall number leaving
* up to thre additional parameters that can be passed in registers. The remainder
* would have to be pushed onto the stack.
/* sys_call macros **********************************************************/
/* System calls with 3 parameters and fewer are handled by sys_call0
* (sys_call1, sys_call2, and sys_call3 are aliases for sys_call0).
* This is because the parmeters are passed in a0-a3. a0 is reserved for
* the syscall number leaving up to three additional parameters that can be
* passed in registers. The remainder would have to be pushed onto the stack.
*
* Instead, these macros are provided which handle parameters four, five and six in
* a non-standard way: The use s0 ($7), s1 ($8), and s2 ($9) to pass the additional
* parameters.
* Instead, these macros are provided which handle parameters four, five and
* six in a non-standard way: The use s0 ($7), s1 ($8), and s2 ($9) to pass
* the additional parameters.
*/
#ifndef __ASSEMBLY__
@@ -148,7 +148,7 @@
__result; \
})
/* Context switching system calls ***************************************************/
/* Context switching system calls *******************************************/
/* SYS call 0: (not used) */
arch/mips/src/common/up_createstack.c
+1 -1
View File
@@ -210,5 +210,5 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
return OK;
}
return ERROR;
return ERROR;
}
arch/mips/src/common/up_initialize.c
+2 -2
View File
@@ -113,8 +113,8 @@ void up_initialize(void)
#endif
#ifdef CONFIG_ARCH_DMA
/* Initialize the DMA subsystem if the weak function up_dma_initialize has been
* brought into the build
/* Initialize the DMA subsystem if the weak function up_dma_initialize has
* been brought into the build.
*/
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
arch/mips/src/common/up_internal.h
+3 -3
View File
@@ -128,9 +128,9 @@ extern uint32_t g_idle_topstack;
extern void g_intstackbase;
#endif
/* These 'addresses' of these values are setup by the linker script. They are
* not actual uint32_t storage locations! They are only used meaningfully in the
* following way:
/* These 'addresses' of these values are setup by the linker script. They are
* not actual uint32_t storage locations! They are only used meaningfully in
* the following way:
*
* - The linker script defines, for example, the symbol_sdata.
* - The declaration extern uint32_t _sdata; makes C happy. C will believe
arch/mips/src/common/up_interruptcontext.c
+1 -1
View File
@@ -66,5 +66,5 @@
bool up_interrupt_context(void)
{
return g_current_regs != NULL;
return g_current_regs != NULL;
}
arch/mips/src/common/up_udelay.c
+4
View File
@@ -100,6 +100,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++)
{
}
microseconds -= 1000;
}
@@ -108,6 +109,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++)
{
}
microseconds -= 100;
}
@@ -116,6 +118,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++)
{
}
microseconds -= 10;
}
@@ -124,6 +127,7 @@ void up_udelay(useconds_t microseconds)
for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++)
{
}
microseconds--;
}
}
arch/mips/src/mips32/mips32-memorymap.h
+12 -12
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/mips32/mips32-memorymap.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
@@ -31,24 +31,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H
#define __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/* MIPS32 address space organization */
@@ -72,13 +72,13 @@
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
arch/mips/src/mips32/up_assert.c
+9 -9
View File
@@ -88,19 +88,19 @@ static void _up_assert(int errorcode)
if (g_current_regs || running_task()->flink == NULL)
{
(void)up_irq_save();
for (; ; )
{
(void)up_irq_save();
for (; ; )
{
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
board_reset(CONFIG_BOARD_ASSERT_RESET_VALUE);
board_reset(CONFIG_BOARD_ASSERT_RESET_VALUE);
#endif
#ifdef CONFIG_ARCH_LEDS
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_autoled_off(LED_PANIC);
up_mdelay(250);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
}
}
else
{
arch/mips/src/mips32/up_doirq.c
+2 -2
View File
@@ -87,8 +87,8 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
DEBUGASSERT(g_current_regs == NULL);
g_current_regs = regs;
/* Disable further occurrences of this interrupt (until the interrupt sources
* have been clear by the driver).
/* Disable further occurrences of this interrupt (until the interrupt
* srouce have been cleared by the driver).
*/
up_disable_irq(irq);
arch/mips/src/mips32/up_dumpstate.c
+21 -14
View File
@@ -103,28 +103,35 @@ static inline void up_registerdump(void)
if (g_current_regs)
{
_alert("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n",
g_current_regs[REG_MFLO], g_current_regs[REG_MFHI], g_current_regs[REG_EPC],
g_current_regs[REG_STATUS]);
g_current_regs[REG_MFLO], g_current_regs[REG_MFHI],
g_current_regs[REG_EPC], g_current_regs[REG_STATUS]);
_alert("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n",
g_current_regs[REG_AT], g_current_regs[REG_V0], g_current_regs[REG_V1],
g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2],
g_current_regs[REG_AT], g_current_regs[REG_V0],
g_current_regs[REG_V1], g_current_regs[REG_A0],
g_current_regs[REG_A1], g_current_regs[REG_A2],
g_current_regs[REG_A3]);
_alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n",
g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2],
g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5],
_alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x "
"T6:%08x T7:%08x\n",
g_current_regs[REG_T0], g_current_regs[REG_T1],
g_current_regs[REG_T2], g_current_regs[REG_T3],
g_current_regs[REG_T4], g_current_regs[REG_T5],
g_current_regs[REG_T6], g_current_regs[REG_T7]);
_alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n",
g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2],
g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5],
_alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
"S6:%08x S7:%08x\n",
g_current_regs[REG_S0], g_current_regs[REG_S1],
g_current_regs[REG_S2], g_current_regs[REG_S3],
g_current_regs[REG_S4], g_current_regs[REG_S5],
g_current_regs[REG_S6], g_current_regs[REG_S7]);
#ifdef MIPS32_SAVE_GP
_alert("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n",
g_current_regs[REG_T8], g_current_regs[REG_T9], g_current_regs[REG_GP],
g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_RA]);
g_current_regs[REG_T8], g_current_regs[REG_T9],
g_current_regs[REG_GP], g_current_regs[REG_SP],
g_current_regs[REG_FP], g_current_regs[REG_RA]);
#else
_alert("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n",
g_current_regs[REG_T8], g_current_regs[REG_T9], g_current_regs[REG_SP],
g_current_regs[REG_FP], g_current_regs[REG_RA]);
g_current_regs[REG_T8], g_current_regs[REG_T9],
g_current_regs[REG_SP], g_current_regs[REG_FP],
g_current_regs[REG_RA]);
#endif
}
}
arch/mips/src/mips32/up_irq.c
+2 -2
View File
@@ -78,8 +78,8 @@ irqstate_t up_irq_save(void)
* Name: up_irq_restore
*
* Description:
* Restore the previous up_irq_enable state (i.e., the one previously returned
* by up_irq_save())
* Restore the previous up_irq_enable state (i.e., the one previously
* returned by up_irq_save())
*
* Input Parameters:
* state - The interrupt state to be restored.
arch/mips/src/mips32/up_reprioritizertr.c
+2 -2
View File
@@ -138,7 +138,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
sched_suspend_scheduler(rtcb);
/* Are we in an interrupt handler? */
/* Are we in an interrupt handler? */
if (g_current_regs)
{
@@ -146,7 +146,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* Just copy the g_current_regs into the OLD rtcb.
*/
up_savestate(rtcb->xcp.regs);
up_savestate(rtcb->xcp.regs);
/* Restore the exception context of the rtcb at the (new) head
* of the ready-to-run task list.
arch/mips/src/mips32/up_swint0.c
+20 -16
View File
@@ -103,17 +103,20 @@ static void dispatch_syscall(void)
{
# error "Missing logic"
/* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for ARM */
/* __asm__ __volatile__ */
/* ( */
/* Save registers */
/* Get the base of the stub lookup table */
/* Get the offset of the stub for this syscall */
/* Load the entry of the stub for this syscall */
/* Call the stub */
/* Restore regsisters */
/* Return from the syscall */
/* ); */
/* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for ARM */
# if 0
__asm__ __volatile__
(
Save registers
Get the base of the stub lookup table
Get the offset of the stub for this syscall
Load the entry of the stub for this syscall
Call the stub
Restore regsisters
Return from the syscall
);
# endif
}
#endif
@@ -153,17 +156,18 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
{
/* R4=SYS_restore_context: This a restore context command:
*
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
* At this point, the following values are saved in context:
*
* R4 = SYS_restore_context
* R5 = restoreregs
*
* In this case, we simply need to set g_current_regs to restore register
* area referenced in the saved R1. context == g_current_regs is the normal
* exception return. By setting g_current_regs = context[R1], we force
* the return to the saved context referenced in R1.
* In this case, we simply need to set g_current_regs to restore the
* register area referenced in the saved R1. context == g_current_regs
* is the normal exception return. By setting g_current_regs equals to
* context[R1], we force the return to the saved context referenced
* in R1.
*/
case SYS_restore_context:
arch/mips/src/mips32/up_vfork.c
+2 -2
View File
@@ -84,8 +84,8 @@
* 1) User code calls vfork(). vfork() collects context information and
* transfers control up up_vfork().
* 2) up_vfork()and calls nxtask_vforksetup().
* 3) nxtask_vforksetup() allocates and configures the child task's TCB. This
* consists of:
* 3) nxtask_vforksetup() allocates and configures the child task's TCB.
* this consists of:
* - Allocation of the child task's TCB.
* - Initialization of file descriptors and streams
* - Configuration of environment variables
arch/mips/src/pic32mx/pic32mx-ethernet.c
+120 -91
View File
File diff suppressed because it is too large Load Diff
arch/mips/src/pic32mx/pic32mx-exception.c
+2 -2
View File
@@ -59,13 +59,13 @@
* Public Functions
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: pic32mx_exception
*
* Description:
* Called from assembly language logic on all other exceptions.
*
************************************************************************************/
****************************************************************************/
uint32_t *pic32mx_exception(uint32_t *regs)
{
arch/mips/src/pic32mx/pic32mx-lowconsole.c
+24 -16
View File
@@ -174,8 +174,8 @@ static void pic32mx_uartsetbaud(uintptr_t uart_base, uint32_t baudrate)
uint32_t brg;
unsigned int mode;
/* We want the largest value of BRG divisor possible (for the best accuracy).
* Subject to BRG <= 65536.
/* We want the largest value of BRG divisor possible
* (for the best accuracy), subject to BRG <= 65536.
*/
tmp = BOARD_PBCLOCK / baudrate;
@@ -194,6 +194,7 @@ static void pic32mx_uartsetbaud(uintptr_t uart_base, uint32_t baudrate)
brg = (tmp + 8) >> 4;
mode = PIC32MX_UART_MODECLR_OFFSET;
}
DEBUGASSERT(brg <= 65536);
/* Set the BRG divisor */
@@ -236,15 +237,18 @@ void pic32mx_uartreset(uintptr_t uart_base)
#ifdef HAVE_UART_DEVICE
void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
unsigned int parity, unsigned int nbits, bool stop2)
unsigned int parity, unsigned int nbits,
bool stop2)
{
/* Clear mode and sta bits */
pic32mx_putreg(uart_base, PIC32MX_UART_MODECLR_OFFSET,
UART_MODE_STSEL | UART_MODE_PDSEL_MASK | UART_MODE_BRGH |
UART_MODE_RXINV | UART_MODE_WAKE | UART_MODE_LPBACK |
UART_MODE_UEN_MASK | UART_MODE_RTSMD | UART_MODE_IREN |
UART_MODE_SIDL | UART_MODE_ON);
UART_MODE_STSEL | UART_MODE_PDSEL_MASK |
UART_MODE_BRGH | UART_MODE_RXINV |
UART_MODE_WAKE | UART_MODE_LPBACK |
UART_MODE_UEN_MASK | UART_MODE_RTSMD |
UART_MODE_IREN | UART_MODE_SIDL |
UART_MODE_ON);
/* Configure the FIFOs:
*
@@ -252,19 +256,21 @@ void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
* TX: Interrupt on FIFO empty
* Invert transmit polarity.
*
* NOTE that there are not many options on trigger TX interrupts. The FIFO not
* full might generate better through-put but with a higher interrupt rate. FIFO
* empty should lower the interrupt rate but result in a burstier output. If
* you change this, please read the comment for acknowledging the interrupt in
* pic32mx-serial.c
* NOTE that there are not many options on trigger TX interrupts.
* The FIFO not full might generate better through-put but with a higher
* interrupt rate. FIFO empty should lower the interrupt rate but result
* in a burstier output. If you change this, please read the comment for
* acknowledging the interrupt in pic32mx-serial.c
*/
#ifdef UART_STA_URXISEL_RXB6
pic32mx_putreg(uart_base, PIC32MX_UART_STACLR_OFFSET,
UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | UART_STA_URXISEL_RXB6);
UART_STA_UTXINV | UART_STA_UTXISEL_TXBE |
UART_STA_URXISEL_RXB6);
#else
pic32mx_putreg(uart_base, PIC32MX_UART_STACLR_OFFSET,
UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | UART_STA_URXISEL_RXB3);
UART_STA_UTXINV | UART_STA_UTXISEL_TXBE |
UART_STA_URXISEL_RXB3);
#endif
/* Configure the FIFO interrupts */
@@ -348,11 +354,13 @@ void up_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE
/* Wait for the transmit buffer not full */
while ((pic32mx_getreg(PIC32MX_CONSOLE_BASE, PIC32MX_UART_STA_OFFSET) & UART_STA_UTXBF) != 0);
while ((pic32mx_getreg(PIC32MX_CONSOLE_BASE, PIC32MX_UART_STA_OFFSET) &
UART_STA_UTXBF) != 0);
/* Then write the character to the TX data register */
pic32mx_putreg(PIC32MX_CONSOLE_BASE, PIC32MX_UART_TXREG_OFFSET, (uint32_t)ch);
pic32mx_putreg(PIC32MX_CONSOLE_BASE, PIC32MX_UART_TXREG_OFFSET,
(uint32_t)ch);
#endif
}
arch/mips/src/pic32mx/pic32mx-lowinit.c
-1
View File
@@ -212,4 +212,3 @@ void pic32mx_lowinit(void)
pic32mx_boardinitialize();
}
arch/mips/src/pic32mx/pic32mx-serial.c
+30 -21
View File
@@ -163,7 +163,8 @@ struct up_dev_s
/* Low-level helpers */
static inline uint32_t up_serialin(struct up_dev_s *priv, int offset);
static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value);
static inline void up_serialout(struct up_dev_s *priv, int offset,
uint32_t value);
static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im);
static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im);
@@ -245,7 +246,7 @@ static uart_dev_t g_uart1port =
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart1priv,
};
@@ -279,7 +280,7 @@ static uart_dev_t g_uart2port =
{
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart2priv,
};
@@ -302,7 +303,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
* Name: up_serialout
****************************************************************************/
static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
static inline void up_serialout(struct up_dev_s *priv, int offset,
uint32_t value)
{
putreg32(value, priv->uartbase + offset);
}
@@ -334,9 +336,10 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im)
flags = enter_critical_section();
if (im)
{
*im = priv->im;
}
{
*im = priv->im;
}
up_restoreuartint(dev, 0);
leave_critical_section(flags);
}
@@ -403,7 +406,8 @@ static void up_shutdown(struct uart_dev_s *dev)
*
* RX and TX interrupts are not enabled by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* interrupts are not enabled until the txint() and rxint() methods are
* called.
*
****************************************************************************/
@@ -474,18 +478,19 @@ static int up_interrupt(int irq, void *context, void *arg)
* following error conditions take place:
* - Parity error PERR (UxSTA bit 3) is detected
* - Framing Error FERR (UxSTA bit 2) is detected
* - Overflow condition for the receive buffer OERR (UxSTA bit 1) occurs
* - Overflow condition for the receive buffer OERR (UxSTA bit 1)
* occurs.
*/
#ifdef CONFIG_DEBUG_FEATURES
if (up_pending_irq(priv->irqe))
{
/* Clear the pending error interrupt */
/* Clear the pending error interrupt */
up_clrpend_irq(priv->irqe);
_err("ERROR: interrupt STA: %08x\n",
up_serialin(priv, PIC32MX_UART_STA_OFFSET));
handled = true;
up_clrpend_irq(priv->irqe);
_err("ERROR: interrupt STA: %08x\n",
up_serialin(priv, PIC32MX_UART_STA_OFFSET));
handled = true;
}
#endif
@@ -509,7 +514,8 @@ static int up_interrupt(int irq, void *context, void *arg)
* longer has space to buffer the serial data.
*/
if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & UART_STA_URXDA) == 0)
if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) &
UART_STA_URXDA) == 0)
{
up_clrpend_irq(priv->irqrx);
}
@@ -518,8 +524,8 @@ static int up_interrupt(int irq, void *context, void *arg)
/* Handle outgoing, transmit bytes The RT FIFO is configured to
* interrupt only when the TX FIFO is empty. There are not many
* options on trigger TX interrupts. The FIFO-not-full might generate
* better through-put but with a higher interrupt rate. FIFO-empty should
* lower the interrupt rate but result in a burstier output. If
* better through-put but with a higher interrupt rate. FIFO-empty
* should lower the interrupt rate but result in a burstier output. If
* you change this, You will probably need to change the conditions for
* clearing the pending TX interrupt below.
*
@@ -545,7 +551,8 @@ static int up_interrupt(int irq, void *context, void *arg)
* to be sent.
*/
if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & UART_STA_UTRMT) != 0)
if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) &
UART_STA_UTRMT) != 0)
{
up_clrpend_irq(priv->irqtx);
}
@@ -657,7 +664,8 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
/* Then return the actual received byte */
return (int)(up_serialin(priv, PIC32MX_UART_RXREG_OFFSET) & UART_RXREG_MASK);
return (int)(up_serialin(priv, PIC32MX_UART_RXREG_OFFSET) &
UART_RXREG_MASK);
}
/****************************************************************************
@@ -678,8 +686,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
im = priv->im;
if (enable)
{
/* Receive an interrupt when their is anything in the Rx data register (or an Rx
* timeout occurs).
/* Receive an interrupt when their is anything in the Rx data register
* (or an Rx timeout occurs).
*/
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
@@ -698,6 +706,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
up_disable_irq(priv->irqrx);
DISABLE_RX(im);
}
priv->im = im;
leave_critical_section(flags);
}
arch/mips/src/pic32mx/pic32mx-spi.c
+78 -50
View File
@@ -108,19 +108,21 @@ static void spi_putreg(FAR struct pic32mx_dev_s *priv,
/* SPI methods */
static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t frequency);
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits);
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch);
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
static void spi_sndblock(FAR struct spi_dev_s *dev,
FAR const void *buffer, size_t nwords);
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
size_t nwords);
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_PIC32MX_SPI1
static const struct spi_ops_s g_spi1ops =
{
.lock = spi_lock,
@@ -147,7 +149,10 @@ static const struct spi_ops_s g_spi1ops =
static struct pic32mx_dev_s g_spi1dev =
{
.spidev = { &g_spi1ops },
.spidev =
{
&g_spi1ops
},
.base = PIC32MX_SPI1_K1BASE,
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
.vector = PIC32MX_IRQ_SPI1,
@@ -182,7 +187,10 @@ static const struct spi_ops_s g_spi2ops =
static struct pic32mx_dev_s g_spi2dev =
{
.spidev = { &g_spi2ops },
.spidev =
{
&g_spi2ops
},
.base = PIC32MX_SPI2_K1BASE,
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
.vector = PIC32MX_IRQ_SPI2,
@@ -217,7 +225,10 @@ static const struct spi_ops_s g_spi3ops =
static struct pic32mx_dev_s g_spi3dev =
{
.spidev = { &g_spi3ops },
.spidev =
{
&g_spi3ops
},
.base = PIC32MX_SPI3_K1BASE,
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
.vector = PIC32MX_IRQ_SPI4,
@@ -252,7 +263,10 @@ static const struct spi_ops_s g_spi4ops =
static struct pic32mx_dev_s g_spi4dev =
{
.spidev = { &g_spi4ops },
.spidev =
{
&g_spi4ops
},
.base = PIC32MX_SPI4_K1BASE,
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
.vector = PIC32MX_IRQ_SPI4,
@@ -287,7 +301,8 @@ static struct pic32mx_dev_s g_spi4dev =
****************************************************************************/
#ifdef CONFIG_PIC32MX_SPI_REGDEBUG
static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv,
unsigned int offset)
{
/* Last address, value, and count */
@@ -313,10 +328,11 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
_info("...\n");
}
if (count == 4)
{
_info("...\n");
}
return value;
}
}
@@ -325,20 +341,20 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
else
{
/* Did we print "..." for the previous value? */
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
_info("[repeats %d more times]\n", count-3);
}
_info("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
/* Save the new address, value, and count */
prevaddr = addr;
prevalue = value;
count = 1;
prevaddr = addr;
prevalue = value;
count = 1;
}
/* Show the register value read */
@@ -347,7 +363,8 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
return value;
}
#else
static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset)
static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv,
unsigned int offset)
{
return getreg32(priv->base + offset);
}
@@ -461,7 +478,8 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
*
****************************************************************************/
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t frequency)
{
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
uint32_t divisor;
@@ -732,14 +750,16 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
* nwords - the length of data to send from the buffer in number of words.
* The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
* packed into uint8_t's; if nbits >8, the data is packed into
* uint16_t's
*
* Returned Value:
* None
*
****************************************************************************/
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
size_t nwords)
{
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
@@ -760,20 +780,23 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
* receive buffer is not empty.
*/
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPIRBE) != 0);
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) &
SPI_STAT_SPIRBE) != 0);
#else
/* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. In
* normal mode, the SPIRBF bit will be set when receive data is available.
/* Wait for the SPIRBF bit in the SPI Status Register to be set to 1.
* In normal mode, the SPIRBF bit will be set when receive data is
* available.
*/
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) == 0);
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) &
SPI_STAT_SPIRBF) == 0);
#endif
/* Read from the buffer register to clear the status bit */
/* Read from the buffer register to clear the status bit */
regval = spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET);
UNUSED(regval);
nwords--;
regval = spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET);
UNUSED(regval);
nwords--;
}
}
@@ -787,16 +810,18 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
* dev - Device-specific state data
* buffer - A pointer to the buffer in which to receive data
* nwords - the length of data that can be received in the buffer in number
* of words. The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
* of words. The wordsize is determined by the number of
* bits-per-word selected for the SPI interface. If nbits <= 8,
* the data is packed into uint8_t's; if nbits > 8, the data is
* packed into uint16_t's
*
* Returned Value:
* None
*
****************************************************************************/
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
size_t nwords)
{
FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev;
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
@@ -816,19 +841,22 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
* receive buffer is not empty.
*/
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPIRBE) != 0);
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) &
SPI_STAT_SPIRBE) != 0);
#else
/* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. In
* normal mode, the SPIRBF bit will be set when receive data is available.
/* Wait for the SPIRBF bit in the SPI Status Register to be set to 1.
* In normal mode, the SPIRBF bit will be set when receive data is
* available.
*/
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) == 0);
while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) &
SPI_STAT_SPIRBF) == 0);
#endif
/* Read the received data from the SPI Data Register */
/* Read the received data from the SPI Data Register */
*ptr++ = (uint8_t)spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET);
nwords--;
*ptr++ = (uint8_t)spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET);
nwords--;
}
}
@@ -888,10 +916,10 @@ FAR struct spi_dev_s *pic32mx_spibus_initialize(int port)
}
else
#endif
{
spierr("ERROR: Unsupported port: %d\n", port);
return NULL;
}
{
spierr("ERROR: Unsupported port: %d\n", port);
return NULL;
}
/* Disable SPI interrupts */
arch/mips/src/pic32mx/pic32mx-timerisr.c
+1 -1
View File
@@ -171,7 +171,7 @@ void mips_timer_initialize(void)
putreg32((TIMER1_CON_TCKPS | TIMER1_CON_TCS), PIC32MX_TIMER1_CON);
putreg32(0, PIC32MX_TIMER1_CNT);
putreg32(TIMER1_MATCH-1, PIC32MX_TIMER1_PR);
putreg32(TIMER1_MATCH - 1, PIC32MX_TIMER1_PR);
putreg32(TIMER_CON_ON, PIC32MX_TIMER1_CONSET);
/* Configure the timer interrupt */
arch/mips/src/pic32mz/pic32mz-dma.c
+2 -2
View File
@@ -902,7 +902,7 @@ void pic32mz_dma_free(DMA_HANDLE handle)
up_clrpend_irq(dmach->irq);
}
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_chcfg
*
* Description:
@@ -910,7 +910,7 @@ void pic32mz_dma_free(DMA_HANDLE handle)
* This config can be done during alloc, however if reconfig is needed,
* this functions should be used.
*
******************************************************************************/
****************************************************************************/
int pic32mz_dma_chcfg(DMA_HANDLE handle,
FAR const struct pic32mz_dma_chcfg_s *cfg)
arch/mips/src/pic32mz/pic32mz-ethernet.c
+103 -73
View File
@@ -179,8 +179,8 @@
/* Debug Configuration *****************************************************/
/* Register/Descriptor debug -- can only happen of CONFIG_DEBUG_FEATURES is selected.
* This will probably generate much more output than you care to see.
/* Register/Descriptor debug -- can only happen of CONFIG_DEBUG_FEATURES is
* selecte. This will probably generate much more output than you care to see.
*/
#ifndef CONFIG_DEBUG_FEATURES
@@ -363,8 +363,8 @@ union pic32mz_rxdesc_u
struct pic32mz_rxdesc_s rxdesc;
};
/* The pic32mz_driver_s encapsulates all state information for a single hardware
* interface
/* The pic32mz_driver_s encapsulates all state information for a single
* single interface
*/
struct pic32mz_driver_s
@@ -438,8 +438,10 @@ static void pic32mz_putreg(uint32_t val, uint32_t addr);
/* Buffer and descriptor management */
#ifdef CONFIG_NET_DESCDEBUG
static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg);
static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, const char *msg);
static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc,
const char *msg);
static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc,
const char *msg);
#else
# define pic32mz_dumptxdesc(txdesc,msg)
# define pic32mz_dumprxdesc(rxdesc,msg)
@@ -447,11 +449,13 @@ static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, const char *msg)
static inline void pic32mz_bufferinit(struct pic32mz_driver_s *priv);
static uint8_t *pic32mz_allocbuffer(struct pic32mz_driver_s *priv);
static void pic32mz_freebuffer(struct pic32mz_driver_s *priv, uint8_t *buffer);
static void pic32mz_freebuffer(struct pic32mz_driver_s *priv,
uint8_t *buffer);
static inline void pic32mz_txdescinit(struct pic32mz_driver_s *priv);
static inline void pic32mz_rxdescinit(struct pic32mz_driver_s *priv);
static inline struct pic32mz_txdesc_s *pic32mz_txdesc(struct pic32mz_driver_s *priv);
static inline struct pic32mz_txdesc_s *
pic32mz_txdesc(struct pic32mz_driver_s *priv);
static inline void pic32mz_txnext(struct pic32mz_driver_s *priv);
static inline void pic32mz_rxreturn(struct pic32mz_rxdesc_s *rxdesc);
static struct pic32mz_rxdesc_s *pic32mz_rxdesc(struct pic32mz_driver_s *priv);
@@ -556,8 +560,8 @@ static void pic32mz_checkreg(uint32_t addr, uint32_t val, bool iswrite)
static uint32_t count = 0;
static bool prevwrite = false;
/* Is this the same value that we read from/wrote to the same register last time?
* Are we polling the register? If so, suppress the output.
/* Is this the same value that we read from/wrote to the same register
* last time? Are we polling the register? If so, suppress the output.
*/
if (addr == prevaddr && val == preval && prevwrite == iswrite)
@@ -663,14 +667,17 @@ static void pic32mz_putreg(uint32_t val, uint32_t addr)
****************************************************************************/
#ifdef CONFIG_NET_DESCDEBUG
static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg)
static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc,
const char *msg)
{
ninfo("TX Descriptor [%p]: %s\n", txdesc, msg);
ninfo(" status: %08x\n", txdesc->status);
ninfo(" address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address));
ninfo(" address: %08x [%08x]\n",
txdesc->address, VIRT_ADDR(txdesc->address));
ninfo(" tsv1: %08x\n", txdesc->tsv1);
ninfo(" tsv2: %08x\n", txdesc->tsv2);
ninfo(" nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted));
ninfo(" nexted: %08x [%08x]\n",
txdesc->nexted, VIRT_ADDR(txdesc->nexted));
}
#endif
@@ -690,14 +697,17 @@ static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg)
****************************************************************************/
#ifdef CONFIG_NET_DESCDEBUG
static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, const char *msg)
static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc,
const char *msg)
{
ninfo("RX Descriptor [%p]: %s\n", rxdesc, msg);
ninfo(" status: %08x\n", rxdesc->status);
ninfo(" address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address));
ninfo(" address: %08x [%08x]\n",
rxdesc->address, VIRT_ADDR(rxdesc->address));
ninfo(" rsv1: %08x\n", rxdesc->rsv1);
ninfo(" rsv2: %08x\n", rxdesc->rsv2);
ninfo(" nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted));
ninfo(" nexted: %08x [%08x]\n",
rxdesc->nexted, VIRT_ADDR(rxdesc->nexted));
}
#endif
@@ -835,7 +845,8 @@ static inline void pic32mz_txdescinit(struct pic32mz_driver_s *priv)
up_flush_dcache((uintptr_t)g_txdesc,
(uintptr_t)g_txdesc +
CONFIG_PIC32MZ_ETH_NTXDESC * sizeof(union pic32mz_txdesc_u));
CONFIG_PIC32MZ_ETH_NTXDESC *
sizeof(union pic32mz_txdesc_u));
/* Position the Tx index to the first descriptor in the ring */
@@ -912,7 +923,8 @@ static inline void pic32mz_rxdescinit(struct pic32mz_driver_s *priv)
up_flush_dcache((uintptr_t)g_rxdesc,
(uintptr_t)g_rxdesc +
CONFIG_PIC32MZ_ETH_NRXDESC * sizeof(union pic32mz_rxdesc_u));
CONFIG_PIC32MZ_ETH_NRXDESC *
sizeof(union pic32mz_rxdesc_u));
/* Update the ETHRXST register with the physical address of the head of the
* RX descriptors list.
@@ -936,7 +948,8 @@ static inline void pic32mz_rxdescinit(struct pic32mz_driver_s *priv)
*
****************************************************************************/
static inline struct pic32mz_txdesc_s *pic32mz_txdesc(struct pic32mz_driver_s *priv)
static inline struct pic32mz_txdesc_s *
pic32mz_txdesc(struct pic32mz_driver_s *priv)
{
struct pic32mz_txdesc_s *txdesc;
@@ -1067,8 +1080,8 @@ static struct pic32mz_rxdesc_s *pic32mz_rxdesc(struct pic32mz_driver_s *priv)
/* Inspect the list of RX descriptors to see if the EOWN bit is cleared.
* If it is, this descriptor is now under software control and a message was
* received. Use SOP and EOP to extract the message, use BYTE_COUNT, RXF_RSV,
* RSV and PKT_CHECKSUM to get the message characteristics.
* received. Use SOP and EOP to extract the message, use BYTE_COUNT,
* RXF_RSV, RSV and PKT_CHECKSUM to get the message characteristics.
*/
for (i = 0; i < CONFIG_PIC32MZ_ETH_NRXDESC; i++)
@@ -1080,7 +1093,8 @@ static struct pic32mz_rxdesc_s *pic32mz_rxdesc(struct pic32mz_driver_s *priv)
/* Forces the first RX descriptor to be re-read from physical memory */
up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(union pic32mz_rxdesc_u));
(uintptr_t)rxdesc +
sizeof(union pic32mz_rxdesc_u));
if ((rxdesc->status & RXDESC_STATUS_EOWN) == 0)
{
@@ -1131,7 +1145,8 @@ static int pic32mz_transmit(struct pic32mz_driver_s *priv)
/* Increment statistics and dump the packet (if so configured) */
NETDEV_TXPACKETS(&priv->pd_dev);
pic32mz_dumppacket("Transmit packet", priv->pd_dev.d_buf, priv->pd_dev.d_len);
pic32mz_dumppacket("Transmit packet",
priv->pd_dev.d_buf, priv->pd_dev.d_len);
/* Flush the content of the TX buffer into physical memory */
@@ -1200,8 +1215,8 @@ static int pic32mz_transmit(struct pic32mz_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
(void)wd_start(priv->pd_txtimeout, PIC32MZ_TXTIMEOUT, pic32mz_txtimeout_expiry,
1, (uint32_t)priv);
(void)wd_start(priv->pd_txtimeout, PIC32MZ_TXTIMEOUT,
pic32mz_txtimeout_expiry, 1, (uint32_t)priv);
return OK;
}
@@ -1266,8 +1281,8 @@ static int pic32mz_txpoll(struct net_driver_s *dev)
if (!devif_loopback(&priv->pd_dev))
{
/* Send this packet. In this context, we know that there is space for
* at least one more packet in the descriptor list.
/* Send this packet. In this context, we know that there is space
* for at least one more packet in the descriptor list.
*/
pic32mz_transmit(priv);
@@ -1401,7 +1416,7 @@ static void pic32mz_timerpoll(struct pic32mz_driver_s *priv)
*
* Description:
* While processing an RxDone event, higher logic decides to send a packet,
* possibly a response to the incoming packet (but probably not, in reality).
* possibly a response to the incoming packet (but probably not, in reality)
* However, since the Rx and Tx operations are decoupled, there is no
* guarantee that there will be a Tx descriptor available at that time.
* This function will perform that check and, if no Tx descriptor is
@@ -1508,8 +1523,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv)
pic32mz_rxreturn(rxdesc);
}
/* If the packet length is greater then the buffer, then we cannot accept
* the packet. Also, since the DMA packet buffers are set up to
/* If the packet length is greater then the buffer, then we cannot
* accept the packet. Also, since the DMA packet buffers are set up to
* be the same size as our max packet size, any fragments also
* imply that the packet is too big.
*/
@@ -1732,9 +1747,9 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv)
DEBUGASSERT(pic32mz_txdesc(priv) != NULL);
/* Inspect the list of TX descriptors to see if the EOWN bit is cleared. If it
* is, this descriptor is now under software control and the message was
* transmitted. Use TSV to check for the transmission result.
/* Inspect the list of TX descriptors to see if the EOWN bit is cleared.
* If it is, this descriptor is now under software control and the message
* was transmitted. Use TSV to check for the transmission result.
*/
for (i = 0; i < CONFIG_PIC32MZ_ETH_NTXDESC; i++)
@@ -1747,7 +1762,8 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv)
*/
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(union pic32mz_txdesc_u));
(uintptr_t)txdesc +
sizeof(union pic32mz_txdesc_u));
/* Check if software owns this descriptor */
@@ -1775,7 +1791,8 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv)
/* Flush the content of the modified TX descriptor. */
up_flush_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(union pic32mz_txdesc_u));
(uintptr_t)txdesc +
sizeof(union pic32mz_txdesc_u));
}
}
}
@@ -1881,9 +1898,9 @@ static void pic32mz_interrupt_work(void *arg)
/* Receive Normal Events **********************************************/
/* RXACT: Receive Activity Interrupt. This bit is set whenever RX packet
* data is stored in the RXBM FIFO. It is cleared by either a Reset or CPU
* write of a '1' to the CLR register.
/* RXACT: Receive Activity Interrupt. This bit is set whenever RX
* packet data is stored in the RXBM FIFO. It is cleared by either
* a Reset or CPU write of a '1' to the CLR register.
*/
/* PKTPEND: Packet Pending Interrupt. This bit is set when the BUFCNT
@@ -1892,9 +1909,9 @@ static void pic32mz_interrupt_work(void *arg)
* Writing a '0' or a '1' has no effect.
*/
/* RXDONE: Receive Done Interrupt. This bit is set whenever an RX packet
* is successfully received. It is cleared by either a Reset or CPU
* write of a '1' to the CLR register.
/* RXDONE: Receive Done Interrupt. This bit is set whenever an RX
* packet is successfully received. It is cleared by either a Reset
* or CPU write of a '1' to the CLR register.
*/
if ((status & ETH_INT_RXDONE) != 0)
@@ -2080,8 +2097,8 @@ static void pic32mz_txtimeout_work(void *arg)
(void)pic32mz_ifup(&priv->pd_dev);
/* Then poll the network for new XMIT data (We are guaranteed to have a free
* buffer here).
/* Then poll the network for new XMIT data (We are guaranteed to have
* a free buffer here).
*/
pic32mz_poll(priv);
@@ -2242,7 +2259,7 @@ static int pic32mz_ifup(struct net_driver_s *dev)
/* Pin Configuration:
*
* No GPIO pin configuration is required. Enabling the Ethernet Controller
* will configure the I/O pin direction as defined by the Ethernet Controller
* will configure the IO pin direction as defined by the Ethernet Controller
* control bits. The port TRIS and LATCH registers will be overridden.
*
* I/O Pin MII RMII Pin Description
@@ -2345,14 +2362,16 @@ static int pic32mz_ifup(struct net_driver_s *dev)
/* Use EMAC1IPGR for setting the non back-to-back inter-packet gap */
pic32mz_putreg(((12 << EMAC1_IPGR_GAP1_SHIFT) | (12 << EMAC1_IPGR_GAP2_SHIFT)),
pic32mz_putreg(((12 << EMAC1_IPGR_GAP1_SHIFT) |
(12 << EMAC1_IPGR_GAP2_SHIFT)),
PIC32MZ_EMAC1_IPGR);
/* Set the collision window and the maximum number of retransmissions in
* EMAC1CLRT.
*/
pic32mz_putreg(((15 << EMAC1_CLRT_RETX_SHIFT) | (55 << EMAC1_CLRT_CWINDOW_SHIFT)),
pic32mz_putreg(((15 << EMAC1_CLRT_RETX_SHIFT) |
(55 << EMAC1_CLRT_CWINDOW_SHIFT)),
PIC32MZ_EMAC1_CLRT);
/* Set the maximum frame length in EMAC1MAXF. "This field resets to
@@ -2384,20 +2403,26 @@ static int pic32mz_ifup(struct net_driver_s *dev)
#else
regval = pic32mz_getreg(PIC32MZ_EMAC1_SA0);
priv->pd_dev.d_mac.ether.ether_addr_octet[4] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[5] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[5] = (uint32_t)((regval >> 8) &
0xff);
regval = pic32mz_getreg(PIC32MZ_EMAC1_SA1);
priv->pd_dev.d_mac.ether.ether_addr_octet[2] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[3] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[3] = (uint32_t)((regval >> 8) &
0xff);
regval = pic32mz_getreg(PIC32MZ_EMAC1_SA2);
priv->pd_dev.d_mac.ether.ether_addr_octet[0] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[1] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[1] = (uint32_t)((regval >> 8) &
0xff);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
#endif
/* Continue Ethernet Controller Initialization ****************************/
@@ -2415,8 +2440,8 @@ static int pic32mz_ifup(struct net_driver_s *dev)
/* Set the RX filters by updating the ETHHT0, ETHHT1, ETHPMM0, ETHPMM1,
* ETHPMCS and ETHRXFC registers.
*
* Set up RX filter and configure to accept broadcast addresses and multicast
* addresses (if so configured). NOTE: There is a selection
* Set up RX filter and configure to accept broadcast addresses and
* multicast addresses (if so configured). NOTE: There is a selection
* CONFIG_NET_BROADCAST, but this enables receipt of UDP broadcast packets
* inside of the stack.
*/
@@ -2472,13 +2497,13 @@ static int pic32mz_ifup(struct net_driver_s *dev)
pic32mz_putreg(0xffffffff, PIC32MZ_ETH_IRQCLR);
/* Configure interrupts. The Ethernet interrupt was attached during one-time
* initialization, so we only need to set the interrupt priority, configure
* interrupts, and enable them.
/* Configure interrupts. The Ethernet interrupt was attached during
* one-time initialization, so we only need to set the interrupt priority,
* configure interrupts, and enable them.
*/
/* If the user provided an interrupt priority, then set the interrupt to that
* priority
/* If the user provided an interrupt priority, then set the interrupt
* to that priority.
*/
#if defined(CONFIG_PIC32MZ_ETH_PRIORITY) && defined(CONFIG_ARCH_IRQPRIO)
@@ -2588,8 +2613,8 @@ static void pic32mz_txavail_work(void *arg)
if (pic32mz_txdesc(priv) != NULL)
{
/* If so, then poll the network for new XMIT data. First allocate a buffer
* to perform the poll
/* If so, then poll the network for new XMIT data.
* First allocate a buffer to perform the poll
*/
pic32mz_poll(priv);
@@ -2671,8 +2696,8 @@ static int pic32mz_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Function: pic32mz_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering.
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@@ -2768,7 +2793,8 @@ static void pic32mz_phybusywait(void)
****************************************************************************/
#ifdef PIC32MZ_HAVE_PHY
static void pic32mz_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata)
static void pic32mz_phywrite(uint8_t phyaddr, uint8_t regaddr,
uint16_t phydata)
{
uint32_t regval;
@@ -3064,8 +3090,9 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv)
#ifdef CONFIG_ETH0_PHY_DP83848C
/* The RMII/MII of operation can be selected by strap options or register
* control (using the RBR register). For RMII mode, it is required to use the
* strap option, since it requires a 50 MHz clock instead of the normal 25 MHz.
* control (using the RBR register). For RMII mode, it is required to use
* the strap option, since it requires a 50 MHz clock instead of the normal
* 25 Mhz.
*/
#endif
@@ -3366,8 +3393,8 @@ static void pic32mz_macmode(uint8_t mode)
/* Set MAC to operate in full duplex mode with CRC and Pad enabled */
pic32mz_putreg((EMAC1_CFG2_FULLDPLX | EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN),
PIC32MZ_EMAC1_CFG2SET);
pic32mz_putreg((EMAC1_CFG2_FULLDPLX | EMAC1_CFG2_CRCEN |
EMAC1_CFG2_PADCRCEN), PIC32MZ_EMAC1_CFG2SET);
}
else
{
@@ -3378,7 +3405,8 @@ static void pic32mz_macmode(uint8_t mode)
/* Set MAC to operate in half duplex mode with CRC and Pad enabled */
pic32mz_putreg(EMAC1_CFG2_FULLDPLX, PIC32MZ_EMAC1_CFG2CLR);
pic32mz_putreg((EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), PIC32MZ_EMAC1_CFG2SET);
pic32mz_putreg((EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN),
PIC32MZ_EMAC1_CFG2SET);
}
/* Set the RMII MAC speed. */
@@ -3432,7 +3460,8 @@ static void pic32mz_ethreset(struct pic32mz_driver_s *priv)
/* Turn the Ethernet Controller off: Clear the ON, RXEN and TXRTS bits */
pic32mz_putreg(ETH_CON1_RXEN | ETH_CON1_TXRTS | ETH_CON1_ON, PIC32MZ_ETH_CON1CLR);
pic32mz_putreg(ETH_CON1_RXEN | ETH_CON1_TXRTS | ETH_CON1_ON,
PIC32MZ_ETH_CON1CLR);
/* Wait activity abort by polling the ETHBUSY bit */
@@ -3473,9 +3502,10 @@ static void pic32mz_ethreset(struct pic32mz_driver_s *priv)
/* Put the MAC into the reset state */
pic32mz_putreg((EMAC1_CFG1_TXRST | EMAC1_CFG1_MCSTXRST | EMAC1_CFG1_RXRST |
EMAC1_CFG1_MCSRXRST | EMAC1_CFG1_SIMRST | EMAC1_CFG1_SOFTRST),
PIC32MZ_EMAC1_CFG1);
pic32mz_putreg((EMAC1_CFG1_TXRST | EMAC1_CFG1_MCSTXRST |
EMAC1_CFG1_RXRST | EMAC1_CFG1_MCSRXRST |
EMAC1_CFG1_SIMRST | EMAC1_CFG1_SOFTRST),
PIC32MZ_EMAC1_CFG1);
/* Take the MAC out of the reset state */
arch/mips/src/pic32mz/pic32mz-exception.c
+2 -2
View File
@@ -59,13 +59,13 @@
* Public Functions
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: pic32mz_exception
*
* Description:
* Called from assembly language logic on all other exceptions.
*
************************************************************************************/
****************************************************************************/
uint32_t *pic32mz_exception(uint32_t *regs)
{
arch/mips/src/pic32mz/pic32mz-gpioirq.c
+6 -4
View File
@@ -286,7 +286,8 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg)
{
/* Yes.. call the attached handler */
status = handler(irq, context, handlers->handler[i].arg);
status = handler(irq, context,
handlers->handler[i].arg);
/* Keep track of the status of the last handler that
* failed.
@@ -335,7 +336,8 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg)
{
/* Yes.. call the attached handler */
status = handler(irq, context, handlers->handler[i].arg);
status = handler(irq, context,
handlers->handler[i].arg);
/* Keep track of the status of the last handler that
* failed.
@@ -353,7 +355,6 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg)
putreg32(pending, base + PIC32MZ_IOPORT_CNFCLR_OFFSET);
}
}
/* Clear the pending interrupt */
@@ -599,7 +600,8 @@ void pic32mz_gpioirqenable(pinset_t pinset)
{
/* Enable edge detect. */
putreg32(IOPORT_CNCON_EDGEDETECT, base + PIC32MZ_IOPORT_CNCONSET_OFFSET);
putreg32(IOPORT_CNCON_EDGEDETECT,
base + PIC32MZ_IOPORT_CNCONSET_OFFSET);
if (pic32mz_edgemode(pinset) == GPIO_EDGE_RISING)
{
arch/mips/src/pic32mz/pic32mz-i2c.c
+146 -114
View File
File diff suppressed because it is too large Load Diff
arch/mips/src/pic32mz/pic32mz-lowconsole.c
+20 -14
View File
@@ -176,7 +176,7 @@ static void pic32mz_uartsetbaud(uintptr_t uart_base, uint32_t baudrate)
uint32_t brg;
unsigned int mode;
/* We want the largest value of BRG divisor possible (for the best accuracy).
/* We want the largest value of BRG divisor possible (for the best accuracy)
* Subject to BRG <= 65536.
*/
@@ -196,6 +196,7 @@ static void pic32mz_uartsetbaud(uintptr_t uart_base, uint32_t baudrate)
brg = (tmp + 8) >> 4;
mode = PIC32MZ_UART_MODECLR_OFFSET;
}
DEBUGASSERT(brg <= 65536);
/* Set the BRG divisor */
@@ -238,15 +239,17 @@ void pic32mz_uartreset(uintptr_t uart_base)
#ifdef HAVE_UART_DEVICE
void pic32mz_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
unsigned int parity, unsigned int nbits, bool stop2)
unsigned int parity, unsigned int nbits,
bool stop2)
{
/* Clear mode and sta bits */
pic32mz_putreg(uart_base, PIC32MZ_UART_MODECLR_OFFSET,
UART_MODE_STSEL | UART_MODE_PDSEL_MASK | UART_MODE_BRGH |
UART_MODE_RXINV | UART_MODE_WAKE | UART_MODE_LPBACK |
UART_MODE_UEN_MASK | UART_MODE_RTSMD | UART_MODE_IREN |
UART_MODE_SIDL | UART_MODE_ON);
UART_MODE_STSEL | UART_MODE_PDSEL_MASK |
UART_MODE_BRGH | UART_MODE_RXINV |
UART_MODE_WAKE | UART_MODE_LPBACK |
UART_MODE_UEN_MASK | UART_MODE_RTSMD |
UART_MODE_IREN | UART_MODE_SIDL | UART_MODE_ON);
/* Configure the FIFOs:
*
@@ -254,15 +257,16 @@ void pic32mz_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
* TX: Interrupt on FIFO empty
* Invert transmit polarity.
*
* NOTE that there are not many options on trigger TX interrupts. The FIFO not
* full might generate better through-put but with a higher interrupt rate. FIFO
* empty should lower the interrupt rate but result in a burstier output. If
* you change this, please read the comment for acknowledging the interrupt in
* pic32mz-serial.c
* NOTE that there are not many options on trigger TX interrupts.
* The FIFO not full might generate better through-put but with a higher
* interrupt rate. FIFO empty should lower the interrupt rate but result
* in a burstier output. If you change this, please read the comment for
* acknowledging the interrupt in pic32mz-serial.c
*/
pic32mz_putreg(uart_base, PIC32MZ_UART_STACLR_OFFSET,
UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | UART_STA_URXISEL_RXB75);
UART_STA_UTXINV | UART_STA_UTXISEL_TXBE |
UART_STA_URXISEL_RXB75);
/* Configure the FIFO interrupts */
@@ -482,10 +486,12 @@ void up_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE
/* Wait for the transmit buffer not full */
while ((pic32mz_getreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_STA_OFFSET) & UART_STA_UTXBF) != 0);
while ((pic32mz_getreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_STA_OFFSET) &
UART_STA_UTXBF) != 0);
/* Then write the character to the TX data register */
pic32mz_putreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_TXREG_OFFSET, (uint32_t)ch);
pic32mz_putreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_TXREG_OFFSET,
(uint32_t)ch);
#endif
}
arch/mips/src/pic32mz/pic32mz-serial.c
+34 -25
View File
@@ -265,7 +265,8 @@ struct up_dev_s
/* Low-level helpers */
static inline uint32_t up_serialin(struct up_dev_s *priv, int offset);
static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value);
static inline void up_serialout(struct up_dev_s *priv, int offset,
uint32_t value);
static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im);
static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im);
@@ -361,7 +362,7 @@ static uart_dev_t g_uart1port =
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart1priv,
};
@@ -393,7 +394,7 @@ static uart_dev_t g_uart2port =
{
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart2priv,
};
@@ -425,7 +426,7 @@ static uart_dev_t g_uart3port =
{
.size = CONFIG_UART3_TXBUFSIZE,
.buffer = g_uart3txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart3priv,
};
@@ -457,7 +458,7 @@ static uart_dev_t g_uart4port =
{
.size = CONFIG_UART4_TXBUFSIZE,
.buffer = g_uart4txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart4priv,
};
@@ -489,7 +490,7 @@ static uart_dev_t g_uart5port =
{
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart5priv,
};
@@ -521,7 +522,7 @@ static uart_dev_t g_uart6port =
{
.size = CONFIG_UART6_TXBUFSIZE,
.buffer = g_uart6txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &g_uart6priv,
};
@@ -544,7 +545,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
* Name: up_serialout
****************************************************************************/
static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
static inline void up_serialout(struct up_dev_s *priv, int offset,
uint32_t value)
{
putreg32(value, priv->uartbase + offset);
}
@@ -576,9 +578,10 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im)
flags = enter_critical_section();
if (im)
{
*im = priv->im;
}
{
*im = priv->im;
}
up_restoreuartint(dev, 0);
leave_critical_section(flags);
}
@@ -639,7 +642,8 @@ static void up_shutdown(struct uart_dev_s *dev)
*
* RX and TX interrupts are not enabled by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* interrupts are not enabled until the txint() and rxint() methods are
* called.
*
****************************************************************************/
@@ -725,18 +729,19 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
* following error conditions take place:
* - Parity error PERR (UxSTA bit 3) is detected
* - Framing Error FERR (UxSTA bit 2) is detected
* - Overflow condition for the receive buffer OERR (UxSTA bit 1) occurs
* - Overflow condition for the receive buffer OERR (UxSTA bit 1)
* occurs.
*/
#ifdef CONFIG_DEBUG_ERROR
if (up_pending_irq(priv->irqe))
{
/* Clear the pending error interrupt */
/* Clear the pending error interrupt */
up_clrpend_irq(priv->irqe);
_err("ERROR: interrupt STA: %08x\n",
up_serialin(priv, PIC32MZ_UART_STA_OFFSET));
handled = true;
up_clrpend_irq(priv->irqe);
_err("ERROR: interrupt STA: %08x\n",
up_serialin(priv, PIC32MZ_UART_STA_OFFSET));
handled = true;
}
#endif
@@ -760,7 +765,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
* longer has space to buffer the serial data.
*/
if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & UART_STA_URXDA) == 0)
if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) &
UART_STA_URXDA) == 0)
{
up_clrpend_irq(priv->irqrx);
}
@@ -769,8 +775,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
/* Handle outgoing, transmit bytes The RT FIFO is configured to
* interrupt only when the TX FIFO is empty. There are not many
* options on trigger TX interrupts. The FIFO-not-full might generate
* better through-put but with a higher interrupt rate. FIFO-empty should
* lower the interrupt rate but result in a burstier output. If
* better through-put but with a higher interrupt rate. FIFO-empty
* should lower the interrupt rate but result in a burstier output. If
* you change this, You will probably need to change the conditions for
* clearing the pending TX interrupt below.
*
@@ -796,7 +802,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
* to be sent.
*/
if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & UART_STA_UTRMT) != 0)
if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) &
UART_STA_UTRMT) != 0)
{
up_clrpend_irq(priv->irqtx);
}
@@ -908,7 +915,8 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
/* Then return the actual received byte */
return (int)(up_serialin(priv, PIC32MZ_UART_RXREG_OFFSET) & UART_RXREG_MASK);
return (int)(up_serialin(priv, PIC32MZ_UART_RXREG_OFFSET) &
UART_RXREG_MASK);
}
/****************************************************************************
@@ -929,8 +937,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
im = priv->im;
if (enable)
{
/* Receive an interrupt when their is anything in the Rx data register (or an Rx
* timeout occurs).
/* Receive an interrupt when their is anything in the Rx data register
* (or an Rx timeout occurs).
*/
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
@@ -949,6 +957,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
up_disable_irq(priv->irqrx);
DISABLE_RX(im);
}
priv->im = im;
leave_critical_section(flags);
}
arch/mips/src/pic32mz/pic32mz-spi.c
+13 -8
View File
@@ -1063,14 +1063,16 @@ static void spi_exchange8(FAR struct pic32mz_dev_s *priv,
* receive buffer is not empty.
*/
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBE) != 0);
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) &
SPI_STAT_SPIRBE) != 0);
#else
/* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. In
* normal mode, the SPIRBF bit will be set when receive data is
/* Wait for the SPIRBF bit in the SPI Status Register to be set to 1.
* In normal mode, the SPIRBF bit will be set when receive data is
* available.
*/
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) == 0);
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) &
SPI_STAT_SPIRBF) == 0);
#endif
/* Read from the buffer register to clear the status bit */
@@ -1135,13 +1137,16 @@ static void spi_exchange16(FAR struct pic32mz_dev_s *priv,
* receive buffer is not empty.
*/
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBE) != 0);
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) &
SPI_STAT_SPIRBE) != 0);
#else
/* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. In
* normal mode, the SPIRBF bit will be set when receive data is available.
/* Wait for the SPIRBF bit in the SPI Status Register to be set to 1.
* In normal mode, the SPIRBF bit will be set when receive data is
* available.
*/
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) == 0);
while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) &
SPI_STAT_SPIRBF) == 0);
#endif
/* Read from the buffer register to clear the status bit */
arch/mips/src/pic32mz/pic32mz-timer.c
+8 -8
View File
@@ -153,7 +153,8 @@ static inline void pic32mz_putreg(FAR struct pic32mz_timer_dev_s *dev,
uint16_t offset, uint32_t value);
static inline bool pic32mz_timer_mode32(FAR struct pic32mz_timer_dev_s *dev);
static inline uint32_t pic32mz_timer_oddoffset(uint32_t evenoffset);
static inline uint32_t pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev);
static inline uint32_t
pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev);
static void pic32mz_timer_stopinidle(FAR struct pic32mz_timer_dev_s *dev,
bool stop);
@@ -606,7 +607,8 @@ static inline uint32_t pic32mz_timer_oddoffset(uint32_t evenoffset)
*
****************************************************************************/
static inline uint32_t pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev)
static inline uint32_t
pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev)
{
uint32_t irq;
@@ -856,10 +858,10 @@ static void pic32mz_timer_setperiod(FAR struct pic32mz_timer_dev_s *dev,
if (pic32mz_timer_mode32(dev))
{
pic32mz_putreg(dev, PIC32MZ_TIMER_PR_OFFSET, period & 0x00000FFFF);
pic32mz_putreg(dev, PIC32MZ_TIMER_PR_OFFSET, period & 0x00000ffff);
pic32mz_putreg(dev, pic32mz_timer_oddoffset(PIC32MZ_TIMER_PR_OFFSET),
(period >> 16) & 0x00000FFFF);
(period >> 16) & 0x00000ffff);
}
else
{
@@ -898,7 +900,6 @@ static uint32_t pic32mz_timer_getcounter(FAR struct pic32mz_timer_dev_s *dev)
{
return pic32mz_getreg(dev, PIC32MZ_TIMER_CNT_OFFSET);
}
}
/****************************************************************************
@@ -919,11 +920,10 @@ static void pic32mz_timer_setcounter(FAR struct pic32mz_timer_dev_s *dev,
if (pic32mz_timer_mode32(dev))
{
pic32mz_putreg(dev, PIC32MZ_TIMER_CNT_OFFSET, count & 0x00000FFFF);
pic32mz_putreg(dev, PIC32MZ_TIMER_CNT_OFFSET, count & 0x00000ffff);
pic32mz_putreg(dev, pic32mz_timer_oddoffset(PIC32MZ_TIMER_CNT_OFFSET),
(count >> 16) & 0x00000FFFF);
(count >> 16) & 0x00000ffff);
}
else
{
arch/mips/src/pic32mz/pic32mz-timerisr.c
+1 -1
View File
@@ -170,7 +170,7 @@ void mips_timer_initialize(void)
putreg32((TIMER1_CON_TCKPS | TIMER1_CON_TCS), PIC32MZ_TIMER1_CON);
putreg32(0, PIC32MZ_TIMER1_CNT);
putreg32(TIMER1_MATCH-1, PIC32MZ_TIMER1_PR);
putreg32(TIMER1_MATCH - 1, PIC32MZ_TIMER1_PR);
putreg32(TIMER_CON_ON, PIC32MZ_TIMER1_CONSET);
/* Configure the timer interrupt */