diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h index 218305c9db6..893b1c067b9 100644 --- a/arch/mips/include/mips32/cp0.h +++ b/arch/mips/include/mips32/cp0.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/mips/include/mips32/cp0.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. @@ -31,21 +31,21 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_MIPS_INCLUDE_MIPS32_CP0_H #define __ARCH_MIPS_INCLUDE_MIPS32_CP0_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ -/* CP0 Register Addresses *******************************************************************/ + ****************************************************************************/ +/* CP0 Register Addresses ***************************************************/ #ifdef __ASSEMBLY__ # define MIPS32_CP0_INDEX1 $0,0 /* Index into the TLB array */ @@ -82,7 +82,7 @@ # define MIPS32_CP0_DESAVE3 $31,0 /* Debug handler scratchpad register */ #endif -/* CP0 Registers ****************************************************************************/ +/* CP0 Registers ************************************************************/ /* Register Number: 0 Sel: 0 Name: Index * Function: Index into the TLB array @@ -574,19 +574,19 @@ * register. */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/******************************************************************************************** +/**************************************************************************** * Inline Functions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Function Prototypes - ********************************************************************************************/ + ****************************************************************************/ #ifdef __cplusplus #define EXTERN extern "C" diff --git a/arch/mips/include/mips32/syscall.h b/arch/mips/include/mips32/syscall.h index 4661145d46e..001b223da42 100644 --- a/arch/mips/include/mips32/syscall.h +++ b/arch/mips/include/mips32/syscall.h @@ -56,11 +56,11 @@ #define SYS_syscall 0x00 -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ /* SYS call 1 and 2 are defined for internal use by the PIC32MX port (see - * arch/mips/include/mips32/syscall.h). In addition, SYS call 3 is the return from - * a SYS call in kernel mode. The first four syscall values must, therefore, be - * reserved (0 is not used). + * arch/mips/include/mips32/syscall.h). In addition, SYS call 3 is the + * return from a SYS call in kernel mode. The first four syscall values must, + * therefore, be reserved (0 is not used). */ #ifdef CONFIG_BUILD_KERNEL @@ -71,16 +71,16 @@ # endif #endif -/* sys_call macros ******************************************************************/ -/* System calls with 3 parameters and fewer are handled by sys_call0 (sys_call1, - * sys_call2, and sys_call3 are aliases for sys_call0). This is because the - * parmeters are passed in a0-a3. a0 is reserved for the syscall number leaving - * up to thre additional parameters that can be passed in registers. The remainder - * would have to be pushed onto the stack. +/* sys_call macros **********************************************************/ +/* System calls with 3 parameters and fewer are handled by sys_call0 + * (sys_call1, sys_call2, and sys_call3 are aliases for sys_call0). + * This is because the parmeters are passed in a0-a3. a0 is reserved for + * the syscall number leaving up to three additional parameters that can be + * passed in registers. The remainder would have to be pushed onto the stack. * - * Instead, these macros are provided which handle parameters four, five and six in - * a non-standard way: The use s0 ($7), s1 ($8), and s2 ($9) to pass the additional - * parameters. + * Instead, these macros are provided which handle parameters four, five and + * six in a non-standard way: The use s0 ($7), s1 ($8), and s2 ($9) to pass + * the additional parameters. */ #ifndef __ASSEMBLY__ @@ -148,7 +148,7 @@ __result; \ }) -/* Context switching system calls ***************************************************/ +/* Context switching system calls *******************************************/ /* SYS call 0: (not used) */ diff --git a/arch/mips/src/common/up_createstack.c b/arch/mips/src/common/up_createstack.c index 715bf8151e3..d15790fc2ea 100644 --- a/arch/mips/src/common/up_createstack.c +++ b/arch/mips/src/common/up_createstack.c @@ -210,5 +210,5 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) return OK; } - return ERROR; + return ERROR; } diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c index d02804fa698..006e725df80 100644 --- a/arch/mips/src/common/up_initialize.c +++ b/arch/mips/src/common/up_initialize.c @@ -113,8 +113,8 @@ void up_initialize(void) #endif #ifdef CONFIG_ARCH_DMA - /* Initialize the DMA subsystem if the weak function up_dma_initialize has been - * brought into the build + /* Initialize the DMA subsystem if the weak function up_dma_initialize has + * been brought into the build. */ #ifdef CONFIG_HAVE_WEAKFUNCTIONS diff --git a/arch/mips/src/common/up_internal.h b/arch/mips/src/common/up_internal.h index 85f0b701487..e8253c186c7 100644 --- a/arch/mips/src/common/up_internal.h +++ b/arch/mips/src/common/up_internal.h @@ -128,9 +128,9 @@ extern uint32_t g_idle_topstack; extern void g_intstackbase; #endif -/* These 'addresses' of these values are setup by the linker script. They are - * not actual uint32_t storage locations! They are only used meaningfully in the - * following way: +/* These 'addresses' of these values are setup by the linker script. They are + * not actual uint32_t storage locations! They are only used meaningfully in + * the following way: * * - The linker script defines, for example, the symbol_sdata. * - The declaration extern uint32_t _sdata; makes C happy. C will believe diff --git a/arch/mips/src/common/up_interruptcontext.c b/arch/mips/src/common/up_interruptcontext.c index 837238ec30d..581f254bcd2 100644 --- a/arch/mips/src/common/up_interruptcontext.c +++ b/arch/mips/src/common/up_interruptcontext.c @@ -66,5 +66,5 @@ bool up_interrupt_context(void) { - return g_current_regs != NULL; + return g_current_regs != NULL; } diff --git a/arch/mips/src/common/up_udelay.c b/arch/mips/src/common/up_udelay.c index 19a7fa0d6ae..cdea99e10a5 100644 --- a/arch/mips/src/common/up_udelay.c +++ b/arch/mips/src/common/up_udelay.c @@ -100,6 +100,7 @@ void up_udelay(useconds_t microseconds) for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++) { } + microseconds -= 1000; } @@ -108,6 +109,7 @@ void up_udelay(useconds_t microseconds) for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++) { } + microseconds -= 100; } @@ -116,6 +118,7 @@ void up_udelay(useconds_t microseconds) for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++) { } + microseconds -= 10; } @@ -124,6 +127,7 @@ void up_udelay(useconds_t microseconds) for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++) { } + microseconds--; } } diff --git a/arch/mips/src/mips32/mips32-memorymap.h b/arch/mips/src/mips32/mips32-memorymap.h index 103ca6e2be6..0db3a0d0bbe 100644 --- a/arch/mips/src/mips32/mips32-memorymap.h +++ b/arch/mips/src/mips32/mips32-memorymap.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/mips/src/mips32/mips32-memorymap.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. @@ -31,24 +31,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H #define __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ /* MIPS32 address space organization */ @@ -72,13 +72,13 @@ #ifndef __ASSEMBLY__ -/******************************************************************************************** +/**************************************************************************** * Inline Functions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Function Prototypes - ********************************************************************************************/ + ****************************************************************************/ #ifdef __cplusplus #define EXTERN extern "C" diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c index d9b6e3c14aa..fbd663f66c5 100644 --- a/arch/mips/src/mips32/up_assert.c +++ b/arch/mips/src/mips32/up_assert.c @@ -88,19 +88,19 @@ static void _up_assert(int errorcode) if (g_current_regs || running_task()->flink == NULL) { - (void)up_irq_save(); - for (; ; ) - { + (void)up_irq_save(); + for (; ; ) + { #if CONFIG_BOARD_RESET_ON_ASSERT >= 1 - board_reset(CONFIG_BOARD_ASSERT_RESET_VALUE); + board_reset(CONFIG_BOARD_ASSERT_RESET_VALUE); #endif #ifdef CONFIG_ARCH_LEDS - board_autoled_on(LED_PANIC); - up_mdelay(250); - board_autoled_off(LED_PANIC); - up_mdelay(250); + board_autoled_on(LED_PANIC); + up_mdelay(250); + board_autoled_off(LED_PANIC); + up_mdelay(250); #endif - } + } } else { diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c index 61599eb99e0..b653dd5731c 100644 --- a/arch/mips/src/mips32/up_doirq.c +++ b/arch/mips/src/mips32/up_doirq.c @@ -87,8 +87,8 @@ uint32_t *up_doirq(int irq, uint32_t *regs) DEBUGASSERT(g_current_regs == NULL); g_current_regs = regs; - /* Disable further occurrences of this interrupt (until the interrupt sources - * have been clear by the driver). + /* Disable further occurrences of this interrupt (until the interrupt + * srouce have been cleared by the driver). */ up_disable_irq(irq); diff --git a/arch/mips/src/mips32/up_dumpstate.c b/arch/mips/src/mips32/up_dumpstate.c index 694e6a9bff2..59d86eac1d4 100644 --- a/arch/mips/src/mips32/up_dumpstate.c +++ b/arch/mips/src/mips32/up_dumpstate.c @@ -103,28 +103,35 @@ static inline void up_registerdump(void) if (g_current_regs) { _alert("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n", - g_current_regs[REG_MFLO], g_current_regs[REG_MFHI], g_current_regs[REG_EPC], - g_current_regs[REG_STATUS]); + g_current_regs[REG_MFLO], g_current_regs[REG_MFHI], + g_current_regs[REG_EPC], g_current_regs[REG_STATUS]); _alert("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n", - g_current_regs[REG_AT], g_current_regs[REG_V0], g_current_regs[REG_V1], - g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2], + g_current_regs[REG_AT], g_current_regs[REG_V0], + g_current_regs[REG_V1], g_current_regs[REG_A0], + g_current_regs[REG_A1], g_current_regs[REG_A2], g_current_regs[REG_A3]); - _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n", - g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2], - g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5], + _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x " + "T6:%08x T7:%08x\n", + g_current_regs[REG_T0], g_current_regs[REG_T1], + g_current_regs[REG_T2], g_current_regs[REG_T3], + g_current_regs[REG_T4], g_current_regs[REG_T5], g_current_regs[REG_T6], g_current_regs[REG_T7]); - _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", - g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2], - g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5], + _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x " + "S6:%08x S7:%08x\n", + g_current_regs[REG_S0], g_current_regs[REG_S1], + g_current_regs[REG_S2], g_current_regs[REG_S3], + g_current_regs[REG_S4], g_current_regs[REG_S5], g_current_regs[REG_S6], g_current_regs[REG_S7]); #ifdef MIPS32_SAVE_GP _alert("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n", - g_current_regs[REG_T8], g_current_regs[REG_T9], g_current_regs[REG_GP], - g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_RA]); + g_current_regs[REG_T8], g_current_regs[REG_T9], + g_current_regs[REG_GP], g_current_regs[REG_SP], + g_current_regs[REG_FP], g_current_regs[REG_RA]); #else _alert("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n", - g_current_regs[REG_T8], g_current_regs[REG_T9], g_current_regs[REG_SP], - g_current_regs[REG_FP], g_current_regs[REG_RA]); + g_current_regs[REG_T8], g_current_regs[REG_T9], + g_current_regs[REG_SP], g_current_regs[REG_FP], + g_current_regs[REG_RA]); #endif } } diff --git a/arch/mips/src/mips32/up_irq.c b/arch/mips/src/mips32/up_irq.c index d36ecd3c97f..2f3f3bbb9dc 100644 --- a/arch/mips/src/mips32/up_irq.c +++ b/arch/mips/src/mips32/up_irq.c @@ -78,8 +78,8 @@ irqstate_t up_irq_save(void) * Name: up_irq_restore * * Description: - * Restore the previous up_irq_enable state (i.e., the one previously returned - * by up_irq_save()) + * Restore the previous up_irq_enable state (i.e., the one previously + * returned by up_irq_save()) * * Input Parameters: * state - The interrupt state to be restored. diff --git a/arch/mips/src/mips32/up_reprioritizertr.c b/arch/mips/src/mips32/up_reprioritizertr.c index d8da73bfbd1..dacf98b8239 100644 --- a/arch/mips/src/mips32/up_reprioritizertr.c +++ b/arch/mips/src/mips32/up_reprioritizertr.c @@ -138,7 +138,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) sched_suspend_scheduler(rtcb); - /* Are we in an interrupt handler? */ + /* Are we in an interrupt handler? */ if (g_current_regs) { @@ -146,7 +146,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) * Just copy the g_current_regs into the OLD rtcb. */ - up_savestate(rtcb->xcp.regs); + up_savestate(rtcb->xcp.regs); /* Restore the exception context of the rtcb at the (new) head * of the ready-to-run task list. diff --git a/arch/mips/src/mips32/up_swint0.c b/arch/mips/src/mips32/up_swint0.c index b093ed0447f..a372007af51 100644 --- a/arch/mips/src/mips32/up_swint0.c +++ b/arch/mips/src/mips32/up_swint0.c @@ -103,17 +103,20 @@ static void dispatch_syscall(void) { # error "Missing logic" -/* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for ARM */ -/* __asm__ __volatile__ */ -/* ( */ -/* Save registers */ -/* Get the base of the stub lookup table */ -/* Get the offset of the stub for this syscall */ -/* Load the entry of the stub for this syscall */ -/* Call the stub */ -/* Restore regsisters */ -/* Return from the syscall */ -/* ); */ + /* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for ARM */ + +# if 0 + __asm__ __volatile__ + ( + Save registers + Get the base of the stub lookup table + Get the offset of the stub for this syscall + Load the entry of the stub for this syscall + Call the stub + Restore regsisters + Return from the syscall + ); +# endif } #endif @@ -153,17 +156,18 @@ int up_swint0(int irq, FAR void *context, FAR void *arg) { /* R4=SYS_restore_context: This a restore context command: * - * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; * * At this point, the following values are saved in context: * * R4 = SYS_restore_context * R5 = restoreregs * - * In this case, we simply need to set g_current_regs to restore register - * area referenced in the saved R1. context == g_current_regs is the normal - * exception return. By setting g_current_regs = context[R1], we force - * the return to the saved context referenced in R1. + * In this case, we simply need to set g_current_regs to restore the + * register area referenced in the saved R1. context == g_current_regs + * is the normal exception return. By setting g_current_regs equals to + * context[R1], we force the return to the saved context referenced + * in R1. */ case SYS_restore_context: diff --git a/arch/mips/src/mips32/up_vfork.c b/arch/mips/src/mips32/up_vfork.c index 6f1616fb9db..97424ef00a4 100644 --- a/arch/mips/src/mips32/up_vfork.c +++ b/arch/mips/src/mips32/up_vfork.c @@ -84,8 +84,8 @@ * 1) User code calls vfork(). vfork() collects context information and * transfers control up up_vfork(). * 2) up_vfork()and calls nxtask_vforksetup(). - * 3) nxtask_vforksetup() allocates and configures the child task's TCB. This - * consists of: + * 3) nxtask_vforksetup() allocates and configures the child task's TCB. + * this consists of: * - Allocation of the child task's TCB. * - Initialization of file descriptors and streams * - Configuration of environment variables diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c index 1bcb7e6e111..a2861146f7f 100644 --- a/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -294,8 +294,8 @@ * Private Types ****************************************************************************/ -/* The pic32mx_driver_s encapsulates all state information for a single hardware - * interface +/* The pic32mx_driver_s encapsulates all state information for a single + * hardware interface. */ struct pic32mx_driver_s @@ -364,8 +364,10 @@ static void pic32mx_putreg(uint32_t val, uint32_t addr); /* Buffer and descriptor management */ #ifdef CONFIG_NET_DESCDEBUG -static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, const char *msg); -static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, const char *msg); +static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, + const char *msg); +static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, + const char *msg); #else # define pic32mx_dumptxdesc(txdesc,msg) # define pic32mx_dumprxdesc(rxdesc,msg) @@ -373,11 +375,13 @@ static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, const char *msg) static inline void pic32mx_bufferinit(struct pic32mx_driver_s *priv); static uint8_t *pic32mx_allocbuffer(struct pic32mx_driver_s *priv); -static void pic32mx_freebuffer(struct pic32mx_driver_s *priv, uint8_t *buffer); +static void pic32mx_freebuffer(struct pic32mx_driver_s *priv, + uint8_t *buffer); static inline void pic32mx_txdescinit(struct pic32mx_driver_s *priv); static inline void pic32mx_rxdescinit(struct pic32mx_driver_s *priv); -static inline struct pic32mx_txdesc_s *pic32mx_txdesc(struct pic32mx_driver_s *priv); +static inline struct pic32mx_txdesc_s * + pic32mx_txdesc(struct pic32mx_driver_s *priv); static inline void pic32mx_txnext(struct pic32mx_driver_s *priv); static inline void pic32mx_rxreturn(struct pic32mx_rxdesc_s *rxdesc); static struct pic32mx_rxdesc_s *pic32mx_rxdesc(struct pic32mx_driver_s *priv); @@ -482,8 +486,8 @@ static void pic32mx_checkreg(uint32_t addr, uint32_t val, bool iswrite) static uint32_t count = 0; static bool prevwrite = false; - /* Is this the same value that we read from/wrote to the same register last time? - * Are we polling the register? If so, suppress the output. + /* Is this the same value that we read from/wrote to the same register + * last time? Are we polling the register? If so, suppress the output. */ if (addr == prevaddr && val == preval && prevwrite == iswrite) @@ -589,14 +593,17 @@ static void pic32mx_putreg(uint32_t val, uint32_t addr) ****************************************************************************/ #ifdef CONFIG_NET_DESCDEBUG -static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, const char *msg) +static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, + const char *msg) { ninfo("TX Descriptor [%p]: %s\n", txdesc, msg); ninfo(" status: %08x\n", txdesc->status); - ninfo(" address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address)); + ninfo(" address: %08x [%08x]\n", + txdesc->address, VIRT_ADDR(txdesc->address)); ninfo(" tsv1: %08x\n", txdesc->tsv1); ninfo(" tsv2: %08x\n", txdesc->tsv2); - ninfo(" nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted)); + ninfo(" nexted: %08x [%08x]\n", + txdesc->nexted, VIRT_ADDR(txdesc->nexted)); } #endif @@ -616,14 +623,17 @@ static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, const char *msg) ****************************************************************************/ #ifdef CONFIG_NET_DESCDEBUG -static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, const char *msg) +static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, + const char *msg) { ninfo("RX Descriptor [%p]: %s\n", rxdesc, msg); ninfo(" status: %08x\n", rxdesc->status); - ninfo(" address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address)); + ninfo(" address: %08x [%08x]\n", + rxdesc->address, VIRT_ADDR(rxdesc->address)); ninfo(" rsv1: %08x\n", rxdesc->rsv1); ninfo(" rsv2: %08x\n", rxdesc->rsv2); - ninfo(" nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted)); + ninfo(" nexted: %08x [%08x]\n", + rxdesc->nexted, VIRT_ADDR(rxdesc->nexted)); } #endif @@ -647,15 +657,15 @@ static inline void pic32mx_bufferinit(struct pic32mx_driver_s *priv) int i; for (i = 0, buffer = priv->pd_buffers; i < PIC32MX_NBUFFERS; i++) - { - /* Add the buffer to the end of the list of free buffers */ + { + /* Add the buffer to the end of the list of free buffers */ - sq_addlast((sq_entry_t *)buffer, &priv->pd_freebuffers); + sq_addlast((sq_entry_t *)buffer, &priv->pd_freebuffers); - /* Get the address of the next buffer */ + /* Get the address of the next buffer */ - buffer += PIC32MX_ALIGNED_BUFSIZE; - } + buffer += PIC32MX_ALIGNED_BUFSIZE; + } } /**************************************************************************** @@ -697,7 +707,7 @@ static void pic32mx_freebuffer(struct pic32mx_driver_s *priv, uint8_t *buffer) { /* Add the buffer to the end of the free buffer list */ - sq_addlast((sq_entry_t *)buffer, &priv->pd_freebuffers); + sq_addlast((sq_entry_t *)buffer, &priv->pd_freebuffers); } /**************************************************************************** @@ -745,13 +755,13 @@ static inline void pic32mx_txdescinit(struct pic32mx_driver_s *priv) * creating a ring. */ - if (i == (CONFIG_PIC32MX_ETH_NRXDESC-1)) + if (i == (CONFIG_PIC32MX_ETH_NRXDESC - 1)) { txdesc->nexted = PHYS_ADDR(priv->pd_txdesc); } else { - txdesc->nexted = PHYS_ADDR(&priv->pd_txdesc[i+1]); + txdesc->nexted = PHYS_ADDR(&priv->pd_txdesc[i + 1]); } pic32mx_dumptxdesc(txdesc, "Initial"); @@ -816,13 +826,13 @@ static inline void pic32mx_rxdescinit(struct pic32mx_driver_s *priv) * creating a ring. */ - if (i == (CONFIG_PIC32MX_ETH_NRXDESC-1)) + if (i == (CONFIG_PIC32MX_ETH_NRXDESC - 1)) { rxdesc->nexted = PHYS_ADDR(priv->pd_rxdesc); } else { - rxdesc->nexted = PHYS_ADDR(&priv->pd_rxdesc[i+1]); + rxdesc->nexted = PHYS_ADDR(&priv->pd_rxdesc[i + 1]); } pic32mx_dumprxdesc(rxdesc, "Initial"); @@ -850,7 +860,8 @@ static inline void pic32mx_rxdescinit(struct pic32mx_driver_s *priv) * ****************************************************************************/ -static inline struct pic32mx_txdesc_s *pic32mx_txdesc(struct pic32mx_driver_s *priv) +static inline struct pic32mx_txdesc_s * + pic32mx_txdesc(struct pic32mx_driver_s *priv) { struct pic32mx_txdesc_s *txdesc; @@ -968,8 +979,8 @@ static struct pic32mx_rxdesc_s *pic32mx_rxdesc(struct pic32mx_driver_s *priv) /* Inspect the list of RX descriptors to see if the EOWN bit is cleared. * If it is, this descriptor is now under software control and a message was - * received. Use SOP and EOP to extract the message, use BYTE_COUNT, RXF_RSV, - * RSV and PKT_CHECKSUM to get the message characteristics. + * received. Use SOP and EOP to extract the message, use BYTE_COUNT, + * RXF_RSV, RSV and PKT_CHECKSUM to get the message characteristics. */ for (i = 0; i < CONFIG_PIC32MX_ETH_NRXDESC; i++) @@ -1026,7 +1037,8 @@ static int pic32mx_transmit(struct pic32mx_driver_s *priv) /* Increment statistics and dump the packet (if so configured) */ NETDEV_TXPACKETS(&priv->pd_dev); - pic32mx_dumppacket("Transmit packet", priv->pd_dev.d_buf, priv->pd_dev.d_len); + pic32mx_dumppacket("Transmit packet", + priv->pd_dev.d_buf, priv->pd_dev.d_len); /* In order to transmit a message: * @@ -1057,7 +1069,7 @@ static int pic32mx_transmit(struct pic32mx_driver_s *priv) * contained in the buffer. */ - status = ((uint32_t)priv->pd_dev.d_len << TXDESC_STATUS_BYTECOUNT_SHIFT); + status = ((uint32_t)priv->pd_dev.d_len << TXDESC_STATUS_BYTECOUNT_SHIFT); priv->pd_dev.d_len = 0; /* Set EOWN = 1 to indicate that the packet belongs to Ethernet and set both @@ -1151,8 +1163,8 @@ static int pic32mx_txpoll(struct net_driver_s *dev) if (!devif_loopback(&priv->pd_dev)) { - /* Send this packet. In this context, we know that there is space for - * at least one more packet in the descriptor list. + /* Send this packet. In this context, we know that there is space + * for at least one more packet in the descriptor list. */ pic32mx_transmit(priv); @@ -1229,10 +1241,10 @@ static void pic32mx_poll(struct pic32mx_driver_s *priv) pic32mx_freebuffer(priv, priv->pd_dev.d_buf); priv->pd_dev.d_buf = NULL; } + priv->pd_polling = false; } } - } /**************************************************************************** @@ -1275,6 +1287,7 @@ static void pic32mx_timerpoll(struct pic32mx_driver_s *priv) pic32mx_freebuffer(priv, priv->pd_dev.d_buf); priv->pd_dev.d_buf = NULL; } + priv->pd_polling = false; } } @@ -1285,7 +1298,7 @@ static void pic32mx_timerpoll(struct pic32mx_driver_s *priv) * * Description: * While processing an RxDone event, higher logic decides to send a packet, - * possibly a response to the incoming packet (but probably not, in reality). + * possibly a response to the incoming packet (but probably not, in reality) * However, since the Rx and Tx operations are decoupled, there is no * guarantee that there will be a Tx descriptor available at that time. * This function will perform that check and, if no Tx descriptor is @@ -1313,19 +1326,19 @@ static void pic32mx_response(struct pic32mx_driver_s *priv) txdesc = pic32mx_txdesc(priv); if (txdesc != NULL) { - /* Yes.. queue the packet now. */ + /* Yes.. queue the packet now. */ - pic32mx_transmit(priv); + pic32mx_transmit(priv); } else { - /* No.. mark the Tx as pending and halt further Rx interrupts */ + /* No.. mark the Tx as pending and halt further Rx interrupts */ - DEBUGASSERT((priv->pd_inten & ETH_INT_TXDONE) != 0); + DEBUGASSERT((priv->pd_inten & ETH_INT_TXDONE) != 0); - priv->pd_txpending = true; - priv->pd_inten &= ~ETH_RXINTS; - pic32mx_putreg(priv->pd_inten, PIC32MX_ETH_IEN); + priv->pd_txpending = true; + priv->pd_inten &= ~ETH_RXINTS; + pic32mx_putreg(priv->pd_inten, PIC32MX_ETH_IEN); } } @@ -1370,6 +1383,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) return; } + pic32mx_dumprxdesc(rxdesc, "RX Complete"); /* Update statistics */ @@ -1378,7 +1392,8 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) /* Get the packet length */ - priv->pd_dev.d_len = (rxdesc->rsv2 & RXDESC_RSV2_BYTECOUNT_MASK) >> RXDESC_RSV2_BYTECOUNT_SHIFT; + priv->pd_dev.d_len = (rxdesc->rsv2 & RXDESC_RSV2_BYTECOUNT_MASK) >> + RXDESC_RSV2_BYTECOUNT_SHIFT; /* Check for errors */ @@ -1390,10 +1405,10 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) pic32mx_rxreturn(rxdesc); } - /* If the packet length is greater then the buffer, then we cannot accept - * the packet. Also, since the DMA packet buffers are set up to - * be the same size as our max packet size, any fragments also - * imply that the packet is too big. + /* If the packet length is greater then the buffer, then we cannot + * accept the packet. Also, since the DMA packet buffers are set up to + * be the same size as our max packet size, any fragments also imply + * that the packet is too big. */ else if (priv->pd_dev.d_len > CONFIG_NET_ETH_PKTSIZE) @@ -1503,7 +1518,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) */ if (priv->pd_dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -1605,9 +1620,9 @@ static void pic32mx_txdone(struct pic32mx_driver_s *priv) DEBUGASSERT(pic32mx_txdesc(priv) != NULL); - /* Inspect the list of TX descriptors to see if the EOWN bit is cleared. If it - * is, this descriptor is now under software control and the message was - * transmitted. Use TSV to check for the transmission result. + /* Inspect the list of TX descriptors to see if the EOWN bit is cleared. + * if it is, this descriptor is now under software control and the message + * was transmitted. Use TSV to check for the transmission result. */ for (i = 0; i < CONFIG_PIC32MX_ETH_NTXDESC; i++) @@ -1727,7 +1742,7 @@ static void pic32mx_interrupt_work(void *arg) /* RXBUSE: Receive BVCI Bus Error Interrupt. This bit is set when the * RX DMA encounters a BVCI Bus error during a memory access. It is - * cleared by either a Reset or CPU write of a ‘1’ to the CLR register. + * cleared by either a Reset or CPU write of a "1" to the CLR register. */ if ((status & ETH_INT_RXBUSE) != 0) @@ -1737,20 +1752,20 @@ static void pic32mx_interrupt_work(void *arg) } /* Receive Normal Events **********************************************/ - /* RXACT: Receive Activity Interrupt. This bit is set whenever RX packet - * data is stored in the RXBM FIFO. It is cleared by either a Reset or CPU - * write of a ‘1’ to the CLR register. + /* RXACT: Receive Activity Interrupt. This bit is set whenever RX + * packet data is stored in the RXBM FIFO. It is cleared by either + * a Reset or CPU write of a "1" to the CLR register. */ /* PKTPEND: Packet Pending Interrupt. This bit is set when the BUFCNT - * counter has a value other than ‘0’. It is cleared by either a Reset + * counter has a value other than "0". It is cleared by either a Reset * or by writing the BUFCDEC bit to decrement the BUFCNT counter. - * Writing a ‘0’ or a ‘1’ has no effect. + * Writing a "0" or a "1" has no effect. */ - /* RXDONE: Receive Done Interrupt. This bit is set whenever an RX packet - * is successfully received. It is cleared by either a Reset or CPU - * write of a ‘1’ to the CLR register. + /* RXDONE: Receive Done Interrupt. This bit is set whenever an RX + * packet is successfully received. It is cleared by either a Reset + * or CPU write of a "1" to the CLR register. */ if ((status & ETH_INT_RXDONE) != 0) @@ -2011,9 +2026,10 @@ static void pic32mx_poll_work(void *arg) net_lock(); if (pic32mx_txdesc(priv) != NULL) { - /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm.. - * might be bug here. Does this mean if there is a transmit in progress, - * we will missing TCP time state updates? + /* If so, update TCP timing states and poll the network for new XMIT + * data. + * Hmmm... might be bug here. Does this mean if there is a transmit + * in progress we will missing TCP time state updates? */ pic32mx_timerpoll(priv); @@ -2095,7 +2111,7 @@ static int pic32mx_ifup(struct net_driver_s *dev) /* Pin Configuration: * * No GPIO pin configuration is required. Enabling the Ethernet Controller - * will configure the I/O pin direction as defined by the Ethernet Controller + * will configure the IO pin direction as defined by the Ethernet Controller * control bits. The port TRIS and LATCH registers will be overridden. * * I/O Pin MII RMII Pin Description @@ -2135,7 +2151,8 @@ static int pic32mx_ifup(struct net_driver_s *dev) #if CONFIG_PIC32MX_FMIIEN == 0 pic32mx_putreg(EMAC1_SUPP_RESETRMII, PIC32MX_EMAC1_SUPPSET); - pic32mx_putreg((EMAC1_SUPP_RESETRMII | EMAC1_SUPP_SPEEDRMII), PIC32MX_EMAC1_SUPPCLR); + pic32mx_putreg((EMAC1_SUPP_RESETRMII | EMAC1_SUPP_SPEEDRMII), + PIC32MX_EMAC1_SUPPCLR); #endif /* Issue an MIIM block reset, by setting the RESETMGMT (EMAC1MCFG:15) bit, @@ -2194,14 +2211,16 @@ static int pic32mx_ifup(struct net_driver_s *dev) /* Program EMAC1IPGT with the back-to-back inter-packet gap */ /* Use EMAC1IPGR for setting the non back-to-back inter-packet gap */ - pic32mx_putreg(((12 << EMAC1_IPGR_GAP1_SHIFT) | (12 << EMAC1_IPGR_GAP2_SHIFT)), + pic32mx_putreg(((12 << EMAC1_IPGR_GAP1_SHIFT) | + (12 << EMAC1_IPGR_GAP2_SHIFT)), PIC32MX_EMAC1_IPGR); /* Set the collision window and the maximum number of retransmissions in * EMAC1CLRT. */ - pic32mx_putreg(((15 << EMAC1_CLRT_RETX_SHIFT) | (55 << EMAC1_CLRT_CWINDOW_SHIFT)), + pic32mx_putreg(((15 << EMAC1_CLRT_RETX_SHIFT) | + (55 << EMAC1_CLRT_CWINDOW_SHIFT)), PIC32MX_EMAC1_CLRT); /* Set the maximum frame length in EMAC1MAXF. "This field resets to @@ -2258,8 +2277,8 @@ static int pic32mx_ifup(struct net_driver_s *dev) /* Set the RX filters by updating the ETHHT0, ETHHT1, ETHPMM0, ETHPMM1, * ETHPMCS and ETHRXFC registers. * - * Set up RX filter and configure to accept broadcast addresses and multicast - * addresses (if so configured). NOTE: There is a selection + * Set up RX filter and configure to accept broadcast addresses and + * multicast addresses (if so configured). NOTE: There is a selection * CONFIG_NET_BROADCAST, but this enables receipt of UDP broadcast packets * inside of the stack. */ @@ -2315,13 +2334,13 @@ static int pic32mx_ifup(struct net_driver_s *dev) pic32mx_putreg(0xffffffff, PIC32MX_ETH_IRQCLR); - /* Configure interrupts. The Ethernet interrupt was attached during one-time - * initialization, so we only need to set the interrupt priority, configure - * interrupts, and enable them. + /* Configure interrupts. The Ethernet interrupt was attached during + * one-time initialization, so we only need to set the interrupt priority, + * configure interrupts, and enable them. */ - /* If the user provided an interrupt priority, then set the interrupt to that - * priority + /* If the user provided an interrupt priority, then set the interrupt to + * that priority. */ #if defined(CONFIG_PIC32MX_ETH_PRIORITY) && defined(CONFIG_ARCH_IRQPRIO) @@ -2430,8 +2449,8 @@ static void pic32mx_txavail_work(void *arg) if (pic32mx_txdesc(priv) != NULL) { - /* If so, then poll the network for new XMIT data. First allocate a buffer - * to perform the poll + /* If so, then poll the network for new XMIT data. First allocate + * a buffer to perform the poll */ pic32mx_poll(priv); @@ -2513,8 +2532,8 @@ static int pic32mx_addmac(struct net_driver_s *dev, const uint8_t *mac) * Function: pic32mx_rmmac * * Description: - * NuttX Callback: Remove the specified MAC address from the hardware multicast - * address filtering + * NuttX Callback: Remove the specified MAC address from the hardware + * multicast address filtering * * Input Parameters: * dev - Reference to the NuttX driver state structure @@ -2610,7 +2629,8 @@ static void pic32mx_phybusywait(void) ****************************************************************************/ #ifdef PIC32MX_HAVE_PHY -static void pic32mx_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata) +static void pic32mx_phywrite(uint8_t phyaddr, uint8_t regaddr, + uint16_t phydata) { uint32_t regval; @@ -2891,8 +2911,9 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) #ifdef CONFIG_ETH0_PHY_DP83848C /* The RMII/MII of operation can be selected by strap options or register - * control (using the RBR register). For RMII mode, it is required to use the - * strap option, since it requires a 50 MHz clock instead of the normal 25 MHz. + * control (using the RBR register). For RMII mode, it is required to use + * the strap option, since it requires a 50 MHz clock instead of the normal + * 25 Mhz. */ #endif @@ -2935,10 +2956,10 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) * PHY address. */ - phyreg = (unsigned int)pic32mx_phyread(phyaddr, MII_PHYID1); - ninfo("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg); + phyreg = (unsigned int)pic32mx_phyread(phyaddr, MII_PHYID1); + ninfo("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg); - if (phyreg == PIC32MX_PHYID1) + if (phyreg == PIC32MX_PHYID1) { phyreg = pic32mx_phyread(phyaddr, MII_PHYID2); ninfo("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg); @@ -2959,6 +2980,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) nerr("ERROR: No PHY detected\n"); return -ENODEV; } + ninfo("phyaddr: %d\n", phyaddr); /* Save the discovered PHY device address */ @@ -2972,6 +2994,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) { return ret; } + pic32mx_showmii(phyaddr, "After reset"); /* Set the MII/RMII operation mode. This usually requires access to a @@ -3137,8 +3160,10 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) #endif ninfo("%dBase-T %s duplex\n", - (priv->pd_mode & PIC32MX_SPEED_MASK) == PIC32MX_SPEED_100 ? 100 : 10, - (priv->pd_mode & PIC32MX_DUPLEX_MASK) == PIC32MX_DUPLEX_FULL ?"full" : "half"); + (priv->pd_mode & PIC32MX_SPEED_MASK) == PIC32MX_SPEED_100 ? + 100 : 10, + (priv->pd_mode & PIC32MX_DUPLEX_MASK) == PIC32MX_DUPLEX_FULL ? + "full" : "half"); /* Disable auto-configuration. Set the fixed speed/duplex mode. * (probably more than little redundant). @@ -3185,7 +3210,8 @@ static void pic32mx_macmode(uint8_t mode) /* Set MAC to operate in full duplex mode with CRC and Pad enabled */ - pic32mx_putreg((EMAC1_CFG2_FULLDPLX | EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), + pic32mx_putreg((EMAC1_CFG2_FULLDPLX | EMAC1_CFG2_CRCEN | + EMAC1_CFG2_PADCRCEN), PIC32MX_EMAC1_CFG2SET); } else @@ -3197,7 +3223,8 @@ static void pic32mx_macmode(uint8_t mode) /* Set MAC to operate in half duplex mode with CRC and Pad enabled */ pic32mx_putreg(EMAC1_CFG2_FULLDPLX, PIC32MX_EMAC1_CFG2CLR); - pic32mx_putreg((EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), PIC32MX_EMAC1_CFG2SET); + pic32mx_putreg((EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), + PIC32MX_EMAC1_CFG2SET); } /* Set the RMII MAC speed. */ @@ -3250,7 +3277,8 @@ static void pic32mx_ethreset(struct pic32mx_driver_s *priv) /* Turn the Ethernet Controller off: Clear the ON, RXEN and TXRTS bits */ - pic32mx_putreg(ETH_CON1_RXEN | ETH_CON1_TXRTS | ETH_CON1_ON, PIC32MX_ETH_CON1CLR); + pic32mx_putreg(ETH_CON1_RXEN | ETH_CON1_TXRTS | ETH_CON1_ON, + PIC32MX_ETH_CON1CLR); /* Wait activity abort by polling the ETHBUSY bit */ @@ -3289,9 +3317,10 @@ static void pic32mx_ethreset(struct pic32mx_driver_s *priv) /* MAC Initialization *****************************************************/ /* Put the MAC into the reset state */ - pic32mx_putreg((EMAC1_CFG1_TXRST | EMAC1_CFG1_MCSTXRST | EMAC1_CFG1_RXRST | - EMAC1_CFG1_MCSRXRST | EMAC1_CFG1_SIMRST | EMAC1_CFG1_SOFTRST), - PIC32MX_EMAC1_CFG1); + pic32mx_putreg((EMAC1_CFG1_TXRST | EMAC1_CFG1_MCSTXRST | + EMAC1_CFG1_RXRST | EMAC1_CFG1_MCSRXRST | + EMAC1_CFG1_SIMRST | EMAC1_CFG1_SOFTRST), + PIC32MX_EMAC1_CFG1); /* Take the MAC out of the reset state */ diff --git a/arch/mips/src/pic32mx/pic32mx-exception.c b/arch/mips/src/pic32mx/pic32mx-exception.c index 86d8ddf133e..6117bbb4389 100644 --- a/arch/mips/src/pic32mx/pic32mx-exception.c +++ b/arch/mips/src/pic32mx/pic32mx-exception.c @@ -59,13 +59,13 @@ * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: pic32mx_exception * * Description: * Called from assembly language logic on all other exceptions. * - ************************************************************************************/ + ****************************************************************************/ uint32_t *pic32mx_exception(uint32_t *regs) { diff --git a/arch/mips/src/pic32mx/pic32mx-lowconsole.c b/arch/mips/src/pic32mx/pic32mx-lowconsole.c index 5c3f2b4116e..b8107f6bcdc 100644 --- a/arch/mips/src/pic32mx/pic32mx-lowconsole.c +++ b/arch/mips/src/pic32mx/pic32mx-lowconsole.c @@ -174,8 +174,8 @@ static void pic32mx_uartsetbaud(uintptr_t uart_base, uint32_t baudrate) uint32_t brg; unsigned int mode; - /* We want the largest value of BRG divisor possible (for the best accuracy). - * Subject to BRG <= 65536. + /* We want the largest value of BRG divisor possible + * (for the best accuracy), subject to BRG <= 65536. */ tmp = BOARD_PBCLOCK / baudrate; @@ -194,6 +194,7 @@ static void pic32mx_uartsetbaud(uintptr_t uart_base, uint32_t baudrate) brg = (tmp + 8) >> 4; mode = PIC32MX_UART_MODECLR_OFFSET; } + DEBUGASSERT(brg <= 65536); /* Set the BRG divisor */ @@ -236,15 +237,18 @@ void pic32mx_uartreset(uintptr_t uart_base) #ifdef HAVE_UART_DEVICE void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate, - unsigned int parity, unsigned int nbits, bool stop2) + unsigned int parity, unsigned int nbits, + bool stop2) { /* Clear mode and sta bits */ pic32mx_putreg(uart_base, PIC32MX_UART_MODECLR_OFFSET, - UART_MODE_STSEL | UART_MODE_PDSEL_MASK | UART_MODE_BRGH | - UART_MODE_RXINV | UART_MODE_WAKE | UART_MODE_LPBACK | - UART_MODE_UEN_MASK | UART_MODE_RTSMD | UART_MODE_IREN | - UART_MODE_SIDL | UART_MODE_ON); + UART_MODE_STSEL | UART_MODE_PDSEL_MASK | + UART_MODE_BRGH | UART_MODE_RXINV | + UART_MODE_WAKE | UART_MODE_LPBACK | + UART_MODE_UEN_MASK | UART_MODE_RTSMD | + UART_MODE_IREN | UART_MODE_SIDL | + UART_MODE_ON); /* Configure the FIFOs: * @@ -252,19 +256,21 @@ void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate, * TX: Interrupt on FIFO empty * Invert transmit polarity. * - * NOTE that there are not many options on trigger TX interrupts. The FIFO not - * full might generate better through-put but with a higher interrupt rate. FIFO - * empty should lower the interrupt rate but result in a burstier output. If - * you change this, please read the comment for acknowledging the interrupt in - * pic32mx-serial.c + * NOTE that there are not many options on trigger TX interrupts. + * The FIFO not full might generate better through-put but with a higher + * interrupt rate. FIFO empty should lower the interrupt rate but result + * in a burstier output. If you change this, please read the comment for + * acknowledging the interrupt in pic32mx-serial.c */ #ifdef UART_STA_URXISEL_RXB6 pic32mx_putreg(uart_base, PIC32MX_UART_STACLR_OFFSET, - UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | UART_STA_URXISEL_RXB6); + UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | + UART_STA_URXISEL_RXB6); #else pic32mx_putreg(uart_base, PIC32MX_UART_STACLR_OFFSET, - UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | UART_STA_URXISEL_RXB3); + UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | + UART_STA_URXISEL_RXB3); #endif /* Configure the FIFO interrupts */ @@ -348,11 +354,13 @@ void up_lowputc(char ch) #ifdef HAVE_SERIAL_CONSOLE /* Wait for the transmit buffer not full */ - while ((pic32mx_getreg(PIC32MX_CONSOLE_BASE, PIC32MX_UART_STA_OFFSET) & UART_STA_UTXBF) != 0); + while ((pic32mx_getreg(PIC32MX_CONSOLE_BASE, PIC32MX_UART_STA_OFFSET) & + UART_STA_UTXBF) != 0); /* Then write the character to the TX data register */ - pic32mx_putreg(PIC32MX_CONSOLE_BASE, PIC32MX_UART_TXREG_OFFSET, (uint32_t)ch); + pic32mx_putreg(PIC32MX_CONSOLE_BASE, PIC32MX_UART_TXREG_OFFSET, + (uint32_t)ch); #endif } diff --git a/arch/mips/src/pic32mx/pic32mx-lowinit.c b/arch/mips/src/pic32mx/pic32mx-lowinit.c index 544baa36cf5..27c5490f921 100644 --- a/arch/mips/src/pic32mx/pic32mx-lowinit.c +++ b/arch/mips/src/pic32mx/pic32mx-lowinit.c @@ -212,4 +212,3 @@ void pic32mx_lowinit(void) pic32mx_boardinitialize(); } - diff --git a/arch/mips/src/pic32mx/pic32mx-serial.c b/arch/mips/src/pic32mx/pic32mx-serial.c index 8e6582a1452..bc8e6327d84 100644 --- a/arch/mips/src/pic32mx/pic32mx-serial.c +++ b/arch/mips/src/pic32mx/pic32mx-serial.c @@ -163,7 +163,8 @@ struct up_dev_s /* Low-level helpers */ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset); -static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value); +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint32_t value); static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im); static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im); @@ -245,7 +246,7 @@ static uart_dev_t g_uart1port = { .size = CONFIG_UART1_TXBUFSIZE, .buffer = g_uart1txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart1priv, }; @@ -279,7 +280,7 @@ static uart_dev_t g_uart2port = { .size = CONFIG_UART2_TXBUFSIZE, .buffer = g_uart2txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart2priv, }; @@ -302,7 +303,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint32_t value) { putreg32(value, priv->uartbase + offset); } @@ -334,9 +336,10 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) flags = enter_critical_section(); if (im) - { - *im = priv->im; - } + { + *im = priv->im; + } + up_restoreuartint(dev, 0); leave_critical_section(flags); } @@ -403,7 +406,8 @@ static void up_shutdown(struct uart_dev_s *dev) * * RX and TX interrupts are not enabled by the attach method (unless the * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * interrupts are not enabled until the txint() and rxint() methods are + * called. * ****************************************************************************/ @@ -474,18 +478,19 @@ static int up_interrupt(int irq, void *context, void *arg) * following error conditions take place: * - Parity error PERR (UxSTA bit 3) is detected * - Framing Error FERR (UxSTA bit 2) is detected - * - Overflow condition for the receive buffer OERR (UxSTA bit 1) occurs + * - Overflow condition for the receive buffer OERR (UxSTA bit 1) + * occurs. */ #ifdef CONFIG_DEBUG_FEATURES if (up_pending_irq(priv->irqe)) { - /* Clear the pending error interrupt */ + /* Clear the pending error interrupt */ - up_clrpend_irq(priv->irqe); - _err("ERROR: interrupt STA: %08x\n", - up_serialin(priv, PIC32MX_UART_STA_OFFSET)); - handled = true; + up_clrpend_irq(priv->irqe); + _err("ERROR: interrupt STA: %08x\n", + up_serialin(priv, PIC32MX_UART_STA_OFFSET)); + handled = true; } #endif @@ -509,7 +514,8 @@ static int up_interrupt(int irq, void *context, void *arg) * longer has space to buffer the serial data. */ - if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & UART_STA_URXDA) == 0) + if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & + UART_STA_URXDA) == 0) { up_clrpend_irq(priv->irqrx); } @@ -518,8 +524,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Handle outgoing, transmit bytes The RT FIFO is configured to * interrupt only when the TX FIFO is empty. There are not many * options on trigger TX interrupts. The FIFO-not-full might generate - * better through-put but with a higher interrupt rate. FIFO-empty should - * lower the interrupt rate but result in a burstier output. If + * better through-put but with a higher interrupt rate. FIFO-empty + * should lower the interrupt rate but result in a burstier output. If * you change this, You will probably need to change the conditions for * clearing the pending TX interrupt below. * @@ -545,7 +551,8 @@ static int up_interrupt(int irq, void *context, void *arg) * to be sent. */ - if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & UART_STA_UTRMT) != 0) + if ((up_serialin(priv, PIC32MX_UART_STA_OFFSET) & + UART_STA_UTRMT) != 0) { up_clrpend_irq(priv->irqtx); } @@ -657,7 +664,8 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) /* Then return the actual received byte */ - return (int)(up_serialin(priv, PIC32MX_UART_RXREG_OFFSET) & UART_RXREG_MASK); + return (int)(up_serialin(priv, PIC32MX_UART_RXREG_OFFSET) & + UART_RXREG_MASK); } /**************************************************************************** @@ -678,8 +686,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) im = priv->im; if (enable) { - /* Receive an interrupt when their is anything in the Rx data register (or an Rx - * timeout occurs). + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx timeout occurs). */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -698,6 +706,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) up_disable_irq(priv->irqrx); DISABLE_RX(im); } + priv->im = im; leave_critical_section(flags); } diff --git a/arch/mips/src/pic32mx/pic32mx-spi.c b/arch/mips/src/pic32mx/pic32mx-spi.c index 9dfdd1d1e52..02664c1202e 100644 --- a/arch/mips/src/pic32mx/pic32mx-spi.c +++ b/arch/mips/src/pic32mx/pic32mx-spi.c @@ -108,19 +108,21 @@ static void spi_putreg(FAR struct pic32mx_dev_s *priv, /* SPI methods */ static int spi_lock(FAR struct spi_dev_s *dev, bool lock); -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency); +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); static void spi_setbits(FAR struct spi_dev_s *dev, int nbits); static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch); -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords); -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords); +static void spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *buffer, size_t nwords); +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords); /**************************************************************************** * Private Data ****************************************************************************/ #ifdef CONFIG_PIC32MX_SPI1 - static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -147,7 +149,10 @@ static const struct spi_ops_s g_spi1ops = static struct pic32mx_dev_s g_spi1dev = { - .spidev = { &g_spi1ops }, + .spidev = + { + &g_spi1ops + }, .base = PIC32MX_SPI1_K1BASE, #ifdef CONFIG_PIC32MX_SPI_INTERRUPTS .vector = PIC32MX_IRQ_SPI1, @@ -182,7 +187,10 @@ static const struct spi_ops_s g_spi2ops = static struct pic32mx_dev_s g_spi2dev = { - .spidev = { &g_spi2ops }, + .spidev = + { + &g_spi2ops + }, .base = PIC32MX_SPI2_K1BASE, #ifdef CONFIG_PIC32MX_SPI_INTERRUPTS .vector = PIC32MX_IRQ_SPI2, @@ -217,7 +225,10 @@ static const struct spi_ops_s g_spi3ops = static struct pic32mx_dev_s g_spi3dev = { - .spidev = { &g_spi3ops }, + .spidev = + { + &g_spi3ops + }, .base = PIC32MX_SPI3_K1BASE, #ifdef CONFIG_PIC32MX_SPI_INTERRUPTS .vector = PIC32MX_IRQ_SPI4, @@ -252,7 +263,10 @@ static const struct spi_ops_s g_spi4ops = static struct pic32mx_dev_s g_spi4dev = { - .spidev = { &g_spi4ops }, + .spidev = + { + &g_spi4ops + }, .base = PIC32MX_SPI4_K1BASE, #ifdef CONFIG_PIC32MX_SPI_INTERRUPTS .vector = PIC32MX_IRQ_SPI4, @@ -287,7 +301,8 @@ static struct pic32mx_dev_s g_spi4dev = ****************************************************************************/ #ifdef CONFIG_PIC32MX_SPI_REGDEBUG -static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) +static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, + unsigned int offset) { /* Last address, value, and count */ @@ -313,10 +328,11 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - _info("...\n"); - } + if (count == 4) + { + _info("...\n"); + } + return value; } } @@ -325,20 +341,20 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) else { - /* Did we print "..." for the previous value? */ + /* Did we print "..." for the previous value? */ - if (count > 3) - { - /* Yes.. then show how many times the value repeated */ + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ - _info("[repeats %d more times]\n", count-3); - } + _info("[repeats %d more times]\n", count - 3); + } - /* Save the new address, value, and count */ + /* Save the new address, value, and count */ - prevaddr = addr; - prevalue = value; - count = 1; + prevaddr = addr; + prevalue = value; + count = 1; } /* Show the register value read */ @@ -347,7 +363,8 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) return value; } #else -static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) +static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, + unsigned int offset) { return getreg32(priv->base + offset); } @@ -461,7 +478,8 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock) * ****************************************************************************/ -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency) { FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev; uint32_t divisor; @@ -732,14 +750,16 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) * nwords - the length of data to send from the buffer in number of words. * The wordsize is determined by the number of bits-per-word * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's * * Returned Value: * None * ****************************************************************************/ -static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, + size_t nwords) { FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev; FAR uint8_t *ptr = (FAR uint8_t *)buffer; @@ -760,20 +780,23 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size * receive buffer is not empty. */ - while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPIRBE) != 0); + while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & + SPI_STAT_SPIRBE) != 0); #else - /* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. In - * normal mode, the SPIRBF bit will be set when receive data is available. + /* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. + * In normal mode, the SPIRBF bit will be set when receive data is + * available. */ - while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) == 0); + while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & + SPI_STAT_SPIRBF) == 0); #endif - /* Read from the buffer register to clear the status bit */ + /* Read from the buffer register to clear the status bit */ - regval = spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET); - UNUSED(regval); - nwords--; + regval = spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET); + UNUSED(regval); + nwords--; } } @@ -787,16 +810,18 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size * dev - Device-specific state data * buffer - A pointer to the buffer in which to receive data * nwords - the length of data that can be received in the buffer in number - * of words. The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits > 8, the data is + * packed into uint16_t's * * Returned Value: * None * ****************************************************************************/ -static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords) { FAR struct pic32mx_dev_s *priv = (FAR struct pic32mx_dev_s *)dev; FAR uint8_t *ptr = (FAR uint8_t *)buffer; @@ -816,19 +841,22 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw * receive buffer is not empty. */ - while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPIRBE) != 0); + while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & + SPI_STAT_SPIRBE) != 0); #else - /* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. In - * normal mode, the SPIRBF bit will be set when receive data is available. + /* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. + * In normal mode, the SPIRBF bit will be set when receive data is + * available. */ - while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) == 0); + while ((spi_getreg(priv, PIC32MX_SPI_STAT_OFFSET) & + SPI_STAT_SPIRBF) == 0); #endif - /* Read the received data from the SPI Data Register */ + /* Read the received data from the SPI Data Register */ - *ptr++ = (uint8_t)spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET); - nwords--; + *ptr++ = (uint8_t)spi_getreg(priv, PIC32MX_SPI_BUF_OFFSET); + nwords--; } } @@ -888,10 +916,10 @@ FAR struct spi_dev_s *pic32mx_spibus_initialize(int port) } else #endif - { - spierr("ERROR: Unsupported port: %d\n", port); - return NULL; - } + { + spierr("ERROR: Unsupported port: %d\n", port); + return NULL; + } /* Disable SPI interrupts */ diff --git a/arch/mips/src/pic32mx/pic32mx-timerisr.c b/arch/mips/src/pic32mx/pic32mx-timerisr.c index 8a801eeecf4..bb7781c15f2 100644 --- a/arch/mips/src/pic32mx/pic32mx-timerisr.c +++ b/arch/mips/src/pic32mx/pic32mx-timerisr.c @@ -171,7 +171,7 @@ void mips_timer_initialize(void) putreg32((TIMER1_CON_TCKPS | TIMER1_CON_TCS), PIC32MX_TIMER1_CON); putreg32(0, PIC32MX_TIMER1_CNT); - putreg32(TIMER1_MATCH-1, PIC32MX_TIMER1_PR); + putreg32(TIMER1_MATCH - 1, PIC32MX_TIMER1_PR); putreg32(TIMER_CON_ON, PIC32MX_TIMER1_CONSET); /* Configure the timer interrupt */ diff --git a/arch/mips/src/pic32mz/pic32mz-dma.c b/arch/mips/src/pic32mz/pic32mz-dma.c index 4a606e4bd4e..e3e84e25145 100644 --- a/arch/mips/src/pic32mz/pic32mz-dma.c +++ b/arch/mips/src/pic32mz/pic32mz-dma.c @@ -902,7 +902,7 @@ void pic32mz_dma_free(DMA_HANDLE handle) up_clrpend_irq(dmach->irq); } -/******************************************************************************* +/**************************************************************************** * Name: pic32mz_dma_chcfg * * Description: @@ -910,7 +910,7 @@ void pic32mz_dma_free(DMA_HANDLE handle) * This config can be done during alloc, however if reconfig is needed, * this functions should be used. * - ******************************************************************************/ + ****************************************************************************/ int pic32mz_dma_chcfg(DMA_HANDLE handle, FAR const struct pic32mz_dma_chcfg_s *cfg) diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c index a83b173f853..6ce249947d6 100644 --- a/arch/mips/src/pic32mz/pic32mz-ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c @@ -179,8 +179,8 @@ /* Debug Configuration *****************************************************/ -/* Register/Descriptor debug -- can only happen of CONFIG_DEBUG_FEATURES is selected. - * This will probably generate much more output than you care to see. +/* Register/Descriptor debug -- can only happen of CONFIG_DEBUG_FEATURES is + * selecte. This will probably generate much more output than you care to see. */ #ifndef CONFIG_DEBUG_FEATURES @@ -363,8 +363,8 @@ union pic32mz_rxdesc_u struct pic32mz_rxdesc_s rxdesc; }; -/* The pic32mz_driver_s encapsulates all state information for a single hardware - * interface +/* The pic32mz_driver_s encapsulates all state information for a single + * single interface */ struct pic32mz_driver_s @@ -438,8 +438,10 @@ static void pic32mz_putreg(uint32_t val, uint32_t addr); /* Buffer and descriptor management */ #ifdef CONFIG_NET_DESCDEBUG -static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg); -static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, const char *msg); +static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, + const char *msg); +static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, + const char *msg); #else # define pic32mz_dumptxdesc(txdesc,msg) # define pic32mz_dumprxdesc(rxdesc,msg) @@ -447,11 +449,13 @@ static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, const char *msg) static inline void pic32mz_bufferinit(struct pic32mz_driver_s *priv); static uint8_t *pic32mz_allocbuffer(struct pic32mz_driver_s *priv); -static void pic32mz_freebuffer(struct pic32mz_driver_s *priv, uint8_t *buffer); +static void pic32mz_freebuffer(struct pic32mz_driver_s *priv, + uint8_t *buffer); static inline void pic32mz_txdescinit(struct pic32mz_driver_s *priv); static inline void pic32mz_rxdescinit(struct pic32mz_driver_s *priv); -static inline struct pic32mz_txdesc_s *pic32mz_txdesc(struct pic32mz_driver_s *priv); +static inline struct pic32mz_txdesc_s * + pic32mz_txdesc(struct pic32mz_driver_s *priv); static inline void pic32mz_txnext(struct pic32mz_driver_s *priv); static inline void pic32mz_rxreturn(struct pic32mz_rxdesc_s *rxdesc); static struct pic32mz_rxdesc_s *pic32mz_rxdesc(struct pic32mz_driver_s *priv); @@ -556,8 +560,8 @@ static void pic32mz_checkreg(uint32_t addr, uint32_t val, bool iswrite) static uint32_t count = 0; static bool prevwrite = false; - /* Is this the same value that we read from/wrote to the same register last time? - * Are we polling the register? If so, suppress the output. + /* Is this the same value that we read from/wrote to the same register + * last time? Are we polling the register? If so, suppress the output. */ if (addr == prevaddr && val == preval && prevwrite == iswrite) @@ -663,14 +667,17 @@ static void pic32mz_putreg(uint32_t val, uint32_t addr) ****************************************************************************/ #ifdef CONFIG_NET_DESCDEBUG -static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg) +static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, + const char *msg) { ninfo("TX Descriptor [%p]: %s\n", txdesc, msg); ninfo(" status: %08x\n", txdesc->status); - ninfo(" address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address)); + ninfo(" address: %08x [%08x]\n", + txdesc->address, VIRT_ADDR(txdesc->address)); ninfo(" tsv1: %08x\n", txdesc->tsv1); ninfo(" tsv2: %08x\n", txdesc->tsv2); - ninfo(" nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted)); + ninfo(" nexted: %08x [%08x]\n", + txdesc->nexted, VIRT_ADDR(txdesc->nexted)); } #endif @@ -690,14 +697,17 @@ static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg) ****************************************************************************/ #ifdef CONFIG_NET_DESCDEBUG -static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, const char *msg) +static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, + const char *msg) { ninfo("RX Descriptor [%p]: %s\n", rxdesc, msg); ninfo(" status: %08x\n", rxdesc->status); - ninfo(" address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address)); + ninfo(" address: %08x [%08x]\n", + rxdesc->address, VIRT_ADDR(rxdesc->address)); ninfo(" rsv1: %08x\n", rxdesc->rsv1); ninfo(" rsv2: %08x\n", rxdesc->rsv2); - ninfo(" nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted)); + ninfo(" nexted: %08x [%08x]\n", + rxdesc->nexted, VIRT_ADDR(rxdesc->nexted)); } #endif @@ -835,7 +845,8 @@ static inline void pic32mz_txdescinit(struct pic32mz_driver_s *priv) up_flush_dcache((uintptr_t)g_txdesc, (uintptr_t)g_txdesc + - CONFIG_PIC32MZ_ETH_NTXDESC * sizeof(union pic32mz_txdesc_u)); + CONFIG_PIC32MZ_ETH_NTXDESC * + sizeof(union pic32mz_txdesc_u)); /* Position the Tx index to the first descriptor in the ring */ @@ -912,7 +923,8 @@ static inline void pic32mz_rxdescinit(struct pic32mz_driver_s *priv) up_flush_dcache((uintptr_t)g_rxdesc, (uintptr_t)g_rxdesc + - CONFIG_PIC32MZ_ETH_NRXDESC * sizeof(union pic32mz_rxdesc_u)); + CONFIG_PIC32MZ_ETH_NRXDESC * + sizeof(union pic32mz_rxdesc_u)); /* Update the ETHRXST register with the physical address of the head of the * RX descriptors list. @@ -936,7 +948,8 @@ static inline void pic32mz_rxdescinit(struct pic32mz_driver_s *priv) * ****************************************************************************/ -static inline struct pic32mz_txdesc_s *pic32mz_txdesc(struct pic32mz_driver_s *priv) +static inline struct pic32mz_txdesc_s * + pic32mz_txdesc(struct pic32mz_driver_s *priv) { struct pic32mz_txdesc_s *txdesc; @@ -1067,8 +1080,8 @@ static struct pic32mz_rxdesc_s *pic32mz_rxdesc(struct pic32mz_driver_s *priv) /* Inspect the list of RX descriptors to see if the EOWN bit is cleared. * If it is, this descriptor is now under software control and a message was - * received. Use SOP and EOP to extract the message, use BYTE_COUNT, RXF_RSV, - * RSV and PKT_CHECKSUM to get the message characteristics. + * received. Use SOP and EOP to extract the message, use BYTE_COUNT, + * RXF_RSV, RSV and PKT_CHECKSUM to get the message characteristics. */ for (i = 0; i < CONFIG_PIC32MZ_ETH_NRXDESC; i++) @@ -1080,7 +1093,8 @@ static struct pic32mz_rxdesc_s *pic32mz_rxdesc(struct pic32mz_driver_s *priv) /* Forces the first RX descriptor to be re-read from physical memory */ up_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(union pic32mz_rxdesc_u)); + (uintptr_t)rxdesc + + sizeof(union pic32mz_rxdesc_u)); if ((rxdesc->status & RXDESC_STATUS_EOWN) == 0) { @@ -1131,7 +1145,8 @@ static int pic32mz_transmit(struct pic32mz_driver_s *priv) /* Increment statistics and dump the packet (if so configured) */ NETDEV_TXPACKETS(&priv->pd_dev); - pic32mz_dumppacket("Transmit packet", priv->pd_dev.d_buf, priv->pd_dev.d_len); + pic32mz_dumppacket("Transmit packet", + priv->pd_dev.d_buf, priv->pd_dev.d_len); /* Flush the content of the TX buffer into physical memory */ @@ -1200,8 +1215,8 @@ static int pic32mz_transmit(struct pic32mz_driver_s *priv) /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->pd_txtimeout, PIC32MZ_TXTIMEOUT, pic32mz_txtimeout_expiry, - 1, (uint32_t)priv); + (void)wd_start(priv->pd_txtimeout, PIC32MZ_TXTIMEOUT, + pic32mz_txtimeout_expiry, 1, (uint32_t)priv); return OK; } @@ -1266,8 +1281,8 @@ static int pic32mz_txpoll(struct net_driver_s *dev) if (!devif_loopback(&priv->pd_dev)) { - /* Send this packet. In this context, we know that there is space for - * at least one more packet in the descriptor list. + /* Send this packet. In this context, we know that there is space + * for at least one more packet in the descriptor list. */ pic32mz_transmit(priv); @@ -1401,7 +1416,7 @@ static void pic32mz_timerpoll(struct pic32mz_driver_s *priv) * * Description: * While processing an RxDone event, higher logic decides to send a packet, - * possibly a response to the incoming packet (but probably not, in reality). + * possibly a response to the incoming packet (but probably not, in reality) * However, since the Rx and Tx operations are decoupled, there is no * guarantee that there will be a Tx descriptor available at that time. * This function will perform that check and, if no Tx descriptor is @@ -1508,8 +1523,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv) pic32mz_rxreturn(rxdesc); } - /* If the packet length is greater then the buffer, then we cannot accept - * the packet. Also, since the DMA packet buffers are set up to + /* If the packet length is greater then the buffer, then we cannot + * accept the packet. Also, since the DMA packet buffers are set up to * be the same size as our max packet size, any fragments also * imply that the packet is too big. */ @@ -1732,9 +1747,9 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv) DEBUGASSERT(pic32mz_txdesc(priv) != NULL); - /* Inspect the list of TX descriptors to see if the EOWN bit is cleared. If it - * is, this descriptor is now under software control and the message was - * transmitted. Use TSV to check for the transmission result. + /* Inspect the list of TX descriptors to see if the EOWN bit is cleared. + * If it is, this descriptor is now under software control and the message + * was transmitted. Use TSV to check for the transmission result. */ for (i = 0; i < CONFIG_PIC32MZ_ETH_NTXDESC; i++) @@ -1747,7 +1762,8 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv) */ up_invalidate_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(union pic32mz_txdesc_u)); + (uintptr_t)txdesc + + sizeof(union pic32mz_txdesc_u)); /* Check if software owns this descriptor */ @@ -1775,7 +1791,8 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv) /* Flush the content of the modified TX descriptor. */ up_flush_dcache((uintptr_t)txdesc, - (uintptr_t)txdesc + sizeof(union pic32mz_txdesc_u)); + (uintptr_t)txdesc + + sizeof(union pic32mz_txdesc_u)); } } } @@ -1881,9 +1898,9 @@ static void pic32mz_interrupt_work(void *arg) /* Receive Normal Events **********************************************/ - /* RXACT: Receive Activity Interrupt. This bit is set whenever RX packet - * data is stored in the RXBM FIFO. It is cleared by either a Reset or CPU - * write of a '1' to the CLR register. + /* RXACT: Receive Activity Interrupt. This bit is set whenever RX + * packet data is stored in the RXBM FIFO. It is cleared by either + * a Reset or CPU write of a '1' to the CLR register. */ /* PKTPEND: Packet Pending Interrupt. This bit is set when the BUFCNT @@ -1892,9 +1909,9 @@ static void pic32mz_interrupt_work(void *arg) * Writing a '0' or a '1' has no effect. */ - /* RXDONE: Receive Done Interrupt. This bit is set whenever an RX packet - * is successfully received. It is cleared by either a Reset or CPU - * write of a '1' to the CLR register. + /* RXDONE: Receive Done Interrupt. This bit is set whenever an RX + * packet is successfully received. It is cleared by either a Reset + * or CPU write of a '1' to the CLR register. */ if ((status & ETH_INT_RXDONE) != 0) @@ -2080,8 +2097,8 @@ static void pic32mz_txtimeout_work(void *arg) (void)pic32mz_ifup(&priv->pd_dev); - /* Then poll the network for new XMIT data (We are guaranteed to have a free - * buffer here). + /* Then poll the network for new XMIT data (We are guaranteed to have + * a free buffer here). */ pic32mz_poll(priv); @@ -2242,7 +2259,7 @@ static int pic32mz_ifup(struct net_driver_s *dev) /* Pin Configuration: * * No GPIO pin configuration is required. Enabling the Ethernet Controller - * will configure the I/O pin direction as defined by the Ethernet Controller + * will configure the IO pin direction as defined by the Ethernet Controller * control bits. The port TRIS and LATCH registers will be overridden. * * I/O Pin MII RMII Pin Description @@ -2345,14 +2362,16 @@ static int pic32mz_ifup(struct net_driver_s *dev) /* Use EMAC1IPGR for setting the non back-to-back inter-packet gap */ - pic32mz_putreg(((12 << EMAC1_IPGR_GAP1_SHIFT) | (12 << EMAC1_IPGR_GAP2_SHIFT)), + pic32mz_putreg(((12 << EMAC1_IPGR_GAP1_SHIFT) | + (12 << EMAC1_IPGR_GAP2_SHIFT)), PIC32MZ_EMAC1_IPGR); /* Set the collision window and the maximum number of retransmissions in * EMAC1CLRT. */ - pic32mz_putreg(((15 << EMAC1_CLRT_RETX_SHIFT) | (55 << EMAC1_CLRT_CWINDOW_SHIFT)), + pic32mz_putreg(((15 << EMAC1_CLRT_RETX_SHIFT) | + (55 << EMAC1_CLRT_CWINDOW_SHIFT)), PIC32MZ_EMAC1_CLRT); /* Set the maximum frame length in EMAC1MAXF. "This field resets to @@ -2384,20 +2403,26 @@ static int pic32mz_ifup(struct net_driver_s *dev) #else regval = pic32mz_getreg(PIC32MZ_EMAC1_SA0); priv->pd_dev.d_mac.ether.ether_addr_octet[4] = (uint32_t)(regval & 0xff); - priv->pd_dev.d_mac.ether.ether_addr_octet[5] = (uint32_t)((regval >> 8) & 0xff); + priv->pd_dev.d_mac.ether.ether_addr_octet[5] = (uint32_t)((regval >> 8) & + 0xff); regval = pic32mz_getreg(PIC32MZ_EMAC1_SA1); priv->pd_dev.d_mac.ether.ether_addr_octet[2] = (uint32_t)(regval & 0xff); - priv->pd_dev.d_mac.ether.ether_addr_octet[3] = (uint32_t)((regval >> 8) & 0xff); + priv->pd_dev.d_mac.ether.ether_addr_octet[3] = (uint32_t)((regval >> 8) & + 0xff); regval = pic32mz_getreg(PIC32MZ_EMAC1_SA2); priv->pd_dev.d_mac.ether.ether_addr_octet[0] = (uint32_t)(regval & 0xff); - priv->pd_dev.d_mac.ether.ether_addr_octet[1] = (uint32_t)((regval >> 8) & 0xff); + priv->pd_dev.d_mac.ether.ether_addr_octet[1] = (uint32_t)((regval >> 8) & + 0xff); ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1], - dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3], - dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]); + dev->d_mac.ether.ether_addr_octet[0], + dev->d_mac.ether.ether_addr_octet[1], + dev->d_mac.ether.ether_addr_octet[2], + dev->d_mac.ether.ether_addr_octet[3], + dev->d_mac.ether.ether_addr_octet[4], + dev->d_mac.ether.ether_addr_octet[5]); #endif /* Continue Ethernet Controller Initialization ****************************/ @@ -2415,8 +2440,8 @@ static int pic32mz_ifup(struct net_driver_s *dev) /* Set the RX filters by updating the ETHHT0, ETHHT1, ETHPMM0, ETHPMM1, * ETHPMCS and ETHRXFC registers. * - * Set up RX filter and configure to accept broadcast addresses and multicast - * addresses (if so configured). NOTE: There is a selection + * Set up RX filter and configure to accept broadcast addresses and + * multicast addresses (if so configured). NOTE: There is a selection * CONFIG_NET_BROADCAST, but this enables receipt of UDP broadcast packets * inside of the stack. */ @@ -2472,13 +2497,13 @@ static int pic32mz_ifup(struct net_driver_s *dev) pic32mz_putreg(0xffffffff, PIC32MZ_ETH_IRQCLR); - /* Configure interrupts. The Ethernet interrupt was attached during one-time - * initialization, so we only need to set the interrupt priority, configure - * interrupts, and enable them. + /* Configure interrupts. The Ethernet interrupt was attached during + * one-time initialization, so we only need to set the interrupt priority, + * configure interrupts, and enable them. */ - /* If the user provided an interrupt priority, then set the interrupt to that - * priority + /* If the user provided an interrupt priority, then set the interrupt + * to that priority. */ #if defined(CONFIG_PIC32MZ_ETH_PRIORITY) && defined(CONFIG_ARCH_IRQPRIO) @@ -2588,8 +2613,8 @@ static void pic32mz_txavail_work(void *arg) if (pic32mz_txdesc(priv) != NULL) { - /* If so, then poll the network for new XMIT data. First allocate a buffer - * to perform the poll + /* If so, then poll the network for new XMIT data. + * First allocate a buffer to perform the poll */ pic32mz_poll(priv); @@ -2671,8 +2696,8 @@ static int pic32mz_addmac(struct net_driver_s *dev, const uint8_t *mac) * Function: pic32mz_rmmac * * Description: - * NuttX Callback: Remove the specified MAC address from the hardware multicast - * address filtering + * NuttX Callback: Remove the specified MAC address from the hardware + * multicast address filtering. * * Input Parameters: * dev - Reference to the NuttX driver state structure @@ -2768,7 +2793,8 @@ static void pic32mz_phybusywait(void) ****************************************************************************/ #ifdef PIC32MZ_HAVE_PHY -static void pic32mz_phywrite(uint8_t phyaddr, uint8_t regaddr, uint16_t phydata) +static void pic32mz_phywrite(uint8_t phyaddr, uint8_t regaddr, + uint16_t phydata) { uint32_t regval; @@ -3064,8 +3090,9 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) #ifdef CONFIG_ETH0_PHY_DP83848C /* The RMII/MII of operation can be selected by strap options or register - * control (using the RBR register). For RMII mode, it is required to use the - * strap option, since it requires a 50 MHz clock instead of the normal 25 MHz. + * control (using the RBR register). For RMII mode, it is required to use + * the strap option, since it requires a 50 MHz clock instead of the normal + * 25 Mhz. */ #endif @@ -3366,8 +3393,8 @@ static void pic32mz_macmode(uint8_t mode) /* Set MAC to operate in full duplex mode with CRC and Pad enabled */ - pic32mz_putreg((EMAC1_CFG2_FULLDPLX | EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), - PIC32MZ_EMAC1_CFG2SET); + pic32mz_putreg((EMAC1_CFG2_FULLDPLX | EMAC1_CFG2_CRCEN | + EMAC1_CFG2_PADCRCEN), PIC32MZ_EMAC1_CFG2SET); } else { @@ -3378,7 +3405,8 @@ static void pic32mz_macmode(uint8_t mode) /* Set MAC to operate in half duplex mode with CRC and Pad enabled */ pic32mz_putreg(EMAC1_CFG2_FULLDPLX, PIC32MZ_EMAC1_CFG2CLR); - pic32mz_putreg((EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), PIC32MZ_EMAC1_CFG2SET); + pic32mz_putreg((EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), + PIC32MZ_EMAC1_CFG2SET); } /* Set the RMII MAC speed. */ @@ -3432,7 +3460,8 @@ static void pic32mz_ethreset(struct pic32mz_driver_s *priv) /* Turn the Ethernet Controller off: Clear the ON, RXEN and TXRTS bits */ - pic32mz_putreg(ETH_CON1_RXEN | ETH_CON1_TXRTS | ETH_CON1_ON, PIC32MZ_ETH_CON1CLR); + pic32mz_putreg(ETH_CON1_RXEN | ETH_CON1_TXRTS | ETH_CON1_ON, + PIC32MZ_ETH_CON1CLR); /* Wait activity abort by polling the ETHBUSY bit */ @@ -3473,9 +3502,10 @@ static void pic32mz_ethreset(struct pic32mz_driver_s *priv) /* Put the MAC into the reset state */ - pic32mz_putreg((EMAC1_CFG1_TXRST | EMAC1_CFG1_MCSTXRST | EMAC1_CFG1_RXRST | - EMAC1_CFG1_MCSRXRST | EMAC1_CFG1_SIMRST | EMAC1_CFG1_SOFTRST), - PIC32MZ_EMAC1_CFG1); + pic32mz_putreg((EMAC1_CFG1_TXRST | EMAC1_CFG1_MCSTXRST | + EMAC1_CFG1_RXRST | EMAC1_CFG1_MCSRXRST | + EMAC1_CFG1_SIMRST | EMAC1_CFG1_SOFTRST), + PIC32MZ_EMAC1_CFG1); /* Take the MAC out of the reset state */ diff --git a/arch/mips/src/pic32mz/pic32mz-exception.c b/arch/mips/src/pic32mz/pic32mz-exception.c index 0c19918cf39..c6ce5ee7510 100644 --- a/arch/mips/src/pic32mz/pic32mz-exception.c +++ b/arch/mips/src/pic32mz/pic32mz-exception.c @@ -59,13 +59,13 @@ * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_exception * * Description: * Called from assembly language logic on all other exceptions. * - ************************************************************************************/ + ****************************************************************************/ uint32_t *pic32mz_exception(uint32_t *regs) { diff --git a/arch/mips/src/pic32mz/pic32mz-gpioirq.c b/arch/mips/src/pic32mz/pic32mz-gpioirq.c index 9d5b5f3ad23..8277b0dcccb 100644 --- a/arch/mips/src/pic32mz/pic32mz-gpioirq.c +++ b/arch/mips/src/pic32mz/pic32mz-gpioirq.c @@ -286,7 +286,8 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg) { /* Yes.. call the attached handler */ - status = handler(irq, context, handlers->handler[i].arg); + status = handler(irq, context, + handlers->handler[i].arg); /* Keep track of the status of the last handler that * failed. @@ -335,7 +336,8 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg) { /* Yes.. call the attached handler */ - status = handler(irq, context, handlers->handler[i].arg); + status = handler(irq, context, + handlers->handler[i].arg); /* Keep track of the status of the last handler that * failed. @@ -353,7 +355,6 @@ static int pic32mz_cninterrupt(int irq, FAR void *context, FAR void *arg) putreg32(pending, base + PIC32MZ_IOPORT_CNFCLR_OFFSET); } - } /* Clear the pending interrupt */ @@ -599,7 +600,8 @@ void pic32mz_gpioirqenable(pinset_t pinset) { /* Enable edge detect. */ - putreg32(IOPORT_CNCON_EDGEDETECT, base + PIC32MZ_IOPORT_CNCONSET_OFFSET); + putreg32(IOPORT_CNCON_EDGEDETECT, + base + PIC32MZ_IOPORT_CNCONSET_OFFSET); if (pic32mz_edgemode(pinset) == GPIO_EDGE_RISING) { diff --git a/arch/mips/src/pic32mz/pic32mz-i2c.c b/arch/mips/src/pic32mz/pic32mz-i2c.c index ff7bc4c3e71..7f411656e27 100644 --- a/arch/mips/src/pic32mz/pic32mz-i2c.c +++ b/arch/mips/src/pic32mz/pic32mz-i2c.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/mips/src/pic32mz/chip/pic32mz-i2c.c * * Copyright (C) 2018 Abdelatif Guettouche. All rights reserved. @@ -31,11 +31,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -66,14 +66,14 @@ #ifdef CONFIG_PIC32MZ_I2C -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ -/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead, - * CPU-intensive polling will be used. +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead CPU-intensive polling will be used. */ /* Interrupt wait timeout in seconds and milliseconds */ @@ -91,14 +91,16 @@ #ifndef CONFIG_PIC32MZ_I2CTIMEOTICKS # define CONFIG_PIC32MZ_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_PIC32MZ_I2CTIMEOSEC) + MSEC2TICK(CONFIG_PIC32MZ_I2CTIMEOMS)) + (SEC2TICK(CONFIG_PIC32MZ_I2CTIMEOSEC) +\ + MSEC2TICK(CONFIG_PIC32MZ_I2CTIMEOMS)) #endif #ifndef CONFIG_PIC32MZ_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_PIC32MZ_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_PIC32MZ_I2CTIMEOTICKS) +# define CONFIG_PIC32MZ_I2C_DYNTIMEO_STARTSTOP \ + TICK2USEC(CONFIG_PIC32MZ_I2CTIMEOTICKS) #endif -/* Debug ****************************************************************************/ +/* Debug *********************************************************************/ /* I2C event trace logic. */ @@ -121,9 +123,9 @@ # error I2C slave logic is not supported yet for PIC32MZ #endif -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ /* Interrupt state */ @@ -222,9 +224,9 @@ struct pic32mz_i2c_priv_s uint32_t status; /* End of transfer status */ }; -/************************************************************************************ +/**************************************************************************** * Private Function Prototypes - ************************************************************************************/ + ****************************************************************************/ static inline uint32_t pic32mz_i2c_getreg(FAR struct pic32mz_i2c_priv_s *priv, uint8_t offset); @@ -239,11 +241,14 @@ static inline void pic32mz_i2c_sem_wait(FAR struct pic32mz_i2c_priv_s *priv); static useconds_t pic32mz_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs); #endif /* CONFIG_PIC32MZ_I2C_DYNTIMEO */ -static inline int pic32mz_i2c_sem_waitdone(FAR struct pic32mz_i2c_priv_s *priv); -static inline void pic32mz_i2c_sem_waitidle(FAR struct pic32mz_i2c_priv_s *priv); +static inline int + pic32mz_i2c_sem_waitdone(FAR struct pic32mz_i2c_priv_s *priv); +static inline void + pic32mz_i2c_sem_waitidle(FAR struct pic32mz_i2c_priv_s *priv); static inline void pic32mz_i2c_sem_post(FAR struct pic32mz_i2c_priv_s *priv); static inline void pic32mz_i2c_sem_init(FAR struct pic32mz_i2c_priv_s *priv); -static inline void pic32mz_i2c_sem_destroy(FAR struct pic32mz_i2c_priv_s *priv); +static inline void + pic32mz_i2c_sem_destroy(FAR struct pic32mz_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE static void pic32mz_i2c_tracereset(FAR struct pic32mz_i2c_priv_s *priv); @@ -256,17 +261,22 @@ static void pic32mz_i2c_tracedump(FAR struct pic32mz_i2c_priv_s *priv); static inline int pic32mz_i2c_setbaudrate(FAR struct pic32mz_i2c_priv_s *priv, uint32_t frequency); -static inline void pic32mz_i2c_send_start(FAR struct pic32mz_i2c_priv_s *priv); +static inline void + pic32mz_i2c_send_start(FAR struct pic32mz_i2c_priv_s *priv); static inline void pic32mz_i2c_send_stop(FAR struct pic32mz_i2c_priv_s *priv); -static inline void pic32mz_i2c_send_repeatedstart(FAR struct pic32mz_i2c_priv_s *priv); +static inline void + pic32mz_i2c_send_repeatedstart(FAR struct pic32mz_i2c_priv_s *priv); static inline void pic32mz_i2c_send_ack(FAR struct pic32mz_i2c_priv_s *priv, bool ack); static inline void pic32mz_i2c_transmitbyte(struct pic32mz_i2c_priv_s *priv, uint8_t data); -static inline uint32_t pic32mz_i2c_receivebyte(struct pic32mz_i2c_priv_s *priv); +static inline uint32_t + pic32mz_i2c_receivebyte(struct pic32mz_i2c_priv_s *priv); -static inline uint32_t pic32mz_i2c_getstatus(FAR struct pic32mz_i2c_priv_s *priv); -static inline bool pic32mz_i2c_master_inactive(FAR struct pic32mz_i2c_priv_s *priv); +static inline uint32_t + pic32mz_i2c_getstatus(FAR struct pic32mz_i2c_priv_s *priv); +static inline bool + pic32mz_i2c_master_inactive(FAR struct pic32mz_i2c_priv_s *priv); static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s * priv); @@ -283,9 +293,9 @@ static int pic32mz_i2c_transfer(FAR struct i2c_master_s *dev, static int pic32mz_i2c_reset(FAR struct i2c_master_s *dev); #endif -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ /* Trace events strings */ @@ -457,9 +467,9 @@ static struct pic32mz_i2c_priv_s pic32mz_i2c5_priv = }; #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_I2C_TRACE static void pic32mz_i2c_traceclear(FAR struct pic32mz_i2c_priv_s *priv) @@ -561,20 +571,21 @@ static void pic32mz_i2c_tracedump(FAR struct pic32mz_i2c_priv_s *priv) { trace = &priv->trace[i]; syslog(LOG_DEBUG, - "%2d. STATUS: %04x COUNT: %3d EVENT: %s(%2d) PARM: %08x TIME: %d\n", + "%2d. STATUS: %04x COUNT: %3d EVENT: %s(%2d) " + "PARM: %08x TIME: %d\n", i + 1, trace->status, trace->count, g_trace_names[trace->event], trace->event, trace->parm, trace->time - priv->start_time); } } #endif /* CONFIG_I2C_TRACE */ -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_getreg * * Description: * Get a 32-bit register value by offset * - ************************************************************************************/ + ****************************************************************************/ static inline uint32_t pic32mz_i2c_getreg(FAR struct pic32mz_i2c_priv_s *priv, uint8_t offset) @@ -582,13 +593,13 @@ static inline uint32_t pic32mz_i2c_getreg(FAR struct pic32mz_i2c_priv_s *priv, return getreg32(priv->config->base + offset); } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_putreg * * Description: * Put a 32-bit register value by offset * - ************************************************************************************/ + ****************************************************************************/ static inline void pic32mz_i2c_putreg(FAR struct pic32mz_i2c_priv_s *priv, uint8_t offset, uint32_t value) @@ -596,13 +607,13 @@ static inline void pic32mz_i2c_putreg(FAR struct pic32mz_i2c_priv_s *priv, putreg32(value, priv->config->base + offset); } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_modifyreg * * Description: * Modify a 32-bit register value by offset * - ************************************************************************************/ + ****************************************************************************/ static inline void pic32mz_i2c_modifyreg(FAR struct pic32mz_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, @@ -611,13 +622,13 @@ static inline void pic32mz_i2c_modifyreg(FAR struct pic32mz_i2c_priv_s *priv, modifyreg32(priv->config->base + offset, clearbits, setbits); } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_sem_wait * * Description: * Take the exclusive access, waiting as necessary * - ************************************************************************************/ + ****************************************************************************/ static inline void pic32mz_i2c_sem_wait(FAR struct pic32mz_i2c_priv_s *priv) { @@ -638,13 +649,14 @@ static inline void pic32mz_i2c_sem_wait(FAR struct pic32mz_i2c_priv_s *priv) while (ret == -EINTR); } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_tousecs * * Description: - * Return a micro-second delay based on the number of bytes left to be processed. + * Return a micro-second delay based on the number of bytes left to be + * processed. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_PIC32MZ_I2C_DYNTIMEO static useconds_t pic32mz_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) @@ -667,7 +679,7 @@ static useconds_t pic32mz_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) } #endif -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_sem_waitdone * * Description: @@ -676,10 +688,11 @@ static useconds_t pic32mz_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) * There are two versions of this function. The first is included when using * interrupts while the second is used if polling (CONFIG_I2C_POLLED=y). * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static inline int pic32mz_i2c_sem_waitdone(FAR struct pic32mz_i2c_priv_s *priv) +static inline int + pic32mz_i2c_sem_waitdone(FAR struct pic32mz_i2c_priv_s *priv) { struct timespec abstime; irqstate_t flags; @@ -752,7 +765,8 @@ static inline int pic32mz_i2c_sem_waitdone(FAR struct pic32mz_i2c_priv_s *priv) return ret; } #else -static inline int pic32mz_i2c_sem_waitdone(FAR struct pic32mz_i2c_priv_s *priv) +static inline int + pic32mz_i2c_sem_waitdone(FAR struct pic32mz_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -803,15 +817,16 @@ static inline int pic32mz_i2c_sem_waitdone(FAR struct pic32mz_i2c_priv_s *priv) } #endif -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_sem_waitidle * * Description: * Wait for the bus to be in idle. * - ************************************************************************************/ + ****************************************************************************/ -static inline void pic32mz_i2c_sem_waitidle(FAR struct pic32mz_i2c_priv_s *priv) +static inline void + pic32mz_i2c_sem_waitidle(FAR struct pic32mz_i2c_priv_s *priv) { uint32_t timeout; uint32_t start; @@ -832,8 +847,8 @@ static inline void pic32mz_i2c_sem_waitidle(FAR struct pic32mz_i2c_priv_s *priv) { elapsed = clock_systimer() - start; - /* The bus is idle if the five least signifcant bits of I2CxCON are cleared, - * and the I2CxSTAT flag is cleared. + /* The bus is idle if the five least signifcant bits of I2CxCON + * are cleared and the I2CxSTAT flag is cleared. */ con = pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET); @@ -850,26 +865,26 @@ static inline void pic32mz_i2c_sem_waitidle(FAR struct pic32mz_i2c_priv_s *priv) i2cinfo("Timeout with I2CxCON: %04x I2CxSTAT: %04x\n", con, stat); } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_sem_post * * Description: * Release the mutual exclusion semaphore * - ************************************************************************************/ + ****************************************************************************/ static inline void pic32mz_i2c_sem_post(FAR struct pic32mz_i2c_priv_s *priv) { nxsem_post(&priv->sem_excl); } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_sem_init * * Description: * Initialize semaphores * - ************************************************************************************/ + ****************************************************************************/ static inline void pic32mz_i2c_sem_init(FAR struct pic32mz_i2c_priv_s *priv) { @@ -885,15 +900,16 @@ static inline void pic32mz_i2c_sem_init(FAR struct pic32mz_i2c_priv_s *priv) #endif } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_sem_destroy * * Description: * Destroy semaphores. * - ************************************************************************************/ + ****************************************************************************/ -static inline void pic32mz_i2c_sem_destroy(FAR struct pic32mz_i2c_priv_s *priv) +static inline void + pic32mz_i2c_sem_destroy(FAR struct pic32mz_i2c_priv_s *priv) { nxsem_destroy(&priv->sem_excl); #ifndef CONFIG_I2C_POLLED @@ -901,13 +917,13 @@ static inline void pic32mz_i2c_sem_destroy(FAR struct pic32mz_i2c_priv_s *priv) #endif } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_isr_process * * Description: * Common interrupt service routine * - ************************************************************************************/ + ****************************************************************************/ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv) { @@ -963,8 +979,8 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv) /* This state is reached either after sending the address to the slave, * or, in the case of multi-byte buffer, after sending a byte. - * We should first check that the previous transmission is not in progress, - * and that the slave had acknowledged it. + * We should first check that the previous transmission is not in + * progress, and that the slave had acknowledged it. */ case PROCESS_STATE_SEND_DATA: @@ -980,7 +996,8 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv) if ((status & I2C_STAT_ACKSTAT) == 0) { /* We need to keep one byte to send before we leave this state. - * This way we can trigger an interrupt and move to the next state. + * This way we can trigger an interrupt and move to the next + * state. */ if (priv->dcnt > 1) @@ -1004,8 +1021,8 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv) /* This state is reached after sending the address to the slave with * the read bit set, or, in the case of multi-byte transfer, * after reading the first byte. - * We should first check that the previous transmission is not in progress, - * and that the slave had acknowledged it. + * We should first check that the previous transmission is not in + * progress, and that the slave had acknowledged it. */ case PROCESS_STATE_ENABLE_READ: @@ -1026,7 +1043,8 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv) if (pic32mz_i2c_master_inactive(priv)) { - pic32mz_i2c_putreg(priv, PIC32MZ_I2C_CONSET_OFFSET, I2C_CON_RCEN); + pic32mz_i2c_putreg(priv, PIC32MZ_I2C_CONSET_OFFSET, + I2C_CON_RCEN); priv->process_state = PROCESS_STATE_READ_DATA; } @@ -1072,7 +1090,8 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv) #ifdef CONFIG_I2C_POLLED leave_critical_section(flags); #endif - /* Go back and re-enable read mode to handle the rest of the data. + /* Go back and re-enable read mode to handle the rest of + * the data. * It is cleared by the hardware at the end of the eighth bit. */ @@ -1286,13 +1305,13 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_isr * * Description: * Common I2C interrupt service routine. * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_I2C_POLLED static int pic32mz_i2c_isr(int irq, void *context, FAR void *arg) @@ -1304,13 +1323,13 @@ static int pic32mz_i2c_isr(int irq, void *context, FAR void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_setbaudrate * * Description: * Calculates the value of the baudrate. * - ************************************************************************************/ + ****************************************************************************/ static inline int pic32mz_i2c_setbaudrate(FAR struct pic32mz_i2c_priv_s *priv, uint32_t frequency) @@ -1339,11 +1358,13 @@ static inline int pic32mz_i2c_setbaudrate(FAR struct pic32mz_i2c_priv_s *priv, if (frequency == 400000) { - pic32mz_i2c_putreg(priv, PIC32MZ_I2C_CONCLR_OFFSET, I2C_CON_DISSLW); + pic32mz_i2c_putreg(priv, PIC32MZ_I2C_CONCLR_OFFSET, + I2C_CON_DISSLW); } else { - pic32mz_i2c_putreg(priv, PIC32MZ_I2C_CONSET_OFFSET, I2C_CON_DISSLW); + pic32mz_i2c_putreg(priv, PIC32MZ_I2C_CONSET_OFFSET, + I2C_CON_DISSLW); } } } @@ -1351,32 +1372,34 @@ static inline int pic32mz_i2c_setbaudrate(FAR struct pic32mz_i2c_priv_s *priv, return OK; } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_send_start * * Description: * Initiate a start condition. * - ************************************************************************************/ + ****************************************************************************/ -static inline void pic32mz_i2c_send_start(FAR struct pic32mz_i2c_priv_s *priv) +static inline void + pic32mz_i2c_send_start(FAR struct pic32mz_i2c_priv_s *priv) { pic32mz_i2c_putreg(priv, PIC32MZ_I2C_CONSET_OFFSET, I2C_CON_SEN); /* To avoid bus collision during polling. */ #ifdef CONFIG_I2C_POLLED - while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET) & I2C_CON_SEN) != 0); + while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET) & + I2C_CON_SEN) != 0); #endif } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_send_stop * * Description: * Initiate a stop condition. * - ************************************************************************************/ + ****************************************************************************/ static inline void pic32mz_i2c_send_stop(FAR struct pic32mz_i2c_priv_s *priv) { @@ -1385,36 +1408,39 @@ static inline void pic32mz_i2c_send_stop(FAR struct pic32mz_i2c_priv_s *priv) /* To avoid bus collision during polling. */ #ifdef CONFIG_I2C_POLLED - while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET) & I2C_CON_PEN) != 0); + while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET) & + I2C_CON_PEN) != 0); #endif } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_send_repeatedstart * * Description: * Initiate a repeated start condition. * - ************************************************************************************/ + ****************************************************************************/ -static inline void pic32mz_i2c_send_repeatedstart(FAR struct pic32mz_i2c_priv_s *priv) +static inline void + pic32mz_i2c_send_repeatedstart(FAR struct pic32mz_i2c_priv_s *priv) { pic32mz_i2c_putreg(priv, PIC32MZ_I2C_CONSET_OFFSET, I2C_CON_RSEN); /* To avoid bus collision during polling. */ #ifdef CONFIG_I2C_POLLED - while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET) & I2C_CON_RSEN) != 0); + while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET) & + I2C_CON_RSEN) != 0); #endif } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_send_ack * * Description: * Issue an ACK or a NACK. * - ************************************************************************************/ + ****************************************************************************/ static inline void pic32mz_i2c_send_ack(FAR struct pic32mz_i2c_priv_s *priv, bool ack) @@ -1433,17 +1459,18 @@ static inline void pic32mz_i2c_send_ack(FAR struct pic32mz_i2c_priv_s *priv, /* To avoid bus collision during polling. */ #ifdef CONFIG_I2C_POLLED - while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET) & I2C_CON_ACKEN) != 0); + while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_CON_OFFSET) & + I2C_CON_ACKEN) != 0); #endif } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_transmitbyte * * Description: * Transmit a byte. * - ************************************************************************************/ + ****************************************************************************/ static inline void pic32mz_i2c_transmitbyte(struct pic32mz_i2c_priv_s *priv, uint8_t data) @@ -1453,26 +1480,29 @@ static inline void pic32mz_i2c_transmitbyte(struct pic32mz_i2c_priv_s *priv, /* To avoid bus collision during polling. */ #ifdef CONFIG_I2C_POLLED - while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_STAT_OFFSET) & I2C_STAT_TRSTAT) != 0); + while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_STAT_OFFSET) & + I2C_STAT_TRSTAT) != 0); #endif } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_receivebyte * * Description: * Receive a byte. * - ************************************************************************************/ + ****************************************************************************/ -static inline uint32_t pic32mz_i2c_receivebyte(struct pic32mz_i2c_priv_s *priv) +static inline uint32_t + pic32mz_i2c_receivebyte(struct pic32mz_i2c_priv_s *priv) { uint32_t val; /* To avoid bus collision during polling. */ #ifdef CONFIG_I2C_POLLED - while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_STAT_OFFSET) & I2C_CON_RCEN) != 0); + while ((pic32mz_i2c_getreg(priv, PIC32MZ_I2C_STAT_OFFSET) & + I2C_CON_RCEN) != 0); #endif val = pic32mz_i2c_getreg(priv, PIC32MZ_I2C_RCV_OFFSET); @@ -1480,16 +1510,17 @@ static inline uint32_t pic32mz_i2c_receivebyte(struct pic32mz_i2c_priv_s *priv) return val; } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_master_inactive * * Description: * Check if the bus is inactive. * No start, stop, ACK is in progress. * - ************************************************************************************/ + ****************************************************************************/ -static inline bool pic32mz_i2c_master_inactive(FAR struct pic32mz_i2c_priv_s *priv) +static inline bool + pic32mz_i2c_master_inactive(FAR struct pic32mz_i2c_priv_s *priv) { uint32_t con; @@ -1498,26 +1529,27 @@ static inline bool pic32mz_i2c_master_inactive(FAR struct pic32mz_i2c_priv_s *pr return ((con & I2C_CON_IDLEMASK) ? false:true); } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_getstatus * * Description: * Get the STAT register. * - ************************************************************************************/ + ****************************************************************************/ -static inline uint32_t pic32mz_i2c_getstatus(FAR struct pic32mz_i2c_priv_s *priv) +static inline uint32_t + pic32mz_i2c_getstatus(FAR struct pic32mz_i2c_priv_s *priv) { return pic32mz_i2c_getreg(priv, PIC32MZ_I2C_STAT_OFFSET); } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * - ************************************************************************************/ + ****************************************************************************/ static int pic32mz_i2c_init(FAR struct pic32mz_i2c_priv_s *priv) { @@ -1544,13 +1576,13 @@ static int pic32mz_i2c_init(FAR struct pic32mz_i2c_priv_s *priv) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_deinit * * Description: * Shutdown the I2C hardware * - ************************************************************************************/ + ****************************************************************************/ static int pic32mz_i2c_deinit(FAR struct pic32mz_i2c_priv_s *priv) { @@ -1570,17 +1602,17 @@ static int pic32mz_i2c_deinit(FAR struct pic32mz_i2c_priv_s *priv) return OK; } -/************************************************************************************ +/**************************************************************************** * Device Driver Operations - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_transfer * * Description: * Generic I2C transfer function * - ************************************************************************************/ + ****************************************************************************/ static int pic32mz_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count) @@ -1685,7 +1717,7 @@ static int pic32mz_i2c_transfer(FAR struct i2c_master_s *dev, return ret; } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2c_reset * * Description: @@ -1697,7 +1729,7 @@ static int pic32mz_i2c_transfer(FAR struct i2c_master_s *dev, * Returned Value: * Zero (OK) on success; a negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_I2C_RESET static int pic32mz_i2c_reset(FAR struct i2c_master_s *dev) @@ -1811,17 +1843,17 @@ out: } #endif /* CONFIG_I2C_RESET */ -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2cbus_initialize * * Description: * Initialize one I2C bus * - ************************************************************************************/ + ****************************************************************************/ FAR struct i2c_master_s *pic32mz_i2cbus_initialize(int port) { @@ -1881,13 +1913,13 @@ FAR struct i2c_master_s *pic32mz_i2cbus_initialize(int port) return (struct i2c_master_s *)priv; } -/************************************************************************************ +/**************************************************************************** * Name: pic32mz_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * - ************************************************************************************/ + ****************************************************************************/ int pic32mz_i2cbus_uninitialize(FAR struct i2c_master_s *dev) { diff --git a/arch/mips/src/pic32mz/pic32mz-lowconsole.c b/arch/mips/src/pic32mz/pic32mz-lowconsole.c index ed582864c7a..21b8125a0f9 100644 --- a/arch/mips/src/pic32mz/pic32mz-lowconsole.c +++ b/arch/mips/src/pic32mz/pic32mz-lowconsole.c @@ -176,7 +176,7 @@ static void pic32mz_uartsetbaud(uintptr_t uart_base, uint32_t baudrate) uint32_t brg; unsigned int mode; - /* We want the largest value of BRG divisor possible (for the best accuracy). + /* We want the largest value of BRG divisor possible (for the best accuracy) * Subject to BRG <= 65536. */ @@ -196,6 +196,7 @@ static void pic32mz_uartsetbaud(uintptr_t uart_base, uint32_t baudrate) brg = (tmp + 8) >> 4; mode = PIC32MZ_UART_MODECLR_OFFSET; } + DEBUGASSERT(brg <= 65536); /* Set the BRG divisor */ @@ -238,15 +239,17 @@ void pic32mz_uartreset(uintptr_t uart_base) #ifdef HAVE_UART_DEVICE void pic32mz_uartconfigure(uintptr_t uart_base, uint32_t baudrate, - unsigned int parity, unsigned int nbits, bool stop2) + unsigned int parity, unsigned int nbits, + bool stop2) { /* Clear mode and sta bits */ pic32mz_putreg(uart_base, PIC32MZ_UART_MODECLR_OFFSET, - UART_MODE_STSEL | UART_MODE_PDSEL_MASK | UART_MODE_BRGH | - UART_MODE_RXINV | UART_MODE_WAKE | UART_MODE_LPBACK | - UART_MODE_UEN_MASK | UART_MODE_RTSMD | UART_MODE_IREN | - UART_MODE_SIDL | UART_MODE_ON); + UART_MODE_STSEL | UART_MODE_PDSEL_MASK | + UART_MODE_BRGH | UART_MODE_RXINV | + UART_MODE_WAKE | UART_MODE_LPBACK | + UART_MODE_UEN_MASK | UART_MODE_RTSMD | + UART_MODE_IREN | UART_MODE_SIDL | UART_MODE_ON); /* Configure the FIFOs: * @@ -254,15 +257,16 @@ void pic32mz_uartconfigure(uintptr_t uart_base, uint32_t baudrate, * TX: Interrupt on FIFO empty * Invert transmit polarity. * - * NOTE that there are not many options on trigger TX interrupts. The FIFO not - * full might generate better through-put but with a higher interrupt rate. FIFO - * empty should lower the interrupt rate but result in a burstier output. If - * you change this, please read the comment for acknowledging the interrupt in - * pic32mz-serial.c + * NOTE that there are not many options on trigger TX interrupts. + * The FIFO not full might generate better through-put but with a higher + * interrupt rate. FIFO empty should lower the interrupt rate but result + * in a burstier output. If you change this, please read the comment for + * acknowledging the interrupt in pic32mz-serial.c */ pic32mz_putreg(uart_base, PIC32MZ_UART_STACLR_OFFSET, - UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | UART_STA_URXISEL_RXB75); + UART_STA_UTXINV | UART_STA_UTXISEL_TXBE | + UART_STA_URXISEL_RXB75); /* Configure the FIFO interrupts */ @@ -482,10 +486,12 @@ void up_lowputc(char ch) #ifdef HAVE_SERIAL_CONSOLE /* Wait for the transmit buffer not full */ - while ((pic32mz_getreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_STA_OFFSET) & UART_STA_UTXBF) != 0); + while ((pic32mz_getreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_STA_OFFSET) & + UART_STA_UTXBF) != 0); /* Then write the character to the TX data register */ - pic32mz_putreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_TXREG_OFFSET, (uint32_t)ch); + pic32mz_putreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_TXREG_OFFSET, + (uint32_t)ch); #endif } diff --git a/arch/mips/src/pic32mz/pic32mz-serial.c b/arch/mips/src/pic32mz/pic32mz-serial.c index 6728a3032b4..f721b98b64a 100644 --- a/arch/mips/src/pic32mz/pic32mz-serial.c +++ b/arch/mips/src/pic32mz/pic32mz-serial.c @@ -265,7 +265,8 @@ struct up_dev_s /* Low-level helpers */ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset); -static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value); +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint32_t value); static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im); static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im); @@ -361,7 +362,7 @@ static uart_dev_t g_uart1port = { .size = CONFIG_UART1_TXBUFSIZE, .buffer = g_uart1txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart1priv, }; @@ -393,7 +394,7 @@ static uart_dev_t g_uart2port = { .size = CONFIG_UART2_TXBUFSIZE, .buffer = g_uart2txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart2priv, }; @@ -425,7 +426,7 @@ static uart_dev_t g_uart3port = { .size = CONFIG_UART3_TXBUFSIZE, .buffer = g_uart3txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart3priv, }; @@ -457,7 +458,7 @@ static uart_dev_t g_uart4port = { .size = CONFIG_UART4_TXBUFSIZE, .buffer = g_uart4txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart4priv, }; @@ -489,7 +490,7 @@ static uart_dev_t g_uart5port = { .size = CONFIG_UART5_TXBUFSIZE, .buffer = g_uart5txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart5priv, }; @@ -521,7 +522,7 @@ static uart_dev_t g_uart6port = { .size = CONFIG_UART6_TXBUFSIZE, .buffer = g_uart6txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart6priv, }; @@ -544,7 +545,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +static inline void up_serialout(struct up_dev_s *priv, int offset, + uint32_t value) { putreg32(value, priv->uartbase + offset); } @@ -576,9 +578,10 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) flags = enter_critical_section(); if (im) - { - *im = priv->im; - } + { + *im = priv->im; + } + up_restoreuartint(dev, 0); leave_critical_section(flags); } @@ -639,7 +642,8 @@ static void up_shutdown(struct uart_dev_s *dev) * * RX and TX interrupts are not enabled by the attach method (unless the * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * interrupts are not enabled until the txint() and rxint() methods are + * called. * ****************************************************************************/ @@ -725,18 +729,19 @@ static int up_interrupt(int irq, void *context, FAR void *arg) * following error conditions take place: * - Parity error PERR (UxSTA bit 3) is detected * - Framing Error FERR (UxSTA bit 2) is detected - * - Overflow condition for the receive buffer OERR (UxSTA bit 1) occurs + * - Overflow condition for the receive buffer OERR (UxSTA bit 1) + * occurs. */ #ifdef CONFIG_DEBUG_ERROR if (up_pending_irq(priv->irqe)) { - /* Clear the pending error interrupt */ + /* Clear the pending error interrupt */ - up_clrpend_irq(priv->irqe); - _err("ERROR: interrupt STA: %08x\n", - up_serialin(priv, PIC32MZ_UART_STA_OFFSET)); - handled = true; + up_clrpend_irq(priv->irqe); + _err("ERROR: interrupt STA: %08x\n", + up_serialin(priv, PIC32MZ_UART_STA_OFFSET)); + handled = true; } #endif @@ -760,7 +765,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg) * longer has space to buffer the serial data. */ - if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & UART_STA_URXDA) == 0) + if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & + UART_STA_URXDA) == 0) { up_clrpend_irq(priv->irqrx); } @@ -769,8 +775,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg) /* Handle outgoing, transmit bytes The RT FIFO is configured to * interrupt only when the TX FIFO is empty. There are not many * options on trigger TX interrupts. The FIFO-not-full might generate - * better through-put but with a higher interrupt rate. FIFO-empty should - * lower the interrupt rate but result in a burstier output. If + * better through-put but with a higher interrupt rate. FIFO-empty + * should lower the interrupt rate but result in a burstier output. If * you change this, You will probably need to change the conditions for * clearing the pending TX interrupt below. * @@ -796,7 +802,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg) * to be sent. */ - if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & UART_STA_UTRMT) != 0) + if ((up_serialin(priv, PIC32MZ_UART_STA_OFFSET) & + UART_STA_UTRMT) != 0) { up_clrpend_irq(priv->irqtx); } @@ -908,7 +915,8 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status) /* Then return the actual received byte */ - return (int)(up_serialin(priv, PIC32MZ_UART_RXREG_OFFSET) & UART_RXREG_MASK); + return (int)(up_serialin(priv, PIC32MZ_UART_RXREG_OFFSET) & + UART_RXREG_MASK); } /**************************************************************************** @@ -929,8 +937,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) im = priv->im; if (enable) { - /* Receive an interrupt when their is anything in the Rx data register (or an Rx - * timeout occurs). + /* Receive an interrupt when their is anything in the Rx data register + * (or an Rx timeout occurs). */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -949,6 +957,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) up_disable_irq(priv->irqrx); DISABLE_RX(im); } + priv->im = im; leave_critical_section(flags); } diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c index 20513ef3651..0e1158fd2a1 100644 --- a/arch/mips/src/pic32mz/pic32mz-spi.c +++ b/arch/mips/src/pic32mz/pic32mz-spi.c @@ -1063,14 +1063,16 @@ static void spi_exchange8(FAR struct pic32mz_dev_s *priv, * receive buffer is not empty. */ - while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBE) != 0); + while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & + SPI_STAT_SPIRBE) != 0); #else - /* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. In - * normal mode, the SPIRBF bit will be set when receive data is + /* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. + * In normal mode, the SPIRBF bit will be set when receive data is * available. */ - while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) == 0); + while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & + SPI_STAT_SPIRBF) == 0); #endif /* Read from the buffer register to clear the status bit */ @@ -1135,13 +1137,16 @@ static void spi_exchange16(FAR struct pic32mz_dev_s *priv, * receive buffer is not empty. */ - while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBE) != 0); + while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & + SPI_STAT_SPIRBE) != 0); #else - /* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. In - * normal mode, the SPIRBF bit will be set when receive data is available. + /* Wait for the SPIRBF bit in the SPI Status Register to be set to 1. + * In normal mode, the SPIRBF bit will be set when receive data is + * available. */ - while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & SPI_STAT_SPIRBF) == 0); + while ((spi_getreg(priv, PIC32MZ_SPI_STAT_OFFSET) & + SPI_STAT_SPIRBF) == 0); #endif /* Read from the buffer register to clear the status bit */ diff --git a/arch/mips/src/pic32mz/pic32mz-timer.c b/arch/mips/src/pic32mz/pic32mz-timer.c index 6ac854538cd..0b216f4a97f 100644 --- a/arch/mips/src/pic32mz/pic32mz-timer.c +++ b/arch/mips/src/pic32mz/pic32mz-timer.c @@ -153,7 +153,8 @@ static inline void pic32mz_putreg(FAR struct pic32mz_timer_dev_s *dev, uint16_t offset, uint32_t value); static inline bool pic32mz_timer_mode32(FAR struct pic32mz_timer_dev_s *dev); static inline uint32_t pic32mz_timer_oddoffset(uint32_t evenoffset); -static inline uint32_t pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev); +static inline uint32_t + pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev); static void pic32mz_timer_stopinidle(FAR struct pic32mz_timer_dev_s *dev, bool stop); @@ -606,7 +607,8 @@ static inline uint32_t pic32mz_timer_oddoffset(uint32_t evenoffset) * ****************************************************************************/ -static inline uint32_t pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev) +static inline uint32_t + pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev) { uint32_t irq; @@ -856,10 +858,10 @@ static void pic32mz_timer_setperiod(FAR struct pic32mz_timer_dev_s *dev, if (pic32mz_timer_mode32(dev)) { - pic32mz_putreg(dev, PIC32MZ_TIMER_PR_OFFSET, period & 0x00000FFFF); + pic32mz_putreg(dev, PIC32MZ_TIMER_PR_OFFSET, period & 0x00000ffff); pic32mz_putreg(dev, pic32mz_timer_oddoffset(PIC32MZ_TIMER_PR_OFFSET), - (period >> 16) & 0x00000FFFF); + (period >> 16) & 0x00000ffff); } else { @@ -898,7 +900,6 @@ static uint32_t pic32mz_timer_getcounter(FAR struct pic32mz_timer_dev_s *dev) { return pic32mz_getreg(dev, PIC32MZ_TIMER_CNT_OFFSET); } - } /**************************************************************************** @@ -919,11 +920,10 @@ static void pic32mz_timer_setcounter(FAR struct pic32mz_timer_dev_s *dev, if (pic32mz_timer_mode32(dev)) { - - pic32mz_putreg(dev, PIC32MZ_TIMER_CNT_OFFSET, count & 0x00000FFFF); + pic32mz_putreg(dev, PIC32MZ_TIMER_CNT_OFFSET, count & 0x00000ffff); pic32mz_putreg(dev, pic32mz_timer_oddoffset(PIC32MZ_TIMER_CNT_OFFSET), - (count >> 16) & 0x00000FFFF); + (count >> 16) & 0x00000ffff); } else { diff --git a/arch/mips/src/pic32mz/pic32mz-timerisr.c b/arch/mips/src/pic32mz/pic32mz-timerisr.c index 6d93837453c..7169a0e9ec3 100644 --- a/arch/mips/src/pic32mz/pic32mz-timerisr.c +++ b/arch/mips/src/pic32mz/pic32mz-timerisr.c @@ -170,7 +170,7 @@ void mips_timer_initialize(void) putreg32((TIMER1_CON_TCKPS | TIMER1_CON_TCS), PIC32MZ_TIMER1_CON); putreg32(0, PIC32MZ_TIMER1_CNT); - putreg32(TIMER1_MATCH-1, PIC32MZ_TIMER1_PR); + putreg32(TIMER1_MATCH - 1, PIC32MZ_TIMER1_PR); putreg32(TIMER_CON_ON, PIC32MZ_TIMER1_CONSET); /* Configure the timer interrupt */