Costmetic fixes to C coding style

arch/arm/src/a1x/a1x_pio.c

@@ -67,7 +67,7 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Private Function Prototypes
+ * Private Functions
  ****************************************************************************/
 /****************************************************************************
  * Name: a1x_pio_pin

arch/arm/src/armv6-m/up_vectors.c

@@ -85,16 +85,16 @@ extern char _ebss;
  */
 
 unsigned _vectors[] __attribute__((section(".vectors"))) =
-  {
-    /* Initial stack */
+{
+  /* Initial stack */
 
-    IDLE_STACK,
+  IDLE_STACK,
 
-    /* Reset exception handler */
+  /* Reset exception handler */
 
-    (unsigned)&__start,
+  (unsigned)&__start,
 
-    /* Vectors 2 - n point directly at the generic handler */
+  /* Vectors 2 - n point directly at the generic handler */
 
-    [2 ... (15 + ARMV6M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
-  };
+  [2 ... (15 + ARMV6M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
+};

arch/arm/src/armv7-a/arm_syscall.c

@@ -128,7 +128,7 @@ static void dispatch_syscall(void)
     " str lr, [sp, #12]\n"         /* Save lr in the stack frame */
     " ldr ip, =g_stublookup\n"     /* R12=The base of the stub lookup table */
     " ldr ip, [ip, r0, lsl #2]\n"  /* R12=The address of the stub for this SYSCALL */
-    " blx ip\n"                    /* Call the stub (modifies lr)*/
+    " blx ip\n"                    /* Call the stub (modifies lr) */
     " ldr lr, [sp, #12]\n"         /* Restore lr */
     " add sp, sp, #16\n"           /* Destroy the stack frame */
     " mov r2, r0\n"                /* R2=Save return value in R2 */

arch/arm/src/armv7-a/arm_virtpgaddr.c

@@ -85,4 +85,4 @@ uintptr_t arm_virtpgaddr(uintptr_t paddr)
   return 0;
 }
 
-#endif /* CONFIG_MM_PGALLOC && CONFIG_ARCH_PGPOOL_MAPPING*/
+#endif /* CONFIG_MM_PGALLOC && CONFIG_ARCH_PGPOOL_MAPPING */

arch/arm/src/armv7-m/arch_enable_dcache.c

@@ -114,7 +114,7 @@ void arch_enable_dcache(void)
         }
       while (tmpways--);
     }
-  while(sets--);
+  while (sets--);
 
   ARM_DSB();
 

arch/arm/src/armv7-m/up_svcall.c

@@ -130,7 +130,7 @@ static void dispatch_syscall(void)
     " str lr, [sp, #12]\n"         /* Save lr in the stack frame */
     " ldr ip, =g_stublookup\n"     /* R12=The base of the stub lookup table */
     " ldr ip, [ip, r0, lsl #2]\n"  /* R12=The address of the stub for this syscall */
-    " blx ip\n"                    /* Call the stub (modifies lr)*/
+    " blx ip\n"                    /* Call the stub (modifies lr) */
     " ldr lr, [sp, #12]\n"         /* Restore lr */
     " add sp, sp, #16\n"           /* Destroy the stack frame */
     " mov r2, r0\n"                /* R2=Save return value in R2 */

arch/arm/src/armv7-m/up_vectors.c

@@ -80,16 +80,16 @@ extern char _ebss;
  */
 
 unsigned _vectors[] __attribute__((section(".vectors"))) =
-  {
-    /* Initial stack */
+{
+  /* Initial stack */
 
-    IDLE_STACK,
+  IDLE_STACK,
 
-    /* Reset exception handler */
+  /* Reset exception handler */
 
-    (unsigned)&__start,
+  (unsigned)&__start,
 
-    /* Vectors 2 - n point directly at the generic handler */
+  /* Vectors 2 - n point directly at the generic handler */
 
-    [2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
-  };
+  [2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common
+};

arch/arm/src/c5471/c5471_ethernet.c

@@ -871,11 +871,11 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
       /* Words #0 and #1 of descriptor */
 
       while (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc))
-       {
-         /* Loop until the SWITCH lets go of the descriptor giving us access
-          * rights to submit our new ether frame to it.
-          */
-       }
+        {
+          /* Loop until the SWITCH lets go of the descriptor giving us access
+           * rights to submit our new ether frame to it.
+           */
+        }
 
       if (bfirstframe)
         {
@@ -1683,7 +1683,7 @@ static int c5471_ifup(struct net_driver_s *dev)
 
   ndbg("Bringing up: %d.%d.%d.%d\n",
        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
-       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
+       (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
 
   /* Initilize Ethernet interface */
 
@@ -2244,12 +2244,12 @@ void up_netinitialize(void)
   g_c5471[0].c_dev.d_addmac  = c5471_addmac;   /* Add multicast MAC address */
   g_c5471[0].c_dev.d_rmmac   = c5471_rmmac;    /* Remove multicast MAC address */
 #endif
- g_c5471[0].c_dev.d_private = (void*)g_c5471; /* Used to recover private state from dev */
+  g_c5471[0].c_dev.d_private = (void*)g_c5471; /* Used to recover private state from dev */
 
   /* Create a watchdog for timing polling for and timing of transmisstions */
 
-  g_c5471[0].c_txpoll       = wd_create();   /* Create periodic poll timer */
-  g_c5471[0].c_txtimeout    = wd_create();   /* Create TX timeout timer */
+  g_c5471[0].c_txpoll        = wd_create();    /* Create periodic poll timer */
+  g_c5471[0].c_txtimeout     = wd_create();    /* Create TX timeout timer */
 
   /* Register the device with the OS so that socket IOCTLs can be performed */
 
@@ -2257,4 +2257,3 @@ void up_netinitialize(void)
 }
 
 #endif /* CONFIG_NET */
-

arch/arm/src/c5471/c5471_serial.c

@@ -562,18 +562,18 @@ static int up_interrupt(int irq, void *context)
       /* Is this an interrupt from the IrDA UART? */
 
       if (irq == C5471_IRQ_UART_IRDA)
-         {
-           /* Save the currently enabled IrDA UART interrupts
-            * so that we can restore the IrDA interrupt state
-            * below.
-            */
+        {
+          /* Save the currently enabled IrDA UART interrupts
+           * so that we can restore the IrDA interrupt state
+           * below.
+           */
 
-           ier_val = up_inserial(priv, UART_IER_OFFS);
+          ier_val = up_inserial(priv, UART_IER_OFFS);
 
-           /* Then disable all IrDA UART interrupts */
+          /* Then disable all IrDA UART interrupts */
 
-           up_serialout(priv, UART_IER_OFFS, 0);
-         }
+          up_serialout(priv, UART_IER_OFFS, 0);
+        }
 
       /* Receive characters from the RX fifo */
 

arch/arm/src/c5471/c5471_timerisr.c

@@ -92,10 +92,10 @@
 
 int up_timerisr(int irq, uint32_t *regs)
 {
-   /* Process timer interrupt */
+  /* Process timer interrupt */
 
-   sched_process_timer();
-   return 0;
+  sched_process_timer();
+  return 0;
 }
 
 /****************************************************************************
@@ -125,4 +125,3 @@ void up_timer_initialize(void)
   irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
   up_enable_irq(C5471_IRQ_SYSTIMER);
 }
-

arch/arm/src/c5471/c5471_watchdog.c

@@ -296,7 +296,7 @@ static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 
   /* Process the IOCTL command (see arch/watchdog.h) */
 
-  switch(cmd)
+  switch (cmd)
     {
     case WDIOC_KEEPALIVE:
       wdt_setusec(MAX_WDT_USEC);

arch/arm/src/calypso/calypso_heap.c

@@ -80,7 +80,7 @@ void up_addregion(void)
   /* Disable watchdog in first non-common function */
   wdog_enable(0);
 #endif
-  // XXX: change to initialization of extern memory with save defaults
+  /* XXX: change to initialization of extern memory with save defaults */
   /* Configure memory interface */
   calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
   calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);

arch/arm/src/calypso/calypso_keypad.c

@@ -143,7 +143,7 @@ static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len)
           *state |= 0x80000000;
         }
 
-        return 1; // break loop in caller
+      return 1; /* break loop in caller */
     }
   else
     {
@@ -164,7 +164,7 @@ static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len)
         }
     }
 
-  return 0; // continue with other columns
+  return 0; /* Continue with other columns */
 }
 
 /****************************************************************************

arch/arm/src/calypso/calypso_serial.c

@@ -73,7 +73,9 @@
 
 #if UART_FCR_OFFS == UART_EFR_OFFS
 # define UART_MULTIPLEX_REGS
-// HW flow control not supported yet
+
+/* HW flow control not supported yet */
+
 # undef  CONFIG_UART_HWFLOWCONTROL
 #endif
 
@@ -622,18 +624,18 @@ static int up_interrupt(int irq, void *context)
       /* Is this an interrupt from the IrDA UART? */
 
       if (irq == UART_IRQ_IRDA)
-         {
-           /* Save the currently enabled IrDA UART interrupts
-            * so that we can restore the IrDA interrupt state
-            * below.
-            */
+        {
+          /* Save the currently enabled IrDA UART interrupts
+           * so that we can restore the IrDA interrupt state
+           * below.
+           */
 
-           ier_val = up_inserial(priv, UART_IER_OFFS);
+          ier_val = up_inserial(priv, UART_IER_OFFS);
 
-           /* Then disable all IrDA UART interrupts */
+          /* Then disable all IrDA UART interrupts */
 
-           up_serialout(priv, UART_IER_OFFS, 0);
-         }
+          up_serialout(priv, UART_IER_OFFS, 0);
+        }
 
       /* Receive characters from the RX fifo */
 

arch/arm/src/calypso/calypso_spi.c

@@ -223,18 +223,18 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
   /* wait until the transfer is complete */
 
   while (1)
-  {
-    reg_status = getreg16(SPI_REG(REG_STATUS));
-    dbg("status=0x%04x ", reg_status);
-    if (din && (reg_status & SPI_STATUS_RE))
-      {
-        break;
-      }
-    else if (reg_status & SPI_STATUS_WE)
-      {
-        break;
-      }
-  }
+    {
+      reg_status = getreg16(SPI_REG(REG_STATUS));
+      dbg("status=0x%04x ", reg_status);
+      if (din && (reg_status & SPI_STATUS_RE))
+        {
+          break;
+        }
+      else if (reg_status & SPI_STATUS_WE)
+        {
+          break;
+        }
+    }
 
   /* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */
 

arch/arm/src/calypso/calypso_timer.c

@@ -161,11 +161,11 @@ void wdog_enable(int on)
 
 void wdog_reset(void)
 {
-  // enable watchdog
+  /* Enable watchdog */
 
   putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
 
-  // force expiration
+  /* Force expiration */
 
   putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
   putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
@@ -186,10 +186,10 @@ void wdog_reset(void)
 
 int up_timerisr(int irq, uint32_t *regs)
 {
- /* Process timer interrupt */
+  /* Process timer interrupt */
 
- sched_process_timer();
- return 0;
+  sched_process_timer();
+  return 0;
 }
 
 /****************************************************************************

arch/arm/src/common/up_checkstack.c

@@ -136,7 +136,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
                 }
 
               up_putc(ch);
-             }
+            }
 
           up_putc('\n');
         }

arch/arm/src/common/up_createstack.c

@@ -231,7 +231,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
       return OK;
     }
 
-   return ERROR;
+  return ERROR;
 }
 
 /****************************************************************************

arch/arm/src/common/up_interruptcontext.c

@@ -66,5 +66,5 @@
 
 bool up_interrupt_context(void)
 {
-   return current_regs != NULL;
+  return current_regs != NULL;
 }

arch/arm/src/common/up_vfork.c

@@ -210,12 +210,12 @@ pid_t up_vfork(const struct vfork_s *context)
   svdbg("Child:  stack base:%08x SP:%08x FP:%08x\n",
         child->cmn.adj_stack_ptr, newsp, newfp);
 
- /* Update the stack pointer, frame pointer, and volatile registers.  When
-  * the child TCB was initialized, all of the values were set to zero.
-  * up_initial_state() altered a few values, but the return value in R0
-  * should be cleared to zero, providing the indication to the newly started
-  * child thread.
-  */
+  /* Update the stack pointer, frame pointer, and volatile registers.  When
+   * the child TCB was initialized, all of the values were set to zero.
+   * up_initial_state() altered a few values, but the return value in R0
+   * should be cleared to zero, providing the indication to the newly started
+   * child thread.
+   */
 
   child->cmn.xcp.regs[REG_R4]  = context->r4;  /* Volatile register r4 */
   child->cmn.xcp.regs[REG_R5]  = context->r5;  /* Volatile register r5 */

arch/arm/src/dm320/dm320_framebuffer.c

@@ -1201,15 +1201,15 @@ static int dm320_putcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *c
   flags = irqsave();
   for (i = cmap.first, len = 0; i < 256 && len < cmap.len, i++, len++)
     {
-       /* Convert the RGB to YUV */
+      /* Convert the RGB to YUV */
 
-       nxgl_rgb2yuv(cmap->red[i], cmap->green[i], cmap->blue[i], &y, &u, &v);
+      nxgl_rgb2yuv(cmap->red[i], cmap->green[i], cmap->blue[i], &y, &u, &v);
 
-       /* Program the CLUT */
+      /* Program the CLUT */
 
-       while (getreg16(DM320_OSD_MISCCTL) & 0x8);
-       putreg16(((uint16_t)y) << 8 | uint16_t(u)), DM320_OSD_CLUTRAMYCB);
-       putreg16(((uint16_t)v << 8 | i), DM320_OSD_CLUTRAMCR);
+      while (getreg16(DM320_OSD_MISCCTL) & 0x8);
+      putreg16(((uint16_t)y) << 8 | uint16_t(u)), DM320_OSD_CLUTRAMYCB);
+      putreg16(((uint16_t)v << 8 | i), DM320_OSD_CLUTRAMCR);
     }
 
   /* Select RAM clut */
@@ -1296,10 +1296,10 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs
     {
       gvdbg("x=%d y=%d\n", settings->pos.x, settings->pos.y);
 
-     if (settings->pos.x > MAX_YRES)
-       {
+      if (settings->pos.x > MAX_YRES)
+        {
           settings->pos.x = MAX_YRES;
-       }
+        }
 
      if (settings->pos.y > MAX_YRES)
        {

arch/arm/src/dm320/dm320_irq.c

@@ -102,9 +102,9 @@ void up_irqinitialize(void)
   putreg16(0xffff, DM320_INTC_IRQ1);
   putreg16(0xffff, DM320_INTC_IRQ2);
 
- /* Make sure that the base addresses are zero and that
-  * the table increment is 4 bytes.
-  */
+  /* Make sure that the base addresses are zero and that
+   * the table increment is 4 bytes.
+   */
 
   putreg16(0, DM320_INTC_EABASE0);
   putreg16(0, DM320_INTC_EABASE1);

arch/arm/src/dm320/dm320_timerisr.c

@@ -119,10 +119,10 @@
 
 int up_timerisr(int irq, uint32_t *regs)
 {
-   /* Process timer interrupt */
+  /* Process timer interrupt */
 
-   sched_process_timer();
-   return 0;
+  sched_process_timer();
+  return 0;
 }
 
 /****************************************************************************

arch/arm/src/dm320/dm320_usbdev.c

@@ -441,10 +441,11 @@ static uint8_t dm320_getreg8(uint32_t addr)
     {
       if (count == 0xffffffff || ++count > 3)
         {
-           if (count == 4)
-             {
-               lldbg("...\n");
-             }
+          if (count == 4)
+            {
+              lldbg("...\n");
+            }
+
           return val;
         }
     }
@@ -727,7 +728,7 @@ static int dm320_ep0write(uint8_t *buf, uint16_t nbytes)
   uint16_t bytesleft;
   uint16_t nwritten;
 
-  if ( nbytes <=  DM320_EP0MAXPACKET)
+  if (nbytes <=  DM320_EP0MAXPACKET)
     {
       bytesleft = nbytes;
       csr0     |= USB_PERCSR0_DATAEND; /* Transaction end bit */
@@ -762,13 +763,13 @@ static int dm320_epwrite(uint8_t epphy, uint8_t *buf, uint16_t nbytes)
   uint16_t bytesleft;
   int ret = ERROR;
 
-  if (/*epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS)
+  if (/* epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS)
     {
       return ret;
     }
   dm320_putreg8(epphy, DM320_USB_INDEX);
 
-  if (epphy == USB_EP0_SELECT )
+  if (epphy == USB_EP0_SELECT)
     {
       return dm320_ep0write(buf, nbytes);
     }
@@ -813,7 +814,7 @@ static int dm320_epread(uint8_t epphy, uint8_t *buf, uint16_t nbytes)
   int bytesleft;
   int ret  = ERROR;
 
-  if (/*epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS)
+  if (/* epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS)
     {
       return ret;
     }
@@ -1848,7 +1849,7 @@ static void dm320_ctrlinitialize(FAR struct dm320_usbdev_s *priv)
   priv->paddr = 0;
   dm320_putreg8(0, DM320_USB_FADDR);
 
-  /* Finished -- set default endpoint as EP0*/
+  /* Finished -- set default endpoint as EP0 */
 
   dm320_putreg8(USB_EP0_SELECT, DM320_USB_INDEX);
 }
@@ -2133,6 +2134,7 @@ static int dm320_epcancel(struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
       return -EINVAL;
     }
 #endif
+
   usbtrace(TRACE_EPCANCEL, privep->epphy);
   priv = privep->dev;
 
@@ -2516,7 +2518,7 @@ int usbdev_register(FAR struct usbdevclass_driver_s *driver)
 
   /* Hook up the driver */
 
- g_usbdev.driver = driver;
+  g_usbdev.driver = driver;
 
   /* Then bind the class driver */
 

arch/arm/src/efm32/efm32_adc.c

@@ -113,8 +113,8 @@ struct efm32_dev_s
 
 /* ADC Register access */
 
-static uint32_t adc_getreg( struct efm32_dev_s *priv, int offset);
-static void     adc_putreg( struct efm32_dev_s *priv, int offset, uint32_t value);
+static uint32_t adc_getreg(struct efm32_dev_s *priv, int offset);
+static void     adc_putreg(struct efm32_dev_s *priv, int offset, uint32_t value);
 static void     adc_hw_reset(struct efm32_dev_s *priv, bool reset);
 
 /* ADC Interrupt Handler */
@@ -662,9 +662,9 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
       /* Just in case, make sure we get non-zero freq for below calculation */
 
       if (!hfperFreq)
-      {
-        hfperFreq = 1;
-      }
+        {
+          hfperFreq = 1;
+        }
     }
 
 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
@@ -675,7 +675,7 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
    * See reference manual for details.
    */
 
-  if (hfperFreq > 32000000 )
+  if (hfperFreq > 32000000)
     {
       hfperFreq = 32000000;
     }

arch/arm/src/efm32/efm32_clockconfig.c

@@ -154,7 +154,7 @@ static inline void efm32_statuswait(uint32_t bitset)
 {
   /* Wait for clock to stabilize if requested */
 
-   while ((getreg32(EFM32_CMU_STATUS) & bitset) == 0);
+  while ((getreg32(EFM32_CMU_STATUS) & bitset) == 0);
 }
 
 /****************************************************************************
@@ -502,7 +502,7 @@ static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv)
  ****************************************************************************/
 
 #ifdef CONFIG_EFM32_LECLOCK
-uint32_t efm32_coreleclk_config( int frequency )
+uint32_t efm32_coreleclk_config(int frequency)
 {
 #ifdef CMU_CTRL_HFLE
   uint32_t regval;

arch/arm/src/efm32/efm32_flash.c

@@ -240,7 +240,9 @@ int __ramfunc__ msc_load_verify_address(uint32_t* address)
       /* Check for invalid address */
 
       if (status & MSC_STATUS_INVADDR)
-        return -EINVAL;
+        {
+          return -EINVAL;
+        }
 
       /* Check for write protected page */
 
@@ -374,7 +376,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words,
           DEBUGASSERT(BOARD_SYSTEM_FREQUENCY >= 1000000);
 
           word_index = 0;
-          while(word_index < num_words)
+          while (word_index < num_words)
             {
               putreg32(*data++,EFM32_MSC_WDATA);
               word_index++;
@@ -431,7 +433,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words,
 
           word_index = 0;
 
-          while(word_index < num_words)
+          while (word_index < num_words)
             {
 
               /* Wait for the MSC to be ready for the next word. */

arch/arm/src/efm32/efm32_gpio.c

@@ -57,7 +57,7 @@
 #define __GPIO_DOUT   (1 << 2) /* Bit 2: An input modified with DOUT setting */
 #define __GPIO_DRIVE  (1 << 3) /* Bit 3: An output with drive selection */
 
- /************************************************************************************
+/************************************************************************************
  * Private Data
  ************************************************************************************/
 

arch/arm/src/efm32/efm32_i2c.c

@@ -126,7 +126,7 @@
 
 /* Macros to convert a I2C pin to a GPIO output */
 
-#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD )
+#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD)
 
 #define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
 
@@ -873,8 +873,8 @@ static void efm32_i2c_setclock(FAR struct efm32_i2c_priv_s *priv,
 #if defined(CONFIG_EFM32_I2C_CLHR_FAST)
 #  define n (11 + 6)          /* Ratio is 11:3 */
 #elif defined(CONFIG_EFM32_I2C_CLHR_ASYMMETRIC)
-#  define n ( 6 + 3)          /* Ratio is 6:3 */
-#else                                /* CLHR STANDARD */
+#  define n (6 + 3)           /* Ratio is 6:3 */
+#else                         /* CLHR STANDARD */
 #  define n ( 4 + 4)          /* Ratio is 4:4 */
 #endif
 
@@ -1284,7 +1284,6 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv)
     }
 
 done:
-
   if (priv->i2c_state == I2CSTATE_DONE)
     {
 #ifndef CONFIG_I2C_POLLED
@@ -1607,35 +1606,35 @@ static int efm32_i2c_process(FAR struct i2c_dev_s *dev,
     {
       /* Check for error status conditions */
 
-      switch(priv->result)
+      switch (priv->result)
         {
-            /* Arbitration lost during transfer. */
+          /* Arbitration lost during transfer. */
 
           case I2CRESULT_ARBLOST:
               errval = EAGAIN;
               break;
 
-              /* NACK received during transfer. */
+          /* NACK received during transfer. */
 
           case I2CRESULT_NACK:
               errval = ENXIO;
               break;
 
-              /* SW fault. */
+          /* SW fault. */
 
           case I2CRESULT_SWFAULT:
               errval = EIO;
               break;
 
-              /* Usage fault. */
+          /* Usage fault. */
 
           case I2CRESULT_USAGEFAULT:
               errval = EINTR;
               break;
 
-              /* Bus error during transfer (misplaced START/STOP).
-               * I2C Bus is for some reason busy
-               */
+          /* Bus error during transfer (misplaced START/STOP).
+           * I2C Bus is for some reason busy
+           */
 
           case I2CRESULT_BUSERR:
               errval = EBUSY;
@@ -1975,7 +1974,6 @@ int up_i2creset(FAR struct i2c_dev_s *dev)
   ret = OK;
 
 out:
-
   /* Release the port for re-use by other clients */
 
   efm32_i2c_sem_post(dev);

arch/arm/src/efm32/efm32_irq.c

@@ -313,8 +313,8 @@ static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
 
   else
     {
-       *regaddr = NVIC_SYSHCON;
-       if (irq == EFM32_IRQ_MEMFAULT)
+      *regaddr = NVIC_SYSHCON;
+      if (irq == EFM32_IRQ_MEMFAULT)
         {
           *bit = NVIC_SYSHCON_MEMFAULTENA;
         }

arch/arm/src/efm32/efm32_leserial.c

@@ -343,9 +343,9 @@ static void efm32_disableuartint(struct efm32_leuart_s *priv, uint32_t *ien)
 
   flags = irqsave();
   if (ien)
-   {
-     *ien = priv->ien;
-   }
+    {
+      *ien = priv->ien;
+    }
 
   efm32_restoreuartint(priv, 0);
   irqrestore(flags);
@@ -362,12 +362,12 @@ static void efm32_disableuartint(struct efm32_leuart_s *priv, uint32_t *ien)
 
 static int efm32_setup(struct uart_dev_s *dev)
 {
- struct efm32_leuart_s *priv = (struct efm32_leuart_s*)dev->priv;
+  struct efm32_leuart_s *priv = (struct efm32_leuart_s*)dev->priv;
 
 #ifndef CONFIG_SUPPRESS_LEUART_CONFIG
- const struct efm32_config_s *config = priv->config;
+  const struct efm32_config_s *config = priv->config;
 
- /* Configure the UART as an RS-232 UART */
+  /* Configure the UART as an RS-232 UART */
 
   efm32_leuartconfigure(config->uartbase, config->baud, config->parity,
                         config->bits, config->stop2);

arch/arm/src/efm32/efm32_pwm.c

@@ -410,7 +410,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
 #error "Not implemented ! Sorry"
 #endif
 
-  if ( efm32_timer_set_freq(priv->base,priv->pclk,info->frequency) < 0 )
+  if (efm32_timer_set_freq(priv->base,priv->pclk,info->frequency) < 0)
     {
       pwmdbg("Cannot set TIMER frequency %dHz from clock %dHz\n",
              info->frequency,
@@ -421,7 +421,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
 
   regval = ((uint32_t)(priv->pinloc)) << _TIMER_ROUTE_LOCATION_SHIFT;
 
-  switch(priv->channel)
+  switch (priv->channel)
     {
     case 0:
       regval |= _TIMER_ROUTE_CC0PEN_MASK;
@@ -439,7 +439,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
       ASSERT(false);
     }
 
-  pwm_putreg( priv, EFM32_TIMER_ROUTE_OFFSET, regval );
+  pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, regval);
 
   regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16;
   pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET , regval);
@@ -449,11 +449,11 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv,
            (_TIMER_CC_CTRL_CMOA_CLEAR << _TIMER_CC_CTRL_CMOA_SHIFT)   | \
            (_TIMER_CC_CTRL_COFOA_SET  << _TIMER_CC_CTRL_COFOA_SHIFT)   ;
 
-  pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CTRL_OFFSET, regval );
+  pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CTRL_OFFSET, regval);
 
   /* Start Timer */
 
-  pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_START );
+  pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_START);
   pwm_dumpregs(priv, "After starting");
   return OK;
 }
@@ -676,7 +676,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
 
   /* Dnable TIMER clock */
 
-  switch(priv->timid)
+  switch (priv->timid)
     {
     case 0:
       modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER0);
@@ -819,7 +819,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 
   pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_STOP);
 
-  irqrestore( flags);
+  irqrestore(flags);
 
   pwm_dumpregs(priv, "After stop");
   return OK;

arch/arm/src/efm32/efm32_rtc_burtc.c

@@ -189,9 +189,9 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context)
   uint32_t source = getreg32(EFM32_BURTC_IF);
 
   if (source & BURTC_IF_LFXOFAIL)
-  {
+    {
       burtcdbg("BURTC_IF_LFXOFAIL");
-  }
+    }
 
 #ifdef CONFIG_RTC_HIRES
   if (source & BURTC_IF_OF)

arch/arm/src/efm32/efm32_serial.c

@@ -593,9 +593,9 @@ static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien)
 
   flags = irqsave();
   if (ien)
-   {
-     *ien = priv->ien;
-   }
+    {
+      *ien = priv->ien;
+    }
 
   efm32_restoreuartint(priv, 0);
   irqrestore(flags);

arch/arm/src/efm32/efm32_spi.c

@@ -903,7 +903,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
        *    = 128 * fHFPERCLK / (256 + CLKDIV)
        */
 
-      actual = (BOARD_HFPERCLK_FREQUENCY << 7) / ( 256 + clkdiv);
+      actual = (BOARD_HFPERCLK_FREQUENCY << 7) / (256 + clkdiv);
       spivdbg("frequency=%u actual=%u\n", frequency, actual);
 
 #ifndef CONFIG_SPI_OWNBUS
@@ -1745,18 +1745,18 @@ struct spi_dev_s *efm32_spi_initialize(int port)
 
       /* Initialize the SPI device */
 
-       ret = spi_portinitialize(priv);
-       if (ret < 0)
-         {
-           spidbg("ERROR: Failed to initialize SPI port %d\n", port);
-           irqrestore(flags);
-           return NULL;
-         }
+      ret = spi_portinitialize(priv);
+      if (ret < 0)
+        {
+          spidbg("ERROR: Failed to initialize SPI port %d\n", port);
+          irqrestore(flags);
+          return NULL;
+        }
 
-       /* Now we are initialized */
+      /* Now we are initialized */
 
-       priv->initialized = true;
-       irqrestore(flags);
+      priv->initialized = true;
+      irqrestore(flags);
     }
 
   return (struct spi_dev_s *)priv;

arch/arm/src/efm32/efm32_start.c

@@ -312,6 +312,6 @@ void __start(void)
 
   /* Shouldn't get here */
 
-  for(;;);
+  for (;;);
 #endif
 }

arch/arm/src/efm32/efm32_timer.c

@@ -191,11 +191,13 @@ void efm32_timer_reset(uintptr_t base)
   putreg32(_TIMER_IEN_RESETVALUE,   base + EFM32_TIMER_STATUS_OFFSET   );
   putreg32(_TIMER_IFC_MASK,         base + EFM32_TIMER_IEN_OFFSET      );
   putreg32(_TIMER_TOP_RESETVALUE,   base + EFM32_TIMER_IF_OFFSET       );
-  putreg32(_TIMER_TOPB_RESETVALUE,  base + EFM32_TIMER_CTRL_OFFSET     ); 
-  putreg32(_TIMER_CNT_RESETVALUE,   base + EFM32_TIMER_CMD_OFFSET      ); 
+  putreg32(_TIMER_TOPB_RESETVALUE,  base + EFM32_TIMER_CTRL_OFFSET     );
+  putreg32(_TIMER_CNT_RESETVALUE,   base + EFM32_TIMER_CMD_OFFSET      );
+
+  /* Do not reset route register, setting should be done independently
+   * (Note: ROUTE register may be locked by DTLOCK register.)
+   */
 
-  /* Do not reset route register, setting should be done independently */
-  /* (Note: ROUTE register may be locked by DTLOCK register.) */
   //putreg32(_TIMER_ROUTE_RESETVALUE, base + EFM32_TIMER_ROUTE_OFFSET    );
 
   for(i = 0; i < EFM32_TIMER_NCC; i++)
@@ -219,13 +221,13 @@ void efm32_timer_reset(uintptr_t base)
   putreg32(_TIMER_DTOGEN_RESETVALUE,base + EFM32_TIMER_DTOGEN_OFFSET   );
   putreg32(_TIMER_DTFAULTC_MASK,    base + EFM32_TIMER_DTFAULTC_OFFSET );
 #endif
-}   
+}
 
 /****************************************************************************
  * Name: efm32_timer_set_freq
  *
  * Description:
- *   set prescaler and top timer with best value to have "freq" 
+ *   set prescaler and top timer with best value to have "freq"
  *
  * Input parameters:
  *   base       - A base address of timer
@@ -239,14 +241,14 @@ void efm32_timer_reset(uintptr_t base)
 int efm32_timer_set_freq(uintptr_t base, uint32_t clk_freq, uint32_t freq)
 {
   int prescaler = 0;
-  int cnt_freq = clk_freq>>16;
+  int cnt_freq = clk_freq >> 16;
   int reload;
 
-  while ( cnt_freq > freq )
+  while (cnt_freq > freq)
     {
       prescaler++;
       cnt_freq>>=1;
-      if ( prescaler > (_TIMER_CTRL_PRESC_MASK>>_TIMER_CTRL_PRESC_SHIFT))
+      if (prescaler > (_TIMER_CTRL_PRESC_MASK>>_TIMER_CTRL_PRESC_SHIFT))
         {
           return -1;
         }

arch/arm/src/efm32/efm32_usbdev.c

@@ -813,10 +813,11 @@ static uint32_t efm32_getreg(uint32_t addr)
     {
       if (count == 0xffffffff || ++count > 3)
         {
-           if (count == 4)
-             {
-               lldbg("...\n");
-             }
+          if (count == 4)
+            {
+              lldbg("...\n");
+            }
+
           return val;
         }
     }

arch/arm/src/efm32/efm32_usbhost.c

@@ -73,8 +73,7 @@
  * Pre-processor Definitions
  ****************************************************************************/
 /* Configuration ***************************************************************/
-/*
- * EFM32 USB OTG FS Host Driver Support
+/* EFM32 USB OTG FS Host Driver Support
  *
  * Pre-requisites
  *
@@ -806,14 +805,14 @@ static void efm32_chan_free(FAR struct efm32_usbhost_s *priv, int chidx)
 
 static inline void efm32_chan_freeall(FAR struct efm32_usbhost_s *priv)
 {
-   uint8_t chidx;
+  uint8_t chidx;
 
-   /* Free all host channels */
+  /* Free all host channels */
 
-   for (chidx = 2; chidx < EFM32_NHOST_CHANNELS; chidx ++)
-     {
-       efm32_chan_free(priv, chidx);
-     }
+  for (chidx = 2; chidx < EFM32_NHOST_CHANNELS; chidx ++)
+    {
+      efm32_chan_free(priv, chidx);
+    }
 }
 
 /****************************************************************************
@@ -2282,7 +2281,7 @@ static void efm32_out_next(FAR struct efm32_usbhost_s *priv,
   int result;
   int ret;
 
-  /* Is the full transfer complete? Did the last chunk transfer complete OK?*/
+  /* Is the full transfer complete? Did the last chunk transfer complete OK? */
 
   result = -(int)chan->result;
   if (chan->xfrd < chan->buflen && result == OK)
@@ -2936,11 +2935,11 @@ static void efm32_gint_disconnected(FAR struct efm32_usbhost_s *priv)
 
       /* Are we bound to a class driver? */
 
-      if ( priv->rhport.hport.devclass)
+      if (priv->rhport.hport.devclass)
         {
           /* Yes.. Disconnect the class driver */
 
-          CLASS_DISCONNECTED( priv->rhport.hport.devclass);
+          CLASS_DISCONNECTED(priv->rhport.hport.devclass);
            priv->rhport.hport.devclass = NULL;
         }
 

arch/arm/src/imx/imx_gpio.c

@@ -106,7 +106,7 @@ void imxgpio_configpfoutput(int port, int bit)
 {
   imxgpio_configinput(port, bit);            /* Same as input except: */
   imxgpio_peripheralfunc(port, bit);         /*   Use as peripheral */
-  imxgpio_primaryperipheralfunc(port, bit);  /*   Primary function*/
+  imxgpio_primaryperipheralfunc(port, bit);  /*   Primary function */
   imxgpio_dirout(port, bit);                 /*   Make output */
 }
 
@@ -118,5 +118,5 @@ void imxgpio_configpfinput(int port, int bit)
 {
   imxgpio_configinput(port, bit);            /* Same as input except: */
   imxgpio_peripheralfunc(port, bit);         /*   Use as peripheral */
-  imxgpio_primaryperipheralfunc(port, bit);  /*   Primary function*/
+  imxgpio_primaryperipheralfunc(port, bit);  /*   Primary function */
 }

arch/arm/src/imx/imx_serial.c

@@ -524,7 +524,7 @@ static int up_setup(struct uart_dev_s *dev)
       /* Set CTS trigger level */
 
       regval |= 30 << UART_UCR4_CTSTL_SHIFT;
-   }
+    }
 #endif
 
   /* i.MX reference clock (PERCLK1) is configured for 16MHz */
@@ -546,15 +546,15 @@ static int up_setup(struct uart_dev_s *dev)
    * First, select a closest value we can for the divider
    */
 
-   div = (IMX_PERCLK1_FREQ >> 4) / priv->baud;
-   if (div > 7)
-     {
-       div = 7;
-     }
-   else if (div < 1)
-     {
-       div = 1;
-     }
+  div = (IMX_PERCLK1_FREQ >> 4) / priv->baud;
+  if (div > 7)
+    {
+      div = 7;
+    }
+  else if (div < 1)
+    {
+      div = 1;
+    }
 
   /* Now find the numerator and denominator.  These must have
    * the ratio baud/(PERCLK / div / 16), but the values cannot

arch/arm/src/imx/imx_spi.c

@@ -139,7 +139,7 @@ struct imx_spidev_s
  * Private Function Prototypes
  ****************************************************************************/
 
- /* SPI register access */
+/* SPI register access */
 
 static inline uint32_t spi_getreg(struct imx_spidev_s *priv, unsigned int offset);
 static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32_t value);
@@ -468,11 +468,11 @@ static void spi_startxfr(struct imx_spidev_s *priv, int ntxd)
    */
 
   if (ntxd > 0)
-   {
+    {
       regval = spi_getreg(priv, CSPI_CTRL_OFFSET);
       regval |= CSPI_CTRL_XCH;
       spi_putreg(priv, CSPI_CTRL_OFFSET, regval);
-   }
+    }
 }
 
 /****************************************************************************
@@ -773,7 +773,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
           freqbits = CSPI_CTRL_DIV256;
           actual   = IMX_PERCLK2_FREQ / 256;
         }
-      else /*if (frequency >= IMX_PERCLK2_FREQ / 512) */
+      else /* if (frequency >= IMX_PERCLK2_FREQ / 512) */
         {
           freqbits = CSPI_CTRL_DIV512;
           actual   = IMX_PERCLK2_FREQ / 512;

arch/arm/src/kinetis/kinetis_enet.c

@@ -394,7 +394,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
   txdesc->length  = kinesis_swap16(priv->dev.d_len);
 #ifdef CONFIG_ENET_ENHANCEDBD
   txdesc->bdu     = 0x00000000;
-  txdesc->status2 = TXDESC_INT | TXDESC_TS; // | TXDESC_IINS | TXDESC_PINS;
+  txdesc->status2 = TXDESC_INT | TXDESC_TS; /* | TXDESC_IINS | TXDESC_PINS; */
 #endif
   txdesc->status1 = (TXDESC_R | TXDESC_L | TXDESC_TC | TXDESC_W);
 
@@ -480,7 +480,7 @@ static int kinetis_txpoll(struct net_driver_s *dev)
 
       if (kinetics_txringfull(priv))
         {
-           return -EBUSY;
+          return -EBUSY;
         }
     }
 
@@ -603,7 +603,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
            */
 
           if (priv->dev.d_len > 0)
-           {
+            {
               /* Update the Ethernet header with the correct MAC address */
 
 #ifdef CONFIG_NET_IPv4

arch/arm/src/kinetis/kinetis_irq.c

@@ -287,8 +287,8 @@ static int kinetis_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
 
   else
     {
-       *regaddr = NVIC_SYSHCON;
-       if (irq == KINETIS_IRQ_MEMFAULT)
+      *regaddr = NVIC_SYSHCON;
+      if (irq == KINETIS_IRQ_MEMFAULT)
         {
           *bit = NVIC_SYSHCON_MEMFAULTENA;
         }

arch/arm/src/kinetis/kinetis_lowputc.c

@@ -169,7 +169,7 @@ void up_lowputc(char ch)
   while ((getreg8(CONSOLE_BASE+KINETIS_UART_S1_OFFSET) & UART_S1_TDRE) == 0);
 #endif
 
- /* Then write the character to the UART data register */
+  /* Then write the character to the UART data register */
 
   putreg8((uint8_t)ch, CONSOLE_BASE+KINETIS_UART_D_OFFSET);
 #endif

arch/arm/src/kinetis/kinetis_pinirq.c

@@ -128,7 +128,7 @@ static int kinetis_portinterrupt(int irq, FAR void *context,
        */
 
       uint32_t bit = (1 << i);
-      if ((isfr & bit ) != 0)
+      if ((isfr & bit) != 0)
         {
           /* I think that bits may be set in the ISFR for DMA activities
            * well.  So, no error is declared if there is no registered
@@ -372,7 +372,7 @@ void kinetis_pinirqenable(uint32_t pinset)
             regval |= PORT_PCR_IRQC_ZERO;
             break;
 
-          case PIN_INT_RISING : /* Interrupt on rising edge*/
+          case PIN_INT_RISING : /* Interrupt on rising edge */
             regval |= PORT_PCR_IRQC_RISING;
             break;
 

arch/arm/src/kinetis/kinetis_sdhc.c

@@ -1047,7 +1047,7 @@ static void kinetis_endtransfer(struct kinetis_dev_s *priv, sdio_eventset_t wkup
   /* If this was a DMA transfer, make sure that DMA is stopped */
 
 #ifdef CONFIG_SDIO_DMA
-  /* Stop the DMA by resetting the data path*/
+  /* Stop the DMA by resetting the data path */
 
   regval = getreg32(KINETIS_SDHC_SYSCTL);
   regval |= SDHC_SYSCTL_RSTD;
@@ -1420,8 +1420,8 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
    *   96MHz / 16 <= 400KHz <= 96MHz / 16 / 16    -- YES, prescaler == 16
    */
 
-  if (/*frequency >= (BOARD_CORECLK_FREQ / 2) && */
-        frequency <= (BOARD_CORECLK_FREQ / 2 / 16))
+  if (/* frequency >= (BOARD_CORECLK_FREQ / 2) && */
+      frequency <= (BOARD_CORECLK_FREQ / 2 / 16))
     {
       sdclkfs   = SDHC_SYSCTL_SDCLKFS_DIV2;
       prescaler = 2;
@@ -1791,7 +1791,7 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
       regval |= SDHC_XFERTYP_RSPTYP_NONE;
       break;
 
-    case MMCSD_R1B_RESPONSE:              /* Response length 48, check busy & cmdindex*/
+    case MMCSD_R1B_RESPONSE:              /* Response length 48, check busy & cmdindex */
       regval |= (SDHC_XFERTYP_RSPTYP_LEN48BSY|SDHC_XFERTYP_CICEN|SDHC_XFERTYP_CCCEN);
       break;
 
@@ -2002,7 +2002,7 @@ static int kinetis_cancel(FAR struct sdio_dev_s *dev)
   /* If this was a DMA transfer, make sure that DMA is stopped */
 
 #ifdef CONFIG_SDIO_DMA
-  /* Stop the DMA by resetting the data path*/
+  /* Stop the DMA by resetting the data path */
 
   regval = getreg32(KINETIS_SDHC_SYSCTL);
   regval |= SDHC_SYSCTL_RSTD;
@@ -2233,7 +2233,7 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r
         }
     }
 
-  /* Return the long response in CMDRSP3..0*/
+  /* Return the long response in CMDRSP3..0 */
 
   if (rlong)
     {
@@ -2404,7 +2404,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev,
 
       if (!timeout)
         {
-           return SDIOWAIT_TIMEOUT;
+          return SDIOWAIT_TIMEOUT;
         }
 
       /* Start the watchdog timer */

arch/arm/src/kinetis/kinetis_serial.c

@@ -590,9 +590,9 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie)
 
   flags = irqsave();
   if (ie)
-   {
-     *ie = priv->ie;
-   }
+    {
+      *ie = priv->ie;
+    }
 
   up_restoreuartint(priv, 0);
   irqrestore(flags);

arch/arm/src/kinetis/kinetis_timerisr.c

@@ -100,10 +100,10 @@
 
 int up_timerisr(int irq, uint32_t *regs)
 {
-   /* Process timer interrupt */
+  /* Process timer interrupt */
 
-   sched_process_timer();
-   return 0;
+  sched_process_timer();
+  return 0;
 }
 
 /****************************************************************************

arch/arm/src/kl/kl_clockconfig.c

@@ -243,4 +243,3 @@ void kl_clockconfig(void)
   //kl_traceconfig();
   //kl_fbconfig();
 }
-