diff --git a/arch/arm/src/a1x/a1x_pio.c b/arch/arm/src/a1x/a1x_pio.c index fbda9608088..bc80416d870 100644 --- a/arch/arm/src/a1x/a1x_pio.c +++ b/arch/arm/src/a1x/a1x_pio.c @@ -67,7 +67,7 @@ ****************************************************************************/ /**************************************************************************** - * Private Function Prototypes + * Private Functions ****************************************************************************/ /**************************************************************************** * Name: a1x_pio_pin diff --git a/arch/arm/src/armv6-m/up_vectors.c b/arch/arm/src/armv6-m/up_vectors.c index a1cd64ff791..b40d6c28870 100644 --- a/arch/arm/src/armv6-m/up_vectors.c +++ b/arch/arm/src/armv6-m/up_vectors.c @@ -85,16 +85,16 @@ extern char _ebss; */ unsigned _vectors[] __attribute__((section(".vectors"))) = - { - /* Initial stack */ +{ + /* Initial stack */ - IDLE_STACK, + IDLE_STACK, - /* Reset exception handler */ + /* Reset exception handler */ - (unsigned)&__start, + (unsigned)&__start, - /* Vectors 2 - n point directly at the generic handler */ + /* Vectors 2 - n point directly at the generic handler */ - [2 ... (15 + ARMV6M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common - }; + [2 ... (15 + ARMV6M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common +}; diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c index 9814b7e8ea5..9a8fc6b05dd 100644 --- a/arch/arm/src/armv7-a/arm_syscall.c +++ b/arch/arm/src/armv7-a/arm_syscall.c @@ -128,7 +128,7 @@ static void dispatch_syscall(void) " str lr, [sp, #12]\n" /* Save lr in the stack frame */ " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */ " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */ - " blx ip\n" /* Call the stub (modifies lr)*/ + " blx ip\n" /* Call the stub (modifies lr) */ " ldr lr, [sp, #12]\n" /* Restore lr */ " add sp, sp, #16\n" /* Destroy the stack frame */ " mov r2, r0\n" /* R2=Save return value in R2 */ diff --git a/arch/arm/src/armv7-a/arm_virtpgaddr.c b/arch/arm/src/armv7-a/arm_virtpgaddr.c index 71b5099b76b..741bf8d1227 100644 --- a/arch/arm/src/armv7-a/arm_virtpgaddr.c +++ b/arch/arm/src/armv7-a/arm_virtpgaddr.c @@ -85,4 +85,4 @@ uintptr_t arm_virtpgaddr(uintptr_t paddr) return 0; } -#endif /* CONFIG_MM_PGALLOC && CONFIG_ARCH_PGPOOL_MAPPING*/ +#endif /* CONFIG_MM_PGALLOC && CONFIG_ARCH_PGPOOL_MAPPING */ diff --git a/arch/arm/src/armv7-m/arch_enable_dcache.c b/arch/arm/src/armv7-m/arch_enable_dcache.c index ad0c82fef29..9c1abe47c69 100644 --- a/arch/arm/src/armv7-m/arch_enable_dcache.c +++ b/arch/arm/src/armv7-m/arch_enable_dcache.c @@ -114,7 +114,7 @@ void arch_enable_dcache(void) } while (tmpways--); } - while(sets--); + while (sets--); ARM_DSB(); diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c index 103c5bd0367..dafbbc47767 100644 --- a/arch/arm/src/armv7-m/up_svcall.c +++ b/arch/arm/src/armv7-m/up_svcall.c @@ -130,7 +130,7 @@ static void dispatch_syscall(void) " str lr, [sp, #12]\n" /* Save lr in the stack frame */ " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */ " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this syscall */ - " blx ip\n" /* Call the stub (modifies lr)*/ + " blx ip\n" /* Call the stub (modifies lr) */ " ldr lr, [sp, #12]\n" /* Restore lr */ " add sp, sp, #16\n" /* Destroy the stack frame */ " mov r2, r0\n" /* R2=Save return value in R2 */ diff --git a/arch/arm/src/armv7-m/up_vectors.c b/arch/arm/src/armv7-m/up_vectors.c index ab24f901f06..ada819c3315 100644 --- a/arch/arm/src/armv7-m/up_vectors.c +++ b/arch/arm/src/armv7-m/up_vectors.c @@ -80,16 +80,16 @@ extern char _ebss; */ unsigned _vectors[] __attribute__((section(".vectors"))) = - { - /* Initial stack */ +{ + /* Initial stack */ - IDLE_STACK, + IDLE_STACK, - /* Reset exception handler */ + /* Reset exception handler */ - (unsigned)&__start, + (unsigned)&__start, - /* Vectors 2 - n point directly at the generic handler */ + /* Vectors 2 - n point directly at the generic handler */ - [2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common - }; + [2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common +}; diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index 79c4adaa02e..866e502f731 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -871,11 +871,11 @@ static int c5471_transmit(struct c5471_driver_s *c5471) /* Words #0 and #1 of descriptor */ while (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) - { - /* Loop until the SWITCH lets go of the descriptor giving us access - * rights to submit our new ether frame to it. - */ - } + { + /* Loop until the SWITCH lets go of the descriptor giving us access + * rights to submit our new ether frame to it. + */ + } if (bfirstframe) { @@ -1683,7 +1683,7 @@ static int c5471_ifup(struct net_driver_s *dev) ndbg("Bringing up: %d.%d.%d.%d\n", dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Initilize Ethernet interface */ @@ -2244,12 +2244,12 @@ void up_netinitialize(void) g_c5471[0].c_dev.d_addmac = c5471_addmac; /* Add multicast MAC address */ g_c5471[0].c_dev.d_rmmac = c5471_rmmac; /* Remove multicast MAC address */ #endif - g_c5471[0].c_dev.d_private = (void*)g_c5471; /* Used to recover private state from dev */ + g_c5471[0].c_dev.d_private = (void*)g_c5471; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmisstions */ - g_c5471[0].c_txpoll = wd_create(); /* Create periodic poll timer */ - g_c5471[0].c_txtimeout = wd_create(); /* Create TX timeout timer */ + g_c5471[0].c_txpoll = wd_create(); /* Create periodic poll timer */ + g_c5471[0].c_txtimeout = wd_create(); /* Create TX timeout timer */ /* Register the device with the OS so that socket IOCTLs can be performed */ @@ -2257,4 +2257,3 @@ void up_netinitialize(void) } #endif /* CONFIG_NET */ - diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c index 4aa51ff6ad6..6e616a787bd 100644 --- a/arch/arm/src/c5471/c5471_serial.c +++ b/arch/arm/src/c5471/c5471_serial.c @@ -562,18 +562,18 @@ static int up_interrupt(int irq, void *context) /* Is this an interrupt from the IrDA UART? */ if (irq == C5471_IRQ_UART_IRDA) - { - /* Save the currently enabled IrDA UART interrupts - * so that we can restore the IrDA interrupt state - * below. - */ + { + /* Save the currently enabled IrDA UART interrupts + * so that we can restore the IrDA interrupt state + * below. + */ - ier_val = up_inserial(priv, UART_IER_OFFS); + ier_val = up_inserial(priv, UART_IER_OFFS); - /* Then disable all IrDA UART interrupts */ + /* Then disable all IrDA UART interrupts */ - up_serialout(priv, UART_IER_OFFS, 0); - } + up_serialout(priv, UART_IER_OFFS, 0); + } /* Receive characters from the RX fifo */ diff --git a/arch/arm/src/c5471/c5471_timerisr.c b/arch/arm/src/c5471/c5471_timerisr.c index 065a15728b8..6f1ca3da87b 100644 --- a/arch/arm/src/c5471/c5471_timerisr.c +++ b/arch/arm/src/c5471/c5471_timerisr.c @@ -92,10 +92,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** @@ -125,4 +125,3 @@ void up_timer_initialize(void) irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)up_timerisr); up_enable_irq(C5471_IRQ_SYSTIMER); } - diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c index c76a0dd4a98..2143246d6e7 100644 --- a/arch/arm/src/c5471/c5471_watchdog.c +++ b/arch/arm/src/c5471/c5471_watchdog.c @@ -296,7 +296,7 @@ static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* Process the IOCTL command (see arch/watchdog.h) */ - switch(cmd) + switch (cmd) { case WDIOC_KEEPALIVE: wdt_setusec(MAX_WDT_USEC); diff --git a/arch/arm/src/calypso/calypso_heap.c b/arch/arm/src/calypso/calypso_heap.c index 7193fa1a7c2..14d73b11ce4 100644 --- a/arch/arm/src/calypso/calypso_heap.c +++ b/arch/arm/src/calypso/calypso_heap.c @@ -80,7 +80,7 @@ void up_addregion(void) /* Disable watchdog in first non-common function */ wdog_enable(0); #endif - // XXX: change to initialization of extern memory with save defaults + /* XXX: change to initialization of extern memory with save defaults */ /* Configure memory interface */ calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1); calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1); diff --git a/arch/arm/src/calypso/calypso_keypad.c b/arch/arm/src/calypso/calypso_keypad.c index 4ff6a520693..e32bcc9a12e 100644 --- a/arch/arm/src/calypso/calypso_keypad.c +++ b/arch/arm/src/calypso/calypso_keypad.c @@ -143,7 +143,7 @@ static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len) *state |= 0x80000000; } - return 1; // break loop in caller + return 1; /* break loop in caller */ } else { @@ -164,7 +164,7 @@ static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len) } } - return 0; // continue with other columns + return 0; /* Continue with other columns */ } /**************************************************************************** diff --git a/arch/arm/src/calypso/calypso_serial.c b/arch/arm/src/calypso/calypso_serial.c index fa5587a2e87..8a7c181505e 100644 --- a/arch/arm/src/calypso/calypso_serial.c +++ b/arch/arm/src/calypso/calypso_serial.c @@ -73,7 +73,9 @@ #if UART_FCR_OFFS == UART_EFR_OFFS # define UART_MULTIPLEX_REGS -// HW flow control not supported yet + +/* HW flow control not supported yet */ + # undef CONFIG_UART_HWFLOWCONTROL #endif @@ -622,18 +624,18 @@ static int up_interrupt(int irq, void *context) /* Is this an interrupt from the IrDA UART? */ if (irq == UART_IRQ_IRDA) - { - /* Save the currently enabled IrDA UART interrupts - * so that we can restore the IrDA interrupt state - * below. - */ + { + /* Save the currently enabled IrDA UART interrupts + * so that we can restore the IrDA interrupt state + * below. + */ - ier_val = up_inserial(priv, UART_IER_OFFS); + ier_val = up_inserial(priv, UART_IER_OFFS); - /* Then disable all IrDA UART interrupts */ + /* Then disable all IrDA UART interrupts */ - up_serialout(priv, UART_IER_OFFS, 0); - } + up_serialout(priv, UART_IER_OFFS, 0); + } /* Receive characters from the RX fifo */ diff --git a/arch/arm/src/calypso/calypso_spi.c b/arch/arm/src/calypso/calypso_spi.c index 7357ccd67a7..b33b08b133c 100644 --- a/arch/arm/src/calypso/calypso_spi.c +++ b/arch/arm/src/calypso/calypso_spi.c @@ -223,18 +223,18 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) /* wait until the transfer is complete */ while (1) - { - reg_status = getreg16(SPI_REG(REG_STATUS)); - dbg("status=0x%04x ", reg_status); - if (din && (reg_status & SPI_STATUS_RE)) - { - break; - } - else if (reg_status & SPI_STATUS_WE) - { - break; - } - } + { + reg_status = getreg16(SPI_REG(REG_STATUS)); + dbg("status=0x%04x ", reg_status); + if (din && (reg_status & SPI_STATUS_RE)) + { + break; + } + else if (reg_status & SPI_STATUS_WE) + { + break; + } + } /* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */ diff --git a/arch/arm/src/calypso/calypso_timer.c b/arch/arm/src/calypso/calypso_timer.c index 548e2240638..7b98041670a 100644 --- a/arch/arm/src/calypso/calypso_timer.c +++ b/arch/arm/src/calypso/calypso_timer.c @@ -161,11 +161,11 @@ void wdog_enable(int on) void wdog_reset(void) { - // enable watchdog + /* Enable watchdog */ putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE)); - // force expiration + /* Force expiration */ putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER)); putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER)); @@ -186,10 +186,10 @@ void wdog_reset(void) int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/common/up_checkstack.c b/arch/arm/src/common/up_checkstack.c index 03cea836d30..dbf08f2ecce 100644 --- a/arch/arm/src/common/up_checkstack.c +++ b/arch/arm/src/common/up_checkstack.c @@ -136,7 +136,7 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size) } up_putc(ch); - } + } up_putc('\n'); } diff --git a/arch/arm/src/common/up_createstack.c b/arch/arm/src/common/up_createstack.c index 0903269f8dc..d7b010054d8 100644 --- a/arch/arm/src/common/up_createstack.c +++ b/arch/arm/src/common/up_createstack.c @@ -231,7 +231,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) return OK; } - return ERROR; + return ERROR; } /**************************************************************************** diff --git a/arch/arm/src/common/up_interruptcontext.c b/arch/arm/src/common/up_interruptcontext.c index c7c7b204909..ec40db40174 100644 --- a/arch/arm/src/common/up_interruptcontext.c +++ b/arch/arm/src/common/up_interruptcontext.c @@ -66,5 +66,5 @@ bool up_interrupt_context(void) { - return current_regs != NULL; + return current_regs != NULL; } diff --git a/arch/arm/src/common/up_vfork.c b/arch/arm/src/common/up_vfork.c index 2c7f183f956..655619d8de2 100644 --- a/arch/arm/src/common/up_vfork.c +++ b/arch/arm/src/common/up_vfork.c @@ -210,12 +210,12 @@ pid_t up_vfork(const struct vfork_s *context) svdbg("Child: stack base:%08x SP:%08x FP:%08x\n", child->cmn.adj_stack_ptr, newsp, newfp); - /* Update the stack pointer, frame pointer, and volatile registers. When - * the child TCB was initialized, all of the values were set to zero. - * up_initial_state() altered a few values, but the return value in R0 - * should be cleared to zero, providing the indication to the newly started - * child thread. - */ + /* Update the stack pointer, frame pointer, and volatile registers. When + * the child TCB was initialized, all of the values were set to zero. + * up_initial_state() altered a few values, but the return value in R0 + * should be cleared to zero, providing the indication to the newly started + * child thread. + */ child->cmn.xcp.regs[REG_R4] = context->r4; /* Volatile register r4 */ child->cmn.xcp.regs[REG_R5] = context->r5; /* Volatile register r5 */ diff --git a/arch/arm/src/dm320/dm320_framebuffer.c b/arch/arm/src/dm320/dm320_framebuffer.c index 9e8c9dc752c..e3471c3b39b 100644 --- a/arch/arm/src/dm320/dm320_framebuffer.c +++ b/arch/arm/src/dm320/dm320_framebuffer.c @@ -1201,15 +1201,15 @@ static int dm320_putcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *c flags = irqsave(); for (i = cmap.first, len = 0; i < 256 && len < cmap.len, i++, len++) { - /* Convert the RGB to YUV */ + /* Convert the RGB to YUV */ - nxgl_rgb2yuv(cmap->red[i], cmap->green[i], cmap->blue[i], &y, &u, &v); + nxgl_rgb2yuv(cmap->red[i], cmap->green[i], cmap->blue[i], &y, &u, &v); - /* Program the CLUT */ + /* Program the CLUT */ - while (getreg16(DM320_OSD_MISCCTL) & 0x8); - putreg16(((uint16_t)y) << 8 | uint16_t(u)), DM320_OSD_CLUTRAMYCB); - putreg16(((uint16_t)v << 8 | i), DM320_OSD_CLUTRAMCR); + while (getreg16(DM320_OSD_MISCCTL) & 0x8); + putreg16(((uint16_t)y) << 8 | uint16_t(u)), DM320_OSD_CLUTRAMYCB); + putreg16(((uint16_t)v << 8 | i), DM320_OSD_CLUTRAMCR); } /* Select RAM clut */ @@ -1296,10 +1296,10 @@ static int dm320_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcurs { gvdbg("x=%d y=%d\n", settings->pos.x, settings->pos.y); - if (settings->pos.x > MAX_YRES) - { + if (settings->pos.x > MAX_YRES) + { settings->pos.x = MAX_YRES; - } + } if (settings->pos.y > MAX_YRES) { diff --git a/arch/arm/src/dm320/dm320_irq.c b/arch/arm/src/dm320/dm320_irq.c index e1ce9c420c3..99274c3fbf7 100644 --- a/arch/arm/src/dm320/dm320_irq.c +++ b/arch/arm/src/dm320/dm320_irq.c @@ -102,9 +102,9 @@ void up_irqinitialize(void) putreg16(0xffff, DM320_INTC_IRQ1); putreg16(0xffff, DM320_INTC_IRQ2); - /* Make sure that the base addresses are zero and that - * the table increment is 4 bytes. - */ + /* Make sure that the base addresses are zero and that + * the table increment is 4 bytes. + */ putreg16(0, DM320_INTC_EABASE0); putreg16(0, DM320_INTC_EABASE1); diff --git a/arch/arm/src/dm320/dm320_timerisr.c b/arch/arm/src/dm320/dm320_timerisr.c index aaa365387b6..e88cac0630c 100644 --- a/arch/arm/src/dm320/dm320_timerisr.c +++ b/arch/arm/src/dm320/dm320_timerisr.c @@ -119,10 +119,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index 612af872717..389fc845b0a 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -441,10 +441,11 @@ static uint8_t dm320_getreg8(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return val; } } @@ -727,7 +728,7 @@ static int dm320_ep0write(uint8_t *buf, uint16_t nbytes) uint16_t bytesleft; uint16_t nwritten; - if ( nbytes <= DM320_EP0MAXPACKET) + if (nbytes <= DM320_EP0MAXPACKET) { bytesleft = nbytes; csr0 |= USB_PERCSR0_DATAEND; /* Transaction end bit */ @@ -762,13 +763,13 @@ static int dm320_epwrite(uint8_t epphy, uint8_t *buf, uint16_t nbytes) uint16_t bytesleft; int ret = ERROR; - if (/*epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS) + if (/* epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS) { return ret; } dm320_putreg8(epphy, DM320_USB_INDEX); - if (epphy == USB_EP0_SELECT ) + if (epphy == USB_EP0_SELECT) { return dm320_ep0write(buf, nbytes); } @@ -813,7 +814,7 @@ static int dm320_epread(uint8_t epphy, uint8_t *buf, uint16_t nbytes) int bytesleft; int ret = ERROR; - if (/*epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS) + if (/* epphy < USB_EP0_SELECT || */ epphy >= DM320_NENDPOINTS) { return ret; } @@ -1848,7 +1849,7 @@ static void dm320_ctrlinitialize(FAR struct dm320_usbdev_s *priv) priv->paddr = 0; dm320_putreg8(0, DM320_USB_FADDR); - /* Finished -- set default endpoint as EP0*/ + /* Finished -- set default endpoint as EP0 */ dm320_putreg8(USB_EP0_SELECT, DM320_USB_INDEX); } @@ -2133,6 +2134,7 @@ static int dm320_epcancel(struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) return -EINVAL; } #endif + usbtrace(TRACE_EPCANCEL, privep->epphy); priv = privep->dev; @@ -2516,7 +2518,7 @@ int usbdev_register(FAR struct usbdevclass_driver_s *driver) /* Hook up the driver */ - g_usbdev.driver = driver; + g_usbdev.driver = driver; /* Then bind the class driver */ diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c index c23654c66f5..c8415970188 100644 --- a/arch/arm/src/efm32/efm32_adc.c +++ b/arch/arm/src/efm32/efm32_adc.c @@ -113,8 +113,8 @@ struct efm32_dev_s /* ADC Register access */ -static uint32_t adc_getreg( struct efm32_dev_s *priv, int offset); -static void adc_putreg( struct efm32_dev_s *priv, int offset, uint32_t value); +static uint32_t adc_getreg(struct efm32_dev_s *priv, int offset); +static void adc_putreg(struct efm32_dev_s *priv, int offset, uint32_t value); static void adc_hw_reset(struct efm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ @@ -662,9 +662,9 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq) /* Just in case, make sure we get non-zero freq for below calculation */ if (!hfperFreq) - { - hfperFreq = 1; - } + { + hfperFreq = 1; + } } #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) @@ -675,7 +675,7 @@ uint8_t ADC_TimebaseCalc(uint32_t hfperFreq) * See reference manual for details. */ - if (hfperFreq > 32000000 ) + if (hfperFreq > 32000000) { hfperFreq = 32000000; } diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c index 75af2d75898..40e1739084d 100644 --- a/arch/arm/src/efm32/efm32_clockconfig.c +++ b/arch/arm/src/efm32/efm32_clockconfig.c @@ -154,7 +154,7 @@ static inline void efm32_statuswait(uint32_t bitset) { /* Wait for clock to stabilize if requested */ - while ((getreg32(EFM32_CMU_STATUS) & bitset) == 0); + while ((getreg32(EFM32_CMU_STATUS) & bitset) == 0); } /**************************************************************************** @@ -502,7 +502,7 @@ static inline uint32_t efm32_hfclk_config(uint32_t hfclksel, uint32_t hfclkdiv) ****************************************************************************/ #ifdef CONFIG_EFM32_LECLOCK -uint32_t efm32_coreleclk_config( int frequency ) +uint32_t efm32_coreleclk_config(int frequency) { #ifdef CMU_CTRL_HFLE uint32_t regval; diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c index 231612b0e81..014f3f8cae6 100644 --- a/arch/arm/src/efm32/efm32_flash.c +++ b/arch/arm/src/efm32/efm32_flash.c @@ -240,7 +240,9 @@ int __ramfunc__ msc_load_verify_address(uint32_t* address) /* Check for invalid address */ if (status & MSC_STATUS_INVADDR) - return -EINVAL; + { + return -EINVAL; + } /* Check for write protected page */ @@ -374,7 +376,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, DEBUGASSERT(BOARD_SYSTEM_FREQUENCY >= 1000000); word_index = 0; - while(word_index < num_words) + while (word_index < num_words) { putreg32(*data++,EFM32_MSC_WDATA); word_index++; @@ -431,7 +433,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, word_index = 0; - while(word_index < num_words) + while (word_index < num_words) { /* Wait for the MSC to be ready for the next word. */ diff --git a/arch/arm/src/efm32/efm32_gpio.c b/arch/arm/src/efm32/efm32_gpio.c index 6a818c93c92..77bc980481d 100644 --- a/arch/arm/src/efm32/efm32_gpio.c +++ b/arch/arm/src/efm32/efm32_gpio.c @@ -57,7 +57,7 @@ #define __GPIO_DOUT (1 << 2) /* Bit 2: An input modified with DOUT setting */ #define __GPIO_DRIVE (1 << 3) /* Bit 3: An output with drive selection */ - /************************************************************************************ +/************************************************************************************ * Private Data ************************************************************************************/ diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c index b1cf9132461..495b920cd91 100644 --- a/arch/arm/src/efm32/efm32_i2c.c +++ b/arch/arm/src/efm32/efm32_i2c.c @@ -126,7 +126,7 @@ /* Macros to convert a I2C pin to a GPIO output */ -#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD ) +#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD) #define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) @@ -873,8 +873,8 @@ static void efm32_i2c_setclock(FAR struct efm32_i2c_priv_s *priv, #if defined(CONFIG_EFM32_I2C_CLHR_FAST) # define n (11 + 6) /* Ratio is 11:3 */ #elif defined(CONFIG_EFM32_I2C_CLHR_ASYMMETRIC) -# define n ( 6 + 3) /* Ratio is 6:3 */ -#else /* CLHR STANDARD */ +# define n (6 + 3) /* Ratio is 6:3 */ +#else /* CLHR STANDARD */ # define n ( 4 + 4) /* Ratio is 4:4 */ #endif @@ -1284,7 +1284,6 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv) } done: - if (priv->i2c_state == I2CSTATE_DONE) { #ifndef CONFIG_I2C_POLLED @@ -1607,35 +1606,35 @@ static int efm32_i2c_process(FAR struct i2c_dev_s *dev, { /* Check for error status conditions */ - switch(priv->result) + switch (priv->result) { - /* Arbitration lost during transfer. */ + /* Arbitration lost during transfer. */ case I2CRESULT_ARBLOST: errval = EAGAIN; break; - /* NACK received during transfer. */ + /* NACK received during transfer. */ case I2CRESULT_NACK: errval = ENXIO; break; - /* SW fault. */ + /* SW fault. */ case I2CRESULT_SWFAULT: errval = EIO; break; - /* Usage fault. */ + /* Usage fault. */ case I2CRESULT_USAGEFAULT: errval = EINTR; break; - /* Bus error during transfer (misplaced START/STOP). - * I2C Bus is for some reason busy - */ + /* Bus error during transfer (misplaced START/STOP). + * I2C Bus is for some reason busy + */ case I2CRESULT_BUSERR: errval = EBUSY; @@ -1975,7 +1974,6 @@ int up_i2creset(FAR struct i2c_dev_s *dev) ret = OK; out: - /* Release the port for re-use by other clients */ efm32_i2c_sem_post(dev); diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c index 9923bcdf259..1b6bb187901 100644 --- a/arch/arm/src/efm32/efm32_irq.c +++ b/arch/arm/src/efm32/efm32_irq.c @@ -313,8 +313,8 @@ static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { - *regaddr = NVIC_SYSHCON; - if (irq == EFM32_IRQ_MEMFAULT) + *regaddr = NVIC_SYSHCON; + if (irq == EFM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index d0e0e80cb88..9ae4fd8341e 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -343,9 +343,9 @@ static void efm32_disableuartint(struct efm32_leuart_s *priv, uint32_t *ien) flags = irqsave(); if (ien) - { - *ien = priv->ien; - } + { + *ien = priv->ien; + } efm32_restoreuartint(priv, 0); irqrestore(flags); @@ -362,12 +362,12 @@ static void efm32_disableuartint(struct efm32_leuart_s *priv, uint32_t *ien) static int efm32_setup(struct uart_dev_s *dev) { - struct efm32_leuart_s *priv = (struct efm32_leuart_s*)dev->priv; + struct efm32_leuart_s *priv = (struct efm32_leuart_s*)dev->priv; #ifndef CONFIG_SUPPRESS_LEUART_CONFIG - const struct efm32_config_s *config = priv->config; + const struct efm32_config_s *config = priv->config; - /* Configure the UART as an RS-232 UART */ + /* Configure the UART as an RS-232 UART */ efm32_leuartconfigure(config->uartbase, config->baud, config->parity, config->bits, config->stop2); diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c index 20c2d44f5a8..d0240c8b4d6 100644 --- a/arch/arm/src/efm32/efm32_pwm.c +++ b/arch/arm/src/efm32/efm32_pwm.c @@ -410,7 +410,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, #error "Not implemented ! Sorry" #endif - if ( efm32_timer_set_freq(priv->base,priv->pclk,info->frequency) < 0 ) + if (efm32_timer_set_freq(priv->base,priv->pclk,info->frequency) < 0) { pwmdbg("Cannot set TIMER frequency %dHz from clock %dHz\n", info->frequency, @@ -421,7 +421,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, regval = ((uint32_t)(priv->pinloc)) << _TIMER_ROUTE_LOCATION_SHIFT; - switch(priv->channel) + switch (priv->channel) { case 0: regval |= _TIMER_ROUTE_CC0PEN_MASK; @@ -439,7 +439,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, ASSERT(false); } - pwm_putreg( priv, EFM32_TIMER_ROUTE_OFFSET, regval ); + pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, regval); regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16; pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET , regval); @@ -449,11 +449,11 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, (_TIMER_CC_CTRL_CMOA_CLEAR << _TIMER_CC_CTRL_CMOA_SHIFT) | \ (_TIMER_CC_CTRL_COFOA_SET << _TIMER_CC_CTRL_COFOA_SHIFT) ; - pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CTRL_OFFSET, regval ); + pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CTRL_OFFSET, regval); /* Start Timer */ - pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_START ); + pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_START); pwm_dumpregs(priv, "After starting"); return OK; } @@ -676,7 +676,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) /* Dnable TIMER clock */ - switch(priv->timid) + switch (priv->timid) { case 0: modifyreg32(EFM32_CMU_HFPERCLKEN0,0,CMU_HFPERCLKEN0_TIMER0); @@ -819,7 +819,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) pwm_putreg(priv, EFM32_TIMER_CMD_OFFSET, TIMER_CMD_STOP); - irqrestore( flags); + irqrestore(flags); pwm_dumpregs(priv, "After stop"); return OK; diff --git a/arch/arm/src/efm32/efm32_rtc_burtc.c b/arch/arm/src/efm32/efm32_rtc_burtc.c index e31df780135..d14383f60f2 100644 --- a/arch/arm/src/efm32/efm32_rtc_burtc.c +++ b/arch/arm/src/efm32/efm32_rtc_burtc.c @@ -189,9 +189,9 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context) uint32_t source = getreg32(EFM32_BURTC_IF); if (source & BURTC_IF_LFXOFAIL) - { + { burtcdbg("BURTC_IF_LFXOFAIL"); - } + } #ifdef CONFIG_RTC_HIRES if (source & BURTC_IF_OF) diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index 92a2be9c181..8a970fc39e7 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -593,9 +593,9 @@ static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien) flags = irqsave(); if (ien) - { - *ien = priv->ien; - } + { + *ien = priv->ien; + } efm32_restoreuartint(priv, 0); irqrestore(flags); diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c index 8d0a05e288d..a042517e597 100644 --- a/arch/arm/src/efm32/efm32_spi.c +++ b/arch/arm/src/efm32/efm32_spi.c @@ -903,7 +903,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) * = 128 * fHFPERCLK / (256 + CLKDIV) */ - actual = (BOARD_HFPERCLK_FREQUENCY << 7) / ( 256 + clkdiv); + actual = (BOARD_HFPERCLK_FREQUENCY << 7) / (256 + clkdiv); spivdbg("frequency=%u actual=%u\n", frequency, actual); #ifndef CONFIG_SPI_OWNBUS @@ -1745,18 +1745,18 @@ struct spi_dev_s *efm32_spi_initialize(int port) /* Initialize the SPI device */ - ret = spi_portinitialize(priv); - if (ret < 0) - { - spidbg("ERROR: Failed to initialize SPI port %d\n", port); - irqrestore(flags); - return NULL; - } + ret = spi_portinitialize(priv); + if (ret < 0) + { + spidbg("ERROR: Failed to initialize SPI port %d\n", port); + irqrestore(flags); + return NULL; + } - /* Now we are initialized */ + /* Now we are initialized */ - priv->initialized = true; - irqrestore(flags); + priv->initialized = true; + irqrestore(flags); } return (struct spi_dev_s *)priv; diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c index 0364c3adb21..9326700d591 100644 --- a/arch/arm/src/efm32/efm32_start.c +++ b/arch/arm/src/efm32/efm32_start.c @@ -312,6 +312,6 @@ void __start(void) /* Shouldn't get here */ - for(;;); + for (;;); #endif } diff --git a/arch/arm/src/efm32/efm32_timer.c b/arch/arm/src/efm32/efm32_timer.c index 407a2a83971..d8047521abe 100644 --- a/arch/arm/src/efm32/efm32_timer.c +++ b/arch/arm/src/efm32/efm32_timer.c @@ -191,11 +191,13 @@ void efm32_timer_reset(uintptr_t base) putreg32(_TIMER_IEN_RESETVALUE, base + EFM32_TIMER_STATUS_OFFSET ); putreg32(_TIMER_IFC_MASK, base + EFM32_TIMER_IEN_OFFSET ); putreg32(_TIMER_TOP_RESETVALUE, base + EFM32_TIMER_IF_OFFSET ); - putreg32(_TIMER_TOPB_RESETVALUE, base + EFM32_TIMER_CTRL_OFFSET ); - putreg32(_TIMER_CNT_RESETVALUE, base + EFM32_TIMER_CMD_OFFSET ); + putreg32(_TIMER_TOPB_RESETVALUE, base + EFM32_TIMER_CTRL_OFFSET ); + putreg32(_TIMER_CNT_RESETVALUE, base + EFM32_TIMER_CMD_OFFSET ); + + /* Do not reset route register, setting should be done independently + * (Note: ROUTE register may be locked by DTLOCK register.) + */ - /* Do not reset route register, setting should be done independently */ - /* (Note: ROUTE register may be locked by DTLOCK register.) */ //putreg32(_TIMER_ROUTE_RESETVALUE, base + EFM32_TIMER_ROUTE_OFFSET ); for(i = 0; i < EFM32_TIMER_NCC; i++) @@ -219,13 +221,13 @@ void efm32_timer_reset(uintptr_t base) putreg32(_TIMER_DTOGEN_RESETVALUE,base + EFM32_TIMER_DTOGEN_OFFSET ); putreg32(_TIMER_DTFAULTC_MASK, base + EFM32_TIMER_DTFAULTC_OFFSET ); #endif -} +} /**************************************************************************** * Name: efm32_timer_set_freq * * Description: - * set prescaler and top timer with best value to have "freq" + * set prescaler and top timer with best value to have "freq" * * Input parameters: * base - A base address of timer @@ -239,14 +241,14 @@ void efm32_timer_reset(uintptr_t base) int efm32_timer_set_freq(uintptr_t base, uint32_t clk_freq, uint32_t freq) { int prescaler = 0; - int cnt_freq = clk_freq>>16; + int cnt_freq = clk_freq >> 16; int reload; - while ( cnt_freq > freq ) + while (cnt_freq > freq) { prescaler++; cnt_freq>>=1; - if ( prescaler > (_TIMER_CTRL_PRESC_MASK>>_TIMER_CTRL_PRESC_SHIFT)) + if (prescaler > (_TIMER_CTRL_PRESC_MASK>>_TIMER_CTRL_PRESC_SHIFT)) { return -1; } diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index 18fcb3c7768..9406fc163bf 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -813,10 +813,11 @@ static uint32_t efm32_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return val; } } diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index f9681d293bd..17ac5ea4231 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -73,8 +73,7 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ***************************************************************/ -/* - * EFM32 USB OTG FS Host Driver Support +/* EFM32 USB OTG FS Host Driver Support * * Pre-requisites * @@ -806,14 +805,14 @@ static void efm32_chan_free(FAR struct efm32_usbhost_s *priv, int chidx) static inline void efm32_chan_freeall(FAR struct efm32_usbhost_s *priv) { - uint8_t chidx; + uint8_t chidx; - /* Free all host channels */ + /* Free all host channels */ - for (chidx = 2; chidx < EFM32_NHOST_CHANNELS; chidx ++) - { - efm32_chan_free(priv, chidx); - } + for (chidx = 2; chidx < EFM32_NHOST_CHANNELS; chidx ++) + { + efm32_chan_free(priv, chidx); + } } /**************************************************************************** @@ -2282,7 +2281,7 @@ static void efm32_out_next(FAR struct efm32_usbhost_s *priv, int result; int ret; - /* Is the full transfer complete? Did the last chunk transfer complete OK?*/ + /* Is the full transfer complete? Did the last chunk transfer complete OK? */ result = -(int)chan->result; if (chan->xfrd < chan->buflen && result == OK) @@ -2936,11 +2935,11 @@ static void efm32_gint_disconnected(FAR struct efm32_usbhost_s *priv) /* Are we bound to a class driver? */ - if ( priv->rhport.hport.devclass) + if (priv->rhport.hport.devclass) { /* Yes.. Disconnect the class driver */ - CLASS_DISCONNECTED( priv->rhport.hport.devclass); + CLASS_DISCONNECTED(priv->rhport.hport.devclass); priv->rhport.hport.devclass = NULL; } diff --git a/arch/arm/src/imx/imx_gpio.c b/arch/arm/src/imx/imx_gpio.c index 94e87fdfef0..17ac2c83279 100644 --- a/arch/arm/src/imx/imx_gpio.c +++ b/arch/arm/src/imx/imx_gpio.c @@ -106,7 +106,7 @@ void imxgpio_configpfoutput(int port, int bit) { imxgpio_configinput(port, bit); /* Same as input except: */ imxgpio_peripheralfunc(port, bit); /* Use as peripheral */ - imxgpio_primaryperipheralfunc(port, bit); /* Primary function*/ + imxgpio_primaryperipheralfunc(port, bit); /* Primary function */ imxgpio_dirout(port, bit); /* Make output */ } @@ -118,5 +118,5 @@ void imxgpio_configpfinput(int port, int bit) { imxgpio_configinput(port, bit); /* Same as input except: */ imxgpio_peripheralfunc(port, bit); /* Use as peripheral */ - imxgpio_primaryperipheralfunc(port, bit); /* Primary function*/ + imxgpio_primaryperipheralfunc(port, bit); /* Primary function */ } diff --git a/arch/arm/src/imx/imx_serial.c b/arch/arm/src/imx/imx_serial.c index 96289cf8967..f17321acf3b 100644 --- a/arch/arm/src/imx/imx_serial.c +++ b/arch/arm/src/imx/imx_serial.c @@ -524,7 +524,7 @@ static int up_setup(struct uart_dev_s *dev) /* Set CTS trigger level */ regval |= 30 << UART_UCR4_CTSTL_SHIFT; - } + } #endif /* i.MX reference clock (PERCLK1) is configured for 16MHz */ @@ -546,15 +546,15 @@ static int up_setup(struct uart_dev_s *dev) * First, select a closest value we can for the divider */ - div = (IMX_PERCLK1_FREQ >> 4) / priv->baud; - if (div > 7) - { - div = 7; - } - else if (div < 1) - { - div = 1; - } + div = (IMX_PERCLK1_FREQ >> 4) / priv->baud; + if (div > 7) + { + div = 7; + } + else if (div < 1) + { + div = 1; + } /* Now find the numerator and denominator. These must have * the ratio baud/(PERCLK / div / 16), but the values cannot diff --git a/arch/arm/src/imx/imx_spi.c b/arch/arm/src/imx/imx_spi.c index 934763827ee..ca650117968 100644 --- a/arch/arm/src/imx/imx_spi.c +++ b/arch/arm/src/imx/imx_spi.c @@ -139,7 +139,7 @@ struct imx_spidev_s * Private Function Prototypes ****************************************************************************/ - /* SPI register access */ +/* SPI register access */ static inline uint32_t spi_getreg(struct imx_spidev_s *priv, unsigned int offset); static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32_t value); @@ -468,11 +468,11 @@ static void spi_startxfr(struct imx_spidev_s *priv, int ntxd) */ if (ntxd > 0) - { + { regval = spi_getreg(priv, CSPI_CTRL_OFFSET); regval |= CSPI_CTRL_XCH; spi_putreg(priv, CSPI_CTRL_OFFSET, regval); - } + } } /**************************************************************************** @@ -773,7 +773,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) freqbits = CSPI_CTRL_DIV256; actual = IMX_PERCLK2_FREQ / 256; } - else /*if (frequency >= IMX_PERCLK2_FREQ / 512) */ + else /* if (frequency >= IMX_PERCLK2_FREQ / 512) */ { freqbits = CSPI_CTRL_DIV512; actual = IMX_PERCLK2_FREQ / 512; diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index 57c877213a0..80636a35f12 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -394,7 +394,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv) txdesc->length = kinesis_swap16(priv->dev.d_len); #ifdef CONFIG_ENET_ENHANCEDBD txdesc->bdu = 0x00000000; - txdesc->status2 = TXDESC_INT | TXDESC_TS; // | TXDESC_IINS | TXDESC_PINS; + txdesc->status2 = TXDESC_INT | TXDESC_TS; /* | TXDESC_IINS | TXDESC_PINS; */ #endif txdesc->status1 = (TXDESC_R | TXDESC_L | TXDESC_TC | TXDESC_W); @@ -480,7 +480,7 @@ static int kinetis_txpoll(struct net_driver_s *dev) if (kinetics_txringfull(priv)) { - return -EBUSY; + return -EBUSY; } } @@ -603,7 +603,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv) */ if (priv->dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index cded69a62a7..368a5ecc748 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -287,8 +287,8 @@ static int kinetis_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { - *regaddr = NVIC_SYSHCON; - if (irq == KINETIS_IRQ_MEMFAULT) + *regaddr = NVIC_SYSHCON; + if (irq == KINETIS_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c index a7b693ccca7..c01ceec5b9b 100644 --- a/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/arch/arm/src/kinetis/kinetis_lowputc.c @@ -169,7 +169,7 @@ void up_lowputc(char ch) while ((getreg8(CONSOLE_BASE+KINETIS_UART_S1_OFFSET) & UART_S1_TDRE) == 0); #endif - /* Then write the character to the UART data register */ + /* Then write the character to the UART data register */ putreg8((uint8_t)ch, CONSOLE_BASE+KINETIS_UART_D_OFFSET); #endif diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c index 6535ac3a20d..45b8136e5a1 100644 --- a/arch/arm/src/kinetis/kinetis_pinirq.c +++ b/arch/arm/src/kinetis/kinetis_pinirq.c @@ -128,7 +128,7 @@ static int kinetis_portinterrupt(int irq, FAR void *context, */ uint32_t bit = (1 << i); - if ((isfr & bit ) != 0) + if ((isfr & bit) != 0) { /* I think that bits may be set in the ISFR for DMA activities * well. So, no error is declared if there is no registered @@ -372,7 +372,7 @@ void kinetis_pinirqenable(uint32_t pinset) regval |= PORT_PCR_IRQC_ZERO; break; - case PIN_INT_RISING : /* Interrupt on rising edge*/ + case PIN_INT_RISING : /* Interrupt on rising edge */ regval |= PORT_PCR_IRQC_RISING; break; diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index bfda25be61b..93529f8e6b8 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -1047,7 +1047,7 @@ static void kinetis_endtransfer(struct kinetis_dev_s *priv, sdio_eventset_t wkup /* If this was a DMA transfer, make sure that DMA is stopped */ #ifdef CONFIG_SDIO_DMA - /* Stop the DMA by resetting the data path*/ + /* Stop the DMA by resetting the data path */ regval = getreg32(KINETIS_SDHC_SYSCTL); regval |= SDHC_SYSCTL_RSTD; @@ -1420,8 +1420,8 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency) * 96MHz / 16 <= 400KHz <= 96MHz / 16 / 16 -- YES, prescaler == 16 */ - if (/*frequency >= (BOARD_CORECLK_FREQ / 2) && */ - frequency <= (BOARD_CORECLK_FREQ / 2 / 16)) + if (/* frequency >= (BOARD_CORECLK_FREQ / 2) && */ + frequency <= (BOARD_CORECLK_FREQ / 2 / 16)) { sdclkfs = SDHC_SYSCTL_SDCLKFS_DIV2; prescaler = 2; @@ -1791,7 +1791,7 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar regval |= SDHC_XFERTYP_RSPTYP_NONE; break; - case MMCSD_R1B_RESPONSE: /* Response length 48, check busy & cmdindex*/ + case MMCSD_R1B_RESPONSE: /* Response length 48, check busy & cmdindex */ regval |= (SDHC_XFERTYP_RSPTYP_LEN48BSY|SDHC_XFERTYP_CICEN|SDHC_XFERTYP_CCCEN); break; @@ -2002,7 +2002,7 @@ static int kinetis_cancel(FAR struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ #ifdef CONFIG_SDIO_DMA - /* Stop the DMA by resetting the data path*/ + /* Stop the DMA by resetting the data path */ regval = getreg32(KINETIS_SDHC_SYSCTL); regval |= SDHC_SYSCTL_RSTD; @@ -2233,7 +2233,7 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r } } - /* Return the long response in CMDRSP3..0*/ + /* Return the long response in CMDRSP3..0 */ if (rlong) { @@ -2404,7 +2404,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev, if (!timeout) { - return SDIOWAIT_TIMEOUT; + return SDIOWAIT_TIMEOUT; } /* Start the watchdog timer */ diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 6bbf899e70f..ec0085a4e01 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -590,9 +590,9 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie) flags = irqsave(); if (ie) - { - *ie = priv->ie; - } + { + *ie = priv->ie; + } up_restoreuartint(priv, 0); irqrestore(flags); diff --git a/arch/arm/src/kinetis/kinetis_timerisr.c b/arch/arm/src/kinetis/kinetis_timerisr.c index c3818cb8e85..659da3e7cba 100644 --- a/arch/arm/src/kinetis/kinetis_timerisr.c +++ b/arch/arm/src/kinetis/kinetis_timerisr.c @@ -100,10 +100,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/kl/kl_clockconfig.c b/arch/arm/src/kl/kl_clockconfig.c index 700e87aa607..b414500f2cd 100644 --- a/arch/arm/src/kl/kl_clockconfig.c +++ b/arch/arm/src/kl/kl_clockconfig.c @@ -243,4 +243,3 @@ void kl_clockconfig(void) //kl_traceconfig(); //kl_fbconfig(); } - diff --git a/arch/arm/src/kl/kl_gpioirq.c b/arch/arm/src/kl/kl_gpioirq.c index 7d831a6f4be..8aed2624316 100644 --- a/arch/arm/src/kl/kl_gpioirq.c +++ b/arch/arm/src/kl/kl_gpioirq.c @@ -123,7 +123,7 @@ static int kl_portinterrupt(int irq, FAR void *context, */ uint32_t bit = (1 << i); - if ((isfr & bit ) != 0) + if ((isfr & bit) != 0) { /* I think that bits may be set in the ISFR for DMA activities * well. So, no error is declared if there is no registered @@ -322,7 +322,7 @@ void kl_gpioirqenable(uint32_t pinset) regval |= PORT_PCR_IRQC_ZERO; break; - case PIN_INT_RISING : /* Interrupt on rising edge*/ + case PIN_INT_RISING : /* Interrupt on rising edge */ regval |= PORT_PCR_IRQC_RISING; break; diff --git a/arch/arm/src/kl/kl_lowgetc.c b/arch/arm/src/kl/kl_lowgetc.c index d0714b67538..cd830093b96 100644 --- a/arch/arm/src/kl/kl_lowgetc.c +++ b/arch/arm/src/kl/kl_lowgetc.c @@ -120,7 +120,7 @@ int kl_lowgetc(void) while ((getreg8(CONSOLE_BASE+KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0); - /* Then read a character from the UART data register */ + /* Then read a character from the UART data register */ ch = getreg8(CONSOLE_BASE+KL_UART_D_OFFSET); #endif diff --git a/arch/arm/src/kl/kl_lowputc.c b/arch/arm/src/kl/kl_lowputc.c index 01288ef874f..4fbb884b9f3 100644 --- a/arch/arm/src/kl/kl_lowputc.c +++ b/arch/arm/src/kl/kl_lowputc.c @@ -136,7 +136,7 @@ void kl_lowputc(uint32_t ch) while ((getreg8(CONSOLE_BASE+KL_UART_S1_OFFSET) & UART_S1_TDRE) == 0); - /* Then write the character to the UART data register */ + /* Then write the character to the UART data register */ putreg8((uint8_t)ch, CONSOLE_BASE+KL_UART_D_OFFSET); diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index 5311daecc0f..04df0f470b3 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -376,9 +376,9 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie) flags = irqsave(); if (ie) - { - *ie = priv->ie; - } + { + *ie = priv->ie; + } up_restoreuartint(priv, 0); irqrestore(flags); @@ -595,10 +595,10 @@ static int up_interrupts(int irq, void *context) * OR: Receiver Overrun Flag. To clear OR, write a logic 1 to the OR flag. */ - if ((s1 & UART_S1_ERRORS) != 0) - { - up_serialout(priv, KL_UART_S1_OFFSET, (s1 & UART_S1_ERRORS)); - } + if ((s1 & UART_S1_ERRORS) != 0) + { + up_serialout(priv, KL_UART_S1_OFFSET, (s1 & UART_S1_ERRORS)); + } } return OK; diff --git a/arch/arm/src/kl/kl_timerisr.c b/arch/arm/src/kl/kl_timerisr.c index 005c3d17f33..bcd17b06485 100644 --- a/arch/arm/src/kl/kl_timerisr.c +++ b/arch/arm/src/kl/kl_timerisr.c @@ -115,10 +115,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/lpc11xx/lpc11_gpioint.c b/arch/arm/src/lpc11xx/lpc11_gpioint.c index b5b8fdc0679..71075d5275e 100644 --- a/arch/arm/src/lpc11xx/lpc11_gpioint.c +++ b/arch/arm/src/lpc11xx/lpc11_gpioint.c @@ -163,10 +163,10 @@ static void lpc11_setintedge(uint32_t intbase, unsigned int pin, static int lpc11_irq2port(int irq) { - /* Set 1: - * LPC176x: 12 interrupts p0.0-p0.11 - * LPC178x: 16 interrupts p0.0-p0.15 - */ + /* Set 1: + * LPC176x: 12 interrupts p0.0-p0.11 + * LPC178x: 16 interrupts p0.0-p0.15 + */ if (irq >= LPC17_VALID_FIRST0L && irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L)) @@ -364,24 +364,24 @@ static void lpc11_gpiodemux(uint32_t intbase, uint32_t intmask, if ((intmask & bit) != 0) { - /* This pin can support an interrupt. Is there an interrupt pending - * and enabled? - */ + /* This pin can support an interrupt. Is there an interrupt pending + * and enabled? + */ - if ((intstatus & bit) != 0) - { - /* Clear the interrupt status */ + if ((intstatus & bit) != 0) + { + /* Clear the interrupt status */ - putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET); + putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET); - /* And dispatch the interrupt */ + /* And dispatch the interrupt */ - irq_dispatch(irq, context); - } + irq_dispatch(irq, context); + } - /* Increment the IRQ number on each interrupt pin */ + /* Increment the IRQ number on each interrupt pin */ - irq++; + irq++; } /* Next bit */ diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c index 8af2c0b25aa..881a0d8ca39 100644 --- a/arch/arm/src/lpc11xx/lpc11_i2c.c +++ b/arch/arm/src/lpc11xx/lpc11_i2c.c @@ -198,7 +198,7 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev; DEBUGASSERT(dev != NULL); - DEBUGASSERT(nbits == 7 ); + DEBUGASSERT(nbits == 7); priv->msg.addr = addr << 1; priv->msg.flags = 0 ; @@ -378,7 +378,7 @@ static int i2c_interrupt(int irq, FAR void *context) switch (state) { - case 0x00: // Bus Error + case 0x00: /* Bus Error */ case 0x20: case 0x30: case 0x38: @@ -386,8 +386,8 @@ static int i2c_interrupt(int irq, FAR void *context) i2c_stop(priv); break; - case 0x08: // START - case 0x10: // Repeat START + case 0x08: /* START */ + case 0x10: /* Repeat START */ putreg32(priv->msg.addr, priv->base + LPC11_I2C_DAT_OFFSET); putreg32(I2C_CONCLR_STAC, priv->base + LPC11_I2C_CONCLR_OFFSET); break; diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c index 3a9809588c7..47d68aae080 100644 --- a/arch/arm/src/lpc11xx/lpc11_serial.c +++ b/arch/arm/src/lpc11xx/lpc11_serial.c @@ -313,7 +313,7 @@ static inline uint32_t lpc11_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 16 / MinDL */ - return 1; + return 1; } #endif /* LPC111x */ @@ -378,8 +378,8 @@ static inline void lpc11_uart0config(void) #ifdef LPC111x static inline uint32_t lpc11_uartdl(uint32_t baud, uint8_t divcode) { + /* TODO: Calculate DL automatically */ - /*TODO: Calculate DL automatically */ uint32_t num = 312; return num; diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c index 80a179c39c4..f65f8386ffe 100644 --- a/arch/arm/src/lpc11xx/lpc11_spi.c +++ b/arch/arm/src/lpc11xx/lpc11_spi.c @@ -483,7 +483,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, * the SPI data transfer. */ - while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); + while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); /* Read the SPI Status Register again to clear the status bit */ diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c index 2401529cb79..c9ab200682f 100644 --- a/arch/arm/src/lpc11xx/lpc11_timer.c +++ b/arch/arm/src/lpc11xx/lpc11_timer.c @@ -387,7 +387,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) flags = irqsave(); - /* Power on the timer peripherals*/ + /* Power on the timer peripherals */ regval = getreg32(LPC17_SYSCON_PCONP); regval |= SYSCON_PCONP_PCTIM0; @@ -396,7 +396,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) regval |= SYSCON_PCONP_PCTIM3; putreg32(regval, LPC17_SYSCON_PCONP); - /* Select clock for the timer peripheral*/ + /* Select clock for the timer peripheral */ regval = getreg32(LPC17_SYSCON_PCLKSEL0); regval &= ~(0x3 << 2); @@ -424,7 +424,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) */ putreg32(((1 << 1)|(3 << 6)), LPC17_TMR0_EMR); - putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0*/ + putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */ /* Configure the output pins GPIO3.26 */ @@ -436,8 +436,8 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */ putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */ -// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0*/ - putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1*/ +// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */ + putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */ /* configure the output pins GPIO3.26 */ // lpc11_configgpio(GPIO_MAT0p1_2); diff --git a/arch/arm/src/lpc11xx/lpc11_timerisr.c b/arch/arm/src/lpc11xx/lpc11_timerisr.c index 8248052d19f..6bbd6e0878d 100644 --- a/arch/arm/src/lpc11xx/lpc11_timerisr.c +++ b/arch/arm/src/lpc11xx/lpc11_timerisr.c @@ -115,10 +115,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/lpc17xx/lpc176x_rtc.c b/arch/arm/src/lpc17xx/lpc176x_rtc.c index 7e471feb8b9..be288db0e49 100644 --- a/arch/arm/src/lpc17xx/lpc176x_rtc.c +++ b/arch/arm/src/lpc17xx/lpc176x_rtc.c @@ -291,7 +291,7 @@ int up_rtcinitialize(void) { up_enable_irq(LPC17_IRQ_RTC); } -#endif /*CONFIG_RTC_ALARM*/ +#endif /* CONFIG_RTC_ALARM */ /* Perform the one-time setup of the RTC */ diff --git a/arch/arm/src/lpc17xx/lpc17_adc.c b/arch/arm/src/lpc17xx/lpc17_adc.c index 2a4d6e4d1cd..0587e3085b4 100644 --- a/arch/arm/src/lpc17xx/lpc17_adc.c +++ b/arch/arm/src/lpc17xx/lpc17_adc.c @@ -174,7 +174,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) putreg32(0x100, LPC17_ADC_INTEN); /* Enable only global interrupt */ putreg32((priv->mask) | /* Select channels 0 to 7 on ADC0 */ -// (clkdiv) << 8) | /* CLKDIV = divisor to make the samples +// (clkdiv) << 8) | /* CLKDIV = divisor to make the samples // * per second conversion rate */ ((32) << 8) | /* CLKDIV = divisor to make the faster * conversion rate */ @@ -187,14 +187,14 @@ static void adc_reset(FAR struct adc_dev_s *dev) * trigger A/D conversion) */ LPC17_ADC_CR); -#else /*CONFIG_ADC_BURSTMODE*/ +#else /* CONFIG_ADC_BURSTMODE */ clkdiv = LPC17_CCLK / 8 / 65 / priv->sps; clkdiv <<= 8; clkdiv &= 0xff00; putreg32(ADC_CR_PDN | ADC_CR_BURST | clkdiv | priv->mask, LPC17_ADC_CR); -#endif /*CONFIG_ADC_BURSTMODE*/ +#endif /* CONFIG_ADC_BURSTMODE */ if ((priv->mask & 0x01) != 0) { @@ -322,11 +322,11 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) putreg32(ADC_INTEN_GLOBAL, LPC17_ADC_INTEN); #endif -#else /*CONFIG_ADC_BURSTMODE*/ +#else /* CONFIG_ADC_BURSTMODE */ /* Enable only global interrupt */ putreg32(0x100, LPC17_ADC_INTEN); -#endif /*CONFIG_ADC_BURSTMODE*/ +#endif /* CONFIG_ADC_BURSTMODE */ } else { @@ -416,7 +416,7 @@ static int adc_interrupt(int irq, void *context) return OK; #endif -#else /*CONFIG_ADC_BURSTMODE*/ +#else /* CONFIG_ADC_BURSTMODE */ FAR struct up_dev_s *priv = (FAR struct up_dev_s *)g_adcdev.ad_priv; volatile uint32_t regVal, regVal2, regVal3; @@ -462,21 +462,21 @@ static int adc_interrupt(int irq, void *context) ADC1Buffer0[0] = regVal; ADC0IntDone = 1; -#else /*CONFIG_ADC_DIRECT_ACCESS*/ +#else /* CONFIG_ADC_DIRECT_ACCESS */ #ifdef CONFIG_ADC_WORKER_THREAD /* Store the data value plus the status bits */ ADC1Buffer0[0] = regVal; ADC0IntDone = 1; -#else /*CONFIG_ADC_WORKER_THREAD*/ +#else /* CONFIG_ADC_WORKER_THREAD */ if ((regVal) & (1 << 31)) { adc_receive(&g_adcdev, 1, (regVal >> 4) & 0xFFF); } -#endif /*CONFIG_ADC_WORKER_THREAD*/ -#endif /*CONFIG_ADC_DIRECT_ACCESS*/ +#endif /* CONFIG_ADC_WORKER_THREAD */ +#endif /* CONFIG_ADC_DIRECT_ACCESS */ } if ((priv->mask & 0x04) != 0) @@ -489,21 +489,21 @@ static int adc_interrupt(int irq, void *context) ADC2Buffer0[0] = regVal; ADC0IntDone = 1; -#else /*CONFIG_ADC_DIRECT_ACCESS*/ +#else /* CONFIG_ADC_DIRECT_ACCESS */ #ifdef CONFIG_ADC_WORKER_THREAD /* Store the data value plus the status bits */ ADC2Buffer0[0] = regVal; ADC0IntDone = 1; -#else /*CONFIG_ADC_WORKER_THREAD*/ +#else /* CONFIG_ADC_WORKER_THREAD */ if ((regVal) & (1 << 31)) { adc_receive(&g_adcdev, 2, (regVal >> 4) & 0xFFF); } -#endif /*CONFIG_ADC_WORKER_THREAD*/ -#endif /*CONFIG_ADC_DIRECT_ACCESS*/ +#endif /* CONFIG_ADC_WORKER_THREAD */ +#endif /* CONFIG_ADC_DIRECT_ACCESS */ } if ((priv->mask & 0x08) != 0) @@ -558,7 +558,7 @@ static int adc_interrupt(int irq, void *context) (FAR void *)priv, 0); } -#endif /*CONFIG_ADC_WORKER_THREAD*/ +#endif /* CONFIG_ADC_WORKER_THREAD */ } regVal3 = getreg32(LPC17_ADC_GDR); /* Read ADGDR clear the DONE and OVERRUN bits */ @@ -575,7 +575,7 @@ static int adc_interrupt(int irq, void *context) //lpc17_gpiowrite(LPCXPRESSO_GPIO0_21, 0); /* Reset pin P0.21 */ //irqrestore(saved_state); return OK; -#endif /*CONFIG_ADC_BURSTMODE*/ +#endif /* CONFIG_ADC_BURSTMODE */ } /**************************************************************************** diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c index a4f357bdcb2..f1e8209deb4 100644 --- a/arch/arm/src/lpc17xx/lpc17_can.c +++ b/arch/arm/src/lpc17xx/lpc17_can.c @@ -322,10 +322,11 @@ static void can_printreg(uint32_t addr, uint32_t value) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return; } } diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index 9957c13e2c1..0e1e34253e1 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -1006,7 +1006,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv) */ if (priv->lp_dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -2681,16 +2681,16 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) for (phyaddr = 1; phyaddr < 32; phyaddr++) { - /* Check if we can see the selected device ID at this - * PHY address. - */ + /* Check if we can see the selected device ID at this + * PHY address. + */ - phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1); - nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg); + phyreg = (unsigned int)lpc17_phyread(phyaddr, MII_PHYID1); + nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg); - /* Compare OUI bits 3-18 */ + /* Compare OUI bits 3-18 */ - if (phyreg == LPC17_PHYID1) + if (phyreg == LPC17_PHYID1) { phyreg = lpc17_phyread(phyaddr, MII_PHYID2); nvdbg("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg); diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c index 530f9bd0490..a8c77281b05 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c @@ -481,13 +481,13 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config, * has the highest priority and DMA channel 7 the lowest priority. */ - regval = getreg32(LPC17_DMA_ENBLDCHNS); - if ((regval & chbit) != 0) - { - /* There is an active DMA on this channel! */ + regval = getreg32(LPC17_DMA_ENBLDCHNS); + if ((regval & chbit) != 0) + { + /* There is an active DMA on this channel! */ - return -EBUSY; - } + return -EBUSY; + } /* 2. "Clear any pending interrupts on the channel to be used by writing * to the DMACIntTCClear and DMACIntErrClear register. The previous diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c index 8d55944a243..fc566876cfb 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -196,7 +196,7 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; DEBUGASSERT(dev != NULL); - DEBUGASSERT(nbits == 7 ); + DEBUGASSERT(nbits == 7); priv->msg.addr = addr << 1; priv->msg.flags = 0 ; @@ -375,7 +375,7 @@ static int i2c_interrupt(int irq, FAR void *context) switch (state) { - case 0x00: // Bus Error + case 0x00: /* Bus Error */ case 0x20: case 0x30: case 0x38: @@ -383,8 +383,8 @@ static int i2c_interrupt(int irq, FAR void *context) i2c_stop(priv); break; - case 0x08: // START - case 0x10: // Repeat START + case 0x08: /* START */ + case 0x10: /* Repeat START */ putreg32(priv->msg.addr, priv->base + LPC17_I2C_DAT_OFFSET); putreg32(I2C_CONCLR_STAC, priv->base + LPC17_I2C_CONCLR_OFFSET); break; diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c index 7a6005c71fb..fcf816f802b 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx/lpc17_irq.c @@ -255,8 +255,8 @@ static int lpc17_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { - *regaddr = NVIC_SYSHCON; - if (irq == LPC17_IRQ_MEMFAULT) + *regaddr = NVIC_SYSHCON; + if (irq == LPC17_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c index 13876a15565..7afe8610797 100644 --- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c +++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c @@ -395,7 +395,7 @@ static void mcpwm_set_apb_clock(FAR struct lpc17_mcpwmtimer_s *priv, bool on) modifyreg32(regaddr, en_bit, 0); } } -#endif /*XXXXX*/ +#endif /**************************************************************************** * Name: mcpwm_setup @@ -452,7 +452,7 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev) putreg32((0xFFFFFFFF), LPC17_MCPWM_CAPCLR);/* Clear all event capture */ - /* Configure the output pins*/ + /* Configure the output pins */ lpc17_configgpio(GPIO_MCPWM_MCOA0); lpc17_configgpio(GPIO_MCPWM_MCOB0); @@ -469,7 +469,7 @@ static int mcpwm_setup(FAR struct pwm_lowerhalf_s *dev) putreg32(400, LPC17_MCPWM_LIM0); /* Set the starting duty cycle to 0.25 */ putreg32(0, LPC17_MCPWM_MAT0); /* Reset the timer */ - putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz*/ + putreg32(100000, LPC17_MCPWM_TC1); /* Count frequency:Fpclk/100000 = 50 MHz/100000 = 500 Hz */ putreg32(50000, LPC17_MCPWM_LIM1); /* Set the starting duty cycle to 0.5 */ putreg32(0, LPC17_MCPWM_MAT1); /* Reset the timer */ diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c index d983b71a5d2..273f3ed3133 100644 --- a/arch/arm/src/lpc17xx/lpc17_pwm.c +++ b/arch/arm/src/lpc17xx/lpc17_pwm.c @@ -413,7 +413,7 @@ static void pwm_set_apb_clock(FAR struct lpc17_pwmtimer_s *priv, bool on) modifyreg32(regaddr, en_bit, 0); } } -#endif /*XXXXX*/ +#endif /**************************************************************************** * Name: pwm_setup diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c index 1e61d471c47..b020d901b80 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.c +++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c @@ -860,10 +860,11 @@ static uint8_t lpc17_log2(uint16_t value) DEBUGASSERT(value > 0); while (value != 1) - { - value >>= 1; - log2++; - } + { + value >>= 1; + log2++; + } + return log2; } @@ -959,27 +960,27 @@ static void lpc17_sendfifo(struct lpc17_dev_s *priv) } else { - /* No.. transfer just the bytes remaining in the user buffer, - * padding with zero as necessary to extend to a full word. - */ + /* No.. transfer just the bytes remaining in the user buffer, + * padding with zero as necessary to extend to a full word. + */ - uint8_t *ptr = (uint8_t *)priv->remaining; - int i; + uint8_t *ptr = (uint8_t *)priv->remaining; + int i; - data.w = 0; - for (i = 0; i < priv->remaining; i++) - { - data.b[i] = *ptr++; - } + data.w = 0; + for (i = 0; i < priv->remaining; i++) + { + data.b[i] = *ptr++; + } - /* Now the transfer is finished */ + /* Now the transfer is finished */ - priv->remaining = 0; - } + priv->remaining = 0; + } - /* Put the word in the FIFO */ + /* Put the word in the FIFO */ - putreg32(data.w, LPC17_SDCARD_FIFO); + putreg32(data.w, LPC17_SDCARD_FIFO); } } diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c index 55d85849c15..4ffa10cc976 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/arch/arm/src/lpc17xx/lpc17_serial.c @@ -478,7 +478,7 @@ static uart_dev_t g_uart3port = # undef TTYS3_DEV /* No ttyS3 */ # endif # endif -#endif /*HAVE_CONSOLE*/ +#endif /* HAVE_CONSOLE */ /************************************************************************************ * Inline Functions @@ -609,7 +609,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 16 / MinDL */ - if (baud < (LPC17_CCLK / 16 / UART_MINDL )) + if (baud < (LPC17_CCLK / 16 / UART_MINDL)) { return SYSCON_PCLKSEL_CCLK; } @@ -625,7 +625,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 8 / MinDL */ - else if (baud < (LPC17_CCLK / 8 / UART_MINDL )) + else if (baud < (LPC17_CCLK / 8 / UART_MINDL)) { return SYSCON_PCLKSEL_CCLK2; } @@ -641,7 +641,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 4 / MinDL */ - else if (baud < (LPC17_CCLK / 4 / UART_MINDL )) + else if (baud < (LPC17_CCLK / 4 / UART_MINDL)) { return SYSCON_PCLKSEL_CCLK4; } @@ -657,7 +657,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud) * BAUD <= CCLK / 2 / MinDL */ - else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL )) */ + else /* if (baud < (LPC17_CCLK / 2 / UART_MINDL)) */ { return SYSCON_PCLKSEL_CCLK8; } @@ -1256,7 +1256,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * and reset the divider in the CLKSEL0/1 register. */ -#if 0 // ifdef LPC176x +#if 0 /* ifdef LPC176x */ priv->cclkdiv = lpc17_uartcclkdiv(priv->baud); #endif /* DLAB open latch */ diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx/lpc17_spi.c index bbdd568c39c..58fbb7de9bb 100644 --- a/arch/arm/src/lpc17xx/lpc17_spi.c +++ b/arch/arm/src/lpc17xx/lpc17_spi.c @@ -474,12 +474,12 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size * data transfer. */ - while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0); + while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0); - /* Read the SPI Status Register again to clear the status bit */ + /* Read the SPI Status Register again to clear the status bit */ - (void)getreg32(LPC17_SPI_SR); - nwords--; + (void)getreg32(LPC17_SPI_SR); + nwords--; } } diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx/lpc17_timer.c index 747137fb365..bc177f16857 100644 --- a/arch/arm/src/lpc17xx/lpc17_timer.c +++ b/arch/arm/src/lpc17xx/lpc17_timer.c @@ -387,7 +387,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) flags = irqsave(); - /* Power on the timer peripherals*/ + /* Power on the timer peripherals */ regval = getreg32(LPC17_SYSCON_PCONP); regval |= SYSCON_PCONP_PCTIM0; @@ -396,7 +396,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) regval |= SYSCON_PCONP_PCTIM3; putreg32(regval, LPC17_SYSCON_PCONP); - /* Select clock for the timer peripheral*/ + /* Select clock for the timer peripheral */ regval = getreg32(LPC17_SYSCON_PCLKSEL0); regval &= ~(0x3 << 2); @@ -424,7 +424,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) */ putreg32(((1 << 1)|(3 << 6)), LPC17_TMR0_EMR); - putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0*/ + putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */ /* Configure the output pins GPIO3.26 */ @@ -436,8 +436,8 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev) putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */ putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */ -// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0*/ - putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1*/ +// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */ + putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */ /* configure the output pins GPIO3.26 */ // lpc17_configgpio(GPIO_MAT0p1_2); diff --git a/arch/arm/src/lpc17xx/lpc17_timerisr.c b/arch/arm/src/lpc17xx/lpc17_timerisr.c index 1b4a6a3794c..f61cf58073b 100644 --- a/arch/arm/src/lpc17xx/lpc17_timerisr.c +++ b/arch/arm/src/lpc17xx/lpc17_timerisr.c @@ -101,10 +101,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/lpc214x/lpc214x_timerisr.c b/arch/arm/src/lpc214x/lpc214x_timerisr.c index ecb280f24f2..24defd5a52d 100644 --- a/arch/arm/src/lpc214x/lpc214x_timerisr.c +++ b/arch/arm/src/lpc214x/lpc214x_timerisr.c @@ -98,20 +98,20 @@ int up_timerisr(uint32_t *regs) int up_timerisr(int irq, uint32_t *regs) #endif { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); + sched_process_timer(); - /* Clear the MR0 match interrupt */ + /* Clear the MR0 match interrupt */ - tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET); + tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET); - /* Reset the VIC as well */ + /* Reset the VIC as well */ #ifdef CONFIG_VECTORED_INTERRUPTS - vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET); + vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET); #endif - return 0; + return 0; } /**************************************************************************** diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c index e9eef2cc9be..6320ac9ec14 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -537,10 +537,11 @@ static uint32_t lpc214x_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return val; } } diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index af014e2da8c..35567fdd522 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -311,9 +311,9 @@ static int i2c_start (struct lpc23xx_i2cdev_s *priv) static void i2c_stop (struct lpc23xx_i2cdev_s *priv) { if (priv->state != 0x38) - { - putreg32(I2C_CONSET_STO | I2C_CONSET_AA, priv->base + I2C_CONSET_OFFSET); - } + { + putreg32(I2C_CONSET_STO | I2C_CONSET_AA, priv->base + I2C_CONSET_OFFSET); + } sem_post (&priv->wait); } diff --git a/arch/arm/src/lpc2378/lpc23xx_timerisr.c b/arch/arm/src/lpc2378/lpc23xx_timerisr.c index e831b34459a..55a29b25e26 100644 --- a/arch/arm/src/lpc2378/lpc23xx_timerisr.c +++ b/arch/arm/src/lpc2378/lpc23xx_timerisr.c @@ -78,7 +78,7 @@ #define T0_PCLKSEL_MASK (0x0000000C) -#define T0_TICKS_COUNT ((CCLK / T0_PCLK_DIV ) / TICK_PER_SEC) +#define T0_TICKS_COUNT ((CCLK / T0_PCLK_DIV) / TICK_PER_SEC) /**************************************************************************** * Private Types diff --git a/arch/arm/src/lpc31xx/lpc31_clkfreq.c b/arch/arm/src/lpc31xx/lpc31_clkfreq.c index aba8384bce9..1151f42df5d 100644 --- a/arch/arm/src/lpc31xx/lpc31_clkfreq.c +++ b/arch/arm/src/lpc31xx/lpc31_clkfreq.c @@ -167,11 +167,10 @@ uint32_t lpc31_clkfreq(enum lpc31_clockid_e clkid, return 0; } - /* Finally, calculate the frequency based on m and n values */ + /* Finally, calculate the frequency based on m and n values */ - freq = (freq * n) / m ; - } + freq = (freq * n) / m ; + } return freq; } - diff --git a/arch/arm/src/lpc31xx/lpc31_clkinit.c b/arch/arm/src/lpc31xx/lpc31_clkinit.c index 0f2c1141fd5..f0cdd44103f 100644 --- a/arch/arm/src/lpc31xx/lpc31_clkinit.c +++ b/arch/arm/src/lpc31xx/lpc31_clkinit.c @@ -138,8 +138,8 @@ static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn) regaddr = LPC31_CGU_ESR(esrndx); putreg32((fdndx << CGU_ESR_ESRSEL_SHIFT) | CGU_ESR_ESREN, regaddr); } - } - } + } + } /* Enable the fractional divider */ @@ -158,7 +158,7 @@ static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn) putreg32(CGU_BCR_FDRUN, regaddr); } - /* Select input base clock for domain*/ + /* Select input base clock for domain */ lpc31_selectfreqin(dmn->dmnid, dmn->finsel); } diff --git a/arch/arm/src/lpc31xx/lpc31_fdcndx.c b/arch/arm/src/lpc31xx/lpc31_fdcndx.c index 6297d65fb25..0bc9c3a5560 100644 --- a/arch/arm/src/lpc31xx/lpc31_fdcndx.c +++ b/arch/arm/src/lpc31xx/lpc31_fdcndx.c @@ -106,22 +106,22 @@ int lpc31_fdcndx(enum lpc31_clockid_e clkid, enum lpc31_domainid_e dmnid) esrndx = lpc31_esrndx(clkid); if (esrndx != ESRNDX_INVALID) - { - /* Read the clock's ESR to get the fractional divider */ - - uint32_t regval = getreg32(LPC31_CGU_ESR(esrndx)); - - /* Check if any fractional divider is enabled for this clock. */ - - if ((regval & CGU_ESR_ESREN) != 0) { - /* Yes.. The FDC index is an offset from this fractional - * divider base for this domain. - */ + /* Read the clock's ESR to get the fractional divider */ - fdcndx = CGU_ESRSEL(regval) + (int)g_fdcbase[dmnid]; + uint32_t regval = getreg32(LPC31_CGU_ESR(esrndx)); + + /* Check if any fractional divider is enabled for this clock. */ + + if ((regval & CGU_ESR_ESREN) != 0) + { + /* Yes.. The FDC index is an offset from this fractional + * divider base for this domain. + */ + + fdcndx = CGU_ESRSEL(regval) + (int)g_fdcbase[dmnid]; + } } - } + return fdcndx; } - diff --git a/arch/arm/src/lpc31xx/lpc31_irq.c b/arch/arm/src/lpc31xx/lpc31_irq.c index 86796d4fb9f..05108d78bb2 100644 --- a/arch/arm/src/lpc31xx/lpc31_irq.c +++ b/arch/arm/src/lpc31xx/lpc31_irq.c @@ -102,7 +102,7 @@ void up_irqinitialize(void) putreg32(0, LPC31_INTC_PRIORITYMASK0); /* Proc interrupt request 0: IRQ */ putreg32(0, LPC31_INTC_PRIORITYMASK1); /* Proc interrupt request 1: FIQ */ - /* Disable all interrupts. Start from index 1 since 0 is unused.*/ + /* Disable all interrupts. Start from index 1 since 0 is unused. */ for (irq = 0; irq < NR_IRQS; irq++) { diff --git a/arch/arm/src/lpc31xx/lpc31_resetclks.c b/arch/arm/src/lpc31xx/lpc31_resetclks.c index fe32879409f..4631f147489 100644 --- a/arch/arm/src/lpc31xx/lpc31_resetclks.c +++ b/arch/arm/src/lpc31xx/lpc31_resetclks.c @@ -103,42 +103,43 @@ void lpc31_resetclks(void) /* Disable all clocks except those that are necessary */ for (i = CLKID_FIRST; i <= CLKID_LAST; i++) - { - /* Check if this clock has an ESR register */ - - esrndx = lpc31_esrndx((enum lpc31_clockid_e)i); - if (esrndx != ESRNDX_INVALID) { - /* Yes.. Clear the clocks ESR to deselect fractional divider */ + /* Check if this clock has an ESR register */ - putreg32(0, LPC31_CGU_ESR(esrndx)); + esrndx = lpc31_esrndx((enum lpc31_clockid_e)i); + if (esrndx != ESRNDX_INVALID) + { + /* Yes.. Clear the clocks ESR to deselect fractional divider */ + + putreg32(0, LPC31_CGU_ESR(esrndx)); + } + + /* Enable external enabling for all possible clocks to conserve power */ + + lpc31_enableexten((enum lpc31_clockid_e)i); + + /* Set enable-out's for only the following clocks */ + + regaddr = LPC31_CGU_PCR(i); + regval = getreg32(regaddr); + if (i == (int)CLKID_ARM926BUSIFCLK || i == (int)CLKID_MPMCCFGCLK) + { + regval |= CGU_PCR_ENOUTEN; + } + else + { + regval &= ~CGU_PCR_ENOUTEN; + } + + putreg32(regval, regaddr); + + /* Set/clear the RUN bit in the PCR regiser of all clocks, depending + * upon if the clock is needed by the board logic or not + */ + + (void)lpc31_defclk((enum lpc31_clockid_e)i); } - /* Enable external enabling for all possible clocks to conserve power */ - - lpc31_enableexten((enum lpc31_clockid_e)i); - - /* Set enable-out's for only the following clocks */ - - regaddr = LPC31_CGU_PCR(i); - regval = getreg32(regaddr); - if (i == (int)CLKID_ARM926BUSIFCLK || i == (int)CLKID_MPMCCFGCLK) - { - regval |= CGU_PCR_ENOUTEN; - } - else - { - regval &= ~CGU_PCR_ENOUTEN; - } - putreg32(regval, regaddr); - - /* Set/clear the RUN bit in the PCR regiser of all clocks, depending - * upon if the clock is needed by the board logic or not - */ - - (void)lpc31_defclk((enum lpc31_clockid_e)i); - } - /* Disable all fractional dividers */ for (i = 0; i < CGU_NFRACDIV; i++) diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c index 5d0524f718c..cf282088f71 100644 --- a/arch/arm/src/lpc31xx/lpc31_spi.c +++ b/arch/arm/src/lpc31xx/lpc31_spi.c @@ -504,8 +504,7 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel return; } - /* - * Since we don't use sequential multi-slave mode, but rather + /* Since we don't use sequential multi-slave mode, but rather * perform the transfer piecemeal by consecutive calls to * SPI_SEND, then we must manually assert the chip select * across the whole transfer @@ -555,7 +554,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) uint32_t spi_clk, div, div1, div2; if (priv->frequency != frequency) - { + { /* The SPI clock is derived from the (main system oscillator / 2), * so compute the best divider from that clock */ @@ -580,8 +579,8 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) priv->slv1 = (priv->slv1 & ~(SPI_SLV_1_CLKDIV2_MASK | SPI_SLV_1_CLKDIV1_MASK)) | (div2 << SPI_SLV_1_CLKDIV2_SHIFT) | (div1 << SPI_SLV_1_CLKDIV1_SHIFT); priv->frequency = frequency; - priv->actual = frequency; // FIXME - } + priv->actual = frequency; /* FIXME */ + } return priv->actual; } @@ -689,10 +688,10 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) { - /* FIXME: is there anyway to determine this - * it should probably be board dependant anyway */ + /* FIXME: is there anyway to determine this + * it should probably be board dependant anyway */ - return SPI_STATUS_PRESENT; + return SPI_STATUS_PRESENT; } /************************************************************************************ diff --git a/arch/arm/src/lpc31xx/lpc31_timerisr.c b/arch/arm/src/lpc31xx/lpc31_timerisr.c index e9a6bc2715d..a6ec4186051 100644 --- a/arch/arm/src/lpc31xx/lpc31_timerisr.c +++ b/arch/arm/src/lpc31xx/lpc31_timerisr.c @@ -125,13 +125,13 @@ void up_timer_initialize(void) regval = getreg32(LPC31_TIMER0_CTRL); if (freq > 1000000) - { - /* Use the divide by 16 pre-divider */ + { + /* Use the divide by 16 pre-divider */ - regval &= ~TIMER_CTRL_PRESCALE_MASK; - regval |= TIMER_CTRL_PRESCALE_DIV16; - freq >>= 4; - } + regval &= ~TIMER_CTRL_PRESCALE_MASK; + regval |= TIMER_CTRL_PRESCALE_DIV16; + freq >>= 4; + } load =((freq * (uint64_t)10000) / 1000000); putreg32((uint32_t)load, LPC31_TIMER0_LOAD); @@ -145,7 +145,7 @@ void up_timer_initialize(void) (void)irq_attach(LPC31_IRQ_TMR0, (xcpt_t)up_timerisr); - /* Clear any latched timer interrupt (Writing any value to the CLEAR register + /* Clear any latched timer interrupt (Writing any value to the CLEAR register * clears the latched interrupt generated by the counter timer) */ diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c index a2e43861693..6c2c110d01f 100644 --- a/arch/arm/src/lpc31xx/lpc31_usbdev.c +++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c @@ -167,7 +167,10 @@ /* Hardware interface **********************************************************/ -/* This represents a Endpoint Transfer Descriptor - note these must be 32 byte aligned */ +/* This represents a Endpoint Transfer Descriptor - note these must be 32 byte + * aligned + */ + struct lpc31_dtd_s { volatile uint32_t nextdesc; /* Address of the next DMA descripto in RAM */ @@ -180,7 +183,8 @@ struct lpc31_dtd_s uint32_t xfer_len; /* Software only - transfer len that was queued */ }; -/* DTD nextdesc field*/ +/* DTD nextdesc field */ + #define DTD_NEXTDESC_INVALID (1 << 0) /* Bit 0 : Next Descriptor Invalid */ /* DTD config field */ @@ -495,10 +499,11 @@ static uint32_t lpc31_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return val; } } @@ -718,26 +723,34 @@ static inline void lpc31_ep0xfer(uint8_t epphy, uint8_t *buf, uint32_t nbytes) * Read a Setup packet from the DTD. * ****************************************************************************/ + static void lpc31_readsetup(uint8_t epphy, struct usb_ctrlreq_s *ctrl) { - struct lpc31_dqh_s *dqh = &g_qh[epphy]; - int i; + struct lpc31_dqh_s *dqh = &g_qh[epphy]; + int i; - do { - /* Set the trip wire */ - lpc31_setbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD); + do + { + /* Set the trip wire */ - /* copy the request... */ - for (i = 0; i < 8; i++) - ((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i]; + lpc31_setbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD); - } while (!(lpc31_getreg(LPC31_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW)); + /* copy the request... */ - /* Clear the trip wire */ - lpc31_clrbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD); + for (i = 0; i < 8; i++) + { + ((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i]; + } + } + while (!(lpc31_getreg(LPC31_USBDEV_USBCMD) & USBDEV_USBCMD_SUTW)); - /* Clear the Setup Interrupt */ - lpc31_putreg (LPC31_ENDPTMASK(LPC31_EP0_OUT), LPC31_USBDEV_ENDPTSETUPSTAT); + /* Clear the trip wire */ + + lpc31_clrbits(USBDEV_USBCMD_SUTW, LPC31_USBDEV_USBCMD); + + /* Clear the Setup Interrupt */ + + lpc31_putreg (LPC31_ENDPTMASK(LPC31_EP0_OUT), LPC31_USBDEV_ENDPTSETUPSTAT); } /**************************************************************************** @@ -909,12 +922,16 @@ static void lpc31_reqcomplete(struct lpc31_ep_s *privep, static void lpc31_cancelrequests(struct lpc31_ep_s *privep, int16_t status) { if (!lpc31_rqempty(privep)) + { lpc31_flushep(privep); + } while (!lpc31_rqempty(privep)) { - // FIXME: the entry at the head should be sync'd with the DTD - // FIXME: only report the error status if the transfer hasn't completed + /* FIXME: the entry at the head should be sync'd with the DTD + * FIXME: only report the error status if the transfer hasn't completed + */ + usbtrace(TRACE_COMPLETE(privep->epphy), (lpc31_rqpeek(privep))->req.xfrd); lpc31_reqcomplete(privep, lpc31_rqdequeue(privep), status); @@ -2193,7 +2210,7 @@ static int lpc31_epstall(FAR struct usbdev_ep_s *ep, bool resume) ****************************************************************************/ static FAR struct usbdev_ep_s *lpc31_allocep(FAR struct usbdev_s *dev, uint8_t eplog, - bool in, uint8_t eptype) + bool in, uint8_t eptype) { FAR struct lpc31_usbdev_s *priv = (FAR struct lpc31_usbdev_s *)dev; uint32_t epset = LPC31_EPALLSET & ~LPC31_EPCTRLSET; diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index d20ad7380c0..18310a27011 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -700,10 +700,11 @@ static uint32_t lpc43_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return val; } } diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c index 52111024900..040f1744cbd 100644 --- a/arch/arm/src/lpc43xx/lpc43_i2c.c +++ b/arch/arm/src/lpc43xx/lpc43_i2c.c @@ -373,7 +373,7 @@ void startStopNextMessage(struct lpc43_i2cdev_s *priv) { priv->nmsg--; - if(priv->nmsg > 0) + if (priv->nmsg > 0) { priv->msgs++; putreg32(I2C_CONSET_STA,priv->base+LPC43_I2C_CONSET_OFFSET); @@ -442,22 +442,28 @@ static int i2c_interrupt(int irq, FAR void *context) case 0x28: /* Data byte in DAT has been transmitted; ACK has been received. */ priv->wrcnt++; - if (priv->wrcnt < msg->length) { + if (priv->wrcnt < msg->length) + { putreg32(msg->buffer[priv->wrcnt],priv->base+LPC43_I2C_DAT_OFFSET); /* Put next byte */ - } else { + } + else + { startStopNextMessage(priv); - } + } break; /* Read cases */ case 0x40: /* SLA+R has been transmitted; ACK has been received */ priv->rdcnt = 0; - if (msg->length > 1) { + if (msg->length > 1) + { putreg32(I2C_CONSET_AA, priv->base + LPC43_I2C_CONSET_OFFSET); /* Set ACK next read */ - } else { + } + else + { putreg32(I2C_CONCLR_AAC,priv->base + LPC43_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */ - } + } break; case 0x50: /* Data byte has been received; ACK has been returned. */ @@ -567,12 +573,11 @@ struct i2c_dev_s *up_i2cinitialize(int port) lpc43_pin_config(PINCONF_I2C1_SDA); i2c_setfrequency(priv, I2C1_DEFAULT_FREQUENCY); - } else #endif { - return NULL; + return NULL; } irqrestore(flags); diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index ee82f24fb3a..a5961a7d56d 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -264,8 +264,8 @@ static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { - *regaddr = NVIC_SYSHCON; - if (irq == LPC43_IRQ_MEMFAULT) + *regaddr = NVIC_SYSHCON; + if (irq == LPC43_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } diff --git a/arch/arm/src/lpc43xx/lpc43_pinconfig.c b/arch/arm/src/lpc43xx/lpc43_pinconfig.c index 77b979607f1..bde44b3f3c1 100644 --- a/arch/arm/src/lpc43xx/lpc43_pinconfig.c +++ b/arch/arm/src/lpc43xx/lpc43_pinconfig.c @@ -103,9 +103,9 @@ int lpc43_pin_config(uint32_t pinconf) /* Enable/disable input buffering */ if (PINCONF_INBUFFER_ENABLED(pinconf)) - { - regval |= SCU_PIN_EZI; /* Set bit to enable */ - } + { + regval |= SCU_PIN_EZI; /* Set bit to enable */ + } /* Enable/disable glitch filtering */ diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c index 380de90a1e6..eb051c10465 100644 --- a/arch/arm/src/lpc43xx/lpc43_rit.c +++ b/arch/arm/src/lpc43xx/lpc43_rit.c @@ -195,7 +195,7 @@ void up_timer_initialize(void) * complicated. When I have a better idea, I'll change this. */ - while(!((mask_test >> mask_bits) & ticks_per_int)) mask_bits++; + while (!((mask_test >> mask_bits) & ticks_per_int)) mask_bits++; lldbg("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n", mask_bits, (0xFFFFFFFF<<(32 - mask_bits)), ticks_per_int); diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 7aa4295d621..d4d84a4acd9 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -480,7 +480,7 @@ static uart_dev_t g_uart3port = # undef TTYS3_DEV /* No ttyS3 */ # endif # endif -#endif /*HAVE_CONSOLE*/ +#endif /* HAVE_CONSOLE */ /**************************************************************************** * Inline Functions @@ -984,15 +984,15 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv, } else { - tmp = ((priv->baud << 4) * mode->delay_rts_after_send) / 1000; - if (tmp > 255) - { - regval = 255; - } - else - { - regval = (uint32_t)tmp; - } + tmp = ((priv->baud << 4) * mode->delay_rts_after_send) / 1000; + if (tmp > 255) + { + regval = 255; + } + else + { + regval = (uint32_t)tmp; + } } diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c index 5974e9102cb..fe71636cfe4 100644 --- a/arch/arm/src/lpc43xx/lpc43_spi.c +++ b/arch/arm/src/lpc43xx/lpc43_spi.c @@ -463,12 +463,12 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size * data transfer. */ - while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0); + while ((getreg32(LPC43_SPI_SR) & SPI_SR_SPIF) == 0); - /* Read the SPI Status Register again to clear the status bit */ + /* Read the SPI Status Register again to clear the status bit */ - (void)getreg32(LPC43_SPI_SR); - nwords--; + (void)getreg32(LPC43_SPI_SR); + nwords--; } } diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.c b/arch/arm/src/lpc43xx/lpc43_spifi.c index 97294c13772..69ce27f26b6 100644 --- a/arch/arm/src/lpc43xx/lpc43_spifi.c +++ b/arch/arm/src/lpc43xx/lpc43_spifi.c @@ -1182,10 +1182,10 @@ FAR struct mtd_dev_s *lpc43_spifi_initialize(void) /* Initialize the SPIFI ROM driver */ ret = lpc43_rominit(priv); - if (ret != OK) - { - return NULL; - } + if (ret != OK) + { + return NULL; + } /* Check if we need to emulator a 512 byte sector */ diff --git a/arch/arm/src/lpc43xx/lpc43_start.c b/arch/arm/src/lpc43xx/lpc43_start.c index 092271e1850..0f3163881ef 100644 --- a/arch/arm/src/lpc43xx/lpc43_start.c +++ b/arch/arm/src/lpc43xx/lpc43_start.c @@ -33,8 +33,7 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ -/* - * Power-Up Reset Overview +/* Power-Up Reset Overview * ----------------------- * * The ARM core starts executing code on reset with the program counter set @@ -81,7 +80,7 @@ * Pre-processor Definitions ****************************************************************************/ - /**************************************************************************** +/**************************************************************************** * Name: showprogress * * Description: diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index 45371bb6a16..90344a4898d 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -514,10 +514,11 @@ static uint32_t lpc43_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return val; } } @@ -956,8 +957,10 @@ static void lpc43_cancelrequests(struct lpc43_ep_s *privep, int16_t status) while (!lpc43_rqempty(privep)) { - // FIXME: the entry at the head should be sync'd with the DTD - // FIXME: only report the error status if the transfer hasn't completed + /* FIXME: the entry at the head should be sync'd with the DTD + * FIXME: only report the error status if the transfer hasn't completed + */ + usbtrace(TRACE_COMPLETE(privep->epphy), (lpc43_rqpeek(privep))->req.xfrd); lpc43_reqcomplete(privep, lpc43_rqdequeue(privep), status); @@ -2646,7 +2649,6 @@ void up_usbinitialize(void) } } - /* Clock */ regval = getreg32(LPC43_BASE_USB0_CLK); @@ -2660,7 +2662,7 @@ void up_usbinitialize(void) regval |= CCU_CLK_CFG_RUN; putreg32(regval, LPC43_CCU1_M4_USB0_CFG); - /* Enable PLL0 clock*/ + /* Enable PLL0 clock */ lpc43_pll0usbconfig(); lpc43_pll0usbenable(); diff --git a/arch/arm/src/moxart/moxart_16550.c b/arch/arm/src/moxart/moxart_16550.c index ce24cf7312b..d2008f945cb 100644 --- a/arch/arm/src/moxart/moxart_16550.c +++ b/arch/arm/src/moxart/moxart_16550.c @@ -83,9 +83,11 @@ void uart_decodeirq(int irq, FAR void *context) i = 0; do { - if (!(status & 0x1)) { - irq_dispatch(VIRQ_START + i, context); - } + if (!(status & 0x1)) + { + irq_dispatch(VIRQ_START + i, context); + } + status >>= 1; } while (++i <= 4); @@ -102,8 +104,7 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg) unsigned int opmode; int bitm_off; - /* - * TODO: calculate bit offset from UART_BASE address. + /* TODO: calculate bit offset from UART_BASE address. * E.g.: * 0x9820_0000 -> 0 * 0x9820_0020 -> 1 diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c index b0475495ca8..4a5ec2e13ff 100644 --- a/arch/arm/src/moxart/moxart_irq.c +++ b/arch/arm/src/moxart/moxart_irq.c @@ -101,7 +101,8 @@ void up_irqinitialize(void) (*(volatile uint32_t *)0x98100008) &= ~0x9; - while (!((*(volatile uint32_t *)0x98100008) & 0x2)) { ; } + while (!((*(volatile uint32_t *)0x98100008) & 0x2)) + ; (*(volatile uint32_t *)0x98100008) |= 0x4; diff --git a/arch/arm/src/moxart/moxart_systemreset.c b/arch/arm/src/moxart/moxart_systemreset.c index eeee5456c92..de671edb233 100644 --- a/arch/arm/src/moxart/moxart_systemreset.c +++ b/arch/arm/src/moxart/moxart_systemreset.c @@ -69,7 +69,7 @@ void up_systemreset(void) { putreg32(0, FTWDT010_CR); putreg32(0, FTWDT010_LOAD); - putreg32(0x5ab9, FTWDT010_RESTART); // Magic + putreg32(0x5ab9, FTWDT010_RESTART); /* Magic */ putreg32(0x11, FTWDT010_CR); putreg32(0x13, FTWDT010_CR); diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c index f068573a345..8fe9c6f14e8 100644 --- a/arch/arm/src/nuc1xx/nuc_serial.c +++ b/arch/arm/src/nuc1xx/nuc_serial.c @@ -730,7 +730,7 @@ static int up_interrupt(int irq, void *context) up_serialout(priv, NUC_UART_MCR_OFFSET, regval | UART_MSR_DCTSF); } - /* Check for line status or buffer errors*/ + /* Check for line status or buffer errors */ if ((isr & UART_ISR_RLS_INT) != 0 || (isr & UART_ISR_BUF_ERR_INT) != 0) @@ -739,7 +739,7 @@ static int up_interrupt(int irq, void *context) regval = up_serialin(priv, NUC_UART_FCR_OFFSET); up_serialout(priv, NUC_UART_FCR_OFFSET, regval | UART_FCR_RFR); - } + } } return OK; diff --git a/arch/arm/src/nuc1xx/nuc_timerisr.c b/arch/arm/src/nuc1xx/nuc_timerisr.c index fa64efdfa87..d30e81b85ca 100644 --- a/arch/arm/src/nuc1xx/nuc_timerisr.c +++ b/arch/arm/src/nuc1xx/nuc_timerisr.c @@ -166,10 +166,10 @@ static inline void nuc_lock(void) int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/sam34/sam4cm_supc.c b/arch/arm/src/sam34/sam4cm_supc.c index 73058cda4d4..468466b80fe 100644 --- a/arch/arm/src/sam34/sam4cm_supc.c +++ b/arch/arm/src/sam34/sam4cm_supc.c @@ -85,11 +85,11 @@ void supc_set_slcd_power_mode(uint32_t mode) if (mode == SUPC_MR_LCDMODE_LCDOFF) { - while(getreg32(SAM_SUPC_SR) & SUPC_SR_LCDS); + while (getreg32(SAM_SUPC_SR) & SUPC_SR_LCDS); } else { - while(!(getreg32(SAM_SUPC_SR) & SUPC_SR_LCDS)); + while (!(getreg32(SAM_SUPC_SR) & SUPC_SR_LCDS)); } } diff --git a/arch/arm/src/sam34/sam4l_periphclks.c b/arch/arm/src/sam34/sam4l_periphclks.c index 0deaa097cde..b344992f337 100644 --- a/arch/arm/src/sam34/sam4l_periphclks.c +++ b/arch/arm/src/sam34/sam4l_periphclks.c @@ -256,7 +256,7 @@ static inline void sam_init_pbamask(void) mask |= PM_PBAMASK_TWIM3; /* TWIM3 */ #endif #ifdef CONFIG_SAM34_LCDCA - mask |= PM_PBAMASK_LCDCA; /* LCDCA*/ + mask |= PM_PBAMASK_LCDCA; /* LCDCA */ #endif #endif diff --git a/arch/arm/src/sam34/sam_aes.c b/arch/arm/src/sam34/sam_aes.c index c83ef8e3b0e..b39c8f45aa4 100644 --- a/arch/arm/src/sam34/sam_aes.c +++ b/arch/arm/src/sam34/sam_aes.c @@ -112,7 +112,7 @@ static void aes_encryptblock(void *out, const void *in) putreg32(AES_CR_START, SAM_AES_CR); - while(!(getreg32(SAM_AES_ISR) & AES_ISR_DATRDY)) {} + while (!(getreg32(SAM_AES_ISR) & AES_ISR_DATRDY)); if (out) { @@ -125,42 +125,46 @@ static int aes_setup_mr(uint32_t keysize, int mode, int encrypt) uint32_t regval = AES_MR_SMOD_MANUAL_START | AES_MR_CKEY; if (encrypt) - regval |= AES_MR_CIPHER_ENCRYPT; + { + regval |= AES_MR_CIPHER_ENCRYPT; + } else - regval |= AES_MR_CIPHER_DECRYPT; + { + regval |= AES_MR_CIPHER_DECRYPT; + } - switch(keysize) - { - case 16: - regval |= AES_MR_KEYSIZE_AES128; - break; - case 24: - regval |= AES_MR_KEYSIZE_AES192; - break; - case 32: - regval |= AES_MR_KEYSIZE_AES256; - break; - default: - return -EINVAL; - } + switch (keysize) + { + case 16: + regval |= AES_MR_KEYSIZE_AES128; + break; + case 24: + regval |= AES_MR_KEYSIZE_AES192; + break; + case 32: + regval |= AES_MR_KEYSIZE_AES256; + break; + default: + return -EINVAL; + } - switch(mode) - { - case AES_MODE_ECB: - regval |= AES_MR_OPMOD_ECB; - break; - case AES_MODE_CBC: - regval |= AES_MR_OPMOD_CBC; - break; - case AES_MODE_CTR: - regval |= AES_MR_OPMOD_CTR; - break; - case AES_MODE_CFB: - regval |= AES_MR_OPMOD_CFB; - break; - default: - return -EINVAL; - } + switch (mode) + { + case AES_MODE_ECB: + regval |= AES_MR_OPMOD_ECB; + break; + case AES_MODE_CBC: + regval |= AES_MR_OPMOD_CBC; + break; + case AES_MODE_CTR: + regval |= AES_MR_OPMOD_CTR; + break; + case AES_MODE_CFB: + regval |= AES_MR_OPMOD_CFB; + break; + default: + return -EINVAL; + } putreg32(regval, SAM_AES_MR); return OK; @@ -176,7 +180,9 @@ int aes_cypher(void *out, const void *in, uint32_t size, const void *iv, int res = OK; if (size % 16) - return -EINVAL; + { + return -EINVAL; + } aes_lock(); diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 002971f4abe..abb2f4a8f19 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -1149,15 +1149,15 @@ static int sam_recvframe(struct sam_emac_s *priv) priv->rxndx = rxndx; } - /* Process the next buffer */ + /* Process the next buffer */ - rxdesc = &priv->rxdesc[rxndx]; + rxdesc = &priv->rxdesc[rxndx]; - /* Invalidate the RX descriptor to force re-fetching from RAM */ + /* Invalidate the RX descriptor to force re-fetching from RAM */ - sam_cmcc_invalidate((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); - } + sam_cmcc_invalidate((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + } /* No packet was found */ @@ -3371,7 +3371,7 @@ static int sam_phyinit(struct sam_emac_s *priv) static inline void sam_ethgpioconfig(struct sam_emac_s *priv) { - /* Configure PIO pins to support EMAC in MII mode*/ + /* Configure PIO pins to support EMAC in MII mode */ sam_configgpio(GPIO_EMAC_TXCK); /* Transmit Clock (or Reference Clock) */ sam_configgpio(GPIO_EMAC_TXEN); /* Transmit Enable */ diff --git a/arch/arm/src/sam34/sam_gpioirq.c b/arch/arm/src/sam34/sam_gpioirq.c index cfd3722bd8b..ef6df44985f 100644 --- a/arch/arm/src/sam34/sam_gpioirq.c +++ b/arch/arm/src/sam34/sam_gpioirq.c @@ -388,42 +388,42 @@ void sam_gpioirq(gpio_pinset_t pinset) uint32_t base = sam_gpiobase(pinset); int pin = sam_gpiopin(pinset); - /* Are any additional interrupt modes selected? */ + /* Are any additional interrupt modes selected? */ - if ((pinset & _GIO_INT_AIM) != 0) - { - /* Yes.. Enable additional interrupt mode */ + if ((pinset & _GIO_INT_AIM) != 0) + { + /* Yes.. Enable additional interrupt mode */ - putreg32(pin, base + SAM_PIO_AIMER_OFFSET); + putreg32(pin, base + SAM_PIO_AIMER_OFFSET); - /* Level or edge detected interrupt? */ + /* Level or edge detected interrupt? */ - if ((pinset & _GPIO_INT_LEVEL) != 0) - { - putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */ - } - else - { - putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */ - } + if ((pinset & _GPIO_INT_LEVEL) != 0) + { + putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */ + } + else + { + putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */ + } /* High level/rising edge or low level /falling edge? */ - if ((pinset & _GPIO_INT_RH) != 0) - { - putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */ - } - else - { - putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */ - } - } - else - { - /* No.. Disable additional interrupt mode */ + if ((pinset & _GPIO_INT_RH) != 0) + { + putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */ + } + else + { + putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */ + } + } + else + { + /* No.. Disable additional interrupt mode */ - putreg32(pin, base + SAM_PIO_AIMDR_OFFSET); - } + putreg32(pin, base + SAM_PIO_AIMDR_OFFSET); + } } /************************************************************************************ diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c index 12c4625b016..4e7db3cf756 100644 --- a/arch/arm/src/sam34/sam_hsmci.c +++ b/arch/arm/src/sam34/sam_hsmci.c @@ -1337,10 +1337,10 @@ static int sam_interrupt(int irq, void *context) } } else - { + { /* The Command-Response sequence ended with no error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE; + wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE; } /* Yes.. Is there a thread waiting for this event set? */ @@ -2268,7 +2268,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, if (!timeout) { - return SDIOWAIT_TIMEOUT; + return SDIOWAIT_TIMEOUT; } /* Start the watchdog timer */ diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 0c33e75f13b..6624c0378a0 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -310,8 +310,8 @@ static int sam_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { - *regaddr = NVIC_SYSHCON; - if (irq == SAM_IRQ_MEMFAULT) + *regaddr = NVIC_SYSHCON; + if (irq == SAM_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index 614bcb5fc1a..bc122476940 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -301,7 +301,7 @@ static int rtc_interrupt(int irq, void *context) rtclldbg("ERRPR: work_queue failed: %d\n", ret); } - /* Disable any further alarm interrupts*/ + /* Disable any further alarm interrupts */ putreg32(RTC_IDR_ALRDIS, SAM_RTC_IDR); @@ -437,7 +437,7 @@ int up_rtcinitialize(void) { g_rtt_offset = getreg32(SAM_RTT_VR); } - while(getreg32(SAM_RTT_VR) != g_rtt_offset); + while (getreg32(SAM_RTT_VR) != g_rtt_offset); #endif rtc_dumpregs("After Initialization"); @@ -769,7 +769,6 @@ int sam_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) ************************************************************************************/ #if defined(CONFIG_RTC_HIRES) && defined (CONFIG_SAM34_RTT) - int up_rtc_gettime(FAR struct timespec *tp) { /* This is a hack to emulate a high resolution rtc using the rtt */ @@ -777,13 +776,15 @@ int up_rtc_gettime(FAR struct timespec *tp) struct tm t; do - { - rtc_cal = getreg32(SAM_RTC_CALR); - rtc_tim = getreg32(SAM_RTC_TIMR); - rtt_val = getreg32(SAM_RTT_VR); - } while((rtc_cal != getreg32(SAM_RTC_CALR)) || - (rtc_tim != getreg32(SAM_RTC_TIMR)) || - (rtt_val != getreg32(SAM_RTT_VR))); + { + rtc_cal = getreg32(SAM_RTC_CALR); + rtc_tim = getreg32(SAM_RTC_TIMR); + rtt_val = getreg32(SAM_RTT_VR); + } + while (rtc_cal != getreg32(SAM_RTC_CALR) || + rtc_tim != getreg32(SAM_RTC_TIMR)); + + (rtt_val != getreg32(SAM_RTT_VR))); t.tm_sec = rtc_bcd2bin((rtc_tim & RTC_TIMR_SEC_MASK) >> RTC_TIMR_SEC_SHIFT); t.tm_min = rtc_bcd2bin((rtc_tim & RTC_TIMR_MIN_MASK) >> RTC_TIMR_MIN_SHIFT); diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index 133ecf99b34..577f15ea9a6 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -178,7 +178,7 @@ static inline uint32_t sam34_readvr(void) { v = getreg32(SAM_RTT_VR); } - while(v != getreg32(SAM_RTT_VR)); + while (v != getreg32(SAM_RTT_VR)); return v; } @@ -210,10 +210,10 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } return val; } @@ -434,7 +434,7 @@ static int sam34_stop(FAR struct timer_lowerhalf_s *lower) rttvdbg("Entry\n"); DEBUGASSERT(priv); - if(!priv->started) + if (!priv->started) { return -EINVAL; } @@ -526,7 +526,10 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, DEBUGASSERT(priv); rttvdbg("Entry: timeout=%d\n", timeout); - if(priv->started) return -EPERM; + if (priv->started) + { + return -EPERM; + } /* Can this timeout be represented? */ diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 414ce0c319e..709330e7ffc 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -1347,7 +1347,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, * Save the final word. */ - for ( ; nwords > 0; nwords--) + for (; nwords > 0; nwords--) { /* Get the data to send (0xff if there is no data source). */ diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index d8c3bda76c6..881dff0c0e7 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -192,10 +192,10 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } return val; } @@ -609,7 +609,7 @@ void sam_tcinitialize(FAR const char *devpath, int irq) * is only called once so it is never necessary to re-zero the structure. */ - switch(irq) + switch (irq) { #if defined(CONFIG_SAM34_TC0) case SAM_IRQ_TC0: diff --git a/arch/arm/src/sam34/sam_timerisr.c b/arch/arm/src/sam34/sam_timerisr.c index 29d3f5613fe..9efd73a6ada 100644 --- a/arch/arm/src/sam34/sam_timerisr.c +++ b/arch/arm/src/sam34/sam_timerisr.c @@ -122,10 +122,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index d9e6f6ceb28..1d8c0461e81 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -530,7 +530,7 @@ static int twi_interrupt(struct twi_dev_s *priv) } } - /* Byte sent*/ + /* Byte sent */ else if ((pending & TWI_INT_TXRDY) != 0) { @@ -639,7 +639,7 @@ static void twi_startread(struct twi_dev_s *priv, struct i2c_msg_s *msg) priv->result = -EBUSY; priv->xfrd = 0; - /* Set STOP signal if only one byte is sent*/ + /* Set STOP signal if only one byte is sent */ if (msg->length == 1) { @@ -685,7 +685,7 @@ static void twi_startwrite(struct twi_dev_s *priv, struct i2c_msg_s *msg) twi_putrel(priv, SAM_TWI_IADR_OFFSET, 0); - /* Write first byte to send.*/ + /* Write first byte to send. */ twi_putrel(priv, SAM_TWI_THR_OFFSET, msg->buffer[priv->xfrd++]); @@ -1126,8 +1126,10 @@ static uint32_t twi_hw_setfrequency(struct twi_dev_s *priv, uint32_t frequency) static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid, uint32_t frequency) { - //uint32_t regval; - //uint32_t mck; +#if 0 + uint32_t regval; + uint32_t mck; +#endif i2cvdbg("TWI%d Initializing\n", priv->twi); diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index b4728260c64..2ff77f237ca 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -2224,7 +2224,7 @@ static int sam_udp_interrupt(int irq, void *context) sam_suspend(priv); } - /* SOF interrupt*/ + /* SOF interrupt */ else if ((pending & UDP_INT_SOF) != 0) { @@ -3971,7 +3971,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) sam_pullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; - } + } return ret; } diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index e90e3b2d7d3..f34289af4fb 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -194,10 +194,11 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return val; } } @@ -328,7 +329,7 @@ static int sam34_start(FAR struct watchdog_lowerhalf_s *lower) } #endif - /* TODO: WDT_MR_WDFIEN if handler available? WDT_MR_WDRPROC? */ + /* TODO: WDT_MR_WDFIEN if handler available? WDT_MR_WDRPROC? */ mr_val |= (WDT_MR_WDD(priv->window) | WDT_MR_WDV(priv->reload) | WDT_MR_WDRSTEN); sam34_putreg(mr_val, SAM_WDT_MR); @@ -534,7 +535,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower, static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower, xcpt_t handler) { -#if 0 // TODO +#if 0 /* TODO */ FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; irqstate_t flags; xcpt_t oldhandler; diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index b201d88a559..9c242e123c3 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -384,10 +384,10 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) { if (priv->count == 0xffffffff || ++priv->count > 3) { - if (priv->count == 4) - { - lldbg("...\n"); - } + if (priv->count == 4) + { + lldbg("...\n"); + } return regval; } @@ -1820,7 +1820,7 @@ static int can_autobaud(struct sam_can_s *priv) #warning Missing logic } - while ( no errors reported ); + while (no errors reported); /* Once no error has been detected, the application disables the Autobaud * Mode, clearing the ABM field in the CAN_MR register. To go back to the diff --git a/arch/arm/src/sama5/sam_dbgu.c b/arch/arm/src/sama5/sam_dbgu.c index 9b56d01871f..2474cc11a87 100644 --- a/arch/arm/src/sama5/sam_dbgu.c +++ b/arch/arm/src/sama5/sam_dbgu.c @@ -201,7 +201,7 @@ static void dbgu_configure(void) /* Enable receiver & transmitter */ - putreg32((DBGU_CR_RXEN|DBGU_CR_TXEN), SAM_DBGU_CR); + putreg32((DBGU_CR_RXEN | DBGU_CR_TXEN), SAM_DBGU_CR); } #else @@ -256,7 +256,8 @@ static void dbgu_shutdown(struct uart_dev_s *dev) /* Reset and disable receiver and transmitter */ - putreg32((DBGU_CR_RSTRX|DBGU_CR_RSTTX|DBGU_CR_RXDIS|DBGU_CR_TXDIS), SAM_DBGU_CR); + putreg32((DBGU_CR_RSTRX | DBGU_CR_RSTTX | DBGU_CR_RXDIS | DBGU_CR_TXDIS), + SAM_DBGU_CR); /* Disable all interrupts */ diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index 300c4e11f4f..5230ba3ff63 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -1826,7 +1826,7 @@ static int sam_dmac_interrupt(struct sam_dmac_s *dmac) /* Is the transfer complete? */ else if ((regval & DMAC_EBC_CBTC(chndx)) != 0) - { + { /* Yes.. Terminate the transfer with success */ sam_dmaterminate(dmach, OK); diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index fafbeb90ae3..bb4af13a93f 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -1155,15 +1155,15 @@ static int sam_recvframe(struct sam_emac_s *priv) priv->rxndx = rxndx; } - /* Process the next buffer */ + /* Process the next buffer */ - rxdesc = &priv->rxdesc[rxndx]; + rxdesc = &priv->rxdesc[rxndx]; - /* Invalidate the RX descriptor to force re-fetching from RAM */ + /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); - } + arch_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); + } /* No packet was found */ @@ -1274,7 +1274,7 @@ static void sam_receive(struct sam_emac_s *priv) */ if (priv->dev.d_len > 0) - { + { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 @@ -2624,7 +2624,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr, /* Write the PHY Maintenance register */ regval = EMAC_MAN_DATA(phyval) | EMAC_MAN_CODE | EMAC_MAN_REGA(regaddr) | - EMAC_MAN_PHYA(phyaddr) | EMAC_MAN_WRITE| EMAC_MAN_SOF; + EMAC_MAN_PHYA(phyaddr) | EMAC_MAN_WRITE | EMAC_MAN_SOF; sam_putreg(priv, SAM_EMAC_MAN, regval); /* Wait until the PHY is again IDLE */ diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 4624bf49369..a8ae8b0b495 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -3934,7 +3934,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) if (priv->attr->emac == EMAC0_INTF) { - /* Configure PIO pins common to RMII and MII mode*/ + /* Configure PIO pins common to RMII and MII mode */ sam_configpio(PIO_EMAC0_TXCK); /* Transmit Clock (or Reference Clock) */ sam_configpio(PIO_EMAC0_TXEN); /* Transmit Enable */ @@ -3947,7 +3947,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) sam_configpio(PIO_EMAC0_MDC); /* Management Data Clock */ sam_configpio(PIO_EMAC0_MDIO); /* Management Data Input/Output */ - /* Configure additional PIO pins to support EMAC in MII mode*/ + /* Configure additional PIO pins to support EMAC in MII mode */ if (!priv->attr->rmii) { @@ -3969,7 +3969,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) if (priv->attr->emac == EMAC1_INTF) { - /* Configure PIO pins common to RMII and MII mode*/ + /* Configure PIO pins common to RMII and MII mode */ sam_configpio(PIO_EMAC1_TXCK); /* Transmit Clock (or Reference Clock) */ sam_configpio(PIO_EMAC1_TXEN); /* Transmit Enable */ @@ -3982,7 +3982,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) sam_configpio(PIO_EMAC1_MDC); /* Management Data Clock */ sam_configpio(PIO_EMAC1_MDIO); /* Management Data Input/Output */ - /* Configure additional PIO pins to support EMAC in MII mode*/ + /* Configure additional PIO pins to support EMAC in MII mode */ if (!priv->attr->rmii) { diff --git a/arch/arm/src/sama5/sam_flexcom_serial.c b/arch/arm/src/sama5/sam_flexcom_serial.c index 14a235ba18f..97d11e0dbff 100644 --- a/arch/arm/src/sama5/sam_flexcom_serial.c +++ b/arch/arm/src/sama5/sam_flexcom_serial.c @@ -747,12 +747,12 @@ static int flexus_setup(struct uart_dev_s *dev) * This may limit BAUD rates for lower USART clocks. */ - regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4); + regval = (SAM_USART_CLOCK + (priv->baud << 3)) / (priv->baud << 4); flexus_serialout(priv, SAM_FLEXUS_BRGR_OFFSET, regval); /* Enable receiver & transmitter */ - flexus_serialout(priv, SAM_FLEXUS_CR_OFFSET, (FLEXUS_CR_RXEN|FLEXUS_CR_TXEN)); + flexus_serialout(priv, SAM_FLEXUS_CR_OFFSET, (FLEXUS_CR_RXEN | FLEXUS_CR_TXEN)); #endif return OK; } @@ -773,7 +773,8 @@ static void flexus_shutdown(struct uart_dev_s *dev) /* Reset and disable receiver and transmitter */ flexus_serialout(priv, SAM_FLEXUS_CR_OFFSET, - (FLEXUS_CR_RSTRX|FLEXUS_CR_RSTTX|FLEXUS_CR_RXDIS|FLEXUS_CR_TXDIS)); + (FLEXUS_CR_RSTRX | FLEXUS_CR_RSTTX | FLEXUS_CR_RXDIS | + FLEXUS_CR_TXDIS)); /* Disable all interrupts */ diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index 5bd7896bc94..ce6eaeb69be 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -1085,15 +1085,15 @@ static int sam_recvframe(struct sam_gmac_s *priv) priv->rxndx = rxndx; } - /* Process the next buffer */ + /* Process the next buffer */ - rxdesc = &priv->rxdesc[rxndx]; + rxdesc = &priv->rxdesc[rxndx]; - /* Invalidate the RX descriptor to force re-fetching from RAM */ + /* Invalidate the RX descriptor to force re-fetching from RAM */ - arch_invalidate_dcache((uintptr_t)rxdesc, - (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s)); - } + arch_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s)); + } /* No packet was found */ @@ -1507,7 +1507,7 @@ static int sam_gmac_interrupt(int irq, void *context) clrbits |= GMAC_RSR_BNA; } - /* Check for HRESP not OK (HNO)*/ + /* Check for HRESP not OK (HNO) */ if ((rsr & GMAC_RSR_HNO) != 0) { diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index c82a9a77cfd..d90176cb8a7 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -1542,13 +1542,13 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) { /* Yes.. Terminate with a timeout. */ - sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_TIMEOUT); + sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } else { /* No.. Terminate with an I/O error. */ - sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR); + sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } } @@ -1616,20 +1616,22 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) { /* Yes.. signal a timeout error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_TIMEOUT; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_TIMEOUT; } else { /* No.. signal some generic I/O error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_ERROR; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_ERROR; } } else - { + { /* The Command-Response sequence ended with no error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE; } /* Yes.. Is there a thread waiting for this event set? */ @@ -2393,14 +2395,16 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* Yes.. return a timeout error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_TIMEOUT; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_TIMEOUT; return -ETIMEDOUT; } else { /* No.. return some generic I/O error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_ERROR; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_ERROR; return -EIO; } } @@ -2408,7 +2412,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* The Command-Response sequence ended with no error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE; return OK; } } @@ -2647,7 +2651,7 @@ static void sam_waitenable(FAR struct sdio_dev_s *dev, */ waitmask = 0; - if ((eventset & (SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE)) != 0) + if ((eventset & (SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE)) != 0) { waitmask |= priv->cmdrmask; } @@ -2723,7 +2727,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, if (!timeout) { - return SDIOWAIT_TIMEOUT; + return SDIOWAIT_TIMEOUT; } /* Start the watchdog timer. I am not sure why this is, but I am diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index 72b2271622b..9ea92e0451b 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -1091,7 +1091,7 @@ static void sam_putreg(uintptr_t address, uint32_t regval) static void sam_wait_lcdstatus(uint32_t mask, uint32_t value) { - while ((sam_getreg(SAM_LCDC_LCDSR) & mask) != value); + while ((sam_getreg(SAM_LCDC_LCDSR) & mask) != value); } /**************************************************************************** @@ -2451,7 +2451,7 @@ static void sam_show_layer(struct sam_layer_s *layer, imgh = 1; } - /* Set display buffer and mode setup*/ + /* Set display buffer and mode setup */ bytespp = (uint32_t)layer->bpp >> 3; bprow = imgw * (uint32_t)layer->bpp; @@ -2547,7 +2547,7 @@ static void sam_show_layer(struct sam_layer_s *layer, /* Pointer to Right,Top (x1,y0) */ buffer = (uint8_t *) - ((uint32_t)layer->framebuffer + bytespp*(imgw - 1)); + ((uint32_t)layer->framebuffer + bytespp * (imgw - 1)); } /* Y mirror: Left,Down -> Right,Top */ @@ -2579,7 +2579,7 @@ static void sam_show_layer(struct sam_layer_s *layer, /* Pointer to Left,Down (x0,y1) */ buffer = (uint8_t *) - ((uintptr_t)layer->framebuffer + (bytesprow+padding)*(imgh-1)); + ((uintptr_t)layer->framebuffer + (bytesprow + padding) * (imgh - 1)); } /* X,Y mirror: Right,Top -> Left,Down */ @@ -2612,8 +2612,8 @@ static void sam_show_layer(struct sam_layer_s *layer, buffer = (uint8_t *) ((uint32_t)layer->framebuffer + - (bytesprow + padding)*(imgh - 1) + - bytespp*(imgw -1 )); + (bytesprow + padding) * (imgh - 1) + + bytespp * (imgw - 1)); } /* Rotate 90: Down,Left -> Top,Right (with w,h swap) */ @@ -2640,13 +2640,13 @@ static void sam_show_layer(struct sam_layer_s *layer, /* X ++ as rows */ regaddr = g_layerstride[lid]; - sam_putreg(regaddr, (bytesprow + padding)*(imgh - 1)); + sam_putreg(regaddr, (bytesprow + padding) * (imgh - 1)); /* Pointer to Bottom,Left */ buffer = (uint8_t *) ((uint32_t)layer->framebuffer + - (bytesprow + padding)*(imgh - 1)); + (bytesprow + padding) * (imgh - 1)); } /* Rotate 270: Top,Right -> Down,Left (with w,h swap) */ @@ -2673,12 +2673,12 @@ static void sam_show_layer(struct sam_layer_s *layer, /* X -- as rows */ regaddr = g_layerstride[lid]; - sam_putreg(regaddr, 0 - 2*bytespp - (bytesprow + padding)*(imgh - 1)); + sam_putreg(regaddr, 0 - 2*bytespp - (bytesprow + padding) * (imgh - 1)); /* Pointer to top right */ buffer = (uint8_t *) - ((uintptr_t)layer->framebuffer + bytespp*(imgw - 1)); + ((uintptr_t)layer->framebuffer + bytespp * (imgw - 1)); } /* Mirror X then Rotate 90: Down,Right -> Top,Left */ @@ -2705,20 +2705,20 @@ static void sam_show_layer(struct sam_layer_s *layer, /* X -- as rows */ regaddr = g_layerstride[lid]; - sam_putreg(regaddr, 0 - 2*bytespp + (bytesprow + padding)*(imgh - 1)); + sam_putreg(regaddr, 0 - 2 * bytespp + (bytesprow + padding) * (imgh - 1)); /* Pointer to down right (x1,y1) */ buffer = (uint8_t *) ((uintptr_t)layer->framebuffer + - (bytesprow+padding)*(imgh - 1) + - (bytespp)*(imgw - 1)); + (bytesprow + padding) * (imgh - 1) + + (bytespp) * (imgw - 1)); } /* Mirror Y then Rotate 90: Top,Left -> Down,Right */ - else if ((!rightleft && bottomup && layer->rotation == 90) - ||(rightleft && !bottomup && layer->rotation == LCDC_ROT_270)) + else if ((!rightleft && bottomup && layer->rotation == 90) || + ( rightleft && !bottomup && layer->rotation == LCDC_ROT_270)) { /* No rotation optimization */ @@ -2739,7 +2739,7 @@ static void sam_show_layer(struct sam_layer_s *layer, /* X ++ as rows */ regaddr = g_layerstride[lid]; - sam_putreg(regaddr, 0 - (bytesprow + padding)*(imgh - 1)); + sam_putreg(regaddr, 0 - (bytesprow + padding) * (imgh - 1)); /* Pointer to top left (x0,y0) */ } diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index 1b2a51d741c..c6d5e8e1d38 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -574,7 +574,7 @@ static int nand_translate_address(struct sam_nandcs_s *priv, static uint32_t nand_get_acycle(int ncycles) { - switch(ncycles) + switch (ncycles) { case 1: return NFCADDR_CMD_ACYCLE_ONE; diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index 4a9a54cd470..acb5492519d 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -1665,7 +1665,7 @@ static void sam_ep0dequeue(struct sam_eplist_s *ep0) preved = NULL; curred && curred != edctrl; preved = curred, - curred =(struct sam_ed_s *)sam_virtramaddr(physcurr)) + curred = (struct sam_ed_s *)sam_virtramaddr(physcurr)) { physcurr = curred->hw.nexted; } @@ -1712,7 +1712,7 @@ static void sam_ep0dequeue(struct sam_eplist_s *ep0) for (currtd = (struct sam_gtd_s *)sam_virtramaddr(physcurr); currtd && currtd != tdtail; - currtd =(struct sam_gtd_s *)sam_virtramaddr(physcurr)) + currtd = (struct sam_gtd_s *)sam_virtramaddr(physcurr)) { physcurr = currtd->hw.nexttd; sam_tdfree(currtd); @@ -2125,7 +2125,7 @@ static void sam_wdh_bottomhalf(void) */ arch_invalidate_dcache((uintptr_t)td, - (uintptr_t)td + sizeof( struct ohci_gtd_s)); + (uintptr_t)td + sizeof(struct ohci_gtd_s)); /* Get the ED in which this TD was enqueued */ @@ -2152,7 +2152,7 @@ static void sam_wdh_bottomhalf(void) */ arch_invalidate_dcache((uintptr_t)ed, - (uintptr_t)ed + sizeof( struct ohci_ed_s)); + (uintptr_t)ed + sizeof(struct ohci_ed_s)); /* Save the condition code from the (single) TD status/control * word. @@ -3393,7 +3393,7 @@ static ssize_t sam_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, } nbytes = eplist->xfrd; - DEBUGASSERT(nbytes >=0 && nbytes <= buflen); + DEBUGASSERT(nbytes >= 0 && nbytes <= buflen); sam_givesem(&g_ohci.exclsem); return nbytes; diff --git a/arch/arm/src/sama5/sam_pioirq.c b/arch/arm/src/sama5/sam_pioirq.c index 9167cc057c8..de4eec38ad1 100644 --- a/arch/arm/src/sama5/sam_pioirq.c +++ b/arch/arm/src/sama5/sam_pioirq.c @@ -404,8 +404,8 @@ void sam_pioirq(pio_pinset_t pinset) /* Is the interrupt secure? */ - regval = getreg32(base + SAM_PIO_ISLR_OFFSET); - if ((pinset & PIO_INT_SECURE) != 0) + regval = getreg32(base + SAM_PIO_ISLR_OFFSET); + if ((pinset & PIO_INT_SECURE) != 0) { /* Yes.. make sure that the corresponding bit in ISLR is cleared */ diff --git a/arch/arm/src/sama5/sam_pmecc.c b/arch/arm/src/sama5/sam_pmecc.c index a964292006a..b1f24333ab9 100644 --- a/arch/arm/src/sama5/sam_pmecc.c +++ b/arch/arm/src/sama5/sam_pmecc.c @@ -98,7 +98,7 @@ struct pmecc_desc_s { uint32_t pagesize; /* 0-3: See HSMC_PMECCFG_PAGESIZE_* definitions */ uint32_t sparesize; /* 4-7: The spare area size is equal to (SPARESIZE+1) bytes */ - uint32_t sectorsz; /* 8-11: See HSMC_PMECCFG_SECTORSZ_* definitions*/ + uint32_t sectorsz; /* 8-11: See HSMC_PMECCFG_SECTORSZ_* definitions */ uint32_t bcherr; /* 12-15: See HSMC_PMECCFG_BCHERR_* definitions */ uint32_t eccsize; /* 16-19: Real size in bytes of ECC in spare */ uint32_t eccstart; /* 20-23: The first byte address of the ECC area */ @@ -440,13 +440,13 @@ static uint32_t pmecc_getsigma(void) /* Compute degree of the new smu polynomial */ - if ((lmu[i]>>1) > ((lmu[ro]>>1) + diff)) + if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff)) { lmu[i + 1] = lmu[i]; } else { - lmu[i + 1] = ((lmu[ro]>>1) + diff) * 2; + lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2; } /* Init smu[i+1] with 0 */ @@ -458,7 +458,7 @@ static uint32_t pmecc_getsigma(void) /* Compute smu[i+1] */ - for (k = 0; k <= lmu[ro]>>1; k ++) + for (k = 0; k <= lmu[ro] >> 1; k++) { if (g_pmecc.desc.smu[ro][k] && dmu[i]) { @@ -469,7 +469,7 @@ static uint32_t pmecc_getsigma(void) } } - for (k = 0; k <= lmu[i]>>1; k ++) + for (k = 0; k <= lmu[i] >> 1; k++) { g_pmecc.desc.smu[i+1][k] ^= g_pmecc.desc.smu[i][k]; } @@ -646,7 +646,7 @@ static uint32_t pmecc_errorcorrection(uintptr_t sectorbase, } else { - if (*(uint8_t*)(sectorbase + bytepos + eccsize)& (1 << bitpos)) + if (*(uint8_t*)(sectorbase + bytepos + eccsize) & (1 << bitpos)) { *(uint8_t*)(sectorbase + bytepos + eccsize) &= (0xff ^ (1 << bitpos)); } @@ -775,14 +775,14 @@ static int pmecc_bcherr512(uint8_t nsectors, uint16_t eccsize) /* 7-bytes per 512 byte sector are required correctability of 4 errors */ - else if (eccsize >= (7 *(unsigned int) nsectors)) + else if (eccsize >= (7 * (unsigned int) nsectors)) { return BCH_ERR4; } /* 4-bytes per 512 byte sector are required correctability of 2 errors */ - else if (eccsize >= (4 *(unsigned int) nsectors)) + else if (eccsize >= (4 * (unsigned int) nsectors)) { return BCH_ERR2; } @@ -823,14 +823,14 @@ static int pmecc_bcherr1k(uint8_t nsectors, uint16_t eccsize) /* 7-bytes per 1024 byte sector are required correctability of 4 errors */ - else if (eccsize >= (7 *(unsigned int) nsectors)) + else if (eccsize >= (7 * (unsigned int) nsectors)) { return BCH_ERR4; } /* 4-bytes per 1024 byte sector are required correctability of 2 errors */ - else if (eccsize >= (4 *(unsigned int) nsectors)) + else if (eccsize >= (4 * (unsigned int) nsectors)) { return BCH_ERR2; } @@ -934,7 +934,9 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize) DEBUGASSERT(bcherr512 >= 0); break; } - } /* Otherwise, fall through for the 1KB sectors */ + } + + /* Otherwise, fall through for the 1KB sectors */ case 2: /* 512B sectors not possible; 1KB sectors possible */ { @@ -1347,7 +1349,7 @@ uint32_t pmecc_get_pagesize(void) ****************************************************************************/ #ifdef CONFIG_SAMA5_PMECC_GALOIS_CUSTOM -void pmecc_buildgf(uint32_t mm, int16_t* indexof, int16_t* alphato) +void pmecc_buildgf(uint32_t mm, int16_t *indexof, int16_t *alphato) { uint32_t i; uint32_t mask; diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c index 01539235a6c..51eafdcb673 100644 --- a/arch/arm/src/sama5/sam_rtc.c +++ b/arch/arm/src/sama5/sam_rtc.c @@ -292,7 +292,7 @@ static int rtc_interrupt(int irq, void *context) rtclldbg("ERRPR: work_queue failed: %d\n", ret); } - /* Disable any further alarm interrupts*/ + /* Disable any further alarm interrupts */ putreg32(RTC_IDR_ALRDIS, SAM_RTC_IDR); diff --git a/arch/arm/src/sama5/sam_sckc.c b/arch/arm/src/sama5/sam_sckc.c index adc96561799..e416aebd8db 100644 --- a/arch/arm/src/sama5/sam_sckc.c +++ b/arch/arm/src/sama5/sam_sckc.c @@ -109,7 +109,7 @@ void sam_sckc_enable(bool enable) regval &= ~SCKC_CR_OSC32BYP; putreg32(regval, SAM_SCKC_CR); - /* Switch slow clock source to external OSC 32 kHz (*/ + /* Switch slow clock source to external OSC 32 kHz */ regval |= SCKC_CR_OSCSEL; putreg32(regval, SAM_SCKC_CR); diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index 9cf97cf1fa5..f007e69810e 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -1238,12 +1238,12 @@ static int up_setup(struct uart_dev_s *dev) * This may limit BAUD rates for lower USART clocks. */ - regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4); + regval = (SAM_USART_CLOCK + (priv->baud << 3)) / (priv->baud << 4); up_serialout(priv, SAM_UART_BRGR_OFFSET, regval); /* Enable receiver & transmitter */ - up_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN|UART_CR_TXEN)); + up_serialout(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN | UART_CR_TXEN)); #endif return OK; } @@ -1264,7 +1264,8 @@ static void up_shutdown(struct uart_dev_s *dev) /* Reset and disable receiver and transmitter */ up_serialout(priv, SAM_UART_CR_OFFSET, - (UART_CR_RSTRX|UART_CR_RSTTX|UART_CR_RXDIS|UART_CR_TXDIS)); + (UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | + UART_CR_TXDIS)); /* Disable all interrupts */ diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c index a1681e54c8f..bc5fa8fe4e7 100644 --- a/arch/arm/src/sama5/sam_ssc.c +++ b/arch/arm/src/sama5/sam_ssc.c @@ -365,7 +365,7 @@ DMACH_FLAG_PERIPHISPERIPH | DMACH_FLAG_PERIPHWIDTH_8BITS | \ DMACH_FLAG_PERIPHCHUNKSIZE_1 | DMACH_FLAG_MEMPID_MAX | \ DMACH_FLAG_MEM_IF | DMACH_FLAG_MEMWIDTH_16BITS | \ - DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_1| \ + DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_1 | \ DMACH_FLAG_MEMBURST_4) #define DMA16_FLAGS \ diff --git a/arch/arm/src/sama5/sam_timerisr.c b/arch/arm/src/sama5/sam_timerisr.c index 4814bf445ea..3861b1217a3 100644 --- a/arch/arm/src/sama5/sam_timerisr.c +++ b/arch/arm/src/sama5/sam_timerisr.c @@ -102,7 +102,7 @@ int up_timerisr(int irq, uint32_t *regs) * Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is * reset and the PITS is cleared, thus acknowledging the interrupt. The * value of PICNT gives the number of periodic intervals elapsed since the - * last read of PIT_PIVR. + * last read of PIT_PIVR." */ uint32_t picnt = getreg32(SAM_PIT_PIVR) >> PIT_PICNT_SHIFT; diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c index 3f0d701fdb1..0480d2e6e48 100644 --- a/arch/arm/src/sama5/sam_trng.c +++ b/arch/arm/src/sama5/sam_trng.c @@ -144,9 +144,9 @@ static int sam_interrupt(int irq, void *context) if ((getreg32(SAM_TRNG_ISR) & TRNG_INT_DATRDY) == 0) { - /* No? Then return and continue processing on the next interrupt. */ + /* No? Then return and continue processing on the next interrupt. */ - return OK; + return OK; } /* As required by the FIPS PUB (Federal Information Processing Standard @@ -258,7 +258,7 @@ static ssize_t sam_read(struct file *filep, char *buffer, size_t buflen) DEBUGASSERT(((uintptr_t)buffer & 3) == 0); - g_trngdev.samples = (uint32_t*)buffer; + g_trngdev.samples = (uint32_t *)buffer; g_trngdev.maxsamples = buflen >> 2; g_trngdev.nsamples = 0; g_trngdev.first = true; diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index 9c44bdd370a..2f930effe6c 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -315,7 +315,7 @@ static int sam_tsd_sample(struct sam_tsd_s *priv, struct sam_sample_s *sample) * sampled data. */ - memcpy(sample, &priv->sample, sizeof(struct sam_sample_s )); + memcpy(sample, &priv->sample, sizeof(struct sam_sample_s)); /* Now manage state transitions */ @@ -330,10 +330,10 @@ static int sam_tsd_sample(struct sam_tsd_s *priv, struct sam_sample_s *sample) priv->id++; } else if (sample->contact == CONTACT_DOWN) - { + { /* First report -- next report will be a movement */ - priv->sample.contact = CONTACT_MOVE; + priv->sample.contact = CONTACT_MOVE; } priv->penchange = false; @@ -596,9 +596,9 @@ static void sam_tsd_bottomhalf(void *arg) * this case; we rely on the timer expiry to get us going again. */ - wd_start(priv->wdog, TSD_WDOG_DELAY, sam_tsd_expiry, 1, (uint32_t)priv); - ier = 0; - goto ignored; + wd_start(priv->wdog, TSD_WDOG_DELAY, sam_tsd_expiry, 1, (uint32_t)priv); + ier = 0; + goto ignored; } else { diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index 99764c8c81f..ed6bca63e18 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -635,7 +635,7 @@ static int twi_interrupt(struct twi_dev_s *priv) } } - /* Byte sent*/ + /* Byte sent */ else if ((pending & TWI_INT_TXRDY) != 0) { @@ -768,7 +768,7 @@ static void twi_startread(struct twi_dev_s *priv, struct i2c_msg_s *msg) priv->result = -EBUSY; priv->xfrd = 0; - /* Set STOP signal if only one byte is sent*/ + /* Set STOP signal if only one byte is sent */ if (msg->length == 1) { @@ -815,7 +815,7 @@ static void twi_startwrite(struct twi_dev_s *priv, struct i2c_msg_s *msg) twi_putrel(priv, SAM_TWI_IADR_OFFSET, 0); - /* Write first byte to send.*/ + /* Write first byte to send. */ twi_putrel(priv, SAM_TWI_THR_OFFSET, msg->buffer[priv->xfrd++]); diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index 0c31311f884..6394c389b38 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -2816,7 +2816,7 @@ static int sam_udphs_interrupt(int irq, void *context) sam_suspend(priv); } - /* SOF interrupt*/ + /* SOF interrupt */ else if ((pending & UDPHS_INT_INTSOF) != 0) { @@ -3497,7 +3497,7 @@ static struct usbdev_req_s *sam_ep_allocreq(struct usbdev_ep_s *ep) static void sam_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct sam_req_s *privreq = (struct sam_req_s*)req; + struct sam_req_s *privreq = (struct sam_req_s *)req; #ifdef CONFIG_DEBUG if (!ep || !req) @@ -4293,7 +4293,7 @@ static void sam_sw_setup(struct sam_usbdev_s *priv) priv->dtdpool = (struct sam_dtd_s *) kmm_memalign(16, CONFIG_SAMA5_UDPHS_NDTDS * sizeof(struct sam_dtd_s)); if (!priv->dtdpool) - { + { udbg("ERROR: Failed to allocate the DMA transfer descriptor pool\n"); return NULL; } diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index 58724d12a1c..cf4cda81108 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -196,10 +196,11 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 0xffffffff || ++count > 3) { - if (count == 4) - { - lldbg("...\n"); - } + if (count == 4) + { + lldbg("...\n"); + } + return regval; } } diff --git a/arch/arm/src/sama5/sama5d2x_pio.c b/arch/arm/src/sama5/sama5d2x_pio.c index 7c54fece09a..a96c50331ab 100644 --- a/arch/arm/src/sama5/sama5d2x_pio.c +++ b/arch/arm/src/sama5/sama5d2x_pio.c @@ -649,8 +649,7 @@ int sam_dumppio(uint32_t pinset, const char *msg) { lldbg(" SCDR: %08x WPMR: %08x WPSR: %08x IOSSR: %08x\n", getreg32(SAM_SPIO_SCDR), getreg32(SAM_SPIO_WPMR), - getreg32(SAM_SPIO_WPSR), getreg32(base + SAM_SPIO_IOSSR_OFFSET), - ); + getreg32(SAM_SPIO_WPSR), getreg32(base + SAM_SPIO_IOSSR_OFFSET)); } else { diff --git a/arch/arm/src/samdl/sam_irq.c b/arch/arm/src/samdl/sam_irq.c index 224c6b062ff..8ef2a6361b9 100644 --- a/arch/arm/src/samdl/sam_irq.c +++ b/arch/arm/src/samdl/sam_irq.c @@ -59,7 +59,7 @@ /* Get a 32-bit version of the default priority */ #define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) /**************************************************************************** diff --git a/arch/arm/src/samdl/sam_serial.c b/arch/arm/src/samdl/sam_serial.c index b21332eb601..ea8e9affc6d 100644 --- a/arch/arm/src/samdl/sam_serial.c +++ b/arch/arm/src/samdl/sam_serial.c @@ -557,7 +557,7 @@ static void sam_disableallints(struct sam_dev_s *priv) static int sam_interrupt(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv;; uint8_t pending; uint8_t intflag; uint8_t inten; @@ -663,7 +663,7 @@ static int sam_setup(struct uart_dev_s *dev) { int ret = 0; #ifndef CONFIG_SUPPRESS_UART_CONFIG - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; /* Configure the SERCOM as a USART. Don't reconfigure the console UART; * that was already done in sam_lowputc.c. @@ -689,7 +689,7 @@ static int sam_setup(struct uart_dev_s *dev) static void sam_shutdown(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; /* Resetting the SERCOM restores all registers to the reget state and * disables the SERCOM. Ignore any requests to shutown the console @@ -720,7 +720,7 @@ static void sam_shutdown(struct uart_dev_s *dev) static int sam_attach(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; const struct sam_usart_config_s * const config = priv->config; int ret; @@ -751,7 +751,7 @@ static int sam_attach(struct uart_dev_s *dev) static void sam_detach(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; const struct sam_usart_config_s * const config = priv->config; /* Disable interrupts at the SERCOM device and at the NVIC */ @@ -785,7 +785,7 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct sam_dev_s *user = (struct sam_dev_s*)arg; + struct sam_dev_s *user = (struct sam_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -818,7 +818,7 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) static int sam_receive(struct uart_dev_s *dev, uint32_t *status) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; /* Return read status */ @@ -839,7 +839,7 @@ static int sam_receive(struct uart_dev_s *dev, uint32_t *status) static void sam_rxint(struct uart_dev_s *dev, bool enable) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; if (enable) { @@ -865,7 +865,7 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable) static bool sam_rxavailable(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_RXC) != 0); } @@ -879,7 +879,7 @@ static bool sam_rxavailable(struct uart_dev_s *dev) static void sam_send(struct uart_dev_s *dev, int ch) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; sam_serialout16(priv, SAM_USART_DATA_OFFSET, (uint16_t)ch); } @@ -893,7 +893,7 @@ static void sam_send(struct uart_dev_s *dev, int ch) static void sam_txint(struct uart_dev_s *dev, bool enable) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -934,7 +934,7 @@ static void sam_txint(struct uart_dev_s *dev, bool enable) static bool sam_txempty(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; return ((sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET) & USART_INT_DRE) != 0); } diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c index 8851da74a7a..afd51e98c44 100644 --- a/arch/arm/src/samdl/sam_spi.c +++ b/arch/arm/src/samdl/sam_spi.c @@ -799,7 +799,7 @@ static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg) #if 0 /* Not used */ static int spi_interrupt(struct sam_spidev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv;; uint8_t pending; uint8_t intflag; uint8_t inten; @@ -959,7 +959,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct sam_spidev_s *priv =(struct sam_spidev_s *)dev; + struct sam_spidev_s *priv = (struct sam_spidev_s *)dev; uint32_t maxfreq; uint32_t actual; uint32_t baud; diff --git a/arch/arm/src/samdl/sam_timerisr.c b/arch/arm/src/samdl/sam_timerisr.c index 73506945727..327e8b72b03 100644 --- a/arch/arm/src/samdl/sam_timerisr.c +++ b/arch/arm/src/samdl/sam_timerisr.c @@ -105,10 +105,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/samdl/sam_userspace.c b/arch/arm/src/samdl/sam_userspace.c index 8a55c7c9eaa..613aa33b3c8 100644 --- a/arch/arm/src/samdl/sam_userspace.c +++ b/arch/arm/src/samdl/sam_userspace.c @@ -86,8 +86,8 @@ void sam_userspace(void) DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && USERSPACE->us_bssstart <= USERSPACE->us_bssend); - dest = (uint8_t*)USERSPACE->us_bssstart; - end = (uint8_t*)USERSPACE->us_bssend; + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; while (dest != end) { @@ -100,9 +100,9 @@ void sam_userspace(void) USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && USERSPACE->us_datastart <= USERSPACE->us_dataend); - src = (uint8_t*)USERSPACE->us_datasource; - dest = (uint8_t*)USERSPACE->us_datastart; - end = (uint8_t*)USERSPACE->us_dataend; + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; while (dest != end) { diff --git a/arch/arm/src/samv7/sam_allocateheap.c b/arch/arm/src/samv7/sam_allocateheap.c index 35a335f9eeb..f092d0767f6 100644 --- a/arch/arm/src/samv7/sam_allocateheap.c +++ b/arch/arm/src/samv7/sam_allocateheap.c @@ -238,7 +238,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the user-space heap settings */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)ubase; + *heap_start = (FAR void *)ubase; *heap_size = usize; /* Allow user-mode access to the user heap memory */ @@ -249,7 +249,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) /* Return the heap settings */ board_led_on(LED_HEAPALLOCATE); - *heap_start = (FAR void*)g_idle_topstack; + *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; #endif } @@ -328,7 +328,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_EXTCS0_BASE, CONFIG_SAMV7_EXTSRAM0SIZE); + kumm_addregion((FAR void *)SAM_EXTCS0_BASE, CONFIG_SAMV7_EXTSRAM0SIZE); #endif /* HAVE_EXTSRAM0_REGION */ @@ -339,7 +339,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_EXTCS1_BASE, CONFIG_SAMV7_EXTSRAM1SIZE); + kumm_addregion((FAR void *)SAM_EXTCS1_BASE, CONFIG_SAMV7_EXTSRAM1SIZE); #endif /* HAVE_EXTSRAM0_REGION */ @@ -350,7 +350,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_EXTCS2_BASE, CONFIG_SAMV7_EXTSRAM2SIZE); + kumm_addregion((FAR void *)SAM_EXTCS2_BASE, CONFIG_SAMV7_EXTSRAM2SIZE); #endif /* HAVE_EXTSRAM0_REGION */ @@ -361,7 +361,7 @@ void up_addregion(void) /* Add the region */ - kumm_addregion((FAR void*)SAM_EXTCS3_BASE, CONFIG_SAMV7_EXTSRAM3SIZE); + kumm_addregion((FAR void *)SAM_EXTCS3_BASE, CONFIG_SAMV7_EXTSRAM3SIZE); #endif /* HAVE_EXTSRAM0_REGION */ } diff --git a/arch/arm/src/samv7/sam_clockconfig.c b/arch/arm/src/samv7/sam_clockconfig.c index 35afb26fffb..a15f06933ef 100644 --- a/arch/arm/src/samv7/sam_clockconfig.c +++ b/arch/arm/src/samv7/sam_clockconfig.c @@ -137,7 +137,7 @@ static inline void sam_supcsetup(void) { uint32_t delay; - putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR); + putreg32((SUPC_CR_XTALSEL | SUPR_CR_KEY), SAM_SUPC_CR); for (delay = 0; (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX; delay++); @@ -312,19 +312,19 @@ static inline void sam_enabledefaultmaster(void) /* Set default master: SRAM0 -> Cortex-M7 System */ regval = getreg32(SAM_MATRIX_SCFG0); - regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS | MATRIX_SCFG_DEFMSTRTYPE_FIXED); putreg32(regval, SAM_MATRIX_SCFG0); /* Set default master: SRAM1 -> Cortex-M7 System */ regval = getreg32(SAM_MATRIX_SCFG1); - regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS | MATRIX_SCFG_DEFMSTRTYPE_FIXED); putreg32(regval, SAM_MATRIX_SCFG1); /* Set default master: Internal flash0 -> Cortex-M7 Instruction/Data */ regval = getreg32(SAM_MATRIX_SCFG3); - regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC | MATRIX_SCFG_DEFMSTRTYPE_FIXED); putreg32(regval, SAM_MATRIX_SCFG3); #endif } diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index af0065d5514..2807714af49 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -4382,7 +4382,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) if (priv->attr->emac == EMAC0_INTF) { - /* Configure PIO pins common to RMII and MII mode*/ + /* Configure PIO pins common to RMII and MII mode */ sam_configgpio(GPIO_EMAC0_TXCK); /* Transmit Clock (or Reference Clock) */ sam_configgpio(GPIO_EMAC0_TXEN); /* Transmit Enable */ @@ -4395,7 +4395,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) sam_configgpio(GPIO_EMAC0_MDC); /* Management Data Clock */ sam_configgpio(GPIO_EMAC0_MDIO); /* Management Data Input/Output */ - /* Configure additional PIO pins to support EMAC in MII mode*/ + /* Configure additional PIO pins to support EMAC in MII mode */ if (!priv->attr->rmii) { @@ -4409,7 +4409,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) sam_configgpio(GPIO_EMAC0_COL); /* Collision Detect */ } } - else + else #endif #if defined(CONFIG_SAMV7_EMAC1) @@ -4417,7 +4417,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) if (priv->attr->emac == EMAC1_INTF) { - /* Configure PIO pins common to RMII and MII mode*/ + /* Configure PIO pins common to RMII and MII mode */ sam_configgpio(GPIO_EMAC1_TXCK); /* Transmit Clock (or Reference Clock) */ sam_configgpio(GPIO_EMAC1_TXEN); /* Transmit Enable */ @@ -4430,7 +4430,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv) sam_configgpio(GPIO_EMAC1_MDC); /* Management Data Clock */ sam_configgpio(GPIO_EMAC1_MDIO); /* Management Data Input/Output */ - /* Configure additional PIO pins to support EMAC in MII mode*/ + /* Configure additional PIO pins to support EMAC in MII mode */ if (!priv->attr->rmii) { diff --git a/arch/arm/src/samv7/sam_gpioirq.c b/arch/arm/src/samv7/sam_gpioirq.c index 9db13c088ee..d7e235c58b8 100644 --- a/arch/arm/src/samv7/sam_gpioirq.c +++ b/arch/arm/src/samv7/sam_gpioirq.c @@ -345,42 +345,42 @@ void sam_gpioirq(gpio_pinset_t pinset) uint32_t base = sam_gpiobase(pinset); int pin = sam_gpiopin(pinset); - /* Are any additional interrupt modes selected? */ + /* Are any additional interrupt modes selected? */ - if ((pinset & _GIO_INT_AIM) != 0) - { - /* Yes.. Enable additional interrupt mode */ + if ((pinset & _GIO_INT_AIM) != 0) + { + /* Yes.. Enable additional interrupt mode */ - putreg32(pin, base + SAM_PIO_AIMER_OFFSET); + putreg32(pin, base + SAM_PIO_AIMER_OFFSET); - /* Level or edge detected interrupt? */ + /* Level or edge detected interrupt? */ - if ((pinset & _GPIO_INT_LEVEL) != 0) - { - putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */ - } - else - { - putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */ - } + if ((pinset & _GPIO_INT_LEVEL) != 0) + { + putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */ + } + else + { + putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */ + } /* High level/rising edge or low level /falling edge? */ - if ((pinset & _GPIO_INT_RH) != 0) - { - putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */ - } - else - { - putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */ - } - } + if ((pinset & _GPIO_INT_RH) != 0) + { + putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */ + } + else + { + putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */ + } + } else - { - /* No.. Disable additional interrupt mode */ + { + /* No.. Disable additional interrupt mode */ - putreg32(pin, base + SAM_PIO_AIMDR_OFFSET); - } + putreg32(pin, base + SAM_PIO_AIMDR_OFFSET); + } } /************************************************************************************ diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index 713fc1c70b9..20db5da509b 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -63,7 +63,6 @@ #include "sam_gpio.h" #include "sam_xdmac.h" #include "sam_periphclks.h" -//#include "sam_memories.h" #include "sam_hsmci.h" #include "chip/sam_xdmac.h" #include "chip/sam_pmc.h" @@ -1475,13 +1474,13 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) { /* Yes.. Terminate with a timeout. */ - sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_TIMEOUT); + sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } else { /* No.. Terminate with an I/O error. */ - sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR); + sam_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } } @@ -1549,25 +1548,27 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) { /* Yes.. signal a timeout error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_TIMEOUT; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_TIMEOUT; } else { /* No.. signal some generic I/O error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_ERROR; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_ERROR; } } else - { + { /* The Command-Response sequence ended with no error */ - wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE; + wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE; } - /* Yes.. Is there a thread waiting for this event set? */ + /* Yes.. Is there a thread waiting for this event set? */ - wkupevent &= priv->waitevents; + wkupevent &= priv->waitevents; if (wkupevent != 0) { /* Yes.. wake the thread up */ @@ -1904,7 +1905,7 @@ static int sam_attach(FAR struct sdio_dev_s *dev) static int sam_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t regval; uint32_t cmdidx; @@ -2098,7 +2099,7 @@ static int sam_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Save the destination buffer information for use by the interrupt handler */ - priv->buffer = (uint32_t*)buffer; + priv->buffer = (uint32_t *)buffer; priv->remaining = buflen; /* And enable interrupts */ @@ -2203,7 +2204,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, static int sam_cancel(FAR struct sdio_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; /* Disable all transfer- and event- related interrupts */ @@ -2256,7 +2257,7 @@ static int sam_cancel(FAR struct sdio_dev_s *dev) static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t sr; uint32_t pending; int32_t timeout; @@ -2311,14 +2312,16 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* Yes.. return a timeout error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_TIMEOUT; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_TIMEOUT; return -ETIMEDOUT; } else { /* No.. return some generic I/O error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_ERROR; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE | + SDIOWAIT_ERROR; return -EIO; } } @@ -2326,7 +2329,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* The Command-Response sequence ended with no error */ - priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE; + priv->wkupevent = SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE; return OK; } } @@ -2366,7 +2369,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) static int sam_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; int ret = OK; /* These responses could have CRC errors: @@ -2450,9 +2453,10 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, return ret; } -static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]) +static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; int ret = OK; /* R2 CID, CSD register (136-bit) @@ -2510,7 +2514,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong static int sam_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; priv->wkupevent = 0; return -ENOSYS; } @@ -2553,7 +2557,7 @@ static int sam_recvnotimpl(FAR struct sdio_dev_s *dev, static void sam_waitenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; uint32_t waitmask; DEBUGASSERT(priv != NULL); @@ -2567,7 +2571,7 @@ static void sam_waitenable(FAR struct sdio_dev_s *dev, */ waitmask = 0; - if ((eventset & (SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE)) != 0) + if ((eventset & (SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE)) != 0) { waitmask |= priv->cmdrmask; } @@ -2612,7 +2616,7 @@ static void sam_waitenable(FAR struct sdio_dev_s *dev, static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; sdio_eventset_t wkupevent = 0; int ret; @@ -2727,7 +2731,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, static void sam_callbackenable(FAR struct sdio_dev_s *dev, sdio_eventset_t eventset) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; fvdbg("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); @@ -2761,7 +2765,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev, static int sam_registercallback(FAR struct sdio_dev_s *dev, worker_t callback, void *arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev; + struct sam_dev_s *priv = (struct sam_dev_s *)dev; /* Disable callbacks and register this callback and is argument */ @@ -3005,7 +3009,7 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev, static void sam_callback(void *arg) { - struct sam_dev_s *priv = (struct sam_dev_s*)arg; + struct sam_dev_s *priv = (struct sam_dev_s *)arg; irqstate_t flags; int ret; diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c index ec6fcee54e2..772a2b2550a 100644 --- a/arch/arm/src/samv7/sam_irq.c +++ b/arch/arm/src/samv7/sam_irq.c @@ -62,9 +62,9 @@ /* Get a 32-bit version of the default priority */ #define DEFPRIORITY32 \ - (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ - NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ NVIC_SYSH_PRIORITY_DEFAULT) /* Given the address of a NVIC ENABLE register, this is the offset to @@ -310,8 +310,8 @@ static int sam_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { - *regaddr = NVIC_SYSHCON; - if (irq == SAM_IRQ_MEMFAULT) + *regaddr = NVIC_SYSHCON; + if (irq == SAM_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index c64921301cd..5f729cbdb82 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -1189,10 +1189,10 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { if (priv->count == 0xffffffff || ++priv->count > 3) { - if (priv->count == 4) - { - lldbg("...\n"); - } + if (priv->count == 4) + { + lldbg("...\n"); + } return regval; } @@ -1440,7 +1440,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv) * be incremented and, hence, to be too low. */ - for(;;) + for (;;) { /* Get the current queue status and semaphore count. */ @@ -2716,7 +2716,7 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) /* Followed by the amount of data corresponding to the DLC (T2..) */ - dest = (FAR uint8_t*)&txbuffer[2]; + dest = (FAR uint8_t *)&txbuffer[2]; src = msg->cm_data; nbytes = mcan_dlc2bytes(priv, msg->cm_hdr.ch_dlc); diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index 6f542a97e70..352501a7d1f 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -750,7 +750,7 @@ static void sam_disableallints(struct sam_dev_s *priv, uint32_t *imr) static int sam_setup(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t divb3; uint32_t intpart; @@ -918,7 +918,7 @@ static int sam_setup(struct uart_dev_s *dev) static void sam_shutdown(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; /* Reset and disable receiver and transmitter */ @@ -947,7 +947,7 @@ static void sam_shutdown(struct uart_dev_s *dev) static int sam_attach(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -977,7 +977,7 @@ static int sam_attach(struct uart_dev_s *dev) static void sam_detach(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1002,7 +1002,7 @@ static int sam_interrupt(struct uart_dev_s *dev) bool handled; DEBUGASSERT(dev && dev->priv); - priv = (struct sam_dev_s*)dev->priv; + priv = (struct sam_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have * been looping for a long time. @@ -1134,7 +1134,7 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct sam_dev_s *user = (struct sam_dev_s*)arg; + struct sam_dev_s *user = (struct sam_dev_s *)arg; if (!user) { ret = -EINVAL; @@ -1326,7 +1326,7 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) static int sam_receive(struct uart_dev_s *dev, uint32_t *status) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; /* Return the error information in the saved status */ @@ -1348,7 +1348,7 @@ static int sam_receive(struct uart_dev_s *dev, uint32_t *status) static void sam_rxint(struct uart_dev_s *dev, bool enable) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; if (enable) { @@ -1376,7 +1376,7 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable) static bool sam_rxavailable(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; return ((sam_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_RXRDY) != 0); } @@ -1390,7 +1390,7 @@ static bool sam_rxavailable(struct uart_dev_s *dev) static void sam_send(struct uart_dev_s *dev, int ch) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; sam_serialout(priv, SAM_UART_THR_OFFSET, (uint32_t)ch); } @@ -1404,7 +1404,7 @@ static void sam_send(struct uart_dev_s *dev, int ch) static void sam_txint(struct uart_dev_s *dev, bool enable) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; irqstate_t flags; flags = irqsave(); @@ -1445,7 +1445,7 @@ static void sam_txint(struct uart_dev_s *dev, bool enable) static bool sam_txready(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; return ((sam_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXRDY) != 0); } @@ -1459,7 +1459,7 @@ static bool sam_txready(struct uart_dev_s *dev) static bool sam_txempty(struct uart_dev_s *dev) { - struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; return ((sam_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0); } diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 78e1c475224..7ab71ec3c42 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -1287,8 +1287,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, if (spics->nbits > 8) { - rxptr16 = (uint16_t*)rxbuffer; - txptr16 = (uint16_t*)txbuffer; + rxptr16 = (uint16_t *)rxbuffer; + txptr16 = (uint16_t *)txbuffer; rxptr8 = NULL; txptr8 = NULL; } @@ -1296,8 +1296,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, { rxptr16 = NULL; txptr16 = NULL; - rxptr8 = (uint8_t*)rxbuffer; - txptr8 = (uint8_t*)txbuffer; + rxptr8 = (uint8_t *)rxbuffer; + txptr8 = (uint8_t *)txbuffer; } /* Make sure that any previous transfer is flushed from the hardware */ @@ -1332,7 +1332,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, * Save the final word. */ - for ( ; nwords > 0; nwords--) + for (; nwords > 0; nwords--) { /* Get the data to send (0xff if there is no data source). */ diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index f3381b007a5..fb9fed17733 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -65,7 +65,6 @@ #include "sam_gpio.h" #include "sam_xdmac.h" -//#include "sam_memories.h" #include "sam_periphclks.h" #include "sam_ssc.h" #include "chip/sam_pmc.h" @@ -339,7 +338,7 @@ DMACH_FLAG_PERIPHISPERIPH | DMACH_FLAG_PERIPHWIDTH_8BITS | \ DMACH_FLAG_PERIPHCHUNKSIZE_1 | DMACH_FLAG_MEMPID_MAX | \ DMACH_FLAG_MEM_IF | DMACH_FLAG_MEMWIDTH_16BITS | \ - DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_1| \ + DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_1 | \ DMACH_FLAG_MEMBURST_4) #define DMA16_FLAGS \ diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index 9e7ebaa5f52..c587db5e750 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -62,8 +62,7 @@ * Pre-processor Definitions ****************************************************************************/ /* Memory Map ***************************************************************/ -/* - * 0x0400:0000 - Beginning of the internal FLASH. Address of vectors. +/* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors. * Mapped as boot memory address 0x0000:0000 at reset. * 0x041f:ffff - End of flash region (assuming the max of 2MiB of FLASH). * 0x2000:0000 - Start of internal SRAM and start of .data (_sdata) diff --git a/arch/arm/src/samv7/sam_timerisr.c b/arch/arm/src/samv7/sam_timerisr.c index 4bf1d95c7a2..9e167aeae70 100644 --- a/arch/arm/src/samv7/sam_timerisr.c +++ b/arch/arm/src/samv7/sam_timerisr.c @@ -108,10 +108,10 @@ int up_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + /* Process timer interrupt */ - sched_process_timer(); - return 0; + sched_process_timer(); + return 0; } /**************************************************************************** diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index 9b6957767ef..ef6d8d1669a 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -647,7 +647,7 @@ static int twi_interrupt(struct twi_dev_s *priv) } } - /* Byte sent*/ + /* Byte sent */ else if ((pending & TWIHS_INT_TXRDY) != 0) { @@ -795,7 +795,7 @@ static void twi_startread(struct twi_dev_s *priv, struct i2c_msg_s *msg) priv->result = -EBUSY; priv->xfrd = 0; - /* Set STOP signal if only one byte is sent*/ + /* Set STOP signal if only one byte is sent */ if (msg->length == 1) { @@ -842,7 +842,7 @@ static void twi_startwrite(struct twi_dev_s *priv, struct i2c_msg_s *msg) twi_putrel(priv, SAM_TWIHS_IADR_OFFSET, 0); - /* Write first byte to send.*/ + /* Write first byte to send. */ twi_putrel(priv, SAM_TWIHS_THR_OFFSET, msg->buffer[priv->xfrd++]); diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index ac95a437950..e1fe56298d8 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -3717,7 +3717,7 @@ static struct usbdev_req_s *sam_ep_allocreq(struct usbdev_ep_s *ep) static void sam_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct sam_req_s *privreq = (struct sam_req_s*)req; + struct sam_req_s *privreq = (struct sam_req_s *)req; DEBUGASSERT(ep != NULL && req != NULL); usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog)); @@ -4555,7 +4555,7 @@ static void sam_hw_setup(struct sam_usbdev_s *priv) /* Clear endpoint status */ sam_putreg(USBHS_DEVEPTICR_ALLINTS, SAM_USBHS_DEVEPTICR(i)); - } + } /* Disable all interrupts */