Merged imxrt1020 into master

2026-05-20 12:33:27 +08:00 · 2019-04-30 16:08:46 -06:00
parent 7f74947c93
commit 3e848fb893
57 changed files with 14005 additions and 1737 deletions
@@ -1,4 +1,4 @@
-/************************************************************************************
+/*****************************************************************************
 * arch/arm/include/imxrt/chip.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -32,27 +32,42 @@
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
- ************************************************************************************/
+ *****************************************************************************/

 #ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
 #define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H

-/************************************************************************************
+/*****************************************************************************
 * Included Files
- ************************************************************************************/
+ *****************************************************************************/

 #include <nuttx/config.h>

-/************************************************************************************
+/*****************************************************************************
 * Pre-processor Definitions
- ************************************************************************************/
+ *****************************************************************************/

 /* Get customizations for each supported chip */

-#if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
+#if defined(CONFIG_ARCH_CHIP_MIMXRT1021CAG4A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1021CAF4A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1021DAF5A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1021DAG5A)
+
+/*  MIMXRT1021CAG4A - 144 pin, 400MHz Industrial
+ *  MIMXRT1021CAF4A - 100 pin, 400MHz Industrial
+ *  MIMXRT1021DAF5A - 100 pin, 500MHz Consumer
+ *  MIMXRT1021DAG5A - 144 pin, 500MHz Consumer
+ */
+
+#  define IMXRT_OCRAM_SIZE      (256 * 1024) /* 256Kb OCRAM */
+#  define IMXRT_GPIO_NPORTS     5            /* Five total ports */
+                                             /* but 4 doesn't exist */
+
+#elif defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
 /* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
 * MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz
 * MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
@@ -63,9 +78,9 @@
 #  define IMXRT_GPIO_NPORTS            5           /* Five total ports */

 #elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A)
+      defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A)
 /* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz
 * MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz
 * MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz
@@ -78,27 +93,28 @@
 #  error "Unknown i.MX RT chip type"
 #endif

-/* NVIC priority levels *************************************************************/
-/* Each priority field holds an 8-bit priority value, 0-15. The lower the value, the
- * greater the priority of the corresponding interrupt.  The i.MX RT processor
- * implements only  bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
+/* NVIC priority levels ******************************************************
+/* Each priority field holds an 8-bit priority value, 0-15. The lower the
+ * value, the greater the priority of the corresponding interrupt.  The i.MX
+ * RT processor implements only bits[7:4] of each field, bits[3:0] read as
+ * zero and ignore writes.
 */

-#define NVIC_SYSH_PRIORITY_MIN        0xf0 /* All bits[7:4] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_MIN        0xf0 /* All bits[7:4] set is min pri */
 #define NVIC_SYSH_PRIORITY_DEFAULT    0x80 /* Midpoint is the default */
 #define NVIC_SYSH_PRIORITY_MAX        0x00 /* Zero is maximum priority */
-#define NVIC_SYSH_PRIORITY_STEP       0x40 /* Two bits of interrupt priority used */
+#define NVIC_SYSH_PRIORITY_STEP       0x40 /* Two bits of interrupt pri used */

-/************************************************************************************
+/*****************************************************************************
 * Public Types
- ************************************************************************************/
+ *****************************************************************************/

-/************************************************************************************
+/*****************************************************************************
 * Public Data
- ************************************************************************************/
+ *****************************************************************************/

-/************************************************************************************
+/*****************************************************************************
 * Public Functions
- ************************************************************************************/
+ *****************************************************************************/

 #endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */
@@ -0,0 +1,469 @@
+/****************************************************************************************
+ * arch/arm/include/imxrt/imxrt105x_irq.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Dave Marples <dave@marples.net>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through
+ * nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H
+#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* External interrupts (priority levels >= 256) *****************************************/
+
+#define IMXRT_IRQ_EDMA0_16     (IMXRT_IRQ_EXTINT + 0)   /* eDMA Channel 0/16 Transfer Complete */
+#define IMXRT_IRQ_EDMA1_17     (IMXRT_IRQ_EXTINT + 1)   /* eDMA Channel 1/17 Transfer Complete */
+#define IMXRT_IRQ_EDMA2_18     (IMXRT_IRQ_EXTINT + 2)   /* eDMA Channel 2/18 Transfer Complete */
+#define IMXRT_IRQ_EDMA3_19     (IMXRT_IRQ_EXTINT + 3)   /* eDMA Channel 3/19 Transfer Complete */
+#define IMXRT_IRQ_EDMA4_20     (IMXRT_IRQ_EXTINT + 4)   /* eDMA Channel 4/20 Transfer Complete */
+#define IMXRT_IRQ_EDMA5_21     (IMXRT_IRQ_EXTINT + 5)   /* eDMA Channel 5/21 Transfer Complete */
+#define IMXRT_IRQ_EDMA6_22     (IMXRT_IRQ_EXTINT + 6)   /* eDMA Channel 6/22 Transfer Complete */
+#define IMXRT_IRQ_EDMA7_23     (IMXRT_IRQ_EXTINT + 7)   /* eDMA Channel 7/23 Transfer Complete */
+#define IMXRT_IRQ_EDMA8_24     (IMXRT_IRQ_EXTINT + 8)   /* eDMA Channel 8/24 Transfer Complete */
+#define IMXRT_IRQ_EDMA9_25     (IMXRT_IRQ_EXTINT + 9)   /* eDMA Channel 9/25 Transfer Complete */
+#define IMXRT_IRQ_EDMA10_26    (IMXRT_IRQ_EXTINT + 10)  /* eDMA Channel 10/26 Transfer Complete */
+#define IMXRT_IRQ_EDMA11_27    (IMXRT_IRQ_EXTINT + 11)  /* eDMA Channel 11/27 Transfer Complete */
+#define IMXRT_IRQ_EDMA12_28    (IMXRT_IRQ_EXTINT + 12)  /* eDMA Channel 12/28 Transfer Complete */
+#define IMXRT_IRQ_EDMA13_29    (IMXRT_IRQ_EXTINT + 13)  /* eDMA Channel 13/29 Transfer Complete */
+#define IMXRT_IRQ_EDMA14_30    (IMXRT_IRQ_EXTINT + 14)  /* eDMA Channel 14/30 Transfer Complete */
+#define IMXRT_IRQ_EDMA15_31    (IMXRT_IRQ_EXTINT + 15)  /* eDMA Channel 15/31 Transfer Complete */
+#define IMXRT_IRQ_EDMA_ERROR   (IMXRT_IRQ_EXTINT + 16)  /* Error Interrupt, Channels 0-15 / 16-31 */
+#define IMXRT_IRQ_CM70         (IMXRT_IRQ_EXTINT + 17)  /* CTI trigger outputs (internal: CTIIRQ[0]) */
+#define IMXRT_IRQ_CM71         (IMXRT_IRQ_EXTINT + 18)  /* CTI trigger outputs (internal: CTIIRQ[1]) */
+#define IMXRT_IRQ_CM7CP        (IMXRT_IRQ_EXTINT + 19)  /* CorePlatform exception IRQ */
+#define IMXRT_IRQ_LPUART1      (IMXRT_IRQ_EXTINT + 20)  /* UART1 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART2      (IMXRT_IRQ_EXTINT + 21)  /* UART2 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART3      (IMXRT_IRQ_EXTINT + 22)  /* UART3 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART4      (IMXRT_IRQ_EXTINT + 23)  /* UART4 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART5      (IMXRT_IRQ_EXTINT + 24)  /* UART5 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART6      (IMXRT_IRQ_EXTINT + 25)  /* UART6 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART7      (IMXRT_IRQ_EXTINT + 26)  /* UART7 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART8      (IMXRT_IRQ_EXTINT + 27)  /* UART8 TX/RX interrupt */
+#define IMXRT_IRQ_LPI2C1       (IMXRT_IRQ_EXTINT + 28)  /* I2C1 Interrupt */
+#define IMXRT_IRQ_LPI2C2       (IMXRT_IRQ_EXTINT + 29)  /* I2C2 Interrupt */
+#define IMXRT_IRQ_LPI2C3       (IMXRT_IRQ_EXTINT + 30)  /* I2C3 Interrupt */
+#define IMXRT_IRQ_LPI2C4       (IMXRT_IRQ_EXTINT + 31)  /* I2C4 Interrupt */
+#define IMXRT_IRQ_LPSPI1       (IMXRT_IRQ_EXTINT + 32)  /* LPSPI1 interrupt */
+#define IMXRT_IRQ_LPSPI2       (IMXRT_IRQ_EXTINT + 33)  /* LPSPI2 interrupt */
+#define IMXRT_IRQ_LPSPI3       (IMXRT_IRQ_EXTINT + 34)  /* LPSPI3 interrupt */
+#define IMXRT_IRQ_LPSPI4       (IMXRT_IRQ_EXTINT + 35)  /* LPSPI4 interrupt */
+#define IMXRT_IRQ_CAN1         (IMXRT_IRQ_EXTINT + 36)  /* CAN1 interrupt */
+#define IMXRT_IRQ_CAN2         (IMXRT_IRQ_EXTINT + 37)  /* CAN2 interrupt */
+#define IMXRT_IRQ_CM7FR        (IMXRT_IRQ_EXTINT + 38)  /* FlexRAM address fault */
+#define IMXRT_IRQ_KPP          (IMXRT_IRQ_EXTINT + 39)  /* Keypad Interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 40)  RESERVED */
+#define IMXRT_IRQ_GPRIRQ       (IMXRT_IRQ_EXTINT + 41)  /* Notify cores on exception while boot */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 42)  RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 43)  RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 44)  RESERVED */
+#define IMXRT_IRQ_WDOG2        (IMXRT_IRQ_EXTINT + 45)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_SNVS         (IMXRT_IRQ_EXTINT + 46)  /* SNVS Functional Interrupt */
+#define IMXRT_IRQ_SNVSSEC      (IMXRT_IRQ_EXTINT + 47)  /* SNVS Security Interrupt */
+#define IMXRT_IRQ_SNVSSB       (IMXRT_IRQ_EXTINT + 48)  /* ON-OFF short button press */
+#define IMXRT_IRQ_CSU          (IMXRT_IRQ_EXTINT + 49)  /* CSU Interrupt Request 1 */
+#define IMXRT_IRQ_DCP          (IMXRT_IRQ_EXTINT + 50)  /* DCP channel/CRC interrupts (channel != 0) */
+#define IMXRT_IRQ_DCP0         (IMXRT_IRQ_EXTINT + 51)  /* DCP channel 0 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 52)  RESERVED */
+#define IMXRT_IRQ_TRNG         (IMXRT_IRQ_EXTINT + 53)  /* TRNG Interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 54)  RESERVED */
+#define IMXRT_IRQ_BEE          (IMXRT_IRQ_EXTINT + 55)  /* BEE IRQ */
+#define IMXRT_IRQ_SAI1         (IMXRT_IRQ_EXTINT + 56)  /* SAI1 interrupt (RX/TX) */
+#define IMXRT_IRQ_SAI2         (IMXRT_IRQ_EXTINT + 57)  /* SAI2 interrupt (RX/TX) */
+#define IMXRT_IRQ_SAI3RX       (IMXRT_IRQ_EXTINT + 58)  /* SAI3 RX interrupt (RX/TX) */
+#define IMXRT_IRQ_SAI3TX       (IMXRT_IRQ_EXTINT + 59)  /* SAI3 TX interrupt (RX/TX) */
+#define IMXRT_IRQ_SPDIF        (IMXRT_IRQ_EXTINT + 60)  /* SPDIF interrupt */
+#define IMXRT_IRQ_PMU          (IMXRT_IRQ_EXTINT + 61)  /* Brown-out event 1.1, 2.5 or 3.0 regulators */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 62)  RESERVED */
+#define IMXRT_IRQ_TEMP         (IMXRT_IRQ_EXTINT + 63)  /* Temperature Monitor */
+#define IMXRT_IRQ_TEMPPANIC    (IMXRT_IRQ_EXTINT + 64)  /* TempSensor panic */
+#define IMXRT_IRQ_USBPHY0      (IMXRT_IRQ_EXTINT + 65)  /* USBPHY (UTMI0) interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 66)  RESERVED */
+#define IMXRT_IRQ_ADC1         (IMXRT_IRQ_EXTINT + 67)  /* ADC1 interrupt */
+#define IMXRT_IRQ_ADC2         (IMXRT_IRQ_EXTINT + 68)  /* ADC2 interrupt */
+#define IMXRT_IRQ_DCDC         (IMXRT_IRQ_EXTINT + 69)  /* DCDC interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 70)  RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 71)  RESERVED */
+#define IMXRT_IRQ_GPIO1_0      (IMXRT_IRQ_EXTINT + 72)  /* GPIO1 INT0 interrupt */
+#define IMXRT_IRQ_GPIO1_1      (IMXRT_IRQ_EXTINT + 73)  /* GPIO1 INT1 interrupt */
+#define IMXRT_IRQ_GPIO1_2      (IMXRT_IRQ_EXTINT + 74)  /* GPIO1 INT2 interrupt */
+#define IMXRT_IRQ_GPIO1_3      (IMXRT_IRQ_EXTINT + 75)  /* GPIO1 INT3 interrupt */
+#define IMXRT_IRQ_GPIO1_4      (IMXRT_IRQ_EXTINT + 76)  /* GPIO1 INT4 interrupt */
+#define IMXRT_IRQ_GPIO1_5      (IMXRT_IRQ_EXTINT + 77)  /* GPIO1 INT5 interrupt */
+#define IMXRT_IRQ_GPIO1_6      (IMXRT_IRQ_EXTINT + 78)  /* GPIO1 INT6 interrupt */
+#define IMXRT_IRQ_GPIO1_7      (IMXRT_IRQ_EXTINT + 79)  /* GPIO1 INT7 interrupt */
+#define IMXRT_IRQ_GPIO1_0_15   (IMXRT_IRQ_EXTINT + 80)  /* GPIO1 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO1_16_31  (IMXRT_IRQ_EXTINT + 81)  /* GPIO1 INT16-31 interrupt */
+#define IMXRT_IRQ_GPIO2_0_15   (IMXRT_IRQ_EXTINT + 82)  /* GPIO2 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO2_16_31  (IMXRT_IRQ_EXTINT + 83)  /* GPIO2 INT16-31 interrupt */
+#define IMXRT_IRQ_GPIO3_0_15   (IMXRT_IRQ_EXTINT + 84)  /* GPIO3 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO3_16_31  (IMXRT_IRQ_EXTINT + 85)  /* GPIO3 INT16-31 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 86)  RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 87)  RESERVED */
+#define IMXRT_IRQ_GPIO5_0_15   (IMXRT_IRQ_EXTINT + 88)  /* GPIO5 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO5_16_31  (IMXRT_IRQ_EXTINT + 89)  /* GPIO5 INT16-31 interrupt */
+#define IMXRT_IRQ_FLEXIO1      (IMXRT_IRQ_EXTINT + 90)  /* FlexIO Interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 91)  RESERVED */
+#define IMXRT_IRQ_WDOG1        (IMXRT_IRQ_EXTINT + 92)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_RTWDOG       (IMXRT_IRQ_EXTINT + 93)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_EWM          (IMXRT_IRQ_EXTINT + 94)  /* EWM interrupt */
+#define IMXRT_IRQ_CCM_1        (IMXRT_IRQ_EXTINT + 95)  /* CCM interrupt 1 */
+#define IMXRT_IRQ_CCM_2        (IMXRT_IRQ_EXTINT + 96)  /* CCM interrupt 2 */
+#define IMXRT_IRQ_GPC          (IMXRT_IRQ_EXTINT + 97)  /* GPC interrupt 1 */
+#define IMXRT_IRQ_SRC          (IMXRT_IRQ_EXTINT + 98)  /* SRC interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 99)  RESERVED */
+#define IMXRT_IRQ_GPT1         (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */
+#define IMXRT_IRQ_GPT2         (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_0   (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_1   (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_2   (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_3   (IMXRT_IRQ_EXTINT + 105) /* FLEXPWM1 capture/compare/reload 3 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_F   (IMXRT_IRQ_EXTINT + 106) /* FLEXPWM1 fault interrupt OR reload error */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 107) RESERVED */
+#define IMXRT_IRQ_FLEXSPI      (IMXRT_IRQ_EXTINT + 108) /* FlexSPI interrupt */
+#define IMXRT_IRQ_SEMC         (IMXRT_IRQ_EXTINT + 109) /* SEMC interrupt */
+#define IMXRT_IRQ_USDHC1       (IMXRT_IRQ_EXTINT + 110) /* USDHC1 interrupt */
+#define IMXRT_IRQ_USDHC2       (IMXRT_IRQ_EXTINT + 111) /* USDHC2 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 112) RESERVED */
+#define IMXRT_IRQ_USBOTG1      (IMXRT_IRQ_EXTINT + 113) /* USBO2 USB OTG1 interrupt */
+#define IMXRT_IRQ_ENET         (IMXRT_IRQ_EXTINT + 114) /* ENET MAC 0 interrupt */
+#define IMXRT_IRQ_ENET1588     (IMXRT_IRQ_EXTINT + 115) /* ENET MAC 0 1588 Timer Interrupt */
+#define IMXRT_IRQ_XBAR1_0_1    (IMXRT_IRQ_EXTINT + 116) /* XBAR1 interrupt 0/1 */
+#define IMXRT_IRQ_XBAR1_2_3    (IMXRT_IRQ_EXTINT + 117) /* XBAR1 interrupt 2/3 */
+#define IMXRT_IRQ_ADCETC_0     (IMXRT_IRQ_EXTINT + 118) /* ADC_ETC interrupt 0 */
+#define IMXRT_IRQ_ADCETC_1     (IMXRT_IRQ_EXTINT + 119) /* ADC_ETC interrupt 1 */
+#define IMXRT_IRQ_ADCETC_2     (IMXRT_IRQ_EXTINT + 120) /* ADC_ETC interrupt 2 */
+#define IMXRT_IRQ_ADCETC_ERR   (IMXRT_IRQ_EXTINT + 121) /* ADC_ETC error interrupt */
+#define IMXRT_IRQ_PIT          (IMXRT_IRQ_EXTINT + 122) /* PIT interrupt */
+#define IMXRT_IRQ_ACMP1        (IMXRT_IRQ_EXTINT + 123) /* ACMP1 interrupt */
+#define IMXRT_IRQ_ACMP2        (IMXRT_IRQ_EXTINT + 124) /* ACMP2 interrupt */
+#define IMXRT_IRQ_ACMP3        (IMXRT_IRQ_EXTINT + 125) /* ACMP3 interrupt */
+#define IMXRT_IRQ_ACMP4        (IMXRT_IRQ_EXTINT + 126) /* ACMP4 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 127) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 128) RESERVED */
+#define IMXRT_IRQ_ENC1         (IMXRT_IRQ_EXTINT + 129) /* ENC1 interrupt */
+#define IMXRT_IRQ_ENC2         (IMXRT_IRQ_EXTINT + 130) /* ENC2 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 131) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 132) RESERVED */
+#define IMXRT_IRQ_QTIMER1      (IMXRT_IRQ_EXTINT + 133) /* QTIMER1 timer 0-3 interrupt */
+#define IMXRT_IRQ_QTIMER2      (IMXRT_IRQ_EXTINT + 134) /* QTIMER2 timer 0-3 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 135) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 136) RESERVED */
+#define IMXRT_IRQ_FLEXPWM2_0   (IMXRT_IRQ_EXTINT + 137) /* FLEXPWM2 capture/compare/reload 0 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_1   (IMXRT_IRQ_EXTINT + 138) /* FLEXPWM2 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_2   (IMXRT_IRQ_EXTINT + 139) /* FLEXPWM2 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_3   (IMXRT_IRQ_EXTINT + 140) /* FLEXPWM2 capture/compare/reload 3 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_F   (IMXRT_IRQ_EXTINT + 141) /* FLEXPWM2 fault interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 142) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 143) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 144) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 146) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 147) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 148) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 149) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 150) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 151) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 152) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 153) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 154) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 155) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 156) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 157) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 158) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 159) RESERVED */
+
+#define IMXRT_IRQ_NEXTINT      160
+
+/* GPIO second level interrupt **********************************************************/
+
+#define IMXRT_GPIO_IRQ_FIRST   (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT)
+#define _IMXRT_GPIO1_0_15_BASE IMXRT_GPIO_IRQ_FIRST
+
+#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
+  /* GPIO1 has dedicated interrupts for pins 0-7
+   * REVISIT:  I am assuming that you really cannot use the dedicated and the multiplex
+   * interrupts concurrently.
+   */
+
+#  define IMXRT_IRQ_GPIO1_0    (_IMXRT_GPIO1_0_15_BASE + 0)   /* GPIO1 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO1_1    (_IMXRT_GPIO1_0_15_BASE + 1)   /* GPIO1 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO1_2    (_IMXRT_GPIO1_0_15_BASE + 2)   /* GPIO1 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO1_3    (_IMXRT_GPIO1_0_15_BASE + 3)   /* GPIO1 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO1_4    (_IMXRT_GPIO1_0_15_BASE + 4)   /* GPIO1 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO1_5    (_IMXRT_GPIO1_0_15_BASE + 5)   /* GPIO1 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO1_6    (_IMXRT_GPIO1_0_15_BASE + 6)   /* GPIO1 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO1_7    (_IMXRT_GPIO1_0_15_BASE + 7)   /* GPIO1 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO1_8    (_IMXRT_GPIO1_0_15_BASE + 8)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_9    (_IMXRT_GPIO1_0_15_BASE + 9)   /* GPIO1 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO1_10   (_IMXRT_GPIO1_0_15_BASE + 10)  /* GPIO1 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO1_11   (_IMXRT_GPIO1_0_15_BASE + 11)  /* GPIO1 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO1_12   (_IMXRT_GPIO1_0_15_BASE + 12)  /* GPIO1 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO1_13   (_IMXRT_GPIO1_0_15_BASE + 13)  /* GPIO1 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO1_14   (_IMXRT_GPIO1_0_15_BASE + 14)  /* GPIO1 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO1_15   (_IMXRT_GPIO1_0_15_BASE + 15)  /* GPIO1 pin 15 interrupt */
+
+#  define _IMXRT_GPIO1_8_15_NIRQS 16
+#  define _IMXRT_GPIO1_16_31_BASE (_IMXRT_GPIO1_0_15_BASE + _IMXRT_GPIO1_8_15_NIRQS)
+#else
+#  define _IMXRT_GPIO1_8_15_NIRQS 0
+#  define _IMXRT_GPIO1_16_31_BASE _IMXRT_GPIO1_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ
+#  define IMXRT_IRQ_GPIO1_16   (_IMXRT_GPIO1_16_31_BASE + 0)  /* GPIO1 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO1_17   (_IMXRT_GPIO1_16_31_BASE + 1)  /* GPIO1 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO1_18   (_IMXRT_GPIO1_16_31_BASE + 2)  /* GPIO1 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO1_19   (_IMXRT_GPIO1_16_31_BASE + 3)  /* GPIO1 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO1_20   (_IMXRT_GPIO1_16_31_BASE + 4)  /* GPIO1 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO1_21   (_IMXRT_GPIO1_16_31_BASE + 5)  /* GPIO1 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO1_22   (_IMXRT_GPIO1_16_31_BASE + 6)  /* GPIO1 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO1_23   (_IMXRT_GPIO1_16_31_BASE + 7)  /* GPIO1 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO1_24   (_IMXRT_GPIO1_16_31_BASE + 8)  /* GPIO1 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO1_25   (_IMXRT_GPIO1_16_31_BASE + 9)  /* GPIO1 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO1_26   (_IMXRT_GPIO1_16_31_BASE + 10) /* GPIO1 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO1_27   (_IMXRT_GPIO1_16_31_BASE + 11) /* GPIO1 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO1_28   (_IMXRT_GPIO1_16_31_BASE + 12) /* GPIO1 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO1_29   (_IMXRT_GPIO1_16_31_BASE + 13) /* GPIO1 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO1_30   (_IMXRT_GPIO1_16_31_BASE + 14) /* GPIO1 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO1_31   (_IMXRT_GPIO1_16_31_BASE + 15) /* GPIO1 pin 31 interrupt */
+
+#  define _IMXRT_GPIO1_16_31_NIRQS 16
+#  define _IMXRT_GPIO2_0_15_BASE (_IMXRT_GPIO1_16_31_BASE + _IMXRT_GPIO1_16_31_NIRQS)
+#  define IMXRT_GPIO1_NIRQS    (_IMXRT_GPIO1_8_15_NIRQS + _IMXRT_GPIO1_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO2_0_15_BASE _IMXRT_GPIO1_16_31_BASE
+#  define IMXRT_GPIO1_NIRQS    _IMXRT_GPIO1_8_15_NIRQS
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ
+#  define IMXRT_IRQ_GPIO2_0    (_IMXRT_GPIO2_0_15_BASE + 0)   /* GPIO2 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO2_1    (_IMXRT_GPIO2_0_15_BASE + 1)   /* GPIO2 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO2_2    (_IMXRT_GPIO2_0_15_BASE + 2)   /* GPIO2 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO2_3    (_IMXRT_GPIO2_0_15_BASE + 3)   /* GPIO2 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO2_4    (_IMXRT_GPIO2_0_15_BASE + 4)   /* GPIO2 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO2_5    (_IMXRT_GPIO2_0_15_BASE + 5)   /* GPIO2 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO2_6    (_IMXRT_GPIO2_0_15_BASE + 6)   /* GPIO2 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO2_7    (_IMXRT_GPIO2_0_15_BASE + 7)   /* GPIO2 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO2_8    (_IMXRT_GPIO2_0_15_BASE + 8)   /* GPIO2 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO2_9    (_IMXRT_GPIO2_0_15_BASE + 9)   /* GPIO2 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO2_10   (_IMXRT_GPIO2_0_15_BASE + 10)  /* GPIO2 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO2_11   (_IMXRT_GPIO2_0_15_BASE + 11)  /* GPIO2 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO2_12   (_IMXRT_GPIO2_0_15_BASE + 12)  /* GPIO2 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO2_13   (_IMXRT_GPIO2_0_15_BASE + 13)  /* GPIO2 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO2_14   (_IMXRT_GPIO2_0_15_BASE + 14)  /* GPIO2 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO2_15   (_IMXRT_GPIO2_0_15_BASE + 15)  /* GPIO2 pin 15 interrupt */
+
+#  define _IMXRT_GPIO2_0_15_NIRQS 16
+#  define _IMXRT_GPIO2_16_31_BASE (_IMXRT_GPIO2_0_15_BASE + _IMXRT_GPIO2_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO2_0_15_NIRQS 0
+#  define _IMXRT_GPIO2_16_31_BASE _IMXRT_GPIO2_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ
+#  define IMXRT_IRQ_GPIO2_16   (_IMXRT_GPIO2_16_31_BASE + 0)  /* GPIO2 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO2_17   (_IMXRT_GPIO2_16_31_BASE + 1)  /* GPIO2 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO2_18   (_IMXRT_GPIO2_16_31_BASE + 2)  /* GPIO2 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO2_19   (_IMXRT_GPIO2_16_31_BASE + 3)  /* GPIO2 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO2_20   (_IMXRT_GPIO2_16_31_BASE + 4)  /* GPIO2 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO2_21   (_IMXRT_GPIO2_16_31_BASE + 5)  /* GPIO2 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO2_22   (_IMXRT_GPIO2_16_31_BASE + 6)  /* GPIO2 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO2_23   (_IMXRT_GPIO2_16_31_BASE + 7)  /* GPIO2 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO2_24   (_IMXRT_GPIO2_16_31_BASE + 8)  /* GPIO2 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO2_25   (_IMXRT_GPIO2_16_31_BASE + 9)  /* GPIO2 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO2_26   (_IMXRT_GPIO2_16_31_BASE + 10) /* GPIO2 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO2_27   (_IMXRT_GPIO2_16_31_BASE + 11) /* GPIO2 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO2_28   (_IMXRT_GPIO2_16_31_BASE + 12) /* GPIO2 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO2_29   (_IMXRT_GPIO2_16_31_BASE + 13) /* GPIO2 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO2_30   (_IMXRT_GPIO2_16_31_BASE + 14) /* GPIO2 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO2_31   (_IMXRT_GPIO2_16_31_BASE + 15) /* GPIO2 pin 31 interrupt */
+
+#  define _IMXRT_GPIO2_16_31_NIRQS 16
+#  define _IMXRT_GPIO3_0_15_BASE (_IMXRT_GPIO2_16_31_BASE + _IMXRT_GPIO2_16_31_NIRQS)
+#  define IMXRT_GPIO2_NIRQS    (_IMXRT_GPIO2_0_15_NIRQS + _IMXRT_GPIO2_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO3_0_15_BASE _IMXRT_GPIO2_16_31_BASE
+#  define IMXRT_GPIO2_NIRQS    _IMXRT_GPIO2_0_15_NIRQS
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ
+#  define IMXRT_IRQ_GPIO3_0    (_IMXRT_GPIO3_0_15_BASE + 0)   /* GPIO3 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO3_1    (_IMXRT_GPIO3_0_15_BASE + 1)   /* GPIO3 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO3_2    (_IMXRT_GPIO3_0_15_BASE + 2)   /* GPIO3 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO3_3    (_IMXRT_GPIO3_0_15_BASE + 3)   /* GPIO3 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO3_4    (_IMXRT_GPIO3_0_15_BASE + 4)   /* GPIO3 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO3_5    (_IMXRT_GPIO3_0_15_BASE + 5)   /* GPIO3 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO3_6    (_IMXRT_GPIO3_0_15_BASE + 6)   /* GPIO3 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO3_7    (_IMXRT_GPIO3_0_15_BASE + 7)   /* GPIO3 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO3_8    (_IMXRT_GPIO3_0_15_BASE + 8)   /* GPIO3 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO3_9    (_IMXRT_GPIO3_0_15_BASE + 9)   /* GPIO3 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO3_10   (_IMXRT_GPIO3_0_15_BASE + 10)  /* GPIO3 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO3_11   (_IMXRT_GPIO3_0_15_BASE + 11)  /* GPIO3 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO3_12   (_IMXRT_GPIO3_0_15_BASE + 12)  /* GPIO3 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO3_13   (_IMXRT_GPIO3_0_15_BASE + 13)  /* GPIO3 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO3_14   (_IMXRT_GPIO3_0_15_BASE + 14)  /* GPIO3 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO3_15   (_IMXRT_GPIO3_0_15_BASE + 15)  /* GPIO3 pin 15 interrupt */
+
+#  define _IMXRT_GPIO3_0_15_NIRQS 16
+#  define _IMXRT_GPIO3_16_31_BASE (_IMXRT_GPIO3_0_15_BASE + _IMXRT_GPIO3_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO3_0_15_NIRQS 0
+#  define _IMXRT_GPIO3_16_31_BASE _IMXRT_GPIO3_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ
+#  define IMXRT_IRQ_GPIO3_16   (_IMXRT_GPIO3_16_31_BASE + 0)  /* GPIO3 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO3_17   (_IMXRT_GPIO3_16_31_BASE + 1)  /* GPIO3 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO3_18   (_IMXRT_GPIO3_16_31_BASE + 2)  /* GPIO3 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO3_19   (_IMXRT_GPIO3_16_31_BASE + 3)  /* GPIO3 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO3_20   (_IMXRT_GPIO3_16_31_BASE + 4)  /* GPIO3 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO3_21   (_IMXRT_GPIO3_16_31_BASE + 5)  /* GPIO3 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO3_22   (_IMXRT_GPIO3_16_31_BASE + 6)  /* GPIO3 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO3_23   (_IMXRT_GPIO3_16_31_BASE + 7)  /* GPIO3 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO3_24   (_IMXRT_GPIO3_16_31_BASE + 8)  /* GPIO3 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO3_25   (_IMXRT_GPIO3_16_31_BASE + 9)  /* GPIO3 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO3_26   (_IMXRT_GPIO3_16_31_BASE + 10) /* GPIO3 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO3_27   (_IMXRT_GPIO3_16_31_BASE + 11) /* GPIO3 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO3_28   (_IMXRT_GPIO3_16_31_BASE + 12) /* GPIO3 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO3_29   (_IMXRT_GPIO3_16_31_BASE + 13) /* GPIO3 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO3_30   (_IMXRT_GPIO3_16_31_BASE + 14) /* GPIO3 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO3_31   (_IMXRT_GPIO3_16_31_BASE + 15) /* GPIO3 pin 31 interrupt */
+
+#  define _IMXRT_GPIO3_16_31_NIRQS 16
+#  define _IMXRT_GPIO5_0_15_BASE (_IMXRT_GPIO3_16_31_BASE + _IMXRT_GPIO3_16_31_NIRQS)
+#  define IMXRT_GPIO3_NIRQS    (_IMXRT_GPIO3_0_15_NIRQS + _IMXRT_GPIO3_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO5_0_15_BASE _IMXRT_GPIO3_16_31_BASE
+#  define IMXRT_GPIO3_NIRQS    _IMXRT_GPIO3_0_15_NIRQS
+#endif
+
+/* There is no GPIO4 on this chip */
+
+#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
+#  define IMXRT_IRQ_GPIO5_0    (_IMXRT_GPIO5_0_15_BASE + 0)   /* GPIO5 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO5_1    (_IMXRT_GPIO5_0_15_BASE + 1)   /* GPIO5 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO5_2    (_IMXRT_GPIO5_0_15_BASE + 2)   /* GPIO5 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO5_3    (_IMXRT_GPIO5_0_15_BASE + 3)   /* GPIO5 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO5_4    (_IMXRT_GPIO5_0_15_BASE + 4)   /* GPIO5 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO5_5    (_IMXRT_GPIO5_0_15_BASE + 5)   /* GPIO5 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO5_6    (_IMXRT_GPIO5_0_15_BASE + 6)   /* GPIO5 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO5_7    (_IMXRT_GPIO5_0_15_BASE + 7)   /* GPIO5 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO5_8    (_IMXRT_GPIO5_0_15_BASE + 8)   /* GPIO5 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO5_9    (_IMXRT_GPIO5_0_15_BASE + 9)   /* GPIO5 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO5_10   (_IMXRT_GPIO5_0_15_BASE + 10)  /* GPIO5 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO5_11   (_IMXRT_GPIO5_0_15_BASE + 11)  /* GPIO5 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO5_12   (_IMXRT_GPIO5_0_15_BASE + 12)  /* GPIO5 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO5_13   (_IMXRT_GPIO5_0_15_BASE + 13)  /* GPIO5 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO5_14   (_IMXRT_GPIO5_0_15_BASE + 14)  /* GPIO5 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO5_15   (_IMXRT_GPIO5_0_15_BASE + 15)  /* GPIO5 pin 15 interrupt */
+
+#  define _IMXRT_GPIO5_0_15_NIRQS 16
+#  define _IMXRT_GPIO5_16_31_BASE (_IMXRT_GPIO5_0_15_BASE + _IMXRT_GPIO5_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO5_0_15_NIRQS 0
+#  define _IMXRT_GPIO5_16_31_BASE _IMXRT_GPIO5_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ
+#  define IMXRT_IRQ_GPIO5_16   (_IMXRT_GPIO5_16_31_BASE + 0)  /* GPIO5 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO5_17   (_IMXRT_GPIO5_16_31_BASE + 1)  /* GPIO5 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO5_18   (_IMXRT_GPIO5_16_31_BASE + 2)  /* GPIO5 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO5_19   (_IMXRT_GPIO5_16_31_BASE + 3)  /* GPIO5 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO5_20   (_IMXRT_GPIO5_16_31_BASE + 4)  /* GPIO5 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO5_21   (_IMXRT_GPIO5_16_31_BASE + 5)  /* GPIO5 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO5_22   (_IMXRT_GPIO5_16_31_BASE + 6)  /* GPIO5 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO5_23   (_IMXRT_GPIO5_16_31_BASE + 7)  /* GPIO5 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO5_24   (_IMXRT_GPIO5_16_31_BASE + 8)  /* GPIO5 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO5_25   (_IMXRT_GPIO5_16_31_BASE + 9)  /* GPIO5 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO5_26   (_IMXRT_GPIO5_16_31_BASE + 10) /* GPIO5 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO5_27   (_IMXRT_GPIO5_16_31_BASE + 11) /* GPIO5 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO5_28   (_IMXRT_GPIO5_16_31_BASE + 12) /* GPIO5 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO5_29   (_IMXRT_GPIO5_16_31_BASE + 13) /* GPIO5 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO5_30   (_IMXRT_GPIO5_16_31_BASE + 14) /* GPIO5 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO5_31   (_IMXRT_GPIO5_16_31_BASE + 15) /* GPIO5 pin 31 interrupt */
+
+#  define _IMXRT_GPIO5_16_31_NIRQS 16
+#  define IMXRT_GPIO5_NIRQS    (_IMXRT_GPIO5_0_15_NIRQS + _IMXRT_GPIO5_16_31_NIRQS)
+#else
+#  define IMXRT_GPIO5_NIRQS    _IMXRT_GPIO5_0_15_NIRQS
+#endif
+
+#define IMXRT_GPIO_NIRQS       (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \
+                                IMXRT_GPIO3_NIRQS + IMXRT_GPIO5_NIRQS)
+#define IMXRT_GPIO_IRQ_LAST    (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS)
+
+/* Total number of IRQ numbers **********************************************************/
+
+#define NR_IRQS                (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS)
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Inline functions
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H */
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
 * arch/arm/include/imxrt/irq.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -32,53 +32,61 @@
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
- ****************************************************************************************/
+ ****************************************************************************/

-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
 */

 #ifndef __ARCH_ARM_INCLUDE_IMXRT_IRQ_H
 #define __ARCH_ARM_INCLUDE_IMXRT_IRQ_H

-/****************************************************************************************
+/*****************************************************************************
 * Included Files
- ****************************************************************************************/
+ *****************************************************************************/

 #include <nuttx/config.h>
 #include <arch/imxrt/chip.h>

-/****************************************************************************************
+/*****************************************************************************
 * Pre-processor Definitions
- ****************************************************************************************/
+ *****************************************************************************/

-/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
- * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC.  This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
 */

 /* Common Processor Exceptions (vectors 0-15) */

-#define IMXRT_IRQ_RESERVED       (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+#define IMXRT_IRQ_RESERVED       (0) /* Reserved vector .. only used with
+                                        CONFIG_DEBUG_FEATURES */
+
                                     /* Vector  0: Reset stack pointer value */
-                                     /* Vector  1: Reset (not handler as an IRQ) */
-#define IMXRT_IRQ_NMI            (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+
+                                     /* Vector  1: Reset (not handled by IRQ) */
+
+#define IMXRT_IRQ_NMI            (2) /* Vector  2: Non-Maskable Int (NMI) */
 #define IMXRT_IRQ_HARDFAULT      (3) /* Vector  3: Hard fault */
 #define IMXRT_IRQ_MEMFAULT       (4) /* Vector  4: Memory management (MPU) */
 #define IMXRT_IRQ_BUSFAULT       (5) /* Vector  5: Bus fault */
 #define IMXRT_IRQ_USAGEFAULT     (6) /* Vector  6: Usage fault */
                                     /* Vectors 7-10: Reserved */
+
 #define IMXRT_IRQ_SVCALL        (11) /* Vector 11: SVC call */
 #define IMXRT_IRQ_DBGMONITOR    (12) /* Vector 12: Debug Monitor */
                                     /* Vector 13: Reserved */
-#define IMXRT_IRQ_PENDSV        (14) /* Vector 14: Pendable system service request */
+
+#define IMXRT_IRQ_PENDSV        (14) /* Vector 14: Pendable SSR */
 #define IMXRT_IRQ_SYSTICK       (15) /* Vector 15: System tick */

 /* Chip-Specific External interrupts */

-#define IMXRT_IRQ_EXTINT        (16) /* Vector number of the first external interrupt */
+#define IMXRT_IRQ_EXTINT        (16) /* Vector number of the first ext int */

-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include <arch/imxrt/imxrt102x_irq.h>
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
 #  include <arch/imxrt/imxrt105x_irq.h>
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
 #  include <arch/imxrt/imxrt106x_irq.h>
@@ -86,15 +94,15 @@
 #  error Unrecognized i.MX RT architecture
 #endif

-/****************************************************************************************
+/****************************************************************************
 * Public Types
- ****************************************************************************************/
+ ****************************************************************************/

 #ifndef __ASSEMBLY__

-/****************************************************************************************
+/****************************************************************************
 * Public Data
- ****************************************************************************************/
+ ****************************************************************************/

 #ifdef __cplusplus
 #define EXTERN extern "C"
@@ -104,9 +112,9 @@ extern "C"
 #define EXTERN extern
 #endif

-/****************************************************************************************
+/****************************************************************************
 * Public Function Prototypes
- ****************************************************************************************/
+ ****************************************************************************/

 #undef EXTERN
 #ifdef __cplusplus
@@ -12,6 +12,22 @@ choice
 	default ARCH_CHIP_MIMXRT1052DVL6A
 	depends on ARCH_CHIP_IMXRT

+config ARCH_CHIP_MIMXRT1021CAG4A
+	bool "MIMXRT1021CAG4A"
+	select ARCH_FAMILY_MIMXRT1021C
+
+config ARCH_CHIP_MIMXRT1021CAF4A
+	bool "MIMXRT1021CAF4A"
+	select ARCH_FAMILY_MIMXRT1021C
+
+config ARCH_CHIP_MIMXRT1021DAF5A
+	bool "MIMXRT1021DAF5A"
+	select ARCH_FAMILY_MIMXRT1021D
+
+config ARCH_CHIP_MIMXRT1021DAG5A
+	bool "MIMXRT1021DAG5A"
+	select ARCH_FAMILY_MIMXRT1021D
+
 config ARCH_CHIP_MIMXRT1051DVL6A
 	bool "MIMXRT1051DVL6A"
 	select ARCH_FAMILY_MXRT105xDVL6A
@@ -48,6 +64,30 @@ endchoice # i.MX RT Chip Selection

 # i.MX RT Families

+config ARCH_FAMILY_MIMXRT1021D
+	bool
+	default n
+	select ARCH_FAMILY_IMXRT102x
+	---help---
+		i.MX RT1020 Crossover Processors for Consumer Products
+
+config ARCH_FAMILY_MIMXRT1021C
+	bool
+	default n
+	select ARCH_FAMILY_IMXRT102x
+	---help---
+		i.MX RT1020 Crossover Processors for Industrial Products
+
+config ARCH_FAMILY_IMXRT102x
+	bool
+	default n
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_DPFPU # REVISIT
+	select ARMV7M_HAVE_ICACHE
+	select ARMV7M_HAVE_DCACHE
+	select ARMV7M_HAVE_ITCM
+	select ARMV7M_HAVE_DTCM
+
 config ARCH_FAMILY_MXRT105xDVL6A
 	bool
 	default n
@@ -348,7 +388,7 @@ menuconfig IMXRT_GPIO_IRQ
 if IMXRT_GPIO_IRQ

 config IMXRT_GPIO1_0_15_IRQ
-	bool "GPIO1 Pins 8-15 interrupts"
+	bool "GPIO1 Pins 0-15 interrupts"
 	default n

 config IMXRT_GPIO1_16_31_IRQ
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
 * arch/arm/src/imxrt/chip/imxrt_dmamux.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -32,33 +32,35 @@
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
- ************************************************************************************/
+ ****************************************************************************/

 #ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H
 #define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H

-/************************************************************************************
+/****************************************************************************
 * Included Files
- ************************************************************************************/
+ ****************************************************************************/

 #include <nuttx/config.h>
 #include "chip/imxrt_memorymap.h"

-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_dmamux.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "chip/rt102x/imxrt102x_dmamux.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "chip/rt105x/imxrt105x_dmamux.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_dmamux.h"
+#  include "chip/rt106x/imxrt106x_dmamux.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif

-/************************************************************************************
+/****************************************************************************
 * Pre-processor definitions
- ************************************************************************************/
+ ****************************************************************************/

 #define IMXRT_DMAMUX_NCHAN             32

-/* DMAMUX Register Offsets **********************************************************/
+/* DMAMUX Register Offsets **************************************************/

 #define IMXRT_DMAMUX_CHCFG_OFFSET(n)   ((uintptr_t)(n) << 2)
 #  define IMXRT_DMAMUX_CHCFG0_OFFSET   0x0000  /* Channel configuration register 0 */
@@ -94,7 +96,7 @@
 #  define IMXRT_DMAMUX_CHCFG30_OFFSET  0x0078  /* Channel configuration register 30 */
 #  define IMXRT_DMAMUX_CHCFG31_OFFSET  0x007c  /* Channel configuration register 31 */

-/* DMAMUX Register Addresses ********************************************************/
+/* DMAMUX Register Addresses ************************************************/

 #define IMXRT_DMAMUX_CHCFG(n)          (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG_OFFSET(n))
 #  define IMXRT_DMAMUX_CHCFG0          (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG0_OFFSET)
@@ -130,7 +132,7 @@
 #  define IMXRT_DMAMUX_CHCFG30         (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG30_OFFSET)
 #  define IMXRT_DMAMUX_CHCFG31         (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG31_OFFSET)

-/* DMAMUX Bit-Field Definitions *****************************************************/
+/* DMAMUX Bit-Field Definitions *********************************************/

 /* Channel configuration registers 0-31 */

@@ -1,4 +1,4 @@
-/********************************************************************************************
+/*****************************************************************************
 * arch/arm/src/imxrt/chip/imxrt_enet.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -31,24 +31,24 @@
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
- ********************************************************************************************/
+ *****************************************************************************/

 #ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H
 #define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H

-/********************************************************************************************
+/*****************************************************************************
 * Included Files
- ********************************************************************************************/
+ *****************************************************************************/

 #include <nuttx/config.h>

 #include "chip.h"

-/********************************************************************************************
+/*****************************************************************************
 * Pre-processor Definitions
- ********************************************************************************************/
+ *****************************************************************************/

-/* Register Offsets *************************************************************************/
+/* Register Offsets **********************************************************/

 #define IMXRT_ENET_EIR_OFFSET      0x0004 /* Interrupt Event Register */
 #define IMXRT_ENET_EIMR_OFFSET     0x0008 /* Interrupt Mask Register */
@@ -103,7 +103,7 @@
 #define IMXRT_ENET_TCSR3_OFFSET    0x0620 /* Timer Control Status Register */
 #define IMXRT_ENET_TCCR3_OFFSET    0x0624 /* Timer Compare Capture Register */

-/* Register Addresses ***********************************************************************/
+/* Register Addresses ********************************************************/

 #define IMXRT_ENET_EIR             (IMXRT_ENET_BASE+IMXRT_ENET_EIR_OFFSET)
 #define IMXRT_ENET_EIMR            (IMXRT_ENET_BASE+IMXRT_ENET_EIMR_OFFSET)
@@ -156,7 +156,7 @@
 #define IMXRT_ENET_TCSR3           (IMXRT_ENET_BASE+IMXRT_ENET_TCSR3_OFFSET)
 #define IMXRT_ENET_TCCR3           (IMXRT_ENET_BASE+IMXRT_ENET_TCCR3_OFFSET)

-/* Register Bit Definitions *****************************************************************/
+/* Register Bit Definitions **************************************************/

 /* Interrupt Event Register, Interrupt Mask Register */
                                               /* Bits 0-14: Reserved */
@@ -199,6 +199,7 @@
 #define ENET_ECR_DBSWP               (1 << 8)  /* Bit 8:  Swap bytes */
 #endif
                                               /* Bits 9-31: Reserved */
+#define ECR_RESV_VAL                 (7 << 28) /* Reserve val to write */
 /* MII Management Frame Register */

 #define ENET_MMFR_DATA_SHIFT         (0)       /* Bits 0-15: Management frame data */
@@ -453,20 +454,20 @@
                                               /* Bits 8-31: Reserved */
 /* Timer Compare Capture Register (32-bit compare value) */

-/* Buffer Descriptors ***********************************************************************/
+/* Buffer Descriptors ********************************************************/
 /* Endian-independent descriptor offsets */

-#define DESC_STATUS1_OFFSET         (0)
-#define DESC_LENGTH_OFFSET          (2)
-#define DESC_DATAPTR_OFFSET         (4)
-#define DESC_LEGACY_LEN             (8)
+#define DESC_STATUS1_OFFSET          (0)
+#define DESC_LENGTH_OFFSET           (2)
+#define DESC_DATAPTR_OFFSET          (4)
+#define DESC_LEGACY_LEN              (8)

-#define DESC_STATUS2_OFFSET         (8)
-#define DESC_LENPROTO_OFFSET        (12)
-#define DESC_CHECKSUM_OFFSET        (14)
-#define DESC_BDU_OFFSET             (16)
-#define DESC_TIMESTAMP_OFFSET       (20)
-#define DESC_ENHANCED_LEN           (32)
+#define DESC_STATUS2_OFFSET          (8)
+#define DESC_LENPROTO_OFFSET         (12)
+#define DESC_CHECKSUM_OFFSET         (14)
+#define DESC_BDU_OFFSET              (16)
+#define DESC_TIMESTAMP_OFFSET        (20)
+#define DESC_ENHANCED_LEN            (32)

 /* Legacy/Common TX Buffer Descriptor Bit Definitions.
 *
@@ -599,10 +600,12 @@
 #  define RXDESC_BDU                 (1 << 7)
 #endif

-/********************************************************************************************
+/*****************************************************************************
 * Public Types
- ********************************************************************************************/
-/* Buffer Descriptors ***********************************************************************/
+ *****************************************************************************/
+
+/* Buffer Descriptors ********************************************************/
+
 /* Legacy Buffer Descriptor */

 #ifdef CONFIG_ENET_ENHANCEDBD
@@ -658,12 +661,12 @@ struct enet_desc_s
 #endif /* IMXRT_USE_DBSWAP */
 #endif /* CONFIG_ENET_ENHANCEDBD */

-/********************************************************************************************
+/*****************************************************************************
 * Public Data
- ********************************************************************************************/
+ *****************************************************************************/

-/********************************************************************************************
+/*****************************************************************************
 * Public Functions
- ********************************************************************************************/
+ *****************************************************************************/

 #endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H */
@@ -43,10 +43,12 @@

 #include <nuttx/config.h>

-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_gpio.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "chip/rt102x/imxrt102x_gpio.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "chip/rt105x/imxrt105x_gpio.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_gpio.h"
+#  include "chip/rt106x/imxrt106x_gpio.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
@@ -43,10 +43,12 @@

 #include <nuttx/config.h>

-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_iomuxc.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "chip/rt102x/imxrt102x_iomuxc.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "chip/rt105x/imxrt105x_iomuxc.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_iomuxc.h"
+#  include "chip/rt106x/imxrt106x_iomuxc.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
@@ -42,10 +42,12 @@

 #include <nuttx/config.h>

-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_memorymap.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "chip/rt102x/imxrt102x_memorymap.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "chip/rt105x/imxrt105x_memorymap.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_memorymap.h"
+#  include "chip/rt106x/imxrt106x_memorymap.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
@@ -43,10 +43,12 @@

 #include <nuttx/config.h>

-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_pinmux.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "chip/rt102x/imxrt102x_pinmux.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "chip/rt105x/imxrt105x_pinmux.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_pinmux.h"
+#  include "chip/rt106x/imxrt106x_pinmux.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
@@ -45,6 +45,17 @@
 #include <stdint.h>
 #include "chip/imxrt_memorymap.h"

+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "chip/rt102x/imxrt102x_xbar.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "chip/rt105x/imxrt105x_xbar.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
+#  include "chip/rt106x/imxrt106x_xbar.h"
+#else
+#  error Unrecognized i.MX RT architecture
+#endif
+
+
 /************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/
@@ -0,0 +1,143 @@
+/*****************************************************************************
+ * arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Dave Marples <dave@marples.net>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <nuttx/config.h>
+
+/*****************************************************************************
+ * Preprocessor Definitions
+ *****************************************************************************/
+
+/* Peripheral DMA request channels */
+
+#define IMXRT_DMACHAN_FLEXIO1_01       0  /* FlexIO1 DMA 0/1, Async DMA 0/1 */
+#define IMXRT_DMACHAN_FLEXIO1_45       1  /* FlexIO1 DMA 4/5, Async DMA 4/5 */
+#define IMXRT_DMACHAN_LPUART1_TX       2  /* LPUART1 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART1_RX       3  /* LPUART1 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART3_TX       4  /* LPUART3 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART3_RX       5  /* LPUART3 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART5_TX       6  /* LPUART5 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART5_RX       7  /* LPUART5 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART7_TX       8  /* LPUART7 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART7_RX       9  /* LPUART7 RX FIFO DMA / Async DMA */
+
+#define IMXRT_DMACHAN_LPSPI1_RX       13  /* LPSPI1 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI1_TX       14  /* LPSPI1 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI3_RX       15  /* LPSPI3 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI3_TX       16  /* LPSPI3 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPI2C1          17  /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPI2C3          18  /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_SAI1_RX         19  /* SAI1 RX FIFO DMA */
+#define IMXRT_DMACHAN_SAI1_TX         20  /* SAI1 TX FIFO DMA */
+#define IMXRT_DMACHAN_SAI2_RX         21  /* SAI2 RX FIFO DMA */
+#define IMXRT_DMACHAN_SAI2_TX         22  /* SAI2 TX FIFO DMA */
+#define IMXRT_DMACHAN_ADC_ETC         23  /* ADC ETC DMA */
+#define IMXRT_DMACHAN_ADC1            24  /* ADC1 DMA */
+#define IMXRT_DMACHAN_ACMP1           25  /* ACMP1 DMA */
+#define IMXRT_DMACHAN_ACMP3           26  /* ACMP3 DMA */
+#define IMXRT_DMACHAN_FLEXSPI_RX      28  /* FlexSPI RX FIFO DMA */
+#define IMXRT_DMACHAN_FLEXSPI_TX      29  /* FlexSPI TX FIFO DMA */
+#define IMXRT_DMACHAN_XBAR1_0         30  /* XBAR1 DMA 0 */
+#define IMXRT_DMACHAN_XBAR1_1         31  /* XBAR1 DMA 1 */
+#define IMXRT_DMACHAN_FLEXPWM1_RX0    32  /* FlexPWM1 RX sub-module0 capture */
+#define IMXRT_DMACHAN_FLEXPWM1_RX1    33  /* FlexPWM1 RX sub-module1 capture */
+#define IMXRT_DMACHAN_FLEXPWM1_RX2    34  /* FlexPWM1 RX sub-module2 capture */
+#define IMXRT_DMACHAN_FLEXPWM1_RX3    35  /* FlexPWM1 RX sub-module3 capture */
+#define IMXRT_DMACHAN_FLEXPWM1_TX0    36  /* FlexPWM1 TX sub-module0 value */
+#define IMXRT_DMACHAN_FLEXPWM1_TX1    37  /* FlexPWM1 TX sub-module1 value */
+#define IMXRT_DMACHAN_FLEXPWM1_TX2    38  /* FlexPWM1 TX sub-module2 value */
+#define IMXRT_DMACHAN_FLEXPWM1_TX3    39  /* FlexPWM1 TX sub-module3 value */
+#define IMXRT_DMACHAN_QTIMER1_RX0     48  /* QTimer1 RX capture timer 0 */
+#define IMXRT_DMACHAN_QTIMER1_RX1     49  /* QTimer1 RX capture timer 1 */
+#define IMXRT_DMACHAN_QTIMER1_RX2     50  /* QTimer1 RX capture timer 2 */
+#define IMXRT_DMACHAN_QTIMER1_RX3     51  /* QTimer1 RX capture timer 3 */
+#define IMXRT_DMACHAN_QTIMER1_TX0     52  /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */
+#define IMXRT_DMACHAN_QTIMER1_TX1     53  /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */
+#define IMXRT_DMACHAN_QTIMER1_TX2     54  /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */
+#define IMXRT_DMACHAN_QTIMER1_TX3     55  /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */
+#define IMXRT_DMACHAN_FLEXIO1_23      64  /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */
+#define IMXRT_DMACHAN_FLEXIO1_67      65  /* FlexIO1 DMA 6 / Async DMA 6 / DMA 7 / Async DMA 7 */
+#define IMXRT_DMACHAN_LPUART2_TX      66  /* LPUART2 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART2_RX      67  /* LPUART2 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART4_TX      68  /* LPUART4 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART4_RX      69  /* LPUART4 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART6_TX      70  /* LPUART6 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART6_RX      71  /* LPUART6 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART8_TX      72  /* LPUART8 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART8_RX      73  /* LPUART8 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI2_RX       77  /* LPSPI2 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI2_TX       78  /* LPSPI2 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI4_RX       79  /* LPSPI4 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI4_TX       80  /* LPSPI4 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPI2C2          81  /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPI2C4          82  /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_SAI3_RX         83  /* SAI3 RX FIFO DMA */
+#define IMXRT_DMACHAN_SAI3_TX         84  /* SAI3 RX FIFO DMA */
+#define IMXRT_DMACHAN_SPDIF_RX        85  /* SPDIF RX DMA */
+#define IMXRT_DMACHAN_SPDIF_TX        86  /* SPDIF TX DMA */
+#define IMXRT_DMACHAN_ADC2            88  /* ADC2 DMA */
+#define IMXRT_DMACHAN_ACMP2           89  /* ACMP2 DMA */
+#define IMXRT_DMACHAN_ACMP4           90  /* ACMP4 DMA */
+#define IMXRT_DMACHAN_ENET_0          92  /* ENET Timer DMA 0 */
+#define IMXRT_DMACHAN_ENET_1          93  /* ENET Timer DMA 1 */
+#define IMXRT_DMACHAN_XBAR1_2         94  /* XBAR1 DMA 2 */
+#define IMXRT_DMACHAN_XBAR1_3         95  /* XBAR1 DMA 3 */
+#define IMXRT_DMACHAN_FLEXPWM2_RX0    96  /* FlexPWM2 RX sub-module0 capture */
+#define IMXRT_DMACHAN_FLEXPWM2_RX1    97  /* FlexPWM2 RX sub-module1 capture */
+#define IMXRT_DMACHAN_FLEXPWM2_RX2    98  /* FlexPWM2 RX sub-module2 capture */
+#define IMXRT_DMACHAN_FLEXPWM2_RX3    99  /* FlexPWM2 RX sub-module3 capture */
+#define IMXRT_DMACHAN_FLEXPWM2_TX0   100  /* FlexPWM2 TX sub-module0 value */
+#define IMXRT_DMACHAN_FLEXPWM2_TX1   101  /* FlexPWM2 TX sub-module1 value */
+#define IMXRT_DMACHAN_FLEXPWM2_TX2   102  /* FlexPWM2 TX sub-module2 value */
+#define IMXRT_DMACHAN_FLEXPWM2_TX3   103  /* FlexPWM2 TX sub-module3 value */
+#define IMXRT_DMACHAN_QTIMER2_RX0    112  /* QTimer2 RX capture timer 0 */
+#define IMXRT_DMACHAN_QTIMER2_RX1    113  /* QTimer2 RX capture timer 1 */
+#define IMXRT_DMACHAN_QTIMER2_RX2    114  /* QTimer2 RX capture timer 2 */
+#define IMXRT_DMACHAN_QTIMER2_RX3    115  /* QTimer2 RX capture timer 3 */
+#define IMXRT_DMACHAN_QTIMER2_TX0    116  /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */
+#define IMXRT_DMACHAN_QTIMER2_TX1    117  /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */
+#define IMXRT_DMACHAN_QTIMER2_TX2    118  /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */
+#define IMXRT_DMACHAN_QTIMER2_TX3    119  /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */
+
+#define IMXRT_DMA_NCHANNELS          128  /* Includes reserved channels */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H */
@@ -0,0 +1,116 @@
+/*****************************************************************************
+ * arch/arm/src/imxrt/chip/rt102x/imxrt105x_gpio.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *            Dave Marples <dave@marples.net>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/imxrt_memorymap.h"
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ *****************************************************************************/
+
+/* Register offsets **********************************************************/
+
+#define IMXRT_GPIO_DR_OFFSET     0x0000  /* GPIO data register */
+#define IMXRT_GPIO_GDIR_OFFSET   0x0004  /* GPIO direction register */
+#define IMXRT_GPIO_PSR_OFFSET    0x0008  /* GPIO pad status register */
+#define IMXRT_GPIO_ICR1_OFFSET   0x000c  /* GPIO interrupt configuration register1 */
+#define IMXRT_GPIO_ICR2_OFFSET   0x0010  /* GPIO interrupt configuration register2 */
+#define IMXRT_GPIO_IMR_OFFSET    0x0014  /* GPIO interrupt mask register */
+#define IMXRT_GPIO_ISR_OFFSET    0x0018  /* GPIO interrupt status register */
+#define IMXRT_GPIO_EDGE_OFFSET   0x001c  /* GPIO edge select register */
+#define IMXRT_GPIO_SET_OFFSET    0x0084  /* GPIO data register SET */
+#define IMXRT_GPIO_CLEAR_OFFSET  0x0088  /* GPIO data register CLEAR */
+#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c  /* GPIO data register TOGGLE */
+
+/* Register addresses ********************************************************/
+
+#define IMXRT_GPIO1_DR           (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO1_GDIR         (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO1_PSR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO1_ICR1         (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO1_ICR2         (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO1_IMR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO1_ISR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO1_EDGE         (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
+#define IMXRT_GPIO1_SET          (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET)
+#define IMXRT_GPIO1_CLEAR        (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET)
+#define IMXRT_GPIO1_TOGGLE       (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
+
+#define IMXRT_GPIO2_DR           (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO2_GDIR         (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO2_PSR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO2_ICR1         (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO2_ICR2         (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO2_IMR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO2_ISR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO2_EDGE         (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
+#define IMXRT_GPIO2_SET          (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET)
+#define IMXRT_GPIO2_CLEAR        (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET)
+#define IMXRT_GPIO2_TOGGLE       (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
+
+#define IMXRT_GPIO3_DR           (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO3_GDIR         (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO3_PSR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO3_ICR1         (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO3_ICR2         (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO3_IMR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO3_ISR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO3_EDGE         (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
+#define IMXRT_GPIO3_SET          (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET)
+#define IMXRT_GPIO3_CLEAR        (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET)
+#define IMXRT_GPIO3_TOGGLE       (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
+
+#define IMXRT_GPIO5_DR           (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO5_GDIR         (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO5_PSR          (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO5_ICR1         (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO5_ICR2         (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO5_IMR          (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO5_ISR          (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO5_EDGE         (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
+#define IMXRT_GPIO5_SET          (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET)
+#define IMXRT_GPIO5_CLEAR        (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET)
+#define IMXRT_GPIO5_TOGGLE       (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H */
@@ -0,0 +1,261 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Dave Marples <dave@marples.net>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <nuttx/config.h>
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ *****************************************************************************/
+
+/* System memory map */
+
+#define IMXRT_ITCM_BASE           0x00000000  /* 256KB ITCM */
+                               /* 0x00040000     768KB ITCM Reserved */
+                               /* 0x00100000     1MB ITCM Reserved */
+#define IMXRT_ROMCP_BASE          0x00200000  /* 96KB ROMCP */
+                               /* 0x00218000     416KB ROMCP Reserved */
+                               /* 0x00280000     1536KB Reserved */
+                               /* 0x00400000     124MB Reserved */
+                               /* 0x00800000     1527MB Reserved */
+#define IMXRT_FLEXSPI_BASE        0x06000000  /* 128MB FlexSPI (Aliased) */
+#define IMXRT_SEMCA_BASE          0x06800000  /* 639MB SEMC (Aliased) */
+                               /* 0x90000000 256MB SEMC (Aliased) */
+#define IMXRT_DTCM_BASE           0x20000000  /* 256KB DTCM */
+                               /* 0x20040000     768KB DTCM Reserved */
+                               /* 0x20100000     1MB Reserved */
+#define IMXRT_OCRAM_BASE          0x20200000  /* 256KB OCRAM */
+                               /* 0x20240000     1792KB OCRAM Reserved */
+                               /* 0x20400000     252MB Reserved */
+                               /* 0x30000000     256MB Reserved */
+#define IMXRT_AIPS1_BASE          0x40000000  /* 1MB AIPS-1 */
+#define IMXRT_AIPS2_BASE          0x40100000  /* 1MB AIPS-2 */
+#define IMXRT_AIPS3_BASE          0x40200000  /* 1MB AIPS-3 */
+#define IMXRT_AIPS4_BASE          0x40300000  /* 1MB AIPS-4 */
+                               /* 0x40400000     12MB Reserved */
+                               /* 0x41000000     1MB Reserved */
+#define IMXRT_MCNF_BASE           0x41100000  /* 1MB "m" configuration port */
+                               /* 41200000       1MB Reserved for "per" GPV */
+                               /* 41300000       1MB Reserved for "ems" GPV */
+#define IMXRT_CPUCNF_BASE         0x41400000  /* 1MB "cpu" configuration port */
+                               /* 0x41500000     1MB GPV Reserved */
+                               /* 0x41600000     1MB GPV Reserved */
+                               /* 0x41700000     1MB GPV Reserved */
+                               /* 0x41800000     8MB Reserved */
+                               /* 0x42000000     32MB Reserved */
+                               /* 0x44000000     64MB Reserved */
+                               /* 0x48000000     384MB Reserved */
+#define IMXRT_FLEXCIPHER_BASE     0x60000000  /* 504MB FlexSPI/ FlexSPI ciphertext */
+#define IMXRT_FLEXSPITX_BASE      0x7f800000  /* 4MB FlexSPI TX FIFO */
+#define IMXRT_FLEXSPIRX_BASE      0x7fc00000  /* 4MB FlexSPI RX FIFO */
+#define IMXRT_EXTMEM_BASE         0x80000000  /* 1.5GB SEMC external memories shared memory space */
+#define IMXRT_CM7_BASE            0xe0000000  /* 1MB CM7 PPB */
+                               /* 0xe0100000     511MB Reserved */
+
+/* AIPS-1 memory map */
+
+                               /* 0x40000000     256KB Reserved */
+                               /* 0x40040000     240KB Reserved */
+#define IMXRT_AIPS1CNF_BASE       0x4007c000  /* 16KB AIPS-1 Configuration */
+#define IMXRT_DCDC_BASE           0x40080000  /* 16KB DCDC */
+#define IMXRT_PIT_BASE            0x40084000  /* 16KB PIT */
+                               /* 0x40088000     16KB Reserved */
+                               /* 0x4008c000     16KB Reserved */
+                               /* 0x40090000     16KB Reserved */
+#define IMXRT_ACMP_BASE           0x40094000  /* 16KB ACMP */
+                               /* 0x40098000     16KB Reserved */
+                               /* 0x4009c000     16KB Reserved */
+                               /* 0x400a0000     16KB Reserved */
+#define IMXRT_IOMUXCSNVSGPR_BASE  0x400a4000  /* 16KB IOMUXC_SNVS_GPR */
+#define IMXRT_IOMUXCSNVS_BASE     0x400a8000  /* 16KB IOMUXC_SNVS */
+#define IMXRT_IOMUXCGPR_BASE      0x400ac000  /* 16KB IOMUXC_GPR */
+#define IMXRT_FLEXRAM_BASE        0x400b0000  /* 16KB CM7_MXRT(FLEXRAM) */
+#define IMXRT_EWM_BASE            0x400b4000  /* 16KB EWM */
+#define IMXRT_WDOG1_BASE          0x400b8000  /* 16KB WDOG1 */
+#define IMXRT_WDOG3_BASE          0x400bc000  /* 16KB WDOG3 */
+#define IMXRT_GPIO5_BASE          0x400c0000  /* 16KB GPIO5 */
+#define IMXRT_ADC1_BASE           0x400c4000  /* 16KB ADC1 */
+#define IMXRT_ADC2_BASE           0x400c8000  /* 16KB ADC2 */
+#define IMXRT_TRNG_BASE           0x400cc000  /* 16KB TRNG */
+#define IMXRT_WDOG2_BASE          0x400d0000  /* 16KB WDOG2 */
+#define IMXRT_SNVSHP_BASE         0x400d4000  /* 16KB SNVS_HP */
+#define IMXRT_ANATOP_BASE         0x400d8000  /* 16KB ANATOP */
+#define IMXRT_CSU_BASE            0x400dc000  /* 16KB CSU */
+                               /* 0x400e0000     16KB Reserved */
+                               /* 0x400e4000     16KB Reserved */
+#define IMXRT_EDMA_BASE           0x400e8000  /* 16KB EDMA */
+#define IMXRT_DMAMUX_BASE         0x400ec000  /* 16KB DMA_CH_MUX */
+                               /* 400f0000       16KB Reserved */
+#define IMXRT_GPC_BASE            0x400f4000  /* 16KB GPC */
+#define IMXRT_SRC_BASE            0x400f8000  /* 16KB SRC */
+#define IMXRT_CCM_BASE            0x400fc000  /* 16KB CCM */
+
+/* AIPS-2 memory map */
+
+                               /* 0x40100000     256KB Reserved */
+                               /* 0x40140000     240KB Reserved */
+#define IMXRT_AIPS2CNF_BASE       0x4017c000  /* 16KB AIPS-2 Configuration */
+#define IMXRT_ROMCPC_BASE         0x40180000  /* 16KB ROMCP controller*/
+#define IMXRT_LPUART1_BASE        0x40184000  /* 16KB LPUART1 */
+#define IMXRT_LPUART2_BASE        0x40188000  /* 16KB LPUART2 */
+#define IMXRT_LPUART3_BASE        0x4018c000  /* 16KB LPUART3 */
+#define IMXRT_LPUART4_BASE        0x40190000  /* 16KB LPUART4 */
+#define IMXRT_LPUART5_BASE        0x40194000  /* 16KB LPUART5 */
+#define IMXRT_LPUART6_BASE        0x40198000  /* 16KB LPUART6 */
+#define IMXRT_LPUART7_BASE        0x4019c000  /* 16KB LPUART7 */
+#define IMXRT_LPUART8_BASE        0x401a0000  /* 16KB LPUART8 */
+                               /* 0x401a4000     16KB Reserved */
+                               /* 0x401a8000     16KB Reserved */
+#define IMXRT_FLEXIO1_BASE        0x401ac000  /* 16KB FlexIO1 */
+                               /* 0x401b0000     16KB Reserved */
+                               /* 0x401b4000     16KB Reserved */
+#define IMXRT_GPIO1_BASE          0x401b8000  /* 16KB GPIO1 */
+#define IMXRT_GPIO2_BASE          0x401bc000  /* 16KB GPIO2 */
+#define IMXRT_GPIO3_BASE          0x401c0000  /* 16KB GPIO3 */
+                               /* 0x401c4000     16KB Reserved */
+                               /* 0x401c8000     16KB Reserved */
+                               /* 0x401cc000     16KB Reserved */
+#define IMXRT_CAN1_BASE           0x401d0000  /* 16KB CAN1 */
+#define IMXRT_CAN2_BASE           0x401d4000  /* 16KB CAN2 */
+                               /* 0x401d8000     16KB Reserved */
+#define IMXRT_QTIMER1_BASE        0x401dc000  /* 16KB QTimer1 */
+#define IMXRT_QTIMER2_BASE        0x401e0000  /* 16KB QTimer2 */
+                               /* 0x401e4000     16KB Reserved */
+                               /* 0x401e8000     16KB Reserved */
+#define IMXRT_GPT1_BASE           0x401ec000  /* 16KB GPT1 */
+#define IMXRT_GPT2_BASE           0x401f0000  /* 16KB GPT2 */
+#define IMXRT_OCOTP_BASE          0x401f4000  /* 16KB OCOTP */
+#define IMXRT_IOMUXC_BASE         0x401f8000  /* 16KB IOMUXC */
+#define IMXRT_KPP_BASE            0x401fc000  /* 16KB KPP */
+
+/* AIPS-3 memory map */
+
+                               /* 0x40200000     256KB Reserved */
+                               /* 0x40240000     240KB Reserved */
+#define IMXRT_AIOS3CNF_BASE       0x4027c000  /* 16KB AIPS-3 Configuration */
+                               /* 0x40280000     16KB Reserved */
+                               /* 0x40284000     16KB Reserved */
+                               /* 0x40288000     16KB Reserved */
+                               /* 0x4028c000     16KB Reserved */
+                               /* 0x40290000     16KB Reserved */
+                               /* 0x40294000     16KB Reserved */
+                               /* 0x40298000     16KB Reserved */
+                               /* 0x4029c000     16KB Reserved */
+                               /* 0x402a0000     16KB Reserved */
+                               /* 0x402a4000     16KB Reserved */
+#define IMXRT_FLEXSPIC_BASE       0x402a8000  /* 16KB FlexSPI controller */
+                               /* 0x402ac000     16KB Reserved */
+                               /* 0x402b0000     16KB Reserved */
+                               /* 0x402b4000     16KB Reserved */
+                               /* 0x402b8000     16KB Reserved */
+                               /* 0x402bc000     16KB Reserved */
+#define IMXRT_USDHC1_BASE         0x402c0000  /* 16KB USDHC1 */
+#define IMXRT_USDHC2_BASE         0x402c4000  /* 16KB USDHC2 */
+                               /* 0x402c8000     16KB Reserved */
+                               /* 0x402cc000     16KB Reserved */
+                               /* 0x402d0000     16KB Reserved */
+                               /* 0x402d4000     16KB Reserved */
+#define IMXRT_ENET_BASE           0x402d8000  /* 16KB ENET */
+                              /*  0x402dc000     16KB Reserved */
+#define IMXRT_USB_BASE            0x402e0000  /* 16KB USB(USB) */
+                               /* 0x402e4000     16KB Reserved */
+                               /* 0x402e8000     16KB Reserved */
+                               /* 0x402ec000     16KB Reserved */
+#define IMXRT_SEMC_BASE           0x402f0000  /* 16KB SEMC */
+                               /* 0x402f4000     16KB Reserved */
+                               /* 0x402f8000     16KB Reserved */
+#define IMXRT_DCP_BASE            0x402fc000  /* 16KB DCP */
+
+/* AIPS-4 memory map */
+
+                               /* 0x40300000     256KB Reserved */
+                               /* 0x40340000     240KB Reserved */
+#define IMXRT_AIPS4CNF_BASE       0x4037c000  /* 16KB AIPS-4 Configuration */
+#define IMXRT_SPDIF_BASE          0x40380000  /* 16KB SPDIF */
+#define IMXRT_SAI1_BASE           0x40384000  /* 16KB SAI1 */
+#define IMXRT_SAI2_BASE           0x40388000  /* 16KB SAI2 */
+#define IMXRT_SAI3_BASE           0x4038c000  /* 16KB SAI3 */
+                               /* 0x40390000     16KB Reserved */
+#define IMXRT_LPSPI1_BASE         0x40394000  /* 16KB LPSPI1 */
+#define IMXRT_LPSPI2_BASE         0x40398000  /* 16KB LPSPI2 */
+#define IMXRT_LPSPI3_BASE         0x4039c000  /* 16KB LPSPI3 */
+#define IMXRT_LPSPI4_BASE         0x403a0000  /* 16KB LPSPI4 */
+                               /* 0x403a4000     16KB Reserved */
+                               /* 0x403a8000     16KB Reserved */
+                               /* 0x403ac000     16KB Reserved */
+#define IMXRT_ADCETC_BASE         0x403b0000  /* 16KB ADC_ETC */
+#define IMXRT_AOI1_BASE           0x403b4000  /* 16KB AOI1 */
+                               /* 0x403b8000     16KB Reserved */
+#define IMXRT_XBAR1_BASE          0x403bc000  /* 16KB XBAR1 */
+#define IMXRT_XBAR2_BASE          0x403c0000  /* 16KB XBAR2 */
+                               /* 0x403c4000     16KB Reserved */
+#define IMXRT_ENC1_BASE           0x403c8000  /* 16KB ENC1 */
+#define IMXRT_ENC2_BASE           0x403cc000  /* 16KB ENC2 */
+                               /* 0x403d0000     16KB Reserved */
+                               /* 0x403d4000     16KB Reserved */
+                               /* 0x403d8000     16KB Reserved */
+#define IMXRT_FLEXPWM1_BASE       0x403dc000  /* 16KB FLEXPWM1 */
+#define IMXRT_FLEXPWM2_BASE       0x403e0000  /* 16KB FLEXPWM2 */
+                               /* 0x403e4000     16KB Reserved */
+                               /* 0x403e8000     16KB Reserved */
+#define IMXRT_BEE_BASE            0x403ec000  /* 16KB BEE */
+#define IMXRT_LPI2C1_BASE         0x403f0000  /* 16KB  */
+#define IMXRT_LPI2C2_BASE         0x403f4000  /* 16KB LPI2C2 */
+#define IMXRT_LPI2C3_BASE         0x403f8000  /* 16KB LPI2C3 */
+#define IMXRT_LPI2C4_BASE         0x403fc000  /* 16KB LPI2C4 */
+
+/* PPB memory map */
+
+#define IMXRT_TPIU_BASE           0xe0040000  /* 4KB TPIU */
+#define IMXRT_ETM_BASE            0xe0041000  /* 4KB ETM */
+#define IMXRT_CTI_BASE            0xe0042000  /* 4KB CTI */
+#define IMXRT_TSGEN_BASE          0xe0043000  /* 4KB TSGEN */
+#define IMXRT_PPBRES_BASE         0xe0044000  /* 4KB PPB RES */
+                               /* 0xe0045000     236KB PPB Reserved */
+#define IMXRT_MCM_BASE            0xe0080000  /* 4KB MCM */
+                               /* 0xe0081000     444KB PPB Reserved */
+                               /* 0xe00f0000     52KB PPB Reserved */
+#define IMXRT_SYSROM_BASE         0xe00fd000  /* 4KB SYS ROM */
+#define IMXRT_PROCROM_BASE        0xe00fe000  /* 4KB Processor ROM */
+#define IMXRT_PPBROM_BASE         0xe00ff000  /* 4KB PPB ROM */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H */
@@ -0,0 +1,324 @@
+/* XBAR Defines for IMXRT102x */
+
+/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
+
+#define IMXRT_XBARA1_IN_LOGIC_LOW                        IMXRT_XBARA1(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
+#define IMXRT_XBARA1_IN_LOGIC_HIGH                       IMXRT_XBARA1(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 2)    RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 3)    RESERVED */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04                  IMXRT_XBARA1(XBAR_INPUT, 4)    /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05                  IMXRT_XBARA1(XBAR_INPUT, 5)    /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06                  IMXRT_XBARA1(XBAR_INPUT, 6)    /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07                  IMXRT_XBARA1(XBAR_INPUT, 7)    /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08                  IMXRT_XBARA1(XBAR_INPUT, 8)    /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09                  IMXRT_XBARA1(XBAR_INPUT, 9)    /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10                  IMXRT_XBARA1(XBAR_INPUT, 10)   /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11                  IMXRT_XBARA1(XBAR_INPUT, 11)   /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12                  IMXRT_XBARA1(XBAR_INPUT, 12)   /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13                  IMXRT_XBARA1(XBAR_INPUT, 13)   /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14                  IMXRT_XBARA1(XBAR_INPUT, 14)   /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15                  IMXRT_XBARA1(XBAR_INPUT, 15)   /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16                  IMXRT_XBARA1(XBAR_INPUT, 16)   /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17                  IMXRT_XBARA1(XBAR_INPUT, 17)   /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18                  IMXRT_XBARA1(XBAR_INPUT, 18)   /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19                  IMXRT_XBARA1(XBAR_INPUT, 19)   /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 20)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 21)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 22)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 23)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 24)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 25)   RESERVED */
+#define IMXRT_XBARA1_IN_ACMP1_OUT                        IMXRT_XBARA1(XBAR_INPUT, 26)   /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
+#define IMXRT_XBARA1_IN_ACMP2_OUT                        IMXRT_XBARA1(XBAR_INPUT, 27)   /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
+#define IMXRT_XBARA1_IN_ACMP3_OUT                        IMXRT_XBARA1(XBAR_INPUT, 28)   /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
+#define IMXRT_XBARA1_IN_ACMP4_OUT                        IMXRT_XBARA1(XBAR_INPUT, 29)   /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 30)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 31)   RESERVED */
+#define IMXRT_XBARA1_IN_QTIMER1_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 32)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
+#define IMXRT_XBARA1_IN_QTIMER1_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 33)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
+#define IMXRT_XBARA1_IN_QTIMER1_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 34)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
+#define IMXRT_XBARA1_IN_QTIMER1_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 35)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
+#define IMXRT_XBARA1_IN_QTIMER2_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 36)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
+#define IMXRT_XBARA1_IN_QTIMER2_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 37)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
+#define IMXRT_XBARA1_IN_QTIMER2_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 38)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
+#define IMXRT_XBARA1_IN_QTIMER2_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 39)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN40 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN40 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN41 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN41 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN42 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN42 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN43 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN43 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN44 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN44 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN45 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN45 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN46 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN46 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN47 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN47 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 48)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 49)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 50)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 51)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 52)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 53)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 54)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 55)   RESERVED */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER0                     IMXRT_XBARA1(XBAR_INPUT, 56)   /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER1                     IMXRT_XBARA1(XBAR_INPUT, 57)   /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER2                     IMXRT_XBARA1(XBAR_INPUT, 58)   /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER3                     IMXRT_XBARA1(XBAR_INPUT, 59)   /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
+#define IMXRT_XBARA1_IN_ENC1_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 60)   /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
+#define IMXRT_XBARA1_IN_ENC2_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 61)   /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 62)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 63)   RESERVED */
+#define IMXRT_XBARA1_IN_DMA_DONE0                        IMXRT_XBARA1(XBAR_INPUT, 64)   /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE1                        IMXRT_XBARA1(XBAR_INPUT, 65)   /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE2                        IMXRT_XBARA1(XBAR_INPUT, 66)   /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE3                        IMXRT_XBARA1(XBAR_INPUT, 67)   /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE4                        IMXRT_XBARA1(XBAR_INPUT, 68)   /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE5                        IMXRT_XBARA1(XBAR_INPUT, 69)   /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE6                        IMXRT_XBARA1(XBAR_INPUT, 70)   /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE7                        IMXRT_XBARA1(XBAR_INPUT, 71)   /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 72)   /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 73)   /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 74)   /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 75)   /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 76)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 77)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 78)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 79)   RESERVED */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARA1(XBAR_INPUT, 80)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARA1(XBAR_INPUT, 81)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARA1(XBAR_INPUT, 82)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARA1(XBAR_INPUT, 83)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARA1(XBAR_INPUT, 84)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARA1(XBAR_INPUT, 85)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARA1(XBAR_INPUT, 86)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARA1(XBAR_INPUT, 87)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
+
+/* XBARA1 Mux Output  (M Muxes) ***************************************************************************************************************/
+
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 0)    /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 1)    /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 2)    /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 3)    /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 4)    /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 5)    /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 6)    /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 7)    /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 8)    /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 9)    /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 10)   /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 11)   /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 12)   /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 13)   /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 14)   /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 15)   /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 16)   /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 17)   /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 18)   /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 19)   /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
+#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 20)   /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 21)   /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 22)   /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 23)   /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 24)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 25)   RESERVED */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 26)   /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 27)   /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 28)   /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 29)   /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 30)   /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 31)   /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 32)   /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 33)   /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 34)   /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 35)   /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 36)   /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT2_SEL_OFFSET     IMXXRT_XBARA1(XBAR_OUTPUT,37)   /* XBARA1_OUT37 output assigned to FLEXPWM1_2_FAULT2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT3_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 38)   /* XBARA1_OUT38 output assigned to FLEXPWM1_2_FAULT3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 39)   /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 40)   /* XBARA1_OUT40 output assigned to FLEXPWM2_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 41)   /* XBARA1_OUT41 output assigned to FLEXPWM2_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 42)   /* XBARA1_OUT42 output assigned to FLEXPWM2_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 43)   /* XBARA1_OUT43 output assigned to FLEXPWM2_EXTA3 */
+
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 44)   /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 45)   /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 46)   /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 47)   /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 48)   /* XBARA1_OUT48 output assigned to FLEXPWM2_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 49)   /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 50)   /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 51)   /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 52)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 53)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 54)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 55)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 56)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 57)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 58)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 59)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 60)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 61)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 62)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 63)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 64)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 65)   RESERVED */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 66)   /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 67)   /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN */
+#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 68)   /* XBARA1_OUT68 output assigned to ENC1_INDEX */
+#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 69)   /* XBARA1_OUT69 output assigned to ENC1_HOME */
+#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 70)   /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 71)   /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 72)   /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN */
+#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 73)   /* XBARA1_OUT73 output assigned to ENC2_INDEX */
+#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 74)   /* XBARA1_OUT74 output assigned to ENC2_HOME */
+#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 75)   /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 76)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 77)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 78)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 79)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 80)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 81)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 82)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 83)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 84)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 85)   RESERVED */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 86)   /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 87)   /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 88)   /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 89)   /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 90)   /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 91)   /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 92)   /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 93)   /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 94)   /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 95)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 96)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 97)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 98)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 99)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 100)  RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 101)  RESERVED */
+#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 102)  /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 103)  /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 104)  /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 105)  /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 106)  /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107)  /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG10 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108)  /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG11 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109)  /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG12 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110)  /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG13 */
+#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 111)  /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 112)  /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 113)  /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 114)  /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 115)  /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 116)  /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 117)  /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 118)  /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 119)  /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 120)  /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 121)  /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 122)  /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 123)  /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 124)  /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 125)  /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 126)  /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 127)  /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 128)  /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 129)  RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 130)  RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 131)  RESERVED */
+
+/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB2_IN_LOGIC_LOW                        IMXRT_XBARB2(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
+#define IMXRT_XBARB2_IN_LOGIC_HIGH                       IMXRT_XBARB2(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 2)    RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 3)    RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 4)    RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 5)    RESERVED */
+#define IMXRT_XBARB2_IN_ACMP1_OUT                        IMXRT_XBARB2(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
+#define IMXRT_XBARB2_IN_ACMP2_OUT                        IMXRT_XBARB2(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
+#define IMXRT_XBARB2_IN_ACMP3_OUT                        IMXRT_XBARB2(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
+#define IMXRT_XBARB2_IN_ACMP4_OUT                        IMXRT_XBARB2(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 10)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 11)   RESERVED */
+#define IMXRT_XBARB2_IN_QTIMER1_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
+#define IMXRT_XBARB2_IN_QTIMER1_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
+#define IMXRT_XBARB2_IN_QTIMER1_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
+#define IMXRT_XBARB2_IN_QTIMER1_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
+#define IMXRT_XBARB2_IN_QTIMER2_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
+#define IMXRT_XBARB2_IN_QTIMER2_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
+#define IMXRT_XBARB2_IN_QTIMER2_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
+#define IMXRT_XBARB2_IN_QTIMER2_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN20 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN20 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN21 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN21 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN22 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN22 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN23 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN23 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN24 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN24 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN25 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN25 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN26 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN26 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN27 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN27 input. */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 28)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 29)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 30)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 31)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 32)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 33)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 34)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 35)   RESERVED */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER0                     IMXRT_XBARB2(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER1                     IMXRT_XBARB2(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB2(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB2(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB2(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB2(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB2(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB2(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB2(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB2(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
+#define IMXRT_XBARB2_IN_ENC1_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
+#define IMXRT_XBARB2_IN_ENC2_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 48)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 49)   RESERVED */
+#define IMXRT_XBARB2_IN_DMA_DONE0                        IMXRT_XBARB2(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE1                        IMXRT_XBARB2(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE2                        IMXRT_XBARB2(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE3                        IMXRT_XBARB2(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE4                        IMXRT_XBARB2(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE5                        IMXRT_XBARB2(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE6                        IMXRT_XBARB2(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE7                        IMXRT_XBARB2(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
+
+/* XBARB2 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 0)    /* XBARB2_OUT0 output assigned to AOI1_IN00 */
+#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 1)    /* XBARB2_OUT1 output assigned to AOI1_IN01 */
+#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 2)    /* XBARB2_OUT2 output assigned to AOI1_IN02 */
+#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 3)    /* XBARB2_OUT3 output assigned to AOI1_IN03 */
+#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 4)    /* XBARB2_OUT4 output assigned to AOI1_IN04 */
+#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 5)    /* XBARB2_OUT5 output assigned to AOI1_IN05 */
+#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 6)    /* XBARB2_OUT6 output assigned to AOI1_IN06 */
+#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 7)    /* XBARB2_OUT7 output assigned to AOI1_IN07 */
+#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 8)    /* XBARB2_OUT8 output assigned to AOI1_IN08 */
+#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 9)    /* XBARB2_OUT9 output assigned to AOI1_IN09 */
+#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 10)   /* XBARB2_OUT10 output assigned to AOI1_IN10 */
+#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 11)   /* XBARB2_OUT11 output assigned to AOI1_IN11 */
+#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 12)   /* XBARB2_OUT12 output assigned to AOI1_IN12 */
+#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 13)   /* XBARB2_OUT13 output assigned to AOI1_IN13 */
+#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 14)   /* XBARB2_OUT14 output assigned to AOI1_IN14 */
+#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 15)   /* XBARB2_OUT15 output assigned to AOI1_IN15 */
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt105x_gpio.h
+ * arch/arm/src/imxrt/rt105x/imxrt105x_gpio.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/imxrt105x_iomuxc.h
+ * arch/arm/src/imxrt/rt105x/imxrt105x_iomuxc.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Author:  Gregory Nutt <gnutt@nuttx.org>
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h
+ * arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -1,5 +1,5 @@
 /*****************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_pinmux.h
+ * arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -0,0 +1,386 @@
+/* XBAR Defines for IMXRT1050 */
+
+/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
+
+#define IMXRT_XBARA1_IN_LOGIC_LOW                        IMXRT_XBARA1(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
+#define IMXRT_XBARA1_IN_LOGIC_HIGH                       IMXRT_XBARA1(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02                  IMXRT_XBARA1(XBAR_INPUT, 2)    /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03                  IMXRT_XBARA1(XBAR_INPUT, 3)    /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04                  IMXRT_XBARA1(XBAR_INPUT, 4)    /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05                  IMXRT_XBARA1(XBAR_INPUT, 5)    /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06                  IMXRT_XBARA1(XBAR_INPUT, 6)    /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07                  IMXRT_XBARA1(XBAR_INPUT, 7)    /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08                  IMXRT_XBARA1(XBAR_INPUT, 8)    /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09                  IMXRT_XBARA1(XBAR_INPUT, 9)    /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10                  IMXRT_XBARA1(XBAR_INPUT, 10)   /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11                  IMXRT_XBARA1(XBAR_INPUT, 11)   /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12                  IMXRT_XBARA1(XBAR_INPUT, 12)   /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13                  IMXRT_XBARA1(XBAR_INPUT, 13)   /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14                  IMXRT_XBARA1(XBAR_INPUT, 14)   /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15                  IMXRT_XBARA1(XBAR_INPUT, 15)   /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16                  IMXRT_XBARA1(XBAR_INPUT, 16)   /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17                  IMXRT_XBARA1(XBAR_INPUT, 17)   /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18                  IMXRT_XBARA1(XBAR_INPUT, 18)   /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19                  IMXRT_XBARA1(XBAR_INPUT, 19)   /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20                  IMXRT_XBARA1(XBAR_INPUT, 20)   /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21                  IMXRT_XBARA1(XBAR_INPUT, 21)   /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22                  IMXRT_XBARA1(XBAR_INPUT, 22)   /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23                  IMXRT_XBARA1(XBAR_INPUT, 23)   /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24                  IMXRT_XBARA1(XBAR_INPUT, 24)   /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25                  IMXRT_XBARA1(XBAR_INPUT, 25)   /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
+#define IMXRT_XBARA1_IN_ACMP1_OUT                        IMXRT_XBARA1(XBAR_INPUT, 26)   /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
+#define IMXRT_XBARA1_IN_ACMP2_OUT                        IMXRT_XBARA1(XBAR_INPUT, 27)   /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
+#define IMXRT_XBARA1_IN_ACMP3_OUT                        IMXRT_XBARA1(XBAR_INPUT, 28)   /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
+#define IMXRT_XBARA1_IN_ACMP4_OUT                        IMXRT_XBARA1(XBAR_INPUT, 29)   /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
+#define IMXRT_XBARA1_IN_RESERVED30                       IMXRT_XBARA1(XBAR_INPUT, 30)   /* XBARA1_IN30 input is reserved. */
+#define IMXRT_XBARA1_IN_RESERVED31                       IMXRT_XBARA1(XBAR_INPUT, 31)   /* XBARA1_IN31 input is reserved. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 32)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 33)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 34)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 35)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 36)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 37)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 38)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 39)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 48)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 49)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 50)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 51)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 52)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 53)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 54)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 55)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER0                     IMXRT_XBARA1(XBAR_INPUT, 56)   /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER1                     IMXRT_XBARA1(XBAR_INPUT, 57)   /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER2                     IMXRT_XBARA1(XBAR_INPUT, 58)   /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER3                     IMXRT_XBARA1(XBAR_INPUT, 59)   /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
+#define IMXRT_XBARA1_IN_ENC1_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 60)   /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
+#define IMXRT_XBARA1_IN_ENC2_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 61)   /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
+#define IMXRT_XBARA1_IN_ENC3_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 62)   /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
+#define IMXRT_XBARA1_IN_ENC4_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 63)   /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE0                        IMXRT_XBARA1(XBAR_INPUT, 64)   /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE1                        IMXRT_XBARA1(XBAR_INPUT, 65)   /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE2                        IMXRT_XBARA1(XBAR_INPUT, 66)   /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE3                        IMXRT_XBARA1(XBAR_INPUT, 67)   /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE4                        IMXRT_XBARA1(XBAR_INPUT, 68)   /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE5                        IMXRT_XBARA1(XBAR_INPUT, 69)   /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE6                        IMXRT_XBARA1(XBAR_INPUT, 70)   /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE7                        IMXRT_XBARA1(XBAR_INPUT, 71)   /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 72)   /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 73)   /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 74)   /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 75)   /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 76)   /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 77)   /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 78)   /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 79)   /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARA1(XBAR_INPUT, 80)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARA1(XBAR_INPUT, 81)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARA1(XBAR_INPUT, 82)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARA1(XBAR_INPUT, 83)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARA1(XBAR_INPUT, 84)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARA1(XBAR_INPUT, 85)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARA1(XBAR_INPUT, 86)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARA1(XBAR_INPUT, 87)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
+
+/* XBARA1 Mux Output  (M Muxes) ***************************************************************************************************************/
+
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 0)    /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 1)    /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 2)    /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 3)    /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 4)    /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 5)    /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 6)    /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 7)    /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 8)    /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 9)    /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 10)   /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 11)   /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 12)   /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 13)   /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 14)   /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 15)   /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 16)   /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 17)   /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 18)   /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 19)   /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
+#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 20)   /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 21)   /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 22)   /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 23)   /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
+#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 24)   /* XBARA1_OUT24 output is reserved. */
+#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 25)   /* XBARA1_OUT25 output is reserved. */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 26)   /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 27)   /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 28)   /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 29)   /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 30)   /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 31)   /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 32)   /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 33)   /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 34)   /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 35)   /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 36)   /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 37)   /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 38)   /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 39)   /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 40)   /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 41)   /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 42)   /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 43)   /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 44)   /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 45)   /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 46)   /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 47)   /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 48)   /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 49)   /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 50)   /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 51)   /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 52)   /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 53)   /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 54)   /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 55)   /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 56)   /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 57)   /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 58)   /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 59)   /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 60)   /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 61)   /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 62)   /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 63)   /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 64)   /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 65)   /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 66)   /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 67)   /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 68)   /* XBARA1_OUT68 output assigned to ENC1_INDEX */
+#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 69)   /* XBARA1_OUT69 output assigned to ENC1_HOME */
+#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 70)   /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 71)   /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 72)   /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 73)   /* XBARA1_OUT73 output assigned to ENC2_INDEX */
+#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 74)   /* XBARA1_OUT74 output assigned to ENC2_HOME */
+#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 75)   /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 76)   /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 77)   /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 78)   /* XBARA1_OUT78 output assigned to ENC3_INDEX */
+#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 79)   /* XBARA1_OUT79 output assigned to ENC3_HOME */
+#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 80)   /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 81)   /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 82)   /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 83)   /* XBARA1_OUT83 output assigned to ENC4_INDEX */
+#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 84)   /* XBARA1_OUT84 output assigned to ENC4_HOME */
+#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 85)   /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 86)   /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 87)   /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 88)   /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 89)   /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 90)   /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 91)   /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 92)   /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 93)   /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 94)   /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 95)   /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 96)   /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 97)   /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 98)   /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 99)   /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 100)  /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 101)  /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 102)  /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 103)  /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 104)  /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 105)  /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 106)  /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 107)  /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 108)  /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 109)  /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 110)  /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
+#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 111)  /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 112)  /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 113)  /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 114)  /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 115)  /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 116)  /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 117)  /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 118)  /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 119)  /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 120)  /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 121)  /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 122)  /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 123)  /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 124)  /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 125)  /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 126)  /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 127)  /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 128)  /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
+#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 129)  /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 130)  /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
+
+/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB2_IN_LOGIC_LOW                        IMXRT_XBARB2(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
+#define IMXRT_XBARB2_IN_LOGIC_HIGH                       IMXRT_XBARB2(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
+#define IMXRT_XBARB2_IN_RESERVED2                        IMXRT_XBARB2(XBAR_INPUT, 2)    /* XBARB2_IN2 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED3                        IMXRT_XBARB2(XBAR_INPUT, 3)    /* XBARB2_IN3 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED4                        IMXRT_XBARB2(XBAR_INPUT, 4)    /* XBARB2_IN4 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED5                        IMXRT_XBARB2(XBAR_INPUT, 5)    /* XBARB2_IN5 input is reserved. */
+#define IMXRT_XBARB2_IN_ACMP1_OUT                        IMXRT_XBARB2(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
+#define IMXRT_XBARB2_IN_ACMP2_OUT                        IMXRT_XBARB2(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
+#define IMXRT_XBARB2_IN_ACMP3_OUT                        IMXRT_XBARB2(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
+#define IMXRT_XBARB2_IN_ACMP4_OUT                        IMXRT_XBARB2(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
+#define IMXRT_XBARB2_IN_RESERVED10                       IMXRT_XBARB2(XBAR_INPUT, 10)   /* XBARB2_IN10 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED11                       IMXRT_XBARB2(XBAR_INPUT, 11)   /* XBARB2_IN11 input is reserved. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER0                     IMXRT_XBARB2(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER1                     IMXRT_XBARB2(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB2(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB2(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB2(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB2(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB2(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB2(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB2(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB2(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
+#define IMXRT_XBARB2_IN_ENC1_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
+#define IMXRT_XBARB2_IN_ENC2_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
+#define IMXRT_XBARB2_IN_ENC3_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
+#define IMXRT_XBARB2_IN_ENC4_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE0                        IMXRT_XBARB2(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE1                        IMXRT_XBARB2(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE2                        IMXRT_XBARB2(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE3                        IMXRT_XBARB2(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE4                        IMXRT_XBARB2(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE5                        IMXRT_XBARB2(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE6                        IMXRT_XBARB2(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE7                        IMXRT_XBARB2(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
+
+/* XBARB2 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 0)    /* XBARB2_OUT0 output assigned to AOI1_IN00 */
+#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 1)    /* XBARB2_OUT1 output assigned to AOI1_IN01 */
+#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 2)    /* XBARB2_OUT2 output assigned to AOI1_IN02 */
+#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 3)    /* XBARB2_OUT3 output assigned to AOI1_IN03 */
+#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 4)    /* XBARB2_OUT4 output assigned to AOI1_IN04 */
+#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 5)    /* XBARB2_OUT5 output assigned to AOI1_IN05 */
+#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 6)    /* XBARB2_OUT6 output assigned to AOI1_IN06 */
+#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 7)    /* XBARB2_OUT7 output assigned to AOI1_IN07 */
+#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 8)    /* XBARB2_OUT8 output assigned to AOI1_IN08 */
+#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 9)    /* XBARB2_OUT9 output assigned to AOI1_IN09 */
+#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 10)   /* XBARB2_OUT10 output assigned to AOI1_IN10 */
+#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 11)   /* XBARB2_OUT11 output assigned to AOI1_IN11 */
+#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 12)   /* XBARB2_OUT12 output assigned to AOI1_IN12 */
+#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 13)   /* XBARB2_OUT13 output assigned to AOI1_IN13 */
+#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 14)   /* XBARB2_OUT14 output assigned to AOI1_IN14 */
+#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 15)   /* XBARB2_OUT15 output assigned to AOI1_IN15 */
+
+/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB3_IN_LOGIC_LOW                        IMXRT_XBARB3(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB3_IN0 input. */
+#define IMXRT_XBARB3_IN_LOGIC_HIGH                       IMXRT_XBARB3(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */
+#define IMXRT_XBARB3_IN_RESERVED2                        IMXRT_XBARB3(XBAR_INPUT, 2)    /* XBARB3_IN2 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED3                        IMXRT_XBARB3(XBAR_INPUT, 3)    /* XBARB3_IN3 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED4                        IMXRT_XBARB3(XBAR_INPUT, 4)    /* XBARB3_IN4 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED5                        IMXRT_XBARB3(XBAR_INPUT, 5)    /* XBARB3_IN5 input is reserved. */
+#define IMXRT_XBARB3_IN_ACMP1_OUT                        IMXRT_XBARB3(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB3_IN6 input. */
+#define IMXRT_XBARB3_IN_ACMP2_OUT                        IMXRT_XBARB3(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB3_IN7 input. */
+#define IMXRT_XBARB3_IN_ACMP3_OUT                        IMXRT_XBARB3(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB3_IN8 input. */
+#define IMXRT_XBARB3_IN_ACMP4_OUT                        IMXRT_XBARB3(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB3_IN9 input. */
+#define IMXRT_XBARB3_IN_RESERVED10                       IMXRT_XBARB3(XBAR_INPUT, 10)   /* XBARB3_IN10 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED11                       IMXRT_XBARB3(XBAR_INPUT, 11)   /* XBARB3_IN11 input is reserved. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
+#define IMXRT_XBARB3_IN_PIT_TRIGGER0                     IMXRT_XBARB3(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
+#define IMXRT_XBARB3_IN_PIT_TRIGGER1                     IMXRT_XBARB3(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB3(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB3(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB3(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB3(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB3(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB3(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB3(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB3(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
+#define IMXRT_XBARB3_IN_ENC1_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
+#define IMXRT_XBARB3_IN_ENC2_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
+#define IMXRT_XBARB3_IN_ENC3_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
+#define IMXRT_XBARB3_IN_ENC4_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE0                        IMXRT_XBARB3(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB3_IN50 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE1                        IMXRT_XBARB3(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB3_IN51 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE2                        IMXRT_XBARB3(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB3_IN52 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE3                        IMXRT_XBARB3(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB3_IN53 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE4                        IMXRT_XBARB3(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB3_IN54 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE5                        IMXRT_XBARB3(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB3_IN55 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE6                        IMXRT_XBARB3(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB3_IN56 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE7                        IMXRT_XBARB3(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB3_IN57 input. */
+
+/* XBARB3 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 0)    /* XBARB3_OUT0 output assigned to AOI2_IN00 */
+#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 1)    /* XBARB3_OUT1 output assigned to AOI2_IN01 */
+#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 2)    /* XBARB3_OUT2 output assigned to AOI2_IN02 */
+#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 3)    /* XBARB3_OUT3 output assigned to AOI2_IN03 */
+#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 4)    /* XBARB3_OUT4 output assigned to AOI2_IN04 */
+#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 5)    /* XBARB3_OUT5 output assigned to AOI2_IN05 */
+#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 6)    /* XBARB3_OUT6 output assigned to AOI2_IN06 */
+#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 7)    /* XBARB3_OUT7 output assigned to AOI2_IN07 */
+#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 8)    /* XBARB3_OUT8 output assigned to AOI2_IN08 */
+#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 9)    /* XBARB3_OUT9 output assigned to AOI2_IN09 */
+#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 10)   /* XBARB3_OUT10 output assigned to AOI2_IN10 */
+#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 11)   /* XBARB3_OUT11 output assigned to AOI2_IN11 */
+#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 12)   /* XBARB3_OUT12 output assigned to AOI2_IN12 */
+#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 13)   /* XBARB3_OUT13 output assigned to AOI2_IN13 */
+#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 14)   /* XBARB3_OUT14 output assigned to AOI2_IN14 */
+#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 15)   /* XBARB3_OUT15 output assigned to AOI2_IN15 */
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt106x_dmamux.h
+ * arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt106x_gpio.h
+ * arch/arm/src/imxrt/rt106x/imxrt106x_gpio.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/imxrt_iomuxc.h
+ * arch/arm/src/imxrt/rt106x/imxrt106x_iomuxc.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Author:  Gregory Nutt <gnutt@nuttx.org>
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h
+ * arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -1,5 +1,5 @@
 /*****************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_pinmux.h
+ * arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -0,0 +1,386 @@
+/* XBAR Defines for IMXRT1060 */
+
+/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
+
+#define IMXRT_XBARA1_IN_LOGIC_LOW                        IMXRT_XBARA1(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
+#define IMXRT_XBARA1_IN_LOGIC_HIGH                       IMXRT_XBARA1(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02                  IMXRT_XBARA1(XBAR_INPUT, 2)    /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03                  IMXRT_XBARA1(XBAR_INPUT, 3)    /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04                  IMXRT_XBARA1(XBAR_INPUT, 4)    /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05                  IMXRT_XBARA1(XBAR_INPUT, 5)    /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06                  IMXRT_XBARA1(XBAR_INPUT, 6)    /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07                  IMXRT_XBARA1(XBAR_INPUT, 7)    /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08                  IMXRT_XBARA1(XBAR_INPUT, 8)    /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09                  IMXRT_XBARA1(XBAR_INPUT, 9)    /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10                  IMXRT_XBARA1(XBAR_INPUT, 10)   /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11                  IMXRT_XBARA1(XBAR_INPUT, 11)   /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12                  IMXRT_XBARA1(XBAR_INPUT, 12)   /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13                  IMXRT_XBARA1(XBAR_INPUT, 13)   /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14                  IMXRT_XBARA1(XBAR_INPUT, 14)   /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15                  IMXRT_XBARA1(XBAR_INPUT, 15)   /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16                  IMXRT_XBARA1(XBAR_INPUT, 16)   /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17                  IMXRT_XBARA1(XBAR_INPUT, 17)   /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18                  IMXRT_XBARA1(XBAR_INPUT, 18)   /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19                  IMXRT_XBARA1(XBAR_INPUT, 19)   /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20                  IMXRT_XBARA1(XBAR_INPUT, 20)   /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21                  IMXRT_XBARA1(XBAR_INPUT, 21)   /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22                  IMXRT_XBARA1(XBAR_INPUT, 22)   /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23                  IMXRT_XBARA1(XBAR_INPUT, 23)   /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24                  IMXRT_XBARA1(XBAR_INPUT, 24)   /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25                  IMXRT_XBARA1(XBAR_INPUT, 25)   /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
+#define IMXRT_XBARA1_IN_ACMP1_OUT                        IMXRT_XBARA1(XBAR_INPUT, 26)   /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
+#define IMXRT_XBARA1_IN_ACMP2_OUT                        IMXRT_XBARA1(XBAR_INPUT, 27)   /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
+#define IMXRT_XBARA1_IN_ACMP3_OUT                        IMXRT_XBARA1(XBAR_INPUT, 28)   /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
+#define IMXRT_XBARA1_IN_ACMP4_OUT                        IMXRT_XBARA1(XBAR_INPUT, 29)   /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
+#define IMXRT_XBARA1_IN_RESERVED30                       IMXRT_XBARA1(XBAR_INPUT, 30)   /* XBARA1_IN30 input is reserved. */
+#define IMXRT_XBARA1_IN_RESERVED31                       IMXRT_XBARA1(XBAR_INPUT, 31)   /* XBARA1_IN31 input is reserved. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 32)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 33)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 34)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 35)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 36)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 37)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 38)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 39)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 48)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 49)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 50)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 51)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 52)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 53)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 54)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 55)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER0                     IMXRT_XBARA1(XBAR_INPUT, 56)   /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER1                     IMXRT_XBARA1(XBAR_INPUT, 57)   /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER2                     IMXRT_XBARA1(XBAR_INPUT, 58)   /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER3                     IMXRT_XBARA1(XBAR_INPUT, 59)   /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
+#define IMXRT_XBARA1_IN_ENC1_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 60)   /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
+#define IMXRT_XBARA1_IN_ENC2_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 61)   /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
+#define IMXRT_XBARA1_IN_ENC3_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 62)   /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
+#define IMXRT_XBARA1_IN_ENC4_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 63)   /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE0                        IMXRT_XBARA1(XBAR_INPUT, 64)   /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE1                        IMXRT_XBARA1(XBAR_INPUT, 65)   /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE2                        IMXRT_XBARA1(XBAR_INPUT, 66)   /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE3                        IMXRT_XBARA1(XBAR_INPUT, 67)   /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE4                        IMXRT_XBARA1(XBAR_INPUT, 68)   /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE5                        IMXRT_XBARA1(XBAR_INPUT, 69)   /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE6                        IMXRT_XBARA1(XBAR_INPUT, 70)   /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE7                        IMXRT_XBARA1(XBAR_INPUT, 71)   /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 72)   /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 73)   /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 74)   /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 75)   /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 76)   /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 77)   /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 78)   /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 79)   /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARA1(XBAR_INPUT, 80)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARA1(XBAR_INPUT, 81)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARA1(XBAR_INPUT, 82)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARA1(XBAR_INPUT, 83)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARA1(XBAR_INPUT, 84)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARA1(XBAR_INPUT, 85)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARA1(XBAR_INPUT, 86)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARA1(XBAR_INPUT, 87)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
+
+/* XBARA1 Mux Output  (M Muxes) ***************************************************************************************************************/
+
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 0)    /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 1)    /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 2)    /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 3)    /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 4)    /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 5)    /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 6)    /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 7)    /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 8)    /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 9)    /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 10)   /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 11)   /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 12)   /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 13)   /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 14)   /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 15)   /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 16)   /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 17)   /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 18)   /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 19)   /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
+#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 20)   /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 21)   /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 22)   /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 23)   /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
+#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 24)   /* XBARA1_OUT24 output is reserved. */
+#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 25)   /* XBARA1_OUT25 output is reserved. */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 26)   /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 27)   /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 28)   /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 29)   /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 30)   /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 31)   /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 32)   /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 33)   /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 34)   /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 35)   /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 36)   /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 37)   /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 38)   /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 39)   /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 40)   /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 41)   /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 42)   /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 43)   /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 44)   /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 45)   /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 46)   /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 47)   /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 48)   /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 49)   /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 50)   /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 51)   /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 52)   /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 53)   /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 54)   /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 55)   /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 56)   /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 57)   /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 58)   /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 59)   /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 60)   /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 61)   /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 62)   /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 63)   /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 64)   /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 65)   /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 66)   /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 67)   /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 68)   /* XBARA1_OUT68 output assigned to ENC1_INDEX */
+#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 69)   /* XBARA1_OUT69 output assigned to ENC1_HOME */
+#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 70)   /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 71)   /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 72)   /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 73)   /* XBARA1_OUT73 output assigned to ENC2_INDEX */
+#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 74)   /* XBARA1_OUT74 output assigned to ENC2_HOME */
+#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 75)   /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 76)   /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 77)   /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 78)   /* XBARA1_OUT78 output assigned to ENC3_INDEX */
+#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 79)   /* XBARA1_OUT79 output assigned to ENC3_HOME */
+#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 80)   /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 81)   /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 82)   /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 83)   /* XBARA1_OUT83 output assigned to ENC4_INDEX */
+#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 84)   /* XBARA1_OUT84 output assigned to ENC4_HOME */
+#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 85)   /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 86)   /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 87)   /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 88)   /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 89)   /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 90)   /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 91)   /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 92)   /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 93)   /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 94)   /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 95)   /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 96)   /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 97)   /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 98)   /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 99)   /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 100)  /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 101)  /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 102)  /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 103)  /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 104)  /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 105)  /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 106)  /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 107)  /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 108)  /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 109)  /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 110)  /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
+#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 111)  /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 112)  /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 113)  /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 114)  /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 115)  /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 116)  /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 117)  /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 118)  /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 119)  /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 120)  /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 121)  /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 122)  /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 123)  /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 124)  /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 125)  /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 126)  /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 127)  /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 128)  /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
+#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 129)  /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 130)  /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
+
+/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB2_IN_LOGIC_LOW                        IMXRT_XBARB2(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
+#define IMXRT_XBARB2_IN_LOGIC_HIGH                       IMXRT_XBARB2(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
+#define IMXRT_XBARB2_IN_RESERVED2                        IMXRT_XBARB2(XBAR_INPUT, 2)    /* XBARB2_IN2 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED3                        IMXRT_XBARB2(XBAR_INPUT, 3)    /* XBARB2_IN3 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED4                        IMXRT_XBARB2(XBAR_INPUT, 4)    /* XBARB2_IN4 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED5                        IMXRT_XBARB2(XBAR_INPUT, 5)    /* XBARB2_IN5 input is reserved. */
+#define IMXRT_XBARB2_IN_ACMP1_OUT                        IMXRT_XBARB2(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
+#define IMXRT_XBARB2_IN_ACMP2_OUT                        IMXRT_XBARB2(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
+#define IMXRT_XBARB2_IN_ACMP3_OUT                        IMXRT_XBARB2(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
+#define IMXRT_XBARB2_IN_ACMP4_OUT                        IMXRT_XBARB2(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
+#define IMXRT_XBARB2_IN_RESERVED10                       IMXRT_XBARB2(XBAR_INPUT, 10)   /* XBARB2_IN10 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED11                       IMXRT_XBARB2(XBAR_INPUT, 11)   /* XBARB2_IN11 input is reserved. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER0                     IMXRT_XBARB2(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER1                     IMXRT_XBARB2(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB2(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB2(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB2(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB2(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB2(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB2(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB2(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB2(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
+#define IMXRT_XBARB2_IN_ENC1_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
+#define IMXRT_XBARB2_IN_ENC2_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
+#define IMXRT_XBARB2_IN_ENC3_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
+#define IMXRT_XBARB2_IN_ENC4_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE0                        IMXRT_XBARB2(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE1                        IMXRT_XBARB2(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE2                        IMXRT_XBARB2(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE3                        IMXRT_XBARB2(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE4                        IMXRT_XBARB2(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE5                        IMXRT_XBARB2(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE6                        IMXRT_XBARB2(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE7                        IMXRT_XBARB2(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
+
+/* XBARB2 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 0)    /* XBARB2_OUT0 output assigned to AOI1_IN00 */
+#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 1)    /* XBARB2_OUT1 output assigned to AOI1_IN01 */
+#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 2)    /* XBARB2_OUT2 output assigned to AOI1_IN02 */
+#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 3)    /* XBARB2_OUT3 output assigned to AOI1_IN03 */
+#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 4)    /* XBARB2_OUT4 output assigned to AOI1_IN04 */
+#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 5)    /* XBARB2_OUT5 output assigned to AOI1_IN05 */
+#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 6)    /* XBARB2_OUT6 output assigned to AOI1_IN06 */
+#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 7)    /* XBARB2_OUT7 output assigned to AOI1_IN07 */
+#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 8)    /* XBARB2_OUT8 output assigned to AOI1_IN08 */
+#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 9)    /* XBARB2_OUT9 output assigned to AOI1_IN09 */
+#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 10)   /* XBARB2_OUT10 output assigned to AOI1_IN10 */
+#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 11)   /* XBARB2_OUT11 output assigned to AOI1_IN11 */
+#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 12)   /* XBARB2_OUT12 output assigned to AOI1_IN12 */
+#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 13)   /* XBARB2_OUT13 output assigned to AOI1_IN13 */
+#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 14)   /* XBARB2_OUT14 output assigned to AOI1_IN14 */
+#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 15)   /* XBARB2_OUT15 output assigned to AOI1_IN15 */
+
+/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB3_IN_LOGIC_LOW                        IMXRT_XBARB3(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB3_IN0 input. */
+#define IMXRT_XBARB3_IN_LOGIC_HIGH                       IMXRT_XBARB3(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */
+#define IMXRT_XBARB3_IN_RESERVED2                        IMXRT_XBARB3(XBAR_INPUT, 2)    /* XBARB3_IN2 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED3                        IMXRT_XBARB3(XBAR_INPUT, 3)    /* XBARB3_IN3 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED4                        IMXRT_XBARB3(XBAR_INPUT, 4)    /* XBARB3_IN4 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED5                        IMXRT_XBARB3(XBAR_INPUT, 5)    /* XBARB3_IN5 input is reserved. */
+#define IMXRT_XBARB3_IN_ACMP1_OUT                        IMXRT_XBARB3(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB3_IN6 input. */
+#define IMXRT_XBARB3_IN_ACMP2_OUT                        IMXRT_XBARB3(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB3_IN7 input. */
+#define IMXRT_XBARB3_IN_ACMP3_OUT                        IMXRT_XBARB3(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB3_IN8 input. */
+#define IMXRT_XBARB3_IN_ACMP4_OUT                        IMXRT_XBARB3(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB3_IN9 input. */
+#define IMXRT_XBARB3_IN_RESERVED10                       IMXRT_XBARB3(XBAR_INPUT, 10)   /* XBARB3_IN10 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED11                       IMXRT_XBARB3(XBAR_INPUT, 11)   /* XBARB3_IN11 input is reserved. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
+#define IMXRT_XBARB3_IN_PIT_TRIGGER0                     IMXRT_XBARB3(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
+#define IMXRT_XBARB3_IN_PIT_TRIGGER1                     IMXRT_XBARB3(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB3(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB3(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB3(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB3(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB3(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB3(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB3(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB3(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
+#define IMXRT_XBARB3_IN_ENC1_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
+#define IMXRT_XBARB3_IN_ENC2_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
+#define IMXRT_XBARB3_IN_ENC3_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
+#define IMXRT_XBARB3_IN_ENC4_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE0                        IMXRT_XBARB3(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB3_IN50 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE1                        IMXRT_XBARB3(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB3_IN51 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE2                        IMXRT_XBARB3(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB3_IN52 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE3                        IMXRT_XBARB3(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB3_IN53 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE4                        IMXRT_XBARB3(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB3_IN54 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE5                        IMXRT_XBARB3(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB3_IN55 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE6                        IMXRT_XBARB3(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB3_IN56 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE7                        IMXRT_XBARB3(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB3_IN57 input. */
+
+/* XBARB3 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 0)    /* XBARB3_OUT0 output assigned to AOI2_IN00 */
+#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 1)    /* XBARB3_OUT1 output assigned to AOI2_IN01 */
+#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 2)    /* XBARB3_OUT2 output assigned to AOI2_IN02 */
+#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 3)    /* XBARB3_OUT3 output assigned to AOI2_IN03 */
+#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 4)    /* XBARB3_OUT4 output assigned to AOI2_IN04 */
+#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 5)    /* XBARB3_OUT5 output assigned to AOI2_IN05 */
+#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 6)    /* XBARB3_OUT6 output assigned to AOI2_IN06 */
+#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 7)    /* XBARB3_OUT7 output assigned to AOI2_IN07 */
+#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 8)    /* XBARB3_OUT8 output assigned to AOI2_IN08 */
+#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 9)    /* XBARB3_OUT9 output assigned to AOI2_IN09 */
+#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 10)   /* XBARB3_OUT10 output assigned to AOI2_IN10 */
+#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 11)   /* XBARB3_OUT11 output assigned to AOI2_IN11 */
+#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 12)   /* XBARB3_OUT12 output assigned to AOI2_IN12 */
+#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 13)   /* XBARB3_OUT13 output assigned to AOI2_IN13 */
+#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 14)   /* XBARB3_OUT14 output assigned to AOI2_IN14 */
+#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 15)   /* XBARB3_OUT15 output assigned to AOI2_IN15 */
@@ -1,10 +1,11 @@
 /****************************************************************************
 * arch/arm/src/imxrt/imxrt_clockconfig.c
 *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
 *   Authors:  Janne Rosberg <janne@offcode.fi>
 *             Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
 *             David Sidrane <david_s5@nscdg.com>
+ *             Dave Marples <dave@marples.net>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -217,11 +218,124 @@ static void imxrt_lcd_clockconfig(void)

  modifyreg32(IMXRT_CCM_CBCMR, CCM_CBCMR_LCDIF_PODF_MASK,
      CCM_CBCMR_LCDIF_PODF(post_divider));
-
 }

 #endif

+/****************************************************************************
+ * Name: imxrt_pllsetup
+ ****************************************************************************/
+
+static void imxrt_pllsetup(void)
+
+{
+  uint32_t reg;
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x))
+
+  /* Init Arm PLL1 */
+
+  reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) |
+        CCM_ANALOG_PLL_ARM_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
+    {
+    }
+
+  /* Init Sys PLL2 */
+
+  reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) |
+        CCM_ANALOG_PLL_SYS_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
+    {
+    }
+
+#ifdef CONFIG_IMXRT_LCD
+  /* Init Video PLL5 */
+
+  imxrt_lcd_clockconfig();
+#endif
+
+  /* Init ENET PLL6 */
+
+  reg    = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ | CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
+           CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN | CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN |
+           CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ;
+
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
+
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0)
+    {
+    }
+
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+  /* Init Sys PLL2 */
+  /* First reset its fractional dividers */
+
+  uint32_t pll2reg=getreg32(IMXRT_CCM_ANALOG_PFD_528);
+    putreg32(pll2reg |
+             CCM_ANALOG_PFD_528_PFD0_CLKGATE |
+             CCM_ANALOG_PFD_528_PFD1_CLKGATE |
+             CCM_ANALOG_PFD_528_PFD2_CLKGATE |
+             CCM_ANALOG_PFD_528_PFD3_CLKGATE,
+             IMXRT_CCM_ANALOG_PFD_528 );
+
+  reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_DIV_SELECT) |
+        CCM_ANALOG_PLL_SYS_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
+    {
+    }
+
+  putreg32(pll2reg,IMXRT_CCM_ANALOG_PFD_528);
+
+  /* Init USB PLL3 */
+  /* capture it's original value */
+
+  uint32_t pll3reg=getreg32(IMXRT_CCM_ANALOG_PFD_480);
+  putreg32(pll3reg |
+            CCM_ANALOG_PFD_480_PFD0_CLKGATE |
+            CCM_ANALOG_PFD_480_PFD1_CLKGATE |
+            CCM_ANALOG_PFD_480_PFD2_CLKGATE |
+            CCM_ANALOG_PFD_480_PFD3_CLKGATE,
+            IMXRT_CCM_ANALOG_PFD_480 );
+
+  reg = CCM_ANALOG_PLL_USB1_DIV_SELECT(IMXRT_USB1_PLL_DIV_SELECT) |
+        CCM_ANALOG_PLL_USB1_ENABLE | CCM_ANALOG_PLL_USB1_EN_USB_CLKS |
+        CCM_ANALOG_PLL_USB1_POWER;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB1);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & CCM_ANALOG_PLL_USB1_LOCK) == 0)
+    {
+    }
+
+  putreg32(pll3reg,IMXRT_CCM_ANALOG_PFD_480);
+
+  /* Init Audio PLL4 */
+
+  reg = CCM_ANALOG_PLL_AUDIO_DIV_SELECT(IMXRT_AUDIO_PLL_DIV_SELECT) |
+        CCM_ANALOG_PLL_AUDIO_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_AUDIO);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_AUDIO) & CCM_ANALOG_PLL_AUDIO_LOCK) == 0)
+    {
+    }
+
+  /* Init ENET PLL6 */
+
+  reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ | CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
+        CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN | CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN;
+
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
+
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0)
+    {
+    }
+
+#else
+#error Unrecognised IMXRT family member for clock config
+#endif
+
+}
+
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
@@ -276,31 +390,9 @@ void imxrt_clockconfig(void)
  reg |= DCDC_REG3_TRG(IMXRT_VDD_SOC);
  putreg32(reg, IMXRT_DCDC_REG3);

-  /* Init Arm PLL1 */
+  /* OK, now nothing is depending on us, configure the PLLs */

-  reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) |
-        CCM_ANALOG_PLL_ARM_ENABLE;
-  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
-  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
-    {
-    }
-
-  /* Init Sys PLL2 */
-
-  reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) |
-        CCM_ANALOG_PLL_SYS_ENABLE;
-  putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
-  while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
-    {
-    }
-
-#ifdef CONFIG_IMXRT_LCD
-  /* Init Video PLL5 */
-
-  imxrt_lcd_clockconfig();
-#endif
-
-  /* TODO: other pll configs */
+  imxrt_pllsetup();

  /* Set Dividers */

@@ -325,7 +417,7 @@ void imxrt_clockconfig(void)
  putreg32(reg, IMXRT_CCM_CSCMR1);

 #ifndef CONFIG_IMXRT_SEMC_INIT_DONE
-  /* Configure SEMC Clock only if not already done by DCD SDRAM init. */
+  /* Configure SEMC Clock only if not already done by DCD SDR */

  reg  = getreg32(IMXRT_CCM_CBCDR);
  reg &= ~CCM_CBCDR_SEMC_PODF_MASK;
@@ -390,7 +482,7 @@ void imxrt_clockconfig(void)

  reg  = getreg32(IMXRT_CCM_CSCDR2);
  reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK;
-  reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5);
+  reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5-1);
  putreg32(reg, IMXRT_CCM_CSCDR2);

  while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
@@ -79,7 +79,9 @@ struct imxrt_daisy_t

 /* Include chip-specific daisy input selection */

-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "imxrt102x_daisy.c"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
 #  include "imxrt105x_daisy.c"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
 #  include "imxrt106x_daisy.c"
@@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/imxrt/imxrt_enet.c
 *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -185,6 +185,9 @@
 *    value into a boolean: true=duplex mode, false=half-duplex mode
 *
 * The imxrt1050-evk board uses a KSZ8081 PHY
+ * The Versiboard2 uses a LAN8720 PHY
+ *
+ * ...and further PHY descriptions here.
 */

 #if defined(CONFIG_ETH0_PHY_KSZ8081)
@@ -196,6 +199,15 @@
 #  define BOARD_PHY_10BASET(s)  (((s) & MII_PHYCTRL1_MODE_10HDX) != 0)
 #  define BOARD_PHY_100BASET(s) (((s) & MII_PHYCTRL1_MODE_100HDX) != 0)
 #  define BOARD_PHY_ISDUPLEX(s) (((s) & MII_PHYCTRL1_MODE_DUPLEX) != 0)
+#elif defined(CONFIG_ETH0_PHY_LAN8720)
+#  define BOARD_PHY_NAME        "LAN8720"
+#  define BOARD_PHYID1          MII_PHYID1_LAN8720
+#  define BOARD_PHYID2          MII_PHYID2_LAN8720
+#  define BOARD_PHY_STATUS      MII_LAN8720_SCSR
+#  define BOARD_PHY_ADDR        (1)
+#  define BOARD_PHY_10BASET(s)  (((s)&MII_LAN8720_SPSCR_10MBPS) != 0)
+#  define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0)
+#  define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0)
 #else
 #  error "Unrecognized or missing PHY selection"
 #endif
@@ -566,8 +578,9 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
 * Function: imxrt_txpoll
 *
 * Description:
- *   The transmitter is available, check if the network has any outgoing packets ready
- *   to send.  This is a callback from devif_poll().  devif_poll() may be called:
+ *   The transmitter is available, check if the network has any outgoing
+ *   packets ready to send.  This is a callback from devif_poll().
+ *   devif_poll() may be called:
 *
 *   1. When the preceding TX packet send is complete,
 *   2. When the preceding TX packet send timesout and the interface is reset
@@ -627,8 +640,8 @@ static int imxrt_txpoll(struct net_driver_s *dev)
          priv->dev.d_buf =
            (uint8_t *)imxrt_swap32((uint32_t)priv->txdesc[priv->txhead].data);

-          /* Check if there is room in the device to hold another packet. If not,
-           * return a non-zero value to terminate the poll.
+          /* Check if there is room in the device to hold another packet. If
+           * not, return a non-zero value to terminate the poll.
           */

          if (imxrt_txringfull(priv))
@@ -976,8 +989,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
  FAR struct imxrt_driver_s *priv = (FAR struct imxrt_driver_s *)arg;
  uint32_t pending;
 #ifdef CONFIG_NET_MCASTGROUP
-  uint32_t gaurStore;
-  uint32_t galrStore;
+  uint32_t gaurstore;
+  uint32_t galrstore;
 #endif

  /* Process pending Ethernet interrupts */
@@ -1017,8 +1030,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
       * multicast hash table.
       */

-      gaurStore = getreg32(IMXRT_ENET_GAUR);
-      galrStore = getreg32(IMXRT_ENET_GALR);
+      gaurstore = getreg32(IMXRT_ENET_GAUR);
+      galrstore = getreg32(IMXRT_ENET_GALR);
 #endif

      (void)imxrt_ifdown(&priv->dev);
@@ -1027,8 +1040,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
 #ifdef CONFIG_NET_MCASTGROUP
      /* Now write the multicast table back */

-      putreg32(gaurStore, IMXRT_ENET_GAUR);
-      putreg32(galrStore, IMXRT_ENET_GALR);
+      putreg32(gaurstore, IMXRT_ENET_GAUR);
+      putreg32(galrstore, IMXRT_ENET_GALR);
 #endif

      /* Then poll the network for new XMIT data */
@@ -1489,8 +1502,8 @@ static void imxrt_txavail_work(FAR void *arg)

      if (!imxrt_txringfull(priv))
        {
-          /* No, there is space for another transfer.  Poll the network for new
-           * XMIT data.
+          /* No, there is space for another transfer.  Poll the network for
+           * new XMIT data.
           */

          (void)devif_poll(&priv->dev, imxrt_txpoll);
@@ -1558,7 +1571,7 @@ static int imxrt_txavail(struct net_driver_s *dev)
 #ifdef CONFIG_NET_MCASTGROUP
 static uint32_t imxrt_calcethcrc(const uint8_t *data, size_t length)
 {
-  uint32_t crc    = 0xFFFFFFFFU;
+  uint32_t crc    = 0xffffffffu;
  uint32_t count1 = 0;
  uint32_t count2 = 0;

@@ -1568,13 +1581,13 @@ static uint32_t imxrt_calcethcrc(const uint8_t *data, size_t length)
    {
      uint8_t c = data[count1];

-      for (count2 = 0; count2 < 0x08U; count2++)
+      for (count2 = 0; count2 < 0x08u; count2++)
        {
          if ((c ^ crc) & 1U)
            {
              crc >>= 1U;
              c   >>= 1U;
-              crc  ^= 0xEDB88320U;
+              crc  ^= 0xedb88320u;
            }
          else
            {
@@ -1614,7 +1627,7 @@ static uint32_t imxrt_enet_hash_index(const uint8_t *mac)
        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);

  crc = imxrt_calcethcrc(mac, 6);
-  hashindex = (crc >> 26) & 0x3F;
+  hashindex = (crc >> 26) & 0x3f;

  return hashindex;
 }
@@ -1672,8 +1685,8 @@ static int imxrt_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
 * Function: imxrt_rmmac
 *
 * Description:
- *   NuttX Callback: Remove the specified MAC address from the hardware multicast
- *   address filtering
+ *   NuttX Callback: Remove the specified MAC address from the hardware
+ *   multicast address filtering
 *
 * Input Parameters:
 *   dev  - Reference to the NuttX driver state structure
@@ -1747,9 +1760,10 @@ static int imxrt_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
    {
 #ifdef CONFIG_NETDEV_PHY_IOCTL
 #ifdef CONFIG_ARCH_PHY_INTERRUPT
-  case SIOCMIINOTIFY: /* Set up for PHY event notifications */
-    {
-          struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg);
+      case SIOCMIINOTIFY: /* Set up for PHY event notifications */
+        {
+          struct mii_ioctl_notify_s *req =
+            (struct mii_ioctl_notify_s *)((uintptr_t)arg);

          ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
          if (ret == OK)
@@ -1834,7 +1848,7 @@ static int imxrt_phyintenable(struct imxrt_driver_s *priv)
      /* Enable link up/down interrupts */

      ret = imxrt_writemii(priv, priv->phyaddr, MII_KSZ8081_INT,
-                           (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                           (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
    }

  return ret;
@@ -2025,7 +2039,8 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
  if (renogphy)
    {
      /* Loop (potentially infinitely?) until we successfully communicate with
-       * the PHY.
+       * the PHY. This is 'standard stuff' that should work for any PHY - we
+       * are not communicating with it's 'special' registers at this point.
       */

      ninfo("%s: Try phyaddr: %u\n", BOARD_PHY_NAME, phyaddr);
@@ -2047,7 +2062,7 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)

      if (retries >= 3)
        {
-          nerr("ERROR: Failed to read %s PHYID1 at address %d\n", phyaddr);
+          nerr("ERROR: Failed to read %s PHYID1 at address %d\n", BOARD_PHY_NAME, phyaddr);
          return -ENOENT;
        }

@@ -2086,6 +2101,7 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
          return -ENXIO;
        }

+#ifdef CONFIG_ETH0_PHY_KSZ8081
      /* Reset PHY */

      imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
@@ -2116,6 +2132,31 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
      imxrt_writemii(priv, phyaddr, MII_KSZ8081_OMSO,
                     (phydata & ~(1 << 5)));

+      /* Set Ethernet led to green = activity and yellow = link and  */
+
+      ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata);
+      if (ret < 0)
+        {
+          nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n");
+          return ret;
+        }
+
+      imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2,
+                     (phydata | (1 << 4)));
+
+#elif defined (CONFIG_ETH0_PHY_LAN8720)
+
+        /* Make sure that PHY comes up in correct mode when it's reset */
+
+        imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES,
+               MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL |
+               MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR));
+
+        /* ...and reset PHY */
+
+        imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
+#endif
+
      /* Start auto negotiation */

      ninfo("%s: Start Autonegotiation...\n",  BOARD_PHY_NAME);
@@ -2163,18 +2204,6 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)

          imxrt_writemii(priv, phyaddr, MII_MCR, 0);
        }
-
-      /* Set Ethernet led to green = activity and yellow = link and  */
-
-      ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata);
-      if (ret < 0)
-        {
-          nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n");
-          return ret;
-        }
-
-      imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2,
-                     (phydata | (1 << 4)));
    }

  /* When we get here we have a (negotiated) speed and duplex. This is also
@@ -2349,8 +2378,8 @@ static void imxrt_initbuffers(struct imxrt_driver_s *priv)

  /* Set the wrap bit in the last descriptors to form a ring */

-  priv->txdesc[CONFIG_IMXRT_ENET_NTXBUFFERS-1].status1 |= TXDESC_W;
-  priv->rxdesc[CONFIG_IMXRT_ENET_NRXBUFFERS-1].status1 |= RXDESC_W;
+  priv->txdesc[CONFIG_IMXRT_ENET_NTXBUFFERS - 1].status1 |= TXDESC_W;
+  priv->rxdesc[CONFIG_IMXRT_ENET_NRXBUFFERS - 1].status1 |= RXDESC_W;

  /* We start with RX descriptor 0 and with no TX descriptors in use */

@@ -2433,19 +2462,7 @@ int imxrt_netinitialize(int intf)
  DEBUGASSERT(intf < CONFIG_IMXRT_ENET_NETHIFS);
  priv = &g_enet[intf];

-  /* Init ENET PLL6 */
-
-  regval = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
-           CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ |
-           CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M |
-           CCM_ANALOG_PLL_ENET_ENET1_125M_EN;
-  putreg32(regval, IMXRT_CCM_ANALOG_PLL_ENET);
-
-  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0)
-    {
-    }
-
-  /* Enable ENET1_TX_CLK_DIR */
+  /* Enable ENET1_TX_CLK_DIR (Provides 50MHz clk OUT to PHY) */

  regval = getreg32(IMXRT_IOMUXC_GPR_GPR1);
  regval |= GPR_GPR1_ENET1_TX_CLK_OUT_EN;
@@ -2457,25 +2474,18 @@ int imxrt_netinitialize(int intf)

  /* Configure all ENET/MII pins */

-  imxrt_config_gpio(GPIO_ENET_MDIO_3);
-  imxrt_config_gpio(GPIO_ENET_MDC_3);
-  imxrt_config_gpio(GPIO_ENET_RX_EN_1);
-  imxrt_config_gpio(GPIO_ENET_RX_ER_1);
-  imxrt_config_gpio(GPIO_ENET_RX_DATA00);
-  imxrt_config_gpio(GPIO_ENET_RX_DATA01);
-  imxrt_config_gpio(GPIO_ENET_TX_DATA00);
-  imxrt_config_gpio(GPIO_ENET_TX_DATA01);
-  imxrt_config_gpio(GPIO_ENET_TX_CLK_1);
-  imxrt_config_gpio(GPIO_ENET_TX_EN_1);
-
-  /* Configure daisy chain pins */
-
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_MDIO_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET0_RXDATA_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET1_RXDATA_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXEN_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXERR_OFFSET);
+  imxrt_config_gpio(GPIO_ENET_MDIO);
+  imxrt_config_gpio(GPIO_ENET_MDC);
+  imxrt_config_gpio(GPIO_ENET_RX_EN);
+  imxrt_config_gpio(GPIO_ENET_RDATA00);
+  imxrt_config_gpio(GPIO_ENET_RDATA01);
+  imxrt_config_gpio(GPIO_ENET_TDATA00);
+  imxrt_config_gpio(GPIO_ENET_TDATA01);
+  imxrt_config_gpio(GPIO_ENET_TX_CLK);
+  imxrt_config_gpio(GPIO_ENET_TX_EN);
+#ifdef GPIO_ENET_RX_ER
+  imxrt_config_gpio(GPIO_ENET_RX_ER);
+#endif

  /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */

@@ -2533,7 +2543,7 @@ int imxrt_netinitialize(int intf)
  mac    = priv->dev.d_mac.ether.ether_addr_octet;

  uidml |= 0x00000200;
-  uidml &= 0x0000FEFF;
+  uidml &= 0x0000feff;

  mac[0] = (uidml & 0x0000ff00) >> 8;
  mac[1] = (uidml & 0x000000ff);
@@ -1,8 +1,9 @@
 /****************************************************************************
 * arch/arm/src/imxrt/imxrt_gpio.c
 *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Dave Marples <dave@marples.net>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -101,6 +102,7 @@ static const uint8_t g_gpio1_padmux[IMXRT_GPIO_NPINS] =
  IMXRT_PADMUX_GPIO_AD_B1_15_INDEX            /* GPIO1 Pin 31 */
 };

+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
 static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] =
 {
  IMXRT_PADMUX_GPIO_B0_00_INDEX,              /* GPIO2 Pin 0 */
@@ -140,6 +142,50 @@ static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] =
  IMXRT_PADMUX_GPIO_B1_15_INDEX               /* GPIO2 Pin 31 */
 };

+#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] =
+{
+  IMXRT_PADMUX_GPIO_EMC_00_INDEX,              /* GPIO2 Pin 0 */
+  IMXRT_PADMUX_GPIO_EMC_01_INDEX,              /* GPIO2 Pin 1 */
+  IMXRT_PADMUX_GPIO_EMC_02_INDEX,              /* GPIO2 Pin 2 */
+  IMXRT_PADMUX_GPIO_EMC_03_INDEX,              /* GPIO2 Pin 3 */
+  IMXRT_PADMUX_GPIO_EMC_04_INDEX,              /* GPIO2 Pin 4 */
+  IMXRT_PADMUX_GPIO_EMC_05_INDEX,              /* GPIO2 Pin 5 */
+  IMXRT_PADMUX_GPIO_EMC_06_INDEX,              /* GPIO2 Pin 6 */
+  IMXRT_PADMUX_GPIO_EMC_07_INDEX,              /* GPIO2 Pin 7 */
+
+  IMXRT_PADMUX_GPIO_EMC_08_INDEX,              /* GPIO2 Pin 8 */
+  IMXRT_PADMUX_GPIO_EMC_09_INDEX,              /* GPIO2 Pin 9 */
+  IMXRT_PADMUX_GPIO_EMC_10_INDEX,              /* GPIO2 Pin 10 */
+  IMXRT_PADMUX_GPIO_EMC_11_INDEX,              /* GPIO2 Pin 11 */
+  IMXRT_PADMUX_GPIO_EMC_12_INDEX,              /* GPIO2 Pin 12 */
+  IMXRT_PADMUX_GPIO_EMC_13_INDEX,              /* GPIO2 Pin 13 */
+  IMXRT_PADMUX_GPIO_EMC_14_INDEX,              /* GPIO2 Pin 14 */
+  IMXRT_PADMUX_GPIO_EMC_15_INDEX,              /* GPIO2 Pin 15 */
+
+  IMXRT_PADMUX_GPIO_EMC_16_INDEX,              /* GPIO2 Pin 16 */
+  IMXRT_PADMUX_GPIO_EMC_17_INDEX,              /* GPIO2 Pin 17 */
+  IMXRT_PADMUX_GPIO_EMC_18_INDEX,              /* GPIO2 Pin 18 */
+  IMXRT_PADMUX_GPIO_EMC_19_INDEX,              /* GPIO2 Pin 19 */
+  IMXRT_PADMUX_GPIO_EMC_20_INDEX,              /* GPIO2 Pin 20 */
+  IMXRT_PADMUX_GPIO_EMC_21_INDEX,              /* GPIO2 Pin 21 */
+  IMXRT_PADMUX_GPIO_EMC_22_INDEX,              /* GPIO2 Pin 22 */
+  IMXRT_PADMUX_GPIO_EMC_23_INDEX,              /* GPIO2 Pin 23 */
+
+  IMXRT_PADMUX_GPIO_EMC_24_INDEX,              /* GPIO2 Pin 24 */
+  IMXRT_PADMUX_GPIO_EMC_25_INDEX,              /* GPIO2 Pin 25 */
+  IMXRT_PADMUX_GPIO_EMC_26_INDEX,              /* GPIO2 Pin 26 */
+  IMXRT_PADMUX_GPIO_EMC_27_INDEX,              /* GPIO2 Pin 27 */
+  IMXRT_PADMUX_GPIO_EMC_28_INDEX,              /* GPIO2 Pin 28 */
+  IMXRT_PADMUX_GPIO_EMC_29_INDEX,              /* GPIO2 Pin 29 */
+  IMXRT_PADMUX_GPIO_EMC_30_INDEX,              /* GPIO2 Pin 30 */
+  IMXRT_PADMUX_GPIO_EMC_31_INDEX               /* GPIO2 Pin 31 */
+};
+#else
+#  error "Unrecognised IMXRT family member"
+#endif
+
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
 static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] =
 {
  IMXRT_PADMUX_GPIO_SD_B1_00_INDEX,           /* GPIO3 Pin 0 */
@@ -178,7 +224,48 @@ static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] =
  IMXRT_PADMUX_INVALID,                       /* GPIO3 Pin 30 */
  IMXRT_PADMUX_INVALID                        /* GPIO3 Pin 31 */
 };
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] =
+{
+  IMXRT_PADMUX_GPIO_EMC_32_INDEX,             /* GPIO3 Pin 0 */
+  IMXRT_PADMUX_GPIO_EMC_33_INDEX,             /* GPIO3 Pin 1 */
+  IMXRT_PADMUX_GPIO_EMC_34_INDEX,             /* GPIO3 Pin 2 */
+  IMXRT_PADMUX_GPIO_EMC_35_INDEX,             /* GPIO3 Pin 3 */
+  IMXRT_PADMUX_GPIO_EMC_36_INDEX,             /* GPIO3 Pin 4 */
+  IMXRT_PADMUX_GPIO_EMC_37_INDEX,             /* GPIO3 Pin 5 */
+  IMXRT_PADMUX_GPIO_EMC_38_INDEX,             /* GPIO3 Pin 6 */
+  IMXRT_PADMUX_GPIO_EMC_39_INDEX,             /* GPIO3 Pin 7 */

+  IMXRT_PADMUX_GPIO_EMC_40_INDEX,             /* GPIO3 Pin 8 */
+  IMXRT_PADMUX_GPIO_EMC_41_INDEX,             /* GPIO3 Pin 9 */
+  IMXRT_PADMUX_INVALID,                       /* GPIO3 Pin 10 */
+  IMXRT_PADMUX_INVALID,                       /* GPIO3 Pin 11 */
+  IMXRT_PADMUX_INVALID,                       /* GPIO3 Pin 12 */
+  IMXRT_PADMUX_GPIO_SD_B0_00_INDEX,           /* GPIO3 Pin 13 */
+  IMXRT_PADMUX_GPIO_SD_B0_01_INDEX,           /* GPIO3 Pin 14 */
+  IMXRT_PADMUX_GPIO_SD_B0_02_INDEX,           /* GPIO3 Pin 15 */
+
+  IMXRT_PADMUX_GPIO_SD_B0_03_INDEX,           /* GPIO3 Pin 16 */
+  IMXRT_PADMUX_GPIO_SD_B0_04_INDEX,           /* GPIO3 Pin 17 */
+  IMXRT_PADMUX_GPIO_SD_B0_05_INDEX,           /* GPIO3 Pin 18 */
+  IMXRT_PADMUX_GPIO_SD_B0_06_INDEX,           /* GPIO3 Pin 19 */
+  IMXRT_PADMUX_GPIO_SD_B1_00_INDEX,           /* GPIO3 Pin 20 */
+  IMXRT_PADMUX_GPIO_SD_B1_01_INDEX,           /* GPIO3 Pin 21 */
+  IMXRT_PADMUX_GPIO_SD_B1_02_INDEX,           /* GPIO3 Pin 22 */
+  IMXRT_PADMUX_GPIO_SD_B1_03_INDEX,           /* GPIO3 Pin 23 */
+
+  IMXRT_PADMUX_GPIO_SD_B1_04_INDEX,           /* GPIO3 Pin 24 */
+  IMXRT_PADMUX_GPIO_SD_B1_05_INDEX,           /* GPIO3 Pin 25 */
+  IMXRT_PADMUX_GPIO_SD_B1_06_INDEX,           /* GPIO3 Pin 26 */
+  IMXRT_PADMUX_GPIO_SD_B1_07_INDEX,           /* GPIO3 Pin 27 */
+  IMXRT_PADMUX_GPIO_SD_B1_08_INDEX,           /* GPIO3 Pin 28 */
+  IMXRT_PADMUX_GPIO_SD_B1_09_INDEX,           /* GPIO3 Pin 29 */
+  IMXRT_PADMUX_GPIO_SD_B1_10_INDEX,           /* GPIO3 Pin 30 */
+  IMXRT_PADMUX_GPIO_SD_B1_11_INDEX,           /* GPIO3 Pin 31 */
+};
+#endif
+
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
 static const uint8_t g_gpio4_padmux[IMXRT_GPIO_NPINS] =
 {
  IMXRT_PADMUX_GPIO_EMC_00_INDEX,             /* GPIO4 Pin 0 */
@@ -217,6 +304,7 @@ static const uint8_t g_gpio4_padmux[IMXRT_GPIO_NPINS] =
  IMXRT_PADMUX_GPIO_EMC_30_INDEX,             /* GPIO4 Pin 30 */
  IMXRT_PADMUX_GPIO_EMC_31_INDEX              /* GPIO4 Pin 31 */
 };
+#endif

 static const uint8_t g_gpio5_padmux[IMXRT_GPIO_NPINS] =
 {
@@ -262,7 +350,11 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
  g_gpio1_padmux,                             /* GPIO1 */
  g_gpio2_padmux,                             /* GPIO2 */
  g_gpio3_padmux,                             /* GPIO3 */
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
  g_gpio4_padmux,                             /* GPIO4 */
+#else
+  NULL,                                       /* GPIO4 doesn't exist on 102x */
+#endif
  g_gpio5_padmux,                             /* GPIO5 */
 #if IMXRT_GPIO_NPORTS > 5
  g_gpio1_padmux,                             /* GPIO6 */
@@ -289,7 +381,11 @@ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] =
  , IMXRT_GPIO3_BASE
 #endif
 #if IMXRT_GPIO_NPORTS > 3
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
  , IMXRT_GPIO4_BASE
+#else
+  , 0
+#endif
 #endif
 #if IMXRT_GPIO_NPORTS > 4
  , IMXRT_GPIO5_BASE
@@ -164,7 +164,7 @@
 #  define GPIO_ALT2            (2 << GPIO_ALT_SHIFT)  /* Alternate function 2 */
 #  define GPIO_ALT3            (3 << GPIO_ALT_SHIFT)  /* Alternate function 3 */
 #  define GPIO_ALT4            (4 << GPIO_ALT_SHIFT)  /* Alternate function 4 */
-                                                      /* Alternate function 5 is GPIO */
+#  define GPIO_ALT5            (5 << GPIO_ALT_SHIFT)  /* Alternate function 5 is GPIO */
 #  define GPIO_ALT6            (6 << GPIO_ALT_SHIFT)  /* Alternate function 6 */
 #  define GPIO_ALT7            (7 << GPIO_ALT_SHIFT)  /* Alternate function 7 */
 #  define GPIO_ALT8            (8 << GPIO_ALT_SHIFT)  /* Alternate function 8 */
@@ -205,6 +205,7 @@
 #define GPIO_PADMUX_SHIFT      (16)      /* Bits 16-23: Peripheral alternate function */
 #define GPIO_PADMUX_MASK       (0xff << GPIO_PADMUX_SHIFT)
 #  define GPIO_PADMUX(n)       ((uint32_t)(n) << GPIO_PADMUX_SHIFT)
+#define GPIO_PADMUX_GET(n)     ((n&GPIO_PADMUX_MASK)>>GPIO_PADMUX_SHIFT)

 /* IOMUX Pin Configuration:
 *
@@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/imxrt/imxrt_gpioirq.c
 *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
 *   Author:  Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -123,13 +123,18 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin)
  else
 #endif
 #ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ
+#ifdef IMXRT_GPIO4_IMR
  if (irq < _IMXRT_GPIO4_0_15_BASE)
+#else
+  if (irq < _IMXRT_GPIO5_0_15_BASE)
+#endif
    {
      *regaddr = IMXRT_GPIO3_IMR;
      *pin     = irq - _IMXRT_GPIO3_16_31_BASE + 16;
    }
  else
 #endif
+#ifdef IMXRT_GPIO4_IMR
 #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
  if (irq < _IMXRT_GPIO4_16_31_BASE)
    {
@@ -146,6 +151,7 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin)
    }
  else
 #endif
+#endif
 #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
  if (irq < _IMXRT_GPIO5_16_31_BASE)
    {
@@ -463,6 +469,7 @@ static int imxrt_gpio3_16_31_interrupt(int irq, FAR void *context,
 }
 #endif

+#ifdef IMXRT_GPIO4_IMR
 #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
 static int imxrt_gpio4_0_15_interrupt(int irq, FAR void *context,
                                      FAR void *arg)
@@ -536,6 +543,7 @@ static int imxrt_gpio4_16_31_interrupt(int irq, FAR void *context,
  return OK;
 }
 #endif
+#endif

 #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
 static int imxrt_gpio5_0_15_interrupt(int irq, FAR void *context,
@@ -629,7 +637,9 @@ void imxrt_gpioirq_initialize(void)
  putreg32(0, IMXRT_GPIO1_IMR);
  putreg32(0, IMXRT_GPIO2_IMR);
  putreg32(0, IMXRT_GPIO3_IMR);
+#if defined(IMXRT_GPIO4_IMR)
  putreg32(0, IMXRT_GPIO4_IMR);
+#endif
  putreg32(0, IMXRT_GPIO5_IMR);

  /* Disable all unconfigured GPIO interrupts at the NVIC */
@@ -652,12 +662,14 @@ void imxrt_gpioirq_initialize(void)
 #ifndef CONFIG_IMXRT_GPIO3_16_31_IRQ
  up_disable_irq(IMXRT_IRQ_GPIO3_16_31);
 #endif
+#ifdef IMXRT_GPIO4_IMR
 #ifndef CONFIG_IMXRT_GPIO4_0_15_IRQ
  up_disable_irq(IMXRT_IRQ_GPIO4_0_15);
 #endif
 #ifndef CONFIG_IMXRT_GPIO4_16_31_IRQ
  up_disable_irq(IMXRT_IRQ_GPIO4_16_31);
 #endif
+#endif
 #ifndef CONFIG_IMXRT_GPIO5_0_15_IRQ
  up_disable_irq(IMXRT_IRQ_GPIO5_0_15);
 #endif
@@ -705,6 +717,7 @@ void imxrt_gpioirq_initialize(void)
  up_enable_irq(IMXRT_IRQ_GPIO3_16_31);
 #endif

+#ifdef IMXRT_GPIO4_IMR
 #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
  DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO4_0_15,
                         imxrt_gpio4_0_15_interrupt, NULL));
@@ -716,6 +729,7 @@ void imxrt_gpioirq_initialize(void)
                         imxrt_gpio4_16_31_interrupt, NULL));
  up_enable_irq(IMXRT_IRQ_GPIO4_16_31);
 #endif
+#endif

 #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
  DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO5_0_15,
@@ -1,7 +1,7 @@
 /****************************************************************************
 * arch/arm/src/imxrt/imxrt_irq.c
 *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
@@ -66,6 +66,7 @@
 * Mux Register index.
 */

+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
 static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
 {
  /* The first mappings are simple 1-to-1 mappings.  This may be a little wasteful */
@@ -198,6 +199,111 @@ static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
  IMXRT_PADCTL_PMIC_ON_REQ_INDEX,
  IMXRT_PADCTL_PMIC_STBY_REQ_INDEX
 };
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
+{
+  /* The first mappings are simple 1-to-1 mappings.  This may be a little wasteful */
+
+  IMXRT_PADCTL_GPIO_EMC_00_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_01_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_02_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_03_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_04_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_05_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_06_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_07_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_08_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_09_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_10_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_11_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_12_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_13_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_14_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_15_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_16_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_17_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_18_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_19_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_20_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_21_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_22_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_23_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_24_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_25_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_26_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_27_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_28_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_29_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_30_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_31_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_32_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_33_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_34_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_35_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_36_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_37_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_38_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_39_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_40_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_41_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_00_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_01_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_02_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_03_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_04_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_05_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_06_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_07_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_08_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_09_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_10_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_11_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_12_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_13_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_14_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_15_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_00_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_01_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_02_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_03_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_04_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_05_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_06_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_07_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_08_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_09_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_10_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_11_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_12_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_13_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_14_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_15_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_00_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_01_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_02_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_03_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_04_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_05_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_06_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_00_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_01_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_02_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_03_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_04_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_05_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_06_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_07_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_08_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_09_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_10_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_11_INDEX,
+  IMXRT_PADCTL_WAKEUP_INDEX,
+  IMXRT_PADCTL_PMIC_ON_REQ_INDEX,
+  IMXRT_PADCTL_PMIC_STBY_REQ_INDEX
+};
+#else
+#error Unrecognised IMXRT family
+#endif

 /****************************************************************************
 * Public Functions
@@ -1617,7 +1617,7 @@ static int imxrt_lpi2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg
  priv->msgc  = count;
  priv->flags = msgs->flags;

-  i2cinfo("Flags %d, len %d \n", msgs->flags, msgs->length);
+  i2cinfo("Flags %x, len %d \n", msgs->flags, msgs->length);

  /* Reset I2C trace logic */

@@ -1651,23 +1651,27 @@ static int imxrt_lpi2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg
        {
          /* Bus Error */

+          i2cerr("Bus error\n");
          ret = -EIO;
        }
      else if (status & LPI2C_MSR_ALF)
        {
          /* Arbitration Lost (master mode) */

+          i2cerr("Arbitration lost\n");
          ret = -EAGAIN;
        }
      else if (status & LPI2C_MSR_NDF)
        {
          /* Acknowledge Failure */

+          i2cerr("Ack failure\n");
          ret = -ENXIO;
        }
      else
        {
-          ret = -EINTR;
+            i2cerr("Unspecified error\n");
+            ret = -EINTR;
        }
    }

@@ -1577,8 +1577,8 @@ void up_serialinit(void)

 int up_putc(int ch)
 {
-#ifdef HAVE_USART_CONSOLE
-  struct lpc54_dev_s *priv = (struct lpc54_dev_s *)CONSOLE_DEV.priv;
+#ifdef CONSOLE_DEV
+  struct imxrt_uart_s *priv = (struct imxrt_uart_s *)CONSOLE_DEV.priv;
  uint32_t ie;

  imxrt_disableuartint(priv, &ie);
@@ -1589,11 +1589,11 @@ int up_putc(int ch)
    {
      /* Add CR */

-      up_lowputc('\r');
+      imxrt_lowputc('\r');
    }

-  up_lowputc(ch);
-  imxrt_restoreuartint(priv, intset);
+  imxrt_lowputc(ch);
+  imxrt_restoreuartint(priv, ie);
 #endif

  return ch;
@@ -54,6 +54,7 @@
 #include "up_arch.h"

 #include "chip.h"
+#include "chip/imxrt_ccm.h"

 /****************************************************************************
 * Pre-processor Definitions
@@ -1294,11 +1294,11 @@ static sdio_statset_t imxrt_status(FAR struct sdio_dev_s *dev)
 {
  struct imxrt_dev_s *priv = (struct imxrt_dev_s *)dev;

-  /* This register reflects the state of CD no matter if it's a separate pin
-   * or DAT3
-   */
-
+#if defined(CONFIG_MMCSD_HAVE_CARDDETECT) && defined(PIN_USDHC1_CD)
+  if (!imxrt_gpio_read(PIN_USDHC1_CD))
+#else
  if ((getreg32(IMXRT_USDHC1_PRSSTAT) & USDHC_PRSSTAT_CINS) != 0)
+#endif
    {
      priv->cdstatus |= SDIO_STATUS_PRESENT;
    }
@@ -58,7 +58,9 @@ static const uintptr_t g_xbars_addresses[] =
 {
  IMXRT_XBAR1_BASE,
  IMXRT_XBAR2_BASE,
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x))
  IMXRT_XBAR3_BASE
+#endif
 };

 /****************************************************************************
@@ -113,390 +113,8 @@
 #define IMXRT_XBAR(six)                                  ((six) & IMXRT_XBARA_INDEX_MASK) >> IMXRT_XBARA_INDEX_SHIFTS
 #define IMXRT_SIDE(six)                                  ((six) & IMXRT_XBARA_SIDE_MASK)  >> IMXRT_XBARA_SIDE_SHIFTS

-/* XBARA1 Mux inputs (I values) *********************************************************************************************************************************************************************************/
-
-#define IMXRT_XBARA1_IN_LOGIC_LOW                        IMXRT_XBARA1(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
-#define IMXRT_XBARA1_IN_LOGIC_HIGH                       IMXRT_XBARA1(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02                  IMXRT_XBARA1(XBAR_INPUT, 2)    /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03                  IMXRT_XBARA1(XBAR_INPUT, 3)    /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04                  IMXRT_XBARA1(XBAR_INPUT, 4)    /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05                  IMXRT_XBARA1(XBAR_INPUT, 5)    /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06                  IMXRT_XBARA1(XBAR_INPUT, 6)    /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07                  IMXRT_XBARA1(XBAR_INPUT, 7)    /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08                  IMXRT_XBARA1(XBAR_INPUT, 8)    /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09                  IMXRT_XBARA1(XBAR_INPUT, 9)    /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10                  IMXRT_XBARA1(XBAR_INPUT, 10)   /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11                  IMXRT_XBARA1(XBAR_INPUT, 11)   /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12                  IMXRT_XBARA1(XBAR_INPUT, 12)   /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13                  IMXRT_XBARA1(XBAR_INPUT, 13)   /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14                  IMXRT_XBARA1(XBAR_INPUT, 14)   /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15                  IMXRT_XBARA1(XBAR_INPUT, 15)   /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16                  IMXRT_XBARA1(XBAR_INPUT, 16)   /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17                  IMXRT_XBARA1(XBAR_INPUT, 17)   /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18                  IMXRT_XBARA1(XBAR_INPUT, 18)   /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19                  IMXRT_XBARA1(XBAR_INPUT, 19)   /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20                  IMXRT_XBARA1(XBAR_INPUT, 20)   /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21                  IMXRT_XBARA1(XBAR_INPUT, 21)   /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22                  IMXRT_XBARA1(XBAR_INPUT, 22)   /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23                  IMXRT_XBARA1(XBAR_INPUT, 23)   /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24                  IMXRT_XBARA1(XBAR_INPUT, 24)   /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25                  IMXRT_XBARA1(XBAR_INPUT, 25)   /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
-#define IMXRT_XBARA1_IN_ACMP1_OUT                        IMXRT_XBARA1(XBAR_INPUT, 26)   /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
-#define IMXRT_XBARA1_IN_ACMP2_OUT                        IMXRT_XBARA1(XBAR_INPUT, 27)   /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
-#define IMXRT_XBARA1_IN_ACMP3_OUT                        IMXRT_XBARA1(XBAR_INPUT, 28)   /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
-#define IMXRT_XBARA1_IN_ACMP4_OUT                        IMXRT_XBARA1(XBAR_INPUT, 29)   /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
-#define IMXRT_XBARA1_IN_RESERVED30                       IMXRT_XBARA1(XBAR_INPUT, 30)   /* XBARA1_IN30 input is reserved. */
-#define IMXRT_XBARA1_IN_RESERVED31                       IMXRT_XBARA1(XBAR_INPUT, 31)   /* XBARA1_IN31 input is reserved. */
-#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 32)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
-#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 33)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
-#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 34)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
-#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 35)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
-#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 36)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
-#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 37)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
-#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 38)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
-#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 39)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 48)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 49)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 50)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 51)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 52)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 53)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 54)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 55)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
-#define IMXRT_XBARA1_IN_PIT_TRIGGER0                     IMXRT_XBARA1(XBAR_INPUT, 56)   /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
-#define IMXRT_XBARA1_IN_PIT_TRIGGER1                     IMXRT_XBARA1(XBAR_INPUT, 57)   /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
-#define IMXRT_XBARA1_IN_PIT_TRIGGER2                     IMXRT_XBARA1(XBAR_INPUT, 58)   /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
-#define IMXRT_XBARA1_IN_PIT_TRIGGER3                     IMXRT_XBARA1(XBAR_INPUT, 59)   /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
-#define IMXRT_XBARA1_IN_ENC1_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 60)   /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
-#define IMXRT_XBARA1_IN_ENC2_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 61)   /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
-#define IMXRT_XBARA1_IN_ENC3_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 62)   /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
-#define IMXRT_XBARA1_IN_ENC4_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 63)   /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE0                        IMXRT_XBARA1(XBAR_INPUT, 64)   /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE1                        IMXRT_XBARA1(XBAR_INPUT, 65)   /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE2                        IMXRT_XBARA1(XBAR_INPUT, 66)   /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE3                        IMXRT_XBARA1(XBAR_INPUT, 67)   /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE4                        IMXRT_XBARA1(XBAR_INPUT, 68)   /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE5                        IMXRT_XBARA1(XBAR_INPUT, 69)   /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE6                        IMXRT_XBARA1(XBAR_INPUT, 70)   /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE7                        IMXRT_XBARA1(XBAR_INPUT, 71)   /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
-#define IMXRT_XBARA1_IN_AOI1_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 72)   /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
-#define IMXRT_XBARA1_IN_AOI1_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 73)   /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
-#define IMXRT_XBARA1_IN_AOI1_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 74)   /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
-#define IMXRT_XBARA1_IN_AOI1_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 75)   /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
-#define IMXRT_XBARA1_IN_AOI2_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 76)   /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */
-#define IMXRT_XBARA1_IN_AOI2_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 77)   /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */
-#define IMXRT_XBARA1_IN_AOI2_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 78)   /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */
-#define IMXRT_XBARA1_IN_AOI2_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 79)   /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARA1(XBAR_INPUT, 80)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARA1(XBAR_INPUT, 81)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARA1(XBAR_INPUT, 82)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARA1(XBAR_INPUT, 83)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARA1(XBAR_INPUT, 84)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARA1(XBAR_INPUT, 85)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARA1(XBAR_INPUT, 86)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARA1(XBAR_INPUT, 87)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
-
-/* XBARA1 Mux Output  (M Muxes) ***************************************************************************************************************/
-
-#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 0)    /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
-#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 1)    /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
-#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 2)    /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
-#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 3)    /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 4)    /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 5)    /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 6)    /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 7)    /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 8)    /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 9)    /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 10)   /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 11)   /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 12)   /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 13)   /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 14)   /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 15)   /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 16)   /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 17)   /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 18)   /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 19)   /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
-#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 20)   /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
-#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 21)   /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
-#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 22)   /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
-#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 23)   /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
-#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 24)   /* XBARA1_OUT24 output is reserved. */
-#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 25)   /* XBARA1_OUT25 output is reserved. */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 26)   /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 27)   /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 28)   /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 29)   /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 30)   /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 31)   /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 32)   /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 33)   /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 34)   /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 35)   /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 36)   /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 37)   /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 38)   /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 39)   /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 40)   /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 41)   /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 42)   /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 43)   /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 44)   /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 45)   /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 46)   /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 47)   /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 48)   /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 49)   /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 50)   /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 51)   /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 52)   /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 53)   /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 54)   /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 55)   /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 56)   /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 57)   /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 58)   /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 59)   /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 60)   /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 61)   /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 62)   /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 63)   /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 64)   /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 65)   /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
-#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 66)   /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */
-#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 67)   /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */
-#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 68)   /* XBARA1_OUT68 output assigned to ENC1_INDEX */
-#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 69)   /* XBARA1_OUT69 output assigned to ENC1_HOME */
-#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 70)   /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
-#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 71)   /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */
-#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 72)   /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */
-#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 73)   /* XBARA1_OUT73 output assigned to ENC2_INDEX */
-#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 74)   /* XBARA1_OUT74 output assigned to ENC2_HOME */
-#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 75)   /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
-#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 76)   /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */
-#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 77)   /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */
-#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 78)   /* XBARA1_OUT78 output assigned to ENC3_INDEX */
-#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 79)   /* XBARA1_OUT79 output assigned to ENC3_HOME */
-#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 80)   /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */
-#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 81)   /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */
-#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 82)   /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */
-#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 83)   /* XBARA1_OUT83 output assigned to ENC4_INDEX */
-#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 84)   /* XBARA1_OUT84 output assigned to ENC4_HOME */
-#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 85)   /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */
-#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 86)   /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 87)   /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 88)   /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 89)   /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 90)   /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 91)   /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 92)   /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 93)   /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 94)   /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 95)   /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 96)   /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 97)   /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 98)   /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 99)   /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 100)  /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 101)  /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */
-#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 102)  /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 103)  /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 104)  /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 105)  /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 106)  /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 107)  /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 108)  /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 109)  /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 110)  /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
-#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 111)  /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 112)  /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 113)  /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 114)  /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 115)  /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 116)  /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 117)  /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 118)  /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 119)  /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 120)  /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 121)  /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 122)  /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 123)  /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 124)  /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 125)  /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 126)  /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 127)  /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
-#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 128)  /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
-#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 129)  /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
-#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 130)  /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
-
-/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
-
-#define IMXRT_XBARB2_IN_LOGIC_LOW                        IMXRT_XBARB2(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
-#define IMXRT_XBARB2_IN_LOGIC_HIGH                       IMXRT_XBARB2(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
-#define IMXRT_XBARB2_IN_RESERVED2                        IMXRT_XBARB2(XBAR_INPUT, 2)    /* XBARB2_IN2 input is reserved. */
-#define IMXRT_XBARB2_IN_RESERVED3                        IMXRT_XBARB2(XBAR_INPUT, 3)    /* XBARB2_IN3 input is reserved. */
-#define IMXRT_XBARB2_IN_RESERVED4                        IMXRT_XBARB2(XBAR_INPUT, 4)    /* XBARB2_IN4 input is reserved. */
-#define IMXRT_XBARB2_IN_RESERVED5                        IMXRT_XBARB2(XBAR_INPUT, 5)    /* XBARB2_IN5 input is reserved. */
-#define IMXRT_XBARB2_IN_ACMP1_OUT                        IMXRT_XBARB2(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
-#define IMXRT_XBARB2_IN_ACMP2_OUT                        IMXRT_XBARB2(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
-#define IMXRT_XBARB2_IN_ACMP3_OUT                        IMXRT_XBARB2(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
-#define IMXRT_XBARB2_IN_ACMP4_OUT                        IMXRT_XBARB2(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
-#define IMXRT_XBARB2_IN_RESERVED10                       IMXRT_XBARB2(XBAR_INPUT, 10)   /* XBARB2_IN10 input is reserved. */
-#define IMXRT_XBARB2_IN_RESERVED11                       IMXRT_XBARB2(XBAR_INPUT, 11)   /* XBARB2_IN11 input is reserved. */
-#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
-#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
-#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
-#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
-#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
-#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
-#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
-#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
-#define IMXRT_XBARB2_IN_PIT_TRIGGER0                     IMXRT_XBARB2(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
-#define IMXRT_XBARB2_IN_PIT_TRIGGER1                     IMXRT_XBARB2(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB2(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB2(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB2(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB2(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB2(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB2(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB2(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB2(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
-#define IMXRT_XBARB2_IN_ENC1_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
-#define IMXRT_XBARB2_IN_ENC2_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
-#define IMXRT_XBARB2_IN_ENC3_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
-#define IMXRT_XBARB2_IN_ENC4_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE0                        IMXRT_XBARB2(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE1                        IMXRT_XBARB2(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE2                        IMXRT_XBARB2(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE3                        IMXRT_XBARB2(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE4                        IMXRT_XBARB2(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE5                        IMXRT_XBARB2(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE6                        IMXRT_XBARB2(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE7                        IMXRT_XBARB2(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
-
-/* XBARB2 Mux Output  (M Muxes) ********************************************************************************************************************/
-
-#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 0)    /* XBARB2_OUT0 output assigned to AOI1_IN00 */
-#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 1)    /* XBARB2_OUT1 output assigned to AOI1_IN01 */
-#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 2)    /* XBARB2_OUT2 output assigned to AOI1_IN02 */
-#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 3)    /* XBARB2_OUT3 output assigned to AOI1_IN03 */
-#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 4)    /* XBARB2_OUT4 output assigned to AOI1_IN04 */
-#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 5)    /* XBARB2_OUT5 output assigned to AOI1_IN05 */
-#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 6)    /* XBARB2_OUT6 output assigned to AOI1_IN06 */
-#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 7)    /* XBARB2_OUT7 output assigned to AOI1_IN07 */
-#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 8)    /* XBARB2_OUT8 output assigned to AOI1_IN08 */
-#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 9)    /* XBARB2_OUT9 output assigned to AOI1_IN09 */
-#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 10)   /* XBARB2_OUT10 output assigned to AOI1_IN10 */
-#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 11)   /* XBARB2_OUT11 output assigned to AOI1_IN11 */
-#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 12)   /* XBARB2_OUT12 output assigned to AOI1_IN12 */
-#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 13)   /* XBARB2_OUT13 output assigned to AOI1_IN13 */
-#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 14)   /* XBARB2_OUT14 output assigned to AOI1_IN14 */
-#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 15)   /* XBARB2_OUT15 output assigned to AOI1_IN15 */
-
-/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/
-
-#define IMXRT_XBARB3_IN_LOGIC_LOW                        IMXRT_XBARB3(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB3_IN0 input. */
-#define IMXRT_XBARB3_IN_LOGIC_HIGH                       IMXRT_XBARB3(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */
-#define IMXRT_XBARB3_IN_RESERVED2                        IMXRT_XBARB3(XBAR_INPUT, 2)    /* XBARB3_IN2 input is reserved. */
-#define IMXRT_XBARB3_IN_RESERVED3                        IMXRT_XBARB3(XBAR_INPUT, 3)    /* XBARB3_IN3 input is reserved. */
-#define IMXRT_XBARB3_IN_RESERVED4                        IMXRT_XBARB3(XBAR_INPUT, 4)    /* XBARB3_IN4 input is reserved. */
-#define IMXRT_XBARB3_IN_RESERVED5                        IMXRT_XBARB3(XBAR_INPUT, 5)    /* XBARB3_IN5 input is reserved. */
-#define IMXRT_XBARB3_IN_ACMP1_OUT                        IMXRT_XBARB3(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB3_IN6 input. */
-#define IMXRT_XBARB3_IN_ACMP2_OUT                        IMXRT_XBARB3(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB3_IN7 input. */
-#define IMXRT_XBARB3_IN_ACMP3_OUT                        IMXRT_XBARB3(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB3_IN8 input. */
-#define IMXRT_XBARB3_IN_ACMP4_OUT                        IMXRT_XBARB3(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB3_IN9 input. */
-#define IMXRT_XBARB3_IN_RESERVED10                       IMXRT_XBARB3(XBAR_INPUT, 10)   /* XBARB3_IN10 input is reserved. */
-#define IMXRT_XBARB3_IN_RESERVED11                       IMXRT_XBARB3(XBAR_INPUT, 11)   /* XBARB3_IN11 input is reserved. */
-#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
-#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
-#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
-#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
-#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
-#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
-#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
-#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
-#define IMXRT_XBARB3_IN_PIT_TRIGGER0                     IMXRT_XBARB3(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
-#define IMXRT_XBARB3_IN_PIT_TRIGGER1                     IMXRT_XBARB3(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB3(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB3(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB3(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB3(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB3(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB3(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB3(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB3(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
-#define IMXRT_XBARB3_IN_ENC1_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
-#define IMXRT_XBARB3_IN_ENC2_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
-#define IMXRT_XBARB3_IN_ENC3_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
-#define IMXRT_XBARB3_IN_ENC4_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE0                        IMXRT_XBARB3(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB3_IN50 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE1                        IMXRT_XBARB3(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB3_IN51 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE2                        IMXRT_XBARB3(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB3_IN52 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE3                        IMXRT_XBARB3(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB3_IN53 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE4                        IMXRT_XBARB3(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB3_IN54 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE5                        IMXRT_XBARB3(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB3_IN55 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE6                        IMXRT_XBARB3(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB3_IN56 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE7                        IMXRT_XBARB3(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB3_IN57 input. */
-
-/* XBARB3 Mux Output  (M Muxes) ********************************************************************************************************************/
-
-#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 0)    /* XBARB3_OUT0 output assigned to AOI2_IN00 */
-#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 1)    /* XBARB3_OUT1 output assigned to AOI2_IN01 */
-#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 2)    /* XBARB3_OUT2 output assigned to AOI2_IN02 */
-#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 3)    /* XBARB3_OUT3 output assigned to AOI2_IN03 */
-#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 4)    /* XBARB3_OUT4 output assigned to AOI2_IN04 */
-#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 5)    /* XBARB3_OUT5 output assigned to AOI2_IN05 */
-#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 6)    /* XBARB3_OUT6 output assigned to AOI2_IN06 */
-#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 7)    /* XBARB3_OUT7 output assigned to AOI2_IN07 */
-#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 8)    /* XBARB3_OUT8 output assigned to AOI2_IN08 */
-#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 9)    /* XBARB3_OUT9 output assigned to AOI2_IN09 */
-#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 10)   /* XBARB3_OUT10 output assigned to AOI2_IN10 */
-#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 11)   /* XBARB3_OUT11 output assigned to AOI2_IN11 */
-#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 12)   /* XBARB3_OUT12 output assigned to AOI2_IN12 */
-#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 13)   /* XBARB3_OUT13 output assigned to AOI2_IN13 */
-#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 14)   /* XBARB3_OUT14 output assigned to AOI2_IN14 */
-#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 15)   /* XBARB3_OUT15 output assigned to AOI2_IN15 */
+/* Collect correct XBAR definitions from chip file */
+#include "chip/imxrt_xbar.h"

 /**************************************************************************************************************************************************
 * Public Functions
@@ -2504,7 +2504,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
      /* Enable link up/down interrupts */

      ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT,
-                        (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                        (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
    }

  /* Disable management port (probably) */
@@ -2539,7 +2539,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
      /* Enable link up/down interrupts */

      ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT,
-                        (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                        (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
    }

  /* Disable management port (probably) */
@@ -2982,7 +2982,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
  uint16_t phyval;
  int ret;

-  /* Does this MAC support a KSZ80x1 PHY? */
+  /* Does this MAC support a KSZ80X1 PHY? */

  if (priv->phytype == SAMA5_PHY_KSZ8051 || priv->phytype == SAMA5_PHY_KSZ8081)
    {
@@ -3001,7 +3001,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
          /* Enable link up/down interrupts */

          ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT,
-                            (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                            (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
        }

      /* Disable management port (probably) */
--- a/Show More
+++ b/Show More