diff --git a/arch/arm/include/imxrt/chip.h b/arch/arm/include/imxrt/chip.h index b2942107806..34faf216dc4 100644 --- a/arch/arm/include/imxrt/chip.h +++ b/arch/arm/include/imxrt/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/***************************************************************************** * arch/arm/include/imxrt/chip.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,27 +32,42 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + *****************************************************************************/ #ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H #define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H -/************************************************************************************ +/***************************************************************************** * Included Files - ************************************************************************************/ + *****************************************************************************/ #include -/************************************************************************************ +/***************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + *****************************************************************************/ /* Get customizations for each supported chip */ -#if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \ - defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \ - defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \ - defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A) +#if defined(CONFIG_ARCH_CHIP_MIMXRT1021CAG4A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1021CAF4A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1021DAF5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1021DAG5A) + +/* MIMXRT1021CAG4A - 144 pin, 400MHz Industrial + * MIMXRT1021CAF4A - 100 pin, 400MHz Industrial + * MIMXRT1021DAF5A - 100 pin, 500MHz Consumer + * MIMXRT1021DAG5A - 144 pin, 500MHz Consumer + */ + +# define IMXRT_OCRAM_SIZE (256 * 1024) /* 256Kb OCRAM */ +# define IMXRT_GPIO_NPORTS 5 /* Five total ports */ + /* but 4 doesn't exist */ + +#elif defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A) /* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz * MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz * MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz @@ -63,9 +78,9 @@ # define IMXRT_GPIO_NPORTS 5 /* Five total ports */ #elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \ - defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \ - defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \ - defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A) + defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A) /* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz * MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz * MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz @@ -78,27 +93,28 @@ # error "Unknown i.MX RT chip type" #endif -/* NVIC priority levels *************************************************************/ -/* Each priority field holds an 8-bit priority value, 0-15. The lower the value, the - * greater the priority of the corresponding interrupt. The i.MX RT processor - * implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes. +/* NVIC priority levels ****************************************************** +/* Each priority field holds an 8-bit priority value, 0-15. The lower the + * value, the greater the priority of the corresponding interrupt. The i.MX + * RT processor implements only bits[7:4] of each field, bits[3:0] read as + * zero and ignore writes. */ -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */ #define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */ -/************************************************************************************ +/***************************************************************************** * Public Types - ************************************************************************************/ + *****************************************************************************/ -/************************************************************************************ +/***************************************************************************** * Public Data - ************************************************************************************/ + *****************************************************************************/ -/************************************************************************************ +/***************************************************************************** * Public Functions - ************************************************************************************/ + *****************************************************************************/ #endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */ diff --git a/arch/arm/include/imxrt/imxrt102x_irq.h b/arch/arm/include/imxrt/imxrt102x_irq.h new file mode 100644 index 00000000000..98cf25460b6 --- /dev/null +++ b/arch/arm/include/imxrt/imxrt102x_irq.h @@ -0,0 +1,469 @@ +/**************************************************************************************** + * arch/arm/include/imxrt/imxrt105x_irq.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H +#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* External interrupts (priority levels >= 256) *****************************************/ + +#define IMXRT_IRQ_EDMA0_16 (IMXRT_IRQ_EXTINT + 0) /* eDMA Channel 0/16 Transfer Complete */ +#define IMXRT_IRQ_EDMA1_17 (IMXRT_IRQ_EXTINT + 1) /* eDMA Channel 1/17 Transfer Complete */ +#define IMXRT_IRQ_EDMA2_18 (IMXRT_IRQ_EXTINT + 2) /* eDMA Channel 2/18 Transfer Complete */ +#define IMXRT_IRQ_EDMA3_19 (IMXRT_IRQ_EXTINT + 3) /* eDMA Channel 3/19 Transfer Complete */ +#define IMXRT_IRQ_EDMA4_20 (IMXRT_IRQ_EXTINT + 4) /* eDMA Channel 4/20 Transfer Complete */ +#define IMXRT_IRQ_EDMA5_21 (IMXRT_IRQ_EXTINT + 5) /* eDMA Channel 5/21 Transfer Complete */ +#define IMXRT_IRQ_EDMA6_22 (IMXRT_IRQ_EXTINT + 6) /* eDMA Channel 6/22 Transfer Complete */ +#define IMXRT_IRQ_EDMA7_23 (IMXRT_IRQ_EXTINT + 7) /* eDMA Channel 7/23 Transfer Complete */ +#define IMXRT_IRQ_EDMA8_24 (IMXRT_IRQ_EXTINT + 8) /* eDMA Channel 8/24 Transfer Complete */ +#define IMXRT_IRQ_EDMA9_25 (IMXRT_IRQ_EXTINT + 9) /* eDMA Channel 9/25 Transfer Complete */ +#define IMXRT_IRQ_EDMA10_26 (IMXRT_IRQ_EXTINT + 10) /* eDMA Channel 10/26 Transfer Complete */ +#define IMXRT_IRQ_EDMA11_27 (IMXRT_IRQ_EXTINT + 11) /* eDMA Channel 11/27 Transfer Complete */ +#define IMXRT_IRQ_EDMA12_28 (IMXRT_IRQ_EXTINT + 12) /* eDMA Channel 12/28 Transfer Complete */ +#define IMXRT_IRQ_EDMA13_29 (IMXRT_IRQ_EXTINT + 13) /* eDMA Channel 13/29 Transfer Complete */ +#define IMXRT_IRQ_EDMA14_30 (IMXRT_IRQ_EXTINT + 14) /* eDMA Channel 14/30 Transfer Complete */ +#define IMXRT_IRQ_EDMA15_31 (IMXRT_IRQ_EXTINT + 15) /* eDMA Channel 15/31 Transfer Complete */ +#define IMXRT_IRQ_EDMA_ERROR (IMXRT_IRQ_EXTINT + 16) /* Error Interrupt, Channels 0-15 / 16-31 */ +#define IMXRT_IRQ_CM70 (IMXRT_IRQ_EXTINT + 17) /* CTI trigger outputs (internal: CTIIRQ[0]) */ +#define IMXRT_IRQ_CM71 (IMXRT_IRQ_EXTINT + 18) /* CTI trigger outputs (internal: CTIIRQ[1]) */ +#define IMXRT_IRQ_CM7CP (IMXRT_IRQ_EXTINT + 19) /* CorePlatform exception IRQ */ +#define IMXRT_IRQ_LPUART1 (IMXRT_IRQ_EXTINT + 20) /* UART1 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART2 (IMXRT_IRQ_EXTINT + 21) /* UART2 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART3 (IMXRT_IRQ_EXTINT + 22) /* UART3 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART4 (IMXRT_IRQ_EXTINT + 23) /* UART4 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART5 (IMXRT_IRQ_EXTINT + 24) /* UART5 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART6 (IMXRT_IRQ_EXTINT + 25) /* UART6 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART7 (IMXRT_IRQ_EXTINT + 26) /* UART7 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART8 (IMXRT_IRQ_EXTINT + 27) /* UART8 TX/RX interrupt */ +#define IMXRT_IRQ_LPI2C1 (IMXRT_IRQ_EXTINT + 28) /* I2C1 Interrupt */ +#define IMXRT_IRQ_LPI2C2 (IMXRT_IRQ_EXTINT + 29) /* I2C2 Interrupt */ +#define IMXRT_IRQ_LPI2C3 (IMXRT_IRQ_EXTINT + 30) /* I2C3 Interrupt */ +#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C4 Interrupt */ +#define IMXRT_IRQ_LPSPI1 (IMXRT_IRQ_EXTINT + 32) /* LPSPI1 interrupt */ +#define IMXRT_IRQ_LPSPI2 (IMXRT_IRQ_EXTINT + 33) /* LPSPI2 interrupt */ +#define IMXRT_IRQ_LPSPI3 (IMXRT_IRQ_EXTINT + 34) /* LPSPI3 interrupt */ +#define IMXRT_IRQ_LPSPI4 (IMXRT_IRQ_EXTINT + 35) /* LPSPI4 interrupt */ +#define IMXRT_IRQ_CAN1 (IMXRT_IRQ_EXTINT + 36) /* CAN1 interrupt */ +#define IMXRT_IRQ_CAN2 (IMXRT_IRQ_EXTINT + 37) /* CAN2 interrupt */ +#define IMXRT_IRQ_CM7FR (IMXRT_IRQ_EXTINT + 38) /* FlexRAM address fault */ +#define IMXRT_IRQ_KPP (IMXRT_IRQ_EXTINT + 39) /* Keypad Interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 40) RESERVED */ +#define IMXRT_IRQ_GPRIRQ (IMXRT_IRQ_EXTINT + 41) /* Notify cores on exception while boot */ +/* RESERVED (IMXRT_IRQ_EXTINT + 42) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 43) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 44) RESERVED */ +#define IMXRT_IRQ_WDOG2 (IMXRT_IRQ_EXTINT + 45) /* Watchdog Timer reset */ +#define IMXRT_IRQ_SNVS (IMXRT_IRQ_EXTINT + 46) /* SNVS Functional Interrupt */ +#define IMXRT_IRQ_SNVSSEC (IMXRT_IRQ_EXTINT + 47) /* SNVS Security Interrupt */ +#define IMXRT_IRQ_SNVSSB (IMXRT_IRQ_EXTINT + 48) /* ON-OFF short button press */ +#define IMXRT_IRQ_CSU (IMXRT_IRQ_EXTINT + 49) /* CSU Interrupt Request 1 */ +#define IMXRT_IRQ_DCP (IMXRT_IRQ_EXTINT + 50) /* DCP channel/CRC interrupts (channel != 0) */ +#define IMXRT_IRQ_DCP0 (IMXRT_IRQ_EXTINT + 51) /* DCP channel 0 interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 52) RESERVED */ +#define IMXRT_IRQ_TRNG (IMXRT_IRQ_EXTINT + 53) /* TRNG Interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 54) RESERVED */ +#define IMXRT_IRQ_BEE (IMXRT_IRQ_EXTINT + 55) /* BEE IRQ */ +#define IMXRT_IRQ_SAI1 (IMXRT_IRQ_EXTINT + 56) /* SAI1 interrupt (RX/TX) */ +#define IMXRT_IRQ_SAI2 (IMXRT_IRQ_EXTINT + 57) /* SAI2 interrupt (RX/TX) */ +#define IMXRT_IRQ_SAI3RX (IMXRT_IRQ_EXTINT + 58) /* SAI3 RX interrupt (RX/TX) */ +#define IMXRT_IRQ_SAI3TX (IMXRT_IRQ_EXTINT + 59) /* SAI3 TX interrupt (RX/TX) */ +#define IMXRT_IRQ_SPDIF (IMXRT_IRQ_EXTINT + 60) /* SPDIF interrupt */ +#define IMXRT_IRQ_PMU (IMXRT_IRQ_EXTINT + 61) /* Brown-out event 1.1, 2.5 or 3.0 regulators */ +/* RESERVED (IMXRT_IRQ_EXTINT + 62) RESERVED */ +#define IMXRT_IRQ_TEMP (IMXRT_IRQ_EXTINT + 63) /* Temperature Monitor */ +#define IMXRT_IRQ_TEMPPANIC (IMXRT_IRQ_EXTINT + 64) /* TempSensor panic */ +#define IMXRT_IRQ_USBPHY0 (IMXRT_IRQ_EXTINT + 65) /* USBPHY (UTMI0) interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 66) RESERVED */ +#define IMXRT_IRQ_ADC1 (IMXRT_IRQ_EXTINT + 67) /* ADC1 interrupt */ +#define IMXRT_IRQ_ADC2 (IMXRT_IRQ_EXTINT + 68) /* ADC2 interrupt */ +#define IMXRT_IRQ_DCDC (IMXRT_IRQ_EXTINT + 69) /* DCDC interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 70) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 71) RESERVED */ +#define IMXRT_IRQ_GPIO1_0 (IMXRT_IRQ_EXTINT + 72) /* GPIO1 INT0 interrupt */ +#define IMXRT_IRQ_GPIO1_1 (IMXRT_IRQ_EXTINT + 73) /* GPIO1 INT1 interrupt */ +#define IMXRT_IRQ_GPIO1_2 (IMXRT_IRQ_EXTINT + 74) /* GPIO1 INT2 interrupt */ +#define IMXRT_IRQ_GPIO1_3 (IMXRT_IRQ_EXTINT + 75) /* GPIO1 INT3 interrupt */ +#define IMXRT_IRQ_GPIO1_4 (IMXRT_IRQ_EXTINT + 76) /* GPIO1 INT4 interrupt */ +#define IMXRT_IRQ_GPIO1_5 (IMXRT_IRQ_EXTINT + 77) /* GPIO1 INT5 interrupt */ +#define IMXRT_IRQ_GPIO1_6 (IMXRT_IRQ_EXTINT + 78) /* GPIO1 INT6 interrupt */ +#define IMXRT_IRQ_GPIO1_7 (IMXRT_IRQ_EXTINT + 79) /* GPIO1 INT7 interrupt */ +#define IMXRT_IRQ_GPIO1_0_15 (IMXRT_IRQ_EXTINT + 80) /* GPIO1 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO1_16_31 (IMXRT_IRQ_EXTINT + 81) /* GPIO1 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO2_0_15 (IMXRT_IRQ_EXTINT + 82) /* GPIO2 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO2_16_31 (IMXRT_IRQ_EXTINT + 83) /* GPIO2 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO3_0_15 (IMXRT_IRQ_EXTINT + 84) /* GPIO3 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO3_16_31 (IMXRT_IRQ_EXTINT + 85) /* GPIO3 INT16-31 interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 86) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 87) RESERVED */ +#define IMXRT_IRQ_GPIO5_0_15 (IMXRT_IRQ_EXTINT + 88) /* GPIO5 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO5_16_31 (IMXRT_IRQ_EXTINT + 89) /* GPIO5 INT16-31 interrupt */ +#define IMXRT_IRQ_FLEXIO1 (IMXRT_IRQ_EXTINT + 90) /* FlexIO Interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 91) RESERVED */ +#define IMXRT_IRQ_WDOG1 (IMXRT_IRQ_EXTINT + 92) /* Watchdog Timer reset */ +#define IMXRT_IRQ_RTWDOG (IMXRT_IRQ_EXTINT + 93) /* Watchdog Timer reset */ +#define IMXRT_IRQ_EWM (IMXRT_IRQ_EXTINT + 94) /* EWM interrupt */ +#define IMXRT_IRQ_CCM_1 (IMXRT_IRQ_EXTINT + 95) /* CCM interrupt 1 */ +#define IMXRT_IRQ_CCM_2 (IMXRT_IRQ_EXTINT + 96) /* CCM interrupt 2 */ +#define IMXRT_IRQ_GPC (IMXRT_IRQ_EXTINT + 97) /* GPC interrupt 1 */ +#define IMXRT_IRQ_SRC (IMXRT_IRQ_EXTINT + 98) /* SRC interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 99) RESERVED */ +#define IMXRT_IRQ_GPT1 (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */ +#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_0 (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_1 (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_2 (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_3 (IMXRT_IRQ_EXTINT + 105) /* FLEXPWM1 capture/compare/reload 3 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_F (IMXRT_IRQ_EXTINT + 106) /* FLEXPWM1 fault interrupt OR reload error */ +/* RESERVED (IMXRT_IRQ_EXTINT + 107) RESERVED */ +#define IMXRT_IRQ_FLEXSPI (IMXRT_IRQ_EXTINT + 108) /* FlexSPI interrupt */ +#define IMXRT_IRQ_SEMC (IMXRT_IRQ_EXTINT + 109) /* SEMC interrupt */ +#define IMXRT_IRQ_USDHC1 (IMXRT_IRQ_EXTINT + 110) /* USDHC1 interrupt */ +#define IMXRT_IRQ_USDHC2 (IMXRT_IRQ_EXTINT + 111) /* USDHC2 interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 112) RESERVED */ +#define IMXRT_IRQ_USBOTG1 (IMXRT_IRQ_EXTINT + 113) /* USBO2 USB OTG1 interrupt */ +#define IMXRT_IRQ_ENET (IMXRT_IRQ_EXTINT + 114) /* ENET MAC 0 interrupt */ +#define IMXRT_IRQ_ENET1588 (IMXRT_IRQ_EXTINT + 115) /* ENET MAC 0 1588 Timer Interrupt */ +#define IMXRT_IRQ_XBAR1_0_1 (IMXRT_IRQ_EXTINT + 116) /* XBAR1 interrupt 0/1 */ +#define IMXRT_IRQ_XBAR1_2_3 (IMXRT_IRQ_EXTINT + 117) /* XBAR1 interrupt 2/3 */ +#define IMXRT_IRQ_ADCETC_0 (IMXRT_IRQ_EXTINT + 118) /* ADC_ETC interrupt 0 */ +#define IMXRT_IRQ_ADCETC_1 (IMXRT_IRQ_EXTINT + 119) /* ADC_ETC interrupt 1 */ +#define IMXRT_IRQ_ADCETC_2 (IMXRT_IRQ_EXTINT + 120) /* ADC_ETC interrupt 2 */ +#define IMXRT_IRQ_ADCETC_ERR (IMXRT_IRQ_EXTINT + 121) /* ADC_ETC error interrupt */ +#define IMXRT_IRQ_PIT (IMXRT_IRQ_EXTINT + 122) /* PIT interrupt */ +#define IMXRT_IRQ_ACMP1 (IMXRT_IRQ_EXTINT + 123) /* ACMP1 interrupt */ +#define IMXRT_IRQ_ACMP2 (IMXRT_IRQ_EXTINT + 124) /* ACMP2 interrupt */ +#define IMXRT_IRQ_ACMP3 (IMXRT_IRQ_EXTINT + 125) /* ACMP3 interrupt */ +#define IMXRT_IRQ_ACMP4 (IMXRT_IRQ_EXTINT + 126) /* ACMP4 interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 127) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 128) RESERVED */ +#define IMXRT_IRQ_ENC1 (IMXRT_IRQ_EXTINT + 129) /* ENC1 interrupt */ +#define IMXRT_IRQ_ENC2 (IMXRT_IRQ_EXTINT + 130) /* ENC2 interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 131) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 132) RESERVED */ +#define IMXRT_IRQ_QTIMER1 (IMXRT_IRQ_EXTINT + 133) /* QTIMER1 timer 0-3 interrupt */ +#define IMXRT_IRQ_QTIMER2 (IMXRT_IRQ_EXTINT + 134) /* QTIMER2 timer 0-3 interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 135) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 136) RESERVED */ +#define IMXRT_IRQ_FLEXPWM2_0 (IMXRT_IRQ_EXTINT + 137) /* FLEXPWM2 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_1 (IMXRT_IRQ_EXTINT + 138) /* FLEXPWM2 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_2 (IMXRT_IRQ_EXTINT + 139) /* FLEXPWM2 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_3 (IMXRT_IRQ_EXTINT + 140) /* FLEXPWM2 capture/compare/reload 3 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_F (IMXRT_IRQ_EXTINT + 141) /* FLEXPWM2 fault interrupt */ +/* RESERVED (IMXRT_IRQ_EXTINT + 142) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 143) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 144) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 146) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 147) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 148) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 149) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 150) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 151) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 152) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 153) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 154) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 155) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 156) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 157) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 158) RESERVED */ +/* RESERVED (IMXRT_IRQ_EXTINT + 159) RESERVED */ + +#define IMXRT_IRQ_NEXTINT 160 + +/* GPIO second level interrupt **********************************************************/ + +#define IMXRT_GPIO_IRQ_FIRST (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT) +#define _IMXRT_GPIO1_0_15_BASE IMXRT_GPIO_IRQ_FIRST + +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ + /* GPIO1 has dedicated interrupts for pins 0-7 + * REVISIT: I am assuming that you really cannot use the dedicated and the multiplex + * interrupts concurrently. + */ + +# define IMXRT_IRQ_GPIO1_0 (_IMXRT_GPIO1_0_15_BASE + 0) /* GPIO1 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO1_1 (_IMXRT_GPIO1_0_15_BASE + 1) /* GPIO1 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO1_2 (_IMXRT_GPIO1_0_15_BASE + 2) /* GPIO1 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO1_3 (_IMXRT_GPIO1_0_15_BASE + 3) /* GPIO1 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO1_4 (_IMXRT_GPIO1_0_15_BASE + 4) /* GPIO1 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO1_5 (_IMXRT_GPIO1_0_15_BASE + 5) /* GPIO1 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO1_6 (_IMXRT_GPIO1_0_15_BASE + 6) /* GPIO1 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO1_7 (_IMXRT_GPIO1_0_15_BASE + 7) /* GPIO1 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO1_8 (_IMXRT_GPIO1_0_15_BASE + 8) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_9 (_IMXRT_GPIO1_0_15_BASE + 9) /* GPIO1 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO1_10 (_IMXRT_GPIO1_0_15_BASE + 10) /* GPIO1 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO1_11 (_IMXRT_GPIO1_0_15_BASE + 11) /* GPIO1 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO1_12 (_IMXRT_GPIO1_0_15_BASE + 12) /* GPIO1 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO1_13 (_IMXRT_GPIO1_0_15_BASE + 13) /* GPIO1 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO1_14 (_IMXRT_GPIO1_0_15_BASE + 14) /* GPIO1 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO1_15 (_IMXRT_GPIO1_0_15_BASE + 15) /* GPIO1 pin 15 interrupt */ + +# define _IMXRT_GPIO1_8_15_NIRQS 16 +# define _IMXRT_GPIO1_16_31_BASE (_IMXRT_GPIO1_0_15_BASE + _IMXRT_GPIO1_8_15_NIRQS) +#else +# define _IMXRT_GPIO1_8_15_NIRQS 0 +# define _IMXRT_GPIO1_16_31_BASE _IMXRT_GPIO1_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ +# define IMXRT_IRQ_GPIO1_16 (_IMXRT_GPIO1_16_31_BASE + 0) /* GPIO1 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO1_17 (_IMXRT_GPIO1_16_31_BASE + 1) /* GPIO1 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO1_18 (_IMXRT_GPIO1_16_31_BASE + 2) /* GPIO1 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO1_19 (_IMXRT_GPIO1_16_31_BASE + 3) /* GPIO1 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO1_20 (_IMXRT_GPIO1_16_31_BASE + 4) /* GPIO1 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO1_21 (_IMXRT_GPIO1_16_31_BASE + 5) /* GPIO1 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO1_22 (_IMXRT_GPIO1_16_31_BASE + 6) /* GPIO1 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO1_23 (_IMXRT_GPIO1_16_31_BASE + 7) /* GPIO1 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO1_24 (_IMXRT_GPIO1_16_31_BASE + 8) /* GPIO1 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO1_25 (_IMXRT_GPIO1_16_31_BASE + 9) /* GPIO1 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO1_26 (_IMXRT_GPIO1_16_31_BASE + 10) /* GPIO1 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO1_27 (_IMXRT_GPIO1_16_31_BASE + 11) /* GPIO1 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO1_28 (_IMXRT_GPIO1_16_31_BASE + 12) /* GPIO1 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO1_29 (_IMXRT_GPIO1_16_31_BASE + 13) /* GPIO1 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO1_30 (_IMXRT_GPIO1_16_31_BASE + 14) /* GPIO1 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO1_31 (_IMXRT_GPIO1_16_31_BASE + 15) /* GPIO1 pin 31 interrupt */ + +# define _IMXRT_GPIO1_16_31_NIRQS 16 +# define _IMXRT_GPIO2_0_15_BASE (_IMXRT_GPIO1_16_31_BASE + _IMXRT_GPIO1_16_31_NIRQS) +# define IMXRT_GPIO1_NIRQS (_IMXRT_GPIO1_8_15_NIRQS + _IMXRT_GPIO1_16_31_NIRQS) +#else +# define _IMXRT_GPIO2_0_15_BASE _IMXRT_GPIO1_16_31_BASE +# define IMXRT_GPIO1_NIRQS _IMXRT_GPIO1_8_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ +# define IMXRT_IRQ_GPIO2_0 (_IMXRT_GPIO2_0_15_BASE + 0) /* GPIO2 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO2_1 (_IMXRT_GPIO2_0_15_BASE + 1) /* GPIO2 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO2_2 (_IMXRT_GPIO2_0_15_BASE + 2) /* GPIO2 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO2_3 (_IMXRT_GPIO2_0_15_BASE + 3) /* GPIO2 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO2_4 (_IMXRT_GPIO2_0_15_BASE + 4) /* GPIO2 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO2_5 (_IMXRT_GPIO2_0_15_BASE + 5) /* GPIO2 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO2_6 (_IMXRT_GPIO2_0_15_BASE + 6) /* GPIO2 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO2_7 (_IMXRT_GPIO2_0_15_BASE + 7) /* GPIO2 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO2_8 (_IMXRT_GPIO2_0_15_BASE + 8) /* GPIO2 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO2_9 (_IMXRT_GPIO2_0_15_BASE + 9) /* GPIO2 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO2_10 (_IMXRT_GPIO2_0_15_BASE + 10) /* GPIO2 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO2_11 (_IMXRT_GPIO2_0_15_BASE + 11) /* GPIO2 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO2_12 (_IMXRT_GPIO2_0_15_BASE + 12) /* GPIO2 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO2_13 (_IMXRT_GPIO2_0_15_BASE + 13) /* GPIO2 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO2_14 (_IMXRT_GPIO2_0_15_BASE + 14) /* GPIO2 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO2_15 (_IMXRT_GPIO2_0_15_BASE + 15) /* GPIO2 pin 15 interrupt */ + +# define _IMXRT_GPIO2_0_15_NIRQS 16 +# define _IMXRT_GPIO2_16_31_BASE (_IMXRT_GPIO2_0_15_BASE + _IMXRT_GPIO2_0_15_NIRQS) +#else +# define _IMXRT_GPIO2_0_15_NIRQS 0 +# define _IMXRT_GPIO2_16_31_BASE _IMXRT_GPIO2_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ +# define IMXRT_IRQ_GPIO2_16 (_IMXRT_GPIO2_16_31_BASE + 0) /* GPIO2 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO2_17 (_IMXRT_GPIO2_16_31_BASE + 1) /* GPIO2 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO2_18 (_IMXRT_GPIO2_16_31_BASE + 2) /* GPIO2 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO2_19 (_IMXRT_GPIO2_16_31_BASE + 3) /* GPIO2 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO2_20 (_IMXRT_GPIO2_16_31_BASE + 4) /* GPIO2 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO2_21 (_IMXRT_GPIO2_16_31_BASE + 5) /* GPIO2 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO2_22 (_IMXRT_GPIO2_16_31_BASE + 6) /* GPIO2 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO2_23 (_IMXRT_GPIO2_16_31_BASE + 7) /* GPIO2 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO2_24 (_IMXRT_GPIO2_16_31_BASE + 8) /* GPIO2 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO2_25 (_IMXRT_GPIO2_16_31_BASE + 9) /* GPIO2 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO2_26 (_IMXRT_GPIO2_16_31_BASE + 10) /* GPIO2 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO2_27 (_IMXRT_GPIO2_16_31_BASE + 11) /* GPIO2 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO2_28 (_IMXRT_GPIO2_16_31_BASE + 12) /* GPIO2 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO2_29 (_IMXRT_GPIO2_16_31_BASE + 13) /* GPIO2 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO2_30 (_IMXRT_GPIO2_16_31_BASE + 14) /* GPIO2 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO2_31 (_IMXRT_GPIO2_16_31_BASE + 15) /* GPIO2 pin 31 interrupt */ + +# define _IMXRT_GPIO2_16_31_NIRQS 16 +# define _IMXRT_GPIO3_0_15_BASE (_IMXRT_GPIO2_16_31_BASE + _IMXRT_GPIO2_16_31_NIRQS) +# define IMXRT_GPIO2_NIRQS (_IMXRT_GPIO2_0_15_NIRQS + _IMXRT_GPIO2_16_31_NIRQS) +#else +# define _IMXRT_GPIO3_0_15_BASE _IMXRT_GPIO2_16_31_BASE +# define IMXRT_GPIO2_NIRQS _IMXRT_GPIO2_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ +# define IMXRT_IRQ_GPIO3_0 (_IMXRT_GPIO3_0_15_BASE + 0) /* GPIO3 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO3_1 (_IMXRT_GPIO3_0_15_BASE + 1) /* GPIO3 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO3_2 (_IMXRT_GPIO3_0_15_BASE + 2) /* GPIO3 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO3_3 (_IMXRT_GPIO3_0_15_BASE + 3) /* GPIO3 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO3_4 (_IMXRT_GPIO3_0_15_BASE + 4) /* GPIO3 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO3_5 (_IMXRT_GPIO3_0_15_BASE + 5) /* GPIO3 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO3_6 (_IMXRT_GPIO3_0_15_BASE + 6) /* GPIO3 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO3_7 (_IMXRT_GPIO3_0_15_BASE + 7) /* GPIO3 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO3_8 (_IMXRT_GPIO3_0_15_BASE + 8) /* GPIO3 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO3_9 (_IMXRT_GPIO3_0_15_BASE + 9) /* GPIO3 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO3_10 (_IMXRT_GPIO3_0_15_BASE + 10) /* GPIO3 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO3_11 (_IMXRT_GPIO3_0_15_BASE + 11) /* GPIO3 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO3_12 (_IMXRT_GPIO3_0_15_BASE + 12) /* GPIO3 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO3_13 (_IMXRT_GPIO3_0_15_BASE + 13) /* GPIO3 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO3_14 (_IMXRT_GPIO3_0_15_BASE + 14) /* GPIO3 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO3_15 (_IMXRT_GPIO3_0_15_BASE + 15) /* GPIO3 pin 15 interrupt */ + +# define _IMXRT_GPIO3_0_15_NIRQS 16 +# define _IMXRT_GPIO3_16_31_BASE (_IMXRT_GPIO3_0_15_BASE + _IMXRT_GPIO3_0_15_NIRQS) +#else +# define _IMXRT_GPIO3_0_15_NIRQS 0 +# define _IMXRT_GPIO3_16_31_BASE _IMXRT_GPIO3_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ +# define IMXRT_IRQ_GPIO3_16 (_IMXRT_GPIO3_16_31_BASE + 0) /* GPIO3 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO3_17 (_IMXRT_GPIO3_16_31_BASE + 1) /* GPIO3 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO3_18 (_IMXRT_GPIO3_16_31_BASE + 2) /* GPIO3 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO3_19 (_IMXRT_GPIO3_16_31_BASE + 3) /* GPIO3 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO3_20 (_IMXRT_GPIO3_16_31_BASE + 4) /* GPIO3 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO3_21 (_IMXRT_GPIO3_16_31_BASE + 5) /* GPIO3 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO3_22 (_IMXRT_GPIO3_16_31_BASE + 6) /* GPIO3 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO3_23 (_IMXRT_GPIO3_16_31_BASE + 7) /* GPIO3 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO3_24 (_IMXRT_GPIO3_16_31_BASE + 8) /* GPIO3 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO3_25 (_IMXRT_GPIO3_16_31_BASE + 9) /* GPIO3 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO3_26 (_IMXRT_GPIO3_16_31_BASE + 10) /* GPIO3 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO3_27 (_IMXRT_GPIO3_16_31_BASE + 11) /* GPIO3 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO3_28 (_IMXRT_GPIO3_16_31_BASE + 12) /* GPIO3 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO3_29 (_IMXRT_GPIO3_16_31_BASE + 13) /* GPIO3 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO3_30 (_IMXRT_GPIO3_16_31_BASE + 14) /* GPIO3 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO3_31 (_IMXRT_GPIO3_16_31_BASE + 15) /* GPIO3 pin 31 interrupt */ + +# define _IMXRT_GPIO3_16_31_NIRQS 16 +# define _IMXRT_GPIO5_0_15_BASE (_IMXRT_GPIO3_16_31_BASE + _IMXRT_GPIO3_16_31_NIRQS) +# define IMXRT_GPIO3_NIRQS (_IMXRT_GPIO3_0_15_NIRQS + _IMXRT_GPIO3_16_31_NIRQS) +#else +# define _IMXRT_GPIO5_0_15_BASE _IMXRT_GPIO3_16_31_BASE +# define IMXRT_GPIO3_NIRQS _IMXRT_GPIO3_0_15_NIRQS +#endif + +/* There is no GPIO4 on this chip */ + +#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ +# define IMXRT_IRQ_GPIO5_0 (_IMXRT_GPIO5_0_15_BASE + 0) /* GPIO5 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO5_1 (_IMXRT_GPIO5_0_15_BASE + 1) /* GPIO5 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO5_2 (_IMXRT_GPIO5_0_15_BASE + 2) /* GPIO5 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO5_3 (_IMXRT_GPIO5_0_15_BASE + 3) /* GPIO5 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO5_4 (_IMXRT_GPIO5_0_15_BASE + 4) /* GPIO5 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO5_5 (_IMXRT_GPIO5_0_15_BASE + 5) /* GPIO5 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO5_6 (_IMXRT_GPIO5_0_15_BASE + 6) /* GPIO5 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO5_7 (_IMXRT_GPIO5_0_15_BASE + 7) /* GPIO5 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO5_8 (_IMXRT_GPIO5_0_15_BASE + 8) /* GPIO5 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO5_9 (_IMXRT_GPIO5_0_15_BASE + 9) /* GPIO5 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO5_10 (_IMXRT_GPIO5_0_15_BASE + 10) /* GPIO5 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO5_11 (_IMXRT_GPIO5_0_15_BASE + 11) /* GPIO5 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO5_12 (_IMXRT_GPIO5_0_15_BASE + 12) /* GPIO5 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO5_13 (_IMXRT_GPIO5_0_15_BASE + 13) /* GPIO5 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO5_14 (_IMXRT_GPIO5_0_15_BASE + 14) /* GPIO5 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO5_15 (_IMXRT_GPIO5_0_15_BASE + 15) /* GPIO5 pin 15 interrupt */ + +# define _IMXRT_GPIO5_0_15_NIRQS 16 +# define _IMXRT_GPIO5_16_31_BASE (_IMXRT_GPIO5_0_15_BASE + _IMXRT_GPIO5_0_15_NIRQS) +#else +# define _IMXRT_GPIO5_0_15_NIRQS 0 +# define _IMXRT_GPIO5_16_31_BASE _IMXRT_GPIO5_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ +# define IMXRT_IRQ_GPIO5_16 (_IMXRT_GPIO5_16_31_BASE + 0) /* GPIO5 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO5_17 (_IMXRT_GPIO5_16_31_BASE + 1) /* GPIO5 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO5_18 (_IMXRT_GPIO5_16_31_BASE + 2) /* GPIO5 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO5_19 (_IMXRT_GPIO5_16_31_BASE + 3) /* GPIO5 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO5_20 (_IMXRT_GPIO5_16_31_BASE + 4) /* GPIO5 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO5_21 (_IMXRT_GPIO5_16_31_BASE + 5) /* GPIO5 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO5_22 (_IMXRT_GPIO5_16_31_BASE + 6) /* GPIO5 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO5_23 (_IMXRT_GPIO5_16_31_BASE + 7) /* GPIO5 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO5_24 (_IMXRT_GPIO5_16_31_BASE + 8) /* GPIO5 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO5_25 (_IMXRT_GPIO5_16_31_BASE + 9) /* GPIO5 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO5_26 (_IMXRT_GPIO5_16_31_BASE + 10) /* GPIO5 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO5_27 (_IMXRT_GPIO5_16_31_BASE + 11) /* GPIO5 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO5_28 (_IMXRT_GPIO5_16_31_BASE + 12) /* GPIO5 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO5_29 (_IMXRT_GPIO5_16_31_BASE + 13) /* GPIO5 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO5_30 (_IMXRT_GPIO5_16_31_BASE + 14) /* GPIO5 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO5_31 (_IMXRT_GPIO5_16_31_BASE + 15) /* GPIO5 pin 31 interrupt */ + +# define _IMXRT_GPIO5_16_31_NIRQS 16 +# define IMXRT_GPIO5_NIRQS (_IMXRT_GPIO5_0_15_NIRQS + _IMXRT_GPIO5_16_31_NIRQS) +#else +# define IMXRT_GPIO5_NIRQS _IMXRT_GPIO5_0_15_NIRQS +#endif + +#define IMXRT_GPIO_NIRQS (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \ + IMXRT_GPIO3_NIRQS + IMXRT_GPIO5_NIRQS) +#define IMXRT_GPIO_IRQ_LAST (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS) + +/* Total number of IRQ numbers **********************************************************/ + +#define NR_IRQS (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H */ diff --git a/arch/arm/include/imxrt/irq.h b/arch/arm/include/imxrt/irq.h index 72bca14fabe..0773511b2f5 100644 --- a/arch/arm/include/imxrt/irq.h +++ b/arch/arm/include/imxrt/irq.h @@ -1,4 +1,4 @@ -/**************************************************************************************** +/**************************************************************************** * arch/arm/include/imxrt/irq.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,53 +32,61 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************/ + ****************************************************************************/ -/* This file should never be included directed but, rather, only indirectly through - * nuttx/irq.h +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h */ #ifndef __ARCH_ARM_INCLUDE_IMXRT_IRQ_H #define __ARCH_ARM_INCLUDE_IMXRT_IRQ_H -/**************************************************************************************** +/***************************************************************************** * Included Files - ****************************************************************************************/ + *****************************************************************************/ #include #include -/**************************************************************************************** +/***************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ + *****************************************************************************/ -/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in the IRQ - * to handle mapping tables. +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words + * of memory in the IRQ to handle mapping tables. */ /* Common Processor Exceptions (vectors 0-15) */ -#define IMXRT_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ +#define IMXRT_IRQ_RESERVED (0) /* Reserved vector .. only used with + CONFIG_DEBUG_FEATURES */ + /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define IMXRT_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ + + /* Vector 1: Reset (not handled by IRQ) */ + +#define IMXRT_IRQ_NMI (2) /* Vector 2: Non-Maskable Int (NMI) */ #define IMXRT_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ #define IMXRT_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ #define IMXRT_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ #define IMXRT_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ /* Vectors 7-10: Reserved */ + #define IMXRT_IRQ_SVCALL (11) /* Vector 11: SVC call */ #define IMXRT_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ /* Vector 13: Reserved */ -#define IMXRT_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ + +#define IMXRT_IRQ_PENDSV (14) /* Vector 14: Pendable SSR */ #define IMXRT_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* Chip-Specific External interrupts */ -#define IMXRT_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ +#define IMXRT_IRQ_EXTINT (16) /* Vector number of the first ext int */ -#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) # include #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) # include @@ -86,15 +94,15 @@ # error Unrecognized i.MX RT architecture #endif -/**************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/**************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************/ + ****************************************************************************/ #ifdef __cplusplus #define EXTERN extern "C" @@ -104,9 +112,9 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************************** +/**************************************************************************** * Public Function Prototypes - ****************************************************************************************/ + ****************************************************************************/ #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 821665dfbda..6d3157eeb6e 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -12,6 +12,22 @@ choice default ARCH_CHIP_MIMXRT1052DVL6A depends on ARCH_CHIP_IMXRT +config ARCH_CHIP_MIMXRT1021CAG4A + bool "MIMXRT1021CAG4A" + select ARCH_FAMILY_MIMXRT1021C + +config ARCH_CHIP_MIMXRT1021CAF4A + bool "MIMXRT1021CAF4A" + select ARCH_FAMILY_MIMXRT1021C + +config ARCH_CHIP_MIMXRT1021DAF5A + bool "MIMXRT1021DAF5A" + select ARCH_FAMILY_MIMXRT1021D + +config ARCH_CHIP_MIMXRT1021DAG5A + bool "MIMXRT1021DAG5A" + select ARCH_FAMILY_MIMXRT1021D + config ARCH_CHIP_MIMXRT1051DVL6A bool "MIMXRT1051DVL6A" select ARCH_FAMILY_MXRT105xDVL6A @@ -48,6 +64,30 @@ endchoice # i.MX RT Chip Selection # i.MX RT Families +config ARCH_FAMILY_MIMXRT1021D + bool + default n + select ARCH_FAMILY_IMXRT102x + ---help--- + i.MX RT1020 Crossover Processors for Consumer Products + +config ARCH_FAMILY_MIMXRT1021C + bool + default n + select ARCH_FAMILY_IMXRT102x + ---help--- + i.MX RT1020 Crossover Processors for Industrial Products + +config ARCH_FAMILY_IMXRT102x + bool + default n + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU # REVISIT + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + config ARCH_FAMILY_MXRT105xDVL6A bool default n @@ -348,7 +388,7 @@ menuconfig IMXRT_GPIO_IRQ if IMXRT_GPIO_IRQ config IMXRT_GPIO1_0_15_IRQ - bool "GPIO1 Pins 8-15 interrupts" + bool "GPIO1 Pins 0-15 interrupts" default n config IMXRT_GPIO1_16_31_IRQ diff --git a/arch/arm/src/imxrt/chip/imxrt_ccm.h b/arch/arm/src/imxrt/chip/imxrt_ccm.h index cc1ca0230fb..ce5206e08e1 100644 --- a/arch/arm/src/imxrt/chip/imxrt_ccm.h +++ b/arch/arm/src/imxrt/chip/imxrt_ccm.h @@ -1,9 +1,10 @@ -/************************************************************************************************************ +/***************************************************************************** * arch/arm/src/imxrt/imxrt_ccm.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. * Authors: Janne Rosberg * David Sidrane + * Dave Marples * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -32,1112 +33,25 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************************************/ + *****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H #define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H -/************************************************************************************************************ +/***************************************************************************** * Included Files - ************************************************************************************************************/ + *****************************************************************************/ #include #include "chip/imxrt_memorymap.h" -/************************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************************/ - -/* Register offsets *****************************************************************************************/ - -#define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ - /* 0x0004 Reserved */ -#define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ -#define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ -#define IMXRT_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */ -#define IMXRT_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */ -#define IMXRT_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */ -#define IMXRT_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */ -#define IMXRT_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */ -#define IMXRT_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */ -#define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ -#define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ -#define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ - /* 0x0034 Reserved */ -#define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ -#define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ - /* 0x0040 Reserved */ - /* 0x0044 Reserved */ -#define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ - /* 0x004c Reserved */ - /* 0x0050 Reserved */ -#define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ - -#define IMXRT_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */ -#define IMXRT_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */ -#define IMXRT_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */ -#define IMXRT_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */ -#define IMXRT_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */ -#define IMXRT_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */ -#define IMXRT_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */ -#define IMXRT_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */ -#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ -#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ -#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ - /* 0x0084 Reserved */ -#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */ - -/* Analog */ - -#define IMXRT_CCM_ANALOG_PLL_ARM_OFFSET 0x0000 /* Analog ARM PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET 0x0010 /* Analog USB1 480MHz PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_USB2_OFFSET 0x0020 /* Analog USB2 480MHz PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET 0x0030 /* Analog System PLL Control Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET 0x0040 /* 528MHz System PLL Spread Spectrum Register */ -#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET 0x0050 /* Numerator of 528MHz System PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET 0x0060 /* Denominator of 528MHz System PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET 0x0070 /* Analog Audio PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET 0x0080 /* Numerator of Audio PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET 0x0090 /* Denominator of Audio PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET 0x00a0 /* Analog Video PLL control Register */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET 0x00b0 /* Numerator of Video PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET 0x00c0 /* Denominator of Video PLL Fractional Loop Divider */ -#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET 0x00e0 /* Analog ENET PLL Control Register */ -#define IMXRT_CCM_ANALOG_PFD_480_OFFSET 0x00f0 /* 480MHz Clock (PLL3) Phase Fractional Divider Control */ -#define IMXRT_CCM_ANALOG_PFD_528_OFFSET 0x0100 /* 528MHz Clock (PLL2) Phase Fractional Divider Control */ -#define IMXRT_CCM_ANALOG_MISC0_OFFSET 0x0150 /* Miscellaneous Register 0 */ -#define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ -#define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ - -/* Register addresses ***************************************************************************************/ - -#define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) -#define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) -#define IMXRT_CCM_CCSR (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET) -#define IMXRT_CCM_CACRR (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET) -#define IMXRT_CCM_CBCDR (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET) -#define IMXRT_CCM_CBCMR (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET) -#define IMXRT_CCM_CSCMR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET) -#define IMXRT_CCM_CSCMR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET) -#define IMXRT_CCM_CSCDR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET) -#define IMXRT_CCM_CS1CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET) -#define IMXRT_CCM_CS2CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET) -#define IMXRT_CCM_CDCDR (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET) -#define IMXRT_CCM_CSCDR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET) -#define IMXRT_CCM_CSCDR3 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET) -#define IMXRT_CCM_CDHIPR (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET) -#define IMXRT_CCM_CLPCR (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET) -#define IMXRT_CCM_CISR (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET) -#define IMXRT_CCM_CIMR (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET) -#define IMXRT_CCM_CCOSR (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET) -#define IMXRT_CCM_CGPR (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET) -#define IMXRT_CCM_CCGR0 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET) -#define IMXRT_CCM_CCGR1 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET) -#define IMXRT_CCM_CCGR2 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET) -#define IMXRT_CCM_CCGR3 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET) -#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET) -#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET) -#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET) -#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET) - -#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_USB1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_USB2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB2_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_SS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET) -#define IMXRT_CCM_ANALOG_PLL_ENET (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET) -#define IMXRT_CCM_ANALOG_PFD_480 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET) -#define IMXRT_CCM_ANALOG_PFD_528 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET) -#define IMXRT_CCM_ANALOG_MISC0 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET) -#define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) -#define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) - -/* Helper Macros *********************************************************************************/ - -#define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ - -/* Register bit definitions *********************************************************************************/ - -/* Control Register */ - -#define CCM_CCR_OSCNT_SHIFT (0) /* Bits 0-7: Oscillator ready counter value */ -#define CCM_CCR_OSCNT_MASK (0xff << CCM_CCR_OSCNT_SHIFT) -# define CCM_CCR_OSCNT(n) ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT) - /* Bits 8-11: Reserved */ -#define CCM_CCR_COSC_EN (1 << 12) /* Bit 12: On chip oscillator enable */ - /* Bits 13-20: Reserved */ -#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21) /* Bits 21-26: Counter for analog_reg_bypass */ -#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT) -# define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) -#define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ - /* Bits 28-31: Reserved */ -/* Status Register */ - -#define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ - /* Bits 1-2: Reserved */ -#define CCM_CSR_CAMP2_READY (3 << 0) /* Bit 3: Status indication of CAMP2 */ - /* Bit 4: Reserved */ -#define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ - /* Bits 6-31: Reserved */ -/* Clock Switcher Register */ - -#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ - -/* Arm Clock Root Register */ - -#define CCM_CACRR_ARM_PODF_SHIFT (0) /* Bits 0-2: Divider for ARM clock root */ -#define CCM_CACRR_ARM_PODF_MASK (0x3 << CCM_CACRR_ARM_PODF_SHIFT) -# define CCM_CACRR_ARM_PODF(n) ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT) - -/* Bus Clock Divider Register */ - - /* Bits 0-5: Reserved */ -#define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ -#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3 (1 << 7) /* Bit 7: PLL3 PFD1 will be selected */ -#define CCM_CBCDR_IPG_PODF_SHIFT (8) /* Bits 8-9: Divider for ipg podf */ -#define CCM_CBCDR_IPG_PODF_MASK (0x3 << CCM_CBCDR_IPG_PODF_SHIFT) -# define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT) -#define CCM_CBCDR_AHB_PODF_SHIFT (10) /* Bits 10-12: Divider for AHB PODF */ -#define CCM_CBCDR_AHB_PODF_MASK (0x3 << CCM_CBCDR_AHB_PODF_SHIFT) -# define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT) - /* Bits 13-15: Reserved */ -#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ -#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT) -# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) - /* Bits 19-24: Reserved */ -#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ -#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCDR_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) -# define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) - - /* Bit 26: Reserved */ -#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ -#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) -# define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) - /* Bits 30-31: Reserved */ - -/* Bus Clock Multiplexer Register */ - - /* Bits 0-3: Reserved */ -#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ -#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1 ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) -# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) - /* Bits 6-11: Reserved */ -#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ -#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) -#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for Trace clock multiplexer */ -#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) -# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) - /* Bits 16-17: Reserved */ -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ -#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 (1) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 (2) -# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1 (3) - /* Bits 20-22: Reserved */ -#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */ -#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT) -# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) -#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ -#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) -# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) - -/* Serial Clock Multiplexer Register 1 */ - -#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ -#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) -# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) -#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6) /* Bit 6: Selector for the perclk clock multiplexer */ -#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) -# define CCM_CSCMR1_PERCLK_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) -# define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0) -# define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK (1) - /* Bits 7-9: Reserved */ -#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for sai1 clock multiplexer */ -#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI1_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) -#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for sai2 clock multiplexer */ -#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI2_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) -#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for sai3 clock multiplexer */ -#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -# define CCM_CSCMR1_SAI3_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) -#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ -# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2 (0 << 16) /* derive clock from PLL2 PFD2 */ -# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 (1 << 16) /* derive clock from PLL2 PFD0 */ -#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ -# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2 (0 << 17) /* derive clock from PLL2 PFD2 */ -# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0 (1 << 17) /* derive clock from PLL2 PFD0 */ - /* Bits 18-22: Reserved */ -#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23) /* Bits 23-25: Divider for flexspi clock root */ -#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) -# define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) - /* Bits 26-28: Reserved */ -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29) /* Bits 29-30: Selector for flexspi clock multiplexer */ -#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) -# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) - /* Bit 31: Reserved */ - -/* Serial Clock Multiplexer Register 2 */ - -#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ -#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) -# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) -#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for FlexCAN clock multiplexer */ -#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60 ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) -# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80 ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) - /* Bits 10-18: Reserved */ -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for flexio2 clock multiplexer */ -#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) -# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) - /* Bits 21-31: Reserved */ - -/* Serial Clock Divider Register 1 */ - -#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ -#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) -# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) -#define CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Bit 6: Selector for the UART clock multiplexer */ -# define CCM_CSCDR1_UART_CLK_SEL_PLL3_80 (0 << 6) /* derive clock from pll3_80m */ -# define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK (1 << 6) /* derive clock from osc_clk */ - /* Bits 7-10: Reserved */ -#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ -#define CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) -# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) - /* Bits 14-15: Reserved */ -#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ -#define CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) -# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) - /* Bits 19-24: Reserved */ -#define CCM_CSCDR1_TRACE_PODF_SHIFT (25) /* Bits 25-27: Divider for trace clock */ -#define CCM_CSCDR1_TRACE_PODF_MASK (0x7 << CCM_CSCDR1_TRACE_PODF_SHIFT) -# define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT) - /* Bits 28-31: Reserved */ - -/* Clock Divider Register 1 */ - -#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai1 clock podf */ -#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) -# define CCM_CS1CDR_SAI1_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) -#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai1 clock pred */ -#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) -# define CCM_CS1CDR_SAI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for flexio2 clock */ -#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) -# define CCM_CS1CDR_FLEXIO2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) - /* Bits 12-15: Reserved */ -#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for sai3 clock podf */ -#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) -# define CCM_CS1CDR_SAI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) -#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for sai3 clock pred */ -#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) -# define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for flexio2 clock */ -#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) -# define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) - /* Bits 28-31: Reserved */ - -/* Clock Divider Register 2 */ - -#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai2 clock podf */ -#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) -# define CCM_CS2CDR_SAI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) -#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai2 clock pred */ -#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) -# define CCM_CS2CDR_SAI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) - -/* D1 Clock Divider Register */ - -#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7) /* Bits 7-8: Selector for flexio1 clock multiplexer */ -#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x3 << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) -#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9) /* Bits 9-11: Divider for flexio1 clock podf */ -#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) -#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12) /* Bits 12-14: Divider for flexio1 clock pred */ -#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) -# define CCM_CDCDR_FLEXIO1_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) - /* Bits 15-19: Reserved */ -#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ -#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) -#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ -#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) -#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ -#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) -# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) - -/* Serial Clock Divider Register 2 */ - - /* Bits 0-8: Reserved */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for LCDIF root clock multiplexer */ -#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_LCDIF ((uint32_t)(0) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI0_CLK ((uint32_t)(1) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI1_CLK ((uint32_t)(2) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI0_CLK ((uint32_t)(3) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI1_CLK ((uint32_t)(4) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) -#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12) /* Bits 12-14: Pre-divider for lcdif clock */ -#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << CCM_CSCDR2_LCDIF_PRED_SHIFT) -# define CCM_CSCDR2_LCDIF_PRED(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRED_SHIFT) -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for lcdif root clock pre-multiplexer */ -#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD3 ((uint32_t)(1) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD0 ((uint32_t)(3) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD1 ((uint32_t)(4) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD1 ((uint32_t)(5) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) -#define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ -# define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ -# define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ -#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for lpi2c clock podf */ -#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) -# define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) - /* Bits 25-31: Reserved */ - -/* Serial Clock Divider Register 3 */ - - /* Bits 0-8: Reserved */ -#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9) /* Bits 9-10: Selector for csi_mclk multiplexer */ -#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_CLK ((uint32_t)(0) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL2_PFD2 ((uint32_t)(1) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_120M ((uint32_t)(2) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_PFD1 ((uint32_t)(3) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) -#define CCM_CSCDR3_CSI_PODF_SHIFT (11) /* Bits 11-13: Post divider for csi_mclk */ -#define CCM_CSCDR3_CSI_PODF_MASK (0x3 << CCM_CSCDR3_CSI_PODF_SHIFT) -# define CCM_CSCDR3_CSI_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_PODF_SHIFT) - -/* Divider Handshake In-Process Register */ - -#define CCM_CDHIPR_SEMC_PODF_BUSY (1 << 0) /* Bit 0: Busy indicator for semc_podf */ -#define CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) /* Bit 1: Busy indicator for ahb_podf */ - /* Bit 2: Reserved */ -#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) /* Bit 3: Busy indicator for periph2_clk_sel mux control */ - /* Bit 4: Reserved */ -#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) /* Bit 5: Busy indicator for periph_clk_sel mux control */ - /* Bits 6-15: Reserved */ -#define CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) /* Bit 16: Busy indicator for arm_podf */ - /* Bits 17-31: Reserved */ - -/* Low Power Control Register */ - -#define CCM_CLPCR_LPM_SHIFT (0) /* Bits 0-1: Setting the low power mode */ -#define CCM_CLPCR_LPM_MASK (0x3 << CCM_CLPCR_LPM_SHIFT) -# define CCM_CLPCR_LPM(n) ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT) -# define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ -# define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ -# define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ - /* Bits 2-4: Reserved */ -#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ -#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ -#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ -#define CCM_CLPCR_VSTBY (1 << 8) /* Bit 8: Voltage standby request bit */ -#define CCM_CLPCR_STBY_COUNT_SHIFT (9) /* Bits 9-10: Standby counter definition */ -#define CCM_CLPCR_STBY_COUNT_MASK (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT) -# define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT) -#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: On chip oscillator power down */ - /* Bits 12-18: Reserved */ -#define CCM_CLPCR_BYPASS_LPM_HS1 (1 << 19) /* Bit 19: Bypass low power mode handshake */ - /* Bit 20: Reserved */ -#define CCM_CLPCR_BYPASS_LPM_HS0 (1 << 21) /* Bit 21: Bypass low power mode handshake */ -#define CCM_CLPCR_MASK_CORE0_WFI (1 << 22) /* Bit 22: Mask WFI of core0 for entering low power mode */ - /* Bits 23-25: Reserved */ -#define CCM_CLPCR_MASK_SCU_IDLE (1 << 26) /* Bit 26: Mask SCU IDLE for entering low power mode */ -#define CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) /* Bit 27: Mask L2CC IDLE for entering low power mode */ - /* Bits 28-31: Reserved */ - -/* Interrupt Status Register */ - -#define CCM_CISR_LRF_PLL (1 << 0) /* Bit 0: CCM irq2, lock of all enabled and not bypassed PLLs */ - /* Bits 1-5: Reserved */ -#define CCM_CISR_COSC_READY (1 << 6) /* Bit 6: CCM irq2, on board oscillator ready */ - /* Bits 7-16: Reserved */ -#define CCM_CISR_SEMC_PODF_LOADED (1 << 17) /* Bit 17: CCM irq1, frequency change of semc_podf */ - /* Bit 18: Reserved */ -#define CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: CCM irq1, frequency change of periph2_clk_sel */ -#define CCM_CISR_AHB_PODF_LOADED (1 << 20) /* Bit 20: CCM irq1, frequency change of ahb_podf */ - /* Bit 21: Reserved */ -#define CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: CCM irq1, update of periph_clk_sel */ - /* Bits 23-25: Reserved */ -#define CCM_CISR_ARM_PODF_LOADED (1 << 26) /* Bit 26: CCM irq1, frequency change of arm_podf */ - /* Bits 27-31: Reserved */ - -/* Interrupt Mask Register */ - -#define CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Bit 0: mask interrupt generation due to lrf of PLLs */ - /* Bits 1-5: Reserved */ -#define CCM_CIMR_MASK_COSC_READY (1 << 6) /* Bit 6: mask interrupt generation due to on board oscillator ready */ - /* Bits 7-16: Reserved */ -#define CCM_CIMR_MASK_SEMC_PODF_LOADED (1 << 17) /* Bit 17: mask interrupt generation due to frequency change of semc_podf */ - /* Bit 18: Reserved */ -#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: mask interrupt generation due to update of periph2_clk_sel */ -#define CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) /* Bit 20: mask interrupt generation due to frequency change of ahb_podf */ - /* Bit 21: Reserved */ -#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: mask interrupt generation due to update of periph_clk_sel */ - /* Bits 23-25: Reserved */ -#define CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) /* Bit 26: mask interrupt generation due to frequency change of arm_podf */ - /* Bits 27-31: Reserved */ - -/* Clock Output Source Register */ - -#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ -#define CCM_CCOSR_CLKO1_SEL_MASK (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_SEMC_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_ENC_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_LCDIF_PIX_CLK ((uint32_t)(10) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_AHB_CLK ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_IPG_CLK ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PER_CLK ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT) -#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ -#define CCM_CCOSR_CLKO1_DIV_MASK (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT) -# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) -#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ -#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ - /* Bits 9-15: Reserved */ -#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ -#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_CSI_CORE ((uint32_t)(11) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_OSC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI1_CLK ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI2_CLK ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SAI3_CLK ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_CAN_CLK ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_UART_CLK ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT) -#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ -#define CCM_CCOSR_CLKO2_DIV_MASK (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT) -# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) -#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ - /* Bits 25-31: Reserved */ - -/* General Purpose Register */ - -#define CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Bit 0: Defines clock division of clock for stby_count */ - /* Bits 1-3: Reserved */ -#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) /* Bit 4: allow fuse programing */ - /* Bits 5-13: Reserved */ -#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14) /* Bits 14-15: System memory DS control */ -#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) -# define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) -#define CCM_CGPR_FPL (1 << 16) /* Bit 16: Fast PLL enable */ -#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) /* Bit 17: Control for the Deep Sleep signal to the ARM Platform memories */ - /* Bits 18-31: Reserved */ - -/* Clock Gating Register 0-6 */ - -#define CCM_CG_OFF (0) /* Clock is off during all modes */ -#define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ -#define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ - -#define CCM_CCGRX_CG_SHIFT(r) ((r) << 1) -#define CCM_CCGRX_CG_MASK(r) (0x3 << CCM_CCGRX_CG_SHIFT(r)) -# define CCM_CCGRX_CG(r,v) ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r)) - -#define CCM_CCGRX_CG0_SHIFT (0) -#define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) -# define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) -#define CCM_CCGRX_CG1_SHIFT (2) -#define CCM_CCGRX_CG1_MASK (0x3 << CCM_CCGRX_CG1_SHIFT) -# define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) -#define CCM_CCGRX_CG2_SHIFT (4) -#define CCM_CCGRX_CG2_MASK (0x3 << CCM_CCGRX_CG2_SHIFT) -# define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) -#define CCM_CCGRX_CG3_SHIFT (6) -#define CCM_CCGRX_CG3_MASK (0x3 << CCM_CCGRX_CG3_SHIFT) -# define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) -#define CCM_CCGRX_CG4_SHIFT (8) -#define CCM_CCGRX_CG4_MASK (0x3 << CCM_CCGRX_CG4_SHIFT) -# define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) -#define CCM_CCGRX_CG5_SHIFT (10) -#define CCM_CCGRX_CG5_MASK (0x3 << CCM_CCGRX_CG5_SHIFT) -# define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) -#define CCM_CCGRX_CG6_SHIFT (12) -#define CCM_CCGRX_CG6_MASK (0x3 << CCM_CCGRX_CG6_SHIFT) -# define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) -#define CCM_CCGRX_CG7_SHIFT (14) -#define CCM_CCGRX_CG7_MASK (0x3 << CCM_CCGRX_CG7_SHIFT) -# define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) -#define CCM_CCGRX_CG8_SHIFT (16) -#define CCM_CCGRX_CG8_MASK (0x3 << CCM_CCGRX_CG8_SHIFT) -# define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) -#define CCM_CCGRX_CG9_SHIFT (18) -#define CCM_CCGRX_CG9_MASK (0x3 << CCM_CCGRX_CG9_SHIFT) -# define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) -#define CCM_CCGRX_CG10_SHIFT (20) -#define CCM_CCGRX_CG10_MASK (0x3 << CCM_CCGRX_CG10_SHIFT) -# define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) -#define CCM_CCGRX_CG11_SHIFT (22) -#define CCM_CCGRX_CG11_MASK (0x3 << CCM_CCGRX_CG11_SHIFT) -# define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) -#define CCM_CCGRX_CG12_SHIFT (24) -#define CCM_CCGRX_CG12_MASK (0x3 << CCM_CCGRX_CG12_SHIFT) -# define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) -#define CCM_CCGRX_CG13_SHIFT (26) -#define CCM_CCGRX_CG13_MASK (0x3 << CCM_CCGRX_CG13_SHIFT) -# define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) -#define CCM_CCGRX_CG14_SHIFT (28) -#define CCM_CCGRX_CG14_MASK (0x3 << CCM_CCGRX_CG14_SHIFT) -# define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) -#define CCM_CCGRX_CG15_SHIFT (30) -#define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) -# define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) - -/* Macros used by imxrt_periphclks.h */ - -#define CCM_CCGR_GPIO2 IMXRT_CCM_CCGR0, 15 -#define CCM_CCGR_LPUART2 IMXRT_CCM_CCGR0, 14 -#define CCM_CCGR_GPT2_SERIAL IMXRT_CCM_CCGR0, 13 -#define CCM_CCGR_GPT2_BUS IMXRT_CCM_CCGR0, 12 -#define CCM_CCGR_TRACE IMXRT_CCM_CCGR0, 11 -#define CCM_CCGR_CAN2_SERIAL IMXRT_CCM_CCGR0, 10 -#define CCM_CCGR_CAN2 IMXRT_CCM_CCGR0, 9 -#define CCM_CCGR_CAN1_SERIAL IMXRT_CCM_CCGR0, 8 -#define CCM_CCGR_CAN1 IMXRT_CCM_CCGR0, 7 -#define CCM_CCGR_LPUART3 IMXRT_CCM_CCGR0, 6 -#define CCM_CCGR_DCP IMXRT_CCM_CCGR0, 5 -#define CCM_CCGR_MQS IMXRT_CCM_CCGR0, 2 -#define CCM_CCGR_AIPS_TZ2 IMXRT_CCM_CCGR0, 1 -#define CCM_CCGR_AIPS_TZ1 IMXRT_CCM_CCGR0, 0 - -#define CCM_CCGR_CSU IMXRT_CCM_CCGR1, 14 -#define CCM_CCGR_GPIO1 IMXRT_CCM_CCGR1, 13 -#define CCM_CCGR_LPUART4 IMXRT_CCM_CCGR1, 12 -#define CCM_CCGR_GPT_SERIAL IMXRT_CCM_CCGR1, 11 -#define CCM_CCGR_GPT_BUS IMXRT_CCM_CCGR1, 10 -#define CCM_CCGR_ADC1 IMXRT_CCM_CCGR1, 8 -#define CCM_CCGR_AOI2 IMXRT_CCM_CCGR1, 7 -#define CCM_CCGR_PIT IMXRT_CCM_CCGR1, 6 -#define CCM_CCGR_ENET IMXRT_CCM_CCGR1, 5 -#define CCM_CCGR_ADC2 IMXRT_CCM_CCGR1, 4 -#define CCM_CCGR_LPSPI4 IMXRT_CCM_CCGR1, 3 -#define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 -#define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 -#define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 - -#define CCM_CCGR_PXP IMXRT_CCM_CCGR2, 15 -#define CCM_CCGR_LCD IMXRT_CCM_CCGR2, 14 -#define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 -#define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 -#define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 -#define CCM_CCGR_IPMUX3 IMXRT_CCM_CCGR2, 10 -#define CCM_CCGR_IPMUX2 IMXRT_CCM_CCGR2, 9 -#define CCM_CCGR_IPMUX1 IMXRT_CCM_CCGR2, 8 -#define CCM_CCGR_XBAR3 IMXRT_CCM_CCGR2, 7 -#define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 -#define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 -#define CCM_CCGR_LPI2C2 IMXRT_CCM_CCGR2, 4 -#define CCM_CCGR_LPI2C1 IMXRT_CCM_CCGR2, 3 -#define CCM_CCGR_IOMUXC_SNVS IMXRT_CCM_CCGR2, 2 -#define CCM_CCGR_CSI IMXRT_CCM_CCGR2, 1 - -#define CCM_CCGR_IOMUXC_SNVS_GPR IMXRT_CCM_CCGR3, 15 -#define CCM_CCGR_OCRAM IMXRT_CCM_CCGR3, 14 -#define CCM_CCGR_ACMP4 IMXRT_CCM_CCGR3, 13 -#define CCM_CCGR_ACMP3 IMXRT_CCM_CCGR3, 12 -#define CCM_CCGR_ACMP2 IMXRT_CCM_CCGR3, 11 -#define CCM_CCGR_ACMP1 IMXRT_CCM_CCGR3, 10 -#define CCM_CCGR_FLEXRAM IMXRT_CCM_CCGR3, 9 -#define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 -#define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 -#define CCM_CCGR_GPIO4 IMXRT_CCM_CCGR3, 6 -#define CCM_CCGR_LCDIF_PIX IMXRT_CCM_CCGR3, 5 -#define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 -#define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 -#define CCM_CCGR_SEMC IMXRT_CCM_CCGR3, 2 -#define CCM_CCGR_LPUART5 IMXRT_CCM_CCGR3, 1 -#define CCM_CCGR_FLEXIO2 IMXRT_CCM_CCGR3, 0 - -#define CCM_CCGR_ENC4 IMXRT_CCM_CCGR4, 15 -#define CCM_CCGR_ENC3 IMXRT_CCM_CCGR4, 14 -#define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 -#define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 -#define CCM_CCGR_PWM4 IMXRT_CCM_CCGR4, 11 -#define CCM_CCGR_PWM3 IMXRT_CCM_CCGR4, 10 -#define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 -#define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 -#define CCM_CCGR_SIM_EMS IMXRT_CCM_CCGR4, 7 -#define CCM_CCGR_SIM_M IMXRT_CCM_CCGR4, 6 -#define CCM_CCGR_TSC_DIG IMXRT_CCM_CCGR4, 5 -#define CCM_CCGR_SIM_M7 IMXRT_CCM_CCGR4, 4 -#define CCM_CCGR_BEE IMXRT_CCM_CCGR4, 3 -#define CCM_CCGR_IOMUXC_GPR IMXRT_CCM_CCGR4, 2 -#define CCM_CCGR_IOMUXC IMXRT_CCM_CCGR4, 1 - -#define CCM_CCGR_SNVS_LP IMXRT_CCM_CCGR5, 15 -#define CCM_CCGR_SNVS_HP IMXRT_CCM_CCGR5, 14 -#define CCM_CCGR_LPUART7 IMXRT_CCM_CCGR5, 13 -#define CCM_CCGR_LPUART1 IMXRT_CCM_CCGR5, 12 -#define CCM_CCGR_SAI3 IMXRT_CCM_CCGR5, 11 -#define CCM_CCGR_SAI2 IMXRT_CCM_CCGR5, 10 -#define CCM_CCGR_SAI1 IMXRT_CCM_CCGR5, 9 -#define CCM_CCGR_SIM_MAIN IMXRT_CCM_CCGR5, 8 -#define CCM_CCGR_SPDIF IMXRT_CCM_CCGR5, 7 -#define CCM_CCGR_AIPSTZ4 IMXRT_CCM_CCGR5, 6 -#define CCM_CCGR_WDOG2 IMXRT_CCM_CCGR5, 5 -#define CCM_CCGR_KPP IMXRT_CCM_CCGR5, 4 -#define CCM_CCGR_DMA IMXRT_CCM_CCGR5, 3 -#define CCM_CCGR_WDOG3 IMXRT_CCM_CCGR5, 2 -#define CCM_CCGR_FLEXIO1 IMXRT_CCM_CCGR5, 1 -#define CCM_CCGR_ROM IMXRT_CCM_CCGR5, 0 - -#define CCM_CCGR_TIMER3 IMXRT_CCM_CCGR6, 15 -#define CCM_CCGR_TIMER2 IMXRT_CCM_CCGR6, 14 -#define CCM_CCGR_TIMER1 IMXRT_CCM_CCGR6, 13 -#define CCM_CCGR_LPI2C4_SERIAL IMXRT_CCM_CCGR6, 12 -#define CCM_CCGR_ANADIG IMXRT_CCM_CCGR6, 11 -#define CCM_CCGR_SIM_PER IMXRT_CCM_CCGR6, 10 -#define CCM_CCGR_AIPS_TZ3 IMXRT_CCM_CCGR6, 9 -#define CCM_CCGR_TIMER4 IMXRT_CCM_CCGR6, 8 -#define CCM_CCGR_LPUART8 IMXRT_CCM_CCGR6, 7 -#define CCM_CCGR_TRNG IMXRT_CCM_CCGR6, 6 -#define CCM_CCGR_FLEXSPI IMXRT_CCM_CCGR6, 5 -#define CCM_CCGR_IPMUX4 IMXRT_CCM_CCGR6, 4 -#define CCM_CCGR_DCDC IMXRT_CCM_CCGR6, 3 -#define CCM_CCGR_USDHC2 IMXRT_CCM_CCGR6, 2 -#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1 -#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0 - -/* Module Enable Override Register */ - - /* Bits 0-4: Reserved */ -#define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ -#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Overide clock enable signal from PIT */ -#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Overide clock enable signal from USDHC */ -#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Overide clock enable signal from TRNG */ - /* Bits 10-27: Reserved */ -#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */ -#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */ - /* Bit 31: Reserved */ - -/* Analog ARM PLL control Register */ - -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider 54-108 */ -#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ARM_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) - /* Bits 7-11 Reserved */ -#define CCM_ANALOG_PLL_ARM_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_ARM_ENABLE (1 << 13) /* Bit 13: Enable the clock output */ -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_ARM_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-18 Reserved */ -#define CCM_ANALOG_PLL_ARM_PLL_SEL (1 << 39) /* Bit 19: ? */ -#define CCM_ANALOG_PLL_ARM_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog USB1 480MHz PLL Control Register */ - -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x1 << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB1_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB1_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) - /* Bits 2-5 Reserved */ -#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ -#define CCM_ANALOG_PLL_USB1_POWER (1 << 12) /* Bit 12: Powers up the PLL */ -#define CCM_ANALOG_PLL_USB1_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ -# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ -#define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ -#define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog USB2 480MHz PLL Control Register */ - -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB2_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_USB2_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) - /* Bits 2-5 Reserved */ -#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ -#define CCM_ANALOG_PLL_USB2_POWER (1 << 12) /* Bit 12: Powers up the PLL */ -#define CCM_ANALOG_PLL_USB2_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_USB2_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ -#define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Analog System PLL Control Register */ - -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ -#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT_20 (0) -# define CCM_ANALOG_PLL_SYS_DIV_SELECT_22 (1) -#define CCM_ANALOG_PLL_SYS_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_SYS_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ -# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ -#define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ - /* Bits 19-30 Reserved */ -#define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* 528MHz System PLL Spread Spectrum Register */ - -#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0) /* Bits 0-14: Frequency change step */ -#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) -# define CCM_ANALOG_PLL_SYS_SS_STEP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) -#define CCM_ANALOG_PLL_SYS_SS_ENABLE (1 << 15) /* Bit 15: Enable bit */ -#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (0) /* Bits 16-31: Frequency change */ -#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) -# define CCM_ANALOG_PLL_SYS_SS_STOP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) - -/* Numerator of 528MHz System PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_SYS_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) - /* Bits 30-31: Reserved */ - -/* Denominator of 528MHz System PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_SYS_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ - -/* Analog Audio PLL control Register */ - -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ -#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) - /* Bits 7-11: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ -#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) - /* Bits 21-30: Reserved */ -#define CCM_ANALOG_PLL_AUDIO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Numerator of Audio PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_AUDIO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) -/* Bits 30-31: Reserved */ - -/* Denominator of Audio PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ -/* Analog Video PLL control Register */ - -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ -#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) - /* Bits 7-11: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_VIDEO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_VIDEO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ -#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) - /* Bits 21-30: Reserved */ -#define CCM_ANALOG_PLL_VIDEO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* Numerator of Video PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) -#define CCM_ANALOG_PLL_VIDEO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) - /* Bits 30-31: Reserved */ - -/* Denominator of Video PLL Fractional Loop Divider Register */ - -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ -#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) -#define CCM_ANALOG_PLL_VIDEO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) - /* Bits 30-31: Reserved */ - -/* Analog ENET PLL Control Register */ - -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2) /* Bits 0-1: Controls the frequency of the ethernet1 reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) -# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) - /* Bits 4-11: Reserved */ -#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ -#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) -# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ -# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ - -/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ - -#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD0_STABLE (6) /* Bit 6: */ -#define CCM_ANALOG_PFD_480_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD1_STABLE (14) /* Bit 14: */ -#define CCM_ANALOG_PFD_480_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD2_STABLE (22) /* Bit 22: */ -#define CCM_ANALOG_PFD_480_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) -# define CCM_ANALOG_PFD_480_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) -#define CCM_ANALOG_PFD_480_PFD3_STABLE (30) /* Bit 30: */ -#define CCM_ANALOG_PFD_480_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ - -/* 528MHz Clock (PLL2) Phase Fractional Divider Control */ - -#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD0_STABLE (6) /* Bit 6: */ -#define CCM_ANALOG_PFD_528_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD1_STABLE (14) /* Bit 14: */ -#define CCM_ANALOG_PFD_528_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD2_STABLE (22) /* Bit 22: */ -#define CCM_ANALOG_PFD_528_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ -#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ -#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) -# define CCM_ANALOG_PFD_528_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) -#define CCM_ANALOG_PFD_528_PFD3_STABLE (30) /* Bit 30: */ -#define CCM_ANALOG_PFD_528_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ - -/* Miscellaneous Register 0 */ - -#define CCM_ANALOG_MISC0_REFTOP_PWD (1 << 0) /* Bit 0: Control bit to power-down the analog bandgap reference circuitry */ - /* Bits 1-2: Reserved */ -#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF (1 << 2) /* Bit 3: Control bit to disable the self-bias circuit in the analog bandgap */ -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4) /* Bits 4-6: VBG (PMU) */ -#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x3 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) -# define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) -#define CCM_ANALOG_MISC0_REFTOP_VBGUP (1 << 7) /* Bit 7: Status bit that signals the analog bandgap voltage is up and stable */ - /* Bits 8-9: Reserved */ -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10) /* Bits 10-11: Configure the analog behavior in stop mode */ -#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) -# define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) -#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS (1 << 12) /* Bit 12: This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */ -#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13) /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */ -#define CCM_ANALOG_MISC0_OSC_I_MASK (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT) -# define CCM_ANALOG_MISC0_OSC_I(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT) -#define CCM_ANALOG_MISC0_OSC_XTALOK (1 << 15) /* Bit 15: bit that signals 24-MHz crystal oscillator is stable */ -#define CCM_ANALOG_MISC0_OSC_XTALOK_EN (1 << 16) /* Bit 16: enables the detector that signals 24MHz crystal oscillator is stable */ - /* Bits 17-24: Reserved */ -#define CCM_ANALOG_MISC0_CLKGATE_CTRL (1 << 25) /* Bit 25: This bit allows disabling the clock gate */ -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26) /* Bits 26-28: delay powering up the XTAL 24MHz */ -#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) -# define CCM_ANALOG_MISC0_CLKGATE_DELAY(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) -#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE (1 << 29) /* Bit 29: which chip source is being used for the rtc clock */ -#define CCM_ANALOG_MISC0_XTAL_24M_PWD (1 << 30) /* Bit 30: power down the 24M crystal oscillator if set true */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_1 (0 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ -#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_2 (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ - -/* Miscellaneous Register 1 */ - -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0) /* Bits 0-4: This field selects the clk to be routed to anaclk1/1b */ -#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1f << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ARM_PLL ((uint32_t)(0) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SYS_PLL ((uint32_t)(1) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD4 ((uint32_t)(2) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD5 ((uint32_t)(3) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD6 ((uint32_t)(4) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD7 ((uint32_t)(5) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_AUDIO_PLL ((uint32_t)(6) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_VIDEO_PLL ((uint32_t)(7) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ETHERNET_REF ((uint32_t)(9) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB1_PLL ((uint32_t)(12) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB2_PLL ((uint32_t)(13) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD0 ((uint32_t)(14) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD1 ((uint32_t)(15) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD2 ((uint32_t)(16) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD3 ((uint32_t)(17) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) -# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_XTAL ((uint32_t)(18) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) - /* Bits 5-9: Reserved */ -#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN (1 << 10) /* Bit 10: This enables the LVDS output buffer for anaclk1/1b */ - /* Bit 11: Reserved */ -#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN (1 << 12) /* Bit 12: This enables the LVDS input buffer for anaclk1/1b */ - /* Bits 13-15: Reserved */ -#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ -#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ - /* Bits 18-26: Reserved */ -#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC (1 << 27) /* Bit 27: temperature sensor panic interrupt */ -#define CCM_ANALOG_MISC1_IRQ_TEMPLOW (1 << 28) /* Bit 28: temperature sensor low interrupt */ -#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH (1 << 29) /* Bit 29: temperature sensor high interrupt */ -#define CCM_ANALOG_MISC1_IRQ_ANA_BO (1 << 30) /* Bit 30: analog regulator brownout interrupt */ -#define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ - -/* Miscellaneous Register 2 */ - -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */ - /* Bit 4: Reserved */ -#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ -#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ - /* Bit 12: Reserved */ -#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ -#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ - -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ -#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) -#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ - /* Bit 20: Reserved */ -#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ -#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ -#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ -#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) -# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) - -#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ -#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) -# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) - +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include "chip/rt102x/imxrt102x_ccm.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/rt105x/imxrt105x_ccm.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) +# include "chip/rt106x/imxrt106x_ccm.h" +#else +# error Unrecognized i.MX RT architecture +#endif #endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_dmamux.h b/arch/arm/src/imxrt/chip/imxrt_dmamux.h index ff58300b675..6bbde542aac 100644 --- a/arch/arm/src/imxrt/chip/imxrt_dmamux.h +++ b/arch/arm/src/imxrt/chip/imxrt_dmamux.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/chip/imxrt_dmamux.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,33 +32,35 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H #define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip/imxrt_memorymap.h" -#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/imxrt105x_dmamux.h" +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include "chip/rt102x/imxrt102x_dmamux.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/rt105x/imxrt105x_dmamux.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/imxrt106x_dmamux.h" +# include "chip/rt106x/imxrt106x_dmamux.h" #else # error Unrecognized i.MX RT architecture #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor definitions - ************************************************************************************/ + ****************************************************************************/ #define IMXRT_DMAMUX_NCHAN 32 -/* DMAMUX Register Offsets **********************************************************/ +/* DMAMUX Register Offsets **************************************************/ #define IMXRT_DMAMUX_CHCFG_OFFSET(n) ((uintptr_t)(n) << 2) # define IMXRT_DMAMUX_CHCFG0_OFFSET 0x0000 /* Channel configuration register 0 */ @@ -94,7 +96,7 @@ # define IMXRT_DMAMUX_CHCFG30_OFFSET 0x0078 /* Channel configuration register 30 */ # define IMXRT_DMAMUX_CHCFG31_OFFSET 0x007c /* Channel configuration register 31 */ -/* DMAMUX Register Addresses ********************************************************/ +/* DMAMUX Register Addresses ************************************************/ #define IMXRT_DMAMUX_CHCFG(n) (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG_OFFSET(n)) # define IMXRT_DMAMUX_CHCFG0 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG0_OFFSET) @@ -130,7 +132,7 @@ # define IMXRT_DMAMUX_CHCFG30 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG30_OFFSET) # define IMXRT_DMAMUX_CHCFG31 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG31_OFFSET) -/* DMAMUX Bit-Field Definitions *****************************************************/ +/* DMAMUX Bit-Field Definitions *********************************************/ /* Channel configuration registers 0-31 */ diff --git a/arch/arm/src/imxrt/chip/imxrt_enet.h b/arch/arm/src/imxrt/chip/imxrt_enet.h index 1e2ae7db667..4aa725475ca 100644 --- a/arch/arm/src/imxrt/chip/imxrt_enet.h +++ b/arch/arm/src/imxrt/chip/imxrt_enet.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/***************************************************************************** * arch/arm/src/imxrt/chip/imxrt_enet.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,24 +31,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + *****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H #define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H -/******************************************************************************************** +/***************************************************************************** * Included Files - ********************************************************************************************/ + *****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/***************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + *****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets **********************************************************/ #define IMXRT_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */ #define IMXRT_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */ @@ -103,7 +103,7 @@ #define IMXRT_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */ #define IMXRT_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses ********************************************************/ #define IMXRT_ENET_EIR (IMXRT_ENET_BASE+IMXRT_ENET_EIR_OFFSET) #define IMXRT_ENET_EIMR (IMXRT_ENET_BASE+IMXRT_ENET_EIMR_OFFSET) @@ -156,7 +156,7 @@ #define IMXRT_ENET_TCSR3 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR3_OFFSET) #define IMXRT_ENET_TCCR3 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR3_OFFSET) -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions **************************************************/ /* Interrupt Event Register, Interrupt Mask Register */ /* Bits 0-14: Reserved */ @@ -199,6 +199,7 @@ #define ENET_ECR_DBSWP (1 << 8) /* Bit 8: Swap bytes */ #endif /* Bits 9-31: Reserved */ +#define ECR_RESV_VAL (7 << 28) /* Reserve val to write */ /* MII Management Frame Register */ #define ENET_MMFR_DATA_SHIFT (0) /* Bits 0-15: Management frame data */ @@ -453,20 +454,20 @@ /* Bits 8-31: Reserved */ /* Timer Compare Capture Register (32-bit compare value) */ -/* Buffer Descriptors ***********************************************************************/ +/* Buffer Descriptors ********************************************************/ /* Endian-independent descriptor offsets */ -#define DESC_STATUS1_OFFSET (0) -#define DESC_LENGTH_OFFSET (2) -#define DESC_DATAPTR_OFFSET (4) -#define DESC_LEGACY_LEN (8) +#define DESC_STATUS1_OFFSET (0) +#define DESC_LENGTH_OFFSET (2) +#define DESC_DATAPTR_OFFSET (4) +#define DESC_LEGACY_LEN (8) -#define DESC_STATUS2_OFFSET (8) -#define DESC_LENPROTO_OFFSET (12) -#define DESC_CHECKSUM_OFFSET (14) -#define DESC_BDU_OFFSET (16) -#define DESC_TIMESTAMP_OFFSET (20) -#define DESC_ENHANCED_LEN (32) +#define DESC_STATUS2_OFFSET (8) +#define DESC_LENPROTO_OFFSET (12) +#define DESC_CHECKSUM_OFFSET (14) +#define DESC_BDU_OFFSET (16) +#define DESC_TIMESTAMP_OFFSET (20) +#define DESC_ENHANCED_LEN (32) /* Legacy/Common TX Buffer Descriptor Bit Definitions. * @@ -599,10 +600,12 @@ # define RXDESC_BDU (1 << 7) #endif -/******************************************************************************************** +/***************************************************************************** * Public Types - ********************************************************************************************/ -/* Buffer Descriptors ***********************************************************************/ + *****************************************************************************/ + +/* Buffer Descriptors ********************************************************/ + /* Legacy Buffer Descriptor */ #ifdef CONFIG_ENET_ENHANCEDBD @@ -658,12 +661,12 @@ struct enet_desc_s #endif /* IMXRT_USE_DBSWAP */ #endif /* CONFIG_ENET_ENHANCEDBD */ -/******************************************************************************************** +/***************************************************************************** * Public Data - ********************************************************************************************/ + *****************************************************************************/ -/******************************************************************************************** +/***************************************************************************** * Public Functions - ********************************************************************************************/ + *****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_gpio.h b/arch/arm/src/imxrt/chip/imxrt_gpio.h index 9b030ad97d8..28d979bf751 100644 --- a/arch/arm/src/imxrt/chip/imxrt_gpio.h +++ b/arch/arm/src/imxrt/chip/imxrt_gpio.h @@ -43,10 +43,12 @@ #include -#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/imxrt105x_gpio.h" +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include "chip/rt102x/imxrt102x_gpio.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/rt105x/imxrt105x_gpio.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/imxrt106x_gpio.h" +# include "chip/rt106x/imxrt106x_gpio.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h index 6d3aa454271..53fa0a38627 100644 --- a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h @@ -43,10 +43,12 @@ #include -#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/imxrt105x_iomuxc.h" +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include "chip/rt102x/imxrt102x_iomuxc.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/rt105x/imxrt105x_iomuxc.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/imxrt106x_iomuxc.h" +# include "chip/rt106x/imxrt106x_iomuxc.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/chip/imxrt_memorymap.h b/arch/arm/src/imxrt/chip/imxrt_memorymap.h index e6352da0a16..217b5a20f69 100644 --- a/arch/arm/src/imxrt/chip/imxrt_memorymap.h +++ b/arch/arm/src/imxrt/chip/imxrt_memorymap.h @@ -42,10 +42,12 @@ #include -#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/imxrt105x_memorymap.h" +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include "chip/rt102x/imxrt102x_memorymap.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/rt105x/imxrt105x_memorymap.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/imxrt106x_memorymap.h" +# include "chip/rt106x/imxrt106x_memorymap.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/chip/imxrt_pinmux.h b/arch/arm/src/imxrt/chip/imxrt_pinmux.h index c92b3d8cb85..ffcdc1f6ab8 100644 --- a/arch/arm/src/imxrt/chip/imxrt_pinmux.h +++ b/arch/arm/src/imxrt/chip/imxrt_pinmux.h @@ -43,10 +43,12 @@ #include -#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) -# include "chip/imxrt105x_pinmux.h" +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include "chip/rt102x/imxrt102x_pinmux.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/rt105x/imxrt105x_pinmux.h" #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) -# include "chip/imxrt106x_pinmux.h" +# include "chip/rt106x/imxrt106x_pinmux.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/chip/imxrt_xbar.h b/arch/arm/src/imxrt/chip/imxrt_xbar.h index 8eb1e2f85f6..47bab85828b 100644 --- a/arch/arm/src/imxrt/chip/imxrt_xbar.h +++ b/arch/arm/src/imxrt/chip/imxrt_xbar.h @@ -45,6 +45,17 @@ #include #include "chip/imxrt_memorymap.h" +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include "chip/rt102x/imxrt102x_xbar.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/rt105x/imxrt105x_xbar.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) +# include "chip/rt106x/imxrt106x_xbar.h" +#else +# error Unrecognized i.MX RT architecture +#endif + + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h new file mode 100644 index 00000000000..0c1c27e64ff --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h @@ -0,0 +1,970 @@ +/***************************************************************************** + * arch/arm/src/imxrt/chip/rt102x/imxrt102x_ccm.h + * + * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. + * Authors: Janne Rosberg + * David Sidrane + * Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_CCM_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_CCM_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/* Register offsets **********************************************************/ + +#define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ + /* 0x0004 Reserved */ +#define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ +#define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ +#define IMXRT_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */ +#define IMXRT_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */ +#define IMXRT_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */ +#define IMXRT_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */ +#define IMXRT_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */ +#define IMXRT_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */ +#define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ +#define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ +#define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ + /* 0x0034 Reserved */ +#define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ +#define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ + /* 0x0040 Reserved */ + /* 0x0044 Reserved */ +#define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ + /* 0x004c Reserved */ + /* 0x0050 Reserved */ +#define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ + +#define IMXRT_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */ +#define IMXRT_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */ +#define IMXRT_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */ +#define IMXRT_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */ +#define IMXRT_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */ +#define IMXRT_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */ +#define IMXRT_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */ +#define IMXRT_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */ +#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ +#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ +#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ + /* 0x0084 Reserved */ +#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */ + +/* Analog */ + +#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET 0x0010 /* Analog USB1 480MHz PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET 0x0030 /* Analog System PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET 0x0040 /* 528MHz System PLL Spread Spectrum Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET 0x0050 /* Numerator of 528MHz System PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET 0x0060 /* Denominator of 528MHz System PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET 0x0070 /* Analog Audio PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET 0x0080 /* Numerator of Audio PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET 0x0090 /* Denominator of Audio PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET 0x00e0 /* Analog ENET PLL Control Register */ +#define IMXRT_CCM_ANALOG_PFD_480_OFFSET 0x00f0 /* 480MHz Clock (PLL3) Phase Fractional Divider Control */ +#define IMXRT_CCM_ANALOG_PFD_528_OFFSET 0x0100 /* 528MHz Clock (PLL2) Phase Fractional Divider Control */ +#define IMXRT_CCM_ANALOG_MISC0_OFFSET 0x0150 /* Miscellaneous Register 0 */ +#define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ +#define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ + +/* Register addresses ********************************************************/ + +#define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) +#define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) +#define IMXRT_CCM_CCSR (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET) +#define IMXRT_CCM_CACRR (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET) +#define IMXRT_CCM_CBCDR (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET) +#define IMXRT_CCM_CBCMR (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET) +#define IMXRT_CCM_CSCMR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET) +#define IMXRT_CCM_CSCMR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET) +#define IMXRT_CCM_CSCDR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET) +#define IMXRT_CCM_CS1CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET) +#define IMXRT_CCM_CS2CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET) +#define IMXRT_CCM_CDCDR (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET) +#define IMXRT_CCM_CSCDR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET) +#define IMXRT_CCM_CSCDR3 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET) +#define IMXRT_CCM_CDHIPR (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET) +#define IMXRT_CCM_CLPCR (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET) +#define IMXRT_CCM_CISR (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET) +#define IMXRT_CCM_CIMR (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET) +#define IMXRT_CCM_CCOSR (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET) +#define IMXRT_CCM_CGPR (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET) +#define IMXRT_CCM_CCGR0 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET) +#define IMXRT_CCM_CCGR1 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET) +#define IMXRT_CCM_CCGR2 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET) +#define IMXRT_CCM_CCGR3 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET) +#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET) +#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET) +#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET) +#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET) + +#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_USB1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_SS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_ENET (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET) +#define IMXRT_CCM_ANALOG_PFD_480 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET) +#define IMXRT_CCM_ANALOG_PFD_528 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET) +#define IMXRT_CCM_ANALOG_MISC0 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET) +#define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) +#define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) + +/* Helper Macros *************************************************************/ + +#define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ + +/* Register bit definitions **************************************************/ + +/* Control Register */ + +#define CCM_CCR_OSCNT_SHIFT (0) /* Bits 0-7: Oscillator ready counter value */ +#define CCM_CCR_OSCNT_MASK (0xff << CCM_CCR_OSCNT_SHIFT) +# define CCM_CCR_OSCNT(n) ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT) + /* Bits 8-11: Reserved */ +#define CCM_CCR_COSC_EN (1 << 12) /* Bit 12: On chip oscillator enable */ + /* Bits 13-20: Reserved */ +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21) /* Bits 21-26: Counter for analog_reg_bypass */ +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT) +# define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) +#define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ + /* Bits 28-31: Reserved */ +/* Status Register */ + +#define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ + /* Bits 1-2: Reserved */ +#define CCM_CSR_CAMP2_READY (3 << 0) /* Bit 3: Status indication of CAMP2 */ + /* Bit 4: Reserved */ +#define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ + /* Bits 6-31: Reserved */ +/* Clock Switcher Register */ + +#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ + +/* Arm Clock Root Register */ + +#define CCM_CACRR_ARM_PODF_SHIFT (0) /* Bits 0-2: Divider for ARM clock root */ +#define CCM_CACRR_ARM_PODF_MASK (0x7 << CCM_CACRR_ARM_PODF_SHIFT) +# define CCM_CACRR_ARM_PODF(n) ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT) + +/* Bus Clock Divider Register */ + + /* Bits 0-5: Reserved */ +#define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3 (1 << 7) /* Bit 7: PLL3 PFD1 will be selected */ +#define CCM_CBCDR_IPG_PODF_SHIFT (8) /* Bits 8-9: Divider for ipg podf */ +#define CCM_CBCDR_IPG_PODF_MASK (0x3 << CCM_CBCDR_IPG_PODF_SHIFT) +# define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT) +#define CCM_CBCDR_AHB_PODF_SHIFT (10) /* Bits 10-12: Divider for AHB PODF */ +#define CCM_CBCDR_AHB_PODF_MASK (0x7 << CCM_CBCDR_AHB_PODF_SHIFT) +# define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT) + /* Bits 13-15: Reserved */ +#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ +#define CCM_CBCDR_SEMC_PODF_MASK (0x7 << CCM_CBCDR_SEMC_PODF_SHIFT) +# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) + /* Bits 19-24: Reserved */ +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCDR_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) +# define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) + + /* Bit 26: Reserved */ +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) +# define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + /* Bits 30-31: Reserved */ + +/* Bus Clock Multiplexer Register */ + + /* Bits 0-3: Reserved */ +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1 ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) + /* Bits 6-11: Reserved */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for Trace clock multiplexer */ +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) + /* Bits 16-17: Reserved */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL3_PFD3 (1) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD3 (2) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL6 (3) + /* Bits 20-25: Reserved */ +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ +#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) +# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) + +/* Serial Clock Multiplexer Register 1 */ + +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) +# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6) /* Bit 6: Selector for the perclk clock multiplexer */ +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) +# define CCM_CSCMR1_PERCLK_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) +# define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0) +# define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK (1) + /* Bits 7-9: Reserved */ +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for sai1 clock multiplexer */ +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for sai2 clock multiplexer */ +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for sai3 clock multiplexer */ +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ +# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2 (0 << 16) /* derive clock from PLL2 PFD2 */ +# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 (1 << 16) /* derive clock from PLL2 PFD0 */ +#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ +# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2 (0 << 17) /* derive clock from PLL2 PFD2 */ +# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0 (1 << 17) /* derive clock from PLL2 PFD0 */ + /* Bits 18-22: Reserved */ +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23) /* Bits 23-25: Divider for flexspi clock root */ +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) +# define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) + /* Bits 26-28: Reserved */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29) /* Bits 29-30: Selector for flexspi clock multiplexer */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) + /* Bit 31: Reserved */ +/* Serial Clock Multiplexer Register 2 */ + +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) +# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for FlexCAN clock multiplexer */ +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60 ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80 ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) + /* Bits 10-18: Reserved */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for flexio2 clock multiplexer */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) + /* Bits 21-31: Reserved */ + +/* Serial Clock Divider Register 1 */ + +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) +# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) +#define CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Bit 6: Selector for the UART clock multiplexer */ +# define CCM_CSCDR1_UART_CLK_SEL_PLL3_80 (0 << 6) /* derive clock from pll3_80m */ +# define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK (1 << 6) /* derive clock from osc_clk */ + /* Bits 7-10: Reserved */ +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) +# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) + /* Bits 14-15: Reserved */ +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) +# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) + /* Bits 19-24: Reserved */ +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25) /* Bits 25-27: Divider for trace clock */ +# define CCM_CSCDR1_TRACE_PODF_MASK (0x3 << CCM_CSCDR1_TRACE_PODF_SHIFT) + /* Bits 27-31: Reserved */ +# define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT) + +/* Clock Divider Register 1 */ + +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai1 clock podf */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) +# define CCM_CS1CDR_SAI1_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai1 clock pred */ +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) +# define CCM_CS1CDR_SAI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for flexio2 clock */ +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) +# define CCM_CS1CDR_FLEXIO2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) + /* Bits 12-15: Reserved */ +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for sai3 clock podf */ +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) +# define CCM_CS1CDR_SAI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for sai3 clock pred */ +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) +# define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for flexio2 clock */ +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) +# define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) + /* Bits 28-31: Reserved */ +/* Clock Divider Register 2 */ + +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai2 clock podf */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) +# define CCM_CS2CDR_SAI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai2 clock pred */ +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) +# define CCM_CS2CDR_SAI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) + +/* D1 Clock Divider Register */ + +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) + +/* Serial Clock Divider Register 2 */ + + /* Bits 0-17: Reserved */ +#define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ +# define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ +# define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for lpi2c clock podf */ +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) +# define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) + /* Bits 25-31: Reserved */ + +/* Divider Handshake In-Process Register */ + +#define CCM_CDHIPR_SEMC_PODF_BUSY (1 << 0) /* Bit 0: Busy indicator for semc_podf */ +#define CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) /* Bit 1: Busy indicator for ahb_podf */ + /* Bit 2: Reserved */ +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) /* Bit 3: Busy indicator for periph2_clk_sel mux control */ + /* Bit 4: Reserved */ +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) /* Bit 5: Busy indicator for periph_clk_sel mux control */ + /* Bits 6-15: Reserved */ +#define CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) /* Bit 16: Busy indicator for arm_podf */ + /* Bits 17-31: Reserved */ + +/* Low Power Control Register */ + +#define CCM_CLPCR_LPM_SHIFT (0) /* Bits 0-1: Setting the low power mode */ +#define CCM_CLPCR_LPM_MASK (0x3 << CCM_CLPCR_LPM_SHIFT) +# define CCM_CLPCR_LPM(n) ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT) +# define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ +# define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ +# define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ + /* Bits 2-4: Reserved */ +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ +#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ +#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ +#define CCM_CLPCR_VSTBY (1 << 8) /* Bit 8: Voltage standby request bit */ +#define CCM_CLPCR_STBY_COUNT_SHIFT (9) /* Bits 9-10: Standby counter definition */ +#define CCM_CLPCR_STBY_COUNT_MASK (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT) +# define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT) +#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: On chip oscillator power down */ + /* Bits 12-18: Reserved */ +#define CCM_CLPCR_BYPASS_LPM_HS1 (1 << 19) /* Bit 19: Bypass low power mode handshake */ + /* Bit 20: Reserved */ +#define CCM_CLPCR_BYPASS_LPM_HS0 (1 << 21) /* Bit 21: Bypass low power mode handshake */ +#define CCM_CLPCR_MASK_CORE0_WFI (1 << 22) /* Bit 22: Mask WFI of core0 for entering low power mode */ + /* Bits 23-25: Reserved */ +#define CCM_CLPCR_MASK_SCU_IDLE (1 << 26) /* Bit 26: Mask SCU IDLE for entering low power mode */ +#define CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) /* Bit 27: Mask L2CC IDLE for entering low power mode */ + /* Bits 28-31: Reserved */ + +/* Interrupt Status Register */ + +#define CCM_CISR_LRF_PLL (1 << 0) /* Bit 0: CCM irq2, lock of all enabled and not bypassed PLLs */ + /* Bits 1-5: Reserved */ +#define CCM_CISR_COSC_READY (1 << 6) /* Bit 6: CCM irq2, on board oscillator ready */ + /* Bits 7-16: Reserved */ +#define CCM_CISR_SEMC_PODF_LOADED (1 << 17) /* Bit 17: CCM irq1, frequency change of semc_podf */ + /* Bit 18: Reserved */ +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: CCM irq1, frequency change of periph2_clk_sel */ +#define CCM_CISR_AHB_PODF_LOADED (1 << 20) /* Bit 20: CCM irq1, frequency change of ahb_podf */ + /* Bit 21: Reserved */ +#define CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: CCM irq1, update of periph_clk_sel */ + /* Bits 23-25: Reserved */ +#define CCM_CISR_ARM_PODF_LOADED (1 << 26) /* Bit 26: CCM irq1, frequency change of arm_podf */ + /* Bits 27-31: Reserved */ + +/* Interrupt Mask Register */ + +#define CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Bit 0: mask interrupt generation due to lrf of PLLs */ + /* Bits 1-5: Reserved */ +#define CCM_CIMR_MASK_COSC_READY (1 << 6) /* Bit 6: mask interrupt generation due to on board oscillator ready */ + /* Bits 7-16: Reserved */ +#define CCM_CIMR_MASK_SEMC_PODF_LOADED (1 << 17) /* Bit 17: mask interrupt generation due to frequency change of semc_podf */ + /* Bit 18: Reserved */ +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: mask interrupt generation due to update of periph2_clk_sel */ +#define CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) /* Bit 20: mask interrupt generation due to frequency change of ahb_podf */ + /* Bit 21: Reserved */ +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: mask interrupt generation due to update of periph_clk_sel */ + /* Bits 23-25: Reserved */ +#define CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) /* Bit 26: mask interrupt generation due to frequency change of arm_podf */ + /* Bits 27-31: Reserved */ + +/* Clock Output Source Register */ + +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT) + +# define CCM_CCOSR_CLKO1_SEL_PLL3_SW_DIV2_CLK ((uint32_t)(0) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PLL2_DIV2_CLK ((uint32_t)(1) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_ENET_PLL_DIV2_CLK ((uint32_t)(2) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_SEMC_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_AHB_CLK ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_IPG_CLK ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PER_CLK ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT) + +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ +#define CCM_CCOSR_CLKO1_DIV_MASK (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT) +# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) +#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ +#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ + /* Bits 9-15: Reserved */ +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_OSC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI1_CLK ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI2_CLK ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI3_CLK ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_TRACE_CLK ((uint32_t)(22) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_CAN_CLK ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_UART_CLK ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT) + +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_DIV_MASK (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT) +# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) +#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ + /* Bits 25-31: Reserved */ + +/* General Purpose Register */ + +#define CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Bit 0: Defines clock division of clock for stby_count */ + /* Bits 1-3: Reserved */ +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) /* Bit 4: allow fuse programing */ + /* Bits 5-13: Reserved */ +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14) /* Bits 14-15: System memory DS control */ +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) +# define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) +#define CCM_CGPR_FPL (1 << 16) /* Bit 16: Fast PLL enable */ +#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) /* Bit 17: Control for the Deep Sleep signal to the ARM Platform memories */ + /* Bits 18-31: Reserved */ + +/* Clock Gating Register 0-6 */ + +#define CCM_CG_OFF (0) /* Clock is off during all modes */ +#define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ +#define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ + +#define CCM_CCGRX_CG_SHIFT(r) ((r) << 1) +#define CCM_CCGRX_CG_MASK(r) (0x3 << CCM_CCGRX_CG_SHIFT(r)) +# define CCM_CCGRX_CG(r,v) ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r)) + +#define CCM_CCGRX_CG0_SHIFT (0) +#define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) +# define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) +#define CCM_CCGRX_CG1_SHIFT (2) +#define CCM_CCGRX_CG1_MASK (0x3 << CCM_CCGRX_CG1_SHIFT) +# define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) +#define CCM_CCGRX_CG2_SHIFT (4) +#define CCM_CCGRX_CG2_MASK (0x3 << CCM_CCGRX_CG2_SHIFT) +# define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) +#define CCM_CCGRX_CG3_SHIFT (6) +#define CCM_CCGRX_CG3_MASK (0x3 << CCM_CCGRX_CG3_SHIFT) +# define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) +#define CCM_CCGRX_CG4_SHIFT (8) +#define CCM_CCGRX_CG4_MASK (0x3 << CCM_CCGRX_CG4_SHIFT) +# define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) +#define CCM_CCGRX_CG5_SHIFT (10) +#define CCM_CCGRX_CG5_MASK (0x3 << CCM_CCGRX_CG5_SHIFT) +# define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) +#define CCM_CCGRX_CG6_SHIFT (12) +#define CCM_CCGRX_CG6_MASK (0x3 << CCM_CCGRX_CG6_SHIFT) +# define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) +#define CCM_CCGRX_CG7_SHIFT (14) +#define CCM_CCGRX_CG7_MASK (0x3 << CCM_CCGRX_CG7_SHIFT) +# define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) +#define CCM_CCGRX_CG8_SHIFT (16) +#define CCM_CCGRX_CG8_MASK (0x3 << CCM_CCGRX_CG8_SHIFT) +# define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) +#define CCM_CCGRX_CG9_SHIFT (18) +#define CCM_CCGRX_CG9_MASK (0x3 << CCM_CCGRX_CG9_SHIFT) +# define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) +#define CCM_CCGRX_CG10_SHIFT (20) +#define CCM_CCGRX_CG10_MASK (0x3 << CCM_CCGRX_CG10_SHIFT) +# define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) +#define CCM_CCGRX_CG11_SHIFT (22) +#define CCM_CCGRX_CG11_MASK (0x3 << CCM_CCGRX_CG11_SHIFT) +# define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) +#define CCM_CCGRX_CG12_SHIFT (24) +#define CCM_CCGRX_CG12_MASK (0x3 << CCM_CCGRX_CG12_SHIFT) +# define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) +#define CCM_CCGRX_CG13_SHIFT (26) +#define CCM_CCGRX_CG13_MASK (0x3 << CCM_CCGRX_CG13_SHIFT) +# define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) +#define CCM_CCGRX_CG14_SHIFT (28) +#define CCM_CCGRX_CG14_MASK (0x3 << CCM_CCGRX_CG14_SHIFT) +# define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) +#define CCM_CCGRX_CG15_SHIFT (30) +#define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) +# define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) + +/* Macros used by imxrt_periphclks.h */ + +#define CCM_CCGR_GPIO2 IMXRT_CCM_CCGR0, 15 +#define CCM_CCGR_LPUART2 IMXRT_CCM_CCGR0, 14 +#define CCM_CCGR_GPT2_SERIAL IMXRT_CCM_CCGR0, 13 +#define CCM_CCGR_GPT2_BUS IMXRT_CCM_CCGR0, 12 +#define CCM_CCGR_TRACE IMXRT_CCM_CCGR0, 11 +#define CCM_CCGR_CAN2_SERIAL IMXRT_CCM_CCGR0, 10 +#define CCM_CCGR_CAN2 IMXRT_CCM_CCGR0, 9 +#define CCM_CCGR_CAN1_SERIAL IMXRT_CCM_CCGR0, 8 +#define CCM_CCGR_CAN1 IMXRT_CCM_CCGR0, 7 +#define CCM_CCGR_LPUART3 IMXRT_CCM_CCGR0, 6 +#define CCM_CCGR_DCP IMXRT_CCM_CCGR0, 5 +# define CCM_CCGR_SIM_M_CLK_R_CLK IMXRT_CCM_CCGR0, 4 + /* 3 : Reserved */ +#define CCM_CCGR_MQS IMXRT_CCM_CCGR0, 2 +#define CCM_CCGR_AIPS_TZ2 IMXRT_CCM_CCGR0, 1 +#define CCM_CCGR_AIPS_TZ1 IMXRT_CCM_CCGR0, 0 + +# define CCM_CCGR_GPIO5 IMXRT_CCM_CCGR1, 15 +#define CCM_CCGR_CSU IMXRT_CCM_CCGR1, 14 +#define CCM_CCGR_GPIO1 IMXRT_CCM_CCGR1, 13 +#define CCM_CCGR_LPUART4 IMXRT_CCM_CCGR1, 12 +#define CCM_CCGR_GPT_SERIAL IMXRT_CCM_CCGR1, 11 +#define CCM_CCGR_GPT_BUS IMXRT_CCM_CCGR1, 10 +#define CCM_CCGR_SEMC_EXSC IMXRT_CCM_CCGR1, 9 +#define CCM_CCGR_ADC1 IMXRT_CCM_CCGR1, 8 + /* 7 : Reserved */ +#define CCM_CCGR_PIT IMXRT_CCM_CCGR1, 6 +#define CCM_CCGR_ENET IMXRT_CCM_CCGR1, 5 +#define CCM_CCGR_ADC2 IMXRT_CCM_CCGR1, 4 +#define CCM_CCGR_LPSPI4 IMXRT_CCM_CCGR1, 3 +#define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 +#define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 +#define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 + + /* 15 : Reserved */ + /* 14 : Reserved */ +#define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 +#define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 +#define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 + /* 10 : Reserved */ + /* 9 : Reserved */ + /* 8 : Reserved */ + /* 7 : Reserved */ +#define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 +#define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 +#define CCM_CCGR_LPI2C2 IMXRT_CCM_CCGR2, 4 +#define CCM_CCGR_LPI2C1 IMXRT_CCM_CCGR2, 3 +#define CCM_CCGR_IOMUXC_SNVS IMXRT_CCM_CCGR2, 2 + /* 1 : Reserved */ +#define CCM_CCGR_OCRAM_EXSC IMXRT_CCM_CCGR2, 0 + +#define CCM_CCGR_IOMUXC_SNVS_GPR IMXRT_CCM_CCGR3, 15 + /* 14 : Reserved */ +#define CCM_CCGR_ACMP4 IMXRT_CCM_CCGR3, 13 +#define CCM_CCGR_ACMP3 IMXRT_CCM_CCGR3, 12 +#define CCM_CCGR_ACMP2 IMXRT_CCM_CCGR3, 11 +#define CCM_CCGR_ACMP1 IMXRT_CCM_CCGR3, 10 +#define CCM_CCGR_FLEXRAM IMXRT_CCM_CCGR3, 9 +#define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 +#define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 + /* 6 : Reserved */ + /* 5 : Reserved */ +#define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 +#define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 +#define CCM_CCGR_SEMC IMXRT_CCM_CCGR3, 2 +#define CCM_CCGR_LPUART5 IMXRT_CCM_CCGR3, 1 + /* 0 : Reserved */ + + /* 15 : Reserved */ + /* 14 : Reserved */ +#define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 +#define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 + /* 11 : Reserved */ + /* 10 : Reserved */ +#define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 +#define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 +#define CCM_CCGR_SIM_EMS IMXRT_CCM_CCGR4, 7 +#define CCM_CCGR_SIM_M IMXRT_CCM_CCGR4, 6 + /* 5 : Reserved */ +#define CCM_CCGR_SIM_M7 IMXRT_CCM_CCGR4, 4 +#define CCM_CCGR_BEE IMXRT_CCM_CCGR4, 3 +#define CCM_CCGR_IOMUXC_GPR IMXRT_CCM_CCGR4, 2 +#define CCM_CCGR_IOMUXC IMXRT_CCM_CCGR4, 1 +#define CCM_CCGR_SIM_M7_R_EN IMXRT_CCM_CCGR4, 0 + +#define CCM_CCGR_SNVS_LP IMXRT_CCM_CCGR5, 15 +#define CCM_CCGR_SNVS_HP IMXRT_CCM_CCGR5, 14 +#define CCM_CCGR_LPUART7 IMXRT_CCM_CCGR5, 13 +#define CCM_CCGR_LPUART1 IMXRT_CCM_CCGR5, 12 +#define CCM_CCGR_SAI3 IMXRT_CCM_CCGR5, 11 +#define CCM_CCGR_SAI2 IMXRT_CCM_CCGR5, 10 +#define CCM_CCGR_SAI1 IMXRT_CCM_CCGR5, 9 + /* 8 : Reserved */ +#define CCM_CCGR_SPDIF IMXRT_CCM_CCGR5, 7 +#define CCM_CCGR_AIPSTZ4 IMXRT_CCM_CCGR5, 6 +#define CCM_CCGR_WDOG2 IMXRT_CCM_CCGR5, 5 +#define CCM_CCGR_KPP IMXRT_CCM_CCGR5, 4 +#define CCM_CCGR_DMA IMXRT_CCM_CCGR5, 3 +#define CCM_CCGR_WDOG3 IMXRT_CCM_CCGR5, 2 +#define CCM_CCGR_FLEXIO1 IMXRT_CCM_CCGR5, 1 +#define CCM_CCGR_ROM IMXRT_CCM_CCGR5, 0 + + /* 15 : Reserved */ +#define CCM_CCGR_TIMER2 IMXRT_CCM_CCGR6, 14 +#define CCM_CCGR_TIMER1 IMXRT_CCM_CCGR6, 13 +#define CCM_CCGR_LPI2C4_SERIAL IMXRT_CCM_CCGR6, 12 +#define CCM_CCGR_ANADIG IMXRT_CCM_CCGR6, 11 +#define CCM_CCGR_SIM_PER IMXRT_CCM_CCGR6, 10 +#define CCM_CCGR_AIPS_TZ3 IMXRT_CCM_CCGR6, 9 + /* 8 : Reserved */ +#define CCM_CCGR_LPUART8 IMXRT_CCM_CCGR6, 7 +#define CCM_CCGR_TRNG IMXRT_CCM_CCGR6, 6 +#define CCM_CCGR_FLEXSPI IMXRT_CCM_CCGR6, 5 + /* 4 : Reserved */ +#define CCM_CCGR_DCDC IMXRT_CCM_CCGR6, 3 +#define CCM_CCGR_USDHC2 IMXRT_CCM_CCGR6, 2 +#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1 +#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0 + +/* Module Enable Override Register */ + + /* Bits 0-4: Reserved */ +#define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ +#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Overide clock enable signal from PIT */ +#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Overide clock enable signal from USDHC */ +#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Overide clock enable signal from TRNG */ + /* Bits 10-27: Reserved */ +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */ +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */ + /* Bit 31: Reserved */ + +/* Analog System PLL (2) Control Register **********************************/ + +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT_20 (0) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT_22 (1) +#define CCM_ANALOG_PLL_SYS_DIV_VAL(n) (((n)==CCM_ANALOG_PLL_SYS_DIV_SELECT_20)?20:22) + /* Bit 1-11: Reserved */ +#define CCM_ANALOG_PLL_SYS_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_SYS_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +#define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-30 Reserved */ +#define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog USB1 480MHz PLL (3) Control Register **********************************/ + /* Bit 0: Reserved */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1) /* Bit 1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK CCM_ANALOG_PLL_USB1_DIV_SELECT(1) +#define CCM_ANALOG_PLL_USB1_DIV_VAL(n) (((n)==CCM_ANALOG_PLL_USB1_DIV_SELECT_20)?20:22) +# define CCM_ANALOG_PLL_USB1_DIV_SELECT_20 (0) +# define CCM_ANALOG_PLL_USB1_DIV_SELECT_22 (1) + /* Bits 2-5 Reserved */ +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ + /* Bits 7-11 Reserved */ +#define CCM_ANALOG_PLL_USB1_POWER (1 << 12) /* Bit 12: Powers up the PLL */ +#define CCM_ANALOG_PLL_USB1_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +#define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-30 Reserved */ +#define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* 528MHz System PLL Spread Spectrum Register */ + +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0) /* Bits 0-14: Frequency change step */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) +# define CCM_ANALOG_PLL_SYS_SS_STEP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE (1 << 15) /* Bit 15: Enable bit */ +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (0) /* Bits 16-31: Frequency change */ +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) +# define CCM_ANALOG_PLL_SYS_SS_STOP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) + +/* Numerator of 528MHz System PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_SYS_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) + /* Bits 30-31: Reserved */ + +/* Denominator of 528MHz System PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_SYS_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ + +/* Analog Audio PLL control Register */ + +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) + /* Bits 7-11: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17-18: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) + /* Bits 21-30: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Numerator of Audio PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) +/* Bits 30-31: Reserved */ + +/* Denominator of Audio PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ +/* Analog ENET PLL Control Register */ + +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) + + /* Bits 2-11: Reserved */ +#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17-20: Reserved */ +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ + +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD0_STABLE (1 << 6) /* Bit 6: */ +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE (1 << 7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD1_STABLE (1 << 14) /* Bit 14: */ +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE (1 << 15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD2_STABLE (1 << 22) /* Bit 22: */ +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE (1 << 23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD3_STABLE (1 << 30) /* Bit 30: */ +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE (1 << 31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ + +/* 528MHz Clock (PLL2) Phase Fractional Divider Control */ + +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD0_STABLE (1 << 6) /* Bit 6: */ +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE (1 << 7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD1_STABLE (1 << 14) /* Bit 14: */ +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE (1 << 15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD2_STABLE (1 << 22) /* Bit 22: */ +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE (1 << 23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD3_STABLE (1 << 30) /* Bit 30: */ +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE (1 << 31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ + +/* Miscellaneous Register 0 */ + +#define CCM_ANALOG_MISC0_REFTOP_PWD (1 << 0) /* Bit 0: Control bit to power-down the analog bandgap reference circuitry */ + /* Bits 1-2: Reserved */ +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF (1 << 2) /* Bit 3: Control bit to disable the self-bias circuit in the analog bandgap */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4) /* Bits 4-6: VBG (PMU) */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x7 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) +# define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP (1 << 7) /* Bit 7: Status bit that signals the analog bandgap voltage is up and stable */ + /* Bits 8-9: Reserved */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10) /* Bits 10-11: Configure the analog behavior in stop mode */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) +# define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS (1 << 12) /* Bit 12: This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */ +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13) /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */ +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT) +# define CCM_ANALOG_MISC0_OSC_I(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT) +#define CCM_ANALOG_MISC0_OSC_XTALOK (1 << 15) /* Bit 15: bit that signals 24-MHz crystal oscillator is stable */ +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN (1 << 16) /* Bit 16: enables the detector that signals 24MHz crystal oscillator is stable */ + /* Bits 17-24: Reserved */ +#define CCM_ANALOG_MISC0_CLKGATE_CTRL (1 << 25) /* Bit 25: This bit allows disabling the clock gate */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26) /* Bits 26-28: delay powering up the XTAL 24MHz */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) +# define CCM_ANALOG_MISC0_CLKGATE_DELAY(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE (1 << 29) /* Bit 29: which chip source is being used for the rtc clock */ +#define CCM_ANALOG_MISC0_XTAL_24M_PWD (1 << 30) /* Bit 30: power down the 24M crystal oscillator if set true */ + /* Bit 31: Reserved */ + +/* Miscellaneous Register 1 */ + + /* Bits 0-15: Reserved */ +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ + /* Bits 18-26: Reserved */ +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC (1 << 27) /* Bit 27: temperature sensor panic interrupt */ +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW (1 << 28) /* Bit 28: temperature sensor low interrupt */ +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH (1 << 29) /* Bit 29: temperature sensor high interrupt */ +#define CCM_ANALOG_MISC1_IRQ_ANA_BO (1 << 30) /* Bit 30: analog regulator brownout interrupt */ +#define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ + +/* Miscellaneous Register 2 */ + /* Bit 0-4: Reserved */ +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ +#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ + /* Bit 12: Reserved */ +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ + +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ + /* Bit 20: Reserved */ +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) + +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) +# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h new file mode 100644 index 00000000000..d83fa2bca63 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h @@ -0,0 +1,143 @@ +/***************************************************************************** + * arch/arm/src/imxrt/chip/rt102x/imxrt102x_dmamux.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +/***************************************************************************** + * Preprocessor Definitions + *****************************************************************************/ + +/* Peripheral DMA request channels */ + +#define IMXRT_DMACHAN_FLEXIO1_01 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */ +#define IMXRT_DMACHAN_FLEXIO1_45 1 /* FlexIO1 DMA 4/5, Async DMA 4/5 */ +#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */ + +#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */ +#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */ +#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */ +#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */ +#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */ +#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */ +#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */ +#define IMXRT_DMACHAN_ACMP3 26 /* ACMP3 DMA */ +#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */ +#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */ +#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */ +#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */ +#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */ +#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */ +#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */ +#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */ +#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */ +#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */ +#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */ +#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */ +#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */ +#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */ +#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */ +#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */ +#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */ +#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */ +#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */ +#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */ +#define IMXRT_DMACHAN_FLEXIO1_23 64 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */ +#define IMXRT_DMACHAN_FLEXIO1_67 65 /* FlexIO1 DMA 6 / Async DMA 6 / DMA 7 / Async DMA 7 */ +#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */ +#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */ +#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */ +#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */ +#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */ +#define IMXRT_DMACHAN_ACMP2 89 /* ACMP2 DMA */ +#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */ +#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */ +#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */ +#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */ +#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */ +#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */ +#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */ +#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */ +#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */ +#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */ +#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */ +#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */ +#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */ +#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */ +#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */ +#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */ +#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */ +#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */ +#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */ +#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */ +#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */ + +#define IMXRT_DMA_NCHANNELS 128 /* Includes reserved channels */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_DMAMUX_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_gpio.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_gpio.h new file mode 100644 index 00000000000..fe288177cb6 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_gpio.h @@ -0,0 +1,116 @@ +/***************************************************************************** + * arch/arm/src/imxrt/chip/rt102x/imxrt105x_gpio.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/* Register offsets **********************************************************/ + +#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ +#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ +#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */ +#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */ +#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */ +#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */ +#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */ +#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */ +#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */ +#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ +#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ + +/* Register addresses ********************************************************/ + +#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_GPIO_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h new file mode 100644 index 00000000000..4d5f325b081 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h @@ -0,0 +1,1606 @@ +/**************************************************************************** + * arch/arm/src/imxrt/chip/rt102x/imxrt102x_iomuxc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * David Sidrane + * Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_IOMUXC_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_IOMUXC_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/* Register offsets **********************************************************/ + +#define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR2_OFFSET 0x0008 /* GPR2 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR3_OFFSET 0x000c /* GPR3 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR4_OFFSET 0x0010 /* GPR4 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR5_OFFSET 0x0014 /* GPR5 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR6_OFFSET 0x0018 /* GPR6 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR7_OFFSET 0x001c /* GPR7 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR8_OFFSET 0x0020 /* GPR8 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR9_OFFSET 0x0024 /* GPR9 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR10_OFFSET 0x0028 /* GPR10 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR11_OFFSET 0x002c /* GPR11 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR12_OFFSET 0x0030 /* GPR12 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR13_OFFSET 0x0034 /* GPR13 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR14_OFFSET 0x0038 /* GPR14 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR15_OFFSET 0x003c /* GPR15 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR16_OFFSET 0x0040 /* GPR16 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR17_OFFSET 0x0044 /* GPR17 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR18_OFFSET 0x0048 /* GPR18 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR19_OFFSET 0x004c /* GPR19 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR20_OFFSET 0x0050 /* GPR20 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR21_OFFSET 0x0054 /* GPR21 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR22_OFFSET 0x0058 /* GPR22 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR23_OFFSET 0x005c /* GPR23 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ + +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET 0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET 0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET 0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET 0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ + +#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET 0x0000 /* SNVC GPR0 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET 0x0004 /* SNVC GPR1 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET 0x0008 /* SNVC GPR2 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ + +/* Pad Mux Register Indices (used by software for table lookups) */ + +#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 +#define IMXRT_PADMUX_GPIO_EMC_01_INDEX 1 +#define IMXRT_PADMUX_GPIO_EMC_02_INDEX 2 +#define IMXRT_PADMUX_GPIO_EMC_03_INDEX 3 +#define IMXRT_PADMUX_GPIO_EMC_04_INDEX 4 +#define IMXRT_PADMUX_GPIO_EMC_05_INDEX 5 +#define IMXRT_PADMUX_GPIO_EMC_06_INDEX 6 +#define IMXRT_PADMUX_GPIO_EMC_07_INDEX 7 +#define IMXRT_PADMUX_GPIO_EMC_08_INDEX 8 +#define IMXRT_PADMUX_GPIO_EMC_09_INDEX 9 +#define IMXRT_PADMUX_GPIO_EMC_10_INDEX 10 +#define IMXRT_PADMUX_GPIO_EMC_11_INDEX 11 +#define IMXRT_PADMUX_GPIO_EMC_12_INDEX 12 +#define IMXRT_PADMUX_GPIO_EMC_13_INDEX 13 +#define IMXRT_PADMUX_GPIO_EMC_14_INDEX 14 +#define IMXRT_PADMUX_GPIO_EMC_15_INDEX 15 +#define IMXRT_PADMUX_GPIO_EMC_16_INDEX 16 +#define IMXRT_PADMUX_GPIO_EMC_17_INDEX 17 +#define IMXRT_PADMUX_GPIO_EMC_18_INDEX 18 +#define IMXRT_PADMUX_GPIO_EMC_19_INDEX 19 +#define IMXRT_PADMUX_GPIO_EMC_20_INDEX 20 +#define IMXRT_PADMUX_GPIO_EMC_21_INDEX 21 +#define IMXRT_PADMUX_GPIO_EMC_22_INDEX 22 +#define IMXRT_PADMUX_GPIO_EMC_23_INDEX 23 +#define IMXRT_PADMUX_GPIO_EMC_24_INDEX 24 +#define IMXRT_PADMUX_GPIO_EMC_25_INDEX 25 +#define IMXRT_PADMUX_GPIO_EMC_26_INDEX 26 +#define IMXRT_PADMUX_GPIO_EMC_27_INDEX 27 +#define IMXRT_PADMUX_GPIO_EMC_28_INDEX 28 +#define IMXRT_PADMUX_GPIO_EMC_29_INDEX 29 +#define IMXRT_PADMUX_GPIO_EMC_30_INDEX 30 +#define IMXRT_PADMUX_GPIO_EMC_31_INDEX 31 +#define IMXRT_PADMUX_GPIO_EMC_32_INDEX 32 +#define IMXRT_PADMUX_GPIO_EMC_33_INDEX 33 +#define IMXRT_PADMUX_GPIO_EMC_34_INDEX 34 +#define IMXRT_PADMUX_GPIO_EMC_35_INDEX 35 +#define IMXRT_PADMUX_GPIO_EMC_36_INDEX 36 +#define IMXRT_PADMUX_GPIO_EMC_37_INDEX 37 +#define IMXRT_PADMUX_GPIO_EMC_38_INDEX 38 +#define IMXRT_PADMUX_GPIO_EMC_39_INDEX 39 +#define IMXRT_PADMUX_GPIO_EMC_40_INDEX 40 +#define IMXRT_PADMUX_GPIO_EMC_41_INDEX 41 +#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX 42 +#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX 43 +#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX 44 +#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX 45 +#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX 46 +#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX 47 +#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX 48 +#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX 49 +#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX 50 +#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX 51 +#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX 52 +#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX 53 +#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX 54 +#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX 55 +#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX 56 +#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX 57 +#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX 58 +#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX 59 +#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX 60 +#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX 61 +#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX 62 +#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX 63 +#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX 64 +#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX 65 +#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX 66 +#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX 67 +#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX 68 +#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX 69 +#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX 70 +#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX 71 +#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX 72 +#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX 73 +#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX 74 +#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX 75 +#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX 76 +#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX 77 +#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX 78 +#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX 79 +#define IMXRT_PADMUX_GPIO_SD_B0_06_INDEX 80 +#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX 81 +#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX 82 +#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX 83 +#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX 84 +#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX 85 +#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX 86 +#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX 87 +#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX 88 +#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX 89 +#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX 90 +#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 91 +#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 92 +#define IMXRT_PADMUX_WAKEUP_INDEX 93 +#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX 94 +#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX 95 + +#define IMXRT_PADMUX_NREGISTERS 96 + +/* Pad Mux Register Offsets */ + +#define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) +#define IMXRT_PADMUX_OFFSET_SNVS(n) ((unsigned int)(n) << 2) + +#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 +#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 +#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET 0x001c +#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET 0x0020 +#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET 0x0024 +#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET 0x0028 +#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET 0x002c +#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET 0x0030 +#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET 0x0034 +#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET 0x0038 +#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET 0x003c +#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET 0x0040 +#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET 0x0044 +#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET 0x0048 +#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET 0x004c +#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET 0x0050 +#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET 0x0054 +#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET 0x0058 +#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET 0x005c +#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET 0x0060 +#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET 0x0064 +#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET 0x0068 +#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET 0x006c +#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET 0x0070 +#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET 0x0074 +#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET 0x0078 +#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET 0x007c +#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET 0x0080 +#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET 0x0084 +#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET 0x0088 +#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET 0x008c +#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET 0x0090 +#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET 0x0094 +#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET 0x0098 +#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET 0x009c +#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET 0x00a0 +#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET 0x00a4 +#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET 0x00a8 +#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET 0x00ac +#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET 0x00b0 +#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET 0x00b4 +#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET 0x00b8 +#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET 0x00bc +#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET 0x00c0 +#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET 0x00c4 +#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET 0x00c8 +#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET 0x00cc +#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET 0x00d0 +#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET 0x00d4 +#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET 0x00d8 +#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET 0x00dc +#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET 0x00e0 +#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET 0x00e4 +#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET 0x00e8 +#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET 0x00ec +#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET 0x00f0 +#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET 0x00f4 +#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET 0x00f8 +#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET 0x00fc +#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET 0x0100 +#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET 0x0104 +#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET 0x0108 +#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET 0x010c +#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET 0x0110 +#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET 0x0114 +#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET 0x0118 +#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET 0x011c +#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET 0x0120 +#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET 0x0124 +#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET 0x0128 +#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET 0x012c +#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET 0x0130 +#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET 0x0134 +#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET 0x0138 +#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET 0x013c +#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET 0x0140 +#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET 0x0144 +#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET 0x0148 +#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET 0x014c +#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET 0x0150 +#define IMXRT_PADMUX_GPIO_SD_B0_06_OFFSET 0x0154 +#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET 0x0158 +#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET 0x015c +#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET 0x0160 +#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET 0x0164 +#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET 0x0168 +#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET 0x016c +#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET 0x0170 +#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET 0x0174 +#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET 0x0178 +#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET 0x017c +#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET 0x0180 +#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET 0x0184 + +/* Pad Control Registers + * Pad Control Register Indices (used by software for table lookups) + */ + +#define IMXRT_PADCTL_GPIO_EMC_00_INDEX 0 +#define IMXRT_PADCTL_GPIO_EMC_01_INDEX 1 +#define IMXRT_PADCTL_GPIO_EMC_02_INDEX 2 +#define IMXRT_PADCTL_GPIO_EMC_03_INDEX 3 +#define IMXRT_PADCTL_GPIO_EMC_04_INDEX 4 +#define IMXRT_PADCTL_GPIO_EMC_05_INDEX 5 +#define IMXRT_PADCTL_GPIO_EMC_06_INDEX 6 +#define IMXRT_PADCTL_GPIO_EMC_07_INDEX 7 +#define IMXRT_PADCTL_GPIO_EMC_08_INDEX 8 +#define IMXRT_PADCTL_GPIO_EMC_09_INDEX 9 +#define IMXRT_PADCTL_GPIO_EMC_10_INDEX 10 +#define IMXRT_PADCTL_GPIO_EMC_11_INDEX 11 +#define IMXRT_PADCTL_GPIO_EMC_12_INDEX 12 +#define IMXRT_PADCTL_GPIO_EMC_13_INDEX 13 +#define IMXRT_PADCTL_GPIO_EMC_14_INDEX 14 +#define IMXRT_PADCTL_GPIO_EMC_15_INDEX 15 +#define IMXRT_PADCTL_GPIO_EMC_16_INDEX 16 +#define IMXRT_PADCTL_GPIO_EMC_17_INDEX 17 +#define IMXRT_PADCTL_GPIO_EMC_18_INDEX 18 +#define IMXRT_PADCTL_GPIO_EMC_19_INDEX 19 +#define IMXRT_PADCTL_GPIO_EMC_20_INDEX 20 +#define IMXRT_PADCTL_GPIO_EMC_21_INDEX 21 +#define IMXRT_PADCTL_GPIO_EMC_22_INDEX 22 +#define IMXRT_PADCTL_GPIO_EMC_23_INDEX 23 +#define IMXRT_PADCTL_GPIO_EMC_24_INDEX 24 +#define IMXRT_PADCTL_GPIO_EMC_25_INDEX 25 +#define IMXRT_PADCTL_GPIO_EMC_26_INDEX 26 +#define IMXRT_PADCTL_GPIO_EMC_27_INDEX 27 +#define IMXRT_PADCTL_GPIO_EMC_28_INDEX 28 +#define IMXRT_PADCTL_GPIO_EMC_29_INDEX 29 +#define IMXRT_PADCTL_GPIO_EMC_30_INDEX 30 +#define IMXRT_PADCTL_GPIO_EMC_31_INDEX 31 +#define IMXRT_PADCTL_GPIO_EMC_32_INDEX 32 +#define IMXRT_PADCTL_GPIO_EMC_33_INDEX 33 +#define IMXRT_PADCTL_GPIO_EMC_34_INDEX 34 +#define IMXRT_PADCTL_GPIO_EMC_35_INDEX 35 +#define IMXRT_PADCTL_GPIO_EMC_36_INDEX 36 +#define IMXRT_PADCTL_GPIO_EMC_37_INDEX 37 +#define IMXRT_PADCTL_GPIO_EMC_38_INDEX 38 +#define IMXRT_PADCTL_GPIO_EMC_39_INDEX 39 +#define IMXRT_PADCTL_GPIO_EMC_40_INDEX 40 +#define IMXRT_PADCTL_GPIO_EMC_41_INDEX 41 +#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX 42 +#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX 43 +#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX 44 +#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX 45 +#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX 46 +#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX 47 +#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX 48 +#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX 49 +#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX 50 +#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX 51 +#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX 52 +#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX 53 +#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX 54 +#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX 55 +#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX 56 +#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX 57 +#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX 58 +#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX 59 +#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX 60 +#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX 61 +#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX 62 +#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX 63 +#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX 64 +#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX 65 +#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX 66 +#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX 67 +#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX 68 +#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX 69 +#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX 70 +#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX 71 +#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX 72 +#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX 73 +#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX 74 +#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX 75 +#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX 76 +#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX 77 +#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX 78 +#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX 79 +#define IMXRT_PADCTL_GPIO_SD_B0_06_INDEX 80 +#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX 81 +#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX 82 +#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX 83 +#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX 84 +#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX 85 +#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX 86 +#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX 87 +#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX 88 +#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX 89 +#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX 90 +#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 91 +#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 92 + +#define IMXRT_PADCTL_WAKEUP_INDEX 93 +#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX 94 +#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX 95 + +#define IMXRT_PADCTL_NREGISTERS 96 + +/* Pad Control Register Offsets */ + +#define IMXRT_PADCTL_OFFSET(n) (0x0188 + ((unsigned int)(n) << 2)) +#define IMXRT_PADCTL_OFFSET_SNVS(n) (0x18 + ((unsigned int)(n-IMXRT_PADCTL_WAKEUP_INDEX) << 2)) + +#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0188 +#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x018c +#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET 0x0190 +#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET 0x0194 +#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET 0x0198 +#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET 0x019c +#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET 0x01a0 +#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET 0x01a4 +#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET 0x01a8 +#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET 0x01ac +#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET 0x01b0 +#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET 0x01b4 +#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET 0x01b8 +#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET 0x01bc +#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET 0x01c0 +#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET 0x01c4 +#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET 0x01c8 +#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET 0x01cc +#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET 0x01d0 +#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET 0x01d4 +#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET 0x01d8 +#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET 0x01dc +#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET 0x01e0 +#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET 0x01e4 +#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET 0x01e8 +#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET 0x01ec +#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET 0x01f0 +#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET 0x01f4 +#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET 0x01f8 +#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET 0x01fc +#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET 0x0200 +#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET 0x0204 +#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET 0x0208 +#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET 0x020c +#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET 0x0210 +#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET 0x0214 +#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET 0x0218 +#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET 0x021c +#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET 0x0220 +#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET 0x0224 +#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET 0x0228 +#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET 0x022c +#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET 0x0230 +#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET 0x0234 +#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET 0x0238 +#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET 0x023c +#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET 0x0240 +#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET 0x0244 +#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET 0x0248 +#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET 0x024c +#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET 0x0250 +#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET 0x0254 +#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET 0x0258 +#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET 0x025c +#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET 0x0260 +#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET 0x0264 +#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET 0x0268 +#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET 0x026c +#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET 0x0270 +#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET 0x0274 +#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET 0x0278 +#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET 0x027c +#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET 0x0280 +#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET 0x0284 +#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET 0x0288 +#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET 0x028c +#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET 0x0290 +#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET 0x0294 +#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET 0x0298 +#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET 0x029c +#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET 0x02a0 +#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET 0x02a4 +#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET 0x02a8 +#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET 0x02ac +#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET 0x02b0 +#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET 0x02b4 +#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET 0x02b8 +#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET 0x02bc +#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET 0x02c0 +#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET 0x02c4 +#define IMXRT_PADCTL_GPIO_SD_B0_06_OFFSET 0x02c8 +#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET 0x02cc +#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET 0x02d0 +#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET 0x02d4 +#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET 0x02d8 +#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET 0x02dc +#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET 0x02e0 +#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET 0x02e4 +#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET 0x02e8 +#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET 0x02ec +#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET 0x02f0 +#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET 0x02f4 +#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET 0x02f8 + +/* Select Input Daisy Register Offsets */ + +#define IMXRT_INPUT_INDEX2OFFSET(n) (0x02fc + ((unsigned int)(n) << 2)) +#define IMXRT_INPUT_OFFSET2INDEX(o) (((unsigned int)(o) - 0x02fc) >> 2) + +#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET 0x02fc +#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET 0x0300 +#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET 0x0304 +#define IMXRT_INPUT_ENET_MDIO_OFFSET 0x0308 +#define IMXRT_INPUT_ENET_RXDATA0_OFFSET 0x030c +#define IMXRT_INPUT_ENET_RXDATA1_OFFSET 0x0310 +#define IMXRT_INPUT_ENET_RXEN_OFFSET 0x0314 +#define IMXRT_INPUT_ENET_RXERR_OFFSET 0x0318 +#define IMXRT_INPUT_ENET_TXCLK_OFFSET 0x031c +#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET 0x0320 +#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET 0x0324 +#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET 0x0328 +#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET 0x032c +#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET 0x0330 +#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET 0x0334 +#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET 0x0338 +#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET 0x033c +#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET 0x0340 +#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET 0x0344 +#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET 0x0348 +#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET 0x034c +#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET 0x0350 +#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET 0x0354 +#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET 0x0358 +#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET 0x035c +#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET 0x0360 +#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET 0x0364 +#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET 0x0368 +#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET 0x036c +#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET 0x0370 +#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET 0x0374 +#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET 0x0378 +#define IMXRT_INPUT_LPI2C1_SCL_OFFSET 0x037c +#define IMXRT_INPUT_LPI2C1_SDA_OFFSET 0x0380 +#define IMXRT_INPUT_LPI2C2_SCL_OFFSET 0x0384 +#define IMXRT_INPUT_LPI2C2_SDA_OFFSET 0x0388 +#define IMXRT_INPUT_LPI2C3_SCL_OFFSET 0x038c +#define IMXRT_INPUT_LPI2C3_SDA_OFFSET 0x0390 +#define IMXRT_INPUT_LPI2C4_SCL_OFFSET 0x0394 +#define IMXRT_INPUT_LPI2C4_SDA_OFFSET 0x0398 +#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET 0x039c +#define IMXRT_INPUT_LPSPI1_SCK_OFFSET 0x03a0 +#define IMXRT_INPUT_LPSPI1_SDI_OFFSET 0x03a4 +#define IMXRT_INPUT_LPSPI1_SDO_OFFSET 0x03a8 +#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET 0x03ac +#define IMXRT_INPUT_LPSPI2_SCK_OFFSET 0x03b0 +#define IMXRT_INPUT_LPSPI2_SDI_OFFSET 0x03b4 +#define IMXRT_INPUT_LPSPI2_SDO_OFFSET 0x03b8 +#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET 0x03bc +#define IMXRT_INPUT_LPSPI4_SCK_OFFSET 0x03c0 +#define IMXRT_INPUT_LPSPI4_SDI_OFFSET 0x03c4 +#define IMXRT_INPUT_LPSPI4_SDO_OFFSET 0x03c8 +#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET 0x03cc +#define IMXRT_INPUT_LPUART2_RX_OFFSET 0x03d0 +#define IMXRT_INPUT_LPUART2_TX_OFFSET 0x03d4 +#define IMXRT_INPUT_LPUART3_RX_OFFSET 0x03d8 +#define IMXRT_INPUT_LPUART3_TX_OFFSET 0x03dc +#define IMXRT_INPUT_LPUART4_CTS_B_OFFSET 0x03e0 +#define IMXRT_INPUT_LPUART4_RX_OFFSET 0x03e4 +#define IMXRT_INPUT_LPUART4_TX_OFFSET 0x03e8 +#define IMXRT_INPUT_LPUART5_RX_OFFSET 0x03ec +#define IMXRT_INPUT_LPUART5_TX_OFFSET 0x03f0 +#define IMXRT_INPUT_LPUART6_RX_OFFSET 0x03f4 +#define IMXRT_INPUT_LPUART6_TX_OFFSET 0x03f8 +#define IMXRT_INPUT_LPUART7_RX_OFFSET 0x03fc +#define IMXRT_INPUT_LPUART7_TX_OFFSET 0x0400 +#define IMXRT_INPUT_LPUART8_RX_OFFSET 0x0404 +#define IMXRT_INPUT_LPUART8_TX_OFFSET 0x0408 +#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET 0x040c +#define IMXRT_INPUT_QTIMER1_TIMER0_OFFSET 0x0410 +#define IMXRT_INPUT_QTIMER1_TIMER1_OFFSET 0x0414 +#define IMXRT_INPUT_QTIMER1_TIMER2_OFFSET 0x0418 +#define IMXRT_INPUT_QTIMER1_TIMER3_OFFSET 0x041c +#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET 0x0420 +#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET 0x0424 +#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET 0x0428 +#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET 0x042c +#define IMXRT_INPUT_SAI1_MCLK_OFFSET 0x0430 +#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET 0x0434 +#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET 0x0438 +#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET 0x043c +#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET 0x0440 +#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET 0x0444 +#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET 0x0448 +#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET 0x044c +#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET 0x0450 +#define IMXRT_INPUT_SAI2_MCLK_OFFSET 0x0454 +#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET 0x0458 +#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET 0x045c +#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET 0x0460 +#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET 0x0464 +#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET 0x0468 +#define IMXRT_INPUT_SAI3_MCLK_OFFSET 0x046c +#define IMXRT_INPUT_SAI3_RX_BCLK_OFFSET 0x0470 +#define IMXRT_INPUT_SAI3_RX_DATA0_OFFSET 0x0474 +#define IMXRT_INPUT_SAI3_RX_SYNC_OFFSET 0x0478 +#define IMXRT_INPUT_SAI3_TX_BCLK_OFFSET 0x047c +#define IMXRT_INPUT_SAI3_TX_SYNC_OFFSET 0x0480 +#define IMXRT_INPUT_SEMC_READY_OFFSET 0x0484 +#define IMXRT_INPUT_SPDIF_IN_OFFSET 0x0488 +#define IMXRT_INPUT_USB_OTG1_OC_OFFSET 0x048c +#define IMXRT_INPUT_USDHC1_CD_B_OFFSET 0x0490 +#define IMXRT_INPUT_USDHC1_WP_OFFSET 0x0494 +#define IMXRT_INPUT_USDHC2_CD_B_OFFSET 0x0498 +#define IMXRT_INPUT_USDHC2_CMD_OFFSET 0x049c +#define IMXRT_INPUT_XBAR1_IN14_OFFSET 0x04a0 +#define IMXRT_INPUT_XBAR1_IN15_OFFSET 0x04a4 +#define IMXRT_INPUT_XBAR1_IN16_OFFSET 0x04a8 +#define IMXRT_INPUT_XBAR1_IN17_OFFSET 0x04ac +#define IMXRT_INPUT_XBAR1_IN10_OFFSET 0x04b0 +#define IMXRT_INPUT_XBAR1_IN12_OFFSET 0x04b4 +#define IMXRT_INPUT_XBAR1_IN13_OFFSET 0x04b8 +#define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x04bc +#define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x04c0 + +/* Register addresses ********************************************************/ + +#define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR2 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR3 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR4 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR5 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR6 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR7 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR8 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR9 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR10 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR11 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR12 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR13 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR14 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR15 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR16 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR17 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR18 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR19 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR20 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR21 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR22 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR23 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) + +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET) + +#define IMXRT_IOMUXC_SNVS_GPR_GPR0 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR1 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR2 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR3 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET) + +/* Pad Mux Registers */ + +#define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) +#define IMXRT_PADMUX_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n)) + +#define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET) + +/* Pad Control Registers */ + +#define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) +#define IMXRT_PADCTL_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n)) + +#define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET) + +/* Select Input Registers */ + +#define IMXRT_INPUT_ANATOP_USB_OTG1_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET) +#define IMXRT_INPUT_CCM_PMIC_READY (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET) +#define IMXRT_INPUT_ENET_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET) +#define IMXRT_INPUT_ENET_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET) +#define IMXRT_INPUT_ENET0_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET) +#define IMXRT_INPUT_ENET1_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET) +#define IMXRT_INPUT_ENET_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET) +#define IMXRT_INPUT_ENET_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET) +#define IMXRT_INPUT_ENET_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET) +#define IMXRT_INPUT_FLEXCAN1_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET) +#define IMXRT_INPUT_FLEXCAN2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET) +#define IMXRT_INPUT_LPI2C1_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C1_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C2_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C2_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C3_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C3_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C4_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C4_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET) +#define IMXRT_INPUT_LPSPI1_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI1_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI1_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI1_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI2_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI2_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI2_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI2_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI4_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI4_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI4_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI4_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET) +#define IMXRT_INPUT_LPUART2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET) +#define IMXRT_INPUT_LPUART2_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET) +#define IMXRT_INPUT_LPUART3_CTS_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET) +#define IMXRT_INPUT_LPUART3_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET) +#define IMXRT_INPUT_LPUART3_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET) +#define IMXRT_INPUT_LPUART4_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET) +#define IMXRT_INPUT_LPUART4_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET) +#define IMXRT_INPUT_LPUART5_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET) +#define IMXRT_INPUT_LPUART5_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET) +#define IMXRT_INPUT_LPUART6_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET) +#define IMXRT_INPUT_LPUART6_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET) +#define IMXRT_INPUT_LPUART7_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET) +#define IMXRT_INPUT_LPUART7_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET) +#define IMXRT_INPUT_LPUART8_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET) +#define IMXRT_INPUT_LPUART8_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET) +#define IMXRT_INPUT_NMI_GLUE_NMI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET) +#define IMXRT_INPUT_QTIMER1_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER0_OFFSET) +#define IMXRT_INPUT_QTIMER1_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER1_OFFSET) +#define IMXRT_INPUT_QTIMER1_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER2_OFFSET) +#define IMXRT_INPUT_QTIMER1_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER3_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET) +#define IMXRT_INPUT_SAI1_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET) +#define IMXRT_INPUT_SAI1_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET) +#define IMXRT_INPUT_SAI1_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI1_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI1_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI2_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET) +#define IMXRT_INPUT_SAI2_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI2_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET) +#define IMXRT_INPUT_SAI2_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI2_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI2_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET) +#define IMXRT_INPUT_SPDIF_IN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET) +#define IMXRT_INPUT_USB_OTG1_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET) +#define IMXRT_INPUT_USDHC1_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET) +#define IMXRT_INPUT_USDHC1_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET) +#define IMXRT_INPUT_USDHC2_CLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET) +#define IMXRT_INPUT_USDHC2_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET) +#define IMXRT_INPUT_XBAR1_IN14 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET) +#define IMXRT_INPUT_XBAR1_IN15 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET) +#define IMXRT_INPUT_XBAR1_IN16 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET) +#define IMXRT_INPUT_XBAR1_IN17 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET) +#define IMXRT_INPUT_XBAR1_IN10 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN10_OFFSET) +#define IMXRT_INPUT_XBAR1_IN12 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN12_OFFSET) +#define IMXRT_INPUT_XBAR1_IN13 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN13_OFFSET) +#define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) +#define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) + +/* Register bit definitions **************************************************/ + +/* General Purpose Register 0 (GPR0) - Reserved */ + +/* General Purpose Register 1 (GPR1) */ + +#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0) +#define GPR_GPR1_SAI1_MCLK1_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3) +#define GPR_GPR1_SAI1_MCLK2_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6) +#define GPR_GPR1_SAI1_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8) +#define GPR_GPR1_SAI2_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10) +#define GPR_GPR1_SAI3_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +#define GPR_GPR1_GINT (1 << 12) +#define GPR_GPR1_ENET1_CLK_SEL (1 << 13) +#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) +#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) +#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) +#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) +#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) +#define GPR_GPR1_SAI2_MCLK_DIR_OUT (1 << 20) +#define GPR_GPR1_SAI3_MCLK_DIR_IN (0 << 21) +#define GPR_GPR1_SAI3_MCLK_DIR_OUT (1 << 21) +#define GPR_GPR1_EXC_MON_OKAY (0 << 22) +#define GPR_GPR1_EXC_MON_SLVERR (1 << 22) +#define GPR_GPR1_ENET_IMG_CLS_S_EN (1 << 23) +#define GPR_GPR1_CM7_FORCE_HCLK_EN (1 << 31) + +/* General Purpose Register 2 (GPR2) */ + +#define GPR_GPR2_L2_MEM_POWERSAVE_EN (1 << 12) +#define GPR_GPR2_RAM_AUTO_CLK_GATING_EN (1 << 13) +#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) +#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) +#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) +# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) +#define GPR_GPR2_MQS_SW_RST_EN (1 << 24) +#define GPR_GPR2_MQS_EN (1 << 25) +#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) +#define GPR_GPR2_MQS_OVERSAMPLE64 (1 << 26) +#define GPR_GPR2_QTIM1_TMR_RESET (1 << 28) +#define GPR_GPR2_QTIM2_TMR_RESET (1 << 29) + +/* General Purpose Register 3 (GPR3) */ + +#define GPR_GPR3_OCRAM_CTL_SHIFT (0) +#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_CTL_SHIFT) +#define GPR_GPR3_DCP_KEY_SEL_128 (0 << 4) +#define GPR_GPR3_DCP_KEY_SEL_256 (1 << 4) +#define GPR_GPR3_OCRAM_STATUS_SHIFT (16) +#define GPR_GPR3_OCRAM_STATUS_MASK (15 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_STATUS_SHIFT) + +/* General Purpose Register 4 (GPR4) */ + +#define GPR_GRP4_EDMA_STOP_REQ (1 << 0) +#define GPR_GPR4_CAN1_STOP_REQ (1 << 1) +#define GPR_GPR4_CAN2_STOP_REQ (1 << 2) +#define GPR_GPR4_TRNG_STOP_REQ (1 << 3) +#define GPR_GPR4_ENET_STOP_REQ (1 << 4) +#define GPR_GPR4_SAI1_STOP_REQ (1 << 5) +#define GPR_GPR4_SAI2_STOP_REQ (1 << 6) +#define GPR_GPR4_SAI3_STOP_REQ (1 << 7) +#define GPR_GPR4_SEMC_STOP_REQ (1 << 9) +#define GPR_GPR4_PIT_STOP_REQ (1 << 10) +#define GPR_GPR4_FLEXSPI_STOP_REQ (1 << 11) +#define GPR_GPR4_FLEXIO1_STOP_REQ (1 << 12) +#define GPR_GRP4_EDMA_STOP_ACK (1 << 16) +#define GPR_GPR4_CAN1_STOP_ACK (1 << 17) +#define GPR_GPR4_CAN2_STOP_ACK (1 << 18) +#define GPR_GPR4_TRNG_STOP_ACK (1 << 19) +#define GPR_GPR4_ENET_STOP_ACK (1 << 20) +#define GPR_GPR4_SAI1_STOP_ACK (1 << 21) +#define GPR_GPR4_SAI2_STOP_ACK (1 << 22) +#define GPR_GPR4_SAI3_STOP_ACK (1 << 23) +#define GPR_GPR4_SEMC_STOP_ACK (1 << 25) +#define GPR_GPR4_PIT_STOP_ACK (1 << 26) +#define GPR_GPR4_FLEXSPI_STOP_ACK (1 << 27) +#define GPR_GPR4_FLEXIO1_STOP_ACK (1 << 28) + +/* General Purpose Register 5 (GPR5) */ + +#define GPR_GPR5_WDOG1_MASK (1 << 6) +#define GPR_GPR5_WDOG2_MASK (1 << 7) +#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) +#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1 (1 << 23) +#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET (0 << 25) +#define GPR_GPR5_ENET_EVENT3IN_SEL_GPT2CMP1 (1 << 25) +#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK (0 << 28) +#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP (1 << 28) +#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK (0 << 29) +#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP (1 << 29) + +/* General Purpose Register 6 (GPR6) */ + +#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0) +#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1) +#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2) +#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3) +#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4) +#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5) +#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6) +#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7) +#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) + +/* General Purpose Register 7 (GPR7) */ + +#define GPR_GPR7_LPI2C1_STOP_REQ (1 << 0) +#define GPR_GPR7_LPI2C2_STOP_REQ (1 << 1) +#define GPR_GPR7_LPI2C3_STOP_REQ (1 << 2) +#define GPR_GPR7_LPI2C4_STOP_REQ (1 << 3) +#define GPR_GPR7_LPSPI1_STOP_REQ (1 << 4) +#define GPR_GPR7_LPSPI2_STOP_REQ (1 << 5) +#define GPR_GPR7_LPSPI3_STOP_REQ (1 << 6) +#define GPR_GPR7_LPSPI4_STOP_REQ (1 << 7) +#define GPR_GPR7_LPUART1_STOP_REQ (1 << 8) +#define GPR_GPR7_LPUART2_STOP_REQ (1 << 9) +#define GPR_GPR7_LPUART3_STOP_REQ (1 << 10) +#define GPR_GPR7_LPUART4_STOP_REQ (1 << 11) +#define GPR_GPR7_LPUART5_STOP_REQ (1 << 12) +#define GPR_GPR7_LPUART6_STOP_REQ (1 << 13) +#define GPR_GPR7_LPUART7_STOP_REQ (1 << 14) +#define GPR_GPR7_LPUART8_STOP_REQ (1 << 15) +#define GPR_GPR7_LPI2C1_STOP_ACK (1 << 16) +#define GPR_GPR7_LPI2C2_STOP_ACK (1 << 17) +#define GPR_GPR7_LPI2C3_STOP_ACK (1 << 18) +#define GPR_GPR7_LPI2C4_STOP_ACK (1 << 19) +#define GPR_GPR7_LPSPI1_STOP_ACK (1 << 20) +#define GPR_GPR7_LPSPI2_STOP_ACK (1 << 21) +#define GPR_GPR7_LPSPI3_STOP_ACK (1 << 22) +#define GPR_GPR7_LPSPI4_STOP_ACK (1 << 23) +#define GPR_GPR7_LPUART1_STOP_ACK (1 << 24) +#define GPR_GPR7_LPUART2_STOP_ACK (1 << 25) +#define GPR_GPR7_LPUART3_STOP_ACK (1 << 26) +#define GPR_GPR7_LPUART4_STOP_ACK (1 << 27) +#define GPR_GPR7_LPUART5_STOP_ACK (1 << 28) +#define GPR_GPR7_LPUART6_STOP_ACK (1 << 29) +#define GPR_GPR7_LPUART7_STOP_ACK (1 << 30) +#define GPR_GPR7_LPUART8_STOP_ACK (1 << 31) + +/* General Purpose Register 8 (GPR8) */ + +#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0) +#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1) +#define GPR_GPR8_LPI2C1_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_DOZED (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2) +#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3) +#define GPR_GPR8_LPI2C2_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_DOZED (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4) +#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5) +#define GPR_GPR8_LPI2C3_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_DOZED (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6) +#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7) +#define GPR_GPR8_LPI2C4_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_DOZED (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8) +#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9) +#define GPR_GPR8_LPSPI1_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_DOZED (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10) +#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11) +#define GPR_GPR8_LPSPI2_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_DOZED (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12) +#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13) +#define GPR_GPR8_LPSPI3_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_DOZED (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14) +#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15) +#define GPR_GPR8_LPSPI4_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_DOZED (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16) +#define GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17) +#define GPR_GPR8_LPUART1_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_DOZED (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18) +#define GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19) +#define GPR_GPR8_LPUART2_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_DOZED (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20) +#define GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21) +#define GPR_GPR8_LPUART3_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_DOZED (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22) +#define GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23) +#define GPR_GPR8_LPUART4_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_DOZED (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24) +#define GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25) +#define GPR_GPR8_LPUART5_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_DOZED (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26) +#define GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27) +#define GPR_GPR8_LPUART6_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_DOZED (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28) +#define GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29) +#define GPR_GPR8_LPUART7_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_DOZED (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30) +#define GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31) +#define GPR_GPR8_LPUART8_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_DOZED (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) + +/* General Purpose Register 9 (GPR9) - Reserved */ + +/* General Purpose Register 10 (GPR10) */ + +#define GPR_GPR10_NIDEN (1 << 0) +#define GPR_GPR10_DBG_EN (1 << 1) +#define GPR_GPR10_SEC_ERR_RESP (1 << 2) +#define GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX (1 << 4) +#define GPR_GPR10_OCRAM_TZ_EN (1 << 8) +#define GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9) +#define GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) +# define GPR_GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) +#define GPR_GPR10_LOCK_NIDEN (1 << 16) +#define GPR_GPR10_LOCK_DBG_EN (1 << 17) +#define GPR_GPR10_LOCK_SEC_ERR_RESP (1 << 18) +#define GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX (1 << 20) +#define GPR_GPR10_LOCK_OCRAM_TZ_EN (1 << 24) +#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25) +#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) +# define GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) + +/* General Purpose Register 11 (GPR11) */ + +#define GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS (0) +#define GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS (2) +#define GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS (4) +#define GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS (6) +#define GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +#define GPR_GPR11_BEE_DE_RX_EN_SHIFTS (8) +#define GPR_GPR11_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R0_EN (1) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R1_EN (2) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R2_EN (4) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R3_EN (8) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS (16) +#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) +#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS (18) +#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) +#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS (20) +#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) +#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS (22) +#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) +#define GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS (24) +#define GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_R0_EN (1) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_R1_EN (2) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_R2_EN (4) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_R3_EN (8) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) + +/* General Purpose Register 12 (GPR12) */ + +#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0) +#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1) +#define GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_DOZED (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +#define GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4) +#define GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_ACMP_IPG_ON_IN_STOP (0 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_ACMP_IPG_OFF_IN_STOP (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) + +/* General Purpose Register 13 (GPR13) */ + +#define GPR_GPR13_ARCACHE_USDHC_CACHEABLE (1 << 0) +#define GPR_GPR13_AWCACHE_USDHC_CACHEABLE (1 << 1) +#define GPR_GPR13_CACHE_ENET_CACHEABLE (1 << 7) +#define GPR_GPR13_CACHE_USB_CACHEABLE (1 << 13) + +/* General Purpose Register 14 (GPR14) */ + +#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN (1 << 0) +#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN (1 << 1) +#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN (1 << 2) +#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN (1 << 3) +#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP (1 << 4) +#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP (1 << 5) +#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP (1 << 6) +#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP (1 << 7) +#define GPR_GPR14_ACMP1_SAMPLE_SYNC_EN (1 << 8) +#define GPR_GPR14_ACMP2_SAMPLE_SYNC_EN (1 << 9) +#define GPR_GPR14_ACMP3_SAMPLE_SYNC_EN (1 << 10) +#define GPR_GPR14_ACMP4_SAMPLE_SYNC_EN (1 << 11) +#define GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16) +#define GPR_GPR14_CM7_CFGITCMSZ_MASK (0x4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_0KB (0 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_4KB (3 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_8KB (4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_16KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_32KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_64KB (7 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_128KB (8 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_256KB (9 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +#define GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20) +#define GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xf << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_0KB (0 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_4KB (3 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_8KB (4 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_16KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_32KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_64KB (7 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_128KB (8 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_256KB (9 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) + +/* General Purpose Register 15 (GPR16) - Reserved */ + +/* General Purpose Register 16 (GPR16) */ + +#define GPR_GPR16_INIT_ITCM_EN (1 << 0) +#define GPR_GPR16_INIT_DTCM_EN (1 << 1) +#define GPR_GPR16_FLEXRAM_BANK_CFG_SELF (1 << 2) + +/* General Purpose Register 17 (GPR17) */ + +#define GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0) +#define GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xffffffff << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK_CFG(n) ((uint32_t)(n)) << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK0_SHIFT (0) +#define GPR_GPR17_FLEXRAM_BANK0_MASK (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_DTCM (2 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_ITCM (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK1_SHIFT (2) +#define GPR_GPR17_FLEXRAM_BANK1_MASK (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_DTCM (2 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_ITCM (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK2_SHIFT (4) +#define GPR_GPR17_FLEXRAM_BANK2_MASK (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_DTCM (2 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_ITCM (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK3_SHIFT (6) +#define GPR_GPR17_FLEXRAM_BANK3_MASK (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_DTCM (2 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_ITCM (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK4_SHIFT (8) +#define GPR_GPR17_FLEXRAM_BANK4_MASK (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_DTCM (2 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_ITCM (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK5_SHIFT (10) +#define GPR_GPR17_FLEXRAM_BANK5_MASK (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_DTCM (2 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_ITCM (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK6_SHIFT (12) +#define GPR_GPR17_FLEXRAM_BANK6_MASK (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_DTCM (2 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_ITCM (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK7_SHIFT (14) +#define GPR_GPR17_FLEXRAM_BANK7_MASK (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_DTCM (2 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_ITCM (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) + +/* General Purpose Register 18 (GPR18) */ + +#define GPR_GPR18_LOCK_M7_APC_AC_R0_BOT (1 << 0) +#define GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3) +#define GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) +#define GPR_GPR18_M7_APC_AC_R0_BOT(n) ((uint32_t)(n)) << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) + +/* General Purpose Register 19 (GPR19) */ + +#define GPR_GPR19_LOCK_M7_APC_AC_R0_TOP (1 << 0) +#define GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3) +#define GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0x1fffffff << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) +#define GPR_GPR19_M7_APC_AC_R0_TOP(n) ((uint32_t)(n)) << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) + +/* General Purpose Register 20 (GPR20) */ + +#define GPR_GPR20_LOCK_M7_APC_AC_R1_BOT (1 << 0) +#define GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3) +#define GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R1_BOT_SHIFT) +#define GPR_GPR20_M7_APC_AC_R1_BOT(n) ((uint32_t)(n)) << GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT) + +/* General Purpose Register 21 (GPR21) */ + +#define GPR_GPR21_LOCK_M7_APC_AC_R1_TOP (1 << 0) +#define GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3) +#define GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0x1fffffff << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) +#define GPR_GPR21_M7_APC_AC_R1_TOP(n) ((uint32_t)(n)) << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) + +/* General Purpose Register 22 (GPR22) */ + +#define GPR_GPR22_LOCK_M7_APC_AC_R2_BOT (1 << 0) +#define GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3) +#define GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R2_BOT_SHIFT) +#define GPR_GPR22_M7_APC_AC_R2_BOT(n) ((uint32_t)(n)) << GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT) + +/* General Purpose Register 23 (GPR23) */ + +#define GPR_GPR23_LOCK_M7_APC_AC_R2_TOP (1 << 0) +#define GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3) +#define GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0x1fffffff << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) +#define GPR_GPR23_M7_APC_AC_R2_TOP(n) ((uint32_t)(n)) << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) + +/* General Purpose Register 24 (GPR24) */ + +#define GPR_GPR24_LOCK_M7_APC_AC_R3_BOT (1 << 0) +#define GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3) +#define GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R3_BOT_SHIFT) +#define GPR_GPR24_M7_APC_AC_R3_BOT(n) ((uint32_t)(n)) << GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT) + +/* General Purpose Register 25 (GPR25) */ + +#define GPR_GPR25_LOCK_M7_APC_AC_R3_TOP (1 << 0) +#define GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3) +#define GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0x1fffffff << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) +#define GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(n)) << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h new file mode 100644 index 00000000000..f380cb48077 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h @@ -0,0 +1,261 @@ +/**************************************************************************** + * arch/arm/src/imxrt/chip/rt102x/imxrt102x_memorymap.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/* System memory map */ + +#define IMXRT_ITCM_BASE 0x00000000 /* 256KB ITCM */ + /* 0x00040000 768KB ITCM Reserved */ + /* 0x00100000 1MB ITCM Reserved */ +#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */ + /* 0x00218000 416KB ROMCP Reserved */ + /* 0x00280000 1536KB Reserved */ + /* 0x00400000 124MB Reserved */ + /* 0x00800000 1527MB Reserved */ +#define IMXRT_FLEXSPI_BASE 0x06000000 /* 128MB FlexSPI (Aliased) */ +#define IMXRT_SEMCA_BASE 0x06800000 /* 639MB SEMC (Aliased) */ + /* 0x90000000 256MB SEMC (Aliased) */ +#define IMXRT_DTCM_BASE 0x20000000 /* 256KB DTCM */ + /* 0x20040000 768KB DTCM Reserved */ + /* 0x20100000 1MB Reserved */ +#define IMXRT_OCRAM_BASE 0x20200000 /* 256KB OCRAM */ + /* 0x20240000 1792KB OCRAM Reserved */ + /* 0x20400000 252MB Reserved */ + /* 0x30000000 256MB Reserved */ +#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ +#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ +#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ +#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ + /* 0x40400000 12MB Reserved */ + /* 0x41000000 1MB Reserved */ +#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ + /* 41200000 1MB Reserved for "per" GPV */ + /* 41300000 1MB Reserved for "ems" GPV */ +#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ + /* 0x41500000 1MB GPV Reserved */ + /* 0x41600000 1MB GPV Reserved */ + /* 0x41700000 1MB GPV Reserved */ + /* 0x41800000 8MB Reserved */ + /* 0x42000000 32MB Reserved */ + /* 0x44000000 64MB Reserved */ + /* 0x48000000 384MB Reserved */ +#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */ +#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */ +#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ +#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ +#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ + /* 0xe0100000 511MB Reserved */ + +/* AIPS-1 memory map */ + + /* 0x40000000 256KB Reserved */ + /* 0x40040000 240KB Reserved */ +#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 16KB AIPS-1 Configuration */ +#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ +#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ + /* 0x40088000 16KB Reserved */ + /* 0x4008c000 16KB Reserved */ + /* 0x40090000 16KB Reserved */ +#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ + /* 0x40098000 16KB Reserved */ + /* 0x4009c000 16KB Reserved */ + /* 0x400a0000 16KB Reserved */ +#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ +#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ +#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */ +#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MXRT(FLEXRAM) */ +#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */ +#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */ +#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */ +#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */ +#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */ +#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */ +#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */ +#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */ +#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ +#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ +#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ + /* 0x400e0000 16KB Reserved */ + /* 0x400e4000 16KB Reserved */ +#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ +#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ + /* 400f0000 16KB Reserved */ +#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ +#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ +#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */ + +/* AIPS-2 memory map */ + + /* 0x40100000 256KB Reserved */ + /* 0x40140000 240KB Reserved */ +#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ +#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ +#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */ +#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */ +#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */ +#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */ +#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */ +#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ +#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ +#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ + /* 0x401a4000 16KB Reserved */ + /* 0x401a8000 16KB Reserved */ +#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ + /* 0x401b0000 16KB Reserved */ + /* 0x401b4000 16KB Reserved */ +#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ +#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ +#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ + /* 0x401c4000 16KB Reserved */ + /* 0x401c8000 16KB Reserved */ + /* 0x401cc000 16KB Reserved */ +#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ +#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ + /* 0x401d8000 16KB Reserved */ +#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */ +#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */ + /* 0x401e4000 16KB Reserved */ + /* 0x401e8000 16KB Reserved */ +#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */ +#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */ +#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */ +#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */ +#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */ + +/* AIPS-3 memory map */ + + /* 0x40200000 256KB Reserved */ + /* 0x40240000 240KB Reserved */ +#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ + /* 0x40280000 16KB Reserved */ + /* 0x40284000 16KB Reserved */ + /* 0x40288000 16KB Reserved */ + /* 0x4028c000 16KB Reserved */ + /* 0x40290000 16KB Reserved */ + /* 0x40294000 16KB Reserved */ + /* 0x40298000 16KB Reserved */ + /* 0x4029c000 16KB Reserved */ + /* 0x402a0000 16KB Reserved */ + /* 0x402a4000 16KB Reserved */ +#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */ + /* 0x402ac000 16KB Reserved */ + /* 0x402b0000 16KB Reserved */ + /* 0x402b4000 16KB Reserved */ + /* 0x402b8000 16KB Reserved */ + /* 0x402bc000 16KB Reserved */ +#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ +#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ + /* 0x402c8000 16KB Reserved */ + /* 0x402cc000 16KB Reserved */ + /* 0x402d0000 16KB Reserved */ + /* 0x402d4000 16KB Reserved */ +#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ + /* 0x402dc000 16KB Reserved */ +#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ + /* 0x402e4000 16KB Reserved */ + /* 0x402e8000 16KB Reserved */ + /* 0x402ec000 16KB Reserved */ +#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ + /* 0x402f4000 16KB Reserved */ + /* 0x402f8000 16KB Reserved */ +#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ + +/* AIPS-4 memory map */ + + /* 0x40300000 256KB Reserved */ + /* 0x40340000 240KB Reserved */ +#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ +#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ +#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ +#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ +#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ + /* 0x40390000 16KB Reserved */ +#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ +#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ +#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ +#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ + /* 0x403a4000 16KB Reserved */ + /* 0x403a8000 16KB Reserved */ + /* 0x403ac000 16KB Reserved */ +#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ +#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ + /* 0x403b8000 16KB Reserved */ +#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */ +#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */ + /* 0x403c4000 16KB Reserved */ +#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */ +#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ + /* 0x403d0000 16KB Reserved */ + /* 0x403d4000 16KB Reserved */ + /* 0x403d8000 16KB Reserved */ +#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ +#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ + /* 0x403e4000 16KB Reserved */ + /* 0x403e8000 16KB Reserved */ +#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */ +#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */ +#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */ +#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */ +#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */ + +/* PPB memory map */ + +#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */ +#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */ +#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ +#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ +#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ + /* 0xe0045000 236KB PPB Reserved */ +#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ + /* 0xe0081000 444KB PPB Reserved */ + /* 0xe00f0000 52KB PPB Reserved */ +#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ +#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ +#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h new file mode 100644 index 00000000000..600f2565e3e --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h @@ -0,0 +1,914 @@ +/***************************************************************************** + * arch/arm/src/imxrt/chip/rt102x/imxrt102x_pinmux.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_PINMUX_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_PINMUX_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include "chip/imxrt_iomuxc.h" + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. + * For example, if LPUART1 CTS connects via the AD_B1_04 pin, then the + * following definition should appear in the board.h header file for + * that board: + * + * #define GPIO_LPUART3_CTS GPIO_LPUART3_CTS_1 + * + * The driver will then automatically configure to use the AD_B1_04 pin + * for LPUART1 CTS. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific IOMUX options such as + * frequency, open-drain, push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. See the upper imxrt_gpio.h and + * imxrt_iomuxc.h header files for available definitions. + */ + +/* Analog Comparator (ACMP) */ + +#define GPIO_ACMP_OUT00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_ACMP_OUT01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_ACMP_OUT02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_ACMP_OUT03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) + +/* ARM */ + +#define GPIO_ARM_CM7_RXEV (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_ARM_CM7_TXEV (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) + +/* Clock Controller Module (CCM) */ + +#define GPIO_CCM_CLKO1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_CCM_CLKO2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_CCM_PMIC_RDY (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_CCM_PMIC_READY_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_CCM_PMIC_READY_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_CCM_PMIC_READY_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) + +#define GPIO_CCM_PMIC_VSTBY_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) +#define GPIO_CCM_REF_EN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_CCM_STOP (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_CCM_WAIT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) + +/* Ethernet (ENET) */ + +#define GPIO_ENET_1588_EVENT0_IN (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_ENET_1588_EVENT0_OUT (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_ENET_1588_EVENT1_IN (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_ENET_1588_EVENT1_OUT (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_ENET_1588_EVENT2_IN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_ENET_1588_EVENT2_OUT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_ENET_1588_EVENT3_IN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_ENET_1588_EVENT3_OUT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_ENET_COL (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_ENET_CRS (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_ENET_MDC_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_MDC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_MDC_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_MDIO_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ + IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_MDIO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ + IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_MDIO_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ + IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RDATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_ENET_RDATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) + +#define GPIO_ENET_REF_CLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ + IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) +#define GPIO_ENET_REF_CLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ + IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) +#define GPIO_ENET_RX_CLK (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC36_INDEX)) +#define GPIO_ENET_RX_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_DATA01 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_DATA02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_ENET_RX_DATA03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_ENET_RX_EN_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_EN_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_ER_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_ER_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_TDATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX ) +#define GPIO_ENET_TDATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX ) +#define GPIO_ENET_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ + IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE ) +#define GPIO_ENET_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ + IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE ) +#define GPIO_ENET_TX_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_TX_DATA01 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_TX_DATA02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_ENET_TX_DATA03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_ENET_TX_EN_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_TX_EN_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_TX_ER (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) + +/* External Watchdog Monitor (EWM) */ + +#define GPIO_EWM_OUT_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_EWM_OUT_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_EWM_OUT_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) + +/* Flexible Controller Area Network (FLEXCAN) */ + +#define GPIO_FLEXCAN1_RX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_FLEXCAN1_RX_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_FLEXCAN1_RX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_FLEXCAN1_RX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_FLEXCAN1_TX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_FLEXCAN1_TX_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_FLEXCAN1_TX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_FLEXCAN1_TX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_FLEXCAN2_RX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_FLEXCAN2_RX_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_FLEXCAN2_RX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_FLEXCAN2_RX_4 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_FLEXCAN2_TX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_FLEXCAN2_TX_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_FLEXCAN2_TX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_FLEXCAN2_TX_4 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) + +/* Flexible I/O (FlexIO) */ + +#define GPIO_FLEXIO1_FLEXIO00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_FLEXIO1_FLEXIO01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_FLEXIO1_FLEXIO02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_FLEXIO1_FLEXIO03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_FLEXIO1_FLEXIO04 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_FLEXIO1_FLEXIO05 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_FLEXIO1_FLEXIO06 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_FLEXIO1_FLEXIO07 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_FLEXIO1_FLEXIO08 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_FLEXIO1_FLEXIO09 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_FLEXIO1_FLEXIO10 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_FLEXIO1_FLEXIO11 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_FLEXIO1_FLEXIO12 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_FLEXIO1_FLEXIO13 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_FLEXIO1_FLEXIO14 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_FLEXIO1_FLEXIO15 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_FLEXIO1_FLEXIO16 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_FLEXIO1_FLEXIO17 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_FLEXIO1_FLEXIO18 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_FLEXIO1_FLEXIO19 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_FLEXIO1_FLEXIO20 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_FLEXIO1_FLEXIO21 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_FLEXIO1_FLEXIO22 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_FLEXIO1_FLEXIO23 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_FLEXIO1_FLEXIO24 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_FLEXIO1_FLEXIO25 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_FLEXIO1_FLEXIO26 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_FLEXIO1_FLEXIO27 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_FLEXIO1_FLEXIO28 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_FLEXIO1_FLEXIO29 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_FLEXIO1_FLEXIO30 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_FLEXIO1_FLEXIO31 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) + +/* Enhanced Flex Pulse Width Modulator (eFlexPWM) */ + +#define GPIO_FLEXPWM1_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_FLEXPWM1_PWMA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_FLEXPWM1_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_FLEXPWM1_PWMA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_FLEXPWM1_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_FLEXPWM1_PWMA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_FLEXPWM1_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_FLEXPWM1_PWMA03_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_FLEXPWM1_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_FLEXPWM1_PWMB00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_FLEXPWM1_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_FLEXPWM1_PWMB01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_FLEXPWM1_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_FLEXPWM1_PWMB02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_FLEXPWM1_PWMB03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_FLEXPWM1_PWMB03_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_FLEXPWM1_PWMX00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_FLEXPWM1_PWMX01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_FLEXPWM1_PWMX02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_FLEXPWM1_PWMX03 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_FLEXPWM2_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_FLEXPWM2_PWMA00_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_FLEXPWM2_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_FLEXPWM2_PWMA01_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_FLEXPWM2_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_FLEXPWM2_PWMA02_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_FLEXPWM2_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_FLEXPWM2_PWMA03_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_FLEXPWM2_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_FLEXPWM2_PWMB00_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_FLEXPWM2_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_FLEXPWM2_PWMB01_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_FLEXPWM2_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_FLEXPWM2_PWMB02_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_FLEXPWM2_PWMB03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_FLEXPWM2_PWMB03_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_FLEXPWM2_PWMX00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_FLEXPWM2_PWMX01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_FLEXPWM2_PWMX02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_FLEXPWM2_PWMX03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) + +/* Flexible SPI (FlexSPI) */ + +#define GPIO_FLEXSPIA_DATA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_FLEXSPIA_DATA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_FLEXSPIA_DATA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_FLEXSPIA_DATA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) +#define GPIO_FLEXSPIA_DATA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_FLEXSPIA_DATA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_FLEXSPIA_DATA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_FLEXSPIA_DATA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_FLEXSPIA_DQS (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_FLEXSPIA_SCLK_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_FLEXSPIA_SCLK_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_FLEXSPIA_SS0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_FLEXSPIA_SS0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) +#define GPIO_FLEXSPIA_SS1_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_FLEXSPIA_SS1_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) + +#define GPIO_FLEXSPIB_DATA00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_FLEXSPIB_DATA01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_FLEXSPIB_DATA02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_FLEXSPIB_DATA03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_FLEXSPIB_DQS (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_FLEXSPIB_SCLK (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_FLEXSPIB_SS0_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_FLEXSPIB_SS0_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_FLEXSPIB_SS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) + +/* GPIO */ + +#define GPIO_GPIO1_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_GPIO1_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_GPIO1_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_GPIO1_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_GPIO1_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_GPIO1_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_GPIO1_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_GPIO1_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_GPIO1_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_GPIO1_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_GPIO1_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_GPIO1_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_GPIO1_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_GPIO1_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_GPIO1_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_GPIO1_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_GPIO1_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_GPIO1_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_GPIO1_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_GPIO1_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_GPIO1_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_GPIO1_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_GPIO1_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_GPIO1_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_GPIO1_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_GPIO1_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_GPIO1_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_GPIO1_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_GPIO1_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_GPIO1_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_GPIO1_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_GPIO1_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) + +#define GPIO_GPIO2_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_GPIO2_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_GPIO2_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_GPIO2_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_GPIO2_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_GPIO2_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_GPIO2_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_GPIO2_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_GPIO2_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_GPIO2_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_GPIO2_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_GPIO2_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_GPIO2_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_GPIO2_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_GPIO2_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_GPIO2_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_GPIO2_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_GPIO2_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_GPIO2_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_GPIO2_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_GPIO2_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_GPIO2_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_GPIO2_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_GPIO2_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_GPIO2_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_GPIO2_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_GPIO2_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_GPIO2_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_GPIO2_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_GPIO2_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_GPIO2_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_GPIO2_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) + +#define GPIO_GPIO3_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC32_INDEX)) +#define GPIO_GPIO3_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC33_INDEX)) +#define GPIO_GPIO3_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC34_INDEX)) +#define GPIO_GPIO3_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX)) +#define GPIO_GPIO3_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC36_INDEX)) +#define GPIO_GPIO3_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC37_INDEX)) +#define GPIO_GPIO3_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC38_INDEX)) +#define GPIO_GPIO3_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX)) +#define GPIO_GPIO3_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC40_INDEX)) +#define GPIO_GPIO3_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC41_INDEX)) +#define GPIO_GPIO3_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_GPIO3_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_GPIO3_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_GPIO3_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_GPIO3_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_GPIO3_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_GPIO3_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) +#define GPIO_GPIO3_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_GPIO3_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_GPIO3_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_GPIO3_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_GPIO3_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_GPIO3_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_GPIO3_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_GPIO3_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_GPIO3_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_GPIO3_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_GPIO3_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) +#define GPIO_GPIO3_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) + +#define GPIO_GPIO5_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) +#define GPIO_GPIO5_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) +#define GPIO_GPIO5_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) + +/* General Purpose Timer (GPT) */ + +#define GPIO_GPT1_CAPTURE1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_GPT1_CAPTURE2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_GPT1_CLK (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX)) +#define GPIO_GPT1_COMPARE1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_GPT1_COMPARE2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_GPT1_COMPARE3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) + +#define GPIO_GPT2_CAPTURE1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_GPT2_CAPTURE2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_GPT2_CLK (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_GPT2_COMPARE1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_GPT2_COMPARE2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_GPT2_COMPARE3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) + +/* JTAG */ + +#define GPIO_JTAG_MOD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_JTAG_TCK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_JTAG_TDI (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_3_INDEX)) +#define GPIO_JTAG_TDO (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_JTAG_TMS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_JTAG_TRSTB (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) + +/* Keypad Port (KPP) */ + +#define GPIO_KPP_COL00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_KPP_COL01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_KPP_COL02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_KPP_COL03 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_KPP_COL04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_KPP_COL05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_KPP_COL06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_KPP_COL07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_KPP_ROW00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_KPP_ROW01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_KPP_ROW02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_KPP_ROW03 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_KPP_ROW04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_KPP_ROW05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_KPP_ROW06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_KPP_ROW07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) + +/* Low Power Inter-Integrated Circuit (LPI2C) */ + +#define GPIO_LPI2C1_HREQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_LPI2C1_SCL_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_LPI2C1_SCL_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ + IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C1_SDA_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_LPI2C1_SDA_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ + IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) + +#define GPIO_LPI2C2_SCL_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_LPI2C2_SCL_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_LPI2C2_SDA_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_LPI2C2_SDA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) + +#define GPIO_LPI2C3_SCL_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_LPI2C3_SCL_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C3_SDA_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_LPI2C3_SDA_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) + +#define GPIO_LPI2C4_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | \ + IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C4_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C4_SDA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) + +/* Low Power Serial Peripheral Interface (LPSPI) */ + +#define IOMUX_LPSPI (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ + IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM) + +#define GPIO_LPSPI1_PCS0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_PCS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_PCS2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_PCS3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SCK_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SDI_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SDO_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX) | IOMUX_LPSPI) + +#define GPIO_LPSPI2_PCS0_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS0_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SCK_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SCK_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDI_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDI_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDO_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDO_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX) | IOMUX_LPSPI) + +#define GPIO_LPSPI3_PCS0 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_PCS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_PCS2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_PCS3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SCK (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SDI (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SDO (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX) | IOMUX_LPSPI) + +#define GPIO_LPSPI4_PCS0_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_PCS1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_PCS2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_PCS3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SCK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SDI_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SDO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX) | IOMUX_LPSPI) + +/* Low Power Universal Asynchronous Receiver/Transmitter (LPUART) */ + +#define IOMUX_UART (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ + IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER) + +#define GPIO_LPUART1_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_LPUART1_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_LPUART1_RX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX) | IOMUX_UART) +#define GPIO_LPUART1_TX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX) | IOMUX_UART) + +#define GPIO_LPUART2_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_LPUART2_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_LPUART2_RTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_LPUART2_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_LPUART2_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX) | IOMUX_UART) +#define GPIO_LPUART2_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX) | IOMUX_UART) +#define GPIO_LPUART2_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX) | IOMUX_UART) +#define GPIO_LPUART2_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX) | IOMUX_UART) + +#define GPIO_LPUART3_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_LPUART3_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_LPUART3_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX) | IOMUX_UART) +#define GPIO_LPUART3_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX) | IOMUX_UART) +#define GPIO_LPUART3_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX) | IOMUX_UART) +#define GPIO_LPUART3_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX) | IOMUX_UART) + +#define GPIO_LPUART4_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_LPUART4_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_LPUART4_RTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_LPUART4_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_LPUART4_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_RX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_TX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX) | IOMUX_UART) + +#define GPIO_LPUART5_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_LPUART5_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_LPUART5_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX) | IOMUX_UART) +#define GPIO_LPUART5_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_LPUART5_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX) | IOMUX_UART) +#define GPIO_LPUART5_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) + +#define GPIO_LPUART6_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_LPUART6_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_LPUART6_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX) | IOMUX_UART) +#define GPIO_LPUART6_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX) | IOMUX_UART) +#define GPIO_LPUART6_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX) | IOMUX_UART) +#define GPIO_LPUART6_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX) | IOMUX_UART) + +#define GPIO_LPUART7_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_LPUART7_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_LPUART7_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_LPUART7_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_LPUART7_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_LPUART7_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) + +#define GPIO_LPUART8_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_LPUART8_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_LPUART8_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX) | IOMUX_UART) +#define GPIO_LPUART8_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX) | IOMUX_UART) +#define GPIO_LPUART8_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX) | IOMUX_UART) +#define GPIO_LPUART8_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX) | IOMUX_UART) + +/* Medium Quality Sound (MQS) */ + +#define GPIO_MQS_LEFT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_MQS_LEFT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_MQS_LEFT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_MQS_RIGHT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_MQS_RIGHT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_MQS_RIGHT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) + +/* NMI */ + +#define GPIO_NMI_GLUE_NMI_1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) +#define GPIO_NMI_GLUE_NMI_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_BO_05_INDEX)) + +/* Periodic Interrupt Timer (PIT) */ + +#define GPIO_PIT_TRIGGER0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_PIT_TRIGGER1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_PIT_TRIGGER2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_PIT_TRIGGER3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) + +/* Quad Timer (QTimer) */ + +#define GPIO_QTIMER1_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_QTIMER1_TIMER0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00INDEX)) +#define GPIO_QTIMER1_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_QTIMER1_TIMER1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_QTIMER1_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_QTIMER1_TIMER2_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_QTIMER1_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_QTIMER1_TIMER3_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) + +#define GPIO_QTIMER2_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_QTIMER2_TIMER0_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_QTIMER2_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_QTIMER2_TIMER1_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_QTIMER2_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_QTIMER2_TIMER2_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_QTIMER2_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_QTIMER2_TIMER3_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_BO_07_INDEX)) + +/* Synchronous Audio Interface (SAI) */ + +#define GPIO_SAI1_MCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_SAI1_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_SAI1_MCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_SAI1_MCLK_4 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_SAI1_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_SAI1_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_SAI1_RX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_SAI1_RX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_SAI1_RX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_SAI1_RX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_SAI1_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_SAI1_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_SAI1_RX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_SAI1_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_SAI1_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_SAI1_TX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_SAI1_TX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_SAI1_TX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_SAI1_TX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_SAI1_TX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_SAI1_TX_DATA01_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_SAI1_TX_DATA02_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_SAI1_TX_DATA02_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_SAI1_TX_DATA03_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_SAI1_TX_DATA03_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_SAI1_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_SAI1_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_SAI1_TX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) + +#define GPIO_SAI2_MCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_SAI2_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_SAI2_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_SAI2_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_SAI2_RX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_SAI2_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_SAI2_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_SAI2_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_SAI2_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_SAI2_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_SAI2_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_SAI2_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_SAI2_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_SAI2_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) + +#define GPIO_SAI3_MCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_SAI3_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_SAI3_MCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_SAI3_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_SAI3_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_SAI3_RX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_SAI3_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) +#define GPIO_SAI3_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_SAI3_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) +#define GPIO_SAI3_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_SAI3_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_SAI3_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_SAI3_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_SAI3_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_SAI3_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) + +/* Smart External Memory Controller (SEMC) */ + +#define GPIO_SEMC_ADDR00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_SEMC_ADDR01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_SEMC_ADDR02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_SEMC_ADDR03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_SEMC_ADDR04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_SEMC_ADDR05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_SEMC_ADDR06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_SEMC_ADDR07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_SEMC_ADDR08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_SEMC_ADDR09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_SEMC_ADDR10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_SEMC_ADDR11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_SEMC_ADDR12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_SEMC_BA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_SEMC_BA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_SEMC_CAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_SEMC_CKE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_SEMC_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_SEMC_CS0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_SEMC_CSX00_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_SEMC_CSX00_2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_SEMC_CSX01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_SEMC_CSX02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_SEMC_CSX03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_SEMC_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_SEMC_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_SEMC_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_SEMC_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_SEMC_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_SEMC_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_SEMC_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_SEMC_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_SEMC_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_SEMC_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_SEMC_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_SEMC_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_SEMC_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_SEMC_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_SEMC_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_SEMC_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_SEMC_DM00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_SEMC_DM01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_SEMC_DQS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_SEMC_RAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_SEMC_RDY_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_SEMC_RDY_2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_SEMC_WE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) + +/* Secure Non-Volatile Storage (SNVS) */ + +#define GPIO_SNVS_LP_PMIC_ON_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) +#define GPIO_SNVS_VIO_5 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_SNVS_VIO_5_CTL (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) + +/* Sony/Philips Digital Interface (SPDIF) */ + +#define GPIO_SPDIF_EXT_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_SPDIF_IN_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_SPDIF_IN_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_SPDIF_LOCK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_SPDIF_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_SPDIF_OUT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_SPDIF_OUT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_SPDIF_SR_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) + +/* Boot Configuration */ + +#define GPIO_SRC_BOOT_MODE00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_SRC_BOOT_MODE01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) + +#define GPIO_SRC_BOOT_CFG00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_SRC_BOOT_CFG01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_SRC_BOOT_CFG02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_SRC_BOOT_CFG03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_SRC_BOOT_CFG04 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_SRC_BOOT_CFG05 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_SRC_BOOT_CFG06 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_SRC_BOOT_CFG07 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_SRC_BOOT_CFG08 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_SRC_BOOT_CFG09 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) + +#define GPIO_SRC_EARLY_RESET (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) +#define GPIO_SRC_POR_B (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_POR_B)) +#define GPIO_SRC_RESET_B (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_ONOFF)) +#define GPIO_SRC_SYSTEM_RESET (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) +#define GPIO_SRC_TESTER_ACK (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) + +/* USB OTG */ + +#define GPIO_USB_OTG_ID_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_USB_OTG_ID_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_USB_OTG_ID_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_USB_OTG_OC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_USB_OTG_OC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_USB_OTG_OC_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_USB_OTG_PWR_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_USB_OTG_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_USB_OTG_PWR_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) + +#define GPIO_USBPHY1_TSTI_TX_DN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_USBPHY1_TSTI_TX_DP (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_USBPHY1_TSTI_TX_EN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_USBPHY1_TSTI_TX_HIZ (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_USBPHY1_TSTI_TX_HS_MODE (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_USBPHY1_TSTI_TX_LS_MODE (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_USBPHY1_TSTO_PLL_CLK20DIV (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_USBPHY1_TSTO_RX_DISC_DET (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_USBPHY1_TSTO_RX_FS_RXD (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIOUSBPHY1_TSTO_RX_HS_RXD (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_USBPHY1_TSTO_RX_SQUELCH (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) + +/* Ultra Secured Digital Host Controller (uSDHC) */ + +#define GPIO_USDHC1_CD_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) +#define GPIO_USDHC1_CD_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_USDHC1_CD_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_USDHC1_CD_4 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_USDHC1_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_USDHC1_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_USDHC1_DATA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_USDHC1_DATA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_USDHC1_DATA2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_USDHC1_DATA3 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_USDHC1_RESET_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_USDHC1_RESET_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) +#define GPIO_USDHC1_VSELECT_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_USDHC1_VSELECT_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_USDHC1_WP_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_USDHC1_WP_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_USDHC1_WP_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_USDHC1_WP_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_USDHC1_WP_5 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) + +#define GPIO_USDHC2_CD_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_USDHC2_CD_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_USDHC2_CD_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_USDHC2_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_USDHC2_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_USDHC2_DATA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_USDHC2_DATA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_USDHC2_DATA2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_USDHC2_DATA3 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_USDHC2_DATA4 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_USDHC2_DATA5 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_USDHC2_DATA6 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) +#define GPIO_USDHC2_DATA7 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) +#define GPIO_USDHC2_RESET (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_USDHC2_WP_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_USDHC2_WP_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) + +/* Watchdog Timer (WDOG1-2) */ + +#define GPIO_WDOG1_ANY (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_WDOG1_WDOG_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_WDOG1_WDOG_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_WDOG1_WDOG_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_WDOG1_WDOG_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) +#define GPIO_WDOG1_WDOG_RST_DEB (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) + +#define GPIO_WDOG2_WDOG (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_WDOG2_RESET_DEB (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) + +/* Inter-Peripheral Crossbar Switch (XBAR) */ + +#define GPIO_XBAR1_INOUT04 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_XBAR1_INOUT05 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_XBAR1_INOUT06 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_XBAR1_INOUT07 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_XBAR1_INOUT08 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_XBAR1_INOUT09 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_XBAR1_INOUT10_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_XBAR1_INOUT10_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_XBAR1_INOUT11 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_XBAR1_INOUT12_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_XBAR1_INOUT12_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_XBAR1_INOUT13_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_XBAR1_INOUT13_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_XBAR1_INOUT14_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_XBAR1_INOUT14_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_XBAR1_INOUT15_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_XBAR1_INOUT15_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_XBAR1_INOUT16_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_XBAR1_INOUT16_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_XBAR1_INOUT17_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_XBAR1_INOUT17_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) +#define GPIO_XBAR1_INOUT18_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_XBAR1_INOUT18_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_XBAR1_INOUT19_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_XBAR1_INOUT19_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) + +/* XTAL Osc */ + +#define GPIO_REF_24M_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_REF_24M_OUT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_REF_24M_OUT_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_REF_32K_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX)) +#define GPIO_REF_32K_OUT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT102X_PINMUX_H */ diff --git a/arch/arm/src/imxrt/chip/rt102x/imxrt102x_xbar.h b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_xbar.h new file mode 100644 index 00000000000..f8d6aefd1f1 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt102x/imxrt102x_xbar.h @@ -0,0 +1,324 @@ +/* XBAR Defines for IMXRT102x */ + +/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ + +#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ +#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 2) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 3) RESERVED */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 20) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 21) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 22) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 23) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 24) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 25) RESERVED */ +#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ +#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ +#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ +#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 30) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 31) RESERVED */ +#define IMXRT_XBARA1_IN_QTIMER1_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ +#define IMXRT_XBARA1_IN_QTIMER1_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ +#define IMXRT_XBARA1_IN_QTIMER1_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ +#define IMXRT_XBARA1_IN_QTIMER1_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ +#define IMXRT_XBARA1_IN_QTIMER2_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ +#define IMXRT_XBARA1_IN_QTIMER2_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ +#define IMXRT_XBARA1_IN_QTIMER2_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ +#define IMXRT_XBARA1_IN_QTIMER2_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN40 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN40 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN41 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN41 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN42 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN42 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN43 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN43 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN44 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN44 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN45 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN45 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN46 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN46 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN47 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN47 input. */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 48) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 49) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 50) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 51) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 52) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 53) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 54) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 55) RESERVED */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ +#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ +#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 62) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 63) RESERVED */ +#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 76) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 77) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 78) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 79) RESERVED */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ + +/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ + +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ +#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 24) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 25) RESERVED */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT2_SEL_OFFSET IMXXRT_XBARA1(XBAR_OUTPUT,37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_FAULT2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_FAULT3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_EXTA0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_EXTA1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_EXTA2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_EXTA3 */ + +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_EXT_CLK */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 52) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 53) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 54) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 55) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 56) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 57) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 58) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 59) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 60) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 61) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 62) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 63) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 64) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 65) RESERVED */ +#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN */ +#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN */ +#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */ +#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */ +#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */ +#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN */ +#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN */ +#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */ +#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */ +#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 76) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 77) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 78) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 79) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 80) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 81) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 82) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 83) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 84) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 85) RESERVED */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 95) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 96) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 97) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 98) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 99) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 100) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 101) RESERVED */ +#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG10 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG11 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG12 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG13 */ +#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN */ +#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN */ +#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ +#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 129) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 130) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 131) RESERVED */ + +/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ + +#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ +#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 2) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 3) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 4) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 5) RESERVED */ +#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ +#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ +#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ +#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 10) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 11) RESERVED */ +#define IMXRT_XBARB2_IN_QTIMER1_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ +#define IMXRT_XBARB2_IN_QTIMER1_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ +#define IMXRT_XBARB2_IN_QTIMER1_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ +#define IMXRT_XBARB2_IN_QTIMER1_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ +#define IMXRT_XBARB2_IN_QTIMER2_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ +#define IMXRT_XBARB2_IN_QTIMER2_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ +#define IMXRT_XBARB2_IN_QTIMER2_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ +#define IMXRT_XBARB2_IN_QTIMER2_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN20 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN20 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN21 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN21 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN22 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN22 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN23 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN23 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN24 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN24 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN25 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN25 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN26 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN26 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN27 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN27 input. */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 28) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 29) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 30) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 31) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 32) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 33) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 34) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 35) RESERVED */ +#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ +#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ +#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ +#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 48) RESERVED */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 49) RESERVED */ +#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ + +/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ + +#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ +#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ +#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ +#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ +#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ +#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ +#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ +#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ +#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ +#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ +#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ +#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ +#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ +#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ +#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ +#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_ccm.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_ccm.h new file mode 100644 index 00000000000..5b214127fb4 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_ccm.h @@ -0,0 +1,1145 @@ +/************************************************************************************************************ + * arch/arm/src/imxrt/chip/rt105x/imxrt_ccm.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Janne Rosberg + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_CCM_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_CCM_H + +/************************************************************************************************************ + * Included Files + ************************************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/************************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************************/ + +/* Register offsets *****************************************************************************************/ + +#define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ + /* 0x0004 Reserved */ +#define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ +#define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ +#define IMXRT_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */ +#define IMXRT_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */ +#define IMXRT_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */ +#define IMXRT_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */ +#define IMXRT_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */ +#define IMXRT_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */ +#define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ +#define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ +#define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ + /* 0x0034 Reserved */ +#define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ +#define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ + /* 0x0040 Reserved */ + /* 0x0044 Reserved */ +#define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ + /* 0x004c Reserved */ + /* 0x0050 Reserved */ +#define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ + +#define IMXRT_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */ +#define IMXRT_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */ +#define IMXRT_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */ +#define IMXRT_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */ +#define IMXRT_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */ +#define IMXRT_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */ +#define IMXRT_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */ +#define IMXRT_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */ +#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ +#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ +#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ + /* 0x0084 Reserved */ +#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */ + +/* Analog */ + +#define IMXRT_CCM_ANALOG_PLL_ARM_OFFSET 0x0000 /* Analog ARM PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET 0x0010 /* Analog USB1 480MHz PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_USB2_OFFSET 0x0020 /* Analog USB2 480MHz PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET 0x0030 /* Analog System PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET 0x0040 /* 528MHz System PLL Spread Spectrum Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET 0x0050 /* Numerator of 528MHz System PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET 0x0060 /* Denominator of 528MHz System PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET 0x0070 /* Analog Audio PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET 0x0080 /* Numerator of Audio PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET 0x0090 /* Denominator of Audio PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET 0x00a0 /* Analog Video PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET 0x00b0 /* Numerator of Video PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET 0x00c0 /* Denominator of Video PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET 0x00e0 /* Analog ENET PLL Control Register */ +#define IMXRT_CCM_ANALOG_PFD_480_OFFSET 0x00f0 /* 480MHz Clock (PLL3) Phase Fractional Divider Control */ +#define IMXRT_CCM_ANALOG_PFD_528_OFFSET 0x0100 /* 528MHz Clock (PLL2) Phase Fractional Divider Control */ +#define IMXRT_CCM_ANALOG_MISC0_OFFSET 0x0150 /* Miscellaneous Register 0 */ +#define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ +#define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ + +/* Register addresses ***************************************************************************************/ + +#define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) +#define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) +#define IMXRT_CCM_CCSR (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET) +#define IMXRT_CCM_CACRR (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET) +#define IMXRT_CCM_CBCDR (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET) +#define IMXRT_CCM_CBCMR (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET) +#define IMXRT_CCM_CSCMR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET) +#define IMXRT_CCM_CSCMR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET) +#define IMXRT_CCM_CSCDR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET) +#define IMXRT_CCM_CS1CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET) +#define IMXRT_CCM_CS2CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET) +#define IMXRT_CCM_CDCDR (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET) +#define IMXRT_CCM_CSCDR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET) +#define IMXRT_CCM_CSCDR3 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET) +#define IMXRT_CCM_CDHIPR (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET) +#define IMXRT_CCM_CLPCR (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET) +#define IMXRT_CCM_CISR (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET) +#define IMXRT_CCM_CIMR (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET) +#define IMXRT_CCM_CCOSR (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET) +#define IMXRT_CCM_CGPR (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET) +#define IMXRT_CCM_CCGR0 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET) +#define IMXRT_CCM_CCGR1 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET) +#define IMXRT_CCM_CCGR2 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET) +#define IMXRT_CCM_CCGR3 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET) +#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET) +#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET) +#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET) +#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET) + +#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_USB1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_USB2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB2_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_SS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_ENET (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET) +#define IMXRT_CCM_ANALOG_PFD_480 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET) +#define IMXRT_CCM_ANALOG_PFD_528 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET) +#define IMXRT_CCM_ANALOG_MISC0 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET) +#define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) +#define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) + +/* Helper Macros *********************************************************************************/ + +#define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ + +/* Register bit definitions *********************************************************************************/ + +/* Control Register */ + +#define CCM_CCR_OSCNT_SHIFT (0) /* Bits 0-7: Oscillator ready counter value */ +#define CCM_CCR_OSCNT_MASK (0xff << CCM_CCR_OSCNT_SHIFT) +# define CCM_CCR_OSCNT(n) ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT) + /* Bits 8-11: Reserved */ +#define CCM_CCR_COSC_EN (1 << 12) /* Bit 12: On chip oscillator enable */ + /* Bits 13-20: Reserved */ +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21) /* Bits 21-26: Counter for analog_reg_bypass */ +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT) +# define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) +#define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ + /* Bits 28-31: Reserved */ +/* Status Register */ + +#define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ + /* Bits 1-2: Reserved */ +#define CCM_CSR_CAMP2_READY (3 << 0) /* Bit 3: Status indication of CAMP2 */ + /* Bit 4: Reserved */ +#define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ + /* Bits 6-31: Reserved */ +/* Clock Switcher Register */ + +#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ + +/* Arm Clock Root Register */ + +#define CCM_CACRR_ARM_PODF_SHIFT (0) /* Bits 0-2: Divider for ARM clock root */ +#define CCM_CACRR_ARM_PODF_MASK (0x3 << CCM_CACRR_ARM_PODF_SHIFT) +# define CCM_CACRR_ARM_PODF(n) ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT) + +/* Bus Clock Divider Register */ + + /* Bits 0-5: Reserved */ +#define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3 (1 << 7) /* Bit 7: PLL3 PFD1 will be selected */ +#define CCM_CBCDR_IPG_PODF_SHIFT (8) /* Bits 8-9: Divider for ipg podf */ +#define CCM_CBCDR_IPG_PODF_MASK (0x3 << CCM_CBCDR_IPG_PODF_SHIFT) +# define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT) +#define CCM_CBCDR_AHB_PODF_SHIFT (10) /* Bits 10-12: Divider for AHB PODF */ +#define CCM_CBCDR_AHB_PODF_MASK (0x3 << CCM_CBCDR_AHB_PODF_SHIFT) +# define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT) + /* Bits 13-15: Reserved */ +#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ +#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT) +# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) + /* Bits 19-24: Reserved */ +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCDR_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) +# define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) + + /* Bit 26: Reserved */ +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) +# define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + /* Bits 30-31: Reserved */ + +/* Bus Clock Multiplexer Register */ + + /* Bits 0-3: Reserved */ +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1 ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) + /* Bits 6-11: Reserved */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for Trace clock multiplexer */ +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) + /* Bits 16-17: Reserved */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 (1) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 (2) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1 (3) + /* Bits 20-22: Reserved */ +#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */ +#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT) +# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ +#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) +# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) + +/* Serial Clock Multiplexer Register 1 */ + +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) +# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6) /* Bit 6: Selector for the perclk clock multiplexer */ +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) +# define CCM_CSCMR1_PERCLK_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) +# define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0) +# define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK (1) + /* Bits 7-9: Reserved */ +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for sai1 clock multiplexer */ +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for sai2 clock multiplexer */ +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for sai3 clock multiplexer */ +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ +# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2 (0 << 16) /* derive clock from PLL2 PFD2 */ +# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 (1 << 16) /* derive clock from PLL2 PFD0 */ +#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ +# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2 (0 << 17) /* derive clock from PLL2 PFD2 */ +# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0 (1 << 17) /* derive clock from PLL2 PFD0 */ + /* Bits 18-22: Reserved */ +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23) /* Bits 23-25: Divider for flexspi clock root */ +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) +# define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) + /* Bits 26-28: Reserved */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29) /* Bits 29-30: Selector for flexspi clock multiplexer */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) + /* Bit 31: Reserved */ + +/* Serial Clock Multiplexer Register 2 */ + +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) +# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for FlexCAN clock multiplexer */ +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60 ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80 ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) + /* Bits 10-18: Reserved */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for flexio2 clock multiplexer */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) + /* Bits 21-31: Reserved */ + +/* Serial Clock Divider Register 1 */ + +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) +# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) +#define CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Bit 6: Selector for the UART clock multiplexer */ +# define CCM_CSCDR1_UART_CLK_SEL_PLL3_80 (0 << 6) /* derive clock from pll3_80m */ +# define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK (1 << 6) /* derive clock from osc_clk */ + /* Bits 7-10: Reserved */ +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) +# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) + /* Bits 14-15: Reserved */ +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) +# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) + /* Bits 19-24: Reserved */ +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25) /* Bits 25-27: Divider for trace clock */ +#define CCM_CSCDR1_TRACE_PODF_MASK (0x7 << CCM_CSCDR1_TRACE_PODF_SHIFT) +# define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT) + /* Bits 28-31: Reserved */ + +/* Clock Divider Register 1 */ + +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai1 clock podf */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) +# define CCM_CS1CDR_SAI1_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai1 clock pred */ +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) +# define CCM_CS1CDR_SAI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for flexio2 clock */ +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) +# define CCM_CS1CDR_FLEXIO2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) + /* Bits 12-15: Reserved */ +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for sai3 clock podf */ +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) +# define CCM_CS1CDR_SAI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for sai3 clock pred */ +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) +# define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for flexio2 clock */ +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) +# define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) + /* Bits 28-31: Reserved */ + +/* Clock Divider Register 2 */ + +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai2 clock podf */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) +# define CCM_CS2CDR_SAI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai2 clock pred */ +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) +# define CCM_CS2CDR_SAI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) + +/* D1 Clock Divider Register */ + +#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7) /* Bits 7-8: Selector for flexio1 clock multiplexer */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x3 << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9) /* Bits 9-11: Divider for flexio1 clock podf */ +#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12) /* Bits 12-14: Divider for flexio1 clock pred */ +#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) + /* Bits 15-19: Reserved */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) + +/* Serial Clock Divider Register 2 */ + + /* Bits 0-8: Reserved */ +#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for LCDIF root clock multiplexer */ +#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_LCDIF ((uint32_t)(0) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI0_CLK ((uint32_t)(1) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI1_CLK ((uint32_t)(2) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI0_CLK ((uint32_t)(3) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI1_CLK ((uint32_t)(4) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12) /* Bits 12-14: Pre-divider for lcdif clock */ +#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << CCM_CSCDR2_LCDIF_PRED_SHIFT) +# define CCM_CSCDR2_LCDIF_PRED(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRED_SHIFT) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for lcdif root clock pre-multiplexer */ +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD3 ((uint32_t)(1) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD0 ((uint32_t)(3) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD1 ((uint32_t)(4) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD1 ((uint32_t)(5) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +#define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ +# define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ +# define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for lpi2c clock podf */ +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) +# define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) + /* Bits 25-31: Reserved */ + +/* Serial Clock Divider Register 3 */ + + /* Bits 0-8: Reserved */ +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9) /* Bits 9-10: Selector for csi_mclk multiplexer */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_CLK ((uint32_t)(0) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL2_PFD2 ((uint32_t)(1) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_120M ((uint32_t)(2) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_PFD1 ((uint32_t)(3) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11) /* Bits 11-13: Post divider for csi_mclk */ +#define CCM_CSCDR3_CSI_PODF_MASK (0x3 << CCM_CSCDR3_CSI_PODF_SHIFT) +# define CCM_CSCDR3_CSI_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_PODF_SHIFT) + +/* Divider Handshake In-Process Register */ + +#define CCM_CDHIPR_SEMC_PODF_BUSY (1 << 0) /* Bit 0: Busy indicator for semc_podf */ +#define CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) /* Bit 1: Busy indicator for ahb_podf */ + /* Bit 2: Reserved */ +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) /* Bit 3: Busy indicator for periph2_clk_sel mux control */ + /* Bit 4: Reserved */ +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) /* Bit 5: Busy indicator for periph_clk_sel mux control */ + /* Bits 6-15: Reserved */ +#define CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) /* Bit 16: Busy indicator for arm_podf */ + /* Bits 17-31: Reserved */ + +/* Low Power Control Register */ + +#define CCM_CLPCR_LPM_SHIFT (0) /* Bits 0-1: Setting the low power mode */ +#define CCM_CLPCR_LPM_MASK (0x3 << CCM_CLPCR_LPM_SHIFT) +# define CCM_CLPCR_LPM(n) ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT) +# define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ +# define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ +# define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ + /* Bits 2-4: Reserved */ +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ +#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ +#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ +#define CCM_CLPCR_VSTBY (1 << 8) /* Bit 8: Voltage standby request bit */ +#define CCM_CLPCR_STBY_COUNT_SHIFT (9) /* Bits 9-10: Standby counter definition */ +#define CCM_CLPCR_STBY_COUNT_MASK (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT) +# define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT) +#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: On chip oscillator power down */ + /* Bits 12-18: Reserved */ +#define CCM_CLPCR_BYPASS_LPM_HS1 (1 << 19) /* Bit 19: Bypass low power mode handshake */ + /* Bit 20: Reserved */ +#define CCM_CLPCR_BYPASS_LPM_HS0 (1 << 21) /* Bit 21: Bypass low power mode handshake */ +#define CCM_CLPCR_MASK_CORE0_WFI (1 << 22) /* Bit 22: Mask WFI of core0 for entering low power mode */ + /* Bits 23-25: Reserved */ +#define CCM_CLPCR_MASK_SCU_IDLE (1 << 26) /* Bit 26: Mask SCU IDLE for entering low power mode */ +#define CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) /* Bit 27: Mask L2CC IDLE for entering low power mode */ + /* Bits 28-31: Reserved */ + +/* Interrupt Status Register */ + +#define CCM_CISR_LRF_PLL (1 << 0) /* Bit 0: CCM irq2, lock of all enabled and not bypassed PLLs */ + /* Bits 1-5: Reserved */ +#define CCM_CISR_COSC_READY (1 << 6) /* Bit 6: CCM irq2, on board oscillator ready */ + /* Bits 7-16: Reserved */ +#define CCM_CISR_SEMC_PODF_LOADED (1 << 17) /* Bit 17: CCM irq1, frequency change of semc_podf */ + /* Bit 18: Reserved */ +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: CCM irq1, frequency change of periph2_clk_sel */ +#define CCM_CISR_AHB_PODF_LOADED (1 << 20) /* Bit 20: CCM irq1, frequency change of ahb_podf */ + /* Bit 21: Reserved */ +#define CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: CCM irq1, update of periph_clk_sel */ + /* Bits 23-25: Reserved */ +#define CCM_CISR_ARM_PODF_LOADED (1 << 26) /* Bit 26: CCM irq1, frequency change of arm_podf */ + /* Bits 27-31: Reserved */ + +/* Interrupt Mask Register */ + +#define CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Bit 0: mask interrupt generation due to lrf of PLLs */ + /* Bits 1-5: Reserved */ +#define CCM_CIMR_MASK_COSC_READY (1 << 6) /* Bit 6: mask interrupt generation due to on board oscillator ready */ + /* Bits 7-16: Reserved */ +#define CCM_CIMR_MASK_SEMC_PODF_LOADED (1 << 17) /* Bit 17: mask interrupt generation due to frequency change of semc_podf */ + /* Bit 18: Reserved */ +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: mask interrupt generation due to update of periph2_clk_sel */ +#define CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) /* Bit 20: mask interrupt generation due to frequency change of ahb_podf */ + /* Bit 21: Reserved */ +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: mask interrupt generation due to update of periph_clk_sel */ + /* Bits 23-25: Reserved */ +#define CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) /* Bit 26: mask interrupt generation due to frequency change of arm_podf */ + /* Bits 27-31: Reserved */ + +/* Clock Output Source Register */ + +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_SEMC_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_ENC_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_LCDIF_PIX_CLK ((uint32_t)(10) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_AHB_CLK ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_IPG_CLK ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PER_CLK ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ +#define CCM_CCOSR_CLKO1_DIV_MASK (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT) +# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) +#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ +#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ + /* Bits 9-15: Reserved */ +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_CSI_CORE ((uint32_t)(11) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_OSC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI1_CLK ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI2_CLK ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI3_CLK ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_CAN_CLK ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_UART_CLK ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_DIV_MASK (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT) +# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) +#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ + /* Bits 25-31: Reserved */ + +/* General Purpose Register */ + +#define CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Bit 0: Defines clock division of clock for stby_count */ + /* Bits 1-3: Reserved */ +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) /* Bit 4: allow fuse programing */ + /* Bits 5-13: Reserved */ +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14) /* Bits 14-15: System memory DS control */ +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) +# define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) +#define CCM_CGPR_FPL (1 << 16) /* Bit 16: Fast PLL enable */ +#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) /* Bit 17: Control for the Deep Sleep signal to the ARM Platform memories */ + /* Bits 18-31: Reserved */ + +/* Clock Gating Register 0-6 */ + +#define CCM_CG_OFF (0) /* Clock is off during all modes */ +#define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ +#define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ + +#define CCM_CCGRX_CG_SHIFT(r) ((r) << 1) +#define CCM_CCGRX_CG_MASK(r) (0x3 << CCM_CCGRX_CG_SHIFT(r)) +# define CCM_CCGRX_CG(r,v) ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r)) + +#define CCM_CCGRX_CG0_SHIFT (0) +#define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) +# define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) +#define CCM_CCGRX_CG1_SHIFT (2) +#define CCM_CCGRX_CG1_MASK (0x3 << CCM_CCGRX_CG1_SHIFT) +# define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) +#define CCM_CCGRX_CG2_SHIFT (4) +#define CCM_CCGRX_CG2_MASK (0x3 << CCM_CCGRX_CG2_SHIFT) +# define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) +#define CCM_CCGRX_CG3_SHIFT (6) +#define CCM_CCGRX_CG3_MASK (0x3 << CCM_CCGRX_CG3_SHIFT) +# define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) +#define CCM_CCGRX_CG4_SHIFT (8) +#define CCM_CCGRX_CG4_MASK (0x3 << CCM_CCGRX_CG4_SHIFT) +# define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) +#define CCM_CCGRX_CG5_SHIFT (10) +#define CCM_CCGRX_CG5_MASK (0x3 << CCM_CCGRX_CG5_SHIFT) +# define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) +#define CCM_CCGRX_CG6_SHIFT (12) +#define CCM_CCGRX_CG6_MASK (0x3 << CCM_CCGRX_CG6_SHIFT) +# define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) +#define CCM_CCGRX_CG7_SHIFT (14) +#define CCM_CCGRX_CG7_MASK (0x3 << CCM_CCGRX_CG7_SHIFT) +# define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) +#define CCM_CCGRX_CG8_SHIFT (16) +#define CCM_CCGRX_CG8_MASK (0x3 << CCM_CCGRX_CG8_SHIFT) +# define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) +#define CCM_CCGRX_CG9_SHIFT (18) +#define CCM_CCGRX_CG9_MASK (0x3 << CCM_CCGRX_CG9_SHIFT) +# define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) +#define CCM_CCGRX_CG10_SHIFT (20) +#define CCM_CCGRX_CG10_MASK (0x3 << CCM_CCGRX_CG10_SHIFT) +# define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) +#define CCM_CCGRX_CG11_SHIFT (22) +#define CCM_CCGRX_CG11_MASK (0x3 << CCM_CCGRX_CG11_SHIFT) +# define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) +#define CCM_CCGRX_CG12_SHIFT (24) +#define CCM_CCGRX_CG12_MASK (0x3 << CCM_CCGRX_CG12_SHIFT) +# define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) +#define CCM_CCGRX_CG13_SHIFT (26) +#define CCM_CCGRX_CG13_MASK (0x3 << CCM_CCGRX_CG13_SHIFT) +# define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) +#define CCM_CCGRX_CG14_SHIFT (28) +#define CCM_CCGRX_CG14_MASK (0x3 << CCM_CCGRX_CG14_SHIFT) +# define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) +#define CCM_CCGRX_CG15_SHIFT (30) +#define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) +# define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) + +/* Macros used by imxrt_periphclks.h */ + +#define CCM_CCGR_GPIO2 IMXRT_CCM_CCGR0, 15 +#define CCM_CCGR_LPUART2 IMXRT_CCM_CCGR0, 14 +#define CCM_CCGR_GPT2_SERIAL IMXRT_CCM_CCGR0, 13 +#define CCM_CCGR_GPT2_BUS IMXRT_CCM_CCGR0, 12 +#define CCM_CCGR_TRACE IMXRT_CCM_CCGR0, 11 +#define CCM_CCGR_CAN2_SERIAL IMXRT_CCM_CCGR0, 10 +#define CCM_CCGR_CAN2 IMXRT_CCM_CCGR0, 9 +#define CCM_CCGR_CAN1_SERIAL IMXRT_CCM_CCGR0, 8 +#define CCM_CCGR_CAN1 IMXRT_CCM_CCGR0, 7 +#define CCM_CCGR_LPUART3 IMXRT_CCM_CCGR0, 6 +#define CCM_CCGR_DCP IMXRT_CCM_CCGR0, 5 +#define CCM_CCGR_MQS IMXRT_CCM_CCGR0, 2 +#define CCM_CCGR_AIPS_TZ2 IMXRT_CCM_CCGR0, 1 +#define CCM_CCGR_AIPS_TZ1 IMXRT_CCM_CCGR0, 0 + +#define CCM_CCGR_CSU IMXRT_CCM_CCGR1, 14 +#define CCM_CCGR_GPIO1 IMXRT_CCM_CCGR1, 13 +#define CCM_CCGR_LPUART4 IMXRT_CCM_CCGR1, 12 +#define CCM_CCGR_GPT_SERIAL IMXRT_CCM_CCGR1, 11 +#define CCM_CCGR_GPT_BUS IMXRT_CCM_CCGR1, 10 +#define CCM_CCGR_ADC1 IMXRT_CCM_CCGR1, 8 +#define CCM_CCGR_AOI2 IMXRT_CCM_CCGR1, 7 +#define CCM_CCGR_PIT IMXRT_CCM_CCGR1, 6 +#define CCM_CCGR_ENET IMXRT_CCM_CCGR1, 5 +#define CCM_CCGR_ADC2 IMXRT_CCM_CCGR1, 4 +#define CCM_CCGR_LPSPI4 IMXRT_CCM_CCGR1, 3 +#define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 +#define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 +#define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 + +#define CCM_CCGR_PXP IMXRT_CCM_CCGR2, 15 +#define CCM_CCGR_LCD IMXRT_CCM_CCGR2, 14 +#define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 +#define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 +#define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 +#define CCM_CCGR_IPMUX3 IMXRT_CCM_CCGR2, 10 +#define CCM_CCGR_IPMUX2 IMXRT_CCM_CCGR2, 9 +#define CCM_CCGR_IPMUX1 IMXRT_CCM_CCGR2, 8 +#define CCM_CCGR_XBAR3 IMXRT_CCM_CCGR2, 7 +#define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 +#define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 +#define CCM_CCGR_LPI2C2 IMXRT_CCM_CCGR2, 4 +#define CCM_CCGR_LPI2C1 IMXRT_CCM_CCGR2, 3 +#define CCM_CCGR_IOMUXC_SNVS IMXRT_CCM_CCGR2, 2 +#define CCM_CCGR_CSI IMXRT_CCM_CCGR2, 1 + +#define CCM_CCGR_IOMUXC_SNVS_GPR IMXRT_CCM_CCGR3, 15 +#define CCM_CCGR_OCRAM IMXRT_CCM_CCGR3, 14 +#define CCM_CCGR_ACMP4 IMXRT_CCM_CCGR3, 13 +#define CCM_CCGR_ACMP3 IMXRT_CCM_CCGR3, 12 +#define CCM_CCGR_ACMP2 IMXRT_CCM_CCGR3, 11 +#define CCM_CCGR_ACMP1 IMXRT_CCM_CCGR3, 10 +#define CCM_CCGR_FLEXRAM IMXRT_CCM_CCGR3, 9 +#define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 +#define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 +#define CCM_CCGR_GPIO4 IMXRT_CCM_CCGR3, 6 +#define CCM_CCGR_LCDIF_PIX IMXRT_CCM_CCGR3, 5 +#define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 +#define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 +#define CCM_CCGR_SEMC IMXRT_CCM_CCGR3, 2 +#define CCM_CCGR_LPUART5 IMXRT_CCM_CCGR3, 1 +#define CCM_CCGR_FLEXIO2 IMXRT_CCM_CCGR3, 0 + +#define CCM_CCGR_ENC4 IMXRT_CCM_CCGR4, 15 +#define CCM_CCGR_ENC3 IMXRT_CCM_CCGR4, 14 +#define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 +#define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 +#define CCM_CCGR_PWM4 IMXRT_CCM_CCGR4, 11 +#define CCM_CCGR_PWM3 IMXRT_CCM_CCGR4, 10 +#define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 +#define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 +#define CCM_CCGR_SIM_EMS IMXRT_CCM_CCGR4, 7 +#define CCM_CCGR_SIM_M IMXRT_CCM_CCGR4, 6 +#define CCM_CCGR_TSC_DIG IMXRT_CCM_CCGR4, 5 +#define CCM_CCGR_SIM_M7 IMXRT_CCM_CCGR4, 4 +#define CCM_CCGR_BEE IMXRT_CCM_CCGR4, 3 +#define CCM_CCGR_IOMUXC_GPR IMXRT_CCM_CCGR4, 2 +#define CCM_CCGR_IOMUXC IMXRT_CCM_CCGR4, 1 + +#define CCM_CCGR_SNVS_LP IMXRT_CCM_CCGR5, 15 +#define CCM_CCGR_SNVS_HP IMXRT_CCM_CCGR5, 14 +#define CCM_CCGR_LPUART7 IMXRT_CCM_CCGR5, 13 +#define CCM_CCGR_LPUART1 IMXRT_CCM_CCGR5, 12 +#define CCM_CCGR_SAI3 IMXRT_CCM_CCGR5, 11 +#define CCM_CCGR_SAI2 IMXRT_CCM_CCGR5, 10 +#define CCM_CCGR_SAI1 IMXRT_CCM_CCGR5, 9 +#define CCM_CCGR_SIM_MAIN IMXRT_CCM_CCGR5, 8 +#define CCM_CCGR_SPDIF IMXRT_CCM_CCGR5, 7 +#define CCM_CCGR_AIPSTZ4 IMXRT_CCM_CCGR5, 6 +#define CCM_CCGR_WDOG2 IMXRT_CCM_CCGR5, 5 +#define CCM_CCGR_KPP IMXRT_CCM_CCGR5, 4 +#define CCM_CCGR_DMA IMXRT_CCM_CCGR5, 3 +#define CCM_CCGR_WDOG3 IMXRT_CCM_CCGR5, 2 +#define CCM_CCGR_FLEXIO1 IMXRT_CCM_CCGR5, 1 +#define CCM_CCGR_ROM IMXRT_CCM_CCGR5, 0 + +#define CCM_CCGR_TIMER3 IMXRT_CCM_CCGR6, 15 +#define CCM_CCGR_TIMER2 IMXRT_CCM_CCGR6, 14 +#define CCM_CCGR_TIMER1 IMXRT_CCM_CCGR6, 13 +#define CCM_CCGR_LPI2C4_SERIAL IMXRT_CCM_CCGR6, 12 +#define CCM_CCGR_ANADIG IMXRT_CCM_CCGR6, 11 +#define CCM_CCGR_SIM_PER IMXRT_CCM_CCGR6, 10 +#define CCM_CCGR_AIPS_TZ3 IMXRT_CCM_CCGR6, 9 +#define CCM_CCGR_TIMER4 IMXRT_CCM_CCGR6, 8 +#define CCM_CCGR_LPUART8 IMXRT_CCM_CCGR6, 7 +#define CCM_CCGR_TRNG IMXRT_CCM_CCGR6, 6 +#define CCM_CCGR_FLEXSPI IMXRT_CCM_CCGR6, 5 +#define CCM_CCGR_IPMUX4 IMXRT_CCM_CCGR6, 4 +#define CCM_CCGR_DCDC IMXRT_CCM_CCGR6, 3 +#define CCM_CCGR_USDHC2 IMXRT_CCM_CCGR6, 2 +#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1 +#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0 + +/* Module Enable Override Register */ + + /* Bits 0-4: Reserved */ +#define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ +#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Overide clock enable signal from PIT */ +#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Overide clock enable signal from USDHC */ +#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Overide clock enable signal from TRNG */ + /* Bits 10-27: Reserved */ +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */ +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */ + /* Bit 31: Reserved */ + +/* Analog ARM PLL control Register */ + +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider 54-108 */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ARM_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) + /* Bits 7-11 Reserved */ +#define CCM_ANALOG_PLL_ARM_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_ARM_ENABLE (1 << 13) /* Bit 13: Enable the clock output */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_ARM_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-18 Reserved */ +#define CCM_ANALOG_PLL_ARM_PLL_SEL (1 << 39) /* Bit 19: ? */ +#define CCM_ANALOG_PLL_ARM_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog USB1 480MHz PLL Control Register */ + +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x1 << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB1_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB1_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) + /* Bits 2-5 Reserved */ +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ +#define CCM_ANALOG_PLL_USB1_POWER (1 << 12) /* Bit 12: Powers up the PLL */ +#define CCM_ANALOG_PLL_USB1_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ +#define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-30 Reserved */ +#define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog USB2 480MHz PLL Control Register */ + +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB2_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB2_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) + /* Bits 2-5 Reserved */ +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ +#define CCM_ANALOG_PLL_USB2_POWER (1 << 12) /* Bit 12: Powers up the PLL */ +#define CCM_ANALOG_PLL_USB2_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_USB2_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-30 Reserved */ +#define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog System PLL Control Register */ + +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT_20 (0) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT_22 (1) +#define CCM_ANALOG_PLL_SYS_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_SYS_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ +#define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ + /* Bits 19-30 Reserved */ +#define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* 528MHz System PLL Spread Spectrum Register */ + +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0) /* Bits 0-14: Frequency change step */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) +# define CCM_ANALOG_PLL_SYS_SS_STEP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE (1 << 15) /* Bit 15: Enable bit */ +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (0) /* Bits 16-31: Frequency change */ +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) +# define CCM_ANALOG_PLL_SYS_SS_STOP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) + +/* Numerator of 528MHz System PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_SYS_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) + /* Bits 30-31: Reserved */ + +/* Denominator of 528MHz System PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_SYS_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ + +/* Analog Audio PLL control Register */ + +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) + /* Bits 7-11: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) + /* Bits 21-30: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Numerator of Audio PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) +/* Bits 30-31: Reserved */ + +/* Denominator of Audio PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ +/* Analog Video PLL control Register */ + +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) + /* Bits 7-11: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_VIDEO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) + /* Bits 21-30: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Numerator of Video PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) + /* Bits 30-31: Reserved */ + +/* Denominator of Video PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ + +/* Analog ENET PLL Control Register */ + +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2) /* Bits 0-1: Controls the frequency of the ethernet1 reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) + /* Bits 4-11: Reserved */ +#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */ + +#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ + +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD0_STABLE (6) /* Bit 6: */ +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD1_STABLE (14) /* Bit 14: */ +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD2_STABLE (22) /* Bit 22: */ +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD3_STABLE (30) /* Bit 30: */ +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ + +/* 528MHz Clock (PLL2) Phase Fractional Divider Control */ + +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD0_STABLE (6) /* Bit 6: */ +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD1_STABLE (14) /* Bit 14: */ +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD2_STABLE (22) /* Bit 22: */ +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD3_STABLE (30) /* Bit 30: */ +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ + +/* Miscellaneous Register 0 */ + +#define CCM_ANALOG_MISC0_REFTOP_PWD (1 << 0) /* Bit 0: Control bit to power-down the analog bandgap reference circuitry */ + /* Bits 1-2: Reserved */ +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF (1 << 2) /* Bit 3: Control bit to disable the self-bias circuit in the analog bandgap */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4) /* Bits 4-6: VBG (PMU) */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x3 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) +# define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP (1 << 7) /* Bit 7: Status bit that signals the analog bandgap voltage is up and stable */ + /* Bits 8-9: Reserved */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10) /* Bits 10-11: Configure the analog behavior in stop mode */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) +# define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS (1 << 12) /* Bit 12: This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */ +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13) /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */ +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT) +# define CCM_ANALOG_MISC0_OSC_I(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT) +#define CCM_ANALOG_MISC0_OSC_XTALOK (1 << 15) /* Bit 15: bit that signals 24-MHz crystal oscillator is stable */ +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN (1 << 16) /* Bit 16: enables the detector that signals 24MHz crystal oscillator is stable */ + /* Bits 17-24: Reserved */ +#define CCM_ANALOG_MISC0_CLKGATE_CTRL (1 << 25) /* Bit 25: This bit allows disabling the clock gate */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26) /* Bits 26-28: delay powering up the XTAL 24MHz */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) +# define CCM_ANALOG_MISC0_CLKGATE_DELAY(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE (1 << 29) /* Bit 29: which chip source is being used for the rtc clock */ +#define CCM_ANALOG_MISC0_XTAL_24M_PWD (1 << 30) /* Bit 30: power down the 24M crystal oscillator if set true */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_1 (0 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_2 (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ + +/* Miscellaneous Register 1 */ + +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0) /* Bits 0-4: This field selects the clk to be routed to anaclk1/1b */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1f << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ARM_PLL ((uint32_t)(0) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SYS_PLL ((uint32_t)(1) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD4 ((uint32_t)(2) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD5 ((uint32_t)(3) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD6 ((uint32_t)(4) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD7 ((uint32_t)(5) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_AUDIO_PLL ((uint32_t)(6) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_VIDEO_PLL ((uint32_t)(7) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ETHERNET_REF ((uint32_t)(9) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB1_PLL ((uint32_t)(12) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB2_PLL ((uint32_t)(13) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD0 ((uint32_t)(14) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD1 ((uint32_t)(15) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD2 ((uint32_t)(16) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD3 ((uint32_t)(17) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_XTAL ((uint32_t)(18) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) + /* Bits 5-9: Reserved */ +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN (1 << 10) /* Bit 10: This enables the LVDS output buffer for anaclk1/1b */ + /* Bit 11: Reserved */ +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN (1 << 12) /* Bit 12: This enables the LVDS input buffer for anaclk1/1b */ + /* Bits 13-15: Reserved */ +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ + /* Bits 18-26: Reserved */ +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC (1 << 27) /* Bit 27: temperature sensor panic interrupt */ +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW (1 << 28) /* Bit 28: temperature sensor low interrupt */ +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH (1 << 29) /* Bit 29: temperature sensor high interrupt */ +#define CCM_ANALOG_MISC1_IRQ_ANA_BO (1 << 30) /* Bit 30: analog regulator brownout interrupt */ +#define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ + +/* Miscellaneous Register 2 */ + +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */ + /* Bit 4: Reserved */ +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ +#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ + /* Bit 12: Reserved */ +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ + +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ + /* Bit 20: Reserved */ +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) + +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) +# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt105x_dmamux.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_dmamux.h similarity index 100% rename from arch/arm/src/imxrt/chip/imxrt105x_dmamux.h rename to arch/arm/src/imxrt/chip/rt105x/imxrt105x_dmamux.h diff --git a/arch/arm/src/imxrt/chip/imxrt105x_gpio.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_gpio.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt105x_gpio.h rename to arch/arm/src/imxrt/chip/rt105x/imxrt105x_gpio.h index c2dea414066..2970ac4224c 100644 --- a/arch/arm/src/imxrt/chip/imxrt105x_gpio.h +++ b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_gpio.h @@ -1,5 +1,5 @@ /******************************************************************************************** - * arch/arm/src/imxrt/imxrt105x_gpio.h + * arch/arm/src/imxrt/rt105x/imxrt105x_gpio.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_iomuxc.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h rename to arch/arm/src/imxrt/chip/rt105x/imxrt105x_iomuxc.h index e079de8cfeb..6666f7a3f8e 100644 --- a/arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h +++ b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_iomuxc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/imxrt/imxrt105x_iomuxc.h + * arch/arm/src/imxrt/rt105x/imxrt105x_iomuxc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt105x_memorymap.h rename to arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h index fe0ed3fa189..1ab9d130d39 100644 --- a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h +++ b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h + * arch/arm/src/imxrt/chip/rt105x/imxrt105x_memorymap.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/imxrt105x_pinmux.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt105x_pinmux.h rename to arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h index 089b54365ca..59955e2183a 100644 --- a/arch/arm/src/imxrt/chip/imxrt105x_pinmux.h +++ b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h @@ -1,5 +1,5 @@ /***************************************************************************************************** - * arch/arm/src/imxrt/chip/imxrt105x_pinmux.h + * arch/arm/src/imxrt/chip/rt105x/imxrt105x_pinmux.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/rt105x/imxrt105x_xbar.h b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_xbar.h new file mode 100644 index 00000000000..697972163f6 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt105x/imxrt105x_xbar.h @@ -0,0 +1,386 @@ +/* XBAR Defines for IMXRT1050 */ + +/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ + +#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ +#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02 IMXRT_XBARA1(XBAR_INPUT, 2) /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03 IMXRT_XBARA1(XBAR_INPUT, 3) /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20 IMXRT_XBARA1(XBAR_INPUT, 20) /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21 IMXRT_XBARA1(XBAR_INPUT, 21) /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22 IMXRT_XBARA1(XBAR_INPUT, 22) /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23 IMXRT_XBARA1(XBAR_INPUT, 23) /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24 IMXRT_XBARA1(XBAR_INPUT, 24) /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25 IMXRT_XBARA1(XBAR_INPUT, 25) /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ +#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ +#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ +#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ +#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ +#define IMXRT_XBARA1_IN_RESERVED30 IMXRT_XBARA1(XBAR_INPUT, 30) /* XBARA1_IN30 input is reserved. */ +#define IMXRT_XBARA1_IN_RESERVED31 IMXRT_XBARA1(XBAR_INPUT, 31) /* XBARA1_IN31 input is reserved. */ +#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ +#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ +#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ +#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ +#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ +#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ +#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ +#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 48) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 49) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 50) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 51) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 52) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 53) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 54) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 55) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ +#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ +#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ +#define IMXRT_XBARA1_IN_ENC3_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 62) /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ +#define IMXRT_XBARA1_IN_ENC4_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 63) /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ +#define IMXRT_XBARA1_IN_AOI2_OUT0 IMXRT_XBARA1(XBAR_INPUT, 76) /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */ +#define IMXRT_XBARA1_IN_AOI2_OUT1 IMXRT_XBARA1(XBAR_INPUT, 77) /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */ +#define IMXRT_XBARA1_IN_AOI2_OUT2 IMXRT_XBARA1(XBAR_INPUT, 78) /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */ +#define IMXRT_XBARA1_IN_AOI2_OUT3 IMXRT_XBARA1(XBAR_INPUT, 79) /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ + +/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ + +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ +#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ +#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 24) /* XBARA1_OUT24 output is reserved. */ +#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 25) /* XBARA1_OUT25 output is reserved. */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 52) /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 53) /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 54) /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 55) /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 56) /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 57) /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 58) /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 59) /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 60) /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 61) /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 62) /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 63) /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 64) /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 65) /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */ +#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */ +#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */ +#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */ +#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */ +#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */ +#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */ +#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */ +#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */ +#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */ +#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 76) /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */ +#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 77) /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */ +#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 78) /* XBARA1_OUT78 output assigned to ENC3_INDEX */ +#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 79) /* XBARA1_OUT79 output assigned to ENC3_HOME */ +#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 80) /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */ +#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 81) /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */ +#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 82) /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */ +#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 83) /* XBARA1_OUT83 output assigned to ENC4_INDEX */ +#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 84) /* XBARA1_OUT84 output assigned to ENC4_HOME */ +#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 85) /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 95) /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 96) /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 97) /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 98) /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 99) /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 100) /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 101) /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ +#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ +#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ +#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ +#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ + +/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ + +#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ +#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ +#define IMXRT_XBARB2_IN_RESERVED2 IMXRT_XBARB2(XBAR_INPUT, 2) /* XBARB2_IN2 input is reserved. */ +#define IMXRT_XBARB2_IN_RESERVED3 IMXRT_XBARB2(XBAR_INPUT, 3) /* XBARB2_IN3 input is reserved. */ +#define IMXRT_XBARB2_IN_RESERVED4 IMXRT_XBARB2(XBAR_INPUT, 4) /* XBARB2_IN4 input is reserved. */ +#define IMXRT_XBARB2_IN_RESERVED5 IMXRT_XBARB2(XBAR_INPUT, 5) /* XBARB2_IN5 input is reserved. */ +#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ +#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ +#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ +#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ +#define IMXRT_XBARB2_IN_RESERVED10 IMXRT_XBARB2(XBAR_INPUT, 10) /* XBARB2_IN10 input is reserved. */ +#define IMXRT_XBARB2_IN_RESERVED11 IMXRT_XBARB2(XBAR_INPUT, 11) /* XBARB2_IN11 input is reserved. */ +#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ +#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ +#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ +#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ +#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ +#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ +#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ +#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ +#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ +#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ +#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ +#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ +#define IMXRT_XBARB2_IN_ENC3_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ +#define IMXRT_XBARB2_IN_ENC4_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ + +/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ + +#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ +#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ +#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ +#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ +#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ +#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ +#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ +#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ +#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ +#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ +#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ +#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ +#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ +#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ +#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ +#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ + +/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/ + +#define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */ +#define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */ +#define IMXRT_XBARB3_IN_RESERVED2 IMXRT_XBARB3(XBAR_INPUT, 2) /* XBARB3_IN2 input is reserved. */ +#define IMXRT_XBARB3_IN_RESERVED3 IMXRT_XBARB3(XBAR_INPUT, 3) /* XBARB3_IN3 input is reserved. */ +#define IMXRT_XBARB3_IN_RESERVED4 IMXRT_XBARB3(XBAR_INPUT, 4) /* XBARB3_IN4 input is reserved. */ +#define IMXRT_XBARB3_IN_RESERVED5 IMXRT_XBARB3(XBAR_INPUT, 5) /* XBARB3_IN5 input is reserved. */ +#define IMXRT_XBARB3_IN_ACMP1_OUT IMXRT_XBARB3(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB3_IN6 input. */ +#define IMXRT_XBARB3_IN_ACMP2_OUT IMXRT_XBARB3(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB3_IN7 input. */ +#define IMXRT_XBARB3_IN_ACMP3_OUT IMXRT_XBARB3(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB3_IN8 input. */ +#define IMXRT_XBARB3_IN_ACMP4_OUT IMXRT_XBARB3(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB3_IN9 input. */ +#define IMXRT_XBARB3_IN_RESERVED10 IMXRT_XBARB3(XBAR_INPUT, 10) /* XBARB3_IN10 input is reserved. */ +#define IMXRT_XBARB3_IN_RESERVED11 IMXRT_XBARB3(XBAR_INPUT, 11) /* XBARB3_IN11 input is reserved. */ +#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ +#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ +#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ +#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ +#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ +#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ +#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ +#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ +#define IMXRT_XBARB3_IN_PIT_TRIGGER0 IMXRT_XBARB3(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ +#define IMXRT_XBARB3_IN_PIT_TRIGGER1 IMXRT_XBARB3(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB3(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB3(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB3(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB3(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB3(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB3(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB3(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB3(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ +#define IMXRT_XBARB3_IN_ENC1_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ +#define IMXRT_XBARB3_IN_ENC2_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ +#define IMXRT_XBARB3_IN_ENC3_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ +#define IMXRT_XBARB3_IN_ENC4_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE0 IMXRT_XBARB3(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB3_IN50 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE1 IMXRT_XBARB3(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB3_IN51 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE2 IMXRT_XBARB3(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB3_IN52 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE3 IMXRT_XBARB3(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB3_IN53 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE4 IMXRT_XBARB3(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB3_IN54 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE5 IMXRT_XBARB3(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB3_IN55 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */ + +/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/ + +#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */ +#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */ +#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 2) /* XBARB3_OUT2 output assigned to AOI2_IN02 */ +#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 3) /* XBARB3_OUT3 output assigned to AOI2_IN03 */ +#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 4) /* XBARB3_OUT4 output assigned to AOI2_IN04 */ +#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 5) /* XBARB3_OUT5 output assigned to AOI2_IN05 */ +#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 6) /* XBARB3_OUT6 output assigned to AOI2_IN06 */ +#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 7) /* XBARB3_OUT7 output assigned to AOI2_IN07 */ +#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 8) /* XBARB3_OUT8 output assigned to AOI2_IN08 */ +#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 9) /* XBARB3_OUT9 output assigned to AOI2_IN09 */ +#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 10) /* XBARB3_OUT10 output assigned to AOI2_IN10 */ +#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 11) /* XBARB3_OUT11 output assigned to AOI2_IN11 */ +#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 12) /* XBARB3_OUT12 output assigned to AOI2_IN12 */ +#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 13) /* XBARB3_OUT13 output assigned to AOI2_IN13 */ +#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 14) /* XBARB3_OUT14 output assigned to AOI2_IN14 */ +#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 15) /* XBARB3_OUT15 output assigned to AOI2_IN15 */ diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_ccm.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_ccm.h new file mode 100644 index 00000000000..d9bb263e082 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_ccm.h @@ -0,0 +1,1144 @@ +/************************************************************************************************************ + * arch/arm/src/imxrt/chip/rt106x/imxrt_ccm.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Janne Rosberg + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_CCM_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_CCM_H + +/************************************************************************************************************ + * Included Files + ************************************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/************************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************************/ + +/* Register offsets *****************************************************************************************/ + +#define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ + /* 0x0004 Reserved */ +#define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ +#define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ +#define IMXRT_CCM_CACRR_OFFSET 0x0010 /* CCM Arm Clock Root Register */ +#define IMXRT_CCM_CBCDR_OFFSET 0x0014 /* CCM Bus Clock Divider Register */ +#define IMXRT_CCM_CBCMR_OFFSET 0x0018 /* CCM Bus Clock Multiplexer Register */ +#define IMXRT_CCM_CSCMR1_OFFSET 0x001c /* CCM Serial Clock Multiplexer Register 1 */ +#define IMXRT_CCM_CSCMR2_OFFSET 0x0020 /* CCM Serial Clock Multiplexer Register 2 */ +#define IMXRT_CCM_CSCDR1_OFFSET 0x0024 /* CCM Serial Clock Divider Register 1 */ +#define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ +#define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ +#define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ + /* 0x0034 Reserved */ +#define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ +#define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ + /* 0x0040 Reserved */ + /* 0x0044 Reserved */ +#define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ + /* 0x004c Reserved */ + /* 0x0050 Reserved */ +#define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ + +#define IMXRT_CCM_CISR_OFFSET 0x0058 /* CCM Interrupt Status Register */ +#define IMXRT_CCM_CIMR_OFFSET 0x005c /* CCM Interrupt Mask Register */ +#define IMXRT_CCM_CCOSR_OFFSET 0x0060 /* CCM Clock Output Source Register */ +#define IMXRT_CCM_CGPR_OFFSET 0x0064 /* CCM General Purpose Register */ +#define IMXRT_CCM_CCGR0_OFFSET 0x0068 /* CCM Clock Gating Register 0 */ +#define IMXRT_CCM_CCGR1_OFFSET 0x006c /* CCM Clock Gating Register 1 */ +#define IMXRT_CCM_CCGR2_OFFSET 0x0070 /* CCM Clock Gating Register 2 */ +#define IMXRT_CCM_CCGR3_OFFSET 0x0074 /* CCM Clock Gating Register 3 */ +#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ +#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ +#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ + /* 0x0084 Reserved */ +#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Overide Register */ + +/* Analog */ + +#define IMXRT_CCM_ANALOG_PLL_ARM_OFFSET 0x0000 /* Analog ARM PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET 0x0010 /* Analog USB1 480MHz PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_USB2_OFFSET 0x0020 /* Analog USB2 480MHz PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET 0x0030 /* Analog System PLL Control Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET 0x0040 /* 528MHz System PLL Spread Spectrum Register */ +#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET 0x0050 /* Numerator of 528MHz System PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET 0x0060 /* Denominator of 528MHz System PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET 0x0070 /* Analog Audio PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET 0x0080 /* Numerator of Audio PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET 0x0090 /* Denominator of Audio PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET 0x00a0 /* Analog Video PLL control Register */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET 0x00b0 /* Numerator of Video PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET 0x00c0 /* Denominator of Video PLL Fractional Loop Divider */ +#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET 0x00e0 /* Analog ENET PLL Control Register */ +#define IMXRT_CCM_ANALOG_PFD_480_OFFSET 0x00f0 /* 480MHz Clock (PLL3) Phase Fractional Divider Control */ +#define IMXRT_CCM_ANALOG_PFD_528_OFFSET 0x0100 /* 528MHz Clock (PLL2) Phase Fractional Divider Control */ +#define IMXRT_CCM_ANALOG_MISC0_OFFSET 0x0150 /* Miscellaneous Register 0 */ +#define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ +#define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ + +/* Register addresses ***************************************************************************************/ + +#define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) +#define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) +#define IMXRT_CCM_CCSR (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET) +#define IMXRT_CCM_CACRR (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET) +#define IMXRT_CCM_CBCDR (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET) +#define IMXRT_CCM_CBCMR (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET) +#define IMXRT_CCM_CSCMR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET) +#define IMXRT_CCM_CSCMR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET) +#define IMXRT_CCM_CSCDR1 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET) +#define IMXRT_CCM_CS1CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET) +#define IMXRT_CCM_CS2CDR (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET) +#define IMXRT_CCM_CDCDR (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET) +#define IMXRT_CCM_CSCDR2 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET) +#define IMXRT_CCM_CSCDR3 (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET) +#define IMXRT_CCM_CDHIPR (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET) +#define IMXRT_CCM_CLPCR (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET) +#define IMXRT_CCM_CISR (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET) +#define IMXRT_CCM_CIMR (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET) +#define IMXRT_CCM_CCOSR (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET) +#define IMXRT_CCM_CGPR (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET) +#define IMXRT_CCM_CCGR0 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET) +#define IMXRT_CCM_CCGR1 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET) +#define IMXRT_CCM_CCGR2 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET) +#define IMXRT_CCM_CCGR3 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET) +#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET) +#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET) +#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET) +#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET) + +#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_USB1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_USB2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB2_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_SS (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET) +#define IMXRT_CCM_ANALOG_PLL_ENET (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET) +#define IMXRT_CCM_ANALOG_PFD_480 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET) +#define IMXRT_CCM_ANALOG_PFD_528 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET) +#define IMXRT_CCM_ANALOG_MISC0 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET) +#define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) +#define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) + +/* Helper Macros *********************************************************************************/ + +#define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ + +/* Register bit definitions *********************************************************************************/ + +/* Control Register */ + +#define CCM_CCR_OSCNT_SHIFT (0) /* Bits 0-7: Oscillator ready counter value */ +#define CCM_CCR_OSCNT_MASK (0xff << CCM_CCR_OSCNT_SHIFT) +# define CCM_CCR_OSCNT(n) ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT) + /* Bits 8-11: Reserved */ +#define CCM_CCR_COSC_EN (1 << 12) /* Bit 12: On chip oscillator enable */ + /* Bits 13-20: Reserved */ +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21) /* Bits 21-26: Counter for analog_reg_bypass */ +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT) +# define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) +#define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ + /* Bits 28-31: Reserved */ +/* Status Register */ + +#define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ + /* Bits 1-2: Reserved */ +#define CCM_CSR_CAMP2_READY (3 << 0) /* Bit 3: Status indication of CAMP2 */ + /* Bit 4: Reserved */ +#define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ + /* Bits 6-31: Reserved */ +/* Clock Switcher Register */ + +#define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ + +/* Arm Clock Root Register */ + +#define CCM_CACRR_ARM_PODF_SHIFT (0) /* Bits 0-2: Divider for ARM clock root */ +#define CCM_CACRR_ARM_PODF_MASK (0x3 << CCM_CACRR_ARM_PODF_SHIFT) +# define CCM_CACRR_ARM_PODF(n) ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT) + +/* Bus Clock Divider Register */ + + /* Bits 0-5: Reserved */ +#define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3 (1 << 7) /* Bit 7: PLL3 PFD1 will be selected */ +#define CCM_CBCDR_IPG_PODF_SHIFT (8) /* Bits 8-9: Divider for ipg podf */ +#define CCM_CBCDR_IPG_PODF_MASK (0x3 << CCM_CBCDR_IPG_PODF_SHIFT) +# define CCM_CBCDR_IPG_PODF(n) ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT) +#define CCM_CBCDR_AHB_PODF_SHIFT (10) /* Bits 10-12: Divider for AHB PODF */ +#define CCM_CBCDR_AHB_PODF_MASK (0x3 << CCM_CBCDR_AHB_PODF_SHIFT) +# define CCM_CBCDR_AHB_PODF(n) ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT) + /* Bits 13-15: Reserved */ +#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ +#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT) +# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) + /* Bits 19-24: Reserved */ +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCDR_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) +# define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) + + /* Bit 26: Reserved */ +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) +# define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + /* Bits 30-31: Reserved */ + +/* Bus Clock Multiplexer Register */ + + /* Bits 0-3: Reserved */ +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1 ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) +# define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) + /* Bits 6-11: Reserved */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for Trace clock multiplexer */ +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) +# define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) + /* Bits 16-17: Reserved */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 (1) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 (2) +# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1 (3) + /* Bits 20-22: Reserved */ +#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */ +#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT) +# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ +#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) +# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) + +/* Serial Clock Multiplexer Register 1 */ + +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) +# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6) /* Bit 6: Selector for the perclk clock multiplexer */ +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) +# define CCM_CSCMR1_PERCLK_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT) +# define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0) +# define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK (1) + /* Bits 7-9: Reserved */ +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for sai1 clock multiplexer */ +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI1_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for sai2 clock multiplexer */ +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI2_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for sai3 clock multiplexer */ +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2 ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL5 ((uint32_t)(1) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +# define CCM_CSCMR1_SAI3_CLK_SEL_PLL4 ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT) +#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ +# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2 (0 << 16) /* derive clock from PLL2 PFD2 */ +# define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0 (1 << 16) /* derive clock from PLL2 PFD0 */ +#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ +# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2 (0 << 17) /* derive clock from PLL2 PFD2 */ +# define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0 (1 << 17) /* derive clock from PLL2 PFD0 */ + /* Bits 18-22: Reserved */ +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23) /* Bits 23-25: Divider for flexspi clock root */ +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) +# define CCM_CSCMR1_FLEXSPI_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT) + /* Bits 26-28: Reserved */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29) /* Bits 29-30: Selector for flexspi clock multiplexer */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) +# define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) + /* Bit 31: Reserved */ + +/* Serial Clock Multiplexer Register 2 */ + +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) +# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for FlexCAN clock multiplexer */ +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60 ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) +# define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80 ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT) + /* Bits 10-18: Reserved */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for flexio2 clock multiplexer */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) +# define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT) + /* Bits 21-31: Reserved */ + +/* Serial Clock Divider Register 1 */ + +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) +# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) +#define CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Bit 6: Selector for the UART clock multiplexer */ +# define CCM_CSCDR1_UART_CLK_SEL_PLL3_80 (0 << 6) /* derive clock from pll3_80m */ +# define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK (1 << 6) /* derive clock from osc_clk */ + /* Bits 7-10: Reserved */ +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) +# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) + /* Bits 14-15: Reserved */ +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) +# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) + /* Bits 19-24: Reserved */ +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25) /* Bits 25-27: Divider for trace clock */ +#define CCM_CSCDR1_TRACE_PODF_MASK (0x7 << CCM_CSCDR1_TRACE_PODF_SHIFT) +# define CCM_CSCDR1_TRACE_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT) + /* Bits 28-31: Reserved */ + +/* Clock Divider Register 1 */ + +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai1 clock podf */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) +# define CCM_CS1CDR_SAI1_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai1 clock pred */ +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) +# define CCM_CS1CDR_SAI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for flexio2 clock */ +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) +# define CCM_CS1CDR_FLEXIO2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT) + /* Bits 12-15: Reserved */ +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for sai3 clock podf */ +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) +# define CCM_CS1CDR_SAI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for sai3 clock pred */ +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) +# define CCM_CS1CDR_SAI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for flexio2 clock */ +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) +# define CCM_CS1CDR_FLEXIO2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT) + /* Bits 28-31: Reserved */ + +/* Clock Divider Register 2 */ + +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for sai2 clock podf */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) +# define CCM_CS2CDR_SAI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for sai2 clock pred */ +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) +# define CCM_CS2CDR_SAI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT) + +/* D1 Clock Divider Register */ + +#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7) /* Bits 7-8: Selector for flexio1 clock multiplexer */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x3 << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9) /* Bits 9-11: Divider for flexio1 clock podf */ +#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12) /* Bits 12-14: Divider for flexio1 clock pred */ +#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7 << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) +# define CCM_CDCDR_FLEXIO1_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT) + /* Bits 15-19: Reserved */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4 ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL5 ((uint32_t)(2) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) +# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) + +/* Serial Clock Divider Register 2 */ + + /* Bits 0-8: Reserved */ +#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for LCDIF root clock multiplexer */ +#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_LCDIF ((uint32_t)(0) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI0_CLK ((uint32_t)(1) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI1_CLK ((uint32_t)(2) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI0_CLK ((uint32_t)(3) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI1_CLK ((uint32_t)(4) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) +#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12) /* Bits 12-14: Pre-divider for lcdif clock */ +#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << CCM_CSCDR2_LCDIF_PRED_SHIFT) +# define CCM_CSCDR2_LCDIF_PRED(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRED_SHIFT) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for lcdif root clock pre-multiplexer */ +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2 ((uint32_t)(0) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD3 ((uint32_t)(1) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 ((uint32_t)(2) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD0 ((uint32_t)(3) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD1 ((uint32_t)(4) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +# define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD1 ((uint32_t)(5) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) +#define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ +# define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ +# define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for lpi2c clock podf */ +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) +# define CCM_CSCDR2_LPI2C_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT) + /* Bits 25-31: Reserved */ + +/* Serial Clock Divider Register 3 */ + + /* Bits 0-8: Reserved */ +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9) /* Bits 9-10: Selector for csi_mclk multiplexer */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_CLK ((uint32_t)(0) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL2_PFD2 ((uint32_t)(1) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_120M ((uint32_t)(2) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +# define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_PFD1 ((uint32_t)(3) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11) /* Bits 11-13: Post divider for csi_mclk */ +#define CCM_CSCDR3_CSI_PODF_MASK (0x3 << CCM_CSCDR3_CSI_PODF_SHIFT) +# define CCM_CSCDR3_CSI_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_PODF_SHIFT) + +/* Divider Handshake In-Process Register */ + +#define CCM_CDHIPR_SEMC_PODF_BUSY (1 << 0) /* Bit 0: Busy indicator for semc_podf */ +#define CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) /* Bit 1: Busy indicator for ahb_podf */ + /* Bit 2: Reserved */ +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) /* Bit 3: Busy indicator for periph2_clk_sel mux control */ + /* Bit 4: Reserved */ +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) /* Bit 5: Busy indicator for periph_clk_sel mux control */ + /* Bits 6-15: Reserved */ +#define CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) /* Bit 16: Busy indicator for arm_podf */ + /* Bits 17-31: Reserved */ + +/* Low Power Control Register */ + +#define CCM_CLPCR_LPM_SHIFT (0) /* Bits 0-1: Setting the low power mode */ +#define CCM_CLPCR_LPM_MASK (0x3 << CCM_CLPCR_LPM_SHIFT) +# define CCM_CLPCR_LPM(n) ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT) +# define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ +# define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ +# define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ + /* Bits 2-4: Reserved */ +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ +#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ +#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ +#define CCM_CLPCR_VSTBY (1 << 8) /* Bit 8: Voltage standby request bit */ +#define CCM_CLPCR_STBY_COUNT_SHIFT (9) /* Bits 9-10: Standby counter definition */ +#define CCM_CLPCR_STBY_COUNT_MASK (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT) +# define CCM_CLPCR_STBY_COUNT(n) ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT) +#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: On chip oscillator power down */ + /* Bits 12-18: Reserved */ +#define CCM_CLPCR_BYPASS_LPM_HS1 (1 << 19) /* Bit 19: Bypass low power mode handshake */ + /* Bit 20: Reserved */ +#define CCM_CLPCR_BYPASS_LPM_HS0 (1 << 21) /* Bit 21: Bypass low power mode handshake */ +#define CCM_CLPCR_MASK_CORE0_WFI (1 << 22) /* Bit 22: Mask WFI of core0 for entering low power mode */ + /* Bits 23-25: Reserved */ +#define CCM_CLPCR_MASK_SCU_IDLE (1 << 26) /* Bit 26: Mask SCU IDLE for entering low power mode */ +#define CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) /* Bit 27: Mask L2CC IDLE for entering low power mode */ + /* Bits 28-31: Reserved */ + +/* Interrupt Status Register */ + +#define CCM_CISR_LRF_PLL (1 << 0) /* Bit 0: CCM irq2, lock of all enabled and not bypassed PLLs */ + /* Bits 1-5: Reserved */ +#define CCM_CISR_COSC_READY (1 << 6) /* Bit 6: CCM irq2, on board oscillator ready */ + /* Bits 7-16: Reserved */ +#define CCM_CISR_SEMC_PODF_LOADED (1 << 17) /* Bit 17: CCM irq1, frequency change of semc_podf */ + /* Bit 18: Reserved */ +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: CCM irq1, frequency change of periph2_clk_sel */ +#define CCM_CISR_AHB_PODF_LOADED (1 << 20) /* Bit 20: CCM irq1, frequency change of ahb_podf */ + /* Bit 21: Reserved */ +#define CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: CCM irq1, update of periph_clk_sel */ + /* Bits 23-25: Reserved */ +#define CCM_CISR_ARM_PODF_LOADED (1 << 26) /* Bit 26: CCM irq1, frequency change of arm_podf */ + /* Bits 27-31: Reserved */ + +/* Interrupt Mask Register */ + +#define CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Bit 0: mask interrupt generation due to lrf of PLLs */ + /* Bits 1-5: Reserved */ +#define CCM_CIMR_MASK_COSC_READY (1 << 6) /* Bit 6: mask interrupt generation due to on board oscillator ready */ + /* Bits 7-16: Reserved */ +#define CCM_CIMR_MASK_SEMC_PODF_LOADED (1 << 17) /* Bit 17: mask interrupt generation due to frequency change of semc_podf */ + /* Bit 18: Reserved */ +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) /* Bit 19: mask interrupt generation due to update of periph2_clk_sel */ +#define CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) /* Bit 20: mask interrupt generation due to frequency change of ahb_podf */ + /* Bit 21: Reserved */ +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) /* Bit 22: mask interrupt generation due to update of periph_clk_sel */ + /* Bits 23-25: Reserved */ +#define CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) /* Bit 26: mask interrupt generation due to frequency change of arm_podf */ + /* Bits 27-31: Reserved */ + +/* Clock Output Source Register */ + +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_SEMC_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_ENC_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_LCDIF_PIX_CLK ((uint32_t)(10) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_AHB_CLK ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_IPG_CLK ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PER_CLK ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO1_SEL_SHIFT) +# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ +#define CCM_CCOSR_CLKO1_DIV_MASK (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT) +# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) +#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ +#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ + /* Bits 9-15: Reserved */ +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK ((uint32_t)(5) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_CSI_CORE ((uint32_t)(11) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_OSC_CLK ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI1_CLK ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI2_CLK ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SAI3_CLK ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_CAN_CLK ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_UART_CLK ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT) +# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_DIV_MASK (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT) +# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) +#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ + /* Bits 25-31: Reserved */ + +/* General Purpose Register */ + +#define CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Bit 0: Defines clock division of clock for stby_count */ + /* Bits 1-3: Reserved */ +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) /* Bit 4: allow fuse programing */ + /* Bits 5-13: Reserved */ +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14) /* Bits 14-15: System memory DS control */ +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) +# define CCM_CGPR_SYS_MEM_DS_CTRL(n) ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT) +#define CCM_CGPR_FPL (1 << 16) /* Bit 16: Fast PLL enable */ +#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) /* Bit 17: Control for the Deep Sleep signal to the ARM Platform memories */ + /* Bits 18-31: Reserved */ + +/* Clock Gating Register 0-6 */ + +#define CCM_CG_OFF (0) /* Clock is off during all modes */ +#define CCM_CG_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ +#define CCM_CG_ALL (3) /* Clock is on during all modes, except STOP mode. */ + +#define CCM_CCGRX_CG_SHIFT(r) ((r) << 1) +#define CCM_CCGRX_CG_MASK(r) (0x3 << CCM_CCGRX_CG_SHIFT(r)) +# define CCM_CCGRX_CG(r,v) ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r)) + +#define CCM_CCGRX_CG0_SHIFT (0) +#define CCM_CCGRX_CG0_MASK (0x3 << CCM_CCGRX_CG0_SHIFT) +# define CCM_CCGRX_CG0(n) ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT) +#define CCM_CCGRX_CG1_SHIFT (2) +#define CCM_CCGRX_CG1_MASK (0x3 << CCM_CCGRX_CG1_SHIFT) +# define CCM_CCGRX_CG1(n) ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT) +#define CCM_CCGRX_CG2_SHIFT (4) +#define CCM_CCGRX_CG2_MASK (0x3 << CCM_CCGRX_CG2_SHIFT) +# define CCM_CCGRX_CG2(n) ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT) +#define CCM_CCGRX_CG3_SHIFT (6) +#define CCM_CCGRX_CG3_MASK (0x3 << CCM_CCGRX_CG3_SHIFT) +# define CCM_CCGRX_CG3(n) ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT) +#define CCM_CCGRX_CG4_SHIFT (8) +#define CCM_CCGRX_CG4_MASK (0x3 << CCM_CCGRX_CG4_SHIFT) +# define CCM_CCGRX_CG4(n) ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT) +#define CCM_CCGRX_CG5_SHIFT (10) +#define CCM_CCGRX_CG5_MASK (0x3 << CCM_CCGRX_CG5_SHIFT) +# define CCM_CCGRX_CG5(n) ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT) +#define CCM_CCGRX_CG6_SHIFT (12) +#define CCM_CCGRX_CG6_MASK (0x3 << CCM_CCGRX_CG6_SHIFT) +# define CCM_CCGRX_CG6(n) ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT) +#define CCM_CCGRX_CG7_SHIFT (14) +#define CCM_CCGRX_CG7_MASK (0x3 << CCM_CCGRX_CG7_SHIFT) +# define CCM_CCGRX_CG7(n) ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT) +#define CCM_CCGRX_CG8_SHIFT (16) +#define CCM_CCGRX_CG8_MASK (0x3 << CCM_CCGRX_CG8_SHIFT) +# define CCM_CCGRX_CG8(n) ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT) +#define CCM_CCGRX_CG9_SHIFT (18) +#define CCM_CCGRX_CG9_MASK (0x3 << CCM_CCGRX_CG9_SHIFT) +# define CCM_CCGRX_CG9(n) ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT) +#define CCM_CCGRX_CG10_SHIFT (20) +#define CCM_CCGRX_CG10_MASK (0x3 << CCM_CCGRX_CG10_SHIFT) +# define CCM_CCGRX_CG10(n) ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT) +#define CCM_CCGRX_CG11_SHIFT (22) +#define CCM_CCGRX_CG11_MASK (0x3 << CCM_CCGRX_CG11_SHIFT) +# define CCM_CCGRX_CG11(n) ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT) +#define CCM_CCGRX_CG12_SHIFT (24) +#define CCM_CCGRX_CG12_MASK (0x3 << CCM_CCGRX_CG12_SHIFT) +# define CCM_CCGRX_CG12(n) ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT) +#define CCM_CCGRX_CG13_SHIFT (26) +#define CCM_CCGRX_CG13_MASK (0x3 << CCM_CCGRX_CG13_SHIFT) +# define CCM_CCGRX_CG13(n) ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT) +#define CCM_CCGRX_CG14_SHIFT (28) +#define CCM_CCGRX_CG14_MASK (0x3 << CCM_CCGRX_CG14_SHIFT) +# define CCM_CCGRX_CG14(n) ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT) +#define CCM_CCGRX_CG15_SHIFT (30) +#define CCM_CCGRX_CG15_MASK (0x3 << CCM_CCGRX_CG15_SHIFT) +# define CCM_CCGRX_CG15(n) ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT) + +/* Macros used by imxrt_periphclks.h */ + +#define CCM_CCGR_GPIO2 IMXRT_CCM_CCGR0, 15 +#define CCM_CCGR_LPUART2 IMXRT_CCM_CCGR0, 14 +#define CCM_CCGR_GPT2_SERIAL IMXRT_CCM_CCGR0, 13 +#define CCM_CCGR_GPT2_BUS IMXRT_CCM_CCGR0, 12 +#define CCM_CCGR_TRACE IMXRT_CCM_CCGR0, 11 +#define CCM_CCGR_CAN2_SERIAL IMXRT_CCM_CCGR0, 10 +#define CCM_CCGR_CAN2 IMXRT_CCM_CCGR0, 9 +#define CCM_CCGR_CAN1_SERIAL IMXRT_CCM_CCGR0, 8 +#define CCM_CCGR_CAN1 IMXRT_CCM_CCGR0, 7 +#define CCM_CCGR_LPUART3 IMXRT_CCM_CCGR0, 6 +#define CCM_CCGR_DCP IMXRT_CCM_CCGR0, 5 +#define CCM_CCGR_MQS IMXRT_CCM_CCGR0, 2 +#define CCM_CCGR_AIPS_TZ2 IMXRT_CCM_CCGR0, 1 +#define CCM_CCGR_AIPS_TZ1 IMXRT_CCM_CCGR0, 0 + +#define CCM_CCGR_CSU IMXRT_CCM_CCGR1, 14 +#define CCM_CCGR_GPIO1 IMXRT_CCM_CCGR1, 13 +#define CCM_CCGR_LPUART4 IMXRT_CCM_CCGR1, 12 +#define CCM_CCGR_GPT_SERIAL IMXRT_CCM_CCGR1, 11 +#define CCM_CCGR_GPT_BUS IMXRT_CCM_CCGR1, 10 +#define CCM_CCGR_ADC1 IMXRT_CCM_CCGR1, 8 +#define CCM_CCGR_AOI2 IMXRT_CCM_CCGR1, 7 +#define CCM_CCGR_PIT IMXRT_CCM_CCGR1, 6 +#define CCM_CCGR_ENET IMXRT_CCM_CCGR1, 5 +#define CCM_CCGR_ADC2 IMXRT_CCM_CCGR1, 4 +#define CCM_CCGR_LPSPI4 IMXRT_CCM_CCGR1, 3 +#define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 +#define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 +#define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 + +#define CCM_CCGR_PXP IMXRT_CCM_CCGR2, 15 +#define CCM_CCGR_LCD IMXRT_CCM_CCGR2, 14 +#define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 +#define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 +#define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 +#define CCM_CCGR_IPMUX3 IMXRT_CCM_CCGR2, 10 +#define CCM_CCGR_IPMUX2 IMXRT_CCM_CCGR2, 9 +#define CCM_CCGR_IPMUX1 IMXRT_CCM_CCGR2, 8 +#define CCM_CCGR_XBAR3 IMXRT_CCM_CCGR2, 7 +#define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 +#define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 +#define CCM_CCGR_LPI2C2 IMXRT_CCM_CCGR2, 4 +#define CCM_CCGR_LPI2C1 IMXRT_CCM_CCGR2, 3 +#define CCM_CCGR_IOMUXC_SNVS IMXRT_CCM_CCGR2, 2 +#define CCM_CCGR_CSI IMXRT_CCM_CCGR2, 1 + +#define CCM_CCGR_IOMUXC_SNVS_GPR IMXRT_CCM_CCGR3, 15 +#define CCM_CCGR_OCRAM IMXRT_CCM_CCGR3, 14 +#define CCM_CCGR_ACMP4 IMXRT_CCM_CCGR3, 13 +#define CCM_CCGR_ACMP3 IMXRT_CCM_CCGR3, 12 +#define CCM_CCGR_ACMP2 IMXRT_CCM_CCGR3, 11 +#define CCM_CCGR_ACMP1 IMXRT_CCM_CCGR3, 10 +#define CCM_CCGR_FLEXRAM IMXRT_CCM_CCGR3, 9 +#define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 +#define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 +#define CCM_CCGR_GPIO4 IMXRT_CCM_CCGR3, 6 +#define CCM_CCGR_LCDIF_PIX IMXRT_CCM_CCGR3, 5 +#define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 +#define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 +#define CCM_CCGR_SEMC IMXRT_CCM_CCGR3, 2 +#define CCM_CCGR_LPUART5 IMXRT_CCM_CCGR3, 1 +#define CCM_CCGR_FLEXIO2 IMXRT_CCM_CCGR3, 0 + +#define CCM_CCGR_ENC4 IMXRT_CCM_CCGR4, 15 +#define CCM_CCGR_ENC3 IMXRT_CCM_CCGR4, 14 +#define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 +#define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 +#define CCM_CCGR_PWM4 IMXRT_CCM_CCGR4, 11 +#define CCM_CCGR_PWM3 IMXRT_CCM_CCGR4, 10 +#define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 +#define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 +#define CCM_CCGR_SIM_EMS IMXRT_CCM_CCGR4, 7 +#define CCM_CCGR_SIM_M IMXRT_CCM_CCGR4, 6 +#define CCM_CCGR_TSC_DIG IMXRT_CCM_CCGR4, 5 +#define CCM_CCGR_SIM_M7 IMXRT_CCM_CCGR4, 4 +#define CCM_CCGR_BEE IMXRT_CCM_CCGR4, 3 +#define CCM_CCGR_IOMUXC_GPR IMXRT_CCM_CCGR4, 2 +#define CCM_CCGR_IOMUXC IMXRT_CCM_CCGR4, 1 + +#define CCM_CCGR_SNVS_LP IMXRT_CCM_CCGR5, 15 +#define CCM_CCGR_SNVS_HP IMXRT_CCM_CCGR5, 14 +#define CCM_CCGR_LPUART7 IMXRT_CCM_CCGR5, 13 +#define CCM_CCGR_LPUART1 IMXRT_CCM_CCGR5, 12 +#define CCM_CCGR_SAI3 IMXRT_CCM_CCGR5, 11 +#define CCM_CCGR_SAI2 IMXRT_CCM_CCGR5, 10 +#define CCM_CCGR_SAI1 IMXRT_CCM_CCGR5, 9 +#define CCM_CCGR_SIM_MAIN IMXRT_CCM_CCGR5, 8 +#define CCM_CCGR_SPDIF IMXRT_CCM_CCGR5, 7 +#define CCM_CCGR_AIPSTZ4 IMXRT_CCM_CCGR5, 6 +#define CCM_CCGR_WDOG2 IMXRT_CCM_CCGR5, 5 +#define CCM_CCGR_KPP IMXRT_CCM_CCGR5, 4 +#define CCM_CCGR_DMA IMXRT_CCM_CCGR5, 3 +#define CCM_CCGR_WDOG3 IMXRT_CCM_CCGR5, 2 +#define CCM_CCGR_FLEXIO1 IMXRT_CCM_CCGR5, 1 +#define CCM_CCGR_ROM IMXRT_CCM_CCGR5, 0 + +#define CCM_CCGR_TIMER3 IMXRT_CCM_CCGR6, 15 +#define CCM_CCGR_TIMER2 IMXRT_CCM_CCGR6, 14 +#define CCM_CCGR_TIMER1 IMXRT_CCM_CCGR6, 13 +#define CCM_CCGR_LPI2C4_SERIAL IMXRT_CCM_CCGR6, 12 +#define CCM_CCGR_ANADIG IMXRT_CCM_CCGR6, 11 +#define CCM_CCGR_SIM_PER IMXRT_CCM_CCGR6, 10 +#define CCM_CCGR_AIPS_TZ3 IMXRT_CCM_CCGR6, 9 +#define CCM_CCGR_TIMER4 IMXRT_CCM_CCGR6, 8 +#define CCM_CCGR_LPUART8 IMXRT_CCM_CCGR6, 7 +#define CCM_CCGR_TRNG IMXRT_CCM_CCGR6, 6 +#define CCM_CCGR_FLEXSPI IMXRT_CCM_CCGR6, 5 +#define CCM_CCGR_IPMUX4 IMXRT_CCM_CCGR6, 4 +#define CCM_CCGR_DCDC IMXRT_CCM_CCGR6, 3 +#define CCM_CCGR_USDHC2 IMXRT_CCM_CCGR6, 2 +#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1 +#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0 + +/* Module Enable Override Register */ + + /* Bits 0-4: Reserved */ +#define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Overide clock enable signal from GPT */ +#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Overide clock enable signal from PIT */ +#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Overide clock enable signal from USDHC */ +#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Overide clock enable signal from TRNG */ + /* Bits 10-27: Reserved */ +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */ +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */ + /* Bit 31: Reserved */ + +/* Analog ARM PLL control Register */ + +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider 54-108 */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ARM_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT) + /* Bits 7-11 Reserved */ +#define CCM_ANALOG_PLL_ARM_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_ARM_ENABLE (1 << 13) /* Bit 13: Enable the clock output */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_ARM_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-18 Reserved */ +#define CCM_ANALOG_PLL_ARM_PLL_SEL (1 << 39) /* Bit 19: ? */ +#define CCM_ANALOG_PLL_ARM_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog USB1 480MHz PLL Control Register */ + +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x1 << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB1_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB1_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) + /* Bits 2-5 Reserved */ +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ +#define CCM_ANALOG_PLL_USB1_POWER (1 << 12) /* Bit 12: Powers up the PLL */ +#define CCM_ANALOG_PLL_USB1_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ +# define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ +#define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-30 Reserved */ +#define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog USB2 480MHz PLL Control Register */ + +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB2_DIV_SELECT_20 ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_USB2_DIV_SELECT_22 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT) + /* Bits 2-5 Reserved */ +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS (1 << 6) /* Bit 6: Enable PLL outputs for USBPHYn */ +#define CCM_ANALOG_PLL_USB2_POWER (1 << 12) /* Bit 12: Powers up the PLL */ +#define CCM_ANALOG_PLL_USB2_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_USB2_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bits 17-30 Reserved */ +#define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Analog System PLL Control Register */ + +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0-1: This field controls the PLL loop divider 20 or 22 */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT_20 (0) +# define CCM_ANALOG_PLL_SYS_DIV_SELECT_22 (1) +#define CCM_ANALOG_PLL_SYS_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_SYS_ENABLE (1 << 13) /* Bit 13: Enable the PLL clock output */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ +# define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ +#define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ + /* Bits 19-30 Reserved */ +#define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* 528MHz System PLL Spread Spectrum Register */ + +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0) /* Bits 0-14: Frequency change step */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) +# define CCM_ANALOG_PLL_SYS_SS_STEP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE (1 << 15) /* Bit 15: Enable bit */ +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (0) /* Bits 16-31: Frequency change */ +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) +# define CCM_ANALOG_PLL_SYS_SS_STOP(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT) + +/* Numerator of 528MHz System PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_SYS_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT) + /* Bits 30-31: Reserved */ + +/* Denominator of 528MHz System PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_SYS_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ + +/* Analog Audio PLL control Register */ + +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) + /* Bits 7-11: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) + /* Bits 21-30: Reserved */ +#define CCM_ANALOG_PLL_AUDIO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Numerator of Audio PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT) +/* Bits 30-31: Reserved */ + +/* Denominator of Audio PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ +/* Analog Video PLL control Register */ + +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT) + /* Bits 7-11: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_VIDEO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV4 ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1 ((uint32_t)(2) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) + /* Bits 21-30: Reserved */ +#define CCM_ANALOG_PLL_VIDEO_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* Numerator of Video PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT) + /* Bits 30-31: Reserved */ + +/* Denominator of Video PLL Fractional Loop Divider Register */ + +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0) /* Bits 0-29: 30 bit numerator (A) */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT) + /* Bits 30-31: Reserved */ + +/* Analog ENET PLL Control Register */ + +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2) /* Bits 0-1: Controls the frequency of the ethernet1 reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) +# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT) + /* Bits 4-11: Reserved */ +#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) +# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ +# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ +#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ + +/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ + +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD0_STABLE (6) /* Bit 6: */ +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD1_STABLE (14) /* Bit 14: */ +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD2_STABLE (22) /* Bit 22: */ +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) +# define CCM_ANALOG_PFD_480_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) +#define CCM_ANALOG_PFD_480_PFD3_STABLE (30) /* Bit 30: */ +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ + +/* 528MHz Clock (PLL2) Phase Fractional Divider Control */ + +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) /* Bits 0-5: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD0_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD0_STABLE (6) /* Bit 6: */ +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE (7) /* Bit 7: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8) /* Bits 8-13: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD1_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD1_STABLE (14) /* Bit 14: */ +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE (15) /* Bit 15: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) /* Bits 8-21: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD2_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD2_STABLE (22) /* Bit 22: */ +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE (23) /* Bit 23: If set to 1, the IO fractional divider clock is off */ +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24) /* Bits 24-29: This field controls the fractional divide value */ +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) +# define CCM_ANALOG_PFD_528_PFD3_FRAC(n) ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT) +#define CCM_ANALOG_PFD_528_PFD3_STABLE (30) /* Bit 30: */ +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE (31) /* Bit 31: If set to 1, the IO fractional divider clock is off */ + +/* Miscellaneous Register 0 */ + +#define CCM_ANALOG_MISC0_REFTOP_PWD (1 << 0) /* Bit 0: Control bit to power-down the analog bandgap reference circuitry */ + /* Bits 1-2: Reserved */ +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF (1 << 2) /* Bit 3: Control bit to disable the self-bias circuit in the analog bandgap */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4) /* Bits 4-6: VBG (PMU) */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x3 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) +# define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP (1 << 7) /* Bit 7: Status bit that signals the analog bandgap voltage is up and stable */ + /* Bits 8-9: Reserved */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10) /* Bits 10-11: Configure the analog behavior in stop mode */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) +# define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS (1 << 12) /* Bit 12: This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */ +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13) /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */ +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT) +# define CCM_ANALOG_MISC0_OSC_I(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT) +#define CCM_ANALOG_MISC0_OSC_XTALOK (1 << 15) /* Bit 15: bit that signals 24-MHz crystal oscillator is stable */ +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN (1 << 16) /* Bit 16: enables the detector that signals 24MHz crystal oscillator is stable */ + /* Bits 17-24: Reserved */ +#define CCM_ANALOG_MISC0_CLKGATE_CTRL (1 << 25) /* Bit 25: This bit allows disabling the clock gate */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26) /* Bits 26-28: delay powering up the XTAL 24MHz */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) +# define CCM_ANALOG_MISC0_CLKGATE_DELAY(n) ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE (1 << 29) /* Bit 29: which chip source is being used for the rtc clock */ +#define CCM_ANALOG_MISC0_XTAL_24M_PWD (1 << 30) /* Bit 30: power down the 24M crystal oscillator if set true */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_1 (0 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_2 (1 << 31) /* Bit 31: Predivider for the source clock of the PLL's */ + +/* Miscellaneous Register 1 */ + +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0) /* Bits 0-4: This field selects the clk to be routed to anaclk1/1b */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1f << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ARM_PLL ((uint32_t)(0) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SYS_PLL ((uint32_t)(1) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD4 ((uint32_t)(2) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD5 ((uint32_t)(3) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD6 ((uint32_t)(4) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD7 ((uint32_t)(5) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_AUDIO_PLL ((uint32_t)(6) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_VIDEO_PLL ((uint32_t)(7) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ETHERNET_REF ((uint32_t)(9) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB1_PLL ((uint32_t)(12) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB2_PLL ((uint32_t)(13) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD0 ((uint32_t)(14) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD1 ((uint32_t)(15) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD2 ((uint32_t)(16) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD3 ((uint32_t)(17) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) +# define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_XTAL ((uint32_t)(18) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT) + /* Bits 5-9: Reserved */ +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN (1 << 10) /* Bit 10: This enables the LVDS output buffer for anaclk1/1b */ + /* Bit 11: Reserved */ +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN (1 << 12) /* Bit 12: This enables the LVDS input buffer for anaclk1/1b */ + /* Bits 13-15: Reserved */ +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ + /* Bits 18-26: Reserved */ +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC (1 << 27) /* Bit 27: temperature sensor panic interrupt */ +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW (1 << 28) /* Bit 28: temperature sensor low interrupt */ +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH (1 << 29) /* Bit 29: temperature sensor high interrupt */ +#define CCM_ANALOG_MISC1_IRQ_ANA_BO (1 << 30) /* Bit 30: analog regulator brownout interrupt */ +#define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ + +/* Miscellaneous Register 2 */ + +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0) /* Bits 0-2: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS (1 << 3) /* Bit 3: Reg0 brownout status bit */ + /* Bit 4: Reserved */ +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ +#define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8) /* Bits 8-10: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS (1 << 11) /* Bit 11: Reg1 brownout status bit */ + /* Bit 12: Reserved */ +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO (1 << 13) /* Bit 13: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG1_OK (1 << 14) /* Bit 14: GPU/VPU supply */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB (1 << 15) /* Bit 15: LSB of Post-divider for Audio PLL */ + +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16) /* Bits 16-18: This field defines the brown out voltage offset */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +# define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS (1 << 19) /* Bit 19: Reg2 brownout status bit */ + /* Bit 20: Reserved */ +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO (1 << 21) /* Bit 21: Enables the brownout detection */ +#define CCM_ANALOG_MISC2_REG2_OK (1 << 22) /* Bit 22: voltage is above the brownout level for the SOC supply */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB (1 << 23) /* Bit 23: MSB of Post-divider for Audio PLL */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24) /* Bits 24-25: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG0_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26) /* Bits 26-27: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG1_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28) /* Bits 28-29: Number of clock periods (24MHz clock) */ +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_64 ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_128 ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_256 ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) +# define CCM_ANALOG_MISC2_REG2_STEP_TIME_512 ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT) + +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30) /* Bits 30-31: Post-divider for video */ +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) +# define CCM_ANALOG_MISC2_VIDEO_DIV(n) ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_CCM_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt106x_dmamux.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt106x_dmamux.h rename to arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h index 52e9e84f296..3e05c859fcb 100644 --- a/arch/arm/src/imxrt/chip/imxrt106x_dmamux.h +++ b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt106x_dmamux.h + * arch/arm/src/imxrt/chip/rt106x/imxrt106x_dmamux.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/imxrt106x_gpio.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_gpio.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt106x_gpio.h rename to arch/arm/src/imxrt/chip/rt106x/imxrt106x_gpio.h index 611ddfe3502..6e732d5ac24 100644 --- a/arch/arm/src/imxrt/chip/imxrt106x_gpio.h +++ b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_gpio.h @@ -1,5 +1,5 @@ /******************************************************************************************** - * arch/arm/src/imxrt/imxrt106x_gpio.h + * arch/arm/src/imxrt/rt106x/imxrt106x_gpio.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_iomuxc.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h rename to arch/arm/src/imxrt/chip/rt106x/imxrt106x_iomuxc.h index 5ec7db7d714..9ec3b043af0 100644 --- a/arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h +++ b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_iomuxc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/imxrt/imxrt_iomuxc.h + * arch/arm/src/imxrt/rt106x/imxrt106x_iomuxc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/imxrt106x_memorymap.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt106x_memorymap.h rename to arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h index 35cdfde5fd6..327dfb9d7f1 100644 --- a/arch/arm/src/imxrt/chip/imxrt106x_memorymap.h +++ b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h + * arch/arm/src/imxrt/chip/rt106x/imxrt106x_memorymap.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/imxrt106x_pinmux.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h similarity index 99% rename from arch/arm/src/imxrt/chip/imxrt106x_pinmux.h rename to arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h index 2a45b60d947..edb3ed25581 100644 --- a/arch/arm/src/imxrt/chip/imxrt106x_pinmux.h +++ b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h @@ -1,5 +1,5 @@ /***************************************************************************************************** - * arch/arm/src/imxrt/chip/imxrt105x_pinmux.h + * arch/arm/src/imxrt/chip/rt106x/imxrt106x_pinmux.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/arch/arm/src/imxrt/chip/rt106x/imxrt106x_xbar.h b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_xbar.h new file mode 100644 index 00000000000..3d697880494 --- /dev/null +++ b/arch/arm/src/imxrt/chip/rt106x/imxrt106x_xbar.h @@ -0,0 +1,386 @@ +/* XBAR Defines for IMXRT1060 */ + +/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ + +#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ +#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02 IMXRT_XBARA1(XBAR_INPUT, 2) /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03 IMXRT_XBARA1(XBAR_INPUT, 3) /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20 IMXRT_XBARA1(XBAR_INPUT, 20) /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21 IMXRT_XBARA1(XBAR_INPUT, 21) /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22 IMXRT_XBARA1(XBAR_INPUT, 22) /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23 IMXRT_XBARA1(XBAR_INPUT, 23) /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24 IMXRT_XBARA1(XBAR_INPUT, 24) /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25 IMXRT_XBARA1(XBAR_INPUT, 25) /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ +#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ +#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ +#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ +#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ +#define IMXRT_XBARA1_IN_RESERVED30 IMXRT_XBARA1(XBAR_INPUT, 30) /* XBARA1_IN30 input is reserved. */ +#define IMXRT_XBARA1_IN_RESERVED31 IMXRT_XBARA1(XBAR_INPUT, 31) /* XBARA1_IN31 input is reserved. */ +#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ +#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ +#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ +#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ +#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ +#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ +#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ +#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 48) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 49) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 50) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 51) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 52) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 53) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 54) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ +#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 55) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ +#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ +#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ +#define IMXRT_XBARA1_IN_ENC3_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 62) /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ +#define IMXRT_XBARA1_IN_ENC4_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 63) /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ +#define IMXRT_XBARA1_IN_AOI2_OUT0 IMXRT_XBARA1(XBAR_INPUT, 76) /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */ +#define IMXRT_XBARA1_IN_AOI2_OUT1 IMXRT_XBARA1(XBAR_INPUT, 77) /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */ +#define IMXRT_XBARA1_IN_AOI2_OUT2 IMXRT_XBARA1(XBAR_INPUT, 78) /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */ +#define IMXRT_XBARA1_IN_AOI2_OUT3 IMXRT_XBARA1(XBAR_INPUT, 79) /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ + +/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ + +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ +#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ +#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ +#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ +#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ +#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 24) /* XBARA1_OUT24 output is reserved. */ +#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 25) /* XBARA1_OUT25 output is reserved. */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 52) /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 53) /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 54) /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 55) /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 56) /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 57) /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 58) /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 59) /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 60) /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 61) /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 62) /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 63) /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 64) /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ +#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 65) /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ +#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */ +#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */ +#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */ +#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */ +#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */ +#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */ +#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */ +#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */ +#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */ +#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */ +#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 76) /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */ +#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 77) /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */ +#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 78) /* XBARA1_OUT78 output assigned to ENC3_INDEX */ +#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 79) /* XBARA1_OUT79 output assigned to ENC3_HOME */ +#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 80) /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */ +#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 81) /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */ +#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 82) /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */ +#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 83) /* XBARA1_OUT83 output assigned to ENC4_INDEX */ +#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 84) /* XBARA1_OUT84 output assigned to ENC4_HOME */ +#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 85) /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 95) /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 96) /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 97) /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 98) /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 99) /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 100) /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */ +#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 101) /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */ +#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ +#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ +#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */ +#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ +#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ +#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ +#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ + +/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ + +#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ +#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ +#define IMXRT_XBARB2_IN_RESERVED2 IMXRT_XBARB2(XBAR_INPUT, 2) /* XBARB2_IN2 input is reserved. */ +#define IMXRT_XBARB2_IN_RESERVED3 IMXRT_XBARB2(XBAR_INPUT, 3) /* XBARB2_IN3 input is reserved. */ +#define IMXRT_XBARB2_IN_RESERVED4 IMXRT_XBARB2(XBAR_INPUT, 4) /* XBARB2_IN4 input is reserved. */ +#define IMXRT_XBARB2_IN_RESERVED5 IMXRT_XBARB2(XBAR_INPUT, 5) /* XBARB2_IN5 input is reserved. */ +#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ +#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ +#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ +#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ +#define IMXRT_XBARB2_IN_RESERVED10 IMXRT_XBARB2(XBAR_INPUT, 10) /* XBARB2_IN10 input is reserved. */ +#define IMXRT_XBARB2_IN_RESERVED11 IMXRT_XBARB2(XBAR_INPUT, 11) /* XBARB2_IN11 input is reserved. */ +#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ +#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ +#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ +#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ +#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ +#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ +#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ +#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ +#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ +#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ +#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ +#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ +#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ +#define IMXRT_XBARB2_IN_ENC3_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ +#define IMXRT_XBARB2_IN_ENC4_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ + +/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ + +#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ +#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ +#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ +#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ +#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ +#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ +#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ +#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ +#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ +#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ +#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ +#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ +#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ +#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ +#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ +#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ + +/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/ + +#define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */ +#define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */ +#define IMXRT_XBARB3_IN_RESERVED2 IMXRT_XBARB3(XBAR_INPUT, 2) /* XBARB3_IN2 input is reserved. */ +#define IMXRT_XBARB3_IN_RESERVED3 IMXRT_XBARB3(XBAR_INPUT, 3) /* XBARB3_IN3 input is reserved. */ +#define IMXRT_XBARB3_IN_RESERVED4 IMXRT_XBARB3(XBAR_INPUT, 4) /* XBARB3_IN4 input is reserved. */ +#define IMXRT_XBARB3_IN_RESERVED5 IMXRT_XBARB3(XBAR_INPUT, 5) /* XBARB3_IN5 input is reserved. */ +#define IMXRT_XBARB3_IN_ACMP1_OUT IMXRT_XBARB3(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB3_IN6 input. */ +#define IMXRT_XBARB3_IN_ACMP2_OUT IMXRT_XBARB3(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB3_IN7 input. */ +#define IMXRT_XBARB3_IN_ACMP3_OUT IMXRT_XBARB3(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB3_IN8 input. */ +#define IMXRT_XBARB3_IN_ACMP4_OUT IMXRT_XBARB3(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB3_IN9 input. */ +#define IMXRT_XBARB3_IN_RESERVED10 IMXRT_XBARB3(XBAR_INPUT, 10) /* XBARB3_IN10 input is reserved. */ +#define IMXRT_XBARB3_IN_RESERVED11 IMXRT_XBARB3(XBAR_INPUT, 11) /* XBARB3_IN11 input is reserved. */ +#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ +#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ +#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ +#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ +#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ +#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ +#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ +#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ +#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ +#define IMXRT_XBARB3_IN_PIT_TRIGGER0 IMXRT_XBARB3(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ +#define IMXRT_XBARB3_IN_PIT_TRIGGER1 IMXRT_XBARB3(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB3(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB3(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB3(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB3(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB3(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB3(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB3(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ +#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB3(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ +#define IMXRT_XBARB3_IN_ENC1_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ +#define IMXRT_XBARB3_IN_ENC2_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ +#define IMXRT_XBARB3_IN_ENC3_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ +#define IMXRT_XBARB3_IN_ENC4_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE0 IMXRT_XBARB3(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB3_IN50 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE1 IMXRT_XBARB3(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB3_IN51 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE2 IMXRT_XBARB3(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB3_IN52 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE3 IMXRT_XBARB3(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB3_IN53 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE4 IMXRT_XBARB3(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB3_IN54 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE5 IMXRT_XBARB3(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB3_IN55 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */ +#define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */ + +/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/ + +#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */ +#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */ +#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 2) /* XBARB3_OUT2 output assigned to AOI2_IN02 */ +#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 3) /* XBARB3_OUT3 output assigned to AOI2_IN03 */ +#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 4) /* XBARB3_OUT4 output assigned to AOI2_IN04 */ +#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 5) /* XBARB3_OUT5 output assigned to AOI2_IN05 */ +#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 6) /* XBARB3_OUT6 output assigned to AOI2_IN06 */ +#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 7) /* XBARB3_OUT7 output assigned to AOI2_IN07 */ +#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 8) /* XBARB3_OUT8 output assigned to AOI2_IN08 */ +#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 9) /* XBARB3_OUT9 output assigned to AOI2_IN09 */ +#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 10) /* XBARB3_OUT10 output assigned to AOI2_IN10 */ +#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 11) /* XBARB3_OUT11 output assigned to AOI2_IN11 */ +#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 12) /* XBARB3_OUT12 output assigned to AOI2_IN12 */ +#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 13) /* XBARB3_OUT13 output assigned to AOI2_IN13 */ +#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 14) /* XBARB3_OUT14 output assigned to AOI2_IN14 */ +#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 15) /* XBARB3_OUT15 output assigned to AOI2_IN15 */ diff --git a/arch/arm/src/imxrt/imxrt102x_daisy.c b/arch/arm/src/imxrt/imxrt102x_daisy.c new file mode 100644 index 00000000000..8d802651e7d --- /dev/null +++ b/arch/arm/src/imxrt/imxrt102x_daisy.c @@ -0,0 +1,5419 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt106x_daisy.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* Based on chip selection this file is included in imxrt_daisy.c */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct imxrt_daisy_t g_daisy_select[] = +{ + /* index:0 GPIO_EMC_00 */ + + { + { + /* Index:0 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:0 Alt:1 GPIO EMC 00 QTIMER2 TIMER0 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), + [ALT1].sel = 0, + + /* Index:0 Alt:2 GPIO EMC 00 LPUART4 CTS B */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_CTS_B_OFFSET), + [ALT2].sel = 0, + + /* Index:0 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:0 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:0 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:0 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:0 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:0 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:0 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:1 GPIO_EMC_01 */ + + { + { + /* Index:1 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:1 Alt:1 GPIO EMC 01 QTIMER2 TIMER1 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), + [ALT1].sel = 0, + + /* Index:1 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:1 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:1 Alt:4 GPIO EMC 01 LPSPI2 PCS0 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), + [ALT4].sel = 0, + + /* Index:1 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:1 Alt:6 GPIO EMC 01 FLEXCAN1 RX */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT6].sel = 0, + + /* Index:1 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:1 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:1 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:2 GPIO_EMC_02 */ + + { + { + /* Index:2 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:2 Alt:1 GPIO EMC 02 QTIMER2 TIMER2 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), + [ALT1].sel = 0, + + /* Index:2 Alt:2 GPIO EMC 02 LPUART4 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), + [ALT2].sel = 0, + + /* Index:2 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:2 Alt:4 GPIO EMC 02 LPSPI2 SDO */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDO_OFFSET), + [ALT4].sel = 0, + + /* Index:2 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:2 Alt:6 GPIO EMC 02 LPI2C1 SCL */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SCL_OFFSET), + [ALT6].sel = 0, + + /* Index:2 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:2 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:2 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:3 GPIO_EMC_03 */ + + { + { + /* Index:3 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:3 Alt:1 GPIO EMC 03 QTIMER2 TIMER3 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), + [ALT1].sel = 0, + + /* Index:3 Alt:2 GPIO EMC 03 LPUART4 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), + [ALT2].sel = 0, + + /* Index:3 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:3 Alt:4 GPIO EMC 03 LPSPI2 SDI */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDI_OFFSET), + [ALT4].sel = 0, + + /* Index:3 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:3 Alt:6 GPIO EMC 03 LPI2C1 SDA */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SDA_OFFSET), + [ALT6].sel = 0, + + /* Index:3 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:3 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:3 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:4 GPIO_EMC_04 */ + + { + { + /* Index:4 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:4 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:4 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:4 Alt:3 GPIO EMC 04 SAI2 TX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:4 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:4 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:4 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:4 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:4 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:4 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:5 GPIO_EMC_05 */ + + { + { + /* Index:5 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:5 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:5 Alt:2 GPIO EMC 05 SPDIF IN */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SPDIF_IN_OFFSET), + [ALT2].sel = 0, + + /* Index:5 Alt:3 GPIO EMC 05 SAI2 TX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), + [ALT3].sel = 1, + + /* Index:5 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:5 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:5 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:5 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:5 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:5 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:6 GPIO_EMC_06 */ + + { + { + /* Index:6 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:6 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:6 Alt:2 GPIO EMC 06 LPUART3 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET), + [ALT2].sel = 0, + + /* Index:6 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:6 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:6 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:6 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:6 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:6 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:6 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:7 GPIO_EMC_07 */ + + { + { + /* Index:7 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:7 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:7 Alt:2 GPIO EMC 07 LPUART3 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_RX_OFFSET), + [ALT2].sel = 0, + + /* Index:7 Alt:3 GPIO EMC 07 SAI2 RX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), + [ALT3].sel = 1, + + /* Index:7 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:7 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:7 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:7 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:7 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:7 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:8 GPIO_EMC_08 */ + + { + { + /* Index:8 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:8 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:8 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:8 Alt:3 GPIO EMC 08 SAI2 RX DATA */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), + [ALT3].sel = 1, + + /* Index:8 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:8 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:8 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:8 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:8 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:8 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:9 GPIO_EMC_09 */ + + { + { + /* Index:9 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:9 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:9 Alt:2 GPIO EMC 09 FLEXCAN2 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT2].sel = 1, + + /* Index:9 Alt:3 GPIO EMC 09 SAI2 RX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:9 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:9 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:9 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:9 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:9 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:9 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:10 GPIO_EMC_10 */ + + { + { + /* Index:10 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:10 Alt:1 GPIO EMC 10 XBAR1 INOUT10 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN10_OFFSET), + [ALT1].sel = 0, + + /* Index:10 Alt:2 GPIO EMC 10 LPI2C4 SDA */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SDA_OFFSET), + [ALT2].sel = 0, + + /* Index:10 Alt:3 GPIO EMC 10 SAI1 TX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].sel = 0, + + /* Index:10 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:10 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:10 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:10 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:10 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:10 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:11 GPIO_EMC_11 */ + + { + { + /* Index:11 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:11 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:11 Alt:2 GPIO EMC 11 LPI2C4 SCL */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SCL_OFFSET), + [ALT2].sel = 0, + + /* Index:11 Alt:3 GPIO EMC 11 SAI1 TX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].sel = 0, + + /* Index:11 Alt:4 GPIO EMC 11 LPSPI2 PCS0 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), + [ALT4].sel = 1, + + /* Index:11 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:11 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:11 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:11 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:11 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:12 GPIO_EMC_12 */ + + { + { + /* Index:12 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:12 Alt:1 GPIO EMC 12 XBAR1 INOUT12 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN12_OFFSET), + [ALT1].sel = 0, + + /* Index:12 Alt:2 GPIO EMC 12 LPUART6 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_TX_OFFSET), + [ALT2].sel = 0, + + /* Index:12 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:12 Alt:4 GPIO EMC 12 LPSPI2 SDO */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDO_OFFSET), + [ALT4].sel = 1, + + /* Index:12 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:12 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:12 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:12 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:12 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:13 GPIO_EMC_13 */ + + { + { + /* Index:13 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:13 Alt:1 GPIO EMC 13 XBAR1 INOUT13 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN13_OFFSET), + [ALT1].sel = 0, + + /* Index:13 Alt:2 GPIO EMC 13 LPUART6 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_RX_OFFSET), + [ALT2].sel = 0, + + /* Index:13 Alt:3 GPIO EMC 13 SAI1 RX DATA00 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].sel = 0, + + /* Index:13 Alt:4 GPIO EMC 13 LPSPI2 SDI */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDI_OFFSET), + [ALT4].sel = 1, + + /* Index:13 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:13 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:13 Alt:7 GPIO EMC 13 CCM PMIC RDY */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT7].sel = 0, + + /* Index:13 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:13 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:14 GPIO_EMC_14 */ + + { + { + /* Index:14 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:14 Alt:1 GPIO EMC 14 XBAR1 INOUT14 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN14_OFFSET), + [ALT1].sel = 1, + + /* Index:14 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:14 Alt:3 GPIO EMC 14 SAI1 RX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:14 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:14 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:14 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:14 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:14 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:14 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:15 GPIO_EMC_15 */ + + { + { + /* Index:15 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:15 Alt:1 GPIO EMC 15 XBAR1 INOUT15 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN15_OFFSET), + [ALT1].sel = 1, + + /* Index:15 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:15 Alt:3 GPIO EMC 15 SAI1 RX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].sel = 1, + + /* Index:15 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:15 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:15 Alt:6 GPIO EMC 15 FLEXCAN1 RX */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT6].sel = 3, + + /* Index:15 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:15 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:15 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:16 GPIO_EMC_16 */ + + { + { + /* Index:16 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:16 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:16 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:16 Alt:3 GPIO EMC 16 SAI2 MCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_MCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:16 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:16 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:16 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:16 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:16 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:16 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:17 GPIO_EMC_17 */ + + { + { + /* Index:17 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:17 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:17 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:17 Alt:3 GPIO EMC 17 SAI3 MCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_MCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:17 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:17 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:17 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:17 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:17 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:17 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:18 GPIO_EMC_18 */ + + { + { + /* Index:18 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:18 Alt:1 GPIO EMC 18 XBAR1 INOUT16 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN16_OFFSET), + [ALT1].sel = 1, + + /* Index:18 Alt:2 GPIO EMC 18 LPI2C2 SDA */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SDA_OFFSET), + [ALT2].sel = 1, + + /* Index:18 Alt:3 GPIO EMC 18 SAI1 RX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].sel = 2, + + /* Index:18 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:18 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:18 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:18 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:18 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:18 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:19 GPIO_EMC_19 */ + + { + { + /* Index:19 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:19 Alt:1 GPIO EMC 19 XBAR1 INOUT17 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), + [ALT1].sel = 1, + + /* Index:19 Alt:2 GPIO EMC 19 LPI2C2 SCL */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SCL_OFFSET), + [ALT2].sel = 1, + + /* Index:19 Alt:3 GPIO EMC 19 SAI1 RX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].sel = 2, + + /* Index:19 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:19 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:19 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:19 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:19 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:19 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:20 GPIO_EMC_20 */ + + { + { + /* Index:20 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:20 Alt:1 GPIO EMC 20 FLEXPWM1 PWMA03 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT1].sel = 1, + + /* Index:20 Alt:2 GPIO EMC 20 LPUART2 CTS B */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), + [ALT2].sel = 1, + + /* Index:20 Alt:3 GPIO EMC 20 SAI1 MCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK_OFFSET), + [ALT3].sel = 3, + + /* Index:20 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:20 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:20 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:20 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:20 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:20 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:21 GPIO_EMC_21 */ + + { + { + /* Index:21 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:21 Alt:1 GPIO EMC 21 FLEXPWM1 PWMB03 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT1].sel = 1, + + /* Index:21 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:21 Alt:3 GPIO EMC 21 SAI1 RX DATA00 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].sel = 2, + + /* Index:21 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:21 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:21 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:21 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:21 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:21 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:22 GPIO_EMC_22 */ + + { + { + /* Index:22 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:22 Alt:1 GPIO EMC 22 FLEXPWM1 PWMA02 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), + [ALT1].sel = 1, + + /* Index:22 Alt:2 GPIO EMC 22 LPUART2 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET), + [ALT2].sel = 1, + + /* Index:22 Alt:3 GPIO EMC 22 SAI1 TX DATA03 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), + [ALT3].sel = 1, + + /* Index:22 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:22 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:22 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:22 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:22 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:22 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:23 GPIO_EMC_23 */ + + { + { + /* Index:23 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:23 Alt:1 GPIO EMC 23 FLEXPWM1 PWMB02 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), + [ALT1].sel = 1, + + /* Index:23 Alt:2 GPIO EMC 23 LPUART2 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_RX_OFFSET), + [ALT2].sel = 1, + + /* Index:23 Alt:3 GPIO EMC 23 SAI1 TX DATA02 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), + [ALT3].sel = 1, + + /* Index:23 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:23 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:23 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:23 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:23 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:23 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:24 GPIO_EMC_24 */ + + { + { + /* Index:24 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:24 Alt:1 GPIO EMC 24 FLEXPWM1 PWMA01 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), + [ALT1].sel = 1, + + /* Index:24 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:24 Alt:3 GPIO EMC 24 SAI1 TX DATA01 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), + [ALT3].sel = 1, + + /* Index:24 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:24 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:24 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:24 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:24 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:24 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:25 GPIO_EMC_25 */ + + { + { + /* Index:25 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:25 Alt:1 GPIO EMC 25 FLEXPWM1 PWMB01 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), + [ALT1].sel = 1, + + /* Index:25 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:25 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:25 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:25 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:25 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:25 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:25 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:25 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:26 GPIO_EMC_26 */ + + { + { + /* Index:26 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:26 Alt:1 GPIO EMC 26 FLEXPWM1 PWMA00 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), + [ALT1].sel = 1, + + /* Index:26 Alt:2 GPIO EMC 26 LPUART8 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET), + [ALT2].sel = 1, + + /* Index:26 Alt:3 GPIO EMC 26 SAI1 TX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].sel = 2, + + /* Index:26 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:26 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:26 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:26 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:26 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:26 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:27 GPIO_EMC_27 */ + + { + { + /* Index:27 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:27 Alt:1 GPIO EMC 27 FLEXPWM1 PWMB00 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), + [ALT1].sel = 1, + + /* Index:27 Alt:2 GPIO EMC 27 LPUART8 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET), + [ALT2].sel = 1, + + /* Index:27 Alt:3 GPIO EMC 27 SAI1 TX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].sel = 2, + + /* Index:27 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:27 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:27 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:27 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:27 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:27 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:28 GPIO_EMC_28 */ + + { + { + /* Index:28 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:28 Alt:1 GPIO EMC 28 FLEXPWM2 PWMA03 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT1].sel = 1, + + /* Index:28 Alt:2 GPIO EMC 28 XBAR1 INOUT18 */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN18_OFFSET), + [ALT2].sel = 0, + + /* Index:28 Alt:3 GPIO EMC 28 SAI3 MCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_MCLK_OFFSET), + [ALT3].sel = 2, + + /* Index:28 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:28 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:28 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:28 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:28 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:28 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:29 GPIO_EMC_29 */ + + { + { + /* Index:29 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:29 Alt:1 GPIO EMC 29 FLEXPWM2 PWMB03 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT1].sel = 1, + + /* Index:29 Alt:2 GPIO EMC 29 XBAR1 INOUT19 */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN19_OFFSET), + [ALT2].sel = 0, + + /* Index:29 Alt:3 GPIO EMC 29 SAI3 RX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_BCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:29 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:29 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:29 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:29 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:29 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:29 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:30 GPIO_EMC_30 */ + + { + { + /* Index:30 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:30 Alt:1 GPIO EMC 30 FLEXPWM2 PWMA02 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), + [ALT1].sel = 1, + + /* Index:30 Alt:2 GPIO EMC 30 LPUART4 CTS B */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_CTS_B_OFFSET), + [ALT2].sel = 1, + + /* Index:30 Alt:3 GPIO EMC 30 SAI3 RX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_SYNC_OFFSET), + [ALT3].sel = 1, + + /* Index:30 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:30 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:30 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:30 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:30 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:30 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:31 GPIO_EMC_31 */ + + { + { + /* Index:31 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:31 Alt:1 GPIO EMC 31 FLEXPWM2 PWMB02 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), + [ALT1].sel = 1, + + /* Index:31 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:31 Alt:3 GPIO EMC 31 SAI3 RX DATA */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_DATA0_OFFSET), + [ALT3].sel = 1, + + /* Index:31 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:31 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:31 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:31 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:31 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:31 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:32 GPIO_EMC_32 */ + + { + { + /* Index:32 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:32 Alt:1 GPIO EMC 32 QTIMER1 TIMER0 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER0_OFFSET), + [ALT1].sel = 1, + + /* Index:32 Alt:2 GPIO EMC 32 LPUART4 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), + [ALT2].sel = 2, + + /* Index:32 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:32 Alt:4 GPIO EMC 32 LPSPI4 SCK */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SCK_OFFSET), + [ALT4].sel = 1, + + /* Index:32 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:32 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:32 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:32 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:32 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:33 GPIO_EMC_33 */ + + { + { + /* Index:33 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:33 Alt:1 GPIO EMC 33 QTIMER1 TIMER1 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER1_OFFSET), + [ALT1].sel = 1, + + /* Index:33 Alt:2 GPIO EMC 33 LPUART4 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), + [ALT2].sel = 2, + + /* Index:33 Alt:3 GPIO EMC 33 SAI3 TX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_TX_BCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:33 Alt:4 GPIO EMC 33 LPSPI4 PCS0 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), + [ALT4].sel = 1, + + /* Index:33 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:33 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:33 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:33 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:33 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:34 GPIO_EMC_34 */ + + { + { + /* Index:34 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:34 Alt:1 GPIO EMC 34 QTIMER1 TIMER2 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER2_OFFSET), + [ALT1].sel = 1, + + /* Index:34 Alt:2 GPIO EMC 34 LPUART7 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_TX_OFFSET), + [ALT2].sel = 1, + + /* Index:34 Alt:3 GPIO EMC 34 SAI3 TX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_TX_SYNC_OFFSET), + [ALT3].sel = 1, + + /* Index:34 Alt:4 GPIO EMC 34 LPSPI4 SDO */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDO_OFFSET), + [ALT4].sel = 1, + + /* Index:34 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:34 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:34 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:34 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:34 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:35 GPIO_EMC_35 */ + + { + { + /* Index:35 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:35 Alt:1 GPIO EMC 35 QTIMER1 TIMER3 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER3_OFFSET), + [ALT1].sel = 1, + + /* Index:35 Alt:2 GPIO EMC 35 LPUART7 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_RX_OFFSET), + [ALT2].sel = 1, + + /* Index:35 Alt:3 GPIO EMC 35 USDHC2 WP */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CMD_OFFSET), + [ALT3].sel = 1, + + /* Index:35 Alt:4 GPIO EMC 35 LPSPI4 SDI */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDI_OFFSET), + [ALT4].sel = 1, + + /* Index:35 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:35 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:35 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:35 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:35 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:36 GPIO_EMC_36 */ + + { + { + /* Index:36 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:36 Alt:1 GPIO EMC 36 FLEXPWM2 PWMA01 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), + [ALT1].sel = 1, + + /* Index:36 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:36 Alt:3 GPIO EMC 36 CCM PMIC RDY */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT3].sel = 3, + + /* Index:36 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:36 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:36 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:36 Alt:7 GPIO EMC 36 USDHC1 WP */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), + [ALT7].sel = 4, + + /* Index:36 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:36 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:37 GPIO_EMC_37 */ + + { + { + /* Index:37 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:37 Alt:1 GPIO EMC 37 FLEXPWM2 PWMB01 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), + [ALT1].sel = 1, + + /* Index:37 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:37 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:37 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:37 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:37 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:37 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:37 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:37 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:38 GPIO_EMC_38 */ + + { + { + /* Index:38 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:38 Alt:1 GPIO EMC 38 FLEXPWM2 PWMA00 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), + [ALT1].sel = 1, + + /* Index:38 Alt:2 GPIO EMC 38 LPUART5 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_TX_OFFSET), + [ALT2].sel = 1, + + /* Index:38 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:38 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:38 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:38 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:38 Alt:7 GPIO EMC 38 USDHC1 CD B */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT7].sel = 3, + + /* Index:38 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:38 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:39 GPIO_EMC_39 */ + + { + { + /* Index:39 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:39 Alt:1 GPIO EMC 39 FLEXPWM2 PWMB00 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), + [ALT1].sel = 1, + + /* Index:39 Alt:2 GPIO EMC 39 LPUART5 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_RX_OFFSET), + [ALT2].sel = 1, + + /* Index:39 Alt:3 GPIO EMC 39 USB OTG1 OC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), + [ALT3].sel = 2, + + /* Index:39 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:39 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:39 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:39 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:39 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:39 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:40 GPIO_EMC_40 */ + + { + { + /* Index:40 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:40 Alt:1 GPIO EMC 40 XBAR1 INOUT18 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN18_OFFSET), + [ALT1].sel = 1, + + /* Index:40 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:40 Alt:3 GPIO EMC 40 USB OTG1 ID */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), + [ALT3].sel = 2, + + /* Index:40 Alt:4 GPIO EMC 40 ENET MDIO */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET), + [ALT4].sel = 2, + + /* Index:40 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:40 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:40 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:40 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:40 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:41 GPIO_EMC_41 */ + + { + { + /* Index:41 Alt:0 GPIO EMC 41 SEMC READY */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SEMC_READY_OFFSET), + [ALT0].sel = 1, + + /* Index:41 Alt:1 GPIO EMC 41 XBAR1 INOUT19 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN19_OFFSET), + [ALT1].sel = 1, + + /* Index:41 Alt:2 GPIO EMC 41 SPDIF IN */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SPDIF_IN_OFFSET), + [ALT2].sel = 1, + + /* Index:41 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:41 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:41 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:41 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:41 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:41 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:41 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:42 GPIO_AD_B0_00 */ + + { + { + /* Index:42 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:42 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:43 GPIO_AD_B0_01 */ + + { + { + /* Index:43 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:43 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:44 GPIO_AD_B0_02 */ + + { + { + /* Index:44 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:44 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:45 GPIO_AD_B0_03 */ + + { + { + /* Index:45 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:45 Alt:1 GPIO AD B0 03 USDHC2 CD B */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), + [ALT1].sel = 1, + + /* Index:45 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:45 Alt:3 GPIO AD B0 03 SAI1 MCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:45 Alt:4 GPIO AD B0 03 USDHC1 WP */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), + [ALT4].sel = 0, + + /* Index:45 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:45 Alt:6 GPIO AD B0 03 USB OTG1 OC */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), + [ALT6].sel = 0, + + /* Index:45 Alt:7 GPIO AD B0 03 CCM PMIC RDY */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT7].sel = 2, + + /* Index:45 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:45 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:46 GPIO_AD_B0_04 */ + + { + { + /* Index:46 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:46 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:46 Alt:2 GPIO AD B0 04 USDHC1 WP */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), + [ALT2].sel = 1, + + /* Index:46 Alt:3 GPIO AD B0 04 QTIMER2 TIMER0 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET), + [ALT3].sel = 1, + + /* Index:46 Alt:4 GPIO AD B0 04 ENET MDIO */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET), + [ALT4].sel = 1, + + /* Index:46 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:46 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:46 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:46 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:46 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:47 GPIO_AD_B0_05 */ + + { + { + /* Index:47 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:47 Alt:1 GPIO AD B0 05 FLEXCAN1 RX */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT1].sel = 2, + + /* Index:47 Alt:2 GPIO AD B0 05 USDHC1 CD B */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT2].sel = 1, + + /* Index:47 Alt:3 GPIO AD B0 05 QTIMER2 TIMER1 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET), + [ALT3].sel = 1, + + /* Index:47 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:47 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:47 Alt:6 GPIO AD B0 05 USB OTG1 ID */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), + [ALT6].sel = 0, + + /* Index:47 Alt:7 GPIO AD B0 05 NMI GLUE NMI */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), + [ALT7].sel = 0, + + /* Index:47 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:47 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:48 GPIO_AD_B0_06 */ + + { + { + /* Index:48 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:48 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:48 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:48 Alt:3 GPIO AD B0 06 QTIMER2 TIMER2 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET), + [ALT3].sel = 1, + + /* Index:48 Alt:4 GPIO AD B0 06 FLEXPWM2 PWMA03 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET), + [ALT4].sel = 0, + + /* Index:48 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:48 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:48 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:48 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:48 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:49 GPIO_AD_B0_07 */ + + { + { + /* Index:49 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:49 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:49 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:49 Alt:3 GPIO AD B0 07 QTIMER2 TIMER3 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET), + [ALT3].sel = 1, + + /* Index:49 Alt:4 GPIO AD B0 07 FLEXPWM2 PWMB03 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET), + [ALT4].sel = 0, + + /* Index:49 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:49 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:49 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:49 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:49 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:50 GPIO_AD_B0_08 */ + + { + { + /* Index:50 Alt:0 GPIO AD B0 08 ENET TX CLK */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_TXCLK_OFFSET), + [ALT0].sel = 1, + + /* Index:50 Alt:1 GPIO AD B0 08 LPI2C3 SCL */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SCL_OFFSET), + [ALT1].sel = 1, + + /* Index:50 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:50 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:50 Alt:4 GPIO AD B0 08 ENET REF CLK1 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), + [ALT4].sel = 1, + + /* Index:50 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:50 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:50 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:50 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:50 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:51 GPIO_AD_B0_09 */ + + { + { + /* Index:51 Alt:0 GPIO AD B0 09 ENET RDATA01 */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXDATA1_OFFSET), + [ALT0].sel = 1, + + /* Index:51 Alt:1 GPIO AD B0 09 LPI2C3 SDA */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SDA_OFFSET), + [ALT1].sel = 1, + + /* Index:51 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:51 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:51 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:51 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:51 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:51 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:51 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:51 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:52 GPIO_AD_B0_10 */ + + { + { + /* Index:52 Alt:0 GPIO AD B0 10 ENET RDATA00 */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXDATA0_OFFSET), + [ALT0].sel = 1, + + /* Index:52 Alt:1 GPIO AD B0 10 LPSPI1 SCK */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SCK_OFFSET), + [ALT1].sel = 1, + + /* Index:52 Alt:2 GPIO AD B0 10 LPUART5 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_TX_OFFSET), + [ALT2].sel = 0, + + /* Index:52 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:52 Alt:4 GPIO AD B0 10 FLEXPWM2 PWMA02 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET), + [ALT4].sel = 0, + + /* Index:52 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:52 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:52 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:52 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:52 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:53 GPIO_AD_B0_11 */ + + { + { + /* Index:53 Alt:0 GPIO AD B0 11 ENET RX EN */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXEN_OFFSET), + [ALT0].sel = 1, + + /* Index:53 Alt:1 GPIO AD B0 11 LPSPI1 PCS0 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), + [ALT1].sel = 1, + + /* Index:53 Alt:2 GPIO AD B0 11 LPUART5 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_RX_OFFSET), + [ALT2].sel = 0, + + /* Index:53 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:53 Alt:4 GPIO AD B0 11 FLEXPWM2 PWMB02 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET), + [ALT4].sel = 0, + + /* Index:53 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:53 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:53 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:53 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:53 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:54 GPIO_AD_B0_12 */ + + { + { + /* Index:54 Alt:0 GPIO AD B0 12 ENET RX ER */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXERR_OFFSET), + [ALT0].sel = 1, + + /* Index:54 Alt:1 GPIO AD B0 12 LPSPI1 SDO */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDO_OFFSET), + [ALT1].sel = 1, + + /* Index:54 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:54 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:54 Alt:4 GPIO AD B0 12 FLEXPWM2 PWMA01 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET), + [ALT4].sel = 0, + + /* Index:54 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:54 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:54 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:54 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:54 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:55 GPIO_AD_B0_13 */ + + { + { + /* Index:55 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:55 Alt:1 GPIO AD B0 13 LPSPI1 SDI */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDI_OFFSET), + [ALT1].sel = 1, + + /* Index:55 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:55 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:55 Alt:4 GPIO AD B0 13 FLEXPWM2 PWMB01 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET), + [ALT4].sel = 0, + + /* Index:55 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:55 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:55 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:55 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:55 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:56 GPIO_AD_B0_14 */ + + { + { + /* Index:56 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:56 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:56 Alt:2 GPIO AD B0 14 LPUART3 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET), + [ALT2].sel = 1, + + /* Index:56 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:56 Alt:4 GPIO AD B0 14 FLEXPWM2 PWMA00 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET), + [ALT4].sel = 0, + + /* Index:56 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:56 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:56 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:56 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:56 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:57 GPIO_AD_B0_15 */ + + { + { + /* Index:57 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:57 Alt:1 GPIO AD B0 15 FLEXCAN2 RX */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT1].sel = 2, + + /* Index:57 Alt:2 GPIO AD B0 15 LPUART3 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_RX_OFFSET), + [ALT2].sel = 1, + + /* Index:57 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:57 Alt:4 GPIO AD B0 15 FLEXPWM2 PWMB00 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET), + [ALT4].sel = 0, + + /* Index:57 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:57 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:57 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:57 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:57 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:58 GPIO_AD_B1_00 */ + + { + { + /* Index:58 Alt:0 GPIO AD B1 00 SEMC READY */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SEMC_READY_OFFSET), + [ALT0].sel = 0, + + /* Index:58 Alt:1 GPIO AD B1 00 FLEXSPI A DATA03 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), + [ALT1].sel = 1, + + /* Index:58 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:58 Alt:3 GPIO AD B1 00 SAI1 MCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK_OFFSET), + [ALT3].sel = 2, + + /* Index:58 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:58 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:58 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:58 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:58 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:58 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:59 GPIO_AD_B1_01 */ + + { + { + /* Index:59 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:59 Alt:1 GPIO AD B1 01 FLEXSPI A SCLK */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), + [ALT1].sel = 1, + + /* Index:59 Alt:2 GPIO AD B1 01 FLEXCAN2 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT2].sel = 3, + + /* Index:59 Alt:3 GPIO AD B1 01 SAI1 TX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET), + [ALT3].sel = 1, + + /* Index:59 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:59 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:59 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:59 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:59 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:59 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:60 GPIO_AD_B1_02 */ + + { + { + /* Index:60 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:60 Alt:1 GPIO AD B1 02 FLEXSPI A DATA00 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), + [ALT1].sel = 1, + + /* Index:60 Alt:2 GPIO AD B1 02 LPSPI4 SCK */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SCK_OFFSET), + [ALT2].sel = 0, + + /* Index:60 Alt:3 GPIO AD B1 02 SAI1 TX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET), + [ALT3].sel = 1, + + /* Index:60 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:60 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:60 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:60 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:60 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:60 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:61 GPIO_AD_B1_03 */ + + { + { + /* Index:61 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:61 Alt:1 GPIO AD B1 03 FLEXSPI A DATA02 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), + [ALT1].sel = 1, + + /* Index:61 Alt:2 GPIO AD B1 03 LPSPI4 PCS0 */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET), + [ALT2].sel = 0, + + /* Index:61 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:61 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:61 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:61 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:61 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:61 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:61 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:62 GPIO_AD_B1_04 */ + + { + { + /* Index:62 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:62 Alt:1 GPIO AD B1 04 FLEXSPI A DATA01 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), + [ALT1].sel = 1, + + /* Index:62 Alt:2 GPIO AD B1 04 LPSPI4 SDO */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDO_OFFSET), + [ALT2].sel = 0, + + /* Index:62 Alt:3 GPIO AD B1 04 SAI1 RX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET), + [ALT3].sel = 0, + + /* Index:62 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:62 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:62 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:62 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:62 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:62 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:63 GPIO_AD_B1_05 */ + + { + { + /* Index:63 Alt:0 GPIO AD B1 05 USDHC1 WP */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), + [ALT0].sel = 2, + + /* Index:63 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:63 Alt:2 GPIO AD B1 05 LPSPI4 SDI */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDI_OFFSET), + [ALT2].sel = 0, + + /* Index:63 Alt:3 GPIO AD B1 05 SAI1 RX DATA00 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET), + [ALT3].sel = 1, + + /* Index:63 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:63 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:63 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:63 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:63 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:63 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:64 GPIO_AD_B1_06 */ + + { + { + /* Index:64 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:64 Alt:1 GPIO AD B1 06 FLEXPWM1 PWMA00 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET), + [ALT1].sel = 0, + + /* Index:64 Alt:2 GPIO AD B1 06 LPUART2 CTS B */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET), + [ALT2].sel = 0, + + /* Index:64 Alt:3 GPIO AD B1 06 SAI1 RX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET), + [ALT3].sel = 0, + + /* Index:64 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:64 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:64 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:64 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:64 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:64 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:65 GPIO_AD_B1_07 */ + + { + { + /* Index:65 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:65 Alt:1 GPIO AD B1 07 FLEXPWM1 PWMB00 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET), + [ALT1].sel = 0, + + /* Index:65 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:65 Alt:3 GPIO AD B1 07 SAI1 TX DATA01 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET), + [ALT3].sel = 0, + + /* Index:65 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:65 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:65 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:65 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:65 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:65 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:66 GPIO_AD_B1_08 */ + + { + { + /* Index:66 Alt:0 GPIO AD B1 08 LPI2C2 SCL */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SCL_OFFSET), + [ALT0].sel = 0, + + /* Index:66 Alt:1 GPIO AD B1 08 FLEXPWM1 PWMA01 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET), + [ALT1].sel = 0, + + /* Index:66 Alt:2 GPIO AD B1 08 LPUART2 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET), + [ALT2].sel = 0, + + /* Index:66 Alt:3 GPIO AD B1 08 SAI1 TX DATA02 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET), + [ALT3].sel = 0, + + /* Index:66 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:66 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:66 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:66 Alt:7 GPIO AD B1 08 XBAR1 INOUT12 */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN12_OFFSET), + [ALT7].sel = 1, + + /* Index:66 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:66 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:67 GPIO_AD_B1_09 */ + + { + { + /* Index:67 Alt:0 GPIO AD B1 09 LPI2C2 SDA */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SDA_OFFSET), + [ALT0].sel = 0, + + /* Index:67 Alt:1 GPIO AD B1 09 FLEXPWM1 PWMB01 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET), + [ALT1].sel = 0, + + /* Index:67 Alt:2 GPIO AD B1 09 LPUART2 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_RX_OFFSET), + [ALT2].sel = 0, + + /* Index:67 Alt:3 GPIO AD B1 09 SAI1 TX DATA03 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET), + [ALT3].sel = 0, + + /* Index:67 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:67 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:67 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:67 Alt:7 GPIO AD B1 09 XBAR1 INOUT13 */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN13_OFFSET), + [ALT7].sel = 1, + + /* Index:67 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:67 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:68 GPIO_AD_B1_10 */ + + { + { + /* Index:68 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:68 Alt:1 GPIO AD B1 10 FLEXPWM1 PWMA02 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET), + [ALT1].sel = 0, + + /* Index:68 Alt:2 GPIO AD B1 10 LPUART4 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET), + [ALT2].sel = 1, + + /* Index:68 Alt:3 GPIO AD B1 10 USDHC1 CD B */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT3].sel = 2, + + /* Index:68 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:68 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:68 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:68 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:68 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:68 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:69 GPIO_AD_B1_11 */ + + { + { + /* Index:69 Alt:0 GPIO AD B1 11 USB OTG1 ID */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET), + [ALT0].sel = 1, + + /* Index:69 Alt:1 GPIO AD B1 11 FLEXPWM1 PWMB02 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET), + [ALT1].sel = 0, + + /* Index:69 Alt:2 GPIO AD B1 11 LPUART4 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET), + [ALT2].sel = 1, + + /* Index:69 Alt:3 GPIO AD B1 11 USDHC1 WP */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET), + [ALT3].sel = 3, + + /* Index:69 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:69 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:69 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:69 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:69 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:69 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:70 GPIO_AD_B1_12 */ + + { + { + /* Index:70 Alt:0 GPIO AD B1 12 USB OTG1 OC */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET), + [ALT0].sel = 1, + + /* Index:70 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:70 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:70 Alt:3 GPIO AD B1 12 USDHC2 CD B */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), + [ALT3].sel = 2, + + /* Index:70 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:70 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:70 Alt:6 GPIO AD B1 12 FLEXPWM1 PWMA03 */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET), + [ALT6].sel = 0, + + /* Index:70 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:70 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:70 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:71 GPIO_AD_B1_13 */ + + { + { + /* Index:71 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:71 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:71 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:71 Alt:3 GPIO AD B1 13 USDHC2 WP */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CMD_OFFSET), + [ALT3].sel = 0, + + /* Index:71 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:71 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:71 Alt:6 GPIO AD B1 13 FLEXPWM1 PWMB03 */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET), + [ALT6].sel = 0, + + /* Index:71 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:71 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:71 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:72 GPIO_AD_B1_14 */ + + { + { + /* Index:72 Alt:0 GPIO AD B1 14 LPI2C1 SCL */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SCL_OFFSET), + [ALT0].sel = 1, + + /* Index:72 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:72 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:72 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:72 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:72 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:72 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:72 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:72 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:72 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:73 GPIO_AD_B1_15 */ + + { + { + /* Index:73 Alt:0 GPIO AD B1 15 LPI2C1 SDA */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SDA_OFFSET), + [ALT0].sel = 1, + + /* Index:73 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:73 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:73 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:73 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:73 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:73 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:73 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:73 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:73 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:74 GPIO_SD_B0_00 */ + + { + { + /* Index:74 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:74 Alt:1 GPIO SD B0 00 QTIMER1 TIMER0 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER0_OFFSET), + [ALT1].sel = 0, + + /* Index:74 Alt:2 GPIO SD B0 00 SAI1 MCLK */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK_OFFSET), + [ALT2].sel = 0, + + /* Index:74 Alt:3 GPIO SD B0 00 SAI2 MCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_MCLK_OFFSET), + [ALT3].sel = 0, + + /* Index:74 Alt:4 GPIO SD B0 00 LPI2C3 SCL */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SCL_OFFSET), + [ALT4].sel = 0, + + /* Index:74 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:74 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:74 Alt:7 GPIO SD B0 00 XBAR1 INOUT14 */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN14_OFFSET), + [ALT7].sel = 0, + + /* Index:74 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:74 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:75 GPIO_SD_B0_01 */ + + { + { + /* Index:75 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:75 Alt:1 GPIO SD B0 01 QTIMER1 TIMER1 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER1_OFFSET), + [ALT1].sel = 0, + + /* Index:75 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:75 Alt:3 GPIO SD B0 01 SAI2 RX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET), + [ALT3].sel = 0, + + /* Index:75 Alt:4 GPIO SD B0 01 LPI2C3 SDA */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SDA_OFFSET), + [ALT4].sel = 0, + + /* Index:75 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:75 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:75 Alt:7 GPIO SD B0 01 XBAR1 INOUT15 */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN15_OFFSET), + [ALT7].sel = 0, + + /* Index:75 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:75 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:76 GPIO_SD_B0_02 */ + + { + { + /* Index:76 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:76 Alt:1 GPIO SD B0 02 QTIMER1 TIMER2 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER2_OFFSET), + [ALT1].sel = 0, + + /* Index:76 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:76 Alt:3 GPIO SD B0 02 SAI2 RX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET), + [ALT3].sel = 0, + + /* Index:76 Alt:4 GPIO SD B0 02 LPSPI1 SCK */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SCK_OFFSET), + [ALT4].sel = 0, + + /* Index:76 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:76 Alt:6 GPIO SD B0 02 ENET MDIO */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET), + [ALT6].sel = 0, + + /* Index:76 Alt:7 GPIO SD B0 02 XBAR1 INOUT16 */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN16_OFFSET), + [ALT7].sel = 0, + + /* Index:76 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:76 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:77 GPIO_SD_B0_03 */ + + { + { + /* Index:77 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:77 Alt:1 GPIO SD B0 03 QTIMER1 TIMER3 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER3_OFFSET), + [ALT1].sel = 0, + + /* Index:77 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:77 Alt:3 GPIO SD B0 03 SAI2 RX DATA */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET), + [ALT3].sel = 0, + + /* Index:77 Alt:4 GPIO SD B0 03 LPSPI1 PCS0 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET), + [ALT4].sel = 0, + + /* Index:77 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:77 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:77 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:77 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:77 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:78 GPIO_SD_B0_04 */ + + { + { + /* Index:78 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:78 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:78 Alt:2 GPIO SD B0 04 LPUART7 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_TX_OFFSET), + [ALT2].sel = 0, + + /* Index:78 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:78 Alt:4 GPIO SD B0 04 LPSPI1 SDO */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDO_OFFSET), + [ALT4].sel = 0, + + /* Index:78 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:78 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:78 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:78 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:78 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:79 GPIO_SD_B0_05 */ + + { + { + /* Index:79 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:79 Alt:1 GPIO SD B0 05 FLEXCAN2 RX */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET), + [ALT1].sel = 0, + + /* Index:79 Alt:2 GPIO SD B0 05 LPUART7 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_RX_OFFSET), + [ALT2].sel = 0, + + /* Index:79 Alt:3 GPIO SD B0 05 SAI2 TX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET), + [ALT3].sel = 0, + + /* Index:79 Alt:4 GPIO SD B0 05 LPSPI1 SDI */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDI_OFFSET), + [ALT4].sel = 0, + + /* Index:79 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:79 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:79 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:79 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:79 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:80 GPIO_SD_B0_06 */ + + { + { + /* Index:80 Alt:0 GPIO SD B0 06 USDHC1 CD B */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET), + [ALT0].sel = 0, + + /* Index:80 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:80 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:80 Alt:3 GPIO SD B0 06 SAI2 TX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET), + [ALT3].sel = 0, + + /* Index:80 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:80 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:80 Alt:6 GPIO SD B0 06 XBAR1 INOUT17 */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET), + [ALT6].sel = 0, + + /* Index:80 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:80 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:80 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:81 GPIO_SD_B1_00 */ + + { + { + /* Index:81 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:81 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:81 Alt:2 GPIO SD B1 00 LPUART6 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_TX_OFFSET), + [ALT2].sel = 1, + + /* Index:81 Alt:3 GPIO SD B1 00 XBAR1 INOUT10 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN10_OFFSET), + [ALT3].sel = 1, + + /* Index:81 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:81 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:81 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:81 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:81 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:81 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:82 GPIO_SD_B1_01 */ + + { + { + /* Index:82 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:82 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:82 Alt:2 GPIO SD B1 01 LPUART6 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_RX_OFFSET), + [ALT2].sel = 1, + + /* Index:82 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:82 Alt:4 GPIO SD B1 01 FLEXCAN1 RX */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET), + [ALT4].sel = 1, + + /* Index:82 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:82 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:82 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:82 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:82 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:83 GPIO_SD_B1_02 */ + + { + { + /* Index:83 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:83 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:83 Alt:2 GPIO SD B1 02 LPUART8 TX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET), + [ALT2].sel = 0, + + /* Index:83 Alt:3 GPIO SD B1 02 LPI2C4 SCL */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SCL_OFFSET), + [ALT3].sel = 1, + + /* Index:83 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:83 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:83 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:83 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:83 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:83 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:84 GPIO_SD_B1_03 */ + + { + { + /* Index:84 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:84 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:84 Alt:2 GPIO SD B1 03 LPUART8 RX */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET), + [ALT2].sel = 0, + + /* Index:84 Alt:3 GPIO SD B1 03 LPI2C4 SDA */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SDA_OFFSET), + [ALT3].sel = 1, + + /* Index:84 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:84 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:84 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:84 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:84 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:84 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:85 GPIO_SD_B1_04 */ + + { + { + /* Index:85 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:85 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:85 Alt:2 GPIO SD B1 04 ENET TX CLK */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_TXCLK_OFFSET), + [ALT2].sel = 0, + + /* Index:85 Alt:3 GPIO SD B1 04 ENET REF CLK1 */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET), + [ALT3].sel = 0, + + /* Index:85 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:85 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:85 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:85 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:85 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:85 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:86 GPIO_SD_B1_05 */ + + { + { + /* Index:86 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:86 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:86 Alt:2 GPIO SD B1 05 ENET RDATA01 */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXDATA1_OFFSET), + [ALT2].sel = 0, + + /* Index:86 Alt:3 GPIO SD B1 05 SAI3 MCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_MCLK_OFFSET), + [ALT3].sel = 0, + + /* Index:86 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:86 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:86 Alt:6 GPIO SD B1 05 CCM PMIC RDY */ + + [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET), + [ALT6].sel = 1, + + /* Index:86 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:86 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:86 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:87 GPIO_SD_B1_06 */ + + { + { + /* Index:87 Alt:0 GPIO SD B1 06 USDHC2 CD B */ + + [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET), + [ALT0].sel = 0, + + /* Index:87 Alt:1 GPIO SD B1 06 FLEXSPI A DATA03 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET), + [ALT1].sel = 0, + + /* Index:87 Alt:2 GPIO SD B1 06 ENET RDATA00 */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXDATA0_OFFSET), + [ALT2].sel = 0, + + /* Index:87 Alt:3 GPIO SD B1 06 SAI3 TX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_TX_BCLK_OFFSET), + [ALT3].sel = 0, + + /* Index:87 Alt:4 GPIO SD B1 06 LPSPI2 PCS0 */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET), + [ALT4].sel = 2, + + /* Index:87 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:87 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:87 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:87 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:87 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:88 GPIO_SD_B1_07 */ + + { + { + /* Index:88 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:88 Alt:1 GPIO SD B1 07 FLEXSPI A SCLK */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET), + [ALT1].sel = 0, + + /* Index:88 Alt:2 GPIO SD B1 07 ENET RX EN */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXEN_OFFSET), + [ALT2].sel = 0, + + /* Index:88 Alt:3 GPIO SD B1 07 SAI3 TX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_TX_SYNC_OFFSET), + [ALT3].sel = 0, + + /* Index:88 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:88 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:88 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:88 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:88 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:88 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:89 GPIO_SD_B1_08 */ + + { + { + /* Index:89 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:89 Alt:1 GPIO SD B1 08 FLEXSPI A DATA00 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET), + [ALT1].sel = 0, + + /* Index:89 Alt:2 GPIO SD B1 08 ENET RX ER */ + + [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXERR_OFFSET), + [ALT2].sel = 0, + + /* Index:89 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:89 Alt:4 GPIO SD B1 08 LPSPI2 SDO */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDO_OFFSET), + [ALT4].sel = 2, + + /* Index:89 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:89 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:89 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:89 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:89 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:90 GPIO_SD_B1_09 */ + + { + { + /* Index:90 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:90 Alt:1 GPIO SD B1 09 FLEXSPI A DATA02 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET), + [ALT1].sel = 0, + + /* Index:90 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:90 Alt:3 GPIO SD B1 09 SAI3 RX BCLK */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_BCLK_OFFSET), + [ALT3].sel = 0, + + /* Index:90 Alt:4 GPIO SD B1 09 LPSPI2 SDI */ + + [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDI_OFFSET), + [ALT4].sel = 2, + + /* Index:90 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:90 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:90 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:90 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:90 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:91 GPIO_SD_B1_10 */ + + { + { + /* Index:91 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:91 Alt:1 GPIO SD B1 10 FLEXSPI A DATA01 */ + + [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET), + [ALT1].sel = 0, + + /* Index:91 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:91 Alt:3 GPIO SD B1 10 SAI3 RX SYNC */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_SYNC_OFFSET), + [ALT3].sel = 0, + + /* Index:91 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:91 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:91 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:91 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:91 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:91 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:92 GPIO_SD_B1_11 */ + + { + { + /* Index:92 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:92 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:92 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:92 Alt:3 GPIO SD B1 11 SAI3 RX DATA */ + + [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_DATA0_OFFSET), + [ALT3].sel = 0, + + /* Index:92 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:92 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:92 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:92 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:92 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:92 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:93 WAKEUP */ + + { + { + /* Index:93 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:93 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:93 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:93 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:93 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:93 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:93 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:93 Alt:7 SNVS WAKEUP NMI GLUE NMI */ + + [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET), + [ALT7].sel = 1, + + /* Index:93 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:93 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:94 PMIC_ON_REQ */ + + { + { + /* Index:94 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:94 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, + + /* index:95 PMIC_STBY_REQ */ + + { + { + /* Index:95 Alt:0 No input selection */ + + [ALT0].index = DAISY_INDEX_INVALID, + [ALT0].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:1 No input selection */ + + [ALT1].index = DAISY_INDEX_INVALID, + [ALT1].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:2 No input selection */ + + [ALT2].index = DAISY_INDEX_INVALID, + [ALT2].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:3 No input selection */ + + [ALT3].index = DAISY_INDEX_INVALID, + [ALT3].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:4 No input selection */ + + [ALT4].index = DAISY_INDEX_INVALID, + [ALT4].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:5 No input selection */ + + [ALT5].index = DAISY_INDEX_INVALID, + [ALT5].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:6 No input selection */ + + [ALT6].index = DAISY_INDEX_INVALID, + [ALT6].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:7 No input selection */ + + [ALT7].index = DAISY_INDEX_INVALID, + [ALT7].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:8 No input selection */ + + [ALT8].index = DAISY_INDEX_INVALID, + [ALT8].sel = DAISY_SEL_INVALID, + + /* Index:95 Alt:9 No input selection */ + + [ALT9].index = DAISY_INDEX_INVALID, + [ALT9].sel = DAISY_SEL_INVALID, + }, + }, +}; diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.c b/arch/arm/src/imxrt/imxrt_clockconfig.c index ba47f0dfeb1..6d38cae7702 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig.c +++ b/arch/arm/src/imxrt/imxrt_clockconfig.c @@ -1,10 +1,11 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_clockconfig.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. * Authors: Janne Rosberg * Ivan Ucherdzhiev * David Sidrane + * Dave Marples * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -217,11 +218,124 @@ static void imxrt_lcd_clockconfig(void) modifyreg32(IMXRT_CCM_CBCMR, CCM_CBCMR_LCDIF_PODF_MASK, CCM_CBCMR_LCDIF_PODF(post_divider)); - } #endif +/**************************************************************************** + * Name: imxrt_pllsetup + ****************************************************************************/ + +static void imxrt_pllsetup(void) + +{ + uint32_t reg; +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x)) + + /* Init Arm PLL1 */ + + reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) | + CCM_ANALOG_PLL_ARM_ENABLE; + putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM); + while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0) + { + } + + /* Init Sys PLL2 */ + + reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) | + CCM_ANALOG_PLL_SYS_ENABLE; + putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS); + while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0) + { + } + +#ifdef CONFIG_IMXRT_LCD + /* Init Video PLL5 */ + + imxrt_lcd_clockconfig(); +#endif + + /* Init ENET PLL6 */ + + reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ | CCM_ANALOG_PLL_ENET_ENET1_125M_EN | + CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN | CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN | + CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ; + + putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET); + + while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0) + { + } + +#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x) + /* Init Sys PLL2 */ + /* First reset its fractional dividers */ + + uint32_t pll2reg=getreg32(IMXRT_CCM_ANALOG_PFD_528); + putreg32(pll2reg | + CCM_ANALOG_PFD_528_PFD0_CLKGATE | + CCM_ANALOG_PFD_528_PFD1_CLKGATE | + CCM_ANALOG_PFD_528_PFD2_CLKGATE | + CCM_ANALOG_PFD_528_PFD3_CLKGATE, + IMXRT_CCM_ANALOG_PFD_528 ); + + reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_DIV_SELECT) | + CCM_ANALOG_PLL_SYS_ENABLE; + putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS); + while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0) + { + } + + putreg32(pll2reg,IMXRT_CCM_ANALOG_PFD_528); + + /* Init USB PLL3 */ + /* capture it's original value */ + + uint32_t pll3reg=getreg32(IMXRT_CCM_ANALOG_PFD_480); + putreg32(pll3reg | + CCM_ANALOG_PFD_480_PFD0_CLKGATE | + CCM_ANALOG_PFD_480_PFD1_CLKGATE | + CCM_ANALOG_PFD_480_PFD2_CLKGATE | + CCM_ANALOG_PFD_480_PFD3_CLKGATE, + IMXRT_CCM_ANALOG_PFD_480 ); + + reg = CCM_ANALOG_PLL_USB1_DIV_SELECT(IMXRT_USB1_PLL_DIV_SELECT) | + CCM_ANALOG_PLL_USB1_ENABLE | CCM_ANALOG_PLL_USB1_EN_USB_CLKS | + CCM_ANALOG_PLL_USB1_POWER; + putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB1); + while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & CCM_ANALOG_PLL_USB1_LOCK) == 0) + { + } + + putreg32(pll3reg,IMXRT_CCM_ANALOG_PFD_480); + + /* Init Audio PLL4 */ + + reg = CCM_ANALOG_PLL_AUDIO_DIV_SELECT(IMXRT_AUDIO_PLL_DIV_SELECT) | + CCM_ANALOG_PLL_AUDIO_ENABLE; + putreg32(reg, IMXRT_CCM_ANALOG_PLL_AUDIO); + while ((getreg32(IMXRT_CCM_ANALOG_PLL_AUDIO) & CCM_ANALOG_PLL_AUDIO_LOCK) == 0) + { + } + + /* Init ENET PLL6 */ + + reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ | CCM_ANALOG_PLL_ENET_ENET1_125M_EN | + CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN | CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN; + + putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET); + + while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0) + { + } + +#else +#error Unrecognised IMXRT family member for clock config +#endif + +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -276,31 +390,9 @@ void imxrt_clockconfig(void) reg |= DCDC_REG3_TRG(IMXRT_VDD_SOC); putreg32(reg, IMXRT_DCDC_REG3); - /* Init Arm PLL1 */ + /* OK, now nothing is depending on us, configure the PLLs */ - reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) | - CCM_ANALOG_PLL_ARM_ENABLE; - putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM); - while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0) - { - } - - /* Init Sys PLL2 */ - - reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) | - CCM_ANALOG_PLL_SYS_ENABLE; - putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS); - while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0) - { - } - -#ifdef CONFIG_IMXRT_LCD - /* Init Video PLL5 */ - - imxrt_lcd_clockconfig(); -#endif - - /* TODO: other pll configs */ + imxrt_pllsetup(); /* Set Dividers */ @@ -325,7 +417,7 @@ void imxrt_clockconfig(void) putreg32(reg, IMXRT_CCM_CSCMR1); #ifndef CONFIG_IMXRT_SEMC_INIT_DONE - /* Configure SEMC Clock only if not already done by DCD SDRAM init. */ + /* Configure SEMC Clock only if not already done by DCD SDR */ reg = getreg32(IMXRT_CCM_CBCDR); reg &= ~CCM_CBCDR_SEMC_PODF_MASK; @@ -390,7 +482,7 @@ void imxrt_clockconfig(void) reg = getreg32(IMXRT_CCM_CSCDR2); reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK; - reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5); + reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5-1); putreg32(reg, IMXRT_CCM_CSCDR2); while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0) diff --git a/arch/arm/src/imxrt/imxrt_daisy.c b/arch/arm/src/imxrt/imxrt_daisy.c index 2267e5048d8..7d668e62680 100644 --- a/arch/arm/src/imxrt/imxrt_daisy.c +++ b/arch/arm/src/imxrt/imxrt_daisy.c @@ -79,7 +79,9 @@ struct imxrt_daisy_t /* Include chip-specific daisy input selection */ -#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) +#if defined(CONFIG_ARCH_FAMILY_IMXRT102x) +# include "imxrt102x_daisy.c" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x) # include "imxrt105x_daisy.c" #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) # include "imxrt106x_daisy.c" diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index e9f4b9494d9..b08780c5251 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_enet.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -185,6 +185,9 @@ * value into a boolean: true=duplex mode, false=half-duplex mode * * The imxrt1050-evk board uses a KSZ8081 PHY + * The Versiboard2 uses a LAN8720 PHY + * + * ...and further PHY descriptions here. */ #if defined(CONFIG_ETH0_PHY_KSZ8081) @@ -196,6 +199,15 @@ # define BOARD_PHY_10BASET(s) (((s) & MII_PHYCTRL1_MODE_10HDX) != 0) # define BOARD_PHY_100BASET(s) (((s) & MII_PHYCTRL1_MODE_100HDX) != 0) # define BOARD_PHY_ISDUPLEX(s) (((s) & MII_PHYCTRL1_MODE_DUPLEX) != 0) +#elif defined(CONFIG_ETH0_PHY_LAN8720) +# define BOARD_PHY_NAME "LAN8720" +# define BOARD_PHYID1 MII_PHYID1_LAN8720 +# define BOARD_PHYID2 MII_PHYID2_LAN8720 +# define BOARD_PHY_STATUS MII_LAN8720_SCSR +# define BOARD_PHY_ADDR (1) +# define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0) +# define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0) +# define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0) #else # error "Unrecognized or missing PHY selection" #endif @@ -566,8 +578,9 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv) * Function: imxrt_txpoll * * Description: - * The transmitter is available, check if the network has any outgoing packets ready - * to send. This is a callback from devif_poll(). devif_poll() may be called: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: * * 1. When the preceding TX packet send is complete, * 2. When the preceding TX packet send timesout and the interface is reset @@ -627,8 +640,8 @@ static int imxrt_txpoll(struct net_driver_s *dev) priv->dev.d_buf = (uint8_t *)imxrt_swap32((uint32_t)priv->txdesc[priv->txhead].data); - /* Check if there is room in the device to hold another packet. If not, - * return a non-zero value to terminate the poll. + /* Check if there is room in the device to hold another packet. If + * not, return a non-zero value to terminate the poll. */ if (imxrt_txringfull(priv)) @@ -976,8 +989,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg) FAR struct imxrt_driver_s *priv = (FAR struct imxrt_driver_s *)arg; uint32_t pending; #ifdef CONFIG_NET_MCASTGROUP - uint32_t gaurStore; - uint32_t galrStore; + uint32_t gaurstore; + uint32_t galrstore; #endif /* Process pending Ethernet interrupts */ @@ -1017,8 +1030,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg) * multicast hash table. */ - gaurStore = getreg32(IMXRT_ENET_GAUR); - galrStore = getreg32(IMXRT_ENET_GALR); + gaurstore = getreg32(IMXRT_ENET_GAUR); + galrstore = getreg32(IMXRT_ENET_GALR); #endif (void)imxrt_ifdown(&priv->dev); @@ -1027,8 +1040,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg) #ifdef CONFIG_NET_MCASTGROUP /* Now write the multicast table back */ - putreg32(gaurStore, IMXRT_ENET_GAUR); - putreg32(galrStore, IMXRT_ENET_GALR); + putreg32(gaurstore, IMXRT_ENET_GAUR); + putreg32(galrstore, IMXRT_ENET_GALR); #endif /* Then poll the network for new XMIT data */ @@ -1489,8 +1502,8 @@ static void imxrt_txavail_work(FAR void *arg) if (!imxrt_txringfull(priv)) { - /* No, there is space for another transfer. Poll the network for new - * XMIT data. + /* No, there is space for another transfer. Poll the network for + * new XMIT data. */ (void)devif_poll(&priv->dev, imxrt_txpoll); @@ -1558,7 +1571,7 @@ static int imxrt_txavail(struct net_driver_s *dev) #ifdef CONFIG_NET_MCASTGROUP static uint32_t imxrt_calcethcrc(const uint8_t *data, size_t length) { - uint32_t crc = 0xFFFFFFFFU; + uint32_t crc = 0xffffffffu; uint32_t count1 = 0; uint32_t count2 = 0; @@ -1568,13 +1581,13 @@ static uint32_t imxrt_calcethcrc(const uint8_t *data, size_t length) { uint8_t c = data[count1]; - for (count2 = 0; count2 < 0x08U; count2++) + for (count2 = 0; count2 < 0x08u; count2++) { if ((c ^ crc) & 1U) { crc >>= 1U; c >>= 1U; - crc ^= 0xEDB88320U; + crc ^= 0xedb88320u; } else { @@ -1614,7 +1627,7 @@ static uint32_t imxrt_enet_hash_index(const uint8_t *mac) mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); crc = imxrt_calcethcrc(mac, 6); - hashindex = (crc >> 26) & 0x3F; + hashindex = (crc >> 26) & 0x3f; return hashindex; } @@ -1672,8 +1685,8 @@ static int imxrt_addmac(struct net_driver_s *dev, FAR const uint8_t *mac) * Function: imxrt_rmmac * * Description: - * NuttX Callback: Remove the specified MAC address from the hardware multicast - * address filtering + * NuttX Callback: Remove the specified MAC address from the hardware + * multicast address filtering * * Input Parameters: * dev - Reference to the NuttX driver state structure @@ -1747,9 +1760,10 @@ static int imxrt_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_NETDEV_PHY_IOCTL #ifdef CONFIG_ARCH_PHY_INTERRUPT - case SIOCMIINOTIFY: /* Set up for PHY event notifications */ - { - struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg); + case SIOCMIINOTIFY: /* Set up for PHY event notifications */ + { + struct mii_ioctl_notify_s *req = + (struct mii_ioctl_notify_s *)((uintptr_t)arg); ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event); if (ret == OK) @@ -1834,7 +1848,7 @@ static int imxrt_phyintenable(struct imxrt_driver_s *priv) /* Enable link up/down interrupts */ ret = imxrt_writemii(priv, priv->phyaddr, MII_KSZ8081_INT, - (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN)); + (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN)); } return ret; @@ -2025,7 +2039,8 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) if (renogphy) { /* Loop (potentially infinitely?) until we successfully communicate with - * the PHY. + * the PHY. This is 'standard stuff' that should work for any PHY - we + * are not communicating with it's 'special' registers at this point. */ ninfo("%s: Try phyaddr: %u\n", BOARD_PHY_NAME, phyaddr); @@ -2047,7 +2062,7 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) if (retries >= 3) { - nerr("ERROR: Failed to read %s PHYID1 at address %d\n", phyaddr); + nerr("ERROR: Failed to read %s PHYID1 at address %d\n", BOARD_PHY_NAME, phyaddr); return -ENOENT; } @@ -2086,6 +2101,7 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) return -ENXIO; } +#ifdef CONFIG_ETH0_PHY_KSZ8081 /* Reset PHY */ imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); @@ -2116,6 +2132,31 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) imxrt_writemii(priv, phyaddr, MII_KSZ8081_OMSO, (phydata & ~(1 << 5))); + /* Set Ethernet led to green = activity and yellow = link and */ + + ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata); + if (ret < 0) + { + nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n"); + return ret; + } + + imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, + (phydata | (1 << 4))); + +#elif defined (CONFIG_ETH0_PHY_LAN8720) + + /* Make sure that PHY comes up in correct mode when it's reset */ + + imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES, + MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL | + MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR)); + + /* ...and reset PHY */ + + imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); +#endif + /* Start auto negotiation */ ninfo("%s: Start Autonegotiation...\n", BOARD_PHY_NAME); @@ -2163,18 +2204,6 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) imxrt_writemii(priv, phyaddr, MII_MCR, 0); } - - /* Set Ethernet led to green = activity and yellow = link and */ - - ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata); - if (ret < 0) - { - nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n"); - return ret; - } - - imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, - (phydata | (1 << 4))); } /* When we get here we have a (negotiated) speed and duplex. This is also @@ -2349,8 +2378,8 @@ static void imxrt_initbuffers(struct imxrt_driver_s *priv) /* Set the wrap bit in the last descriptors to form a ring */ - priv->txdesc[CONFIG_IMXRT_ENET_NTXBUFFERS-1].status1 |= TXDESC_W; - priv->rxdesc[CONFIG_IMXRT_ENET_NRXBUFFERS-1].status1 |= RXDESC_W; + priv->txdesc[CONFIG_IMXRT_ENET_NTXBUFFERS - 1].status1 |= TXDESC_W; + priv->rxdesc[CONFIG_IMXRT_ENET_NRXBUFFERS - 1].status1 |= RXDESC_W; /* We start with RX descriptor 0 and with no TX descriptors in use */ @@ -2433,19 +2462,7 @@ int imxrt_netinitialize(int intf) DEBUGASSERT(intf < CONFIG_IMXRT_ENET_NETHIFS); priv = &g_enet[intf]; - /* Init ENET PLL6 */ - - regval = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ | - CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ | - CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M | - CCM_ANALOG_PLL_ENET_ENET1_125M_EN; - putreg32(regval, IMXRT_CCM_ANALOG_PLL_ENET); - - while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0) - { - } - - /* Enable ENET1_TX_CLK_DIR */ + /* Enable ENET1_TX_CLK_DIR (Provides 50MHz clk OUT to PHY) */ regval = getreg32(IMXRT_IOMUXC_GPR_GPR1); regval |= GPR_GPR1_ENET1_TX_CLK_OUT_EN; @@ -2457,25 +2474,18 @@ int imxrt_netinitialize(int intf) /* Configure all ENET/MII pins */ - imxrt_config_gpio(GPIO_ENET_MDIO_3); - imxrt_config_gpio(GPIO_ENET_MDC_3); - imxrt_config_gpio(GPIO_ENET_RX_EN_1); - imxrt_config_gpio(GPIO_ENET_RX_ER_1); - imxrt_config_gpio(GPIO_ENET_RX_DATA00); - imxrt_config_gpio(GPIO_ENET_RX_DATA01); - imxrt_config_gpio(GPIO_ENET_TX_DATA00); - imxrt_config_gpio(GPIO_ENET_TX_DATA01); - imxrt_config_gpio(GPIO_ENET_TX_CLK_1); - imxrt_config_gpio(GPIO_ENET_TX_EN_1); - - /* Configure daisy chain pins */ - - putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET); - putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_MDIO_OFFSET); - putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET0_RXDATA_OFFSET); - putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET1_RXDATA_OFFSET); - putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXEN_OFFSET); - putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXERR_OFFSET); + imxrt_config_gpio(GPIO_ENET_MDIO); + imxrt_config_gpio(GPIO_ENET_MDC); + imxrt_config_gpio(GPIO_ENET_RX_EN); + imxrt_config_gpio(GPIO_ENET_RDATA00); + imxrt_config_gpio(GPIO_ENET_RDATA01); + imxrt_config_gpio(GPIO_ENET_TDATA00); + imxrt_config_gpio(GPIO_ENET_TDATA01); + imxrt_config_gpio(GPIO_ENET_TX_CLK); + imxrt_config_gpio(GPIO_ENET_TX_EN); +#ifdef GPIO_ENET_RX_ER + imxrt_config_gpio(GPIO_ENET_RX_ER); +#endif /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */ @@ -2533,7 +2543,7 @@ int imxrt_netinitialize(int intf) mac = priv->dev.d_mac.ether.ether_addr_octet; uidml |= 0x00000200; - uidml &= 0x0000FEFF; + uidml &= 0x0000feff; mac[0] = (uidml & 0x0000ff00) >> 8; mac[1] = (uidml & 0x000000ff); diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c index a8a956a94b3..0997c1fb63c 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.c +++ b/arch/arm/src/imxrt/imxrt_gpio.c @@ -1,8 +1,9 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_gpio.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Dave Marples * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -101,6 +102,7 @@ static const uint8_t g_gpio1_padmux[IMXRT_GPIO_NPINS] = IMXRT_PADMUX_GPIO_AD_B1_15_INDEX /* GPIO1 Pin 31 */ }; +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] = { IMXRT_PADMUX_GPIO_B0_00_INDEX, /* GPIO2 Pin 0 */ @@ -140,6 +142,50 @@ static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] = IMXRT_PADMUX_GPIO_B1_15_INDEX /* GPIO2 Pin 31 */ }; +#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x) +static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] = +{ + IMXRT_PADMUX_GPIO_EMC_00_INDEX, /* GPIO2 Pin 0 */ + IMXRT_PADMUX_GPIO_EMC_01_INDEX, /* GPIO2 Pin 1 */ + IMXRT_PADMUX_GPIO_EMC_02_INDEX, /* GPIO2 Pin 2 */ + IMXRT_PADMUX_GPIO_EMC_03_INDEX, /* GPIO2 Pin 3 */ + IMXRT_PADMUX_GPIO_EMC_04_INDEX, /* GPIO2 Pin 4 */ + IMXRT_PADMUX_GPIO_EMC_05_INDEX, /* GPIO2 Pin 5 */ + IMXRT_PADMUX_GPIO_EMC_06_INDEX, /* GPIO2 Pin 6 */ + IMXRT_PADMUX_GPIO_EMC_07_INDEX, /* GPIO2 Pin 7 */ + + IMXRT_PADMUX_GPIO_EMC_08_INDEX, /* GPIO2 Pin 8 */ + IMXRT_PADMUX_GPIO_EMC_09_INDEX, /* GPIO2 Pin 9 */ + IMXRT_PADMUX_GPIO_EMC_10_INDEX, /* GPIO2 Pin 10 */ + IMXRT_PADMUX_GPIO_EMC_11_INDEX, /* GPIO2 Pin 11 */ + IMXRT_PADMUX_GPIO_EMC_12_INDEX, /* GPIO2 Pin 12 */ + IMXRT_PADMUX_GPIO_EMC_13_INDEX, /* GPIO2 Pin 13 */ + IMXRT_PADMUX_GPIO_EMC_14_INDEX, /* GPIO2 Pin 14 */ + IMXRT_PADMUX_GPIO_EMC_15_INDEX, /* GPIO2 Pin 15 */ + + IMXRT_PADMUX_GPIO_EMC_16_INDEX, /* GPIO2 Pin 16 */ + IMXRT_PADMUX_GPIO_EMC_17_INDEX, /* GPIO2 Pin 17 */ + IMXRT_PADMUX_GPIO_EMC_18_INDEX, /* GPIO2 Pin 18 */ + IMXRT_PADMUX_GPIO_EMC_19_INDEX, /* GPIO2 Pin 19 */ + IMXRT_PADMUX_GPIO_EMC_20_INDEX, /* GPIO2 Pin 20 */ + IMXRT_PADMUX_GPIO_EMC_21_INDEX, /* GPIO2 Pin 21 */ + IMXRT_PADMUX_GPIO_EMC_22_INDEX, /* GPIO2 Pin 22 */ + IMXRT_PADMUX_GPIO_EMC_23_INDEX, /* GPIO2 Pin 23 */ + + IMXRT_PADMUX_GPIO_EMC_24_INDEX, /* GPIO2 Pin 24 */ + IMXRT_PADMUX_GPIO_EMC_25_INDEX, /* GPIO2 Pin 25 */ + IMXRT_PADMUX_GPIO_EMC_26_INDEX, /* GPIO2 Pin 26 */ + IMXRT_PADMUX_GPIO_EMC_27_INDEX, /* GPIO2 Pin 27 */ + IMXRT_PADMUX_GPIO_EMC_28_INDEX, /* GPIO2 Pin 28 */ + IMXRT_PADMUX_GPIO_EMC_29_INDEX, /* GPIO2 Pin 29 */ + IMXRT_PADMUX_GPIO_EMC_30_INDEX, /* GPIO2 Pin 30 */ + IMXRT_PADMUX_GPIO_EMC_31_INDEX /* GPIO2 Pin 31 */ +}; +#else +# error "Unrecognised IMXRT family member" +#endif + +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] = { IMXRT_PADMUX_GPIO_SD_B1_00_INDEX, /* GPIO3 Pin 0 */ @@ -178,7 +224,48 @@ static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] = IMXRT_PADMUX_INVALID, /* GPIO3 Pin 30 */ IMXRT_PADMUX_INVALID /* GPIO3 Pin 31 */ }; +#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x) +static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] = +{ + IMXRT_PADMUX_GPIO_EMC_32_INDEX, /* GPIO3 Pin 0 */ + IMXRT_PADMUX_GPIO_EMC_33_INDEX, /* GPIO3 Pin 1 */ + IMXRT_PADMUX_GPIO_EMC_34_INDEX, /* GPIO3 Pin 2 */ + IMXRT_PADMUX_GPIO_EMC_35_INDEX, /* GPIO3 Pin 3 */ + IMXRT_PADMUX_GPIO_EMC_36_INDEX, /* GPIO3 Pin 4 */ + IMXRT_PADMUX_GPIO_EMC_37_INDEX, /* GPIO3 Pin 5 */ + IMXRT_PADMUX_GPIO_EMC_38_INDEX, /* GPIO3 Pin 6 */ + IMXRT_PADMUX_GPIO_EMC_39_INDEX, /* GPIO3 Pin 7 */ + IMXRT_PADMUX_GPIO_EMC_40_INDEX, /* GPIO3 Pin 8 */ + IMXRT_PADMUX_GPIO_EMC_41_INDEX, /* GPIO3 Pin 9 */ + IMXRT_PADMUX_INVALID, /* GPIO3 Pin 10 */ + IMXRT_PADMUX_INVALID, /* GPIO3 Pin 11 */ + IMXRT_PADMUX_INVALID, /* GPIO3 Pin 12 */ + IMXRT_PADMUX_GPIO_SD_B0_00_INDEX, /* GPIO3 Pin 13 */ + IMXRT_PADMUX_GPIO_SD_B0_01_INDEX, /* GPIO3 Pin 14 */ + IMXRT_PADMUX_GPIO_SD_B0_02_INDEX, /* GPIO3 Pin 15 */ + + IMXRT_PADMUX_GPIO_SD_B0_03_INDEX, /* GPIO3 Pin 16 */ + IMXRT_PADMUX_GPIO_SD_B0_04_INDEX, /* GPIO3 Pin 17 */ + IMXRT_PADMUX_GPIO_SD_B0_05_INDEX, /* GPIO3 Pin 18 */ + IMXRT_PADMUX_GPIO_SD_B0_06_INDEX, /* GPIO3 Pin 19 */ + IMXRT_PADMUX_GPIO_SD_B1_00_INDEX, /* GPIO3 Pin 20 */ + IMXRT_PADMUX_GPIO_SD_B1_01_INDEX, /* GPIO3 Pin 21 */ + IMXRT_PADMUX_GPIO_SD_B1_02_INDEX, /* GPIO3 Pin 22 */ + IMXRT_PADMUX_GPIO_SD_B1_03_INDEX, /* GPIO3 Pin 23 */ + + IMXRT_PADMUX_GPIO_SD_B1_04_INDEX, /* GPIO3 Pin 24 */ + IMXRT_PADMUX_GPIO_SD_B1_05_INDEX, /* GPIO3 Pin 25 */ + IMXRT_PADMUX_GPIO_SD_B1_06_INDEX, /* GPIO3 Pin 26 */ + IMXRT_PADMUX_GPIO_SD_B1_07_INDEX, /* GPIO3 Pin 27 */ + IMXRT_PADMUX_GPIO_SD_B1_08_INDEX, /* GPIO3 Pin 28 */ + IMXRT_PADMUX_GPIO_SD_B1_09_INDEX, /* GPIO3 Pin 29 */ + IMXRT_PADMUX_GPIO_SD_B1_10_INDEX, /* GPIO3 Pin 30 */ + IMXRT_PADMUX_GPIO_SD_B1_11_INDEX, /* GPIO3 Pin 31 */ +}; +#endif + +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) static const uint8_t g_gpio4_padmux[IMXRT_GPIO_NPINS] = { IMXRT_PADMUX_GPIO_EMC_00_INDEX, /* GPIO4 Pin 0 */ @@ -217,6 +304,7 @@ static const uint8_t g_gpio4_padmux[IMXRT_GPIO_NPINS] = IMXRT_PADMUX_GPIO_EMC_30_INDEX, /* GPIO4 Pin 30 */ IMXRT_PADMUX_GPIO_EMC_31_INDEX /* GPIO4 Pin 31 */ }; +#endif static const uint8_t g_gpio5_padmux[IMXRT_GPIO_NPINS] = { @@ -262,7 +350,11 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = g_gpio1_padmux, /* GPIO1 */ g_gpio2_padmux, /* GPIO2 */ g_gpio3_padmux, /* GPIO3 */ +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) g_gpio4_padmux, /* GPIO4 */ +#else + NULL, /* GPIO4 doesn't exist on 102x */ +#endif g_gpio5_padmux, /* GPIO5 */ #if IMXRT_GPIO_NPORTS > 5 g_gpio1_padmux, /* GPIO6 */ @@ -289,7 +381,11 @@ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = , IMXRT_GPIO3_BASE #endif #if IMXRT_GPIO_NPORTS > 3 +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) , IMXRT_GPIO4_BASE +#else + , 0 +#endif #endif #if IMXRT_GPIO_NPORTS > 4 , IMXRT_GPIO5_BASE diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h index 5afb822939e..3d44e475ba1 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.h +++ b/arch/arm/src/imxrt/imxrt_gpio.h @@ -164,7 +164,7 @@ # define GPIO_ALT2 (2 << GPIO_ALT_SHIFT) /* Alternate function 2 */ # define GPIO_ALT3 (3 << GPIO_ALT_SHIFT) /* Alternate function 3 */ # define GPIO_ALT4 (4 << GPIO_ALT_SHIFT) /* Alternate function 4 */ - /* Alternate function 5 is GPIO */ +# define GPIO_ALT5 (5 << GPIO_ALT_SHIFT) /* Alternate function 5 is GPIO */ # define GPIO_ALT6 (6 << GPIO_ALT_SHIFT) /* Alternate function 6 */ # define GPIO_ALT7 (7 << GPIO_ALT_SHIFT) /* Alternate function 7 */ # define GPIO_ALT8 (8 << GPIO_ALT_SHIFT) /* Alternate function 8 */ @@ -205,6 +205,7 @@ #define GPIO_PADMUX_SHIFT (16) /* Bits 16-23: Peripheral alternate function */ #define GPIO_PADMUX_MASK (0xff << GPIO_PADMUX_SHIFT) # define GPIO_PADMUX(n) ((uint32_t)(n) << GPIO_PADMUX_SHIFT) +#define GPIO_PADMUX_GET(n) ((n&GPIO_PADMUX_MASK)>>GPIO_PADMUX_SHIFT) /* IOMUX Pin Configuration: * diff --git a/arch/arm/src/imxrt/imxrt_gpioirq.c b/arch/arm/src/imxrt/imxrt_gpioirq.c index 9d360087591..0b0461b09d4 100644 --- a/arch/arm/src/imxrt/imxrt_gpioirq.c +++ b/arch/arm/src/imxrt/imxrt_gpioirq.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_gpioirq.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -123,13 +123,18 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin) else #endif #ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ +#ifdef IMXRT_GPIO4_IMR if (irq < _IMXRT_GPIO4_0_15_BASE) +#else + if (irq < _IMXRT_GPIO5_0_15_BASE) +#endif { *regaddr = IMXRT_GPIO3_IMR; *pin = irq - _IMXRT_GPIO3_16_31_BASE + 16; } else #endif +#ifdef IMXRT_GPIO4_IMR #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ if (irq < _IMXRT_GPIO4_16_31_BASE) { @@ -146,6 +151,7 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin) } else #endif +#endif #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ if (irq < _IMXRT_GPIO5_16_31_BASE) { @@ -463,6 +469,7 @@ static int imxrt_gpio3_16_31_interrupt(int irq, FAR void *context, } #endif +#ifdef IMXRT_GPIO4_IMR #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ static int imxrt_gpio4_0_15_interrupt(int irq, FAR void *context, FAR void *arg) @@ -536,6 +543,7 @@ static int imxrt_gpio4_16_31_interrupt(int irq, FAR void *context, return OK; } #endif +#endif #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ static int imxrt_gpio5_0_15_interrupt(int irq, FAR void *context, @@ -629,7 +637,9 @@ void imxrt_gpioirq_initialize(void) putreg32(0, IMXRT_GPIO1_IMR); putreg32(0, IMXRT_GPIO2_IMR); putreg32(0, IMXRT_GPIO3_IMR); +#if defined(IMXRT_GPIO4_IMR) putreg32(0, IMXRT_GPIO4_IMR); +#endif putreg32(0, IMXRT_GPIO5_IMR); /* Disable all unconfigured GPIO interrupts at the NVIC */ @@ -652,12 +662,14 @@ void imxrt_gpioirq_initialize(void) #ifndef CONFIG_IMXRT_GPIO3_16_31_IRQ up_disable_irq(IMXRT_IRQ_GPIO3_16_31); #endif +#ifdef IMXRT_GPIO4_IMR #ifndef CONFIG_IMXRT_GPIO4_0_15_IRQ up_disable_irq(IMXRT_IRQ_GPIO4_0_15); #endif #ifndef CONFIG_IMXRT_GPIO4_16_31_IRQ up_disable_irq(IMXRT_IRQ_GPIO4_16_31); #endif +#endif #ifndef CONFIG_IMXRT_GPIO5_0_15_IRQ up_disable_irq(IMXRT_IRQ_GPIO5_0_15); #endif @@ -705,6 +717,7 @@ void imxrt_gpioirq_initialize(void) up_enable_irq(IMXRT_IRQ_GPIO3_16_31); #endif +#ifdef IMXRT_GPIO4_IMR #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO4_0_15, imxrt_gpio4_0_15_interrupt, NULL)); @@ -716,6 +729,7 @@ void imxrt_gpioirq_initialize(void) imxrt_gpio4_16_31_interrupt, NULL)); up_enable_irq(IMXRT_IRQ_GPIO4_16_31); #endif +#endif #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO5_0_15, diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.c b/arch/arm/src/imxrt/imxrt_iomuxc.c index a325715994f..3b7a15217fd 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc.c +++ b/arch/arm/src/imxrt/imxrt_iomuxc.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_irq.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -66,6 +66,7 @@ * Mux Register index. */ +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] = { /* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */ @@ -198,6 +199,111 @@ static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] = IMXRT_PADCTL_PMIC_ON_REQ_INDEX, IMXRT_PADCTL_PMIC_STBY_REQ_INDEX }; +#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x) +static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] = +{ + /* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */ + + IMXRT_PADCTL_GPIO_EMC_00_INDEX, + IMXRT_PADCTL_GPIO_EMC_01_INDEX, + IMXRT_PADCTL_GPIO_EMC_02_INDEX, + IMXRT_PADCTL_GPIO_EMC_03_INDEX, + IMXRT_PADCTL_GPIO_EMC_04_INDEX, + IMXRT_PADCTL_GPIO_EMC_05_INDEX, + IMXRT_PADCTL_GPIO_EMC_06_INDEX, + IMXRT_PADCTL_GPIO_EMC_07_INDEX, + IMXRT_PADCTL_GPIO_EMC_08_INDEX, + IMXRT_PADCTL_GPIO_EMC_09_INDEX, + IMXRT_PADCTL_GPIO_EMC_10_INDEX, + IMXRT_PADCTL_GPIO_EMC_11_INDEX, + IMXRT_PADCTL_GPIO_EMC_12_INDEX, + IMXRT_PADCTL_GPIO_EMC_13_INDEX, + IMXRT_PADCTL_GPIO_EMC_14_INDEX, + IMXRT_PADCTL_GPIO_EMC_15_INDEX, + IMXRT_PADCTL_GPIO_EMC_16_INDEX, + IMXRT_PADCTL_GPIO_EMC_17_INDEX, + IMXRT_PADCTL_GPIO_EMC_18_INDEX, + IMXRT_PADCTL_GPIO_EMC_19_INDEX, + IMXRT_PADCTL_GPIO_EMC_20_INDEX, + IMXRT_PADCTL_GPIO_EMC_21_INDEX, + IMXRT_PADCTL_GPIO_EMC_22_INDEX, + IMXRT_PADCTL_GPIO_EMC_23_INDEX, + IMXRT_PADCTL_GPIO_EMC_24_INDEX, + IMXRT_PADCTL_GPIO_EMC_25_INDEX, + IMXRT_PADCTL_GPIO_EMC_26_INDEX, + IMXRT_PADCTL_GPIO_EMC_27_INDEX, + IMXRT_PADCTL_GPIO_EMC_28_INDEX, + IMXRT_PADCTL_GPIO_EMC_29_INDEX, + IMXRT_PADCTL_GPIO_EMC_30_INDEX, + IMXRT_PADCTL_GPIO_EMC_31_INDEX, + IMXRT_PADCTL_GPIO_EMC_32_INDEX, + IMXRT_PADCTL_GPIO_EMC_33_INDEX, + IMXRT_PADCTL_GPIO_EMC_34_INDEX, + IMXRT_PADCTL_GPIO_EMC_35_INDEX, + IMXRT_PADCTL_GPIO_EMC_36_INDEX, + IMXRT_PADCTL_GPIO_EMC_37_INDEX, + IMXRT_PADCTL_GPIO_EMC_38_INDEX, + IMXRT_PADCTL_GPIO_EMC_39_INDEX, + IMXRT_PADCTL_GPIO_EMC_40_INDEX, + IMXRT_PADCTL_GPIO_EMC_41_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_00_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_01_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_02_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_03_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_04_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_05_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_06_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_07_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_08_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_09_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_10_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_11_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_12_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_13_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_14_INDEX, + IMXRT_PADCTL_GPIO_AD_B0_15_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_00_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_01_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_02_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_03_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_04_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_05_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_06_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_07_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_08_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_09_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_10_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_11_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_12_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_13_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_14_INDEX, + IMXRT_PADCTL_GPIO_AD_B1_15_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_00_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_01_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_02_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_03_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_04_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_05_INDEX, + IMXRT_PADCTL_GPIO_SD_B0_06_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_00_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_01_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_02_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_03_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_04_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_05_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_06_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_07_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_08_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_09_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_10_INDEX, + IMXRT_PADCTL_GPIO_SD_B1_11_INDEX, + IMXRT_PADCTL_WAKEUP_INDEX, + IMXRT_PADCTL_PMIC_ON_REQ_INDEX, + IMXRT_PADCTL_PMIC_STBY_REQ_INDEX +}; +#else +#error Unrecognised IMXRT family +#endif /**************************************************************************** * Public Functions diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c index 2899d4e0559..b4dd258fc43 100644 --- a/arch/arm/src/imxrt/imxrt_lpi2c.c +++ b/arch/arm/src/imxrt/imxrt_lpi2c.c @@ -1617,7 +1617,7 @@ static int imxrt_lpi2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg priv->msgc = count; priv->flags = msgs->flags; - i2cinfo("Flags %d, len %d \n", msgs->flags, msgs->length); + i2cinfo("Flags %x, len %d \n", msgs->flags, msgs->length); /* Reset I2C trace logic */ @@ -1651,23 +1651,27 @@ static int imxrt_lpi2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg { /* Bus Error */ + i2cerr("Bus error\n"); ret = -EIO; } else if (status & LPI2C_MSR_ALF) { /* Arbitration Lost (master mode) */ + i2cerr("Arbitration lost\n"); ret = -EAGAIN; } else if (status & LPI2C_MSR_NDF) { /* Acknowledge Failure */ + i2cerr("Ack failure\n"); ret = -ENXIO; } else { - ret = -EINTR; + i2cerr("Unspecified error\n"); + ret = -EINTR; } } diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index a0e64508eec..40204831593 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -1577,8 +1577,8 @@ void up_serialinit(void) int up_putc(int ch) { -#ifdef HAVE_USART_CONSOLE - struct lpc54_dev_s *priv = (struct lpc54_dev_s *)CONSOLE_DEV.priv; +#ifdef CONSOLE_DEV + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)CONSOLE_DEV.priv; uint32_t ie; imxrt_disableuartint(priv, &ie); @@ -1589,11 +1589,11 @@ int up_putc(int ch) { /* Add CR */ - up_lowputc('\r'); + imxrt_lowputc('\r'); } - up_lowputc(ch); - imxrt_restoreuartint(priv, intset); + imxrt_lowputc(ch); + imxrt_restoreuartint(priv, ie); #endif return ch; diff --git a/arch/arm/src/imxrt/imxrt_timerisr.c b/arch/arm/src/imxrt/imxrt_timerisr.c index 666d5e2e762..817b9e1b962 100644 --- a/arch/arm/src/imxrt/imxrt_timerisr.c +++ b/arch/arm/src/imxrt/imxrt_timerisr.c @@ -54,6 +54,7 @@ #include "up_arch.h" #include "chip.h" +#include "chip/imxrt_ccm.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c index 77c0bb652d7..5de359050b3 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.c +++ b/arch/arm/src/imxrt/imxrt_usdhc.c @@ -1294,11 +1294,11 @@ static sdio_statset_t imxrt_status(FAR struct sdio_dev_s *dev) { struct imxrt_dev_s *priv = (struct imxrt_dev_s *)dev; - /* This register reflects the state of CD no matter if it's a separate pin - * or DAT3 - */ - +#if defined(CONFIG_MMCSD_HAVE_CARDDETECT) && defined(PIN_USDHC1_CD) + if (!imxrt_gpio_read(PIN_USDHC1_CD)) +#else if ((getreg32(IMXRT_USDHC1_PRSSTAT) & USDHC_PRSSTAT_CINS) != 0) +#endif { priv->cdstatus |= SDIO_STATUS_PRESENT; } diff --git a/arch/arm/src/imxrt/imxrt_xbar.c b/arch/arm/src/imxrt/imxrt_xbar.c index 33ff302d556..43ae264d9e4 100644 --- a/arch/arm/src/imxrt/imxrt_xbar.c +++ b/arch/arm/src/imxrt/imxrt_xbar.c @@ -58,7 +58,9 @@ static const uintptr_t g_xbars_addresses[] = { IMXRT_XBAR1_BASE, IMXRT_XBAR2_BASE, +#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x)) IMXRT_XBAR3_BASE +#endif }; /**************************************************************************** diff --git a/arch/arm/src/imxrt/imxrt_xbar.h b/arch/arm/src/imxrt/imxrt_xbar.h index 11a299c4d46..6636cd9c16b 100644 --- a/arch/arm/src/imxrt/imxrt_xbar.h +++ b/arch/arm/src/imxrt/imxrt_xbar.h @@ -113,390 +113,8 @@ #define IMXRT_XBAR(six) ((six) & IMXRT_XBARA_INDEX_MASK) >> IMXRT_XBARA_INDEX_SHIFTS #define IMXRT_SIDE(six) ((six) & IMXRT_XBARA_SIDE_MASK) >> IMXRT_XBARA_SIDE_SHIFTS -/* XBARA1 Mux inputs (I values) *********************************************************************************************************************************************************************************/ - -#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ -#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02 IMXRT_XBARA1(XBAR_INPUT, 2) /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03 IMXRT_XBARA1(XBAR_INPUT, 3) /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20 IMXRT_XBARA1(XBAR_INPUT, 20) /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21 IMXRT_XBARA1(XBAR_INPUT, 21) /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22 IMXRT_XBARA1(XBAR_INPUT, 22) /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23 IMXRT_XBARA1(XBAR_INPUT, 23) /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24 IMXRT_XBARA1(XBAR_INPUT, 24) /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25 IMXRT_XBARA1(XBAR_INPUT, 25) /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ -#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ -#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ -#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ -#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ -#define IMXRT_XBARA1_IN_RESERVED30 IMXRT_XBARA1(XBAR_INPUT, 30) /* XBARA1_IN30 input is reserved. */ -#define IMXRT_XBARA1_IN_RESERVED31 IMXRT_XBARA1(XBAR_INPUT, 31) /* XBARA1_IN31 input is reserved. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ -#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 35) /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 36) /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 37) /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 38) /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ -#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT IMXRT_XBARA1(XBAR_INPUT, 39) /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 40) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 41) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 42) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 43) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 44) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 45) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 48) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 49) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 50) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 51) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 52) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 53) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 54) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ -#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARA1(XBAR_INPUT, 55) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ -#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ -#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ -#define IMXRT_XBARA1_IN_ENC3_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 62) /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ -#define IMXRT_XBARA1_IN_ENC4_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 63) /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT0 IMXRT_XBARA1(XBAR_INPUT, 76) /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT1 IMXRT_XBARA1(XBAR_INPUT, 77) /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT2 IMXRT_XBARA1(XBAR_INPUT, 78) /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */ -#define IMXRT_XBARA1_IN_AOI2_OUT3 IMXRT_XBARA1(XBAR_INPUT, 79) /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ - -/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ - -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 2) /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ -#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 3) /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 4) /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 5) /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 6) /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 7) /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 8) /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 9) /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 10) /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 11) /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 12) /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 13) /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 14) /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 15) /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 16) /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 17) /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 18) /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ -#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 19) /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ -#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 20) /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ -#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ -#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 24) /* XBARA1_OUT24 output is reserved. */ -#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 25) /* XBARA1_OUT25 output is reserved. */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 29) /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 30) /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 31) /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 32) /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 33) /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 34) /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 35) /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 36) /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 37) /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 38) /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 39) /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 40) /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 41) /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 42) /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 43) /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 44) /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 45) /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 46) /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 47) /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 48) /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 52) /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 53) /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 54) /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 55) /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 56) /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 57) /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 58) /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 59) /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 60) /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 61) /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 62) /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 63) /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 64) /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ -#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 65) /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ -#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */ -#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 69) /* XBARA1_OUT69 output assigned to ENC1_HOME */ -#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 70) /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 71) /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 72) /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */ -#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */ -#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 76) /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 77) /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 78) /* XBARA1_OUT78 output assigned to ENC3_INDEX */ -#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 79) /* XBARA1_OUT79 output assigned to ENC3_HOME */ -#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 80) /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */ -#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 81) /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */ -#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 82) /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */ -#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 83) /* XBARA1_OUT83 output assigned to ENC4_INDEX */ -#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 84) /* XBARA1_OUT84 output assigned to ENC4_HOME */ -#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 85) /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 89) /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 90) /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 91) /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 95) /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 96) /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 97) /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 98) /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 99) /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 100) /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */ -#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 101) /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */ -#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 105) /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 106) /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107) /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108) /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109) /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ -#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110) /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ -#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 111) /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 112) /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 113) /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 114) /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 115) /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 116) /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 117) /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 118) /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 119) /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 120) /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 121) /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 122) /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 123) /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 124) /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 125) /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */ -#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ -#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ -#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ -#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ - -/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ - -#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ -#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ -#define IMXRT_XBARB2_IN_RESERVED2 IMXRT_XBARB2(XBAR_INPUT, 2) /* XBARB2_IN2 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED3 IMXRT_XBARB2(XBAR_INPUT, 3) /* XBARB2_IN3 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED4 IMXRT_XBARB2(XBAR_INPUT, 4) /* XBARB2_IN4 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED5 IMXRT_XBARB2(XBAR_INPUT, 5) /* XBARB2_IN5 input is reserved. */ -#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ -#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ -#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ -#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ -#define IMXRT_XBARB2_IN_RESERVED10 IMXRT_XBARB2(XBAR_INPUT, 10) /* XBARB2_IN10 input is reserved. */ -#define IMXRT_XBARB2_IN_RESERVED11 IMXRT_XBARB2(XBAR_INPUT, 11) /* XBARB2_IN11 input is reserved. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ -#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ -#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT IMXRT_XBARB2(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ -#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB2(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ -#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ -#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ -#define IMXRT_XBARB2_IN_ENC3_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ -#define IMXRT_XBARB2_IN_ENC4_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ - -/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ - -#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ -#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ -#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ -#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ -#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ -#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ -#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ -#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ -#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ -#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ -#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ -#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ -#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ -#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ -#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ -#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ - -/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/ - -#define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */ -#define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */ -#define IMXRT_XBARB3_IN_RESERVED2 IMXRT_XBARB3(XBAR_INPUT, 2) /* XBARB3_IN2 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED3 IMXRT_XBARB3(XBAR_INPUT, 3) /* XBARB3_IN3 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED4 IMXRT_XBARB3(XBAR_INPUT, 4) /* XBARB3_IN4 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED5 IMXRT_XBARB3(XBAR_INPUT, 5) /* XBARB3_IN5 input is reserved. */ -#define IMXRT_XBARB3_IN_ACMP1_OUT IMXRT_XBARB3(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB3_IN6 input. */ -#define IMXRT_XBARB3_IN_ACMP2_OUT IMXRT_XBARB3(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB3_IN7 input. */ -#define IMXRT_XBARB3_IN_ACMP3_OUT IMXRT_XBARB3(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB3_IN8 input. */ -#define IMXRT_XBARB3_IN_ACMP4_OUT IMXRT_XBARB3(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB3_IN9 input. */ -#define IMXRT_XBARB3_IN_RESERVED10 IMXRT_XBARB3(XBAR_INPUT, 10) /* XBARB3_IN10 input is reserved. */ -#define IMXRT_XBARB3_IN_RESERVED11 IMXRT_XBARB3(XBAR_INPUT, 11) /* XBARB3_IN11 input is reserved. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ -#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 15) /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT IMXRT_XBARB3(XBAR_INPUT, 16) /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT IMXRT_XBARB3(XBAR_INPUT, 17) /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT IMXRT_XBARB3(XBAR_INPUT, 18) /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ -#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT IMXRT_XBARB3(XBAR_INPUT, 19) /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 20) /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 21) /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 22) /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 23) /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 24) /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 25) /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 28) /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 29) /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 30) /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 31) /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 32) /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 33) /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 34) /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ -#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01 IMXRT_XBARB3(XBAR_INPUT, 35) /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ -#define IMXRT_XBARB3_IN_PIT_TRIGGER0 IMXRT_XBARB3(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ -#define IMXRT_XBARB3_IN_PIT_TRIGGER1 IMXRT_XBARB3(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB3(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB3(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB3(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB3(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB3(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB3(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB3(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ -#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB3(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ -#define IMXRT_XBARB3_IN_ENC1_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ -#define IMXRT_XBARB3_IN_ENC2_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ -#define IMXRT_XBARB3_IN_ENC3_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 48) /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ -#define IMXRT_XBARB3_IN_ENC4_POS_MATCH IMXRT_XBARB3(XBAR_INPUT, 49) /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE0 IMXRT_XBARB3(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB3_IN50 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE1 IMXRT_XBARB3(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB3_IN51 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE2 IMXRT_XBARB3(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB3_IN52 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE3 IMXRT_XBARB3(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB3_IN53 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE4 IMXRT_XBARB3(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB3_IN54 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE5 IMXRT_XBARB3(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB3_IN55 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */ -#define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */ - -/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/ - -#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */ -#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */ -#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 2) /* XBARB3_OUT2 output assigned to AOI2_IN02 */ -#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 3) /* XBARB3_OUT3 output assigned to AOI2_IN03 */ -#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 4) /* XBARB3_OUT4 output assigned to AOI2_IN04 */ -#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 5) /* XBARB3_OUT5 output assigned to AOI2_IN05 */ -#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 6) /* XBARB3_OUT6 output assigned to AOI2_IN06 */ -#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 7) /* XBARB3_OUT7 output assigned to AOI2_IN07 */ -#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 8) /* XBARB3_OUT8 output assigned to AOI2_IN08 */ -#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 9) /* XBARB3_OUT9 output assigned to AOI2_IN09 */ -#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 10) /* XBARB3_OUT10 output assigned to AOI2_IN10 */ -#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 11) /* XBARB3_OUT11 output assigned to AOI2_IN11 */ -#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 12) /* XBARB3_OUT12 output assigned to AOI2_IN12 */ -#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 13) /* XBARB3_OUT13 output assigned to AOI2_IN13 */ -#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 14) /* XBARB3_OUT14 output assigned to AOI2_IN14 */ -#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 15) /* XBARB3_OUT15 output assigned to AOI2_IN15 */ +/* Collect correct XBAR definitions from chip file */ +#include "chip/imxrt_xbar.h" /************************************************************************************************************************************************** * Public Functions diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index bb7efc789b7..2c25ed0ea25 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -2504,7 +2504,7 @@ static int sam_phyintenable(struct sam_emac_s *priv) /* Enable link up/down interrupts */ ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT, - (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN)); + (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN)); } /* Disable management port (probably) */ diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 4447bddfe57..a77c7090e90 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -2539,7 +2539,7 @@ static int sam_phyintenable(struct sam_emac_s *priv) /* Enable link up/down interrupts */ ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT, - (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN)); + (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN)); } /* Disable management port (probably) */ diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 6807fa4f6a6..3d102b83ccb 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -2982,7 +2982,7 @@ static int sam_phyintenable(struct sam_emac_s *priv) uint16_t phyval; int ret; - /* Does this MAC support a KSZ80x1 PHY? */ + /* Does this MAC support a KSZ80X1 PHY? */ if (priv->phytype == SAMA5_PHY_KSZ8051 || priv->phytype == SAMA5_PHY_KSZ8081) { @@ -3001,7 +3001,7 @@ static int sam_phyintenable(struct sam_emac_s *priv) /* Enable link up/down interrupts */ ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT, - (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN)); + (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN)); } /* Disable management port (probably) */ diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index 4432bf74451..6a2039ab70d 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -3462,7 +3462,7 @@ static int sam_phyintenable(struct sam_emac_s *priv) uint16_t phyval; int ret; - /* Does this MAC support a KSZ80x1 PHY? */ + /* Does this MAC support a KSZ80X1 PHY? */ if (priv->phytype == SAMV7_PHY_KSZ8051 || priv->phytype == SAMV7_PHY_KSZ8061 || @@ -3483,7 +3483,7 @@ static int sam_phyintenable(struct sam_emac_s *priv) /* Enable link up/down interrupts */ ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT, - (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN)); + (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN)); } /* Disable management port (probably) */ diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index 406fdfc963c..974ebcf11ba 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -206,7 +206,7 @@ # error missing logic # elif defined( CONFIG_ETH0_PHY_KSZ8081) # define MII_INT_REG MII_KSZ8081_INT -# define MII_INT_SETEN MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN +# define MII_INT_SETEN MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN # define MII_INT_CLREN 0 # elif defined( CONFIG_ETH0_PHY_KSZ90x1) # error missing logic diff --git a/configs/imxrt1050-evk/include/board.h b/configs/imxrt1050-evk/include/board.h index 9cfd9ddb2c4..257a9156b26 100644 --- a/configs/imxrt1050-evk/include/board.h +++ b/configs/imxrt1050-evk/include/board.h @@ -206,6 +206,14 @@ #define BOARD_USDHC_SD4MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 #define BOARD_USDHC_SD4MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) +/* ETH Disambiguation ***************************************************************/ +#define GPIO_ENET_MDIO GPIO_ENET_MDIO_3 +#define GPIO_ENET_MDC GPIO_ENET_MDC_3 +#define GPIO_ENET_RX_EN GPIO_ENET_RX_EN_1 +#define GPIO_ENET_RX_ER GPIO_ENET_RX_ER_1 +#define GPIO_ENET_TX_CLK GPIO_ENET_TX_CLK_1 +#define GPIO_ENET_TX_EN GPIO_ENET_TX_EN_1 + /* PIO Disambiguation ***************************************************************/ /* LPUARTs diff --git a/configs/imxrt1060-evk/include/board.h b/configs/imxrt1060-evk/include/board.h index a77946df855..d0153fdd3b7 100644 --- a/configs/imxrt1060-evk/include/board.h +++ b/configs/imxrt1060-evk/include/board.h @@ -1,9 +1,10 @@ /************************************************************************************ * configs/imxrt1060/include/board.h * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane + * Dave Marples * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -197,6 +198,15 @@ #define BOARD_USDHC_SD4MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 #define BOARD_USDHC_SD4MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) +/* ETH Disambiguation ***************************************************************/ + +#define GPIO_ENET_MDIO GPIO_ENET_MDIO_3 +#define GPIO_ENET_MDC GPIO_ENET_MDC_3 +#define GPIO_ENET_RX_EN GPIO_ENET_RX_EN_1 +#define GPIO_ENET_RX_ER GPIO_ENET_RX_ER_1 +#define GPIO_ENET_TX_CLK GPIO_ENET_TX_CLK_1 +#define GPIO_ENET_TX_EN GPIO_ENET_TX_EN_1 + /* PIO Disambiguation ***************************************************************/ /* LPUARTs * diff --git a/drivers/i2c/i2c_driver.c b/drivers/i2c/i2c_driver.c index 9a3e659d9df..b3aeaae6a68 100644 --- a/drivers/i2c/i2c_driver.c +++ b/drivers/i2c/i2c_driver.c @@ -241,7 +241,7 @@ static int i2cdrvr_ioctl(FAR struct file *filep, int cmd, unsigned long arg) FAR struct i2c_transfer_s *transfer; int ret; - i2cinfo("cmd=%d arg=%lu\n", cmd, arg); + i2cinfo("cmd=%x arg=%08x\n", cmd, arg); /* Get our private data structure */ diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index be7fd548be3..74f7de76f34 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -97,7 +97,7 @@ #define MMCSD_SCR_DATADELAY (100) /* Wait up to 100MS to get SCR */ #define MMCSD_BLOCK_RDATADELAY (100) /* Wait up to 100MS to get one data block */ -#define MMCSD_BLOCK_WDATADELAY (230) /* Wait up to 230MS to write one data block */ +#define MMCSD_BLOCK_WDATADELAY (260) /* Wait up to 260MS to write one data block */ #define IS_EMPTY(priv) (priv->type == MMCSD_CARDTYPE_UNKNOWN) diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h index e4e915e70cf..c7cb4f1f9cf 100644 --- a/include/nuttx/net/mii.h +++ b/include/nuttx/net/mii.h @@ -1,7 +1,8 @@ /**************************************************************************** * include/nuttx/net/mii.h * - * Copyright (C) 2008-2010, 2012-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2010, 2012-2015, 2019 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -369,6 +370,24 @@ #define MII_LAN8720_SPSCR_ANEGDONE (1 << 12) /* Bit 12: Autonegotiation complete */ /* Bits 13-15: Reserved */ +/* SMSC LAN8720 MODES register bits */ + +#define MII_LAN8720_MODES_PHYAD_SHIFT (0) /* Bits 0-4: Phy Address */ +#define MII_LAN8720_MODES_PHYAD_MASK (0x1f << MII_LAN8720_MODES_PHYAD_SHIFT) +#define MII_LAN8720_MODES_PHYAD(n) ((n<