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jjlange
2019-07-09 12:30:01 -05:00
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COPYING
+51 -33
View File
@@ -1,29 +1,47 @@
COPYING -- Describes the terms under which Nuttx is distributed. A copy of
the BSD-style licensing is included in this file. In my words -- I believe
that you should free to use NuttX in any environment, private, private,
commercial, open, closed, etc. provided only that you respect the modest
copyright notices as described in license (below), respect Trademarks, and
include a copy of the BSD license. Please feel free to contact me if you
have any licensing concerns.
COPYING
=======
Copyright Date Notation: Copyright information is provided in the header
of each file. This copyright information includes the name of the copyright
holder and the year(s) in which copyrighted additions to the file were made
to the file. A comma (',') is used to separate years in the list of years.
A hyphen ('-') is used as a more compact notation when additions were made
over several consecutive years. So for example, "2007, 2011" would mean
that copyrighted additions were made during the years of 2007 and 2011
whereas "2007-2011" would indicate copyrighted additions in the years 2007,
2008, 2009, 2010, and 2011.
Describes the terms under which Nuttx is distributed. A copy of the BSD-
style licensing is included in this file. In my words -- I believe that you
should free to use NuttX in any environment, private, private, commercial,
open, closed, etc. provided only that you respect the modest copyright
notices as described in license (below), respect Trademarks, and include a
copy of the BSD license. Please feel free to contact me if you have any
icensing concerns.
Copyright Line Continuation: Copy information which exceeds the usable line
lengh may be broken and continued on the following line, such as:
Tool Licenses
-------------
Tools under the nuttx/tools directory are not intended for binary
distribution. You may find other licensing on individual tools in that
directory. If you intend to redistribute these tools in binary form, please
respect the individual license of each tool as identified in the file header
of the tool source files.
Copyright Date Notation
-----------------------
Copyright information is provided in the header of each file. This
copyright information includes the name of the copyright holder and the
year(s) in which copyrighted additions to the file were made to the file.
A comma (',') is used to separate years in the list of years. A hyphen ('-')
is used as a more compact notation when additions were made over several
consecutive years. So for example, "2007, 2011" would mean that copyrighted
additions were made during the years of 2007 and 2011 whereas "2007-2011"
would indicate copyrighted additions in the years 2007, 2008, 2009, 2010,
and 2011.
Copyright Line Continuation
---------------------------
Copy information which exceeds the usable line lengh may be broken and
continued on the following line, such as:
Copyright (C) 2007-2010, 2012, 2014-2015, 2017 Gregory Nutt. All
rights reserved.
NuttX
^^^^^
=====
License for NuttX in general (authorship and copyright dates on individual
files will vary):
@@ -64,7 +82,7 @@ files will vary):
****************************************************************************/
FAT Long File Names
^^^^^^^^^^^^^^^^^^^
===================
NOTE: If CONFIG_FAT_LFN is defined in your NuttX configuration file, then
there may be some legal, patent issues. The following was extracted from
@@ -99,7 +117,7 @@ FAT Long File Names
So you have been forewarned: Use the long filename at your own risk!
uIP
^^^
===
Many lower-level networking components of NuttX derive from uIP which
has a similar BSD style license:
@@ -108,7 +126,7 @@ has a similar BSD style license:
All rights reserved.
IGMP
^^^^
===
IGMP support, if enabled, adds additional logic by Steve Reynolds:
@@ -116,7 +134,7 @@ IGMP support, if enabled, adds additional logic by Steve Reynolds:
All rights reserved.
The HID Parser in drivers/usbhost
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
=================================
Adapted from the LUFA Library (MIT license):
@@ -144,8 +162,8 @@ The HID Parser in drivers/usbhost
Certain functions in the NuttX C-library derive from other BSD-compatible
sources:
fs/nfs:
^^^^^^^
fs/nfs
======
NFS:
@@ -166,7 +184,7 @@ fs/nfs:
California, Berkeley and its contributors."
fs/spiffs
^^^^^^^^^
=========
The MIT License (MIT)
@@ -189,14 +207,14 @@ fs/spiffs
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
strtod():
^^^^^^^^
strtod()
========
Copyright (C) 2002 Michael Ringgaard. All rights reserved.
Copyright (C) 2006-2007 H. Peter Anvin.
dtoa():
^^^^^^
dtoa()
======
If you enable floating point conversions with CONFIG_LIBC_FLOATINGPOINT,
then some files with an unmodified BSD license will be included. That
@@ -207,7 +225,7 @@ dtoa():
California, Berkeley and its contributors."
libc/string/lib_vikmemcpy.c
^^^^^^^^^^^^^^^^^^^^^^^^^^^
===========================
If you enable CONFIG_MEMCPY_VIK, then you will build with the optimized
version of memcpy from Daniel Vik. Licensing information for that version
@@ -236,7 +254,7 @@ libc/string/lib_vikmemcpy.c
distribution.
libs/libc/math
^^^^^^^^^^^^^^
==============
If you enable CONFIG_LIB, you will build the math library at libc/math.
This library was taken from the math library developed for the Rhombus
@@ -258,7 +276,7 @@ libs/libc/math
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
drivers/video/ov2640
^^^^^^^^^^^^^^^^^^^^
====================
WARNING: Some of the information in the data tables in this file came
from other projects with conflicting licenses: Linux and ArduCAM. Those
Documentation/NuttXCCodingStandard.html
+182 -27
View File
@@ -17,7 +17,9 @@
</table>
<ul>
<b>1.0 <a href="#general">General Conventions</a></b>
<p>
<b>1.0 <a href="#general">General Conventions</a></b>
</p>
<ul>
1.1 <a href="#fileorganization">File Organization</a></br>
1.2 <a href="#lines">Lines</a><br>
@@ -26,7 +28,9 @@
1.5 <a href="#indentation">Indentation</a><br>
1.6 <a href="#parentheses">Parentheses</a><br>
</ul>
<b>2.0 <a href="#datatypes">Data and Type Definitions</a></b>
<p>
<b>2.0 <a href="#datatypes">Data and Type Definitions</a></b>
</p>
<ul>
2.1 <a href="#onedatperline">One Definition/Declaration Per Line</a><br>
2.2 <a href="#globalvariable">Global Variables</a><br>
@@ -39,7 +43,9 @@
2.9 <a href="#pointers">Pointer Variables</a><br>
2.10 <a href="#initializers">Initializers</a>
</ul>
<b>3.0 <a href="#functions">Functions</a></b>
<p>
<b>3.0 <a href="#functions">Functions</a></b>
</p>
<ul>
3.1 <a href="#funcheaders">Function Headers</a><br>
3.2 <a href="#funcname">Function Names</a><br>
@@ -47,7 +53,9 @@
3.4 <a href="#funcbody">Function Body</a><br>
3.5 <a href="#retvalues">Returned Values</a>
</ul>
<b>4.0 <a href="#statements">Statements</a></b>
<p>
<b>4.0 <a href="#statements">Statements</a></b>
</p>
<ul>
4.1 <a href="#onestatement">One Statement Per Line</a><br>
4.2 <a href="#casts">Casts</a><br>
@@ -58,7 +66,12 @@
4.7 <a href="#dowhile"><code>do while</code> Statement</a><br>
4.8 <a href="#goto">Use of <code>goto</code></a>
</ul>
<b><a href="#appndxa">Appendix A</a></b>
<p>
<b>5.0 <a href="#cplusplus">C++</a></b>
</p>
<p>
<b><a href="#appndxa">Appendix A</a></b>
</p>
<ul>
<a href="#cfilestructure">A.1 C Source File Structure</a><br>
<a href="#hfilestructure">A.2 C Header File Structure</a>
@@ -74,7 +87,7 @@
<h1><big><font color="#3c34ec">
<i>NuttX C Coding Standard</i>
</font></big></h1>
<p>Last Updated: February 5, 2019</p>
<p>Last Updated: July 6, 2019</p>
</td>
</tr>
</table>
@@ -247,7 +260,7 @@
<p>
<b>Forming Guard Names</b>.
Then pre-processor macro name used in the guard is formed from the full, relative path to the header for from the top-level, controlled directory.
That pat is preceded by <code>__</code> and <code>_</code> replaces each character that would otherwise be invalid in a macro name.
That path is preceded by <code>__</code> and <code>_</code> replaces each character that would otherwise be invalid in a macro name.
So, for example, __INCLUDE_NUTTX_ARCH_H corresponds to the header file <code>include/nuttx/arch.h</code>
</p>
@@ -1026,6 +1039,16 @@ int animals(int animal)
<b>Indentation of Pre-Processor Lines</b>.
C Pre-processor commands following any conditional computation are also indented following basically the indentation same rules, differing in that the <code>#</code> always remains in column 1.
</p>
<p>
When C pre-processor statements are indented, they should be should be indented by 2 spaces per level-of-indentation following the <code>#</code>.
C pre-processor statements should be indented when they are enclosed within C pre-processor conditional logic (<code>#if</code>..<code>#endif</code>). The level of indentation increases with each level of such nested conditional logic.
</p>
<p>
C pre-processor statements should always be indented in this way in the <code>Pre-processor Definitions</code> <a href="#cfilestructure">section</a> of each file.
C pre-processor statements may be indented in the <code>Public/Private Data</code> and <code>Public/Private Functions</code> sections of the file.
However, often the indentation of C pre-processor statements conflicts with the indentation of the C code and makes the code more difficult to read.
In such cases, indentation of C pre-processor statements should be ommitted in those sections (only).
</p>
<center><table width="60%" border=1>
<tr><td bgcolor="white">
@@ -1802,6 +1825,10 @@ enum xyz_state_e
<b>Side effects</b>.
Be careful of side effects.
</li>
<li>
<b>Indentation</b>.
See the <a href="#indentation">Indentation of Pre-Processor Lines</a> requirements above.
</li>
</ul>
<p>
<b>Other Applicable Coding Standards</b>.
@@ -2065,7 +2092,14 @@ ptr = (FAR struct somestruct_s *)value;
As a rule of thumb, the length of a function should be limited so that it would fit on a single page (if you were to print the source code).
</li>
<li>
<b>Space after the function body</b>
<b>Return Statement</b>.
The argument of the <code>return</code> statement should <i>not</i> be enclosed in parentheses.
A reasonable exception is the case where the returned value argument is a complex expression and where the parentheses improve the readability of the code.
Such complex expressions might be Boolean expressions or expressions containing conditions.
Simple arithmetic computations would not be considered <i>complex</i> expressions.
</li>
<li>
<b>Space after the function body</b>.
A one (and only one) blank line must follow the closing right brace of the function body.
</li>
</ul>
@@ -2094,7 +2128,7 @@ ptr = (FAR struct somestruct_s *)value;
}
}
return e / a;
return (e / a);
}
</ul></pre></font>
</td></tr>
@@ -2102,28 +2136,28 @@ ptr = (FAR struct somestruct_s *)value;
<p><font color="green"><b>Correct</b></p>
<ul><pre>
int myfunction(int a, int b)
{
int c;
int d;
int e;
int i;
{
int c;
int d;
int e;
int i;
c = a
d = b;
e = c + d;
c = a
d = b;
e = c + d;
for (i = 0; i &lt; a; i++)
{
int j;
for (i = 0; i &lt; a; i++)
{
int j;
for (j = 0; j &lt; b; j++)
{
e += j * d;
}
}
for (j = 0; j &lt; b; j++)
{
e += j * d;
}
}
return e / a;
}
return e / a;
}
</ul></pre></font>
</td></tr>
</table></center>
@@ -2720,6 +2754,127 @@ error:
See the discussion of <a href="#farnear">pointers</a> for information about the <code>FAR</code> qualifier used above.
</p>
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
<h1>5.0 <a name="cplusplus">C++</a></h1>
</td>
</tr>
</table>
<p>
There is no existing document that provides a complete coding standard for NuttX C++ files.
This section is included here to provide some minimal guidance in C++ code development.
In most details like indentation, spacing, and file organization, it is identical to the C coding standard.
But there are significant differences in the acceptable standard beyond that.
The primary differences are as follows:
</p>
<ol>
<li>
<p>
C++ style comments are not only permissible but are required (other than for the following exception).
This includes the block comments of in the <i>Source File Structure</i> described in an <a href="#appndxa">Appendix</a> to this standard.
</p>
</li>
<li>
<p>
Deoxygen tags are acceptable. As are C style comments when needed to provide DOxygen tags.
</p>
</li>
<li>
<p>
There is currently no requirement to conform any specific C++ version.
However, for portability reasons, conformance to older, pre-C++11 standards is encouraged where reasonable.
</p>
<li>
<p>
C++ file name extensions: The extension <code>.cxx</code> is used for C++ source files; the extension <code>.hxx</code> is used for C++ header files.
</p>
<li>
<p>
All naming must use <i>CamelCase</i>.
Use of the underbar character, '_' is discouraged.
This includes variables, classes, structures, ..., etc.: All user-nameable C++ elements.
Pre-processor definitions are still required to be all upper case.
</p>
</li>
<li>
<p>
Local variable, method names, and function names must all begin with a lower case letter.
As examples, <code>myLocalVariable</code> would be a compliant name for a local variable;
<code>myMethod</code> would be a compliant name for a method;
</p>
<li>
<p>
Namespaces, global variable, class, structure, template, and enumeration names begin with a capital letter identifying what is being named:
</p>
</li>
<p><ul>
<dl>
<dt>
<i>Namespace Names</i>
</dt>
<dd>
Namespaces begin with an upper case character but no particular character is specified.
As an example, <code>MyNamespace</code> is fully compliant.
</dd>
<dt>
<i>Global Variable Names</i>
</dt>
<dd>
Global variables and singletons begin with an upper case '<b>G</b>'.
For example, <code>GMyGlobalVariable</code>.
The prefix <code>g_</code> is never used.
</dd>
<dt>
<i>Implementation Class Names</i>
</dt>
<dd>
Classes that implement methods begin with an upper case '<b>C</b>'.
For example, <code>CMyClass</code>.
A fully qualified method of <code>CMyClass</code> could be <code>MyNamespace::CMyClass::myMethod</code>
</dd>
<dt>
<i>Pure Virtual Base Class Names</i>
</dt>
<dd>
Such base classes begin with an upper case '<b>I</b>'.
For example, <code>IMyInterface</code>.
</dd>
<dt>
<i>Template Class Names</i>
</dt>
<dd>
Template classes begin with an upper case '<b>T</b>'.
For example, <code>TMyTemplate</code>.
</dd>
<dt>
<i><code>typedef</code>'d Type Names</i>
</dt>
<dd>
Currently all such types also begin with an upper case '<b>T</b>'.
That probably needs some resolution to distinguish for template names.
The suffix <code>_t</code> is never used.
</dd>
<dt>
<i>Structure Names</i>
</dt>
<dd>
Structures begin with an upper case '<b>S</b>'.
For example, <code>SMyStructure</code>.
The suffix <code>_s</code> is never used.
</dd>
<dt>
<i>Enumerations Names</i>
</dt>
<dd>
Enumerations begin with an upper case '<b>E</b>'.
For example, <code>EMyEnumeration</code>.
The suffix <code>_e</code> is never used.
</ul></p>
</dl>
</ol>
<table width ="100%">
<tr bgcolor="#e4e4e4">
<td>
Documentation/README.html
+4 -1
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@@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
<p>Last Updated: June 4, 2019</p>
<p>Last Updated: June 17, 2019</p>
</td>
</tr>
</table>
@@ -160,6 +160,7 @@ nuttx/
| |- lpcxpresso-lpc54628/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/lpcxpresso-lpc54628/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- makerlisp/
| | |- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/makerlisp/nsh/README.txt" target="_blank">nsh/README.txt</a>
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/makerlisp/README.txt" target="_blank"><b><i>README.txt</i></b></a>\
| |- maple/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/maple/README.txt" target="_blank"><b><i>README.txt</i></b></a>\
@@ -253,6 +254,8 @@ nuttx/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pic32mx7mmb/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- pic32mz-starterkit/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pic32mz-starterkit/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- pnev5180b/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pnev5180b/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- qemu-i486/
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/qemu-i486/README.txt" target="_blank"><b><i>README.txt</i></b></a>
| |- sabre-6quad/
Kconfig
+11
View File
@@ -281,6 +281,13 @@ config RRLOAD_BINARY
Create nuttx.rr in the rrload binary format used with
BSPs from www.ridgerun.com using the tools/mkimage.sh script.
config CXD56_BINARY
bool "spk binary format"
default n
---help---
Create nuttx.spk binary format used on spresense board and boards
based on cxd56xx arch.
config INTELHEX_BINARY
bool "Intel HEX binary format"
default n
@@ -1684,6 +1691,10 @@ menu "Audio Support"
source audio/Kconfig
endmenu
menu "Video Support"
source video/Kconfig
endmenu
menu "Wireless Support"
source wireless/Kconfig
endmenu
README.txt
+28 -4
View File
@@ -135,6 +135,10 @@ Installing Cygwin
of the Cygwin utilities that you will need to build NuttX. The
build will fail in numerous places because of missing packages.
NOTE: The last time I installed EVERYTHING, the download was
about 5GiB. The server I selected was also very slow so it took
over a day to do the whole install!
NOTE: You don't really have to install EVERYTHING but I cannot
answer the question "Then what should I install?" I don't know
the answer to that and so will continue to recommend installing
@@ -147,6 +151,19 @@ Installing Cygwin
Perhaps a minimum set would be those packages listed below for the
"Ubuntu Bash under Windows 10" installation?
UPDATE: Sergey Frolov had success with the following minimal
Cygwin configuration:
1. After starting the Cygwin installer, keep the recommended
packages that are pre-selected in the default configuration.
2. Using the installation tools, add the following packages:
make (GNU make) bison libgmp3-dev
gcc-core byacc libmpfr-dev
gcc-g++ gperf libmpc-dev
flex gdb automake-1.15
libncurses-dev libgmp-dev
After installing Cygwin, you will get lots of links for installed
tools and shells. I use the RXVT native shell. It is fast and reliable
and does not require you to run the Cygwin X server (which is neither
@@ -154,10 +171,6 @@ Installing Cygwin
instructions assume that you are at a bash command line prompt in
either Linux or in Cygwin shell.
UPDATE: The last time I installed EVERYTHING, the download was
about 5GiB. The server I selected was also very slow so it took
over a day to do the whole install!
Using MSYS
----------
@@ -457,6 +470,14 @@ Downloading from Repositories
Cloning the Repository
BEFORE cloning repositories on any Windows platform do the following GIT
command:
git config --global core.autocrlf false
That will avoid conversions of linefeeds (newlines, \n) to carriage
return plus linefeed sequences (\r\n)
The current NuttX du jour is available in from a GIT repository. Here are
instructions for cloning the core NuttX RTOS (corresponding to the nuttx
tarball discussed above)::
@@ -1834,6 +1855,7 @@ nuttx/
| |- lpcxpresso-lpc54628/
| | `- README.txt
| |- makerlisp/
| | |- nsh/README.txt
| | `- README.txt
| |- maple/
| | `- README.txt
@@ -1926,6 +1948,8 @@ nuttx/
| | `- README.txt
| |- pic32mz-starterkit/
| | `- README.txt
| |- pnev5180b/
| | `- README.txt
| |- qemu-i486/
| | `- README.txt
| |- sabre-6quad/
TODO
+2 -19
View File
@@ -1,4 +1,4 @@
NuttX TODO List (Last updated April 29, 2019)
NuttX TODO List (Last updated July 1, 2019)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -19,7 +19,7 @@ nuttx/:
(9) Kernel/Protected Build
(3) C++ Support
(5) Binary loaders (binfmt/)
(18) Network (net/, drivers/net)
(17) Network (net/, drivers/net)
(4) USB (drivers/usbdev, drivers/usbhost)
(2) Other drivers (drivers/)
(9) Libraries (libs/libc/, libs/libm/)
@@ -1653,23 +1653,6 @@ o Network (net/, drivers/net)
before, so I suspect it might not be so prevalent as one
might expect.
Title: TCP SOCKETS CLOSED TOO QUICKLY
Description: When a socket is closed, the resources are torn down
immediately (unless the SO_LINGER option is selected). As a
result, the socket does not send the FIN and this looks like
an unexpected, abnormal loss of connection to the remote peer.
Actually, it is worse than this: The is NO logic to send
FIN in when the file is close. This is pretty easy to do,
however:
- Wait for a TCP poll, then
- Call tcp_append with TCP_CLOSE in the flags. There is
already logic in tcp_appsend to send the FIN in this case,
it is just not being use.
Status: Open
Priority: Medium-Low.
Title: LOCAL DATAGRAM RECVFROM RETURNS WRONG SENDER ADDRESS
Description: The recvfrom logic for local datagram sockets returns the
incorrect sender "from" address. Instead, it returns the
arch/arm/include/cxd56xx/adc.h
+96
View File
@@ -0,0 +1,96 @@
/****************************************************************************
* arch/arm/include/cxd56xx/adc.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_CXD56_ADC_H
#define __ARCH_ARM_INCLUDE_CXD56XX_CXD56_ADC_H
/****************************************************************************
* include files
***************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include <nuttx/analog/ioctl.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ANIOC_USER (AN_FIRST + AN_NCMDS)
/* Start sampling
*
* param None
* return ioctl return value provides success/failure indication
*/
#define ANIOC_CXD56_START _ANIOC(ANIOC_USER + 0)
/* Stop sampling
*
* param None
* return ioctl return value provides success/failure indication
*/
#define ANIOC_CXD56_STOP _ANIOC(ANIOC_USER + 1)
/* Set sampling frequency
*
* param None
* return ioctl return value provides success/failure indication
*/
#define ANIOC_CXD56_FREQ _ANIOC(ANIOC_USER + 2)
/* Set fifo size
*
* param None
* return ioctl return value provides success/failure indication
*/
#define ANIOC_CXD56_FIFOSIZE _ANIOC(ANIOC_USER + 3)
/****************************************************************************
* Public Types
****************************************************************************/
/* Initialize valid ADC channels
*
* return OK(0) is success. negative value is failure.
*/
int cxd56_adcinitialize(void);
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_CXD56_ADC_H */
arch/arm/include/cxd56xx/battery_ioctl.h
+115
View File
@@ -0,0 +1,115 @@
/****************************************************************************
* include/arch/chip/battery_ioctl.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_BATTERY_IOCTL_H
#define __ARCH_ARM_INCLUDE_CXD56XX_BATTERY_IOCTL_H
#include <nuttx/fs/ioctl.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ioctl commands */
#define BATIOC_GET_CHGVOLTAGE _BATIOC(0x0010)
#define BATIOC_GET_CHGCURRENT _BATIOC(0x0012)
#define BATIOC_GET_RECHARGEVOL _BATIOC(0x0013)
#define BATIOC_SET_RECHARGEVOL _BATIOC(0x0014)
#define BATIOC_GET_COMPCURRENT _BATIOC(0x0015)
#define BATIOC_SET_COMPCURRENT _BATIOC(0x0016)
#define BATIOC_GET_TEMPTABLE _BATIOC(0x0017)
#define BATIOC_SET_TEMPTABLE _BATIOC(0x0018)
#define BATIOC_GET_CURRENT _BATIOC(0x0019)
#define BATIOC_GET_VOLTAGE _BATIOC(0x001a)
#define BATIOC_MONITOR_ENABLE _BATIOC(0x0030)
#define BATIOC_MONITOR_STATUS _BATIOC(0x0031)
#define BATIOC_MONITOR_SET _BATIOC(0x0032)
#define BATIOC_MONITOR_GET _BATIOC(0x0033)
#define BATIOC_DEBUG _BATIOC(0x00db)
/****************************************************************************
* Public Types
****************************************************************************/
struct battery_temp_table_s
{
int T60; /* 60 degree C */
int T45; /* 45 degree C */
int T10; /* 10 degree C */
int T00; /* 0 degree C */
};
struct bat_monitor_enable_s
{
int on;
int interval;
int threshold_volt;
int threshold_current;
};
struct bat_monitor_status_s
{
int run;
int index;
int latest;
int totalwatt;
int totaltime;
};
struct bat_monitor_set_s
{
int clearbuf;
int clearsum;
};
struct bat_monitor_rec_s
{
uint16_t index;
uint16_t timestamp;
uint16_t voltage;
int16_t current;
};
struct bat_monitor_log_s
{
FAR struct bat_monitor_rec_s *rec;
int index;
int size;
};
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_BATTERY_IOCTL_H */
arch/arm/include/cxd56xx/cisif.h
+111
View File
@@ -0,0 +1,111 @@
/****************************************************************************
* arch/arm/include/cxd56xx/cisif.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_CISIF_H
#define __ARCH_ARM_INCLUDE_CXD56XX_CISIF_H
/****************************************************************************
* Public Types
****************************************************************************/
typedef void (*notify_callback_t)(uint8_t code, uint32_t size, uint32_t addr);
typedef void (*comp_callback_t)(uint8_t code, uint32_t size, uint32_t addr);
struct cisif_init_yuv_param_s
{
uint16_t hsize;
uint16_t vsize;
uint32_t notify_size;
notify_callback_t notify_func;
};
typedef struct cisif_init_yuv_param_s cisif_init_yuv_param_t;
struct cisif_init_jpeg_param_s
{
uint32_t notify_size;
notify_callback_t notify_func;
};
typedef struct cisif_init_jpeg_param_s cisif_init_jpeg_param_t;
struct cisif_sarea_s
{
uint8_t *strg_addr;
uint32_t strg_size;
};
typedef struct cisif_sarea_s cisif_sarea_t;
struct cisif_param_s
{
uint32_t format;
cisif_init_yuv_param_t yuv_param;
cisif_init_jpeg_param_t jpg_param;
cisif_sarea_t sarea;
comp_callback_t comp_func;
};
typedef struct cisif_param_s cisif_param_t;
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
int cxd56_cisifinit(void);
int cxd56_cisiffinalize(void);
int cxd56_cisifstartcapture(cisif_param_t *param, cisif_sarea_t *sarea);
int cxd56_cisifstopcapture(void);
int cxd56_cisifsetdmabuf(cisif_sarea_t *sarea);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_CISIF_H */
arch/arm/include/cxd56xx/irq.h
-15
View File
@@ -218,21 +218,6 @@
#define NR_VECTORS CXD56_IRQ_NIRQS
#define NR_IRQS CXD56_IRQ_NIRQS
/* Cortex-M0 External interrupts (vectors >= 16) */
#if 0
# define CXD56M0_IRQ_NIRQS (CXD56_IRQ_EXTINT + CXD56M0_IRQ_NEXTINT)
#endif
/* Total number of IRQ numbers (This will need to be revisited if/when the
* Cortex-M0 is supported)
*/
#if 0
# define NR_VECTORS CXD56M0_IRQ_NIRQS
# define NR_IRQS CXD56M0_IRQ_NIRQS
#endif
/****************************************************************************
* Public Types
****************************************************************************/
arch/arm/include/cxd56xx/pm.h
-3
View File
@@ -32,9 +32,6 @@
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/**
* @file pm.h
*/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_PM_H
#define __ARCH_ARM_INCLUDE_CXD56XX_PM_H
arch/arm/include/cxd56xx/scu.h
+560
View File
File diff suppressed because it is too large Load Diff
arch/arm/include/cxd56xx/timer.h
+66
View File
@@ -0,0 +1,66 @@
/****************************************************************************
* arch/arm/include/cxd56xx/timer.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_TIMER_H
#define __ARCH_ARM_INCLUDE_CXD56XX_TIMER_H
#include <nuttx/timers/timer.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/*
* Set callback handler
*
* param A pointer to struct timer_sethandler_s
* return ioctl return value provides success/failure indication
*/
#define TCIOC_SETHANDLER _TCIOC(0x0020)
/****************************************************************************
* Public Types
****************************************************************************/
/* This is the type of the argument passed to the TCIOC_SETHANDLER ioctl */
struct timer_sethandler_s
{
FAR void *arg; /* An argument */
CODE tccb_t handler; /* The timer interrupt handler */
};
#endif /* __ARCH_ARM_INCLUDE_CXD56XX_TIMER_H */
arch/arm/src/am335x/Kconfig
+140 -7
View File
@@ -94,16 +94,18 @@ config AM335X_GPIO
bool "GPIO"
default n
config AM335X_LCDC
bool "LCD controller"
default n
depends on VIDEO && EXPERIMENTAL
select VIDEO_EDID
config AM335X_TSC
bool "Touchscreen Controller"
default n
config AM335X_LCDC
bool "LCD Controller"
default n
config AM335X_CPSW
bool "Ethernet subsustem"
bool "Ethernet subsystem"
default n
config AM335X_PWMSS
@@ -134,11 +136,11 @@ config AM335X_I2C0
bool "Multi-master I2C Controller 0"
default n
config AM335X_I2C0
config AM335X_I2C1
bool "Multi-master I2C Controller 1"
default n
config AM335X_I2C0
config AM335X_I2C2
bool "Multi-master I2C Controller 2"
default n
@@ -248,4 +250,135 @@ config AM335X_DDR_MAPSIZE
plus the size of the available heap. NOTE that RAM_SIZE may not
include all of SDRAM up to the end of mapped region.
menu "LCD Configuration"
depends on AM335X_LCDC
config AM335X_LCDC_FB_VBASE
hex "Video RAM base address (virtual)"
default 0x80000000
---help---
Base address of the video RAM frame buffer. The default of 0x80000000
assumes that the framebuffer lies at the beginning of DRAM and that
a 1-to-1 virtual-to-physical address mapping is used.
config AM335X_LCDC_FB_PBASE
hex "Video RAM base address (physical)"
default 0x80000000
---help---
Base address of the video RAM frame buffer. The default of 0x80000000
assumes that the framebuffer lies at the beginning of DRAM.
config AM335X_LCDC_FB_SIZE
hex "Video RAM base size"
default 0x00100000
---help---
Size of the video RAM frame buffer. Default: 1Mb.
config AM335X_LCDC_USE_CLKIN
bool "Use optional input clock"
default n
config AM335X_LCDC_CLKIN_FREQUENCY
int "Input clock frequency"
default 0
depends on AM335X_LCDC_USE_CLKIN
config AM335X_LCDC_REFRESH_FREQ
int "LCD refesh rate (Hz)"
default 50
---help---
LCD refesh rate (Hz)
choice
prompt "Bits per pixel"
default AM335X_LCDC_BPP16_565
config AM335X_LCDC_BPP1
bool "1 BPP"
config AM335X_LCDC_BPP2
bool "2 BPP"
config AM335X_LCDC_BPP4
bool "4 BPP"
config AM335X_LCDC_BPP8
bool "8 BPP"
config AM335X_LCDC_BPP12_444
bool "12 bpp, 4:4:4 mode"
config AM335X_LCDC_BPP16_565
bool "16 BPP, 5:6:5 mode"
config AM335X_LCDC_BPP24
bool "24 BPP, 8:8:8 mode (packed)"
config AM335X_LCDC_BPP32
bool "32 BPP, 8:8:8 mode (unpacked)"
endchoice
config AM335X_LCDC_BGR
bool "Blue-Green-Red color order"
default n
depends on !AM335X_LCDC_MONOCHROME
---help---
This option selects BGR color order vs. default RGB
config AM335X_LCDC_BACKCOLOR
hex "Initial background color"
default 0x0
---help---
Initial background color
config AM335X_LCDC_ACBIAS
int "AC bias pin frequency"
default 255
range 0 255
config AM335X_LCDC_ACBIAS_PINT
int "AC bias pin transitions per interrupt"
default 0
range 0 15
choice
prompt "DMA burst size"
default AM335X_LCDC_DMA_BURST16
config AM335X_LCDC_DMA_BURST1
bool "1"
config AM335X_LCDC_DMA_BURST2
bool "2"
config AM335X_LCDC_DMA_BURST4
bool "4"
config AM335X_LCDC_DMA_BURST8
bool "8"
config AM335X_LCDC_DMA_BURST16
bool "16"
endchoice
config AM335X_LCDC_FDD
int "Palette loading delay"
default 128
range 0 255
config AM335X_LCDC_SYNC_EDGE
bool "HSYNC/VSYNC rise or fall"
default n
config AM335X_LCDC_SYNC_CTRL
bool "Hsync/Vsync pixel clock control on/off"
default y
config AM335X_LCDC_PIXCLK_INVERT
bool "Invert pixel clock"
default y
endmenu # LCD Configuration
endif # ARCH_CHIP_AM335X
arch/arm/src/am335x/Make.defs
+6 -1
View File
@@ -126,6 +126,7 @@ CHIP_ASRCS =
CHIP_CSRCS = am335x_boot.c am335x_clockconfig.c am335x_pinmux.c am335x_irq.c
CHIP_CSRCS += am335x_gpio.c am335x_lowputc.c am335x_serial.c am335x_wdog.c
CHIP_CSRCS += am335x_sysclk.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += am335x_timerisr.c
@@ -133,4 +134,8 @@ endif
ifeq ($(CONFIG_AM335X_GPIO_IRQ),y)
CHIP_CSRCS += am335x_gpioirq.c
endif
endif
ifeq ($(CONFIG_AM335X_LCDC),y)
CHIP_CSRCS += am335x_lcdc.c am335x_edid.c
endif
arch/arm/src/am335x/am335x_boot.c
+39 -10
View File
@@ -66,6 +66,13 @@
* Pre-processor Definitions
****************************************************************************/
/* If the LCDC is enabled, then this will provide the number of sections
* to map for the framebuffer.
*/
#define AM335X_LCDC_FBNSECTIONS \
((CONFIG_AM335X_LCDC_FB_SIZE + 0x000fffff) >> 20)
/****************************************************************************
* Name: showprogress
*
@@ -105,9 +112,8 @@
extern uint32_t _vector_start; /* Beginning of vector block */
extern uint32_t _vector_end; /* End+1 of vector block */
/****************************************************************************
* Private Functions
****************************************************************************/
#define SAMA5_LCDC_FBNSECTIONS \
((CONFIG_SAMA5_LCDC_FB_SIZE + 0x000fffff) >> 20)
/****************************************************************************
* Private Data
@@ -120,32 +126,55 @@ extern uint32_t _vector_end; /* End+1 of vector block */
#ifndef CONFIG_ARCH_ROMPGTABLE
static const struct section_mapping_s g_section_mapping[] =
{
{ AM335X_GPMC_PSECTION, AM335X_GPMC_VSECTION, /* Includes vectors and page table */
{
AM335X_GPMC_PSECTION, AM335X_GPMC_VSECTION, /* Includes vectors and page table */
AM335X_GPMC_MMUFLAGS, AM335X_GPMC_NSECTIONS
},
{ AM335X_BROM_PSECTION, AM335X_BROM_VSECTION,
{
AM335X_BROM_PSECTION, AM335X_BROM_VSECTION,
AM335X_BROM_MMUFLAGS, AM335X_BROM_NSECTIONS
},
{ AM335X_ISRAM_PSECTION, AM335X_ISRAM_VSECTION,
{
AM335X_ISRAM_PSECTION, AM335X_ISRAM_VSECTION,
AM335X_ISRAM_MMUFLAGS, AM335X_ISRAM_NSECTIONS
},
{ AM335X_OCMC0_PSECTION, AM335X_OCMC0_VSECTION,
{
AM335X_OCMC0_PSECTION, AM335X_OCMC0_VSECTION,
AM335X_OCMC0_MMUFLAGS, AM335X_OCMC0_NSECTIONS
},
{ AM335X_PERIPH_PSECTION, AM335X_PERIPH_VSECTION,
{
AM335X_PERIPH_PSECTION, AM335X_PERIPH_VSECTION,
AM335X_PERIPH_MMUFLAGS, AM335X_PERIPH_NSECTIONS
},
{ AM335X_DDR_PSECTION, AM335X_DDR_VSECTION,
{
AM335X_DDR_PSECTION, AM335X_DDR_VSECTION,
AM335X_DDR_MMUFLAGS, AM335X_DDR_NSECTIONS
}
#ifdef CONFIG_AM335X_LCDC
,
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cache-able and non-buffer-able.
*/
{
CONFIG_AM335X_LCDC_FB_PBASE, CONFIG_AM335X_LCDC_FB_VBASE,
MMU_IOFLAGS, AM335X_LCDC_FBNSECTIONS
}
#endif
};
#define NMAPPINGS \
(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
const size_t g_num_mappings = NMAPPINGS;
static const size_t g_num_mappings = NMAPPINGS;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_setupmappings
*
arch/arm/src/am335x/am335x_clockconfig.c
+32 -4
View File
@@ -40,13 +40,39 @@
#include <nuttx/config.h>
#include "up_arch.h"
#if 0
/* TODO: add clock register module */
#include "hardware/am335x_ccm.h"
#endif
#include "hardware/am335x_cm.h"
#include "am335x_config.h"
#include "am335x_clockconfig.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_dmtimer1ms_clockconfig
****************************************************************************/
static inline void am335x_dmtimer1ms_clockconfig(void)
{
putreg32(CM_DPLL_DMTIMER1_CLKSEL_CLK_M_OSC,
AM335X_CM_DPLL_CLKSEL_TIMER1MS_CLK);
while ((getreg32(AM335X_CM_DPLL_CLKSEL_TIMER1MS_CLK) &
CM_DPLL_DMTIMER1MS_CLKSEL_MASK)
!= CM_DPLL_DMTIMER1_CLKSEL_CLK_M_OSC)
{
}
modifyreg32(AM335X_CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_CLKCTRL_MODULEMODE_MASK,
CM_WKUP_CLKCTRL_MODULEMODE_ENABLE);
while ((getreg32(AM335X_CM_WKUP_TIMER1_CLKCTRL) &
(CM_WKUP_CLKCTRL_MODULEMODE_MASK | CM_WKUP_CLKCTRL_IDLEST_MASK))
!= (CM_WKUP_CLKCTRL_MODULEMODE_ENABLE | CM_WKUP_CLKCTRL_IDLEST_FUNC))
{
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -75,6 +101,8 @@ void am335x_clockconfig(void)
* 792MHz.
*/
am335x_dmtimer1ms_clockconfig();
#ifndef CONFIG_AM335X_BOOT_SDRAM
# warning Missing logic
#endif
arch/arm/src/am335x/am335x_edid.c
+397
View File
@@ -0,0 +1,397 @@
/****************************************************************************
* arch/arm/src/am335x/am335x_wdog.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* The LCD driver derives from the LPC54xx LCD driver but also includes
* information from the FreeBSD AM335x LCD driver which was released under
* a two-clause BSD license:
*
* Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/video/edid.h>
#include "am335x_lcdc.h"
/****************************************************************************
* Pre-processor definitions Functions
****************************************************************************/
#define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end)
#define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay)
#define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start)
#define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end)
#define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay)
#define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start)
#define MAX_PIXEL_CLOCK 126000
#define MAX_BANDWIDTH (1280*1024*60)
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_lcd_edid
*
* Description:
* Return the vertical refresh rate for this video mode.
*
****************************************************************************/
static uint32_t
am335x_videomode_vrefresh(FAR const struct edid_videomode_s *videomode)
{
uint32_t refresh;
/* Calculate vertical refresh rate */
refresh = (videomode->dotclock * 1000 / videomode->htotal);
refresh = (refresh + videomode->vtotal / 2) / videomode->vtotal;
if (videomode->flags & VID_INTERLACE)
{
refresh *= 2;
}
if (videomode->flags & VID_DBLSCAN)
{
refresh /= 2;
}
return refresh;
}
/****************************************************************************
* Name: am335x_videomode_valid
*
* Description:
* Return true if the provided video mode is valid.
*
****************************************************************************/
static bool
am335x_videomode_valid(FAR const struct edid_videomode_s *videomode)
{
size_t fbstride;
size_t fbsize;
uint32_t hbp;
uint32_t hfp;
uint32_t hsw;
uint32_t vbp;
uint32_t vfp;
uint32_t vsw;
uint32_t vrefresh;
if (videomode->dotclock > MAX_PIXEL_CLOCK)
{
return false;
}
if (videomode->hdisplay & 0xf)
{
return false;
}
if (videomode->vdisplay > 2048)
{
return false;
}
/* Check ranges for timing parameters */
hbp = MODE_HBP(videomode) - 1;
hfp = MODE_HFP(videomode) - 1;
hsw = MODE_HSW(videomode) - 1;
vbp = MODE_VBP(videomode);
vfp = MODE_VFP(videomode);
vsw = MODE_VSW(videomode) - 1;
if (hbp > 0x3ff)
{
return false;
}
if (hfp > 0x3ff)
{
return false;
}
if (hsw > 0x3ff)
{
return false;
}
if (vbp > 0xff)
{
return false;
}
if (vfp > 0xff)
{
return false;
}
if (vsw > 0x3f)
{
return false;
}
vrefresh = am335x_videomode_vrefresh(videomode);
if (videomode->vdisplay * videomode->hdisplay * vrefresh > MAX_BANDWIDTH)
{
return false;
}
/* Finally, make sure that the framebuffer buffer region is large enough
* to support this video mode.
*/
fbstride = (videomode->hdisplay * AM335X_BPP + 7) >> 3;
fbsize = videomode->vdisplay * fbstride;
if (fbsize > AM335X_LCDC_FB_SIZE)
{
return false;
}
return true;
}
/****************************************************************************
* Name: am335x_lcd_pickmode
*
* Description:
* If there is access to Extended Display Identification Data (EDIDI),
* then the board-specific logic may read the EDID data and use this
* function to select an appropriate video mode.
*
* edid_parse() should be used to convert the raw EDID data into the
* digested form of struct edid_info.
*
* The returned video mode may be used to both (1) configure HDMI and (2)
* initialize the AM335x LCD controller.
*
****************************************************************************/
static const struct edid_videomode_s *
am335x_lcd_pickmode(FAR struct edid_info_s *ei)
{
FAR const struct edid_videomode_s *videomode;
int n;
/* Get standard VGA as default */
videomode = NULL;
/* Pick a video mode -- First check if we can support the preferred mode. */
if (ei->edid_preferred_mode != NULL)
{
if (am335x_videomode_valid(ei->edid_preferred_mode))
{
videomode = ei->edid_preferred_mode;
return videomode;
}
}
/* Sort video modes by refresh rate, aspect ratio (*), then resolution.
* Preferred mode or largest mode is first in the list and other modes
* are sorted on closest match to that mode.
*/
edid_sort_modes(ei->edid_modes, &ei->edid_preferred_mode, ei->edid_nmodes);
/* Pick the first valid mode in the list */
for (n = 0; n < ei->edid_nmodes; n++)
{
if (am335x_videomode_valid(&ei->edid_modes[n]))
{
videomode = &ei->edid_modes[n];
break;
}
}
return videomode;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_lcd_videomode
*
* Description:
* If the video mod is known, then the board-specific logic may read the
* use this function to convert the video mode data to an instance of
* struct am335x_panel_info_s which then may be used to initialize the
* the LCD/
*
* Input Parameters:
* videomode - A reference to the desired video mode.
* panel - A user provided location to receive the panel data.
*
* Returned value:
* None. Always succeeds.
*
****************************************************************************/
void am335x_lcd_videomode(FAR const struct edid_videomode_s *videomode,
FAR struct am335x_panel_info_s *panel)
{
lcdinfo("Detected videomode: %dx%d @ %dKHz\n",
videomode->hdisplay, videomode->vdisplay,
am335x_videomode_vrefresh(videomode));
panel->width = videomode->hdisplay;
panel->height = videomode->vdisplay;
panel->hfp = videomode->hsync_start - videomode->hdisplay;
panel->hbp = videomode->htotal - videomode->hsync_end;
panel->hsw = videomode->hsync_end - videomode->hsync_start;
panel->vfp = videomode->vsync_start - videomode->vdisplay;
panel->vbp = videomode->vtotal - videomode->vsync_end;
panel->vsw = videomode->vsync_end - videomode->vsync_start;
panel->pixelclk_active = true;
/* Logic for HSYNC should be reversed */
panel->hsync_active = ((videomode->flags & VID_NHSYNC) != 0);
panel->vsync_active = ((videomode->flags & VID_NVSYNC) == 0);
panel->pixclk = videomode->dotclock * 1000;
/* Set other values to the default */
#ifdef CONFIG_AM335X_LCDC_SYNC_EDGE
panel->sync_edge = true;
#else
panel->sync_edge = false;
#endif
#ifdef CONFIG_AM335X_LCDC_SYNC_CTRL
panel->sync_ctrl = true;
#else
panel->sync_ctrl = false;
#endif
#ifdef CONFIG_AM335X_LCDC_PIXCLK_INVERT
panel->pixelclk_active = true;
#else
panel->pixelclk_active = false;
#endif
panel->acbias = CONFIG_AM335X_LCDC_ACBIAS;
panel->acbias_pint = CONFIG_AM335X_LCDC_ACBIAS_PINT;
panel->dma_burstsz = AM335X_LCD_DMA_BURSTSZ;
panel->bpp = AM335X_BPP; /* REVISIT */
panel->fdd = CONFIG_AM335X_LCDC_FDD;
}
/****************************************************************************
* Name: am335x_lcd_edid
*
* Description:
* If there is access to Extended Display Identification Data (EDID),
* then the board-specific logic may read the EDID data and use this
* function to initialize an instance of struct am335x_panel_info_s.
*
* The returned video mode may optionally be returned to configure HDMI.
*
* Input Parameters:
* edid - A reference to the raw EDID data.
* len - The length of the EDID data in bytes
* panel - A user provided location to receive the panel data.
* selected - A user provided location to receive the selected video mode.
*
* Returned value:
* None. Always succeeds. The logic will fallback to VGA mode if no
* EDID data is provided or if there is no valid video mode in the EDID
* data.
*
****************************************************************************/
void am335x_lcd_edid(FAR const uint8_t *edid, size_t edid_len,
FAR struct am335x_panel_info_s *panel,
FAR struct edid_videomode_s *selected)
{
FAR const struct edid_videomode_s *videomode = NULL;
struct edid_info_s ei;
/* Do we have EDID data? */
if (edid != NULL && edid_len > 0)
{
/* Parse the EDID data */
if (edid_parse(edid, &ei) == 0)
{
videomode = am335x_lcd_pickmode(&ei);
}
else
{
lcderr("ERROR: Failed to parse EDID\n");
}
}
/* Use standard VGA as fallback */
if (videomode == NULL)
{
videomode = edid_mode_lookup("640x480x60");
DEBUGASSERT(videomode != NULL);
}
/* Initialize the LCD using the selected video mode */
am335x_lcd_videomode(videomode, panel);
/* Return the selected video mode */
if (selected != NULL)
{
memcpy(selected, videomode, sizeof(struct edid_videomode_s));
}
}
arch/arm/src/am335x/am335x_lcdc.c
+948
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File diff suppressed because it is too large Load Diff
arch/arm/src/am335x/am335x_lcdc.h
+302
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@@ -0,0 +1,302 @@
/****************************************************************************
* arch/arm/src/am335x/am335x_lcdc.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* The LCD driver derives from the LPC54xx LCD driver but also includes
* information from the FreeBSD AM335x LCD driver which was released under
* a two-clause BSD license:
*
* Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The LPC54 LCD driver uses the common framebuffer interfaces declared in
* include/nuttx/video/fb.h.
*/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_LCDC_H
#define __ARCH_ARM_SRC_AM335X_AM335X_LCDC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include <nuttx/nx/nxglib.h>
#include "hardware/am335x_lcd.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Background color */
#ifndef CONFIG_AM335X_LCDC_BACKCOLOR
# warning "Assuming background color == 16"
# define CONFIG_AM335X_LCDC_BACKCOLOR 0 /* Initial background color */
#endif
/* Default characteristics (may be overridden via struct am335x_panel_info_s */
/* Bits per pixel / color format */
#undef AM335X_COLOR_FMT
#if defined(CONFIG_AM335X_LCDC_BPP1)
# define AM335X_BPP 1
# define AM335X_COLOR_FMT FB_FMT_Y1
#elif defined(CONFIG_AM335X_LCDC_BPP2)
# define AM335X_BPP 2
# define AM335X_COLOR_FMT FB_FMT_Y2
#elif defined(CONFIG_AM335X_LCDC_BPP4)
# define AM335X_BPP 4
# define AM335X_COLOR_FMT FB_FMT_Y4
#elif defined(CONFIG_AM335X_LCDC_BPP8)
# define AM335X_BPP 8
# define AM335X_COLOR_FMT FB_FMT_Y8
#elif defined(CONFIG_AM335X_LCDC_BPP12_444)
# define AM335X_BPP 1 12
# define AM335X_COLOR_FMT FB_FMT_RGB12_444
#elif defined(CONFIG_AM335X_LCDC_BPP16_565)
# define AM335X_BPP 16
# define AM335X_COLOR_FMT FB_FMT_RGB16_565
#elif defined(CONFIG_AM335X_LCDC_BPP24)
# define AM335X_BPP 24 RGB */
# define AM335X_COLOR_FMT FB_FMT_RGB24
#else
# warning "Assuming 16 BPP 5:6:5"
# define AM335X_BPP 16
# define CONFIG_AM335X_LCDC_BPP16_565 1
# define AM335X_COLOR_FMT FB_FMT_RGB16_565
#endif
#ifndef CONFIG_AM335X_LCDC_ACBIAS
# warning "Assuming AC bias == 255"
# define CONFIG_AM335X_LCDC_ACBIAS 255
#endif
#ifndef CONFIG_AM335X_LCDC_ACBIAS_PINT
# warning "Assuming AC bias per interrupt == 0"
# define CONFIG_AM335X_LCDC_ACBIAS_PINT 0
#endif
#if defined(CONFIG_AM335X_LCDC_DMA_BURST1)
# define AM335X_LCD_DMA_BURSTSZ 1
#elif defined(CONFIG_AM335X_LCDC_DMA_BURST2)
# define AM335X_LCD_DMA_BURSTSZ 2
#elif defined(CONFIG_AM335X_LCDC_DMA_BURST4)
# define AM335X_LCD_DMA_BURSTSZ 4
#elif defined(CONFIG_AM335X_LCDC_DMA_BURST8)
# define AM335X_LCD_DMA_BURSTSZ 8
#elif defined(CONFIG_AM335X_LCDC_DMA_BURST16)
# define AM335X_LCD_DMA_BURSTSZ 16
#else
# warning "Assuming DMA burst size == 16"
# define CONFIG_AM335X_LCDC_DMA_BURST16 1
# define AM335X_LCD_DMA_BURSTSZ 16
#endif
#ifndef CONFIG_AM335X_LCDC_FDD
# warning "Assuming FDD == 128"
# define CONFIG_AM335X_LCDC_FDD 128
#endif
#if (CONFIG_AM335X_LCDC_FB_SIZE & 0x000fffff) != 0
# warning "Framebuffer size must be a multiple of 1Mb"
#endif
#define AM335X_LCDC_FB_SIZE \
((CONFIG_AM335X_LCDC_FB_SIZE + 0x000fffff) & ~0x000fffff)
/****************************************************************************
* Public Types
****************************************************************************/
/* Describes the LCD panel configuration */
struct am335x_panel_info_s
{
bool hsync_active; /* HSync active */
bool vsync_active; /* Invert VSync */
bool sync_edge; /* HSYNC/VSYNC rise or fall */
bool sync_ctrl; /* Hsync/Vsync pixel clock control on/off */
bool pixelclk_active; /* Invert pixel clock */
uint32_t width; /* Display width (pixels) */
uint32_t height; /* Display height (lines) */
uint32_t hfp; /* Horizontal front porch (pixels) */
uint32_t hbp; /* Horizontal back porch (pixels) */
uint32_t hsw; /* HSync width */
uint32_t vfp; /* Vertical front porch (lines) */
uint32_t vbp; /* Vertical back porch (lines) */
uint32_t vsw; /* VSync width */
uint32_t pixclk; /* Pixel clock */
uint32_t acbias; /* AC bias pin frequency */
uint32_t acbias_pint; /* AC bias pins transitions per interrupt */
uint32_t dma_burstsz; /* DMA burst size */
uint32_t bpp; /* Bits per pixel */
uint32_t fdd; /* Palette loading delay */
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_lcd_initialize
*
* Description:
* Initialize the AM335x for use the display described by the provided
* instance of struct am335x_panel_info_s.
*
* This function must be called by board specific logic to initialize the
* LCD. Normally the calling sequence is as follows:
*
* 1a. Graphics application starts and initializes the NX server via
* boardctl(BOARDIOC_NX_START). This calls the graphics
* initialization function nxmu_start() which, in turn, will call
* up_fbinitialize(). Or,
* 1b. The framebuffer character driver is initialized and calls
* up_fbinitialize().
* 2. The function up_fbinitialize() must reside in board specific logic
* under configs/. It must create the instance of struct
* am335x_panel_info_s and call this function with that instance.
*
* For a directly connected LCD, either (1) the struct am335x_panel_info_s
* may be initialized with constant data or (2) the desired video mode can
* obtained via lookup from edid_mode_lookup() and the struct
* am335x_panel_info_s can be created with am335x_lcd_videomode().
*
* If there is access to Extended Display Identification Data (EDID), then
* the board-specific logic may read the EDID data and use
* am335x_lcd_edid() to use the EDID data to initialize the struct
* am335x_panel_info_s instance.
*
* Input Parameters:
* panel - Provides information about the connect LCD panel.
*
* Returned value:
* Zero (OK) is returned on success; a negated errno value is returned in
* the the case of a failure.
*
****************************************************************************/
int am335x_lcd_initialize(FAR const struct am335x_panel_info_s *panel);
/****************************************************************************
* Name: am335x_lcdclear
*
* Description:
* This is a non-standard LCD interface just for the AM335x. Clearing
* the display in the normal way by writing a sequences of runs that
* covers the entire display can be slow. Here the display is cleared by
* simply setting all VRAM memory to the specified color.
*
****************************************************************************/
void am335x_lcdclear(nxgl_mxpixel_t color);
/****************************************************************************
* Name: am335x_lcd_videomode
*
* Description:
* If the video mod is known, then the board-specific logic may read the
* use this function to convert the video mode data to an instance of
* struct am335x_panel_info_s which then may be used to initialize the
* the LCD/
*
* Input Parameters:
* videomode - A reference to the desired video mode.
* panel - A user provided location to receive the panel data.
*
* Returned value:
* None. Always succeeds.
*
****************************************************************************/
struct edid_videomode_s; /* Forward reference */
void am335x_lcd_videomode(FAR const struct edid_videomode_s *videomode,
FAR struct am335x_panel_info_s *panel);
/****************************************************************************
* Name: am335x_lcd_edid
*
* Description:
* If there is access to Extended Display Identification Data (EDID),
* then the board-specific logic may read the EDID data and use this
* function to initialize an instance of struct am335x_panel_info_s.
*
* The returned video mode may optionally be returned to configure HDMI.
*
* Input Parameters:
* edid - A reference to the raw EDID data.
* len - The length of the EDID data in bytes
* panel - A user provided location to receive the panel data.
* selected - A user provided location to receive the selected video mode.
*
* Returned value:
* None. Always succeeds. The logic will fallback to VGA mode if no
* EDID data is provided or if there is no valid video mode in the EDID
* data.
*
****************************************************************************/
void am335x_lcd_edid(FAR const uint8_t *edid, size_t edid_len,
FAR struct am335x_panel_info_s *panel,
FAR struct edid_videomode_s *selected);
/****************************************************************************
* Name: am335x_backlight
*
* Description:
* If CONFIG_AM335X_LCDC_BACKLIGHT is defined, then the board-specific
* logic must provide this interface to turn the backlight on and off.
*
* REVISIT: Current assumes a discrete ON/OFF control. Needs additional
* support for backlight level control.
*
****************************************************************************/
#ifdef CONFIG_AM335X_LCDC_BACKLIGHT
void am335x_backlight(bool blon);
#endif
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_LCDC_H */
arch/arm/src/am335x/am335x_sysclk.c
+102
View File
@@ -0,0 +1,102 @@
/****************************************************************************
* arch/arm/src/am335x/am335x_sysclk.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <errno.h>
#include "up_arch.h"
#include "hardware/am335x_memorymap.h"
#include "am335x_sysclk.h"
/****************************************************************************
* Pre-processor definitions
****************************************************************************/
/* REVISIT: These belong in a control module register header file */
#define AM335X_SCM_CTRL_STATUS_OFFSET 0x40
#define AM335X_SCM_CTRL_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_CTRL_STATUS_OFFSET)
#define SCM_CTRL_STATUS_SYSBOOT1_SHIFT (22) /* Bits 22-23: Crystal clock frequency selection */
#define SCM_CTRL_STATUS_SYSBOOT1_MASK (3 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_19p2MHZ (0 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_24MHZ (1 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_25MHZ (2 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_26MHZ (3 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: am335x_get_sysclk
*
* Description:
* Return the sysclk frequency
*
****************************************************************************/
int32_t am335x_get_sysclk(void)
{
uint32_t regval;
/* Read the input clock freq from the control module. */
regval = getreg32(AM335X_SCM_CTRL_STATUS);
/* Return the frequency of the configured crystal */
switch (regval & SCM_CTRL_STATUS_SYSBOOT1_MASK)
{
case SCM_CTRL_STATUS_SYSBOOT1_19p2MHZ: /* 19.2Mhz */
return 19200000;
case SCM_CTRL_STATUS_SYSBOOT1_24MHZ: /* 24Mhz */
return 24000000;
case SCM_CTRL_STATUS_SYSBOOT1_25MHZ: /* 25Mhz */
return 25000000;
case SCM_CTRL_STATUS_SYSBOOT1_26MHZ: /* 26Mhz */
return 26000000;
}
return -EINVAL; /* Should never happen */
}
arch/arm/src/am335x/am335x_sysclk.h
+59
View File
@@ -0,0 +1,59 @@
/****************************************************************************
* arch/arm/src/am335x/am335x_sysclk.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_AM335X_SYSCLK_H
#define __ARCH_ARM_SRC_AM335X_AM335X_SYSCLK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: am335x_get_sysclk
*
* Description:
* Return the sysclk frequency
*
****************************************************************************/
int32_t am335x_get_sysclk(void);
#endif /* __ARCH_ARM_SRC_AM335X_AM335X_SYSCLK_H */
arch/arm/src/am335x/am335x_timerisr.c
+4 -19
View File
@@ -51,20 +51,15 @@
#include "up_arch.h"
#include "hardware/am335x_timer.h"
#define USE_TIMER1MS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef USE_TIMER1MS
/* Timer 1 clock selects the external 32.768 KHz oscillator/clock */
# define TMR_CLOCK (32768)
#else
/* Timer clock selects system clock CLK_M_OSC (24MHz) */
# define TMR_CLOCK (24000000ll)
#endif
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
@@ -78,21 +73,12 @@
#define TMR_TLDR (0xffffffff - (TMR_CLOCK / CLK_TCK) + 1)
#define TMR_TCRR (0xffffffff - (TMR_CLOCK / CLK_TCK) + 1)
#ifdef USE_TIMER1MS
# define TMR_TPIR \
(((TMR_CLOCK / CLK_TCK + 1) * 1000000l) - \
(TMR_CLOCK * (1000000l / CLK_TCK)))
# define TMR_TNIR \
(((TMR_CLOCK / CLK_TCK) * 1000000l) - \
(TMR_CLOCK * (1000000l / CLK_TCK)))
#else
# define TMR_TPIR \
#define TMR_TPIR \
(((TMR_CLOCK / CLK_TCK + 1) * 1000000ll) - \
(TMR_CLOCK * (1000000ll / CLK_TCK)))
# define TMR_TNIR \
#define TMR_TNIR \
(((TMR_CLOCK / CLK_TCK) * 1000000ll) - \
(TMR_CLOCK * (1000000ll / CLK_TCK)))
#endif
/****************************************************************************
* Private Functions
@@ -214,6 +200,5 @@ void arm_timer_initialize(void)
/* And enable the timer interrupt */
up_enable_irq(AM335X_IRQ_TIMER2);
#endif
}
arch/arm/src/am335x/am335x_wdog.c
+4 -4
View File
@@ -58,13 +58,13 @@
void am335x_wdog_disable_all(void)
{
putreg32(WDT_WSPR_STOP_FEED_A, AM335X_WDT_WSPR);
while ((getreg32(AM335X_WDT_WWPS) & WDT_WWPS_W_PEND_WSPR) != 0)
putreg32(WDT_SPR_STOP_FEED_A, AM335X_WDT_SPR);
while ((getreg32(AM335X_WDT_WPS) & WDT_WPS_W_PEND_WSPR) != 0)
{
}
putreg32(WDT_WSPR_STOP_FEED_B, AM335X_WDT_WSPR);
while ((getreg32(AM335X_WDT_WWPS) & WDT_WWPS_W_PEND_WSPR) != 0)
putreg32(WDT_SPR_STOP_FEED_B, AM335X_WDT_SPR);
while ((getreg32(AM335X_WDT_WPS) & WDT_WPS_W_PEND_WSPR) != 0)
{
}
}
arch/arm/src/am335x/hardware/am335x_cm.h
+368
View File
@@ -0,0 +1,368 @@
/********************************************************************************************
* arch/arm/src/am335x/hardware/am335x_cm.h
*
* Copyright (C) 2019 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CM_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CM_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include <hardware/am335x_memorymap.h>
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Clock Module Register Offsets ************************************************************/
#define AM335X_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
#define AM335X_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004
#define AM335X_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c
#define AM335X_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014
#define AM335X_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018
#define AM335X_CM_PER_USB0_CLKCTRL_OFFSET 0x001c
#define AM335X_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024
#define AM335X_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028
#define AM335X_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c
#define AM335X_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030
#define AM335X_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034
#define AM335X_CM_PER_UART5_CLKCTRL_OFFSET 0x0038
#define AM335X_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c
#define AM335X_CM_PER_ELM_CLKCTRL_OFFSET 0x0040
#define AM335X_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044
#define AM335X_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048
#define AM335X_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c
#define AM335X_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050
#define AM335X_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060
#define AM335X_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068
#define AM335X_CM_PER_UART1_CLKCTRL_OFFSET 0x006c
#define AM335X_CM_PER_UART2_CLKCTRL_OFFSET 0x0070
#define AM335X_CM_PER_UART3_CLKCTRL_OFFSET 0x0074
#define AM335X_CM_PER_UART4_CLKCTRL_OFFSET 0x0078
#define AM335X_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c
#define AM335X_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080
#define AM335X_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084
#define AM335X_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088
#define AM335X_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac
#define AM335X_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0
#define AM335X_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4
#define AM335X_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc
#define AM335X_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0
#define AM335X_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4
#define AM335X_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc
#define AM335X_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4
#define AM335X_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8
#define AM335X_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc
#define AM335X_CM_PER_L3_CLKCTRL_OFFSET 0x00e0
#define AM335X_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4
#define AM335X_CM_PER_PRU_ICSS_CLKCTRL_OFFSET 0x00e8
#define AM335X_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec
#define AM335X_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0
#define AM335X_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4
#define AM335X_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8
#define AM335X_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc
#define AM335X_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100
#define AM335X_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c
#define AM335X_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110
#define AM335X_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c
#define AM335X_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120
#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c
#define AM335X_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130
#define AM335X_CM_PER_PRU_ICSS_CLKSTCTRL_OFFSET 0x0140
#define AM335X_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144
#define AM335X_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148
#define AM335X_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c
#define AM335X_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150
#define AM335X_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
#define AM335X_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004
#define AM335X_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008
#define AM335X_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c
#define AM335X_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010
#define AM335X_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014
#define AM335X_CM_WKUP_L3_AON_CLKSTCTRL_OFFSET 0x0018
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_MPU_OFFSET 0x001c
#define AM335X_CM_WKUP_IDLEST_DPLL_MPU_OFFSET 0x0020
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028
#define AM335X_CM_WKUP_CLKSEL_DPLL_MPU_OFFSET 0x002c
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_DDR_OFFSET 0x0030
#define AM335X_CM_WKUP_IDLEST_DPLL_DDR_OFFSET 0x0034
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c
#define AM335X_CM_WKUP_CLKSEL_DPLL_DDR_OFFSET 0x0040
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_DISP_OFFSET 0x0044
#define AM335X_CM_WKUP_IDLEST_DPLL_DISP_OFFSET 0x0048
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050
#define AM335X_CM_WKUP_CLKSEL_DPLL_DISP_OFFSET 0x0054
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_CORE_OFFSET 0x0058
#define AM335X_CM_WKUP_IDLEST_DPLL_CORE_OFFSET 0x005c
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064
#define AM335X_CM_WKUP_CLKSEL_DPLL_CORE_OFFSET 0x0068
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_PER_OFFSET 0x006c
#define AM335X_CM_WKUP_IDLEST_DPLL_PER_OFFSET 0x0070
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078
#define AM335X_CM_WKUP_CLKDCOLDO_DPLL_PER_OFFSET 0x007c
#define AM335X_CM_WKUP_DIV_M4_DPLL_CORE_OFFSET 0x0080
#define AM335X_CM_WKUP_DIV_M5_DPLL_CORE_OFFSET 0x0084
#define AM335X_CM_WKUP_CLKMODE_DPLL_MPU_OFFSET 0x0088
#define AM335X_CM_WKUP_CLKMODE_DPLL_PER_OFFSET 0x008c
#define AM335X_CM_WKUP_CLKMODE_DPLL_CORE_OFFSET 0x0090
#define AM335X_CM_WKUP_CLKMODE_DPLL_DDR_OFFSET 0x0094
#define AM335X_CM_WKUP_CLKMODE_DPLL_DISP_OFFSET 0x0098
#define AM335X_CM_WKUP_CLKSEL_DPLL_PERIPH_OFFSET 0x009c
#define AM335X_CM_WKUP_DIV_M2_DPLL_DDR_OFFSET 0x00a0
#define AM335X_CM_WKUP_DIV_M2_DPLL_DISP_OFFSET 0x00a4
#define AM335X_CM_WKUP_DIV_M2_DPLL_MPU_OFFSET 0x00a8
#define AM335X_CM_WKUP_DIV_M2_DPLL_PER_OFFSET 0x00ac
#define AM335X_CM_WKUP_M3_CLKCTRL_OFFSET 0x00b0
#define AM335X_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4
#define AM335X_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8
#define AM335X_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc
#define AM335X_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0
#define AM335X_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4
#define AM335X_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8
#define AM335X_CM_WKUP_L4WKUP_AON_CLKSTCTRL_OFFSET 0x00cc
#define AM335X_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4
#define AM335X_CM_WKUP_DIV_M6_DPLL_CORE_OFFSET 0x00d8
#define AM335X_CM_DPLL_CLKSEL_TIMER7_CLK_OFFSET 0x0004
#define AM335X_CM_DPLL_CLKSEL_TIMER2_CLK_OFFSET 0x0008
#define AM335X_CM_DPLL_CLKSEL_TIMER3_CLK_OFFSET 0x000c
#define AM335X_CM_DPLL_CLKSEL_TIMER4_CLK_OFFSET 0x0010
#define AM335X_CM_DPLL_CLKSEL_MAC_CLK_OFFSET 0x0014
#define AM335X_CM_DPLL_CLKSEL_TIMER5_CLK_OFFSET 0x0018
#define AM335X_CM_DPLL_CLKSEL_TIMER6_CLK_OFFSET 0x001c
#define AM335X_CM_DPLL_CLKSEL_CPTS_RFT_CLK_OFFSET 0x0020
#define AM335X_CM_DPLL_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028
#define AM335X_CM_DPLL_CLKSEL_GFX_FCLK_OFFSET 0x002c
#define AM335X_CM_DPLL_CLKSEL_PRU_ICSS_OCP_CLK_OFFSET 0x0030
#define AM335X_CM_DPLL_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034
#define AM335X_CM_DPLL_CLKSEL_WDT1_CLK_OFFSET 0x0038
#define AM335X_CM_DPLL_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c
#define AM335X_CM_MPU_CLKSTCTRL_OFFSET 0x0000
#define AM335X_CM_MPU_CLKCTRL_OFFSET 0x0004
#define AM335X_CM_DEVICE_CLKOUT_CTRL_OFFSET 0x0000
#define AM335X_CM_RTC_CLKCTRL_OFFSET 0x0000
#define AM335X_CM_RTC_CLKSTCTRL_OFFSET 0x0004
#define AM335X_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
#define AM335X_CM_GFX_CLKCTRL_OFFSET 0x0004
#define AM335X_CM_GFX_L4LS_CLKSTCTRL_OFFSET 0x000c
#define AM335X_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010
#define AM335X_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014
#define AM335X_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
#define AM335X_CM_CEFUSE_CLKCTRL_OFFSET 0x0020
/* Clock Module Register Addresses **********************************************************/
#define AM335X_CM_PER_L4LS_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_L4LS_CLKSTCTRL_OFFSET)
#define AM335X_CM_PER_L3S_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_L3S_CLKSTCTRL_OFFSET)
#define AM335X_CM_PER_L3_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_L3_CLKSTCTRL_OFFSET)
#define AM335X_CM_PER_CPGMAC0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_CPGMAC0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_LCDC_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_LCDC_CLKCTRL_OFFSET)
#define AM335X_CM_PER_USB0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_USB0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TPTC0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TPTC0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_EMIF_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_EMIF_CLKCTRL_OFFSET)
#define AM335X_CM_PER_OCMCRAM_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_OCMCRAM_CLKCTRL_OFFSET)
#define AM335X_CM_PER_GPMC_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_GPMC_CLKCTRL_OFFSET)
#define AM335X_CM_PER_MCASP0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_MCASP0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_UART5_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_UART5_CLKCTRL_OFFSET)
#define AM335X_CM_PER_MMC0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_MMC0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_ELM_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_ELM_CLKCTRL_OFFSET)
#define AM335X_CM_PER_I2C2_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_I2C2_CLKCTRL_OFFSET)
#define AM335X_CM_PER_I2C1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_I2C1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_SPI0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_SPI0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_SPI1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_SPI1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_L4LS_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_L4LS_CLKCTRL_OFFSET)
#define AM335X_CM_PER_MCASP1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_MCASP1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_UART1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_UART1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_UART2_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_UART2_CLKCTRL_OFFSET)
#define AM335X_CM_PER_UART3_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_UART3_CLKCTRL_OFFSET)
#define AM335X_CM_PER_UART4_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_UART4_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TIMER7_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TIMER7_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TIMER2_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TIMER2_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TIMER3_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TIMER3_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TIMER4_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TIMER4_CLKCTRL_OFFSET)
#define AM335X_CM_PER_GPIO1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_GPIO1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_GPIO2_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_GPIO2_CLKCTRL_OFFSET)
#define AM335X_CM_PER_GPIO3_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_GPIO3_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TPCC_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TPCC_CLKCTRL_OFFSET)
#define AM335X_CM_PER_DCAN0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_DCAN0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_DCAN1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_DCAN1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_EPWMSS1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_EPWMSS0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_EPWMSS2_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL_OFFSET)
#define AM335X_CM_PER_L3_INSTR_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_L3_INSTR_CLKCTRL_OFFSET)
#define AM335X_CM_PER_L3_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_L3_CLKCTRL_OFFSET)
#define AM335X_CM_PER_IEEE5000_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_IEEE5000_CLKCTRL_OFFSET)
#define AM335X_CM_PER_PRU_ICSS_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_PRU_ICSS_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TIMER5_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TIMER5_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TIMER6_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TIMER6_CLKCTRL_OFFSET)
#define AM335X_CM_PER_MMC1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_MMC1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_MMC2_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_MMC2_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TPTC1_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TPTC1_CLKCTRL_OFFSET)
#define AM335X_CM_PER_TPTC2_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_TPTC2_CLKCTRL_OFFSET)
#define AM335X_CM_PER_SPINLOCK_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_SPINLOCK_CLKCTRL_OFFSET)
#define AM335X_CM_PER_MAILBOX0_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_MAILBOX0_CLKCTRL_OFFSET)
#define AM335X_CM_PER_L4HS_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_L4HS_CLKSTCTRL_OFFSET)
#define AM335X_CM_PER_L4HS_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_L4HS_CLKCTRL_OFFSET)
#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET)
#define AM335X_CM_PER_OCPWP_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_OCPWP_CLKCTRL_OFFSET)
#define AM335X_CM_PER_PRU_ICSS_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_PRU_ICSS_CLKSTCTRL_OFFSET)
#define AM335X_CM_PER_CPSW_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_CPSW_CLKSTCTRL_OFFSET)
#define AM335X_CM_PER_LCDC_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_LCDC_CLKSTCTRL_OFFSET)
#define AM335X_CM_PER_CLKDIV32K_CLKCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_CLKDIV32K_CLKCTRL_OFFSET)
#define AM335X_CM_PER_CLK_24MHZ_CLKSTCTRL (AM335X_CM_PER_VADDR + AM335X_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET)
#define AM335X_CM_WKUP_CLKSTCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKSTCTRL_OFFSET)
#define AM335X_CM_WKUP_CONTROL_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CONTROL_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_GPIO0_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_GPIO0_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_L4WKUP_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_L4WKUP_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_TIMER0_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_TIMER0_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_DEBUGSS_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_L3_AON_CLKSTCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_L3_AON_CLKSTCTRL_OFFSET)
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_MPU (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_AUTOIDLE_DPLL_MPU_OFFSET)
#define AM335X_CM_WKUP_IDLEST_DPLL_MPU (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_IDLEST_DPLL_MPU_OFFSET)
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_MPU (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_MPU_OFFSET)
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_MPU (AM335X_CM_WKUP_VADDR + AM335X_CM-WKUP_SSC_MODFREQDIV_DPLL_MPU_OFFSET)
#define AM335X_CM_WKUP_CLKSEL_DPLL_MPU (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKSEL_DPLL_MPU_OFFSET)
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_DDR (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_AUTOIDLE_DPLL_DDR_OFFSET)
#define AM335X_CM_WKUP_IDLEST_DPLL_DDR (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_IDLEST_DPLL_DDR_OFFSET)
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_DDR (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_DDR_OFFSET)
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_DDR (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_DDR_OFFSET)
#define AM335X_CM_WKUP_CLKSEL_DPLL_DDR (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKSEL_DPLL_DDR_OFFSET)
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_DISP (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_AUTOIDLE_DPLL_DISP_OFFSET)
#define AM335X_CM_WKUP_IDLEST_DPLL_DISP (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_IDLEST_DPLL_DISP_OFFSET)
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_DISP (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_DISP_OFFSET)
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_DISP (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_DISP_OFFSET)
#define AM335X_CM_WKUP_CLKSEL_DPLL_DISP (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKSEL_DPLL_DISP_OFFSET)
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_AUTOIDLE_DPLL_CORE_OFFSET)
#define AM335X_CM_WKUP_IDLEST_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_IDLEST_DPLL_CORE_OFFSET)
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_CORE_OFFSET)
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_CORE_OFFSET)
#define AM335X_CM_WKUP_CLKSEL_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKSEL_DPLL_CORE_OFFSET)
#define AM335X_CM_WKUP_AUTOIDLE_DPLL_PER (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_AUTOIDLE_DPLL_PER_OFFSET)
#define AM335X_CM_WKUP_IDLEST_DPLL_PER (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_IDLEST_DPLL_PER_OFFSET)
#define AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_PER (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_DELTAMSTEP_DPLL_PER_OFFSET)
#define AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_PER (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SSC_MODFREQDIV_DPLL_PER_OFFSET)
#define AM335X_CM_WKUP_CLKDCOLDO_DPLL_PER (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKDCOLDO_DPLL_PER_OFFSET)
#define AM335X_CM_WKUP_DIV_M4_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_DIV_M4_DPLL_CORE_OFFSET)
#define AM335X_CM_WKUP_DIV_M5_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_DIV_M5_DPLL_CORE_OFFSET)
#define AM335X_CM_WKUP_CLKMODE_DPLL_MPU (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKMODE_DPLL_MPU_OFFSET)
#define AM335X_CM_WKUP_CLKMODE_DPLL_PER (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKMODE_DPLL_PER_OFFSET)
#define AM335X_CM_WKUP_CLKMODE_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKMODE_DPLL_CORE_OFFSET)
#define AM335X_CM_WKUP_CLKMODE_DPLL_DDR (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKMODE_DPLL_DDR_OFFSET)
#define AM335X_CM_WKUP_CLKMODE_DPLL_DISP (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKMODE_DPLL_DISP_OFFSET)
#define AM335X_CM_WKUP_CLKSEL_DPLL_PERIPH (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_CLKSEL_DPLL_PERIPH_OFFSET)
#define AM335X_CM_WKUP_DIV_M2_DPLL_DDR (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_DIV_M2_DPLL_DDR_OFFSET)
#define AM335X_CM_WKUP_DIV_M2_DPLL_DISP (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_DIV_M2_DPLL_DISP_OFFSET)
#define AM335X_CM_WKUP_DIV_M2_DPLL_MPU (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_DIV_M2_DPLL_MPU_OFFSET)
#define AM335X_CM_WKUP_DIV_M2_DPLL_PER (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_DIV_M2_DPLL_PER_OFFSET)
#define AM335X_CM_WKUP_WKUP_M3_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_M3_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_UART0_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_UART0_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_I2C0_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_I2C0_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_ADC_TSC_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_SMARTREFLEX0_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SMARTREFLEX0_CLKCTRL _OFFSET)
#define AM335X_CM_WKUP_TIMER1_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_TIMER1_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_SMARTREFLEX1_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_L4WKUP_AON_CLKSTCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_L4WKUP_AON_CLKSTCTRL_OFFSET)
#define AM335X_CM_WKUP_WDT1_CLKCTRL (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_WDT1_CLKCTRL_OFFSET)
#define AM335X_CM_WKUP_DIV_M6_DPLL_CORE (AM335X_CM_WKUP_VADDR + AM335X_CM_WKUP_DIV_M6_DPLL_CORE_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_TIMER7_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_TIMER7_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_TIMER2_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_TIMER2_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_TIMER3_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_TIMER3_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_TIMER4_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_TIMER4_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_MAC_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_MAC_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_TIMER5_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_TIMER5_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_TIMER6_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_TIMER6_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_CPTS_RFT_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_CPTS_RFT_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_TIMER1MS_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_TIMER1MS_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_GFX_FCLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_GFX_FCLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_PRU_ICSS_OCP_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_PRU_ICSS_OCP_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_LCDC_PIXEL_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_LCDC_PIXEL_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_WDT1_CLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_WDT1_CLK_OFFSET)
#define AM335X_CM_DPLL_CLKSEL_GPIO0_DBCLK (AM335X_CM_DPLL_VADDR + AM335X_CM_DPLL_CLKSEL_GPIO0_DBCLK_OFFSET)
#define AM335X_CM_MPU_CLKSTCTRL (AM335X_CM_MPU_VADDR + AM335X_CM_MPU_CLKSTCTRL_OFFSET)
#define AM335X_CM_MPU_CLKCTRL (AM335X_CM_MPU_VADDR + AM335X_CM_MPU_CLKCTRL_OFFSET)
#define AM335X_CM_DEVICE_CLKOUT_CTRL (AM335X_CM_DEVICE_VADDR + AM335X_CM_DEVICE_CLKOUT_CTRL_OFFSET)
#define AM335X_CM_RTC_CLKCTRL (AM335X_CM_RTC_VADDR + AM335X_CM_RTC_CLKCTRL_OFFSET)
#define AM335X_CM_RTC_CLKSTCTRL (AM335X_CM_RTC_VADDR + AM335X_CM_RTC_CLKSTCTRL_OFFSET)
#define AM335X_CM_GFX_L3_CLKSTCTRL (AM335X_CM_GFX_VADDR + AM335X_CM_GFX_L3_CLKSTCTRL_OFFSET)
#define AM335X_CM_GFX_CLKCTRL (AM335X_CM_GFX_VADDR + AM335X_CM_GFX_CLKCTRL_OFFSET)
#define AM335X_CM_GFX_L4LS_CLKSTCTRL (AM335X_CM_GFX_VADDR + AM335X_CM_GFX_L4LS_CLKSTCTRL_OFFSET)
#define AM335X_CM_GFX_MMUCFG_CLKCTRL (AM335X_CM_GFX_VADDR + AM335X_CM_GFX_MMUCFG_CLKCTRL_OFFSET)
#define AM335X_CM_GFX_MMUDATA_CLKCTRL (AM335X_CM_GFX_VADDR + AM335X_CM_GFX_MMUDATA_CLKCTRL_OFFSET)
#define AM335X_CM_CEFUSE_CLKSTCTRL (AM335X_CM_CEFUSE_VADDR + AM335X_CM_CEFUSE_CLKSTCTRL_OFFSET)
#define AM335X_CM_CEFUSE_CLKCTRL (AM335X_CM_CEFUSE_VADDR + AM335X_CM_CEFUSE_CLKCTRL_OFFSET)
/* Clock Module Register Bit Definitions **************************************************/
#define CM_WKUP_CLKCTRL_MODULEMODE_SHIFT (0) /* Bits 0-1: Control the way mandatory clocks are managed */
#define CM_WKUP_CLKCTRL_MODULEMODE_MASK (3 << CM_WKUP_CLKCTRL_MODULEMODE_SHIFT)
# define CM_WKUP_CLKCTRL_MODULEMODE_DISABLE (0 << CM_WKUP_CLKCTRL_MODULEMODE_SHIFT) /* Module is disable by SW */
# define CM_WKUP_CLKCTRL_MODULEMODE_ENABLE (2 << CM_WKUP_CLKCTRL_MODULEMODE_SHIFT) /* Module is explicitly enabled */
#define CM_WKUP_CLKCTRL_IDLEST_SHIFT (16) /* Bits 16-17: Module idle status. */
#define CM_WKUP_CLKCTRL_IDLEST_MASK (3 << CM_WKUP_CLKCTRL_IDLEST_SHIFT)
# define CM_WKUP_CLKCTRL_IDLEST_FUNC (0 << CM_WKUP_CLKCTRL_IDLEST_SHIFT) /* Module is fully functional, including OCP */
# define CM_WKUP_CLKCTRL_IDLEST_TRANS (1 << CM_WKUP_CLKCTRL_IDLEST_SHIFT) /* Module is performing transition: wakeup, or sleep, or sleep abortion */
# define CM_WKUP_CLKCTRL_IDLEST_IDLE (2 << CM_WKUP_CLKCTRL_IDLEST_SHIFT) /* Module is in Idle mode (only OCP part) */
# define CM_WKUP_CLKCTRL_IDLEST_DISABLED (3 << CM_WKUP_CLKCTRL_IDLEST_SHIFT) /* Module is disabled and cannot be accessed */
#define CM_WKUP_CLKCTRL_STBYST (1 << 18) /* Bit 18: Module standby status. */
#define CM_DPLL_DMTIMER1MS_CLKSEL_SHIFT (0) /* Bits 0-2: Mux select line for DMTIMER_1MS clock */
#define CM_DPLL_DMTIMER1MS_CLKSEL_MASK (7 << CM_DPLL_DMTIMER1MS_CLKSEL_SHIFT)
# define CM_DPLL_DMTIMER1_CLKSEL_CLK_M_OSC (0 << CM_DPLL_DMTIMER1MS_CLKSEL_SHIFT) /* Select CLK_M_OSC clock */
# define CM_DPLL_DMTIMER1_CLKSEL_CLK_32KHZ (1 << CM_DPLL_DMTIMER1MS_CLKSEL_SHIFT) /* Select CLK_32KHZ clock */
# define CM_DPLL_DMTIMER1_CLKSEL_TCLKIN (2 << CM_DPLL_DMTIMER1MS_CLKSEL_SHIFT) /* Select TCLKIN clock */
# define CM_DPLL_DMTIMER1_CLKSEL_CLK_RC32K (3 << CM_DPLL_DMTIMER1MS_CLKSEL_SHIFT) /* Select CLK_RC32K clock */
# define CM_DPLL_DMTIMER1_CLKSEL_CLK_32768 (4 << CM_DPLL_DMTIMER1MS_CLKSEL_SHIFT) /* Selects the CLK_32768 from 32KHz Crystal Osc */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CM_H */
arch/arm/src/am335x/hardware/am335x_dcan.h
+423
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@@ -0,0 +1,423 @@
/********************************************************************************************
* arch/arm/src/am335x/hardware/am335x_cm.h
*
* Copyright (C) 2019 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_DCAN_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_DCAN_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include <hardware/am335x_memorymap.h>
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_DCAN_CTL_OFFSET 0x0000 /* CAN Control Register */
#define AM335X_DCAN_ES_OFFSET 0x0004 /* Error and Status Register */
#define AM335X_DCAN_ERRC_OFFSET 0x0008 /* Error Counter Register */
#define AM335X_DCAN_BTR_OFFSET 0x000c /* Bit Timing Register */
#define AM335X_DCAN_INT_OFFSET 0x0010 /* Interrupt Register */
#define AM335X_DCAN_TEST_OFFSET 0x0014 /* Test Register */
#define AM335X_DCAN_PERR_OFFSET 0x001c /* Parity Error Code Register */
#define AM335X_DCAN_ABOTR_OFFSET 0x0080 /* Auto-Bus-On Time Register */
#define AM335X_DCAN_TXRQ_X_OFFSET 0x0084 /* Transmission Request X Register */
#define AM335X_DCAN_TXRQ12_OFFSET 0x0088 /* Transmission Request Register 12 */
#define AM335X_DCAN_TXRQ34_OFFSET 0x008c /* Transmission Request Register 34 */
#define AM335X_DCAN_TXRQ56_OFFSET 0x0090 /* Transmission Request Register 56 */
#define AM335X_DCAN_TXRQ78_OFFSET 0x0094 /* Transmission Request Register 78 */
#define AM335X_DCAN_NWDAT_X_OFFSET 0x0098 /* New Data X Register */
#define AM335X_DCAN_NWDAT12_OFFSET 0x009c /* New Data Register 12 */
#define AM335X_DCAN_NWDAT34_OFFSET 0x00a0 /* New Data Register 34 */
#define AM335X_DCAN_NWDAT56_OFFSET 0x00a4 /* New Data Register 56 */
#define AM335X_DCAN_NWDAT78_OFFSET 0x00a8 /* New Data Register 78 */
#define AM335X_DCAN_INTPND_X_OFFSET 0x00ac /* Interrupt Pending X Register */
#define AM335X_DCAN_INTPND12_OFFSET 0x00b0 /* Interrupt Pending Register 12 */
#define AM335X_DCAN_INTPND34_OFFSET 0x00b4 /* Interrupt Pending Register 34 */
#define AM335X_DCAN_INTPND56_OFFSET 0x00b8 /* Interrupt Pending Register 56 */
#define AM335X_DCAN_INTPND78_OFFSET 0x00bc /* Interrupt Pending Register 78 */
#define AM335X_DCAN_MSGVAL_X_OFFSET 0x00c0 /* Message Valid X Register */
#define AM335X_DCAN_MSGVAL12_OFFSET 0x00c4 /* Message Valid Register 12 */
#define AM335X_DCAN_MSGVAL34_OFFSET 0x00c8 /* Message Valid Register 34 */
#define AM335X_DCAN_MSGVAL56_OFFSET 0x00cc /* Message Valid Register 56 */
#define AM335X_DCAN_MSGVAL78_OFFSET 0x00d0 /* Message Valid Register 78 */
#define AM335X_DCAN_INTMUX12_OFFSET 0x00d8 /* Interrupt Multiplexer Register 12 */
#define AM335X_DCAN_INTMUX34_OFFSET 0x00dc /* Interrupt Multiplexer Register 34 */
#define AM335X_DCAN_INTMUX56_OFFSET 0x00e0 /* Interrupt Multiplexer Register 56 */
#define AM335X_DCAN_INTMUX78_OFFSET 0x00e4 /* Interrupt Multiplexer Register 78 */
#define AM335X_DCAN_IF1CMD_OFFSET 0x0100 /* IF1 Command Registers */
#define AM335X_DCAN_IF1MSK_OFFSET 0x0104 /* IF1 Mask Register */
#define AM335X_DCAN_IF1ARB_OFFSET 0x0108 /* IF1 Arbitration Register */
#define AM335X_DCAN_IF1MCTL_OFFSET 0x010c /* IF1 Message Control Register */
#define AM335X_DCAN_IF1DATA_OFFSET 0x0110 /* IF1 Data A Register */
#define AM335X_DCAN_IF1DATB_OFFSET 0x0114 /* IF1 Data B Register */
#define AM335X_DCAN_IF2CMD_OFFSET 0x0120 /* IF2 Command Registers */
#define AM335X_DCAN_IF2MSK_OFFSET 0x0124 /* IF2 Mask Register */
#define AM335X_DCAN_IF2ARB_OFFSET 0x0128 /* IF2 Arbitration Register */
#define AM335X_DCAN_IF2MCTL_OFFSET 0x012c /* IF2 Message Control Register */
#define AM335X_DCAN_IF2DATA_OFFSET 0x0130 /* IF2 Data A Register */
#define AM335X_DCAN_IF2DATB_OFFSET 0x0134 /* IF2 Data B Register */
#define AM335X_DCAN_IF3OBS_OFFSET 0x0140 /* IF3 Observation Register */
#define AM335X_DCAN_IF3MSK_OFFSET 0x0144 /* IF3 Mask Register */
#define AM335X_DCAN_IF3ARB_OFFSET 0x0148 /* IF3 Arbitration Register */
#define AM335X_DCAN_IF3MCTL_OFFSET 0x014c /* IF3 Message Control Register */
#define AM335X_DCAN_IF3DATA_OFFSET 0x0150 /* IF3 Data A Register */
#define AM335X_DCAN_IF3DATB_OFFSET 0x0154 /* IF3 Data B Register */
#define AM335X_DCAN_IF3UPD12_OFFSET 0x0160 /* IF3 Update Enable Register 12 */
#define AM335X_DCAN_IF3UPD34_OFFSET 0x0164 /* IF3 Update Enable Register 34 */
#define AM335X_DCAN_IF3UPD56_OFFSET 0x0168 /* IF3 Update Enable Register 56 */
#define AM335X_DCAN_IF3UPD78_OFFSET 0x016c /* IF3 Update Enable Register 78 */
#define AM335X_DCAN_TIOC_OFFSET 0x01e0 /* CAN TX IO Control Register */
#define AM335X_DCAN_RIOC_OFFSET 0x01e4 /* CAN RX IO Control Register */
#define AM335X_DCAN_TXRQ_OFFSET(n) (0x0088 + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_NWDAT_OFFSET(n) (0x009c + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_INTPND_OFFSET(n) (0x00b0 + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_MSGVAL_OFFSET(n) (0x00c4 + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_INTMUX_OFFSET(n) (0x00d8 + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_IFCMD_OFFSET(n) (0x0100 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFMSK_OFFSET(n) (0x0104 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFARB_OFFSET(n) (0x0108 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFMCTL_OFFSET(n) (0x010c + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFDATA_OFFSET(n) (0x0110 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFDATB_OFFSET(n) (0x0114 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IF3UPD_OFFSET(n) (0x0160 + ((((unsigned int)(n) - 1) >> 5) << 2))
/* Register virtual addresses *******************************************************/
#define AM335X_DCAN0_CTL (AM335X_DCAN0_VADDR + AM335X_DCAN_CTL_OFFSET)
#define AM335X_DCAN0_ES (AM335X_DCAN0_VADDR + AM335X_DCAN_ES_OFFSET)
#define AM335X_DCAN0_ERRC (AM335X_DCAN0_VADDR + AM335X_DCAN_ERRC_OFFSET)
#define AM335X_DCAN0_BTR (AM335X_DCAN0_VADDR + AM335X_DCAN_BTR_OFFSET)
#define AM335X_DCAN0_INT (AM335X_DCAN0_VADDR + AM335X_DCAN_INT_OFFSET)
#define AM335X_DCAN0_TEST (AM335X_DCAN0_VADDR + AM335X_DCAN_TEST_OFFSET)
#define AM335X_DCAN0_PERR (AM335X_DCAN0_VADDR + AM335X_DCAN_PERR_OFFSET)
#define AM335X_DCAN0_ABOTR (AM335X_DCAN0_VADDR + AM335X_DCAN_ABOTR_OFFSET)
#define AM335X_DCAN0_TXRQ_X (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ_X_OFFSET)
#define AM335X_DCAN0_TXRQ12 (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ12_OFFSET)
#define AM335X_DCAN0_TXRQ34 (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ34_OFFSET)
#define AM335X_DCAN0_TXRQ56 (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ56_OFFSET)
#define AM335X_DCAN0_TXRQ78 (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ78_OFFSET)
#define AM335X_DCAN0_NWDAT_X (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT_X_OFFSET)
#define AM335X_DCAN0_NWDAT12 (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT12_OFFSET)
#define AM335X_DCAN0_NWDAT34 (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT34_OFFSET)
#define AM335X_DCAN0_NWDAT56 (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT56_OFFSET)
#define AM335X_DCAN0_NWDAT78 (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT78_OFFSET)
#define AM335X_DCAN0_INTPND_X (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND_X_OFFSET)
#define AM335X_DCAN0_INTPND12 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND12_OFFSET)
#define AM335X_DCAN0_INTPND34 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND34_OFFSET)
#define AM335X_DCAN0_INTPND56 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND56_OFFSET)
#define AM335X_DCAN0_INTPND78 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND78_OFFSET)
#define AM335X_DCAN0_MSGVAL_X (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL_X_OFFSET)
#define AM335X_DCAN0_MSGVAL12 (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL12_OFFSET)
#define AM335X_DCAN0_MSGVAL34 (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL34_OFFSET)
#define AM335X_DCAN0_MSGVAL56 (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL56_OFFSET)
#define AM335X_DCAN0_MSGVAL78 (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL78_OFFSET)
#define AM335X_DCAN0_INTMUX12 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX12_OFFSET)
#define AM335X_DCAN0_INTMUX34 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX34_OFFSET)
#define AM335X_DCAN0_INTMUX56 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX56_OFFSET)
#define AM335X_DCAN0_INTMUX78 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX78_OFFSET)
#define AM335X_DCAN0_IF1CMD (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1CMD_OFFSET)
#define AM335X_DCAN0_IF1MSK (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1MSK_OFFSET)
#define AM335X_DCAN0_IF1ARB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1ARB_OFFSET)
#define AM335X_DCAN0_IF1MCTL (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1MCTL_OFFSET)
#define AM335X_DCAN0_IF1DATA (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1DATA_OFFSET)
#define AM335X_DCAN0_IF1DATB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1DATB_OFFSET)
#define AM335X_DCAN0_IF2CMD (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2CMD_OFFSET)
#define AM335X_DCAN0_IF2MSK (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2MSK_OFFSET)
#define AM335X_DCAN0_IF2ARB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2ARB_OFFSET)
#define AM335X_DCAN0_IF2MCTL (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2MCTL_OFFSET)
#define AM335X_DCAN0_IF2DATA (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2DATA_OFFSET)
#define AM335X_DCAN0_IF2DATB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2DATB_OFFSET)
#define AM335X_DCAN0_IF3OBS (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3OBS_OFFSET)
#define AM335X_DCAN0_IF3MSK (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3MSK_OFFSET)
#define AM335X_DCAN0_IF3ARB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3ARB_OFFSET)
#define AM335X_DCAN0_IF3MCTL (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3MCTL_OFFSET)
#define AM335X_DCAN0_IF3DATA (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3DATA_OFFSET)
#define AM335X_DCAN0_IF3DATB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3DATB_OFFSET)
#define AM335X_DCAN0_IF3UPD12 (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD12_OFFSET)
#define AM335X_DCAN0_IF3UPD34 (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD34_OFFSET)
#define AM335X_DCAN0_IF3UPD56 (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD56_OFFSET)
#define AM335X_DCAN0_IF3UPD78 (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD78_OFFSET)
#define AM335X_DCAN0_TIOC (AM335X_DCAN0_VADDR + AM335X_DCAN_TIOC_OFFSET)
#define AM335X_DCAN0_RIOC (AM335X_DCAN0_VADDR + AM335X_DCAN_RIOC_OFFSET)
#define AM335X_DCAN0_TXRQ(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ_OFFSET(n))
#define AM335X_DCAN0_NWDAT(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT_OFFSET(n))
#define AM335X_DCAN0_INTPND(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND_OFFSET(n))
#define AM335X_DCAN0_MSGVAL(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL_OFFSET(n))
#define AM335X_DCAN0_INTMUX(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX_OFFSET(n))
#define AM335X_DCAN0_IFCMD(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFCMD_OFFSET(n))
#define AM335X_DCAN0_IFMSK(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFMSK_OFFSET(n))
#define AM335X_DCAN0_IFARB(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFARB_OFFSET(n))
#define AM335X_DCAN0_IFMCTL(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFMCTL_OFFSET(n))
#define AM335X_DCAN0_IFDATA(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFDATA_OFFSET(n))
#define AM335X_DCAN0_IFDATB(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFDATB_OFFSET(n))
#define AM335X_DCAN0_IF3UPD(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD_OFFSET(n))
#define AM335X_DCAN1_CTL (AM335X_DCAN1_VADDR + AM335X_DCAN_CTL_OFFSET)
#define AM335X_DCAN1_ES (AM335X_DCAN1_VADDR + AM335X_DCAN_ES_OFFSET)
#define AM335X_DCAN1_ERRC (AM335X_DCAN1_VADDR + AM335X_DCAN_ERRC_OFFSET)
#define AM335X_DCAN1_BTR (AM335X_DCAN1_VADDR + AM335X_DCAN_BTR_OFFSET)
#define AM335X_DCAN1_INT (AM335X_DCAN1_VADDR + AM335X_DCAN_INT_OFFSET)
#define AM335X_DCAN1_TEST (AM335X_DCAN1_VADDR + AM335X_DCAN_TEST_OFFSET)
#define AM335X_DCAN1_PERR (AM335X_DCAN1_VADDR + AM335X_DCAN_PERR_OFFSET)
#define AM335X_DCAN1_ABOTR (AM335X_DCAN1_VADDR + AM335X_DCAN_ABOTR_OFFSET)
#define AM335X_DCAN1_TXRQ_X (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ_X_OFFSET)
#define AM335X_DCAN1_TXRQ12 (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ12_OFFSET)
#define AM335X_DCAN1_TXRQ34 (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ34_OFFSET)
#define AM335X_DCAN1_TXRQ56 (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ56_OFFSET)
#define AM335X_DCAN1_TXRQ78 (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ78_OFFSET)
#define AM335X_DCAN1_NWDAT_X (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT_X_OFFSET)
#define AM335X_DCAN1_NWDAT12 (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT12_OFFSET)
#define AM335X_DCAN1_NWDAT34 (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT34_OFFSET)
#define AM335X_DCAN1_NWDAT56 (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT56_OFFSET)
#define AM335X_DCAN1_NWDAT78 (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT78_OFFSET)
#define AM335X_DCAN1_INTPND_X (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND_X_OFFSET)
#define AM335X_DCAN1_INTPND12 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND12_OFFSET)
#define AM335X_DCAN1_INTPND34 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND34_OFFSET)
#define AM335X_DCAN1_INTPND56 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND56_OFFSET)
#define AM335X_DCAN1_INTPND78 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND78_OFFSET)
#define AM335X_DCAN1_MSGVAL_X (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL_X_OFFSET)
#define AM335X_DCAN1_MSGVAL12 (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL12_OFFSET)
#define AM335X_DCAN1_MSGVAL34 (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL34_OFFSET)
#define AM335X_DCAN1_MSGVAL56 (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL56_OFFSET)
#define AM335X_DCAN1_MSGVAL78 (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL78_OFFSET)
#define AM335X_DCAN1_INTMUX12 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX12_OFFSET)
#define AM335X_DCAN1_INTMUX34 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX34_OFFSET)
#define AM335X_DCAN1_INTMUX56 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX56_OFFSET)
#define AM335X_DCAN1_INTMUX78 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX78_OFFSET)
#define AM335X_DCAN1_IF1CMD (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1CMD_OFFSET)
#define AM335X_DCAN1_IF1MSK (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1MSK_OFFSET)
#define AM335X_DCAN1_IF1ARB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1ARB_OFFSET)
#define AM335X_DCAN1_IF1MCTL (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1MCTL_OFFSET)
#define AM335X_DCAN1_IF1DATA (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1DATA_OFFSET)
#define AM335X_DCAN1_IF1DATB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1DATB_OFFSET)
#define AM335X_DCAN1_IF2CMD (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2CMD_OFFSET)
#define AM335X_DCAN1_IF2MSK (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2MSK_OFFSET)
#define AM335X_DCAN1_IF2ARB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2ARB_OFFSET)
#define AM335X_DCAN1_IF2MCTL (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2MCTL_OFFSET)
#define AM335X_DCAN1_IF2DATA (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2DATA_OFFSET)
#define AM335X_DCAN1_IF2DATB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2DATB_OFFSET)
#define AM335X_DCAN1_IF3OBS (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3OBS_OFFSET)
#define AM335X_DCAN1_IF3MSK (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3MSK_OFFSET)
#define AM335X_DCAN1_IF3ARB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3ARB_OFFSET)
#define AM335X_DCAN1_IF3MCTL (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3MCTL_OFFSET)
#define AM335X_DCAN1_IF3DATA (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3DATA_OFFSET)
#define AM335X_DCAN1_IF3DATB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3DATB_OFFSET)
#define AM335X_DCAN1_IF3UPD12 (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD12_OFFSET)
#define AM335X_DCAN1_IF3UPD34 (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD34_OFFSET)
#define AM335X_DCAN1_IF3UPD56 (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD56_OFFSET)
#define AM335X_DCAN1_IF3UPD78 (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD78_OFFSET)
#define AM335X_DCAN1_TIOC (AM335X_DCAN1_VADDR + AM335X_DCAN_TIOC_OFFSET)
#define AM335X_DCAN1_RIOC (AM335X_DCAN1_VADDR + AM335X_DCAN_RIOC_OFFSET)
#define AM335X_DCAN1_TXRQ(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ_OFFSET(n))
#define AM335X_DCAN1_NWDAT(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT_OFFSET(n))
#define AM335X_DCAN1_INTPND(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND_OFFSET(n))
#define AM335X_DCAN1_MSGVAL(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL_OFFSET(n))
#define AM335X_DCAN1_INTMUX(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX_OFFSET(n))
#define AM335X_DCAN1_IFCMD(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFCMD_OFFSET(n))
#define AM335X_DCAN1_IFMSK(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFMSK_OFFSET(n))
#define AM335X_DCAN1_IFARB(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFARB_OFFSET(n))
#define AM335X_DCAN1_IFMCTL(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFMCTL_OFFSET(n))
#define AM335X_DCAN1_IFDATA(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFDATA_OFFSET(n))
#define AM335X_DCAN1_IFDATB(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFDATB_OFFSET(n))
#define AM335X_DCAN1_IF3UPD(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD_OFFSET(n))
/* Register bit field definitions ***************************************************/
#define DCAN_CTL_INIT (1 << 0) /* Bit 0: Initialization mode */
#define DCAN_CTL_IE0 (1 << 1) /* Bit 1: Interrupt line 0 enable */
#define DCAN_CTL_SIE (1 << 2) /* Bit 2: Status change interrupt enable */
#define DCAN_CTL_EIE (1 << 3) /* Bit 3: Error interrupt enable */
#define DCAN_CTL_DAR (1 << 5) /* Bit 5: Disable automatic retransmission */
#define DCAN_CTL_CCE (1 << 6) /* Bit 6: Configuration change enable */
#define DCAN_CTL_TEST (1 << 7) /* Bit 7: Test mode enable */
#define DCAN_CTL_IDS (1 << 8) /* Bit 8: Interruption debug support enable */
#define DCAN_CTL_ABO (1 << 9) /* Bit 9: Auto-Bus-On enable */
#define DCAN_CTL_PMD_SHIFT (10) /* Bits 10-13: Parity on/off. */
#define DCAN_CTL_PMD_MASK (15 << DCAN_CTL_PMD_SHIFT)
# define DCAN_CTL_PMD_OFF (5 << DCAN_CTL_PMD_SHIFT) /* Parity function disabled */
# define DCAN_CTL_PMD_ON (10 << DCAN_CTL_PMD_SHIFT) /* Parity function enabled */
#define DCAN_CTL_SWR (1 << 15) /* Bit 15: Software reset enable */
#define DCAN_CTL_INITDBG (1 << 16) /* Bit 16: Internal init state while debug access */
#define DCAN_CTL_IE1 (1 << 17) /* Bit 17: Interrupt line 1 enable */
#define DCAN_CTL_DE1 (1 << 18) /* Bit 18: Enable DMA request line for IF1 */
#define DCAN_CTL_DE2 (1 << 19) /* Bit 19: Enable DMA request line for IF2 */
#define DCAN_CTL_DE3 (1 << 20) /* Bit 20: Enable DMA request line for IF3 */
#define DCAN_CTL_PDR (1 << 24) /* Bit 24: Request for local low power-down mode */
#define DCAN_CTL_WUBA (1 << 25) /* Bit 25: Automatic wake up on bus activity when in local power-down mode */
#define DCAN_ES_LEC_SHIFT (0) /* Bits 0-2: Last error code. */
#define DCAN_ES_LEC_MASK (7 << DCAN_ES_LEC_SHIFT)
# define DCAN_ES_LEC_NO_ERROR (0 << DCAN_ES_LEC_SHIFT) /* No error */
# define DCAN_ES_LEC_STUFF_ERROR (1 << DCAN_ES_LEC_SHIFT) /* Stuff error */
# define DCAN_ES_LEC_FORM_ERROR (2 << DCAN_ES_LEC_SHIFT) /* Form error */
# define DCAN_ES_LEC_ACK_ERROR (3 << DCAN_ES_LEC_SHIFT) /* Ack error */
# define DCAN_ES_LEC_BIT1_ERROR (4 << DCAN_ES_LEC_SHIFT) /* Bit1 error */
# define DCAN_ES_LEC_BIT0_ERROR (5 << DCAN_ES_LEC_SHIFT) /* Bit0 error */
# define DCAN_ES_LEC_CRC_ERROR (6 << DCAN_ES_LEC_SHIFT) /* CRC error */
# define DCAN_ES_LEC_NO_EVENT (7 << DCAN_ES_LEC_SHIFT) /* No CAN bus event since last read */
#define DCAN_ES_TX_OK (1 << 3) /* Bit 3: Transmitted a message successfully */
#define DCAN_ES_RX_OK (1 << 4) /* Bit 4: Received a message successfully */
#define DCAN_ES_EPASSIVE (1 << 5) /* Bit 5: Error passive state */
#define DCAN_ES_EWARN (1 << 6) /* Bit 6: Warning state */
#define DCAN_ES_BUSOFF (1 << 7) /* Bit 7: Bus-Off state */
#define DCAN_ES_PER (1 << 8) /* Bit 8: Parity error detected */
#define DCAN_ES_WKUP_PND (1 << 9) /* Bit 9: Wake up pending */
#define DCAN_ES_PDA (1 << 10) /* Bit 10: Local power-down mode acknowledge */
#define DCAN_ERRC_TEC_SHIFT (0) /* Bits 10-13: Parity on/off. */
#define DCAN_ERRC_TEC_MASK (255 << DCAN_ERRC_TEC_SHIFT)
#define DCAN_ERRC_REC_SHIFT (8) /* Bits 10-13: Parity on/off. */
#define DCAN_ERRC_REC_MASK (255 << DCAN_ERRC_REC_SHIFT)
#define DCAN_ERRC_RP (1 << 15) /* Bit 15: Receive error passive */
#define DCAN_BTR_BRP_SHIFT (0) /* Bits 0-5: Baud rate prescaler */
#define DCAN_BTR_BRP_MASK (63 << DCAN_BTR_BRP_SHIFT)
#define DCAN_BTR_SJW_SHIFT (6) /* Bits 6-7: Synchronization Jump Width */
#define DCAN_BTR_SJW_MASK (3 << DCAN_BTR_SJW_SHIFT)
#define DCAN_BTR_TSEG1_SHIFT (8) /* Bits 8-11: Time segment before the sample point */
#define DCAN_BTR_TSEG1_MASK (15 << DCAN_BTR_TSEG1_SHIFT)
#define DCAN_BTR_TSEG2_SHIFT (12) /* Bits 12-14: Time segment after the sample point */
#define DCAN_BTR_TSEG2_MASK (7 << DCAN_BTR_TSEG2_SHIFT)
#define DCAN_BTR_BRPE_SHIFT (16) /* Bits 16-19: Baud rate prescaler extension */
#define DCAN_BTR_BRPE_MASK (15 << DCAN_BTR_BRPE_SHIFT)
#define DCAN_INT_LINE0_SHIFT (0) /* Bits 0-15: Interrupt Line 0 Identifier */
#define DCAN_INT_LINE0_MASK (65535 << DCAN_INT_LINE0_SHIFT)
#define DCAN_INT_LINE1_SHIFT (16) /* Bits 16-23: Interrupt Line 1 Identifier */
#define DCAN_INT_LINE1_MASK (255 << DCAN_INT_LINE1_SHIFT)
#define DCAN_TEST_SILENT (1 << 3) /* Bit 3: Silent mode */
#define DCAN_TEST_LBACK (1 << 4) /* Bit 4: Loopback mode */
#define DCAN_TEST_TX_SHIFT (5) /* Bits 5-6: Control of CAN_TX pin */
#define DCAN_TEST_TX_MASK (3 << DCAN_TEST_TX_SHIFT)
# define DCAN_TEST_TX_NORMAL (0 << DCAN_TEST_TX_SHIFT) /* Normal operation */
# define DCAN_TEST_TX_SAMLE (1 << DCAN_TEST_TX_SHIFT) /* Sample point can be monitored at CAN_TX pin */
# define DCAN_TEST_TX_DOMINANT (2 << DCAN_TEST_TX_SHIFT) /* CAN_TX pin drives a dominant value */
# define DCAN_TEST_TX_RECESSIVE (3 << DCAN_TEST_TX_SHIFT) /* CAN_TX pin drives a recessive value */
#define DCAN_TEST_RX (1 << 7) /* Bit 7: Receive pin monitoring */
#define DCAN_TEST_EXL (1 << 8) /* Bit 8: External loopback mode */
#define DCAN_TEST_RDA (1 << 9) /* Bit 9: RAM direct access enable */
#define DCAN_PERR_MSG_NUM_SHIFT (0) /* Bits 0-7: Message number */
#define DCAN_PERR_MSG_NUM_MASK (255 << DCAN_PERR_MSG_NUM_SHIFT)
#define DCAN_PERR_WORD_NUM_SHIFT (8) /* Bits 8-10: Word number where parity error has been detected */
#define DCAN_PERR_WORD_NUM_MASK (7 << DCAN_PERR_WORD_NUM_SHIFT)
#define DCAN_TXRQ(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: Transmission request bits (for all message objects) */
#define DCAN_NWDAT(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: New Data Bits (for all message objects) */
#define DCAN_INTPND(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: Interrupt Pending Bits (for all message objects) */
#define DCAN_MSGVAL(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: Message valid bits (for all message objects) */
#define DCAN_INTMUX_LAST (1 << 0) /* Bit 0: Last implemented message object */
#define DCAN_INTMUX(n) (1 << ((unsigned int)(n) & 0x1f)) /* Bit n: Message object number n */
#define DCAN_IFCMD_MSG_NUM_SHIFT (0) /* Bits 0-7: Number of message object in message RAM which is used for data transfer */
#define DCAN_IFCMD_MSG_NUM_MASK (0xff << DCAN_IFCMD_MSG_NUM_SHIFT)
#define DCAN_IFCMD_DMA_ACTIVE (1 << 14) /* Bit 14: Activation of DMA feature for subsequent internal IF update */
#define DCAN_IFCMD_BUSY (1 << 15) /* Bit 15: Busy flag */
#define DCAN_IFCMD_DATA_B (1 << 16) /* Bit 16: Access Data Bytes 4 to 7 */
#define DCAN_IFCMD_DATA_A (1 << 17) /* Bit 17: Access Data Bytes 0 to 3 */
#define DCAN_IFCMD_TX_RQST_NEWDAT (1 << 18) /* Bit 18: Access transmission request bit */
#define DCAN_IFCMD_CLR_INTPND (1 << 19) /* Bit 19: Clear interrupt pending bit */
#define DCAN_IFCMD_CONTROL (1 << 20) /* Bit 20: Access control bits */
#define DCAN_IFCMD_ARB (1 << 21) /* Bit 21: Access arbitration bits */
#define DCAN_IFCMD_MASK (1 << 22) /* Bit 22: Access mask bits */
#define DCAN_IFCMD_WR_RD (1 << 23) /* Bit 23: Write/Read direction */
#define DCAN_IFMSK_MSK_SHIFT (0) /* Bits 0-28: Message identifier mask */
#define DCAN_IFMSK_MSK_MASK (0x1fffffff << DCAN_IFCMD_MSK_SHIFT)
#define DCAN_IFMSK_MDIR (1 << 30) /* Bit 30: Mask message direction */
#define DCAN_IFMSK_MXTD (1 << 31) /* Bit 31: Mask extended identifier */
#define DCAN_IFARB_ID_SHIFT (0) /* Bits 0-28: Message identifier */
#define DCAN_IFARB_ID_MASK (0x1fffffff << DCAN_IFCMD_MSK_SHIFT)
#define DCAN_IFARB_DIR (1 << 29) /* Bit 29: Message direction */
#define DCAN_IFARB_XTD (1 << 30) /* Bit 30: Extended identifier */
#define DCAN_IFARB_MSG_VAL (1 << 31) /* Bit 31: Message valid */
#define DCAN_IFMCTL_DLC_SHIFT (0) /* Bits 0-3: Data length code */
#define DCAN_IFMCTL_DLC_MASK (15 << DCAN_IFMCTL_DLC_SHIFT)
#define DCAN_IFMCTL_EOB (1 << 7) /* Bit 7: Data frame has 0 to 8 data bits. */
#define DCAN_IFMCTL_TX_RQST (1 << 8) /* Bit 8: Transmit request */
#define DCAN_IFMCTL_RMT_EN (1 << 9) /* Bit 9: Remote enable */
#define DCAN_IFMCTL_RX_IE (1 << 10) /* Bit 10: Receive interrupt enable */
#define DCAN_IFMCTL_TX_IE (1 << 11) /* Bit 11: Transmit interrupt enable */
#define DCAN_IFMCTL_UMASK (1 << 12) /* Bit 12: Use acceptance mask */
#define DCAN_IFMCTL_INTPND (1 << 13) /* Bit 13: Interrupt pending */
#define DCAN_IFMCTL_MSGLST (1 << 14) /* Bit 14: Message lost (only valid for message objects with direction Receive) */
#define DCAN_IFMCTL_NEWDAT (1 << 15) /* Bit 15: New data */
#define DCAN_IF3OBS_MASK (1 << 0) /* Bit 0: Mask data read observation */
#define DCAN_IF3OBS_ARB (1 << 1) /* Bit 1: Arbitration data read observation */
#define DCAN_IF3OBS_CTRL (1 << 2) /* Bit 2: Control read observation */
#define DCAN_IF3OBS_DATAA (1 << 3) /* Bit 3: Data A read observation */
#define DCAN_IF3OBS_DATAB (1 << 4) /* Bit 4: Data B read observation */
#define DCAN_IF3OBS_SM (1 << 8) /* Bit 8: Status of Mask data read access */
#define DCAN_IF3OBS_SA (1 << 9) /* Bit 9: Status of Arbitration data read access */
#define DCAN_IF3OBS_SC (1 << 10) /* Bit 10: Status of control bits read access */
#define DCAN_IF3OBS_SDA (1 << 11) /* Bit 11: Status of Data A read access */
#define DCAN_IF3OBS_SDB (1 << 12) /* Bit 12: Status of Data B read access */
#define DCAN_IF3OBS_UPD (1 << 15) /* Bit 15: Update Data*/
#define DCAN_IF3UPD(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: IF3 Update Enabled (for all message objects) */
#define DCAN_TIOC_IN (1 << 0) /* Bit 0: CAN_TX data in */
#define DCAN_TIOC_OUT (1 << 1) /* Bit 1: CAN_TX data out write */
#define DCAN_TIOC_DIR (1 << 2) /* Bit 2: CAN_TX data direction */
#define DCAN_TIOC_FUNC (1 << 3) /* Bit 3: CAN_TX function */
#define DCAN_TIOC_OD (1 << 16) /* Bit 16: CAN_TX open drain enable */
#define DCAN_TIOC_PD (1 << 17) /* Bit 17: CAN_TX pull disable */
#define DCAN_TIOC_PU (1 << 18) /* Bit 18: CAN_TX pull up/pull down select */
#define DCAN_RIOC_IN (1 << 0) /* Bit 0: CAN_RX data in */
#define DCAN_RIOC_OUT (1 << 1) /* Bit 1: CAN_RX data out write */
#define DCAN_RIOC_DIR (1 << 2) /* Bit 2: CAN_RX data direction */
#define DCAN_RIOC_FUNC (1 << 3) /* Bit 3: CAN_RX function */
#define DCAN_RIOC_OD (1 << 16) /* Bit 16: CAN_RX open drain enable */
#define DCAN_RIOC_PD (1 << 17) /* Bit 17: CAN_RX pull disable */
#define DCAN_RIOC_PU (1 << 18) /* Bit 18: CAN_RX pull up/pull down select */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_DCAN_H */
arch/arm/src/am335x/hardware/am335x_i2c.h
+299
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@@ -0,0 +1,299 @@
/************************************************************************************
* arch/arm/src/am335x/hardware/am335x_i2c.h
*
* Copyright (C) 2019 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_I2C_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_I2C_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_I2C_SYSC_OFFSET 0x0010
#define AM335X_I2C_IRQ_STAT_RAW_OFFSET 0x0024
#define AM335X_I2C_IRQ_STAT_OFFSET 0x0028
#define AM335X_I2C_IRQ_EN_SET_OFFSET 0x002c
#define AM335X_I2C_IRQ_EN_CLR_OFFSET 0x0030
#define AM335X_I2C_WE_OFFSET 0x0034
#define AM335X_I2C_DMA_RX_EN_SET_OFFSET 0x0038
#define AM335X_I2C_DMA_TX_EN_SET_OFFSET 0x003c
#define AM335X_I2C_DMA_RX_EN_CLR_OFFSET 0x0040
#define AM335X_I2C_DMA_TX_EN_CLR_OFFSET 0x0044
#define AM335X_I2C_DMA_RX_WAKE_EN_OFFSET 0x0048
#define AM335X_I2C_DMA_TX_WAKE_EN_OFFSET 0x004c
#define AM335X_I2C_SYSS_OFFSET 0x0090
#define AM335X_I2C_BUF_OFFSET 0x0094
#define AM335X_I2C_CNT_OFFSET 0x0098
#define AM335X_I2C_DATA_OFFSET 0x009c
#define AM335X_I2C_CON_OFFSET 0x00a4
#define AM335X_I2C_OA_OFFSET 0x00a8
#define AM335X_I2C_SA_OFFSET 0x00ac
#define AM335X_I2C_PSC_OFFSET 0x00b0
#define AM335X_I2C_SCLL_OFFSET 0x00b4
#define AM335X_I2C_SCLH_OFFSET 0x00b8
#define AM335X_I2C_SYSTEST_OFFSET 0x00bc
#define AM335X_I2C_BUFSTAT_OFFSET 0x00c0
#define AM335X_I2C_OA1_OFFSET 0x00c4
#define AM335X_I2C_OA2_OFFSET 0x00c8
#define AM335X_I2C_OA3_OFFSET 0x00cc
#define AM335X_I2C_ACTOA_OFFSET 0x00d0
#define AM335X_I2C_SBLOCK_OFFSET 0x00d4
/* Register virtual addresses *******************************************************/
#define AM335X_I2C0_SYSC (AM335X_I2C0_VADDR + AM335X_I2C_SYSC_OFFSET)
#define AM335X_I2C0_IRQ_STAT_RAW (AM335X_I2C0_VADDR + AM335X_I2C_IRQ_STAT_RAW_OFFSET)
#define AM335X_I2C0_IRQ_STAT (AM335X_I2C0_VADDR + AM335X_I2C_IRQ_STAT_OFFSET)
#define AM335X_I2C0_IRQ_EN_SET (AM335X_I2C0_VADDR + AM335X_I2C_IRQ_EN_SET_OFFSET)
#define AM335X_I2C0_IRQ_EN_CLR (AM335X_I2C0_VADDR + AM335X_I2C_IRQ_EN_CLR_OFFSET)
#define AM335X_I2C0_WE (AM335X_I2C0_VADDR + AM335X_I2C_WE_OFFSET)
#define AM335X_I2C0_DMA_RX_EN_SET (AM335X_I2C0_VADDR + AM335X_I2C_DMA_RX_EN_SET_OFFSET)
#define AM335X_I2C0_DMA_TX_EN_SET (AM335X_I2C0_VADDR + AM335X_I2C_DMA_TX_EN_SET_OFFSET)
#define AM335X_I2C0_DMA_RX_EN_CLR (AM335X_I2C0_VADDR + AM335X_I2C_DMA_RX_EN_CLR_OFFSET)
#define AM335X_I2C0_DMA_TX_EN_CLR (AM335X_I2C0_VADDR + AM335X_I2C_DMA_TX_EN_CLR_OFFSET)
#define AM335X_I2C0_DMA_RX_WAKE_EN (AM335X_I2C0_VADDR + AM335X_I2C_DMA_RX_WAKE_EN_OFFSET)
#define AM335X_I2C0_DMA_TX_WAKE_EN (AM335X_I2C0_VADDR + AM335X_I2C_DMA_TX_WAKE_EN_OFFSET)
#define AM335X_I2C0_SYSS (AM335X_I2C0_VADDR + AM335X_I2C_SYSS_OFFSET)
#define AM335X_I2C0_BUF (AM335X_I2C0_VADDR + AM335X_I2C_BUF_OFFSET)
#define AM335X_I2C0_CNT (AM335X_I2C0_VADDR + AM335X_I2C_CNT_OFFSET)
#define AM335X_I2C0_DATA (AM335X_I2C0_VADDR + AM335X_I2C_DATA_OFFSET)
#define AM335X_I2C0_CON (AM335X_I2C0_VADDR + AM335X_I2C_CON_OFFSET)
#define AM335X_I2C0_OA (AM335X_I2C0_VADDR + AM335X_I2C_OA_OFFSET)
#define AM335X_I2C0_SA (AM335X_I2C0_VADDR + AM335X_I2C_SA_OFFSET)
#define AM335X_I2C0_PSC (AM335X_I2C0_VADDR + AM335X_I2C_PSC_OFFSET)
#define AM335X_I2C0_SCLL (AM335X_I2C0_VADDR + AM335X_I2C_SCLL_OFFSET)
#define AM335X_I2C0_SCLH (AM335X_I2C0_VADDR + AM335X_I2C_SCLH_OFFSET)
#define AM335X_I2C0_SYSTEST (AM335X_I2C0_VADDR + AM335X_I2C_SYSTEST_OFFSET)
#define AM335X_I2C0_BUFSTAT (AM335X_I2C0_VADDR + AM335X_I2C_BUFSTAT_OFFSET)
#define AM335X_I2C0_OA1 (AM335X_I2C0_VADDR + AM335X_I2C_OA1_OFFSET)
#define AM335X_I2C0_OA2 (AM335X_I2C0_VADDR + AM335X_I2C_OA2_OFFSET)
#define AM335X_I2C0_OA3 (AM335X_I2C0_VADDR + AM335X_I2C_OA3_OFFSET)
#define AM335X_I2C0_ACTOA (AM335X_I2C0_VADDR + AM335X_I2C_ACTOA_OFFSET)
#define AM335X_I2C0_SBLOCK (AM335X_I2C0_VADDR + AM335X_I2C_SBLOCK_OFFSET)
#define AM335X_I2C1_SYSC (AM335X_I2C1_VADDR + AM335X_I2C_SYSC_OFFSET)
#define AM335X_I2C1_IRQ_STAT_RAW (AM335X_I2C1_VADDR + AM335X_I2C_IRQ_STAT_RAW_OFFSET)
#define AM335X_I2C1_IRQ_STAT (AM335X_I2C1_VADDR + AM335X_I2C_IRQ_STAT_OFFSET)
#define AM335X_I2C1_IRQ_EN_SET (AM335X_I2C1_VADDR + AM335X_I2C_IRQ_EN_SET_OFFSET)
#define AM335X_I2C1_IRQ_EN_CLR (AM335X_I2C1_VADDR + AM335X_I2C_IRQ_EN_CLR_OFFSET)
#define AM335X_I2C1_WE (AM335X_I2C1_VADDR + AM335X_I2C_WE_OFFSET)
#define AM335X_I2C1_DMA_RX_EN_SET (AM335X_I2C1_VADDR + AM335X_I2C_DMA_RX_EN_SET_OFFSET)
#define AM335X_I2C1_DMA_TX_EN_SET (AM335X_I2C1_VADDR + AM335X_I2C_DMA_TX_EN_SET_OFFSET)
#define AM335X_I2C1_DMA_RX_EN_CLR (AM335X_I2C1_VADDR + AM335X_I2C_DMA_RX_EN_CLR_OFFSET)
#define AM335X_I2C1_DMA_TX_EN_CLR (AM335X_I2C1_VADDR + AM335X_I2C_DMA_TX_EN_CLR_OFFSET)
#define AM335X_I2C1_DMA_RX_WAKE_EN (AM335X_I2C1_VADDR + AM335X_I2C_DMA_RX_WAKE_EN_OFFSET)
#define AM335X_I2C1_DMA_TX_WAKE_EN (AM335X_I2C1_VADDR + AM335X_I2C_DMA_TX_WAKE_EN_OFFSET)
#define AM335X_I2C1_SYSS (AM335X_I2C1_VADDR + AM335X_I2C_SYSS_OFFSET)
#define AM335X_I2C1_BUF (AM335X_I2C1_VADDR + AM335X_I2C_BUF_OFFSET)
#define AM335X_I2C1_CNT (AM335X_I2C1_VADDR + AM335X_I2C_CNT_OFFSET)
#define AM335X_I2C1_DATA (AM335X_I2C1_VADDR + AM335X_I2C_DATA_OFFSET)
#define AM335X_I2C1_CON (AM335X_I2C1_VADDR + AM335X_I2C_CON_OFFSET)
#define AM335X_I2C1_OA (AM335X_I2C1_VADDR + AM335X_I2C_OA_OFFSET)
#define AM335X_I2C1_SA (AM335X_I2C1_VADDR + AM335X_I2C_SA_OFFSET)
#define AM335X_I2C1_PSC (AM335X_I2C1_VADDR + AM335X_I2C_PSC_OFFSET)
#define AM335X_I2C1_SCLL (AM335X_I2C1_VADDR + AM335X_I2C_SCLL_OFFSET)
#define AM335X_I2C1_SCLH (AM335X_I2C1_VADDR + AM335X_I2C_SCLH_OFFSET)
#define AM335X_I2C1_SYSTEST (AM335X_I2C1_VADDR + AM335X_I2C_SYSTEST_OFFSET)
#define AM335X_I2C1_BUFSTAT (AM335X_I2C1_VADDR + AM335X_I2C_BUFSTAT_OFFSET)
#define AM335X_I2C1_OA1 (AM335X_I2C1_VADDR + AM335X_I2C_OA1_OFFSET)
#define AM335X_I2C1_OA2 (AM335X_I2C1_VADDR + AM335X_I2C_OA2_OFFSET)
#define AM335X_I2C1_OA3 (AM335X_I2C1_VADDR + AM335X_I2C_OA3_OFFSET)
#define AM335X_I2C1_ACTOA (AM335X_I2C1_VADDR + AM335X_I2C_ACTOA_OFFSET)
#define AM335X_I2C1_SBLOCK (AM335X_I2C1_VADDR + AM335X_I2C_SBLOCK_OFFSET)
#define AM335X_I2C2_SYSC (AM335X_I2C2_VADDR + AM335X_I2C_SYSC_OFFSET)
#define AM335X_I2C2_IRQ_STAT_RAW (AM335X_I2C2_VADDR + AM335X_I2C_IRQ_STAT_RAW_OFFSET)
#define AM335X_I2C2_IRQ_STAT (AM335X_I2C2_VADDR + AM335X_I2C_IRQ_STAT_OFFSET)
#define AM335X_I2C2_IRQ_EN_SET (AM335X_I2C2_VADDR + AM335X_I2C_IRQ_EN_SET_OFFSET)
#define AM335X_I2C2_IRQ_EN_CLR (AM335X_I2C2_VADDR + AM335X_I2C_IRQ_EN_CLR_OFFSET)
#define AM335X_I2C2_WE (AM335X_I2C2_VADDR + AM335X_I2C_WE_OFFSET)
#define AM335X_I2C2_DMA_RX_EN_SET (AM335X_I2C2_VADDR + AM335X_I2C_DMA_RX_EN_SET_OFFSET)
#define AM335X_I2C2_DMA_TX_EN_SET (AM335X_I2C2_VADDR + AM335X_I2C_DMA_TX_EN_SET_OFFSET)
#define AM335X_I2C2_DMA_RX_EN_CLR (AM335X_I2C2_VADDR + AM335X_I2C_DMA_RX_EN_CLR_OFFSET)
#define AM335X_I2C2_DMA_TX_EN_CLR (AM335X_I2C2_VADDR + AM335X_I2C_DMA_TX_EN_CLR_OFFSET)
#define AM335X_I2C2_DMA_RX_WAKE_EN (AM335X_I2C2_VADDR + AM335X_I2C_DMA_RX_WAKE_EN_OFFSET)
#define AM335X_I2C2_DMA_TX_WAKE_EN (AM335X_I2C2_VADDR + AM335X_I2C_DMA_TX_WAKE_EN_OFFSET)
#define AM335X_I2C2_SYSS (AM335X_I2C2_VADDR + AM335X_I2C_SYSS_OFFSET)
#define AM335X_I2C2_BUF (AM335X_I2C2_VADDR + AM335X_I2C_BUF_OFFSET)
#define AM335X_I2C2_CNT (AM335X_I2C2_VADDR + AM335X_I2C_CNT_OFFSET)
#define AM335X_I2C2_DATA (AM335X_I2C2_VADDR + AM335X_I2C_DATA_OFFSET)
#define AM335X_I2C2_CON (AM335X_I2C2_VADDR + AM335X_I2C_CON_OFFSET)
#define AM335X_I2C2_OA (AM335X_I2C2_VADDR + AM335X_I2C_OA_OFFSET)
#define AM335X_I2C2_SA (AM335X_I2C2_VADDR + AM335X_I2C_SA_OFFSET)
#define AM335X_I2C2_PSC (AM335X_I2C2_VADDR + AM335X_I2C_PSC_OFFSET)
#define AM335X_I2C2_SCLL (AM335X_I2C2_VADDR + AM335X_I2C_SCLL_OFFSET)
#define AM335X_I2C2_SCLH (AM335X_I2C2_VADDR + AM335X_I2C_SCLH_OFFSET)
#define AM335X_I2C2_SYSTEST (AM335X_I2C2_VADDR + AM335X_I2C_SYSTEST_OFFSET)
#define AM335X_I2C2_BUFSTAT (AM335X_I2C2_VADDR + AM335X_I2C_BUFSTAT_OFFSET)
#define AM335X_I2C2_OA1 (AM335X_I2C2_VADDR + AM335X_I2C_OA1_OFFSET)
#define AM335X_I2C2_OA2 (AM335X_I2C2_VADDR + AM335X_I2C_OA2_OFFSET)
#define AM335X_I2C2_OA3 (AM335X_I2C2_VADDR + AM335X_I2C_OA3_OFFSET)
#define AM335X_I2C2_ACTOA (AM335X_I2C2_VADDR + AM335X_I2C_ACTOA_OFFSET)
#define AM335X_I2C2_SBLOCK (AM335X_I2C2_VADDR + AM335X_I2C_SBLOCK_OFFSET)
/* Register bit field definitions ***************************************************/
#define I2C_SYSC_AUTOIDLE (1 << 0) /* Bit 0: Autoidle */
#define I2C_SYSC_SRST (1 << 1) /* Bit 1: SoftReset */
#define I2C_SYSC_WAKEUP (1 << 2) /* Bit 2: Enable Wakeup control */
#define I2C_SYSC_IDLE_SHIFT (3) /* Bits 3-4: Idle Mode selection */
#define I2C_SYSC_IDLE_MASK (3 << I2C_SYSC_IDLE_SHIFT)
# define I2C_SYSC_IDLE_FORCE (0 << I2C_SYSC_IDLE_SHIFT) /* Force-idle mode */
# define I2C_SYSC_IDLE_NO (1 << I2C_SYSC_IDLE_SHIFT) /* No-idle mode */
# define I2C_SYSC_IDLE_SMART (2 << I2C_SYSC_IDLE_SHIFT) /* Smart-idle mode */
# define I2C_SYSC_IDLE_SMART_WKUP (3 << I2C_SYSC_IDLE_SHIFT) /* Smart-idle Wakeup mode */
#define I2C_SYSC_CLK_SHIFT (8) /* Bits 8-9: Clock Activity selection */
#define I2C_SYSC_CLK_MASK (3 << I2C_SYSC_CLK_SHIFT)
# define I2C_SYSC_CLK_NONE (0 << I2C_SYSC_CLK_SHIFT) /* Both clocks can be cut off */
# define I2C_SYSC_CLK_OCP (1 << I2C_SYSC_CLK_SHIFT) /* Only Interface/OCP clock must be kept active */
# define I2C_SYSC_CLK_FUNC (2 << I2C_SYSC_CLK_SHIFT) /* Only functions clock must be kept active */
# define I2C_SYSC_CLK_BOTH (3 << I2C_SYSC_CLK_SHIFT) /* Both clocks must be kept active */
#define I2C_IRQ_AL (1 << 0) /* Bit 0: Arbitration lost */
#define I2C_IRQ_NACK (1 << 1) /* Bit 1: No acknowledgment */
#define I2C_IRQ_ARDY (1 << 2) /* Bit 2: Register access ready */
#define I2C_IRQ_RRDY (1 << 3) /* Bit 3: Receive data ready */
#define I2C_IRQ_XRDY (1 << 4) /* Bit 4: Transmit data ready */
#define I2C_IRQ_GC (1 << 5) /* Bit 5: General call */
#define I2C_IRQ_STC (1 << 6) /* Bit 6: Start Condition */
#define I2C_IRQ_AERR (1 << 7) /* Bit 7: Access Error */
#define I2C_IRQ_BF (1 << 8) /* Bit 8: Bus Free */
#define I2C_IRQ_AAS (1 << 9) /* Bit 9: Address recognized as slave */
#define I2C_IRQ_XUDF (1 << 10) /* Bit 10: Transmit underflow */
#define I2C_IRQ_ROVR (1 << 11) /* Bit 11: Receive overrun */
#define I2C_IRQ_BB (1 << 12) /* Bit 12: Bus busy */
#define I2C_IRQ_RDR (1 << 13) /* Bit 13: Receive draining IRQ */
#define I2C_IRQ_XDR (1 << 14) /* Bit 14: Transmit draining IRQ */
#define I2C_WE_AL (1 << 0) /* Bit 0: Arbitration lost */
#define I2C_WE_NACK (1 << 1) /* Bit 1: No acknowledgment */
#define I2C_WE_ARDY (1 << 2) /* Bit 2: Register access ready */
#define I2C_WE_DRDY (1 << 3) /* Bit 3: Receive/Transmit data ready */
#define I2C_WE_GC (1 << 5) /* Bit 5: General call */
#define I2C_WE_STC (1 << 6) /* Bit 6: Start Condition */
#define I2C_WE_BF (1 << 8) /* Bit 8: Bus Free */
#define I2C_WE_AAS (1 << 9) /* Bit 9: Address recognized as slave */
#define I2C_WE_XUDF (1 << 10) /* Bit 10: Transmit underflow */
#define I2C_WE_ROVR (1 << 11) /* Bit 11: Receive overrun */
#define I2C_WE_RDR (1 << 13) /* Bit 13: Receive draining IRQ */
#define I2C_WE_XDR (1 << 14) /* Bit 14: Transmit draining IRQ */
#define I2C_DMA_ENABLE (1 << 0) /* Bit 0: DMA channel enable */
#define I2C_SYSS_RST_DONE (1 << 0) /* Bit 0: Reset done */
#define I2C_BUF_TXTRSH_SHIFT (0) /* Bits 0-5: Threshold value for FIFO buffer in TX mode */
#define I2C_BUF_TXTRSH_MASK (63 << I2C_BUF_TXTRSH_SHIFT)
#define I2C_BUF_TXFIFO_CLR (1 << 6) /* Bit 6: Transmit FIFO clear */
#define I2C_BUF_XDMA_EN (1 << 7) /* Bit 7: Transmit DMA channel enable */
#define I2C_BUF_RXTRSH_SHIFT (8) /* Bits 8-13: Threshold value for FIFO buffer in RX mode */
#define I2C_BUF_RXTRSH_MASK (63 << I2C_BUF_RXTRSH_SHIFT)
#define I2C_BUF_RXFIFO_CLR (1 << 14) /* Bit 14: Receive FIFO clear */
#define I2C_BUF_RDMA_EN (1 << 15) /* Bit 15: Receive DMA channel enable */
#define I2C_CNT_SHIFT (0) /* Bits 0-15: Data count */
#define I2C_CNT_MASK (65535 << I2C_CNT_SHIFT)
#define I2C_DATA_SHIFT (0) /* Bits 0-7: Transmit/Receive data FIFO endpoint */
#define I2C_DATA_MASK (255 << I2C_DATA_SHIFT)
#define I2C_CON_STT (1 << 0) /* Bit 0: Start condition (I2C master mode only) */
#define I2C_CON_STP (1 << 1) /* Bit 1: Stop condition (I2C master mode only) */
#define I2C_CON_XOA3 (1 << 4) /* Bit 4: Expand own address 3 */
#define I2C_CON_XOA2 (1 << 5) /* Bit 5: Expand own address 2 */
#define I2C_CON_XOA1 (1 << 6) /* Bit 6: Expand own address 1 */
#define I2C_CON_XOA0 (1 << 7) /* Bit 7: Expand own address 0 */
#define I2C_CON_XSA (1 << 8) /* Bit 8: Expand slave address */
#define I2C_CON_TRX (1 << 9) /* Bit 9: Transmitter/receiver mode (I2C master mode only) */
#define I2C_CON_MST (1 << 10) /* Bit 10: Master/slave mode */
#define I2C_CON_STB (1 << 11) /* Bit 11: Start byte mode (I2C master mode only) */
#define I2C_CON_OPMODE_SHIFT (1 << 12) /* Bits 12-13: Operation mode selection */
#define I2C_CON_OPMODE_MASK (3 << I2C_CON_OPMODE_SHIFT)
# define I2C_CON_OPMODE_FAST (0 << I2C_CON_OPMODE_SHIFT)
#define I2C_CON_EN (1 << 15) /* Bit 15: I2C module enable */
#define I2C_SA_SHIFT (0) /* Bits 0-9: Slave address */
#define I2C_SA_MASK (0x3ff << I2C_SA_SHIFT)
#define I2C_PSC_SHIFT (0) /* Bits 0-7: Fast/Standard mode prescale sampling clock divider */
#define I2C_PSC_MASK (255 << I2C_PSC_SHIFT)
#define I2C_SCLL_SHIFT (0) /* Bits 0-7: Fast/Standard mode SCL low time */
#define I2C_SCLL_MASK (255 << I2C_SCLL_SHIFT)
#define I2C_SCLH_SHIFT (0) /* Bits 0-7: Fast/Standard mode SCL high time. */
#define I2C_SCLH_MASK (255 << I2C_SCLH_SHIFT)
#define I2C_SYSTEST_SDA_O (1 << 0) /* Bit 0: SDA line drive output value */
#define I2C_SYSTEST_SDA_I (1 << 1) /* Bit 1: SDA line sense input value */
#define I2C_SYSTEST_SCL_O (1 << 2) /* Bit 2: SCL line drive output value */
#define I2C_SYSTEST_SCL_I (1 << 3) /* Bit 3: SCL line sense input value */
#define I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* Bit 5: SDA line output value (functional mode) */
#define I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* Bit 6: SDA line input value (functional mode) */
#define I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* Bit 7: SCL line output value (functional mode) */
#define I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* Bit 8: SCL line input value (functional mode) */
#define I2C_SYSTEST_SSB (1 << 11) /* Bit 11: Set status bits */
#define I2C_SYSTEST_TMODE_SHIFT (12) /* Bits 12-13: Test mode select */
#define I2C_SYSTEST_TMODE_MASK (3 << I2C_SYSTEST_TMODE_SHIFT)
# define I2C_SYSTEST_TMODE_FUNC (0 << I2C_SYSTEST_TMODE_SHIFT) /* Functional mode */
# define I2C_SYSTEST_TMODE_SCL (2 << I2C_SYSTEST_TMODE_SHIFT) /* Test of SCL counters (SCLL, SCLH, PSC) */
# define I2C_SYSTEST_TMODE_LOOPBACK (3 << I2C_SYSTEST_TMODE_SHIFT) /* Loop back mode select + SDA/SCL IO mode select */
#define I2C_SYSTEST_FREE (1 << 14) /* Bit 14: Free running mode (on breakpoint) */
#define I2C_SYSTEST_ST_EN (1 << 15) /* Bit 15: System test enable */
#define I2C_BUFSTAT_TXSTAT_SHIFT (0) /* Bits 0-5: TX buffer status */
#define I2C_BUFSTAT_TXSTAT_MASK (63 << I2C_BUFSTAT_TXSTAT_SHIFT)
#define I2C_BUFSTAT_RXSTAT_SHIFT (8) /* Bits 8-13: RX buffer status */
#define I2C_BUFSTAT_RXSTAT_MASK (63 << I2C_BUFSTAT_RXSTAT_SHIFT)
#define I2C_BUFSTAT_FIFODEPTH_SHIFT (14) /* Bits 14-15: Internal FIFO buffers depth */
#define I2C_BUFSTAT_FIFODEPTH_MASK (3 << I2C_BUFSTAT_FIFODEPTH_SHIFT)
#define I2C_OA_SHIFT (0) /* Bits 0-9: Own address */
#define I2C_OA_MASK (0x3ff << I2C_OA_SHIFT)
#define I2C_OA0_SELECT (1 << 0) /* Bit 0: Own address 0 */
#define I2C_OA1_SELECT (1 << 1) /* Bit 1: Own address 1 */
#define I2C_OA2_SELECT (1 << 2) /* Bit 2: Own address 2 */
#define I2C_OA3_SELECT (1 << 3) /* Bit 3: Own address 3 */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_I2C_H */
arch/arm/src/am335x/hardware/am335x_lcd.h
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/************************************************************************************
* arch/arm/src/am335x/hardware/am335x_lcd.h
*
* Copyright (C) 2019 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_LCD_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_LCD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_LCD_PID_OFFSET 0x0000
#define AM335X_LCD_CTRL_OFFSET 0x0004
#define AM335X_LCD_LIDD_CTRL_OFFSET 0x000c
#define AM335X_LCD_LIDD_CS0_CONF_OFFSET 0x0010
#define AM335X_LCD_LIDD_CS0_ADDR_OFFSET 0x0014
#define AM335X_LCD_LIDD_CS0_DATA_OFFSET 0x0018
#define AM335X_LCD_LIDD_CS1_CONF_OFFSET 0x001c
#define AM335X_LCD_LIDD_CS1_ADDR_OFFSET 0x0020
#define AM335X_LCD_LIDD_CS1_DATA_OFFSET 0x0024
#define AM335X_LCD_RASTER_CTRL_OFFSET 0x0028
#define AM335X_LCD_RASTER_TIMING_0_OFFSET 0x002c
#define AM335X_LCD_RASTER_TIMING_1_OFFSET 0x0030
#define AM335X_LCD_RASTER_TIMING_2_OFFSET 0x0034
#define AM335X_LCD_RASTER_SUBPANEL_OFFSET 0x0038
#define AM335X_LCD_RASTER_SUBPANEL2_OFFSET 0x003c
#define AM335X_LCD_DMA_CTRL_OFFSET 0x0040
#define AM335X_LCD_DMA_FB0_BASE_OFFSET 0x0044
#define AM335X_LCD_DMA_FB0_CEIL_OFFSET 0x0048
#define AM335X_LCD_DMA_FB1_BASE_OFFSET 0x004c
#define AM335X_LCD_DMA_FB1_CEIL_OFFSET 0x0050
#define AM335X_LCD_SYSC_OFFSET 0x0054
#define AM335X_LCD_IRQ_STAT_RAW_OFFSET 0x0058
#define AM335X_LCD_IRQ_STAT_OFFSET 0x005c
#define AM335X_LCD_IRQ_EN_SET_OFFSET 0x0060
#define AM335X_LCD_IRQ_EN_CLEAR_OFFSET 0x0064
#define AM335X_LCD_END_INT_OFFSET 0x0068
#define AM335X_LCD_CLKC_ENABLE_OFFSET 0x006c
#define AM335X_LCD_CLKC_RESET_OFFSET 0x0070
#define AM335X_LCD_LIDD_CS_CONF_OFFSET(n) (0x0010 + (unsigned int)(n) * 0x0c)
#define AM335X_LCD_LIDD_CS_ADDR_OFFSET(n) (0x0014 + (unsigned int)(n) * 0x0c)
#define AM335X_LCD_LIDD_CS_DATA_OFFSET(n) (0x0018 + (unsigned int)(n) * 0x0c)
#define AM335X_LCD_DMA_FB_BASE_OFFSET(n) (0x0044 + (unsigned int)(n) * 0x08)
#define AM335X_LCD_DMA_FB_CEIL_OFFSET(n) (0x0048 + (unsigned int)(n) * 0x08)
/* Register virtual addresses *******************************************************/
#define AM335X_LCD_PID (AM335X_LCD_VADDR + AM335X_LCD_PID_OFFSET)
#define AM335X_LCD_CTRL (AM335X_LCD_VADDR + AM335X_LCD_CTRL_OFFSET)
#define AM335X_LCD_LIDD_CTRL (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CTRL_OFFSET)
#define AM335X_LCD_LIDD_CS0_CONF (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS0_CONF_OFFSET)
#define AM335X_LCD_LIDD_CS0_ADDR (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS0_ADDR_OFFSET)
#define AM335X_LCD_LIDD_CS0_DATA (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS0_DATA_OFFSET)
#define AM335X_LCD_LIDD_CS1_CONF (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS1_CONF_OFFSET)
#define AM335X_LCD_LIDD_CS1_ADDR (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS1_ADDR_OFFSET)
#define AM335X_LCD_LIDD_CS1_DATA (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS1_DATA_OFFSET)
#define AM335X_LCD_RASTER_CTRL (AM335X_LCD_VADDR + AM335X_LCD_RASTER_CTRL_OFFSET)
#define AM335X_LCD_RASTER_TIMING_0 (AM335X_LCD_VADDR + AM335X_LCD_RASTER_TIMING_0_OFFSET)
#define AM335X_LCD_RASTER_TIMING_1 (AM335X_LCD_VADDR + AM335X_LCD_RASTER_TIMING_1_OFFSET)
#define AM335X_LCD_RASTER_TIMING_2 (AM335X_LCD_VADDR + AM335X_LCD_RASTER_TIMING_2_OFFSET)
#define AM335X_LCD_RASTER_SUBPANEL (AM335X_LCD_VADDR + AM335X_LCD_RASTER_SUBPANEL_OFFSET)
#define AM335X_LCD_RASTER_SUBPANEL2 (AM335X_LCD_VADDR + AM335X_LCD_RASTER_SUBPANEL2_OFFSET)
#define AM335X_LCD_DMA_CTRL (AM335X_LCD_VADDR + AM335X_LCD_DMA_CTRL_OFFSET)
#define AM335X_LCD_DMA_FB0_BASE (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB0_BASE_OFFSET)
#define AM335X_LCD_DMA_FB0_CEIL (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB0_CEIL_OFFSET)
#define AM335X_LCD_DMA_FB1_BASE (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB1_BASE_OFFSET)
#define AM335X_LCD_DMA_FB1_CEIL (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB1_CEIL_OFFSET)
#define AM335X_LCD_SYSC (AM335X_LCD_VADDR + AM335X_LCD_SYSC_OFFSET)
#define AM335X_LCD_IRQ_STAT_RAW (AM335X_LCD_VADDR + AM335X_LCD_IRQ_STAT_RAW_OFFSET)
#define AM335X_LCD_IRQ_STAT (AM335X_LCD_VADDR + AM335X_LCD_IRQ_STAT_OFFSET)
#define AM335X_LCD_IRQ_EN_SET (AM335X_LCD_VADDR + AM335X_LCD_IRQ_EN_SET_OFFSET)
#define AM335X_LCD_IRQ_EN_CLEAR (AM335X_LCD_VADDR + AM335X_LCD_IRQ_EN_CLEAR_OFFSET)
#define AM335X_LCD_END_INT (AM335X_LCD_VADDR + AM335X_LCD_END_INT_OFFSET)
#define AM335X_LCD_CLKC_ENABLE (AM335X_LCD_VADDR + AM335X_LCD_CLKC_ENABLE_OFFSET)
#define AM335X_LCD_CLKC_RESET (AM335X_LCD_VADDR + AM335X_LCD_CLKC_RESET_OFFSET)
#define AM335X_LCD_LIDD_CS_CONF(n) (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS_CONF_OFFSET(n))
#define AM335X_LCD_LIDD_CS_ADDR(n) (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS_ADDR_OFFSET(n))
#define AM335X_LCD_LIDD_CS_DATA(n) (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS_DATA_OFFSET(n))
#define AM335X_LCD_DMA_FB_BASE(n) (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB_BASE_OFFSET(n))
#define AM335X_LCD_DMA_FB_CEIL(n) (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB_CEIL_OFFSET(n))
/* Register bit field definitions ***************************************************/
#define LCD_CTRL_MODE_SEL (1 << 0) /* Bit 0: LCD Mode select */
# define LCD_CTRL_MODE_LIDD (0)
# define LCD_CTRL_MODE_RASTER LCD_CTRL_MODE_SEL
#define LCD_CTRL_AUTO_UFLOW_RESTART (1 << 1) /* Bit 1: Underflow restart selection */
#define LCD_CTRL_CLKDIV_SHIFT (8) /* Bits 8-15: Clock divisor */
#define LCD_CTRL_CLKDIV_MASK (255 << LCD_CTRL_CLKDIV_SHIFT)
#define LCD_LIDD_CTRL_MODE_SEL_SHIFT (0) /* Bits 0-2: LIDD Mode Select */
#define LCD_LIDD_CTRL_MODE_SEL_MASK (7 << LCD_LIDD_CTRL_MODE_SEL_SHIFT)
# define LCD_LIDD_CTRL_SYNC_MPU68 (0 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Sync MPU68 */
# define LCD_LIDD_CTRL_ASYNC_MPU68 (1 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Async MPU68 */
# define LCD_LIDD_CTRL_SYNC_MPU80 (2 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Sync MPU80 */
# define LCD_LIDD_CTRL_ASYNC_MPU80 (3 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Async MPU80 */
# define LCD_LIDD_CTRL_HITACHI (4 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Hitachi (Async) */
#define LCD_LIDD_CTRL_ALEPOL (1 << 3) /* Bit 3: Address Latch Enable (ALE) Polarity Control */
#define LCD_LIDD_CTRL_RS_EN_POL (1 << 4) /* Bit 4: Read Strobe/Direction Polarity Control */
#define LCD_LIDD_CTRL_WS_DIR_POL (1 << 5) /* Bit 5: Write Strobe/Direction Polarity Control */
#define LCD_LIDD_CTRL_CS0_E0_POL (1 << 6) /* Bit 6: Chip Select 0/Enable 0 (Secondary) Polarity Control */
#define LCD_LIDD_CTRL_CS1_E1_POL (1 << 7) /* Bit 7: Chip Select 1/Enable 1 (Secondary) Polarity Control */
#define LCD_LIDD_CTRL_DMA_EN (1 << 8) /* Bit 8: LIDD DMA Enable */
#define LCD_LIDD_CTRL_DMA_CS0_CS1 (1 << 9) /* Bit 9: CS0/CS1 Select for LIDD DMA writes */
#define LCD_LIDD_CS_CONF_TA_SHIFT (0) /* Bits 0-1: Turn-around Access */
#define LCD_LIDD_CS_CONF_TA_MASK (3 << LCD_LIDD_CS0_CONF_TA_SHIFT)
#define LCD_LIDD_CS_CONF_R_HOLD_SHIFT (2) /* Bits 2-5: Read Strobe Hold cycles */
#define LCD_LIDD_CS_CONF_R_HOLD_MASK (15 << LCD_LIDD_CS0_CONF_R_HOLD_SHIFT)
#define LCD_LIDD_CS_CONF_R_STROBE_SHIFT (6) /* Bits 6-11: Read Strobe Duration cycles */
#define LCD_LIDD_CS_CONF_R_STROBE_MASK (63 << LCD_LIDD_CS0_CONF_R_STROBE_SHIFT)
#define LCD_LIDD_CS_CONF_R_SU_SHIFT (12) /* Bits 12-16: Read Strobe Set-Up cycles */
#define LCD_LIDD_CS_CONF_R_SU_MASK (31 << LCD_LIDD_CS0_CONF_R_SU_SHIFT)
#define LCD_LIDD_CS_CONF_W_HOLD_SHIFT (17) /* Bits 17-20: Write Strobe Hold cycles */
#define LCD_LIDD_CS_CONF_W_HOLD_MASK (15 << LCD_LIDD_CS0_CONF_W_HOLD_SHIFT)
#define LCD_LIDD_CS_CONF_W_STROBE_SHIFT (21) /* Bits 21-26: Write Strobe Duration cycles */
#define LCD_LIDD_CS_CONF_W_STROBE_MASK (63 << LCD_LIDD_CS0_CONF_W_STROBE_SHIFT)
#define LCD_LIDD_CS_CONF_W_SU_SHIFT (27) /* Bits 27-31: Write Strobe Set-Up cycles */
#define LCD_LIDD_CS_CONF_W_SU_MASK (31 << LCD_LIDD_CS0_CONF_W_SU_SHIFT)
#define LCD_LIDD_CS_ADDR_SHIFT (0) /* Bits 0-15: Address index */
#define LCD_LIDD_CS_ADDR_MASK (0xffff << LCD_LIDD_CS_ADDR_SHIFT)
#define LCD_LIDD_CS_DATA_SHIFT (0) /* Bits 0-15: Data */
#define LCD_LIDD_CS_DATA_MASK (0xffff << LCD_LIDD_CS_DATA_SHIFT)
#define LCD_RASTER_CTRL_LCD_EN (1 << 0) /* Bit 0: LCD Controller Enable */
#define LCD_RASTER_CTRL_LCD_BW (1 << 1) /* Bit 1: Only Applies for Passive Matrix Panels LCD Monochrome */
#define LCD_RASTER_CTRL_LCD_TFT (1 << 7) /* Bit 7: Active/Passive or display operation selection */
#define LCD_RASTER_CTRL_RD_ORDER (1 << 8) /* Bit 8: Raster Data Order Select */
#define LCD_RASTER_CTRL_MONO_8B (1 << 9) /* Bit 9: Mono 8 bit */
#define LCD_RASTER_CTRL_REQDLY_SHIFT (12) /* Bits 12-19: Palette Loading Delay When loading the Palette from DDR */
#define LCD_RASTER_CTRL_REQDLY_MASK (255 << LCD_RASTER_CTRL_REQDLY_SHIFT)
#define LCD_RASTER_CTRL_PALMODE_SHIFT (20) /* Bits 20-21: Palette Loading Mode */
#define LCD_RASTER_CTRL_PALMODE_MASK (3 << LCD_RASTER_CTRL_PALMODE_SHIFT)
# define LCD_RASTER_CTRL_PALETTE_DATA (0 << LCD_RASTER_CTRL_PALMODE_SHIFT) /* Palette and data loading */
# define LCD_RASTER_CTRL_PALETTE (1 << LCD_RASTER_CTRL_PALMODE_SHIFT) /* Palette loading only */
# define LCD_RASTER_CTRL_DATA (2 << LCD_RASTER_CTRL_PALMODE_SHIFT) /* Data loading only For Raw Data (12/16/24 bpp) framebuffers, no palette lookup is employed */
#define LCD_RASTER_CTRL_NIB_MODE (1 << 22) /* Bit 22: Nibble Mode */
#define LCD_RASTER_CTRL_TFT_MAP (1 << 23) /* Bit 23: TFT Mode Alternate Signal Mapping for Palettized framebuffer */
#define LCD_RASTER_CTRL_STN565 (1 << 24) /* Bit 24: Selects whether the framebuffer format is 16 bpp 565 or 12 bpp. */
#define LCD_RASTER_CTRL_TFT24 (1 << 25) /* Bit 25: 24 bit mode */
#define LCD_RASTER_CTRL_TFT24_UNPACKED (1 << 26) /* Bit 26: 24 bit Mode Packing */
#define LCD_RASTER_TIMING_0_PPLMSB (1 << 3) /* Bit 3: Pixels-per-line MSB[10] */
#define LCD_RASTER_TIMING_0_PPLLSB_SHIFT (4) /* Bits 4-9: Pixels-per-line LSB */
#define LCD_RASTER_TIMING_0_PPLLSB_MASK (63 << LCD_RASTER_TIMING_0_PPLLSB_SHIFT)
#define LCD_RASTER_TIMING_0_HSW_SHIFT (10) /* Bits 10-15: Horizontal Sync Pulse Width Lowbits*/
#define LCD_RASTER_TIMING_0_HSW_MASK (63 << LCD_RASTER_TIMING_0_HSW_SHIFT)
#define LCD_RASTER_TIMING_0_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch Lowbits */
#define LCD_RASTER_TIMING_0_HFP_MASK (255 << LCD_RASTER_TIMING_0_HFP_SHIFT)
#define LCD_RASTER_TIMING_0_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch Lowbits */
#define LCD_RASTER_TIMING_0_HBP_MASK (255 << LCD_RASTER_TIMING_0_HBP_SHIFT)
#define LCD_RASTER_TIMING_1_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel */
#define LCD_RASTER_TIMING_1_LPP_MASK (255 << LCD_RASTER_TIMING_1_LPP_SHIFT)
#define LCD_RASTER_TIMING_1_VSW_SHIFT (10) /* Bits 10-15: Vertical Sync Width Pulse */
#define LCD_RASTER_TIMING_1_VSW_MASK (255 << LCD_RASTER_TIMING_1_VSW_SHIFT)
#define LCD_RASTER_TIMING_1_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */
#define LCD_RASTER_TIMING_1_VFP_MASK (255 << LCD_RASTER_TIMING_1_VFP_SHIFT)
#define LCD_RASTER_TIMING_1_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */
#define LCD_RASTER_TIMING_1_VBP_MASK (255 << LCD_RASTER_TIMING_1_VBP_SHIFT)
#define LCD_RASTER_TIMING_2_HFP_HBITS_SHIFT (0) /* Bits 0-1: Bits 9:8 of the horizontal front porch field */
#define LCD_RASTER_TIMING_2_HFP_HBITS_MASK (3 << LCD_RASTER_TIMING_2_HFP_HBITS_SHIFT)
#define LCD_RASTER_TIMING_2_HBP_HBITS_SHIFT (4) /* Bits 4-5: Bits 9:8 of the horizontal back porch field */
#define LCD_RASTER_TIMING_2_HBP_HBITS_MASK (3 << LCD_RASTER_TIMING_2_HBP_HBITS_SHIFT)
#define LCD_RASTER_TIMING_2_ACB_SHIFT (8) /* Bits 8-15: AC Bias Pin Frequency */
#define LCD_RASTER_TIMING_2_ACB_MASK (255 << LCD_RASTER_TIMING_2_ACB_SHIFT)
#define LCD_RASTER_TIMING_2_ACBI_SHIFT (16) /* Bits 16-19: AC Bias Pins Transitions per Interrupt */
#define LCD_RASTER_TIMING_2_ACBI_MASK (15 << LCD_RASTER_TIMING_2_ACBI_SHIFT)
#define LCD_RASTER_TIMING_2_IVS (1 << 20) /* Bit 20: Invert Vsync */
#define LCD_RASTER_TIMING_2_IHS (1 << 21) /* Bit 21: Invert Hsync */
#define LCD_RASTER_TIMING_2_IPC (1 << 22) /* Bit 22: Invert Pixel Clock */
#define LCD_RASTER_TIMING_2_IEO (1 << 23) /* Bit 23: Invert Output Enable */
#define LCD_RASTER_TIMING_2_PHSVS_RF (1 << 24) /* Bit 24: Program HSYNC/VSYNC Rise or Fall */
#define LCD_RASTER_TIMING_2_PHSVS_ON (1 << 25) /* Bit 25: Hsync/Vsync Pixel Clock Control On/Off */
#define LCD_RASTER_TIMING_2_LPP_B10_SHIFT (26) /* Bit 26: Lines Per Panel Bit 10 */
#define LCD_RASTER_TIMING_2_LPP_B10_MASK (1 << LCD_RASTER_TIMING_2_LPP_B10_SHIFT)
#define LCD_RASTER_TIMING_2_HSW_HBITS_SHIFT (27) /* Bits 27-30: Bits 9 to 6 of the horizontal sync width field */
#define LCD_RASTER_TIMING_2_HSW_HBITS_MASK (15 << LCD_RASTER_TIMING_2_HSW_HBITS_SHITF)
#define LCD_RASTER_SUBPANEL_DPDLSB_SHIFT (0) /* Bits 0-15: Default Pixel Data LSB */
#define LCD_RASTER_SUBPANEL_DPDLSB_MASK (65535 << LCD_RASTER_SUBPANEL_DPDLSB_SHIFT)
#define LCD_RASTER_SUBPANEL_LPPT_SHIFT (16) /* Bits 16-25: Line Per Panel Threshold */
#define LCD_RASTER_SUBPANEL_LPPT_MASK (1023 << LCD_RASTER_SUBPANEL_LPPT_SHIFT)
#define LCD_RASTER_SUBPANEL_HOLS (1 << 29) /* Bit 29: High or Low Signal */
#define LCD_RASTER_SUBPANEL_SPEN (1 << 31) /* Bit 31: Sub Panel Enable */
#define LCD_RASTER_SUBPANEL2_DPDMSB_SHIFT (0) /* Bits 0-7: Default Pixel Data MSB */
#define LCD_RASTER_SUBPANEL2_DPDMSB_MASK (255 << LCD_RASTER_SUBPANEL2_DPDMSB_SHIFT)
#define LCD_RASTER_SUBPANEL2_LPPT_B10 (1 << 8) /* Bit 8: Lines Per Panel Threshold Bit 10 */
#define LCD_DMA_CTRL_FRAME_MODE (1 << 0) /* Bit 0: Frame Mode */
#define LCD_DMA_CTRL_BE (1 << 1) /* Bit 1: Big Endian Enable */
#define LCD_DMA_CTRL_BYTE_SWAP (1 << 3) /* Bit 3: Bytelane Ordering */
#define LCD_DMA_CTRL_BURST_SIZE_SHIFT (4) /* Bits 4-6: Burst Size setting for DMA transfers */
#define LCD_DMA_CTRL_BURST_SIZE_MASK (7 << LCD_DMA_CTRL_BURST_SIZE_SHIFT)
# define LCD_DMA_CTRL_BURST_SIZE_1 (0 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 1 */
# define LCD_DMA_CTRL_BURST_SIZE_2 (1 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 2 */
# define LCD_DMA_CTRL_BURST_SIZE_4 (2 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 4 */
# define LCD_DMA_CTRL_BURST_SIZE_8 (3 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 8 */
# define LCD_DMA_CTRL_BURST_SIZE_16 (4 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 6 */
#define LCD_DMA_CTRL_TH_FIFO_RDY_SHIFT (8) /* Bits 8-10: DMA FIFO threshold */
#define LCD_DMA_CTRL_TH_FIFO_RDY_MASK (7 << LCD_DMA_CTRL_TH_FIFO_RDY_SHIFT)
# define LCD_DMA_CTRL_TH_FIFO_RDY_8 (0 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 8 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_16 (1 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 16 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_32 (2 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 32 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_64 (3 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 64 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_128 (4 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 128 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_256 (5 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 256 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_512 (6 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 512 words have been loaded */
#define LCD_DMA_CTRL_MASTER_PRIO_SHIFT (16) /* Bits 16-18: Priority for the L3 OCP Master Bus */
#define LCD_DMA_CTRL_MASTER_PRIO_MASK (7 << LCD_DMA_CTRL_MASTER_PRIO_SHIFT)
#define LCD_DMA_FB_BASE_SHIFT (2) /* Bits 2-31: Frame Buffer Base Address pointer */
#define LCD_DMA_FB_BASE_MASK (0x3fffffff << LCD_DMA_FB_BASE_SHIFT)
#define LCD_DMA_FB_CEIL_SHIFT (2) /* Bits 2-31: Frame Buffer Ceiling Address pointer */
#define LCD_DMA_FB_CEIL_MASK (0x3fffffff << LCD_DMA_FB_BASE_SHIFT)
#define LCD_SYSC_IDLE_SHIFT (2) /* Bits 2-3: Configuration of the local target state management mode */
#define LCD_SYSC_IDLE_MASK (3 << LCD_SYSC_IDLE_SHIFT)
# define LCD_SYSC_IDLE_FORCE (0 << LCD_SYSC_IDLE_SHIFT) /* Force-idle mode */
# define LCD_SYSC_IDLE_NO (1 << LCD_SYSC_IDLE_SHIFT) /* No-idle mode */
# define LCD_SYSC_IDLE_SMART (2 << LCD_SYSC_IDLE_SHIFT) /* Smart-idle mode */
#define LCD_SYSC_STANDBY_SHIFT (4) /* Bits 4-5: Configuration of the local initiator state management mode */
#define LCD_SYSC_STANDBY_MASK (3 << LCD_SYSC_STANDBY_SHIFT)
# define LCD_SYSC_STANDBY_FORCE (0 << LCD_SYSC_STANDBY_SHIFT) /* Force-standby mode */
# define LCD_SYSC_STANDBY_NO (1 << LCD_SYSC_STANDBY_SHIFT) /* No-standby mode */
# define LCD_SYSC_STANDBY_SMART (2 << LCD_SYSC_STANDBY_SHIFT) /* Smart-standby mode */
#define LCD_IRQ_DONE (1 << 0) /* Bit 0: Raster or LIDD Frame Done */
#define LCD_IRQ_RR_DONE (1 << 1) /* Bit 1: Raster Mode Frame Done */
#define LCD_IRQ_SYNC (1 << 2) /* Bit 2: Frame Synchronization Lost */
#define LCD_IRQ_ACB (1 << 3) /* Bit 3: For Passive Matrix Panels Only AC Bias Count */
#define LCD_IRQ_FUF (1 << 5) /* Bit 5: DMA FIFO Underflow */
#define LCD_IRQ_PL (1 << 6) /* Bit 6: DMA Palette Loaded */
#define LCD_IRQ_EOF0 (1 << 8) /* Bit 8: DMA End-of-Frame 0 */
#define LCD_IRQ_EOF1 (1 << 9) /* Bit 9: DMA End-of-Frame 1 */
#define LCD_CLKC_ENABLE_CORE (1 << 0) /* Bit 0: Software Clock Enable for the DMA submodule */
#define LCD_CLKC_ENABLE_LIDD (1 << 1) /* Bit 1: Software Clock Enable for the LIDD submodule */
#define LCD_CLKC_ENABLE_DMA (1 << 2) /* Bit 2: Software Clock Enable for the Core */
#define LCD_CLKC_RESET_CORE (1 << 0) /* Bit 0: Software Reset for the Core */
#define LCD_CLKC_RESET_LIDD (1 << 1) /* Bit 1: Software Reset for the LIDD submodule */
#define LCD_CLKC_RESET_DMA (1 << 2) /* Bit 2: Software Reset for the DMA submodule */
#define LCD_CLKC_RESET_MAIN (1 << 3) /* Bit 3: Software Reset for the entire LCD module */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_LCD_H */
arch/arm/src/am335x/hardware/am335x_mcspi.h
+322
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/************************************************************************************
* arch/arm/src/am335x/hardware/am335x_mcspi.h
*
* Copyright (C) 2019 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_MCSPI_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_MCSPI_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_MCSPI_SYSC_OFFSET 0x0110
#define AM335X_MCSPI_SYSS_OFFSET 0x0114
#define AM335X_MCSPI_IRQ_STAT_OFFSET 0x0118
#define AM335X_MCSPI_IRQ_EN_OFFSET 0x011c
#define AM335X_MCSPI_SYST_OFFSET 0x0124
#define AM335X_MCSPI_MODUL_CTRL_OFFSET 0x0128
#define AM335X_MCSPI_CH0_CONF_OFFSET 0x012c
#define AM335X_MCSPI_CH0_STAT_OFFSET 0x0130
#define AM335X_MCSPI_CH0_CTRL_OFFSET 0x0134
#define AM335X_MCSPI_TX0_OFFSET 0x0138
#define AM335X_MCSPI_RX0_OFFSET 0x013c
#define AM335X_MCSPI_CH1_CONF_OFFSET 0x0140
#define AM335X_MCSPI_CH1_STAT_OFFSET 0x0144
#define AM335X_MCSPI_CH1_CTRL_OFFSET 0x0148
#define AM335X_MCSPI_TX1_OFFSET 0x014c
#define AM335X_MCSPI_RX1_OFFSET 0x0150
#define AM335X_MCSPI_CH2_CONF_OFFSET 0x0154
#define AM335X_MCSPI_CH2_STAT_OFFSET 0x0158
#define AM335X_MCSPI_CH2_CTRL_OFFSET 0x015c
#define AM335X_MCSPI_TX2_OFFSET 0x0160
#define AM335X_MCSPI_RX2_OFFSET 0x0164
#define AM335X_MCSPI_CH3_CONF_OFFSET 0x0168
#define AM335X_MCSPI_CH3_STAT_OFFSET 0x016c
#define AM335X_MCSPI_CH3_CTRL_OFFSET 0x0170
#define AM335X_MCSPI_TX3_OFFSET 0x0174
#define AM335X_MCSPI_RX3_OFFSET 0x0178
#define AM335X_MCSPI_XFER_LEVEL_OFFSET 0x017c
#define AM335X_MCSPI_DAFTX_OFFSET 0x0180
#define AM335X_MCSPI_DAFRX_OFFSET 0x01a0
#define AM335X_MCSPI_CH_CONF_OFFSET(n) (0x012c + (unsigned int)(n) * 0x14)
#define AM335X_MCSPI_CH_STAT_OFFSET(n) (0x0130 + (unsigned int)(n) * 0x14)
#define AM335X_MCSPI_CH_CTRL_OFFSET(n) (0x0134 + (unsigned int)(n) * 0x14)
#define AM335X_MCSPI_TX_OFFSET(n) (0x0138 + (unsigned int)(n) * 0x14)
#define AM335X_MCSPI_RX_OFFSET(n) (0x013c + (unsigned int)(n) * 0x14)
/* Register virtual addresses *******************************************************/
#define AM335X_MCSPI0_SYSC (AM335X_MCSPI0_VADDR + AM335X_MCSPI_SYSC_OFFSET)
#define AM335X_MCSPI0_SYSS (AM335X_MCSPI0_VADDR + AM335X_MCSPI_SYSS_OFFSET)
#define AM335X_MCSPI0_IRQ_STAT (AM335X_MCSPI0_VADDR + AM335X_MCSPI_IRQ_STAT_OFFSET)
#define AM335X_MCSPI0_IRQ_EN (AM335X_MCSPI0_VADDR + AM335X_MCSPI_IRQ_EN_OFFSET)
#define AM335X_MCSPI0_SYST (AM335X_MCSPI0_VADDR + AM335X_MCSPI_SYST_OFFSET)
#define AM335X_MCSPI0_MODUL_CTRL (AM335X_MCSPI0_VADDR + AM335X_MCSPI_MODUL_CTRL_OFFSET)
#define AM335X_MCSPI0_CH0_CONF (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH0_CONF_OFFSET)
#define AM335X_MCSPI0_CH0_STAT (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH0_STAT_OFFSET)
#define AM335X_MCSPI0_CH0_CTRL (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH0_CTRL_OFFSET)
#define AM335X_MCSPI0_TX0 (AM335X_MCSPI0_VADDR + AM335X_MCSPI_TX0_OFFSET)
#define AM335X_MCSPI0_RX0 (AM335X_MCSPI0_VADDR + AM335X_MCSPI_RX0_OFFSET)
#define AM335X_MCSPI0_CH1_CONF (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH1_CONF_OFFSET)
#define AM335X_MCSPI0_CH1_STAT (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH1_STAT_OFFSET)
#define AM335X_MCSPI0_CH1_CTRL (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH1_CTRL_OFFSET)
#define AM335X_MCSPI0_TX1 (AM335X_MCSPI0_VADDR + AM335X_MCSPI_TX1_OFFSET)
#define AM335X_MCSPI0_RX1 (AM335X_MCSPI0_VADDR + AM335X_MCSPI_RX1_OFFSET)
#define AM335X_MCSPI0_CH2_CONF (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH2_CONF_OFFSET)
#define AM335X_MCSPI0_CH2_STAT (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH2_STAT_OFFSET)
#define AM335X_MCSPI0_CH2_CTRL (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH2_CTRL_OFFSET)
#define AM335X_MCSPI0_TX2 (AM335X_MCSPI0_VADDR + AM335X_MCSPI_TX2_OFFSET)
#define AM335X_MCSPI0_RX2 (AM335X_MCSPI0_VADDR + AM335X_MCSPI_RX2_OFFSET)
#define AM335X_MCSPI0_CH3_CONF (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH3_CONF_OFFSET)
#define AM335X_MCSPI0_CH3_STAT (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH3_STAT_OFFSET)
#define AM335X_MCSPI0_CH3_CTRL (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH3_CTRL_OFFSET)
#define AM335X_MCSPI0_TX3 (AM335X_MCSPI0_VADDR + AM335X_MCSPI_TX3_OFFSET)
#define AM335X_MCSPI0_RX3 (AM335X_MCSPI0_VADDR + AM335X_MCSPI_RX3_OFFSET)
#define AM335X_MCSPI0_XFER_LEVEL (AM335X_MCSPI0_VADDR + AM335X_MCSPI_XFER_LEVEL_OFFSET)
#define AM335X_MCSPI0_DAFTX (AM335X_MCSPI0_VADDR + AM335X_MCSPI_DAFTX_OFFSET)
#define AM335X_MCSPI0_DAFRX (AM335X_MCSPI0_VADDR + AM335X_MCSPI_DAFRX_OFFSET)
#define AM335X_MCSPI0_CH_CONF(n) (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH_CONF_OFFSET(n))
#define AM335X_MCSPI0_CH_STAT(n) (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH_STAT_OFFSET(n))
#define AM335X_MCSPI0_CH_CTRL(n) (AM335X_MCSPI0_VADDR + AM335X_MCSPI_CH_CTRL_OFFSET(n))
#define AM335X_MCSPI0_TX(n) (AM335X_MCSPI0_VADDR + AM335X_MCSPI_TX_OFFSET(n))
#define AM335X_MCSPI0_RX(n) (AM335X_MCSPI0_VADDR + AM335X_MCSPI_RX_OFFSET(n))
#define AM335X_MCSPI1_SYSC (AM335X_MCSPI1_VADDR + AM335X_MCSPI_SYSC_OFFSET)
#define AM335X_MCSPI1_SYSS (AM335X_MCSPI1_VADDR + AM335X_MCSPI_SYSS_OFFSET)
#define AM335X_MCSPI1_IRQ_STAT (AM335X_MCSPI1_VADDR + AM335X_MCSPI_IRQ_STAT_OFFSET)
#define AM335X_MCSPI1_IRQ_EN (AM335X_MCSPI1_VADDR + AM335X_MCSPI_IRQ_EN_OFFSET)
#define AM335X_MCSPI1_SYST (AM335X_MCSPI1_VADDR + AM335X_MCSPI_SYST_OFFSET)
#define AM335X_MCSPI1_MODUL_CTRL (AM335X_MCSPI1_VADDR + AM335X_MCSPI_MODUL_CTRL_OFFSET)
#define AM335X_MCSPI1_CH0_CONF (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH0_CONF_OFFSET)
#define AM335X_MCSPI1_CH0_STAT (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH0_STAT_OFFSET)
#define AM335X_MCSPI1_CH0_CTRL (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH0_CTRL_OFFSET)
#define AM335X_MCSPI1_TX0 (AM335X_MCSPI1_VADDR + AM335X_MCSPI_TX0_OFFSET)
#define AM335X_MCSPI1_RX0 (AM335X_MCSPI1_VADDR + AM335X_MCSPI_RX0_OFFSET)
#define AM335X_MCSPI1_CH1_CONF (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH1_CONF_OFFSET)
#define AM335X_MCSPI1_CH1_STAT (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH1_STAT_OFFSET)
#define AM335X_MCSPI1_CH1_CTRL (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH1_CTRL_OFFSET)
#define AM335X_MCSPI1_TX1 (AM335X_MCSPI1_VADDR + AM335X_MCSPI_TX1_OFFSET)
#define AM335X_MCSPI1_RX1 (AM335X_MCSPI1_VADDR + AM335X_MCSPI_RX1_OFFSET)
#define AM335X_MCSPI1_CH2_CONF (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH2_CONF_OFFSET)
#define AM335X_MCSPI1_CH2_STAT (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH2_STAT_OFFSET)
#define AM335X_MCSPI1_CH2_CTRL (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH2_CTRL_OFFSET)
#define AM335X_MCSPI1_TX2 (AM335X_MCSPI1_VADDR + AM335X_MCSPI_TX2_OFFSET)
#define AM335X_MCSPI1_RX2 (AM335X_MCSPI1_VADDR + AM335X_MCSPI_RX2_OFFSET)
#define AM335X_MCSPI1_CH3_CONF (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH3_CONF_OFFSET)
#define AM335X_MCSPI1_CH3_STAT (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH3_STAT_OFFSET)
#define AM335X_MCSPI1_CH3_CTRL (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH3_CTRL_OFFSET)
#define AM335X_MCSPI1_TX3 (AM335X_MCSPI1_VADDR + AM335X_MCSPI_TX3_OFFSET)
#define AM335X_MCSPI1_RX3 (AM335X_MCSPI1_VADDR + AM335X_MCSPI_RX3_OFFSET)
#define AM335X_MCSPI1_XFER_LEVEL (AM335X_MCSPI1_VADDR + AM335X_MCSPI_XFER_LEVEL_OFFSET)
#define AM335X_MCSPI1_DAFTX (AM335X_MCSPI1_VADDR + AM335X_MCSPI_DAFTX_OFFSET)
#define AM335X_MCSPI1_DAFRX (AM335X_MCSPI1_VADDR + AM335X_MCSPI_DAFRX_OFFSET)
#define AM335X_MCSPI1_CH_CONF(n) (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH_CONF_OFFSET(n))
#define AM335X_MCSPI1_CH_STAT(n) (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH_STAT_OFFSET(n))
#define AM335X_MCSPI1_CH_CTRL(n) (AM335X_MCSPI1_VADDR + AM335X_MCSPI_CH_CTRL_OFFSET(n))
#define AM335X_MCSPI1_TX(n) (AM335X_MCSPI1_VADDR + AM335X_MCSPI_TX_OFFSET(n))
#define AM335X_MCSPI1_RX(n) (AM335X_MCSPI1_VADDR + AM335X_MCSPI_RX_OFFSET(n))
/* Register bit field definitions ***************************************************/
#define MCSPI_SYSC_AUTOIDLE (1 << 0) /* Bit 0: Internal OCP Clock gating strategy */
#define MCSPI_SYSC_SRST (1 << 1) /* Bit 1: Software reset */
#define MCSPI_SYSC_IDLE_SHIFT (3) /* Bits 3-4: Power management */
#define MCSPI_SYSC_IDLE_MASK (3 << MCSPI_SYSC_IDLE_MASK)
# define MCSPI_SYSC_IDLE_FORCE (0 << MCSPI_SYSC_IDLE_SHIFT) /* Force-idle mode */
# define MCSPI_SYSC_IDLE_NO (1 << MCSPI_SYSC_IDLE_SHIFT) /* No-idle mode */
# define MCSPI_SYSC_IDLE_SMART (2 << MCSPI_SYSC_IDLE_SHIFT) /* Smart-idle mode */
#define MCSPI_SYSC_CLK_SHIFT (8) /* Bits 8-9: Clocks activity during wake-up mode period */
#define MCSPI_SYSC_CLK_MASK (3 << MCSPI_SYSC_CLK_SHIFT)
# define MCSPI_SYSC_CLK_NONE (0 << MCSPI_SYSC_CLK_SHIFT) /* Both clocks may be switched off */
# define MCSPI_SYSC_CLK_OCP (1 << MCSPI_SYSC_CLK_SHIFT) /* Only OCP clock is maintained */
# define MCSPI_SYSC_CLK_FUNC (2 << MCSPI_SYSC_CLK_SHIFT) /* Only functions clock is maintained */
# define MCSPI_SYSC_CLK_BOTH (3 << MCSPI_SYSC_CLK_SHIFT) /* Both clocks are maintained */
#define MCSPI_SYSS_RST_DONE (1 << 0) /* Bit 0: Reset done */
#define MCSPI_IRQ_TX0_EMPTY (0) /* Bit 0: Channel 0 transmitter register empty or almost empty */
#define MCSPI_IRQ_TX0_UFLOW (1) /* Bit 1: Channel 0 transmitter register underflow */
#define MCSPI_IRQ_RX0_FULL (2) /* Bit 2: Channel 0 receiver register full or almost full */
#define MCSPI_IRQ_RX0_OFLOW (3) /* Bit 3: Channel 0 receiver register overflow (slave mode only). */
#define MCSPI_IRQ_TX1_EMPTY (4) /* Bit 4: Channel 1 transmitter register empty or almost empty */
#define MCSPI_IRQ_TX1_UFLOW (5) /* Bit 5: Channel 1 transmitter register underflow */
#define MCSPI_IRQ_RX1_FULL (6) /* Bit 6: Channel 1 receiver register full or almost full */
#define MCSPI_IRQ_TX2_EMPTY (8) /* Bit 8: Channel 2 transmitter register empty or almost empty */
#define MCSPI_IRQ_TX2_UFLOW (9) /* Bit 9: Channel 2 transmitter register underflow */
#define MCSPI_IRQ_RX2_FULL (10) /* Bit 10: Channel 2 receiver register full or almost full */
#define MCSPI_IRQ_TX3_EMPTY (12) /* Bit 12: Channel 3 transmitter register empty or almost empty */
#define MCSPI_IRQ_TX3_UFLOW (13) /* Bit 13: Channel 3 transmitter register underflow */
#define MCSPI_IRQ_RX3_FULL (14) /* Bit 14: Channel 3 receiver register full or almost full */
#define MCSPI_IRQ_EOW (17) /* Bit 17: End of word (EOW) count event */
#define MCSPI_SYST_SPIEN0 (1 << 0) /* Bit 0: SPIEN[0] line (signal data value) */
#define MCSPI_SYST_SPIEN1 (1 << 1) /* Bit 1: SPIEN[1] line (signal data value) */
#define MCSPI_SYST_SPIEN2 (1 << 2) /* Bit 2: SPIEN[2] line (signal data value) */
#define MCSPI_SYST_SPIEN3 (1 << 3) /* Bit 3: SPIEN[3] line (signal data value) */
#define MCSPI_SYST_SPIDAT0 (1 << 4) /* Bit 4: SPIDAT[0] line (signal data value) */
#define MCSPI_SYST_SPIDAT1 (1 << 5) /* Bit 5: SPIDAT[1] line (signal data value) */
#define MCSPI_SYST_SPICLK (1 << 6) /* Bit 6: SPICLK line (signal data value) */
#define MCSPI_SYST_SPIDAT_DIR0 (1 << 8) /* Bit 8: Sets the direction of the SPIDAT[0] */
#define MCSPI_SYST_SPIDAT_DIR1 (1 << 9) /* Bit 9: Sets the direction of the SPIDAT[1] */
#define MCSPI_SYST_SPIEN_DIR (1 << 10) /* Bit 10: Sets the direction of the SPIEN */
#define MCSPI_SYST_SSB (1 << 11) /* Bit 11: Set status bit */
#define MCSPI_MODUL_CTRL_SINGLE (1 << 0) /* Bit 0: Single Channel / Multi Channel selection */
#define MCSPI_MODUL_CTRL_PIN34 (1 << 1) /* Bit 1: Pin mode selection */
#define MCSPI_MODUL_CTRL_MS (1 << 2) /* Bit 2: Master / Slave selection */
#define MCSPI_MODUL_CTRL_SYS_TEST (1 << 3) /* Bit 3: Enables the system test mode */
#define MCSPI_MODUL_CTRL_IDLY_SHIFT (4) /* Bits 4-6: Initial SPI delay for first transfer */
#define MCSPI_MODUL_CTRL_IDLY_MASK (15 << MCSPI_MODUL_CTRL_INIT_DLY_SHIFT)
# define MCSPI_MODUL_CTRL_IDLY_NONE (0 << MCSPI_MODUL_CTRL_INIT_DLY_SHIFT) /* No delay for first SPI transfer */
# define MCSPI_MODUL_CTRL_IDLY_4CLK (1 << MCSPI_MODUL_CTRL_INIT_DLY_SHIFT) /* The controller wait 4 SPI bus clock */
# define MCSPI_MODUL_CTRL_IDLY_8CLK (2 << MCSPI_MODUL_CTRL_INIT_DLY_SHIFT) /* The controller wait 8 SPI bus clock */
# define MCSPI_MODUL_CTRL_IDLY_16CLK (3 << MCSPI_MODUL_CTRL_INIT_DLY_SHIFT) /* The controller wait 16 SPI bus clock */
# define MCSPI_MODUL_CTRL_IDLY_32CLK (4 << MCSPI_MODUL_CTRL_INIT_DLY_SHIFT) /*The controller wait 32 SPI bus clock */
#define MCSPI_MODUL_CTRL_MOA (1 << 7) /* Bit 7: Multiple word OCP access */
#define MCSPI_MODUL_CTRL_FDAA (1 << 8) /* Bit 8: FIFO DMA Address 256 bit aligned */
#define MCSPI_CH_CONF_PHA (1 << 0) /* Bit 0: SPICLK phase */
#define MCSPI_CH_CONF_POL (1 << 1) /* Bit 1: SPICLK polarity */
#define MCSPI_CH_CONF_CLKD_SHIFT (2) /* Bits 2-5: Frequency divider for SPICLK */
#define MCSPI_CH_CONF_CLKD_MASK (15 << MCSPI_CH_CONF_CLKD_SHIFT)
# define MCSPI_CH_CONF_CLKD_DIV1 (0 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 1 */
# define MCSPI_CH_CONF_CLKD_DIV2 (1 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 2 */
# define MCSPI_CH_CONF_CLKD_DIV4 (2 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 4 */
# define MCSPI_CH_CONF_CLKD_DIV8 (3 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 8 */
# define MCSPI_CH_CONF_CLKD_DIV16 (4 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 16 */
# define MCSPI_CH_CONF_CLKD_DIV32 (5 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 32 */
# define MCSPI_CH_CONF_CLKD_DIV64 (6 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 64 */
# define MCSPI_CH_CONF_CLKD_DIV128 (7 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 128 */
# define MCSPI_CH_CONF_CLKD_DIV256 (8 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 256 */
# define MCSPI_CH_CONF_CLKD_DIV512 (9 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 512 */
# define MCSPI_CH_CONF_CLKD_DIV1K (10 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 1024 */
# define MCSPI_CH_CONF_CLKD_DIV2K (11 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 2048 */
# define MCSPI_CH_CONF_CLKD_DIV4K (12 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 4096 */
# define MCSPI_CH_CONF_CLKD_DIV8K (13 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 8192 */
# define MCSPI_CH_CONF_CLKD_DIV16K (14 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 16384 */
# define MCSPI_CH_CONF_CLKD_DIV32K (15 << MCSPI_CH_CONF_CLKD_SHIFT) /* Divide by 32768 */
#define MCSPI_CH_CONF_EPOL (1 << 6) /* Bit 6: SPIEN polarity */
#define MCSPI_CH_CONF_WL_SHIFT (7) /* Bits 7-11: SPI word length */
#define MCSPI_CH_CONF_WL_MASK (31 << MCSPI_CH_CONF_WL_SHIFT)
# define MCSPI_CH_CONF_WL_4BITS (3 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 4-bits long */
# define MCSPI_CH_CONF_WL_5BITS (4 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 5-bits long */
# define MCSPI_CH_CONF_WL_6BITS (5 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 6-bits long */
# define MCSPI_CH_CONF_WL_7BITS (6 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 7-bits long */
# define MCSPI_CH_CONF_WL_8BITS (7 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 8-bits long */
# define MCSPI_CH_CONF_WL_9BITS (8 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 9-bits long */
# define MCSPI_CH_CONF_WL_10BITS (9 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 10-bits long */
# define MCSPI_CH_CONF_WL_11BITS (10 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 11-bits long */
# define MCSPI_CH_CONF_WL_12BITS (11 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 12-bits long */
# define MCSPI_CH_CONF_WL_13BITS (12 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 13-bits long */
# define MCSPI_CH_CONF_WL_14BITS (13 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 14-bits long */
# define MCSPI_CH_CONF_WL_15BITS (14 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 15-bits long */
# define MCSPI_CH_CONF_WL_16BITS (15 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 16-bits long */
# define MCSPI_CH_CONF_WL_17BITS (16 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 17-bits long */
# define MCSPI_CH_CONF_WL_18BITS (17 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 18-bits long */
# define MCSPI_CH_CONF_WL_19BITS (18 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 19-bits long */
# define MCSPI_CH_CONF_WL_20BITS (19 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 20-bits long */
# define MCSPI_CH_CONF_WL_21BITS (20 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 21-bits long */
# define MCSPI_CH_CONF_WL_22BITS (21 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 22-bits long */
# define MCSPI_CH_CONF_WL_23BITS (22 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 23-bits long */
# define MCSPI_CH_CONF_WL_24BITS (23 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 24-bits long */
# define MCSPI_CH_CONF_WL_25BITS (24 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 25-bits long */
# define MCSPI_CH_CONF_WL_26BITS (25 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 26-bits long */
# define MCSPI_CH_CONF_WL_27BITS (26 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 27-bits long */
# define MCSPI_CH_CONF_WL_28BITS (27 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 28-bits long */
# define MCSPI_CH_CONF_WL_29BITS (28 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 29-bits long */
# define MCSPI_CH_CONF_WL_30BITS (29 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 30-bits long */
# define MCSPI_CH_CONF_WL_31BITS (30 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 31-bits long */
# define MCSPI_CH_CONF_WL_32BITS (31 << MCSPI_CH_CONF_WL_SHIFT) /* The SPI word is 32-bits long */
#define MCSPI_CH_CONF_TRM_SHIFT (12) /* Bits 12-13: Transmit/receive modes */
#define MCSPI_CH_CONF_TRM_MASK (3 << MCSPI_CH_CONF_TRM_SHIFT)
# define MCSPI_CH_CONF_TRM_RXTX (0 << MCSPI_CH_CONF_TRM_SHIFT) /* Transmit and receive mode */
# define MCSPI_CH_CONF_TRM_RX (1 << MCSPI_CH_CONF_TRM_SHIFT) /* Receive-only mode */
# define MCSPI_CH_CONF_TRM_TX (2 << MCSPI_CH_CONF_TRM_SHIFT) /* Transmit-only mode */
#define MCSPI_CH_CONF_DMAW (1 << 14) /* Bit 14: DMA write request */
#define MCSPI_CH_CONF_DMAR (1 << 15) /* Bit 15: DMA read request */
#define MCSPI_CH_CONF_DPE0 (1 << 16) /* Bit 16: Transmission enable for data line 0 */
#define MCSPI_CH_CONF_DPE1 (1 << 17) /* Bit 17: Transmission enable for data line 1 */
#define MCSPI_CH_CONF_IS (1 << 18) /* Bit 18: Input select */
#define MCSPI_CH_CONF_TURBO (1 << 19) /* Bit 19: Turbo mode */
#define MCSPI_CH_CONF_FORCE (1 << 20) /* Bit 20: Manual SPIEN assertion to keep SPIEN active between SPI words */
#define MCSPI_CH_CONF_SPIENSLV_SHIFT (21) /* Bits 21-22: SPI slave select signal detection */
#define MCSPI_CH_CONF_SPIENSLV_MASK (3 << MCSPI_CH_CONF_SPIENSLV_SHIFT)
# define MCSPI_CH_CONF_SPIENSLV0 (0 << MCSPI_CH_CONF_SPIENSLV_SHIFT) /* Detection enabled only on SPIEN[0] */
# define MCSPI_CH_CONF_SPIENSLV1 (1 << MCSPI_CH_CONF_SPIENSLV_SHIFT) /* Detection enabled only on SPIEN[1] */
# define MCSPI_CH_CONF_SPIENSLV2 (2 << MCSPI_CH_CONF_SPIENSLV_SHIFT) /* Detection enabled only on SPIEN[2] */
# define MCSPI_CH_CONF_SPIENSLV3 (3 << MCSPI_CH_CONF_SPIENSLV_SHIFT) /* Detection enabled only on SPIEN[3] */
#define MCSPI_CH_CONF_SBE (1 << 23) /* Bit 23: Start bit enable for SPI transfer */
#define MCSPI_CH_CONF_SBPOL (1 << 24) /* Bit 24: Start bit polarity */
#define MCSPI_CH_CONF_TCS_SHIFT (25) /* Bits 25-26: Chip select time control */
#define MCSPI_CH_CONF_TCS_MASK (3 << MCSPI_CH_CONF_TCS_SHIFT)
# define MCSPI_CH_CONF_TCS_0P5 (0 << MCSPI_CH_CONF_TCS_SHIFT) /* 0.5 clock cycles */
# define MCSPI_CH_CONF_TCS_1P5 (1 << MCSPI_CH_CONF_TCS_SHIFT) /* 1.5 clock cycles */
# define MCSPI_CH_CONF_TCS_2P5 (2 << MCSPI_CH_CONF_TCS_SHIFT) /* 2.5 clock cycles */
# define MCSPI_CH_CONF_TCS_3P5 (3 << MCSPI_CH_CONF_TCS_SHIFT) /* 3.5 clock cycles */
#define MCSPI_CH_CONF_FFEW (1 << 27) /* Bit 27: FIFO enabled for transmit */
#define MCSPI_CH_CONF_FFER (1 << 28) /* Bit 28: FIFO enabled for receive */
#define MCSPI_CH_CONF_CLKG (1 << 29) /* Bit 29: Clock divider granularity */
#define MCSPI_CH_STAT_RXS (1 << 0) /* Bit 0: Channel receiver register status */
#define MCSPI_CH_STAT_TXS (1 << 1) /* Bit 1: Channel transmitter register status */
#define MCSPI_CH_STAT_EOT (1 << 2) /* Bit 2: Channel end-of-transfer status */
#define MCSPI_CH_STAT_TXFFE (1 << 3) /* Bit 3: Channel FIFO transmit buffer empty status */
#define MCSPI_CH_STAT_TXFFF (1 << 4) /* Bit 4: Channel FIFO transmit buffer full status */
#define MCSPI_CH_STAT_RXFFE (1 << 5) /* Bit 5: Channel FIFO receive buffer empty status */
#define MCSPI_CH_STAT_RXFFF (1 << 6) /* Bit 6: Channel FIFO receive buffer full status */
#define MCSPI_CH_CTRL_EN (1 << 0) /* Bit 0: Channel enable */
#define MCSPI_CH_CTRL_EXTCLK_SHFT (8) /* Bits 8-15: Clock ratio extension */
#define MCSPI_CH_CTRL_EXTCLK_MASK (255 << MCSPI_CH_CTRL_EXTCLK_SHFT)
#define MCSPI_XFER_LEVEL_AEL_SHIFT (0) /* Bits 0-7: Buffer almost empty */
#define MCSPI_XFER_LEVEL_AEL_MASK (255 << MCSPI_XFER_LEVEL_AEL_SHIFT)
#define MCSPI_XFER_LEVEL_AFL_SHIFT (8) /* Bits 8-15: Buffer almost full */
#define MCSPI_XFER_LEVEL_AFL_MASK (255 << MCSPI_XFER_LEVEL_AFL_SHIFT)
#define MCSPI_XFER_LEVEL_WCNT_SHIFT (16) /* Bits 16-31: SPI word counter */
#define MCSPI_XFER_LEVEL_WCNT_MASK (65535 << MCSPI_XFER_LEVEL_WCNT_SHIFT)
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_MCSPI_H */
arch/arm/src/am335x/hardware/am335x_wdog.h
+54 -54
View File
@@ -49,57 +49,57 @@
/* Register offsets *****************************************************************/
#define AM335X_WDT_WIDR_OFFSET 0x0000 /* Watchdog Identification Register */
#define AM335X_WDT_WDSC_OFFSET 0x0010 /* Watchdog System Control Register */
#define AM335X_WDT_WDST_OFFSET 0x0014 /* Watchdog Status Register */
#define AM335X_WDT_WISR_OFFSET 0x0018 /* Watchdog Interrupt Status Register */
#define AM335X_WDT_WIER_OFFSET 0x001C /* Watchdog Interrupt Enable Register */
#define AM335X_WDT_WCLR_OFFSET 0x0024 /* Watchdog Control Register */
#define AM335X_WDT_WCRR_OFFSET 0x0028 /* Watchdog Counter Register */
#define AM335X_WDT_WLDR_OFFSET 0x002C /* Watchdog Load Register */
#define AM335X_WDT_WTGR_OFFSET 0x0030 /* Watchdog Trigger Register */
#define AM335X_WDT_WWPS_OFFSET 0x0034 /* Watchdog Write Posting Bits Register */
#define AM335X_WDT_WDLY_OFFSET 0x0044 /* Watchdog Delay Configuration Register */
#define AM335X_WDT_WSPR_OFFSET 0x0048 /* Watchdog Start/Stop Register */
#define AM335X_WDT_WIRQSTATRAW_OFFSET 0x0054 /* Watchdog Raw Interrupt Status Register */
#define AM335X_WDT_WIRQSTAT_OFFSET 0x0058 /* Watchdog Interrupt Status Register */
#define AM335X_WDT_WIRQENSET_OFFSET 0x005C /* Watchdog Interrupt Enable Set Register */
#define AM335X_WDT_WIRQENCLR_OFFSET 0x0060 /* Watchdog Interrupt Enable Clear Register */
#define AM335X_WDT_IDR_OFFSET 0x0000 /* Watchdog Identification Register */
#define AM335X_WDT_DSC_OFFSET 0x0010 /* Watchdog System Control Register */
#define AM335X_WDT_DST_OFFSET 0x0014 /* Watchdog Status Register */
#define AM335X_WDT_ISR_OFFSET 0x0018 /* Watchdog Interrupt Status Register */
#define AM335X_WDT_IER_OFFSET 0x001c /* Watchdog Interrupt Enable Register */
#define AM335X_WDT_CLR_OFFSET 0x0024 /* Watchdog Control Register */
#define AM335X_WDT_CRR_OFFSET 0x0028 /* Watchdog Counter Register */
#define AM335X_WDT_LDR_OFFSET 0x002c /* Watchdog Load Register */
#define AM335X_WDT_TGR_OFFSET 0x0030 /* Watchdog Trigger Register */
#define AM335X_WDT_WPS_OFFSET 0x0034 /* Watchdog Write Posting Bits Register */
#define AM335X_WDT_DLY_OFFSET 0x0044 /* Watchdog Delay Configuration Register */
#define AM335X_WDT_SPR_OFFSET 0x0048 /* Watchdog Start/Stop Register */
#define AM335X_WDT_IRQ_STAT_RAW_OFFSET 0x0054 /* Watchdog Raw Interrupt Status Register */
#define AM335X_WDT_IRQ_STAT_OFFSET 0x0058 /* Watchdog Interrupt Status Register */
#define AM335X_WDT_IRQ_EN_SET_OFFSET 0x005c /* Watchdog Interrupt Enable Set Register */
#define AM335X_WDT_IRQ_EN_CLR_OFFSET 0x0060 /* Watchdog Interrupt Enable Clear Register */
/* Register addresses ***************************************************************/
#define AM335X_WDT_WIDR (AM335X_WDT1_VADDR + AM335X_WDT_WIDR_OFFSET)
#define AM335X_WDT_WDSC (AM335X_WDT1_VADDR + AM335X_WDT_WDSC_OFFSET)
#define AM335X_WDT_WDST (AM335X_WDT1_VADDR + AM335X_WDT_WDST_OFFSET)
#define AM335X_WDT_WISR (AM335X_WDT1_VADDR + AM335X_WDT_WISR_OFFSET)
#define AM335X_WDT_WIER (AM335X_WDT1_VADDR + AM335X_WDT_WIER_OFFSET)
#define AM335X_WDT_WCLR (AM335X_WDT1_VADDR + AM335X_WDT_WCLR_OFFSET)
#define AM335X_WDT_WCRR (AM335X_WDT1_VADDR + AM335X_WDT_WCRR_OFFSET)
#define AM335X_WDT_WLDR (AM335X_WDT1_VADDR + AM335X_WDT_WLDR_OFFSET)
#define AM335X_WDT_WTGR (AM335X_WDT1_VADDR + AM335X_WDT_WTGR_OFFSET)
#define AM335X_WDT_WWPS (AM335X_WDT1_VADDR + AM335X_WDT_WWPS_OFFSET)
#define AM335X_WDT_WDLY (AM335X_WDT1_VADDR + AM335X_WDT_WDLY_OFFSET)
#define AM335X_WDT_WSPR (AM335X_WDT1_VADDR + AM335X_WDT_WSPR_OFFSET)
#define AM335X_WDT_WIRQSTATRAW (AM335X_WDT1_VADDR + AM335X_WDT_WIRQSTATRAW_OFFSET)
#define AM335X_WDT_WIRQSTAT (AM335X_WDT1_VADDR + AM335X_WDT_WIRQSTAT_OFFSET)
#define AM335X_WDT_WIRQENSET (AM335X_WDT1_VADDR + AM335X_WDT_WIRQENSET_OFFSET)
#define AM335X_WDT_WIRQENCLR (AM335X_WDT1_VADDR + AM335X_WDT_WIRQENCLR_OFFSET)
#define AM335X_WDT_IDR (AM335X_WDT1_VADDR + AM335X_WDT_IDR_OFFSET)
#define AM335X_WDT_DSC (AM335X_WDT1_VADDR + AM335X_WDT_DSC_OFFSET)
#define AM335X_WDT_DST (AM335X_WDT1_VADDR + AM335X_WDT_DST_OFFSET)
#define AM335X_WDT_ISR (AM335X_WDT1_VADDR + AM335X_WDT_ISR_OFFSET)
#define AM335X_WDT_IER (AM335X_WDT1_VADDR + AM335X_WDT_IER_OFFSET)
#define AM335X_WDT_CLR (AM335X_WDT1_VADDR + AM335X_WDT_CLR_OFFSET)
#define AM335X_WDT_CRR (AM335X_WDT1_VADDR + AM335X_WDT_CRR_OFFSET)
#define AM335X_WDT_LDR (AM335X_WDT1_VADDR + AM335X_WDT_LDR_OFFSET)
#define AM335X_WDT_TGR (AM335X_WDT1_VADDR + AM335X_WDT_TGR_OFFSET)
#define AM335X_WDT_WPS (AM335X_WDT1_VADDR + AM335X_WDT_WPS_OFFSET)
#define AM335X_WDT_DLY (AM335X_WDT1_VADDR + AM335X_WDT_DLY_OFFSET)
#define AM335X_WDT_SPR (AM335X_WDT1_VADDR + AM335X_WDT_SPR_OFFSET)
#define AM335X_WDT_IRQ_STAT_RAW (AM335X_WDT1_VADDR + AM335X_WDT_IRQ_STAT_RAW_OFFSET)
#define AM335X_WDT_IRQ_STAT (AM335X_WDT1_VADDR + AM335X_WDT_IRQ_STAT_OFFSET)
#define AM335X_WDT_IRQ_EN_SET (AM335X_WDT1_VADDR + AM335X_WDT_IRQ_EN_SET_OFFSET)
#define AM335X_WDT_IRQ_EN_CLR (AM335X_WDT1_VADDR + AM335X_WDT_IRQ_EN_CLR_OFFSET)
/* Register bit definitions *********************************************************/
/* Watchdog System Control Register */
#define WDT_WDSC_SOFTRESET (1 << 1) /* Bit 1: Watchdog Software Reset */
#define WDT_WDSC_IDLEMODE_SHIFT (3) /* Bit 3-4: Watchdog Idle Mode */
# define WDT_WDSC_IDLEMODE_FORCE (0 << WDT_WDSC_IDLEMODE_SHIFT) /* Force-idle Mode */
# define WDT_WDSC_IDLEMODE_NO (1 << WDT_WDSC_IDLEMODE_SHIFT) /* No-idle Mode */
# define WDT_WDSC_IDLEMODE_SMART (2 << WDT_WDSC_IDLEMODE_SHIFT) /* Smart-idle Mode */
# define WDT_WDSC_IDLEMODE_SMART_WKUP (3 << WDT_WDSC_IDLEMODE_SHIFT) /* Smart-idle Wakeup-capable Mode */
#define WDT_WDSC_EMUFREE (1 << 5) /* Bit 5: Watchdog DEBUG Disable */
#define WDT_DSC_SOFT_RST (1 << 1) /* Bit 1: Watchdog Software Reset */
#define WDT_DSC_IDLE_SHIFT (3) /* Bit 3-4: Watchdog Idle Mode */
# define WDT_DSC_IDLE_FORCE (0 << WDT_DSC_IDLE_SHIFT) /* Force-idle Mode */
# define WDT_DSC_IDLE_NO (1 << WDT_DSC_IDLE_SHIFT) /* No-idle Mode */
# define WDT_DSC_IDLE_SMART (2 << WDT_DSC_IDLE_SHIFT) /* Smart-idle Mode */
# define WDT_DSC_IDLE_SMART_WKUP (3 << WDT_DSC_IDLE_SHIFT) /* Smart-idle Wakeup-capable Mode */
#define WDT_DSC_EMU_FREE (1 << 5) /* Bit 5: Watchdog DEBUG Disable */
/* Watchdog Status Register */
#define WDT_WDST_RESETDONE (1 << 0) /* Bit 0: Watchdog Reset Completed */
#define WDT_DST_RST_DONE (1 << 0) /* Bit 0: Watchdog Reset Completed */
/* Watchdog Interrupt Registers */
@@ -108,26 +108,26 @@
/* Watchdog Control Register */
#define WDT_WCLR_PTV_SHIFT (2) /* Bits 2-4: Prescaler Value */
#define WDT_WCLR_PTV_MASK (7 << WDT_WCLR_PTV_SHIFT)
# define WDT_WCLR_PTV(n) ((uint32_t)(n) << WDT_WCLR_PTV_SHIFT)
#define WDT_WCLR_PRE_ENABLE (1 << 5) /* Bit 5: Prescaler Enabled */
#define WDT_CLR_PTV_SHIFT (2) /* Bits 2-4: Prescaler Value */
#define WDT_CLR_PTV_MASK (7 << WDT_CLR_PTV_SHIFT)
# define WDT_CLR_PTV(n) ((uint32_t)(n) << WDT_CLR_PTV_SHIFT)
#define WDT_CLR_PRE_ENABLE (1 << 5) /* Bit 5: Prescaler Enabled */
/* Watchdog Write Posting Bits Register */
#define WDT_WWPS_W_PEND_WCLR (1 << 0) /* Bit 0: Write Pending for Register WCLR */
#define WDT_WWPS_W_PEND_WCRR (1 << 1) /* Bit 1: Write pending for register WCRR */
#define WDT_WWPS_W_PEND_WLDR (1 << 2) /* Bit 2: Write pending for register WLDR */
#define WDT_WWPS_W_PEND_WTGR (1 << 3) /* Bit 3: Write pending for register WTGR */
#define WDT_WWPS_W_PEND_WSPR (1 << 4) /* Bit 4: Write pending for register WSPR */
#define WDT_WWPS_W_PEND_WDLY (1 << 5) /* Bit 5: Write pending for register WDLY */
#define WDT_WPS_W_PEND_WCLR (1 << 0) /* Bit 0: Write Pending for Register WCLR */
#define WDT_WPS_W_PEND_WCRR (1 << 1) /* Bit 1: Write pending for register WCRR */
#define WDT_WPS_W_PEND_WLDR (1 << 2) /* Bit 2: Write pending for register WLDR */
#define WDT_WPS_W_PEND_WTGR (1 << 3) /* Bit 3: Write pending for register WTGR */
#define WDT_WPS_W_PEND_WSPR (1 << 4) /* Bit 4: Write pending for register WSPR */
#define WDT_WPS_W_PEND_WDLY (1 << 5) /* Bit 5: Write pending for register WDLY */
/* Watchdog Start/Stop Register */
#define WDT_WSPR_START_FEED_A (0x0000bbbb)
#define WDT_WSPR_START_FEED_B (0x00004444)
#define WDT_WSPR_STOP_FEED_A (0x0000aaaa)
#define WDT_WSPR_STOP_FEED_B (0x00005555)
#define WDT_SPR_START_FEED_A (0x0000bbbb)
#define WDT_SPR_START_FEED_B (0x00004444)
#define WDT_SPR_STOP_FEED_A (0x0000aaaa)
#define WDT_SPR_STOP_FEED_B (0x00005555)
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_WDOG_H */
arch/arm/src/armv7-a/arm_pgalloc.c
-1
View File
@@ -53,7 +53,6 @@
#ifdef CONFIG_BUILD_KERNEL
/****************************************************************************
* Private Functions
****************************************************************************/
arch/arm/src/cxd56xx/Kconfig
+1072 -4
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/cxd56xx/Make.defs
+80
View File
@@ -83,16 +83,34 @@ CMN_CSRCS += up_copyarmstate.c
endif
endif
CHIP_ASRCS += cxd56_farapistub.S
CHIP_CSRCS = cxd56_allocateheap.c cxd56_idle.c
CHIP_CSRCS += cxd56_uid.c
CHIP_CSRCS += cxd56_serial.c cxd56_uart.c cxd56_irq.c
CHIP_CSRCS += cxd56_start.c
CHIP_CSRCS += cxd56_timerisr.c
CHIP_CSRCS += cxd56_pinconfig.c
CHIP_CSRCS += cxd56_clock.c
CHIP_CSRCS += cxd56_delay.c
CHIP_CSRCS += cxd56_gpio.c
CHIP_CSRCS += cxd56_pmic.c
CHIP_CSRCS += cxd56_cpufifo.c
CHIP_CSRCS += cxd56_icc.c
CHIP_CSRCS += cxd56_powermgr.c
CHIP_CSRCS += cxd56_farapi.c
CHIP_CSRCS += cxd56_sysctl.c
ifeq ($(CONFIG_CXD56_PM_PROCFS),y)
CHIP_CSRCS += cxd56_powermgr_procfs.c
endif
ifeq ($(CONFIG_CXD56_RTC),y)
CHIP_CSRCS += cxd56_rtc.c
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += cxd56_rtc_lowerhalf.c
endif
endif
ifeq ($(CONFIG_CXD56_GPIO_IRQ),y)
CHIP_CSRCS += cxd56_gpioint.c
@@ -101,3 +119,65 @@ endif
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += cxd56_usbdev.c
endif
ifeq ($(CONFIG_CXD56_SDIO),y)
CHIP_CSRCS += cxd56_sdhci.c
endif
ifeq ($(CONFIG_CXD56_SFC),y)
CHIP_CSRCS += cxd56_sfc.c
endif
ifeq ($(CONFIG_CXD56_EMMC),y)
CHIP_CSRCS += cxd56_emmc.c
endif
ifeq ($(CONFIG_CXD56_SPI),y)
CHIP_CSRCS += cxd56_spi.c
endif
ifeq ($(CONFIG_CXD56_I2C),y)
CHIP_CSRCS += cxd56_i2c.c
endif
ifeq ($(CONFIG_CXD56_DMAC),y)
CHIP_CSRCS += cxd56_dmac.c
endif
ifeq ($(CONFIG_CXD56_PWM),y)
CHIP_CSRCS += cxd56_pwm.c
endif
ifeq ($(CONFIG_CXD56_GAUGE),y)
CHIP_CSRCS += cxd56_gauge.c
endif
ifeq ($(CONFIG_CXD56_CHARGER),y)
CHIP_CSRCS += cxd56_charger.c
endif
ifeq ($(CONFIG_CXD56_GE2D),y)
CHIP_CSRCS += cxd56_ge2d.c
endif
ifeq ($(CONFIG_CXD56_CISIF),y)
CHIP_CSRCS += cxd56_cisif.c
endif
ifeq ($(CONFIG_CXD56_SCU),y)
CHIP_CSRCS += cxd56_scu.c cxd56_scufifo.c
ifeq ($(CONFIG_CXD56_ADC),y)
CHIP_CSRCS += cxd56_adc.c
endif
ifeq ($(CONFIG_CXD56_UDMAC),y)
CHIP_CSRCS += cxd56_udmac.c
endif
endif
ifeq ($(CONFIG_CXD56_TIMER),y)
CHIP_CSRCS += cxd56_timer.c
endif
ifeq ($(CONFIG_CXD56_WDT),y)
CHIP_CSRCS += cxd56_wdt.c
endif
arch/arm/src/cxd56xx/cxd56_adc.c
+1065
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File diff suppressed because it is too large Load Diff
arch/arm/src/cxd56xx/cxd56_adc.h
+79
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@@ -0,0 +1,79 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_adc.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_ADC_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: cxd56_adc_getinterval
*
* Description:
*
****************************************************************************/
#ifdef CONFIG_CXD56_ADC
void cxd56_adc_getinterval(int adctype, uint32_t *interval, uint16_t *adjust);
#else
#define cxd56_adc_getinterval(adctype, interval, adjust)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_ADC_H */
arch/arm/src/cxd56xx/cxd56_charger.c
+688
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File diff suppressed because it is too large Load Diff
arch/arm/src/cxd56xx/cxd56_charger.h
+44
View File
@@ -0,0 +1,44 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_charger.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CHARGER_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_CHARGER_H
/* initialize function */
int cxd56_charger_initialize(FAR const char *devpath);
int cxd56_charger_uninitialize(FAR const char *devpath);
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CHARGER_H */
arch/arm/src/cxd56xx/cxd56_cisif.c
+910
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File diff suppressed because it is too large Load Diff
arch/arm/src/cxd56xx/cxd56_clock.c
+106 -55
View File
@@ -97,10 +97,9 @@
#ifndef CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER
#define CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER 4
#endif /* CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER */
#endif
/*
* Flags for IMG device active
/* Flags for IMG device active
*
* This flags for fixed clock devices.
*/
@@ -139,10 +138,14 @@ struct power_domain
static void cxd56_img_clock_enable(void);
static void cxd56_img_clock_disable(void);
static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on);
static void cxd56_scu_peri_clock_enable(FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_disable(FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_gating(FAR const struct scu_peripheral *p, int enable) __unused;
static void cxd56_scu_clock_ctrl(\
uint32_t block, uint32_t intr, int on);
static void cxd56_scu_peri_clock_enable(\
FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_disable(\
FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_gating(\
FAR const struct scu_peripheral *p, int enable) __unused;
/****************************************************************************
* Public Data
@@ -286,7 +289,7 @@ static inline void release_pwd_reset(uint32_t domain)
{
/* Release power domain reset */
putreg32(domain | domain <<16, CXD56_TOPREG_PWD_RESET0);
putreg32(domain | domain << 16, CXD56_TOPREG_PWD_RESET0);
}
}
@@ -298,7 +301,7 @@ static void enable_pwd(int pdid)
stat = getreg32(CXD56_TOPREG_PWD_STAT);
if ((stat & domain) != domain)
{
putreg32((domain|(domain<<16)), CXD56_TOPREG_PWD_CTL);
putreg32((domain | (domain << 16)), CXD56_TOPREG_PWD_CTL);
do_power_control();
release_pwd_reset(domain);
}
@@ -316,7 +319,7 @@ static void disable_pwd(int pdid)
g_digital.refs[pdid]--;
if (g_digital.refs[pdid] == 0)
{
putreg32(domain<<16, CXD56_TOPREG_PWD_CTL);
putreg32(domain << 16, CXD56_TOPREG_PWD_CTL);
do_power_control();
}
}
@@ -330,7 +333,7 @@ static void enable_apwd(int apdid)
stat = getreg32(CXD56_TOPREG_ANA_PW_STAT);
if ((stat & domain) != domain)
{
putreg32(domain|(domain<<16), CXD56_TOPREG_ANA_PW_CTL);
putreg32(domain | (domain << 16), CXD56_TOPREG_ANA_PW_CTL);
do_power_control();
}
g_analog.refs[apdid]++;
@@ -347,7 +350,7 @@ static void disable_apwd(int apdid)
g_analog.refs[apdid]--;
if (g_analog.refs[apdid] == 0)
{
putreg32(domain<<16, CXD56_TOPREG_ANA_PW_CTL);
putreg32(domain << 16, CXD56_TOPREG_ANA_PW_CTL);
do_power_control();
}
}
@@ -419,7 +422,8 @@ void cxd56_xosc_disable(void)
void cxd56_spif_clock_enable(void)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (val & CK_SFC)
@@ -446,7 +450,8 @@ void cxd56_spif_clock_enable(void)
void cxd56_spif_clock_disable(void)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (!(val & CK_SFC))
@@ -470,7 +475,8 @@ void cxd56_spif_clock_disable(void)
uint32_t cxd56_get_cpu_baseclk(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_AHB);
n = (val >> 16) & 0x7f;
@@ -507,7 +513,8 @@ void cxd56_cpu_clock_enable(int cpu)
void cxd56_cpulist_clock_enable(uint32_t cpus)
{
uint32_t c, bits = (cpus & 0x3f) << 16;
uint32_t c;
uint32_t bits = (cpus & 0x3f) << 16;
c = getreg32(CXD56_CRG_CK_GATE_AHB);
putreg32(c | bits, CXD56_CRG_CK_GATE_AHB);
@@ -534,7 +541,8 @@ void cxd56_cpu_clock_disable(int cpu)
void cxd56_cpulist_clock_disable(uint32_t cpus)
{
uint32_t c, bits = (cpus & 0x3f) << 16;
uint32_t c;
uint32_t bits = (cpus & 0x3f) << 16;
c = getreg32(CXD56_CRG_CK_GATE_AHB);
putreg32(c & ~bits, CXD56_CRG_CK_GATE_AHB);
@@ -561,7 +569,9 @@ void cxd56_cpu_reset(int cpu)
void cxd56_cpulist_reset(uint32_t cpus)
{
uint32_t c, r, bits = (cpus & 0x3f) << 16;
uint32_t c;
uint32_t r;
uint32_t bits = (cpus & 0x3f) << 16;
/* Reset assert */
@@ -589,7 +599,8 @@ void cxd56_cpulist_reset(uint32_t cpus)
void cxd56_usb_clock_enable(void)
{
uint32_t c, r;
uint32_t c;
uint32_t r;
enable_pwd(PDID_APP_SUB);
@@ -615,7 +626,8 @@ void cxd56_usb_clock_enable(void)
void cxd56_usb_clock_disable(void)
{
uint32_t c, r;
uint32_t c;
uint32_t r;
c = getreg32(CXD56_CRG_CK_GATE_AHB);
if (c & CK_GATE_USB)
@@ -639,7 +651,9 @@ void cxd56_usb_clock_disable(void)
void cxd56_emmc_clock_enable(uint32_t div, uint32_t driver, uint32_t sample)
{
uint32_t c, r, g;
uint32_t c;
uint32_t r;
uint32_t g;
enable_pwd(PDID_APP_SUB);
@@ -686,7 +700,9 @@ void cxd56_emmc_clock_enable(uint32_t div, uint32_t driver, uint32_t sample)
void cxd56_emmc_clock_disable(void)
{
uint32_t c, r, g;
uint32_t c;
uint32_t r;
uint32_t g;
c = getreg32(CXD56_CRG_CKEN_EMMC);
if (c != 7)
@@ -699,7 +715,7 @@ void cxd56_emmc_clock_disable(void)
putreg32(0, CXD56_CRG_CKEN_EMMC);
r = getreg32(CXD56_CRG_RESET);
putreg32(r & ~(XRS_MMC|XRS_MMC_CRG), CXD56_CRG_RESET);
putreg32(r & ~(XRS_MMC | XRS_MMC_CRG), CXD56_CRG_RESET);
disable_pwd(PDID_APP_SUB);
}
@@ -713,7 +729,8 @@ void cxd56_emmc_clock_disable(void)
void cxd56_sdio_clock_enable(void)
{
uint32_t c, r;
uint32_t c;
uint32_t r;
enable_pwd(PDID_APP_SUB);
@@ -738,7 +755,8 @@ void cxd56_sdio_clock_enable(void)
void cxd56_sdio_clock_disable(void)
{
uint32_t c, r;
uint32_t c;
uint32_t r;
c = getreg32(CXD56_CRG_CK_GATE_AHB);
if (c & CK_GATE_SDIO)
@@ -814,7 +832,8 @@ bool cxd56_audio_clock_is_enabled(void)
static void cxd56_spim_clock_enable(void)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (val & CK_SPIM)
@@ -822,14 +841,16 @@ static void cxd56_spim_clock_enable(void)
return;
}
putreg32(val | CK_SPIM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_SPIM | CK_COM_BRG |
CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
busy_wait(10);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
putreg32(rst | XRST_SPIM, CXD56_TOPREG_SWRESET_BUS);
putreg32(val | CK_SPIM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_SPIM | CK_COM_BRG |
CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
}
/****************************************************************************
@@ -842,7 +863,9 @@ static void cxd56_spim_clock_enable(void)
static void cxd56_spim_clock_disable(void)
{
uint32_t val, rst, mask;
uint32_t val;
uint32_t rst;
uint32_t mask;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (!(val & CK_SPIM))
@@ -1095,7 +1118,8 @@ void cxd56_spi_clock_gear_adjust(int port, uint32_t maxfreq)
static void cxd56_i2cm_clock_enable(void)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (val & CK_I2CM)
@@ -1103,14 +1127,16 @@ static void cxd56_i2cm_clock_enable(void)
return;
}
putreg32(val | CK_I2CM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_I2CM | CK_COM_BRG |
CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
busy_wait(10);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
putreg32(rst | XRST_I2CM, CXD56_TOPREG_SWRESET_BUS);
putreg32(val | CK_I2CM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_I2CM | CK_COM_BRG |
CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
}
/****************************************************************************
@@ -1122,7 +1148,9 @@ static void cxd56_i2cm_clock_enable(void)
static void cxd56_i2cm_clock_disable(void)
{
uint32_t val, rst, mask;
uint32_t val;
uint32_t rst;
uint32_t mask;
val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
if (!(val & CK_I2CM))
@@ -1249,7 +1277,8 @@ void cxd56_i2c_clock_gate_disable(int port)
uint32_t cxd56_get_img_uart_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_IMG_UART);
n = (val >> 16) & 1;
@@ -1412,7 +1441,9 @@ static uint32_t cxd56_get_clock(enum clock_source cs)
return CONFIG_CXD56_XOSC_CLOCK;
case SYSPLL:
{
uint32_t ctrl, rc, fb;
uint32_t ctrl;
uint32_t rc;
uint32_t fb;
ctrl = getreg32(CXD56_TOPREG_SYS_PLL_CTRL2);
rc = ctrl >> 30;
@@ -1466,7 +1497,7 @@ uint32_t cxd56_get_sys_baseclock(void)
{
uint32_t div = ((val >> 10) & 0x3) + 1;
if (div == 4 && (val & (1<<2)))
if (div == 4 && (val & (1 << 2)))
{
div = 5;
}
@@ -1525,7 +1556,7 @@ uint32_t cxd56_get_appsmp_baseclock(void)
{
uint32_t div = ((val >> 10) & 0x3) + 1;
if (div == 4 && (val & (1<<7)))
if (div == 4 && (val & (1 << 7)))
{
div = 5;
}
@@ -1554,7 +1585,8 @@ uint32_t cxd56_get_com_baseclock(void)
uint32_t cxd56_get_sdio_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_PER_SDIO);
n = (val >> 16) & 1;
@@ -1573,7 +1605,8 @@ uint32_t cxd56_get_sdio_baseclock(void)
uint32_t cxd56_get_img_spi_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_IMG_SPI);
n = (val >> 16) & 1;
@@ -1592,7 +1625,8 @@ uint32_t cxd56_get_img_spi_baseclock(void)
uint32_t cxd56_get_img_wspi_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_IMG_WSPI);
n = (val >> 16) & 1;
@@ -1704,7 +1738,8 @@ static void cxd56_img_clock_disable(void)
static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
{
uint32_t val, stat;
uint32_t val;
uint32_t stat;
int retry = 10000;
putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
@@ -1743,7 +1778,8 @@ static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
static void cxd56_scu_clock_enable(void)
{
uint32_t val, stat;
uint32_t val;
uint32_t stat;
int retry = 1000;
val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
@@ -1797,7 +1833,8 @@ static void cxd56_scu_clock_enable(void)
void cxd56_scu_clock_disable(void)
{
uint32_t val, stat;
uint32_t val;
uint32_t stat;
int retry = 1000;
val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
@@ -1823,7 +1860,8 @@ void cxd56_scu_clock_disable(void)
/* Enable each blocks in SCU */
val = getreg32(CXD56_TOPREG_SCU_CKEN);
putreg32(val & ~(SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ), CXD56_TOPREG_SCU_CKEN);
putreg32(val & ~(SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ),
CXD56_TOPREG_SCU_CKEN);
do
{
@@ -1904,7 +1942,8 @@ void cxd56_scuseq_clock_disable(void)
static void cxd56_scu_peri_clock_enable(FAR const struct scu_peripheral *p)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
uint32_t cken = 1u << p->cken;
uint32_t crgintmask = 1u << p->crgintmask;
uint32_t swreset = 1u << p->swreset;
@@ -1932,7 +1971,8 @@ static void cxd56_scu_peri_clock_enable(FAR const struct scu_peripheral *p)
static void cxd56_scu_peri_clock_disable(FAR const struct scu_peripheral *p)
{
uint32_t val, rst;
uint32_t val;
uint32_t rst;
uint32_t cken = 1u << p->cken;
uint32_t crgintmask = 1u << p->crgintmask;
uint32_t swreset = 1u << p->swreset;
@@ -1953,7 +1993,8 @@ static void cxd56_scu_peri_clock_disable(FAR const struct scu_peripheral *p)
disable_pwd(PDID_SCU);
}
static void cxd56_scu_peri_clock_gating(FAR const struct scu_peripheral *p, int enable)
static void cxd56_scu_peri_clock_gating(\
FAR const struct scu_peripheral *p, int enable)
{
uint32_t cken = 1u << p->cken;
@@ -2086,7 +2127,8 @@ uint32_t cxd56_get_syspll_clock(void)
uint32_t cxd56_get_sys_ahb_baseclock(void)
{
uint32_t bus, ahb;
uint32_t bus;
uint32_t ahb;
bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
ahb = 1 << ((bus >> 16) & 0x7);
@@ -2095,7 +2137,8 @@ uint32_t cxd56_get_sys_ahb_baseclock(void)
uint32_t cxd56_get_sys_apb_baseclock(void)
{
uint32_t bus, apb;
uint32_t bus;
uint32_t apb;
bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
apb = 1 << ((bus >> 24) & 0x3);
@@ -2104,7 +2147,8 @@ uint32_t cxd56_get_sys_apb_baseclock(void)
uint32_t cxd56_get_sys_sfc_baseclock(void)
{
uint32_t bus, sfchclk;
uint32_t bus;
uint32_t sfchclk;
bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
sfchclk = ((bus >> 28) & 0xf);
@@ -2191,7 +2235,8 @@ uint32_t cxd56_get_gps_ahb_baseclock(void)
uint32_t cxd56_get_usb_baseclock(void)
{
uint32_t val;
int n, m;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_PER_USB);
n = (val >> 16) & 1;
@@ -2209,7 +2254,8 @@ uint32_t cxd56_get_usb_baseclock(void)
uint32_t cxd56_get_img_vsync_baseclock(void)
{
int n, m;
int n;
int m;
n = getreg32(CXD56_CRG_GEAR_N_IMG_VENB);
m = getreg32(CXD56_CRG_GEAR_M_IMG_VENB);
@@ -2226,9 +2272,13 @@ uint32_t cxd56_get_img_vsync_baseclock(void)
int up_pmramctrl(int cmd, uintptr_t addr, size_t size)
{
int startidx, endidx;
int startidx;
int endidx;
int i;
uint32_t mode, mask, ctrl, stat;
uint32_t mode;
uint32_t mask;
uint32_t ctrl;
uint32_t stat;
uint32_t val;
int changed = 0;
@@ -2317,7 +2367,8 @@ int up_pmramctrl(int cmd, uintptr_t addr, size_t size)
void up_pmstatdump(void)
{
uint32_t stat0, stat1;
uint32_t stat0;
uint32_t stat1;
const char statch[] = " -?+"; /* OFF, retention, invalid, ON */
const char gatech[] = "| "; /* clock on, clock off */
arch/arm/src/cxd56xx/cxd56_config.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56XX_CONFIG_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56XX_CONFIG_H
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CONFIG_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_CONFIG_H
/****************************************************************************
* Included Files
@@ -135,4 +135,4 @@
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56XX_CONFIG_H */
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CONFIG_H */
arch/arm/src/cxd56xx/cxd56_cpufifo.c
+1
View File
@@ -80,6 +80,7 @@ static void cpufifo_reserve(uint32_t data[2]);
/****************************************************************************
* Private Data
****************************************************************************/
/* Only for SYS, GNSS CPUs */
static sq_queue_t g_pushqueue;
arch/arm/src/cxd56xx/cxd56_delay.c
+119
View File
@@ -0,0 +1,119 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_delay.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include "cxd56_clock.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CXD56XX_LOOPSPERMSEC_156MHZ 7428ull
#define CXD56XX_LOOPSPERMSEC_BY_CLOCK(clock) \
(uint32_t)(CXD56XX_LOOPSPERMSEC_156MHZ * (clock) / 156000000ull)
/* Adjust manually to be up_udelay(1000) is neary equal with up_udelay(999) */
#define CXD56XX_LOOPSPERUSEC_ADJUST 810ul;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_mdelay
*
* Description:
* Delay inline for the requested number of milliseconds.
* *** NOT multi-tasking friendly ***
*
****************************************************************************/
void up_mdelay(unsigned int milliseconds)
{
volatile unsigned int i;
volatile unsigned int j;
uint32_t clock = cxd56_get_cpu_baseclk();
uint32_t loops = CXD56XX_LOOPSPERMSEC_BY_CLOCK(clock);
for (i = 0; i < milliseconds; i++)
{
for (j = 0; j < loops; j++)
{
}
}
}
/****************************************************************************
* Name: up_udelay
*
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
*
****************************************************************************/
void up_udelay(useconds_t microseconds)
{
volatile unsigned int i;
volatile unsigned int j;
uint32_t clock = cxd56_get_cpu_baseclk();
uint32_t loops = CXD56XX_LOOPSPERMSEC_BY_CLOCK(clock);
uint32_t milliseconds = microseconds / 1000;
for (i = 0; i < milliseconds; i++)
{
for (j = 0; j < loops; j++)
{
}
}
loops = loops * (microseconds % 1000) / CXD56XX_LOOPSPERUSEC_ADJUST;
for (i = 0; i < loops; i++)
{
}
}
arch/arm/src/cxd56xx/cxd56_dmac.c
+980
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/cxd56xx/cxd56_dmac.h
+206
View File
@@ -0,0 +1,206 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_dmac.h
*
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H
#include <stdint.h>
#include "hardware/cxd56_dmac_common.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CXD56_DMA_PERIPHERAL_MASK (0x0f)
#define CXD56_DMA_PERIPHERAL_UART2_TX (0)
#define CXD56_DMA_PERIPHERAL_UART2_RX (1)
#define CXD56_DMA_PERIPHERAL_SPI4_TX (2)
#define CXD56_DMA_PERIPHERAL_SPI4_RX (3)
#define CXD56_DMA_PERIPHERAL_SPI5_TX (4)
#define CXD56_DMA_PERIPHERAL_SPI5_RX (5)
#define CXD56_DMA_INTR_ITC (1u<<0) /**< Terminal count interrupt status */
#define CXD56_DMA_INTR_ERR (1u<<1) /**< Error interrupt status */
#define CXD56_DMAC_WIDTH8 0 /**< 8 bit width */
#define CXD56_DMAC_WIDTH16 1 /**< 16 bit width */
#define CXD56_DMAC_WIDTH32 2 /**< 32 bit width */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: cxd56_dmachannel
*
* Description:
* Allocate a DMA channel. This function gives the caller mutually exclusive
* access to a DMA channel.
*
* If no DMA channel is available, then cxd56_dmachannel() will wait until
* the holder of a channel relinquishes the channel by calling
* cxd56_dmafree().
*
* Input parameters:
* ch - DMA channel to use
* maxsize - Max size to be transfered in bytes
*
* Returned Value:
* This function ALWAYS returns a non-NULL, void* DMA channel handle.
*
* Assumptions:
* - The caller can wait for a DMA channel to be freed if it is not
* available.
*
****************************************************************************/
DMA_HANDLE cxd56_dmachannel(int ch, ssize_t maxsize);
/****************************************************************************
* Name: cxd56_dmafree
*
* Description:
* Release a DMA channel. If another thread is waiting for this DMA channel
* in a call to cxd56_dmachannel, then this function will re-assign the DMA
* channel to that thread and wake it up.
*
* NOTE: The 'handle' used in this argument must NEVER be used again until
* cxd56_dmachannel() is called again to re-gain access to the channel.
*
* Returned Value:
* None
*
* Assumptions:
* - The caller holds the DMA channel.
* - There is no DMA in progress
*
****************************************************************************/
void cxd56_dmafree(DMA_HANDLE handle);
/****************************************************************************
* Name: cxd56_rxdmasetup
*
* Description:
* Configure an RX (peripheral-to-memory) DMA before starting the transfer.
*
* Input Parameters:
* paddr - Peripheral address (source)
* maddr - Memory address (destination)
* nbytes - Number of bytes to transfer. Must be an even multiple of the
* configured transfer size.
* config - Channel configuration selections
*
****************************************************************************/
void cxd56_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
size_t nbytes, dma_config_t config);
/****************************************************************************
* Name: cxd56_txdmasetup
*
* Description:
* Configure an TX (memory-to-peripheral) DMA before starting the transfer.
*
* Input Parameters:
* paddr - Peripheral address (destination)
* maddr - Memory address (source)
* nbytes - Number of bytes to transfer. Must be an even multiple of the
* configured transfer size.
* config - Channel configuration selections
*
****************************************************************************/
void cxd56_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
size_t nbytes, dma_config_t config);
/****************************************************************************
* Name: cxd56_dmastart
*
* Description:
* Start the DMA transfer
*
* Assumptions:
* - DMA handle allocated by cxd56_dmachannel()
* - No DMA in progress
*
****************************************************************************/
void cxd56_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
/****************************************************************************
* Name: cxd56_dmastop
*
* Description:
* Cancel the DMA. After cxd56_dmastop() is called, the DMA channel is reset
* and cxd56_dmasetup() must be called before cxd56_dmastart() can be called
* again
*
* Assumptions:
* - DMA handle allocated by cxd56_dmachannel()
*
****************************************************************************/
void cxd56_dmastop(DMA_HANDLE handle);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H */
arch/arm/src/cxd56xx/cxd56_dmac_common.h
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_dmac_common.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H
#include <stdint.h>
/****************************************************************************
* Public Types
****************************************************************************/
/* DMA_HANDLE provides an opaque are reference that can be used to represent a
* DMA channel.
*/
typedef FAR void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the
* completion of the DMA.
*
* Input Parameters:
* handle - Refers tot he DMA channel or stream
* status - A bit encoded value that provides the completion status.
* See the DMASTATUS_* definitions above.
* arg - A user-provided value that was provided when cxd56_dmastart()
* was called.
*/
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
/* Type of 'config' argument passed to cxd56_rxdmasetup() and
* cxd56_txdmasetup.
* See CXD56_DMA_* encodings above. If these encodings exceed 16-bits, then
* this should be changed to a uint32_t.
*/
typedef struct {
uint16_t channel_cfg;
uint8_t dest_width;
uint8_t src_width;
} dma_config_t;
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H */
arch/arm/src/cxd56xx/cxd56_emmc.c
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arch/arm/src/cxd56xx/cxd56_emmc.h
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_emmc.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_EMMC_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_EMMC_H
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
int cxd56_emmcinitialize(void);
void cxd56_emmcuninitialize(void);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_EMMC_H */
arch/arm/src/cxd56xx/cxd56_farapi.c
+287
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_farapi.c
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/sched.h>
#include <nuttx/irq.h>
#include <debug.h>
#include <errno.h>
#include <arch/chip/pm.h>
#include "up_arch.h"
#include "up_internal.h"
#include "chip.h"
#include "cxd56_icc.h"
#include "cxd56_config.h"
#include "cxd56_farapistub.h"
#include "hardware/cxd5602_backupmem.h"
int PM_WakeUpCpu(int cpuid);
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define GPS_CPU_ID (1)
#ifndef CONFIG_CXD56_FARAPI_VERSION_CHECK
#define CONFIG_CXD56_FARAPI_VERSION_CHECK 1
#endif
#define CPU_ID (CXD56_CPU_BASE + 0x40)
/****************************************************************************
* Private Type
****************************************************************************/
typedef int farapicallback(void *data);
struct modulelist_s
{
void *mod;
int cpuno;
void *reserved;
int16_t mbxid;
};
struct apimsg_s
{
int id;
void *arg;
int16_t mbxid;
int16_t flagid;
int flagbitno;
};
struct farcallback_s
{
int (*cbfunc)(void *); /* pointer to callback function */
void *data; /* callback data */
int flagbitno; /* callback eventflag bitno */
};
struct farmsghead_s
{
struct farmsghead_s *next;
};
struct farmsg_s
{
struct farmsghead_s head; /* message head */
int cpuid; /* CPU ID of API caller */
int modid; /* module table offset */
union
{
struct apimsg_s api;
struct farcallback_s cb;
} u;
};
/****************************************************************************
* Public Data
****************************************************************************/
extern char Image$$MODLIST$$Base[];
/****************************************************************************
* Private Data
****************************************************************************/
static sem_t g_farwait;
static sem_t g_farlock;
static struct pm_cpu_wakelock_s g_wlock = {
.count = 0,
.info = PM_CPUWAKELOCK_TAG('R', 'M', 0),
};
/****************************************************************************
* Private Functions
****************************************************************************/
static int farapi_semtake(sem_t *id)
{
while (sem_wait(id) != 0)
{
ASSERT(errno == EINTR);
}
return OK;
}
#ifdef CONFIG_CXD56_FARAPI_DEBUG
static void dump_farapi_message(struct farmsg_s *msg)
{
_info("cpuid : %d\n", msg->cpuid);
_info("modid : %d\n", msg->modid);
_info("id : %d\n", msg->u.api.id);
_info("arg : %08x\n", msg->u.api.arg);
_info("mbxid : %d\n", msg->u.api.mbxid);
_info("flagid: %d\n", msg->u.api.flagid);
_info("flagbitno: %d\n", msg->u.api.flagbitno);
}
# define fainfo(x, ...) _info(x, ##__VA_ARGS__)
#else
# define dump_farapi_message(x)
# define fainfo(x, ...)
#endif
static int cxd56_sendmsg(int cpuid, int protoid, int msgtype, uint16_t pdata,
uint32_t data)
{
iccmsg_t msg;
msg.cpuid = cpuid;
msg.msgid = msgtype << 4;
msg.protodata = pdata;
msg.data = data;
return cxd56_iccsend(protoid, &msg, 0);
}
static int cxd56_farapidonehandler(int cpuid, int protoid,
uint32_t pdata, uint32_t data,
FAR void *userdata)
{
/* Receive event flag message as Far API done.
* We need only far API done event.
*/
if (protoid == CXD56_PROTO_FLG && (pdata & 0xf) == 0x7)
{
/* Send event flag response */
cxd56_sendmsg(cpuid, CXD56_PROTO_FLG, 5, pdata & 0xff00, 0);
sem_post(&g_farwait);
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
__attribute__((used))
void farapi_main(int id, void *arg, struct modulelist_s *mlist)
{
struct farmsg_s msg;
struct apimsg_s *api;
int ret;
#ifdef CONFIG_CXD56_GNSS_HOT_SLEEP
uint32_t gnscken;
if (mlist->cpuno == GPS_CPU_ID)
{
gnscken = getreg32(CXD56_TOPREG_GNSDSP_CKEN);
if (((gnscken & GNSDSP_CKEN_P1) != GNSDSP_CKEN_P1) &&
((gnscken & GNSDSP_CKEN_COP) != GNSDSP_CKEN_COP))
{
PM_WakeUpCpu(GPS_CPU_ID);
}
}
#endif
farapi_semtake(&g_farlock);
api = &msg.u.api;
msg.cpuid = getreg32(CPU_ID);
msg.modid = mlist - (struct modulelist_s *)&Image$$MODLIST$$Base;
api->id = id;
api->arg = arg;
api->mbxid = mlist->mbxid;
api->flagid = (msg.cpuid + 1) << 8 | 7; /* 7 is a magic. not zero */
api->flagbitno = 0; /* ignore */
dump_farapi_message(&msg);
/* Send request by mailbox protocol */
ret = cxd56_sendmsg(mlist->cpuno, CXD56_PROTO_MBX, 4, 1 << 8 | 1,
(uint32_t)(uintptr_t)&msg);
if (ret)
{
_err("Failed far api push\n");
goto err;
}
/* Suppress hot sleep until Far API done */
up_pm_acquire_wakelock(&g_wlock);
/* Wait event flag message as Far API done */
farapi_semtake(&g_farwait);
/* Permit hot sleep with Far API done */
up_pm_release_wakelock(&g_wlock);
dump_farapi_message(&msg);
err:
sem_post(&g_farlock);
}
void cxd56_farapiinitialize(void)
{
#ifdef CONFIG_CXD56_FARAPI_VERSION_CHECK
if (GET_SYSFW_VERSION_BUILD() < FARAPISTUB_VERSION)
{
_alert("Mismatched version: loader(%d) != Self(%d)\n",
GET_SYSFW_VERSION_BUILD(), FARAPISTUB_VERSION);
_alert("Please update loader and gnssfw firmwares!!\n");
# ifdef CONFIG_CXD56_FARAPI_VERSION_FAILED_PANIC
PANIC();
# endif
}
#endif
sem_init(&g_farlock, 0, 1);
sem_init(&g_farwait, 0, 0);
cxd56_iccinit(CXD56_PROTO_MBX);
cxd56_iccinit(CXD56_PROTO_FLG);
/* Setup CPU FIFO interrupt for SYS and GNSS */
cxd56_iccregisterhandler(CXD56_PROTO_MBX, cxd56_farapidonehandler, NULL);
cxd56_iccregisterhandler(CXD56_PROTO_FLG, cxd56_farapidonehandler, NULL);
}
arch/arm/src/cxd56xx/cxd56_farapi.h
+56
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/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_farapi.h
*
* Copyright 2018 Sony Semiconductor Solutions Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPI_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPI_H
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif /* ARCH_ARM_SRC_CXD56XX_CXD56_FARAPI_H */
void cxd56_farapiinitialize(void);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPI_H */
arch/arm/src/cxd56xx/cxd56_farapistub.S
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