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https://github.com/apache/nuttx.git
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arch/stm32: split common Kconfig into per-peripheral files
STM32 common Kconfig into smaller files. Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
Xiang Xiao
+122
-9485
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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#
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# STM32 common BLE options.
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#
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if STM32_BLE
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config STM32_BLE_C2HOST
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bool "Enable CPU2 HOST stack"
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default n
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---help---
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The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and
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control it using vendor ACL protocol. However, it is not expected to enable
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this option in the current implementation.
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config STM32_BLE_MAX_CONN
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int "Maximum BLE simultaneous connections"
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range 1 8
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default 2
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config STM32_BLE_GATT_MAX_ATTR_NUM
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int "GATT attributes max count"
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range 9 255
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default 64
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config STM32_BLE_GATT_MAX_SVC_NUM
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int "GATT services max count"
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range 2 64
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default 8
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config STM32_BLE_GATT_ATTR_BUF_SIZE
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int "GATT attributes storage buf size"
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default 1344
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---help---
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Size of the storage area for attribute values. Hardcoded in CPU2 firmware.
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config STM32_BLE_DLE
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bool "Support Data Length Extension (DLE)"
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default y
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config STM32_BLE_MAX_ATT_MTU
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int "Maximum supported attribute MTU"
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range 23 512
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default 156
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config STM32_BLE_SLAVE_SCA
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int "Sleep clock accuracy in slave mode [PPM]"
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default 500
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---help---
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Sleep clock accuracy (ppm value) in slave mode.
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choice
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prompt "Sleep clock accuracy in master mode"
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default STM32_BLE_MASTER_SCA_0
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---help---
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Sleep clock accuracy in master mode.
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config STM32_BLE_MASTER_SCA_0
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bool "251-500 ppm"
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config STM32_BLE_MASTER_SCA_1
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bool "151-250 ppm"
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config STM32_BLE_MASTER_SCA_2
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bool "101-150 ppm"
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config STM32_BLE_MASTER_SCA_3
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bool "76-100 ppm"
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config STM32_BLE_MASTER_SCA_4
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bool "51-75 ppm"
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config STM32_BLE_MASTER_SCA_5
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bool "31-50 ppm"
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config STM32_BLE_MASTER_SCA_6
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bool "21-30 ppm"
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config STM32_BLE_MASTER_SCA_7
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bool "0-20 ppm"
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endchoice # Sleep clock accuracy in master mode
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config STM32_BLE_MASTER_SCA
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int
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default 7 if STM32_BLE_MASTER_SCA_7
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default 6 if STM32_BLE_MASTER_SCA_6
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default 5 if STM32_BLE_MASTER_SCA_5
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default 4 if STM32_BLE_MASTER_SCA_4
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default 3 if STM32_BLE_MASTER_SCA_3
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default 2 if STM32_BLE_MASTER_SCA_2
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default 1 if STM32_BLE_MASTER_SCA_1
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default 0
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choice
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prompt "Low speed clock source"
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default STM32_BLE_LS_CLK_SRC_LSE
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---help---
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Low speed 32 kHz clock source.
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config STM32_BLE_LS_CLK_SRC_LSE
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bool "LSE"
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config STM32_BLE_LS_CLK_SRC_HSE
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bool "HSE"
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endchoice # Low speed clock source
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config STM32_BLE_LS_CLK_SRC
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int
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default 1 if STM32_BLE_LS_CLKSRC_HSE
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default 0
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config STM32_BLE_MAX_CONN_EVT_LENGTH
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hex "Max connection event length"
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default 0xffffffff
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---help---
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Maximum duration of a slave connection event in units of 625/256us (~2.44us).
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config STM32_BLE_HSE_STARTUP
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hex "HSE startup time"
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default 0x148
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---help---
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HSE startup time in units of 625/256us (~2.44us).
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config STM32_BLE_VITERBI
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bool "Enable Viterbi algorithm"
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default y
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---help---
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Enable Viterbi algorithm implementation
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config STM32_BLE_MAX_INITOR_COC_NUM
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int "Max number of connection-oriented channels"
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range 0 64
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default 32
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---help---
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Maximum number of connection-oriented channels in initiator mode.
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config STM32_BLE_SVC_CHANGED_CHAR
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bool "Enable service changed characteristic"
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default n
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config STM32_BLE_WRITABLE_DEVICE_NAME
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bool "Writable device name"
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default y
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config STM32_BLE_CHAN_SEL_ALG2
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bool "Enable channel selection algorithm 2"
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default n
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choice
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prompt "Power class"
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default STM32_BLE_POWER_CLASS_2_3
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config STM32_BLE_POWER_CLASS_2_3
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bool "Power Class 2-3"
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config STM32_BLE_POWER_CLASS_1
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bool "Power Class 1"
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endchoice # Power class
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config STM32_BLE_MIN_TX_POWER
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int "Minimum transmit power [dBm]"
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range -127 20
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default 0
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config STM32_BLE_MAX_TX_POWER
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int "Maximum transmit power [dBm]"
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range -127 20
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default 0
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choice
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prompt "AGC RSSI model"
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default STM32_BLE_AGC_RSSI_LEGACY
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config STM32_BLE_AGC_RSSI_LEGACY
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bool "AGC RSSI Legacy"
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config STM32_BLE_AGC_RSSI_IMPROVED
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bool "AGC RSSI Improved"
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endchoice # AGC RSSI model
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config STM32_BLE_ADVERTISING
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bool "Support advertising"
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default y
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config STM32_BLE_SCANNING
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bool "Support scanning"
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default y
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config STM32_BLE_LE_2M_PHY
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bool "Support LE 2M PHY"
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default y
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config STM32_BLE_LE_CODED_PHY
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bool "Support LE Coded PHY"
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default STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55
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depends on STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55
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config STM32_BLE_FICR_STATIC_ADDR
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bool "Configure factory generated static random address"
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default n
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config STM32_BLE_PUB_ADDR
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hex "Configure BT public address"
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default 0x0000000000
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endif # STM32_BLE
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if STM32_MBOX
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config STM32_MBOX_TX_CMD_QUEUE_LEN
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int "Mailbox TX command queue length"
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default 2
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config STM32_MBOX_RX_EVT_QUEUE_LEN
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int "Mailbox RX event queue length"
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default 5
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endif # STM32_MBOX
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@@ -0,0 +1,238 @@
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#
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# STM32 cache configuration options.
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#
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menu "ICACHE Configuration"
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depends on STM32_ICACHE
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config STM32_ICACHE_MONITOR_EN
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bool "Enable ICACHE Hit/Miss Counters"
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default n
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config STM32_ICACHE_DIRECT
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bool "Enable 1-Way Direct Mapped Cache (N-Way = default)"
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default n
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menu "ICACHE Interrupt Configuration"
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depends on STM32_ICACHE
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config STM32_ICACHE_INV_INT
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bool "Enable interrupts on full invalidation completion."
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default n
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config STM32_ICACHE_ERR_INT
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bool "Enable interrupts on occurrences of cache errors."
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default n
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endmenu # ICACHE Interrupt Configuration
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menu "ICACHE Region Configuration"
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depends on STM32_ICACHE
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config STM32_ICACHE_REGION0
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bool "Enable Configuration of ICACHE Region 0"
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default n
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config STM32_ICACHE_REGION1
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bool "Enable Configuration of ICACHE Region 1"
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default n
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config STM32_ICACHE_REGION2
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bool "Enable Configuration of ICACHE Region 2"
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default n
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config STM32_ICACHE_REGION3
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bool "Enable Configuration of ICACHE Region 3"
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default n
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menu "Region 0 Configuration"
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depends on STM32_ICACHE_REGION0 && STM32_HAVE_ICACHE_REMAP
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config STM32_ICACHE_REGION0_BADDR
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hex "ICACHE Region 0 Base Address Bits [28:21]"
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default 0
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range 0 255
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depends on STM32_ICACHE_REGION0
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---help---
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Set bits [28:21] of the base address for ICACHE Region 0.
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config STM32_ICACHE_REGION0_RSIZE
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int "ICACHE Region 0 Size"
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default 1
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range 1 7
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depends on STM32_ICACHE_REGION0
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---help---
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Set the size of Region 0.
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1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes,
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5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes.
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config STM32_ICACHE_REGION0_REMAPADDR
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hex "ICACHE Region 0 Remap Address Bits [31:21]"
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default 0
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range 0 2047
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depends on STM32_ICACHE_REGION0
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---help---
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Set bits [31:21] of ICACHE Region 0 Remap Address..
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config STM32_ICACHE_REGION0_MSTSEL
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int "ICACHE Region 0 Master Select (0 or 1)"
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default 0
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range 0 1
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depends on STM32_ICACHE_REGION0
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---help---
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Select ICACHE Region 0 Master 1 (0) or Master 2 (1).
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config STM32_ICACHE_REGION0_HBURST
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int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)"
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default 0
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range 0 1
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depends on STM32_ICACHE_REGION0
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---help---
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Select Wrap (0) or Increment (1) Output Burst Type.
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endmenu # Region 0 Configuration
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menu "Region 1 Configuration"
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depends on STM32_ICACHE_REGION1 && STM32_HAVE_ICACHE_REMAP
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config STM32_ICACHE_REGION1_BADDR
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hex "ICACHE Region 1 Base Address Bits [28:21]"
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default 0
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range 0 255
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depends on STM32_ICACHE_REGION1
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---help---
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Set bits [28:21] of the base address for ICACHE Region 1.
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config STM32_ICACHE_REGION1_RSIZE
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int "ICACHE Region 1 Size"
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default 1
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range 1 7
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depends on STM32_ICACHE_REGION1
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---help---
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Set the size of Region 1.
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1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes,
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5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes.
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config STM32_ICACHE_REGION1_REMAPADDR
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hex "ICACHE Region 1 Remap Address Bits [31:21]"
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default 0
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range 0 2047
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depends on STM32_ICACHE_REGION1
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---help---
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Set bits [31:21] of ICACHE Region 1 Remap Address..
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config STM32_ICACHE_REGION1_MSTSEL
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int "ICACHE Region 1 Master Select (0 or 1)"
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default 0
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range 0 1
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depends on STM32_ICACHE_REGION1
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---help---
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Select ICACHE Region 1 Master 1 (0) or Master 2 (1).
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config STM32_ICACHE_REGION1_HBURST
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int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)"
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default 0
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range 0 1
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depends on STM32_ICACHE_REGION1
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---help---
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Select Wrap (0) or Increment (1) Output Burst Type.
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endmenu # Region 1 Configuration
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menu "Region 2 Configuration"
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depends on STM32_ICACHE_REGION2 && STM32_HAVE_ICACHE_REMAP
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config STM32_ICACHE_REGION2_BADDR
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hex "ICACHE Region 2 Base Address Bits [28:21]"
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default 0
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range 0 255
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depends on STM32_ICACHE_REGION2
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---help---
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Set bits [28:21] of the base address for ICACHE Region 2.
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config STM32_ICACHE_REGION2_RSIZE
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int "ICACHE Region 2 Size"
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default 1
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range 1 7
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depends on STM32_ICACHE_REGION2
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---help---
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Set the size of Region 2.
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1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes,
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5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes.
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config STM32_ICACHE_REGION2_REMAPADDR
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hex "ICACHE Region 2 Remap Address Bits [31:21]"
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default 0
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range 0 2047
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depends on STM32_ICACHE_REGION2
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---help---
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Set bits [31:21] of ICACHE Region 2 Remap Address..
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config STM32_ICACHE_REGION2_MSTSEL
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int "ICACHE Region 2 Master Select (0 or 1)"
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default 0
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range 0 1
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depends on STM32_ICACHE_REGION2
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---help---
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Select ICACHE Region 2 Master 1 (0) or Master 2 (1).
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config STM32_ICACHE_REGION2_HBURST
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int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)"
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default 0
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range 0 1
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depends on STM32_ICACHE_REGION2
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---help---
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Select Wrap (0) or Increment (1) Output Burst Type.
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endmenu # Region 2 Configuration
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menu "Region 3 Configuration"
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depends on STM32_ICACHE_REGION3 && STM32_HAVE_ICACHE_REMAP
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config STM32_ICACHE_REGION3_BADDR
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hex "ICACHE Region 3 Base Address Bits [28:21]"
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default 0
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range 0 255
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depends on STM32_ICACHE_REGION3
|
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---help---
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Set bits [28:21] of the base address for ICACHE Region 3.
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||||
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config STM32_ICACHE_REGION3_RSIZE
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int "ICACHE Region 3 Size"
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default 1
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range 1 7
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depends on STM32_ICACHE_REGION3
|
||||
---help---
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Set the size of Region 3.
|
||||
1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes,
|
||||
5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes.
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||||
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config STM32_ICACHE_REGION3_REMAPADDR
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||||
hex "ICACHE Region 3 Remap Address Bits [31:21]"
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||||
default 0
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||||
range 0 2047
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||||
depends on STM32_ICACHE_REGION3
|
||||
---help---
|
||||
Set bits [31:21] of ICACHE Region 3 Remap Address..
|
||||
|
||||
config STM32_ICACHE_REGION3_MSTSEL
|
||||
int "ICACHE Region 3 Master Select (0 or 1)"
|
||||
default 0
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||||
range 0 1
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||||
depends on STM32_ICACHE_REGION3
|
||||
---help---
|
||||
Select ICACHE Region 3 Master 1 (0) or Master 2 (1).
|
||||
|
||||
config STM32_ICACHE_REGION3_HBURST
|
||||
int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)"
|
||||
default 0
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||||
range 0 1
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||||
depends on STM32_ICACHE_REGION3
|
||||
---help---
|
||||
Select Wrap (0) or Increment (1) Output Burst Type.
|
||||
|
||||
endmenu # Region 3 Configuration
|
||||
|
||||
endmenu # ICACHE Region Configuration
|
||||
|
||||
endmenu # ICACHE Configuration
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@@ -0,0 +1,58 @@
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#
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# STM32 CAN configuration options.
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||||
#
|
||||
|
||||
choice
|
||||
prompt "CAN character driver or SocketCAN support"
|
||||
default STM32_CAN_CHARDRIVER
|
||||
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||||
config STM32_CAN_CHARDRIVER
|
||||
bool "STM32 CAN character driver support"
|
||||
select ARCH_HAVE_CAN_ERRORS
|
||||
select CAN
|
||||
|
||||
config STM32_CAN_SOCKET
|
||||
bool "STM32 CAN SocketCAN support"
|
||||
select NET_CAN_HAVE_ERRORS
|
||||
|
||||
endchoice # CAN character driver or SocketCAN support
|
||||
|
||||
config STM32_CAN1_BAUD
|
||||
int "CAN1 BAUD"
|
||||
depends on STM32_CAN1
|
||||
default 250000
|
||||
---help---
|
||||
CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined.
|
||||
|
||||
config STM32_CAN2_BAUD
|
||||
int "CAN2 BAUD"
|
||||
depends on STM32_CAN2
|
||||
default 250000
|
||||
---help---
|
||||
CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined.
|
||||
|
||||
config STM32_CAN3_BAUD
|
||||
int "CAN3 BAUD"
|
||||
depends on STM32_CAN3
|
||||
default 250000
|
||||
---help---
|
||||
CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined.
|
||||
|
||||
config STM32_CAN_TSEG1
|
||||
int "TSEG1 quanta"
|
||||
default 6
|
||||
---help---
|
||||
The number of CAN time quanta in segment 1. Default: 6
|
||||
|
||||
config STM32_CAN_TSEG2
|
||||
int "TSEG2 quanta"
|
||||
default 7
|
||||
---help---
|
||||
The number of CAN time quanta in segment 2. Default: 7
|
||||
|
||||
config STM32_CAN_REGDEBUG
|
||||
bool "CAN Register level debug"
|
||||
depends on DEBUG_CAN_INFO
|
||||
---help---
|
||||
Output detailed register-level CAN device debug information.
|
||||
Requires also CONFIG_DEBUG_CAN_INFO.
|
||||
@@ -0,0 +1,387 @@
|
||||
#
|
||||
# STM32 analog comparator (COMP) configuration options.
|
||||
#
|
||||
|
||||
# COMP supported only for M3M4 for now
|
||||
|
||||
if STM32_HAVE_IP_COMP_M3M4_V2
|
||||
|
||||
if STM32_COMP1
|
||||
|
||||
config STM32_COMP1_OUT
|
||||
bool "COMP1 GPIO Output"
|
||||
default n
|
||||
---help---
|
||||
Enables COMP1 output.
|
||||
|
||||
config STM32_COMP1_INM
|
||||
int "COMP1 inverting input assignment"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP1 inverting input pin.
|
||||
|
||||
config STM32_COMP1_INP
|
||||
int "COMP1 non-inverting input assignment"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP1 non-inverting input pin.
|
||||
|
||||
config STM32_COMP1_POL
|
||||
int "COMP1 polarity"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP1 output polarity.
|
||||
|
||||
config STM32_COMP1_HYST
|
||||
int "COMP1 hysteresis"
|
||||
depends on STM32_STM32G4XXX
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the hysteresis of the COMP1.
|
||||
|
||||
config STM32_COMP1_BLANKSEL
|
||||
int "COMP1 blanking signal select"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the blanking signal for comparator COMP1.
|
||||
|
||||
config STM32_COMP1_LOCK
|
||||
int "COMP1 COMP_CxCSR register lock"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Locks COMP_CxCSR register.
|
||||
0 - Unlock 1 - Lock
|
||||
|
||||
endif # STM32_COMP1
|
||||
|
||||
if STM32_COMP2
|
||||
|
||||
config STM32_COMP2_OUT
|
||||
bool "COMP2 GPIO Output"
|
||||
default n
|
||||
---help---
|
||||
Enables COMP2 output.
|
||||
|
||||
config STM32_COMP2_INM
|
||||
int "COMP2 inverting input assignment"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP2 inverting input pin.
|
||||
|
||||
config STM32_COMP2_INP
|
||||
int "COMP2 non-inverting input assignment"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP2 non-inverting input pin.
|
||||
|
||||
config STM32_COMP2_POL
|
||||
int "COMP2 polarity"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP2 output polarity.
|
||||
|
||||
config STM32_COMP2_HYST
|
||||
int "COMP2 hysteresis"
|
||||
depends on STM32_STM32G4XXX
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the hysteresis of the COMP2.
|
||||
|
||||
config STM32_COMP2_BLANKSEL
|
||||
int "COMP2 blanking signal select"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the blanking signal for comparator COMP2.
|
||||
|
||||
config STM32_COMP2_LOCK
|
||||
int "COMP2 COMP_CxCSR register lock"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Locks COMP_CxCSR register.
|
||||
0 - Unlock 1 - Lock
|
||||
|
||||
endif # STM32_COMP2
|
||||
|
||||
if STM32_COMP3
|
||||
|
||||
config STM32_COMP3_OUT
|
||||
bool "COMP3 GPIO Output"
|
||||
default n
|
||||
---help---
|
||||
Enables COMP3 output.
|
||||
|
||||
config STM32_COMP3_INM
|
||||
int "COMP3 inverting input assignment"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP3 inverting input pin.
|
||||
|
||||
config STM32_COMP3_INP
|
||||
int "COMP3 non-inverting input assignment"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP3 non-inverting input pin.
|
||||
|
||||
config STM32_COMP3_POL
|
||||
int "COMP3 polarity"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP3 output polarity.
|
||||
|
||||
config STM32_COMP3_HYST
|
||||
int "COMP3 hysteresis"
|
||||
depends on STM32_STM32G4XXX
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the hysteresis of the COMP3.
|
||||
|
||||
config STM32_COMP3_BLANKSEL
|
||||
int "COMP3 blanking signal select"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the blanking signal for comparator COMP3.
|
||||
|
||||
config STM32_COMP3_LOCK
|
||||
int "COMP3 COMP_CxCSR register lock"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Locks COMP_CxCSR register.
|
||||
0 - Unlock 1 - Lock
|
||||
|
||||
endif # STM32_COMP3
|
||||
|
||||
if STM32_COMP4
|
||||
|
||||
config STM32_COMP4_OUT
|
||||
bool "COMP4 GPIO Output"
|
||||
default n
|
||||
---help---
|
||||
Enables COMP4 output.
|
||||
|
||||
config STM32_COMP4_INM
|
||||
int "COMP4 inverting input assignment"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP4 inverting input pin.
|
||||
|
||||
config STM32_COMP4_INP
|
||||
int "COMP4 non-inverting input assignment"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP4 non-inverting input pin.
|
||||
|
||||
config STM32_COMP4_POL
|
||||
int "COMP4 polarity"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP4 output polarity.
|
||||
|
||||
config STM32_COMP4_HYST
|
||||
int "COMP4 hysteresis"
|
||||
depends on STM32_STM32G4XXX
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the hysteresis of the COMP4.
|
||||
|
||||
config STM32_COMP4_BLANKSEL
|
||||
int "COMP4 blanking signal select"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the blanking signal for comparator COMP4.
|
||||
|
||||
config STM32_COMP4_LOCK
|
||||
int "COMP4 COMP_CxCSR register lock"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Locks COMP_CxCSR register.
|
||||
0 - Unlock 1 - Lock
|
||||
|
||||
endif # STM32_COMP4
|
||||
|
||||
if STM32_COMP5
|
||||
|
||||
config STM32_COMP5_OUT
|
||||
bool "COMP5 GPIO Output"
|
||||
default n
|
||||
---help---
|
||||
Enables COMP5 output.
|
||||
|
||||
config STM32_COMP5_INM
|
||||
int "COMP5 inverting input assignment"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP5 inverting input pin.
|
||||
|
||||
config STM32_COMP5_INP
|
||||
int "COMP5 non-inverting input assignment"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP5 non-inverting input pin.
|
||||
|
||||
config STM32_COMP5_POL
|
||||
int "COMP5 polarity"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP5 output polarity.
|
||||
|
||||
config STM32_COMP5_HYST
|
||||
int "COMP5 hysteresis"
|
||||
depends on STM32_STM32G4XXX
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the hysteresis of the COMP5.
|
||||
|
||||
config STM32_COMP5_BLANKSEL
|
||||
int "COMP5 blanking signal select"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the blanking signal for comparator COMP5.
|
||||
|
||||
config STM32_COMP5_LOCK
|
||||
int "COMP5 COMP_CxCSR register lock"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Locks COMP_CxCSR register.
|
||||
0 - Unlock 1 - Lock
|
||||
|
||||
endif # STM32_COMP5
|
||||
|
||||
if STM32_COMP6
|
||||
|
||||
config STM32_COMP6_OUT
|
||||
bool "COMP6 GPIO Output"
|
||||
default n
|
||||
---help---
|
||||
Enables COMP6 output.
|
||||
|
||||
config STM32_COMP6_INM
|
||||
int "COMP6 inverting input assignment"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP6 inverting input pin.
|
||||
|
||||
config STM32_COMP6_INP
|
||||
int "COMP6 non-inverting input assignment"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP6 non-inverting input pin.
|
||||
|
||||
config STM32_COMP6_POL
|
||||
int "COMP6 polarity"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP6 output polarity.
|
||||
|
||||
config STM32_COMP6_HYST
|
||||
int "COMP6 hysteresis"
|
||||
depends on STM32_STM32G4XXX
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the hysteresis of the COMP6.
|
||||
|
||||
config STM32_COMP6_BLANKSEL
|
||||
int "COMP6 blanking signal select"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the blanking signal for comparator COMP6.
|
||||
|
||||
config STM32_COMP6_LOCK
|
||||
int "COMP6 COMP_CxCSR register lock"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Locks COMP_CxCSR register.
|
||||
0 - Unlock 1 - Lock
|
||||
|
||||
endif # STM32_COMP6
|
||||
|
||||
if STM32_COMP7
|
||||
|
||||
config STM32_COMP7_OUT
|
||||
bool "COMP7 GPIO Output"
|
||||
default n
|
||||
---help---
|
||||
Enables COMP7 output.
|
||||
|
||||
config STM32_COMP7_INM
|
||||
int "COMP7 inverting input assignment"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP7 inverting input pin.
|
||||
|
||||
config STM32_COMP7_INP
|
||||
int "COMP7 non-inverting input assignment"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP7 non-inverting input pin.
|
||||
|
||||
config STM32_COMP7_POL
|
||||
int "COMP7 polarity"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Selects COMP7 output polarity.
|
||||
|
||||
config STM32_COMP7_HYST
|
||||
int "COMP7 hysteresis"
|
||||
depends on STM32_STM32G4XXX
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the hysteresis of the COMP7.
|
||||
|
||||
config STM32_COMP7_BLANKSEL
|
||||
int "COMP7 blanking signal select"
|
||||
range 0 7
|
||||
default 0
|
||||
---help---
|
||||
Selects the blanking signal for comparator COMP7.
|
||||
|
||||
config STM32_COMP7_LOCK
|
||||
int "COMP7 COMP_CxCSR register lock"
|
||||
range 0 1
|
||||
default 0
|
||||
---help---
|
||||
Locks COMP_CxCSR register.
|
||||
0 - Unlock 1 - Lock
|
||||
|
||||
endif # STM32_COMP7
|
||||
|
||||
endif # STM32_HAVE_IP_COMP_M3M4_V2
|
||||
@@ -0,0 +1,363 @@
|
||||
#
|
||||
# STM32 DAC configuration options.
|
||||
#
|
||||
|
||||
config STM32_DAC_LL_OPS
|
||||
bool "DAC low-level operations"
|
||||
default n
|
||||
---help---
|
||||
Enable low-level DAC ops.
|
||||
|
||||
config STM32_DAC1_DMA
|
||||
bool "DAC1 DMA"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1
|
||||
---help---
|
||||
If DMA is selected, then a timer and output frequency must also be
|
||||
provided to support the DMA transfer. The DMA transfer could be
|
||||
supported by an EXTI trigger, but this feature is not currently
|
||||
supported by the driver.
|
||||
|
||||
config STM32_DAC1_TIMER
|
||||
int "DAC1 timer"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA
|
||||
range 2 8
|
||||
|
||||
config STM32_DAC1_TIMER_FREQUENCY
|
||||
int "DAC1 timer frequency"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA
|
||||
default 100
|
||||
---help---
|
||||
DAC1 output frequency. Default: 100Hz
|
||||
|
||||
config STM32_DAC1_DMA_BUFFER_SIZE
|
||||
int "DAC1 DMA buffer size"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA
|
||||
default 1
|
||||
|
||||
config STM32_DAC2_DMA
|
||||
bool "DAC2 DMA"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2
|
||||
---help---
|
||||
If DMA is selected, then a timer and output frequency must also be
|
||||
provided to support the DMA transfer. The DMA transfer could be
|
||||
supported by an EXTI trigger, but this feature is not currently
|
||||
supported by the driver.
|
||||
|
||||
config STM32_DAC2_TIMER
|
||||
int "DAC2 timer"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA
|
||||
default 0
|
||||
range 2 8
|
||||
|
||||
config STM32_DAC2_TIMER_FREQUENCY
|
||||
int "DAC2 timer frequency"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA
|
||||
default 100
|
||||
---help---
|
||||
DAC2 output frequency. Default: 100Hz
|
||||
|
||||
config STM32_DAC2_DMA_BUFFER_SIZE
|
||||
int "DAC2 DMA buffer size"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA
|
||||
default 1
|
||||
|
||||
menu "DAC Configuration"
|
||||
depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4
|
||||
|
||||
config STM32_DAC1CH1_MODE
|
||||
int "DAC1CH1 channel mode"
|
||||
depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_M3M4_V2
|
||||
default 0
|
||||
range 0 7
|
||||
---help---
|
||||
– DAC channel in Normal mode
|
||||
0: DAC channel is connected to external pin with Buffer enabled
|
||||
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
|
||||
2: DAC channel2 is connected to external pin with buffer disabled
|
||||
3: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
- DAC channel in Sample and hold mode
|
||||
4: DAC channel is connected to external pin with Buffer enabled
|
||||
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
|
||||
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
|
||||
7: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
|
||||
config STM32_DAC1CH1_DMA
|
||||
bool "DAC1CH1 DMA"
|
||||
depends on STM32_DAC1CH1
|
||||
default n
|
||||
---help---
|
||||
If DMA is selected, then a timer and output frequency must also be
|
||||
provided to support the DMA transfer. The DMA transfer could be
|
||||
supported by and EXTI trigger, but this feature is not currently
|
||||
supported by the driver.
|
||||
|
||||
if STM32_DAC1CH1_DMA
|
||||
|
||||
config STM32_DAC1CH1_DMA_BUFFER_SIZE
|
||||
int "DAC1CH1 DMA buffer size"
|
||||
default 256
|
||||
|
||||
config STM32_DAC1CH1_DMA_EXTERNAL
|
||||
bool "DAC1CH1 DMA External Trigger"
|
||||
default n
|
||||
|
||||
if STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC1CH1_HRTIM_TRG1
|
||||
bool "DAC1CH1 HRTIM Trigger 1"
|
||||
default n
|
||||
|
||||
config STM32_DAC1CH1_HRTIM_TRG2
|
||||
bool "DAC1CH1 HRTIM Trigger 2"
|
||||
default n
|
||||
|
||||
endif # STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC1CH1_TIMER
|
||||
int "DAC1CH1 timer"
|
||||
depends on !STM32_DAC1CH1_DMA_EXTERNAL
|
||||
range 2 8
|
||||
|
||||
config STM32_DAC1CH1_TIMER_FREQUENCY
|
||||
int "DAC1CH1 timer frequency"
|
||||
depends on !STM32_DAC1CH1_DMA_EXTERNAL
|
||||
default 0
|
||||
|
||||
endif
|
||||
|
||||
config STM32_DAC1CH2_MODE
|
||||
int "DAC1CH2 channel mode"
|
||||
depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_M3M4_V2
|
||||
default 0
|
||||
range 0 7
|
||||
---help---
|
||||
– DAC channel in Normal mode
|
||||
0: DAC channel is connected to external pin with Buffer enabled
|
||||
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
|
||||
2: DAC channel2 is connected to external pin with buffer disabled
|
||||
3: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
- DAC channel in Sample and hold mode
|
||||
4: DAC channel is connected to external pin with Buffer enabled
|
||||
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
|
||||
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
|
||||
7: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
|
||||
config STM32_DAC1CH2_DMA
|
||||
bool "DAC1CH2 DMA"
|
||||
depends on STM32_DAC1CH2
|
||||
default n
|
||||
---help---
|
||||
If DMA is selected, then a timer and output frequency must also be
|
||||
provided to support the DMA transfer. The DMA transfer could be
|
||||
supported by and EXTI trigger, but this feature is not currently
|
||||
supported by the driver.
|
||||
|
||||
if STM32_DAC1CH2_DMA
|
||||
|
||||
config STM32_DAC1CH2_DMA_BUFFER_SIZE
|
||||
int "DAC1CH2 DMA buffer size"
|
||||
default 256
|
||||
|
||||
config STM32_DAC1CH2_DMA_EXTERNAL
|
||||
bool "DAC1CH2 DMA External Trigger"
|
||||
default n
|
||||
|
||||
if STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC1CH2_HRTIM_TRG1
|
||||
bool "DAC1CH2 HRTIM Trigger 1"
|
||||
default n
|
||||
|
||||
config STM32_DAC1CH2_HRTIM_TRG2
|
||||
bool "DAC1CH2 HRTIM Trigger 2"
|
||||
default n
|
||||
|
||||
endif # STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC1CH2_TIMER
|
||||
int "DAC1CH2 timer"
|
||||
depends on !STM32_DAC1CH2_DMA_EXTERNAL
|
||||
range 2 8
|
||||
|
||||
config STM32_DAC1CH2_TIMER_FREQUENCY
|
||||
int "DAC1CH2 timer frequency"
|
||||
depends on !STM32_DAC1CH2_DMA_EXTERNAL
|
||||
default 0
|
||||
|
||||
endif
|
||||
|
||||
config STM32_DAC2CH1_MODE
|
||||
int "DAC2CH1 channel mode"
|
||||
depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_M3M4_V2
|
||||
default 0
|
||||
range 0 7
|
||||
---help---
|
||||
– DAC channel in Normal mode
|
||||
0: DAC channel is connected to external pin with Buffer enabled
|
||||
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
|
||||
2: DAC channel2 is connected to external pin with buffer disabled
|
||||
3: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
- DAC channel in Sample and hold mode
|
||||
4: DAC channel is connected to external pin with Buffer enabled
|
||||
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
|
||||
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
|
||||
7: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
|
||||
config STM32_DAC2CH1_DMA
|
||||
bool "DAC2CH1 DMA"
|
||||
depends on STM32_DAC2CH1
|
||||
default n
|
||||
---help---
|
||||
If DMA is selected, then a timer and output frequency must also be
|
||||
provided to support the DMA transfer. The DMA transfer could be
|
||||
supported by and EXTI trigger, but this feature is not currently
|
||||
supported by the driver.
|
||||
|
||||
if STM32_DAC2CH1_DMA
|
||||
|
||||
config STM32_DAC2CH1_DMA_BUFFER_SIZE
|
||||
int "DAC2CH1 DMA buffer size"
|
||||
default 256
|
||||
|
||||
config STM32_DAC2CH1_DMA_EXTERNAL
|
||||
bool "DAC2CH1 DMA External Trigger"
|
||||
default n
|
||||
|
||||
if STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC2CH1_HRTIM_TRG3
|
||||
bool "DAC2CH1 HRTIM Trigger 3"
|
||||
default n
|
||||
|
||||
endif # STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC2CH1_TIMER
|
||||
int "DAC2CH1 timer"
|
||||
depends on !STM32_DAC2CH1_DMA_EXTERNAL
|
||||
default 0
|
||||
range 2 8
|
||||
|
||||
config STM32_DAC2CH1_TIMER_FREQUENCY
|
||||
int "DAC2CH1 timer frequency"
|
||||
depends on !STM32_DAC2CH1_DMA_EXTERNAL
|
||||
default 0
|
||||
|
||||
endif
|
||||
|
||||
config STM32_DAC3CH1_MODE
|
||||
int "DAC3CH1 channel mode"
|
||||
depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_M3M4_V2
|
||||
default 0
|
||||
range 0 7
|
||||
---help---
|
||||
– DAC channel in Normal mode
|
||||
0: DAC channel is connected to external pin with Buffer enabled
|
||||
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
|
||||
2: DAC channel is connected to external pin with buffer disabled
|
||||
3: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
- DAC channel in Sample and hold mode
|
||||
4: DAC channel is connected to external pin with Buffer enabled
|
||||
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
|
||||
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
|
||||
7: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
|
||||
config STM32_DAC3CH1_DMA
|
||||
bool "DAC3CH1 DMA"
|
||||
depends on STM32_DAC3CH1
|
||||
default n
|
||||
---help---
|
||||
If DMA is selected, then a timer and output frequency must also be
|
||||
provided to support the DMA transfer. The DMA transfer could be
|
||||
supported by an EXTI trigger, but this feature is not currently
|
||||
supported by the driver.
|
||||
|
||||
if STM32_DAC3CH1_DMA
|
||||
|
||||
config STM32_DAC3CH1_DMA_BUFFER_SIZE
|
||||
int "DAC3CH1 DMA buffer size"
|
||||
default 256
|
||||
|
||||
config STM32_DAC3CH1_DMA_EXTERNAL
|
||||
bool "DAC3CH1 DMA External Trigger"
|
||||
default n
|
||||
|
||||
if STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC3CH1_HRTIM_TRG3
|
||||
bool "DAC3CH1 HRTIM Trigger 3"
|
||||
default n
|
||||
|
||||
endif # STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC3CH1_TIMER
|
||||
int "DAC3CH1 timer"
|
||||
depends on !STM32_DAC3CH1_DMA_EXTERNAL
|
||||
default 0
|
||||
range 2 8
|
||||
|
||||
config STM32_DAC3CH1_TIMER_FREQUENCY
|
||||
int "DAC3CH1 timer frequency"
|
||||
depends on !STM32_DAC3CH1_DMA_EXTERNAL
|
||||
default 0
|
||||
|
||||
endif
|
||||
|
||||
config STM32_DAC3CH2_MODE
|
||||
int "DAC3CH2 channel mode"
|
||||
depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_M3M4_V2
|
||||
default 0
|
||||
range 0 7
|
||||
---help---
|
||||
– DAC channel in Normal mode
|
||||
0: DAC channel is connected to external pin with Buffer enabled
|
||||
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
|
||||
2: DAC channel2 is connected to external pin with buffer disabled
|
||||
3: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
- DAC channel in Sample and hold mode
|
||||
4: DAC channel is connected to external pin with Buffer enabled
|
||||
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
|
||||
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
|
||||
7: DAC channel is connected to on chip peripherals with Buffer disabled
|
||||
|
||||
config STM32_DAC3CH2_DMA
|
||||
bool "DAC3CH2 DMA"
|
||||
depends on STM32_DAC3CH2
|
||||
default n
|
||||
---help---
|
||||
If DMA is selected, then a timer and output frequency must also be
|
||||
provided to support the DMA transfer. The DMA transfer could be
|
||||
supported by an EXTI trigger, but this feature is not currently
|
||||
supported by the driver.
|
||||
|
||||
if STM32_DAC3CH2_DMA
|
||||
|
||||
config STM32_DAC3CH2_DMA_BUFFER_SIZE
|
||||
int "DAC3CH2 DMA buffer size"
|
||||
default 256
|
||||
|
||||
config STM32_DAC3CH2_DMA_EXTERNAL
|
||||
bool "DAC3CH1 DMA External Trigger"
|
||||
default n
|
||||
|
||||
if STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC3CH2_HRTIM_TRG3
|
||||
bool "DAC3CH2 HRTIM Trigger 3"
|
||||
default n
|
||||
|
||||
endif # STM32_HRTIM_DAC
|
||||
|
||||
config STM32_DAC3CH2_TIMER
|
||||
int "DAC3CH2 timer"
|
||||
depends on !STM32_DAC3CH2_DMA_EXTERNAL
|
||||
default 0
|
||||
range 2 8
|
||||
|
||||
config STM32_DAC3CH2_TIMER_FREQUENCY
|
||||
int "DAC3CH2 timer frequency"
|
||||
depends on !STM32_DAC3CH2_DMA_EXTERNAL
|
||||
default 0
|
||||
|
||||
endif
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,46 @@
|
||||
#
|
||||
# STM32 digital filter configuration options.
|
||||
#
|
||||
|
||||
config STM32_ADC1_DFSDM_L4_CHIP
|
||||
bool
|
||||
default y if STM32_STM32L496XX || STM32_STM32L4XR
|
||||
select STM32_ADC1_HAVE_OUTPUT_DFSDM
|
||||
|
||||
config STM32_ADC1_DFSDM_L5_CHIP
|
||||
bool
|
||||
default y if STM32_STM32L596XX || STM32_STM32L5XR
|
||||
select STM32_ADC1_HAVE_OUTPUT_DFSDM
|
||||
|
||||
config STM32_ADC1_DFSDM_U5_CHIP
|
||||
bool
|
||||
default y if STM32_STM32U596XX || STM32_STM32U5XR
|
||||
select STM32_ADC1_HAVE_OUTPUT_DFSDM
|
||||
|
||||
config STM32_DFSDM1_FLT0
|
||||
bool "DFSDM1 Filter 0"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1
|
||||
select STM32_DFSDM
|
||||
|
||||
config STM32_DFSDM1_FLT1
|
||||
bool "DFSDM1 Filter 1"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1
|
||||
select STM32_DFSDM
|
||||
|
||||
config STM32_DFSDM1_FLT2
|
||||
bool "DFSDM1 Filter 2"
|
||||
depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3)
|
||||
select STM32_DFSDM
|
||||
|
||||
config STM32_DFSDM1_FLT3
|
||||
bool "DFSDM1 Filter 3"
|
||||
depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3)
|
||||
select STM32_DFSDM
|
||||
|
||||
config STM32_DFSDM1_DMA
|
||||
bool "DFSDM1 DMA"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM
|
||||
---help---
|
||||
If DMA is selected, then the DFSDM may be configured to support
|
||||
DMA transfer, which is necessary if multiple channels are read
|
||||
or if very high trigger frequencies are used.
|
||||
@@ -0,0 +1,118 @@
|
||||
#
|
||||
# STM32 DMA configuration options.
|
||||
#
|
||||
|
||||
config STM32_DMA1_HAVE_CHAN8
|
||||
bool
|
||||
default y if STM32_STM32G47XX
|
||||
|
||||
config STM32_DMA2_HAVE_CHAN678
|
||||
bool
|
||||
default y if STM32_STM32G47XX
|
||||
|
||||
config STM32_DMACAPABLE
|
||||
bool "Workaround non-DMA capable memory"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA
|
||||
default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA
|
||||
---help---
|
||||
This option enables the DMA interface stm32_dmacapable that can be
|
||||
used to check if it is possible to do DMA from the selected address.
|
||||
Drivers then may use this information to determine if they should
|
||||
attempt the DMA or fall back to a different transfer method.
|
||||
|
||||
if STM32_DMA2D
|
||||
|
||||
config STM32_DMA2D_NLAYERS
|
||||
int "Number DMA2D overlays"
|
||||
default 1
|
||||
range 1 256
|
||||
---help---
|
||||
Number of supported DMA2D layer.
|
||||
|
||||
config STM32_DMA2D_LAYER_SHARED
|
||||
bool "Overlays shared memory region"
|
||||
---help---
|
||||
Several overlays can share the same memory region.
|
||||
Setup a whole memory area (usually multiple size of the visible screen)
|
||||
allows image preprocessing before they become visible by blit operation.
|
||||
|
||||
config STM32_DMA2D_LAYER_PPLINE
|
||||
int "Pixel per line"
|
||||
default 1
|
||||
range 1 65535
|
||||
---help---
|
||||
If you are using the DMA2D, then you must provide the pixel per line or
|
||||
width of the overlay.
|
||||
|
||||
config STM32_DMA2D_FB_BASE
|
||||
hex "Framebuffer memory start address"
|
||||
default 0
|
||||
---help---
|
||||
If you are using the DMA2D, then you must provide the address
|
||||
of the start of the DMA2D overlays framebuffer. This address will typically
|
||||
be in the SRAM or SDRAM memory region of the FSMC/FMC.
|
||||
|
||||
config STM32_DMA2D_FB_SIZE
|
||||
int "Framebuffer memory size (bytes)"
|
||||
default 0
|
||||
---help---
|
||||
Must be the whole size of all DMA2D overlays.
|
||||
|
||||
config STM32_DMA2D_L8
|
||||
bool "8 bpp L8 (8-bit CLUT)"
|
||||
depends on STM32_FB_CMAP && STM32_LTDC_L1_L8
|
||||
default y
|
||||
|
||||
config STM32_DMA2D_AL44
|
||||
bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)"
|
||||
depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44
|
||||
default y
|
||||
|
||||
config STM32_DMA2D_AL88
|
||||
bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)"
|
||||
depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88
|
||||
default y
|
||||
|
||||
config STM32_DMA2D_RGB565
|
||||
bool "16 bpp RGB 565"
|
||||
depends on STM32_LTDC_L1_RGB565
|
||||
default y
|
||||
|
||||
config STM32_DMA2D_ARGB4444
|
||||
bool "16 bpp ARGB 4444"
|
||||
depends on STM32_LTDC_L1_ARGB4444
|
||||
default y
|
||||
|
||||
config STM32_DMA2D_ARGB1555
|
||||
bool "16 bpp ARGB 1555"
|
||||
depends on STM32_LTDC_L1_ARGB15555
|
||||
default y
|
||||
|
||||
config STM32_DMA2D_RGB888
|
||||
bool "24 bpp RGB 888"
|
||||
depends on STM32_LTDC_L1_RGB888
|
||||
default y
|
||||
|
||||
config STM32_DMA2D_ARGB8888
|
||||
bool "32 bpp ARGB 8888"
|
||||
depends on STM32_LTDC_L1_ARGB8888
|
||||
default y
|
||||
|
||||
config STM32_DMA2D_REGDEBUG
|
||||
bool "DMA2D Register level debug"
|
||||
depends on DEBUG_INFO && DEBUG_LCD
|
||||
---help---
|
||||
Output detailed register-level DMA2D device debug information.
|
||||
|
||||
endif # STM32_DMA2D
|
||||
|
||||
config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED
|
||||
bool "Do not disqualify DMA capability based on cache alignment"
|
||||
depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH
|
||||
---help---
|
||||
This option configures the stm32_dmacapable to not disqualify
|
||||
DMA operations on memory that is not dcache aligned based solely
|
||||
on the starting address and byte count.
|
||||
|
||||
Use this when ALL buffer extents are known to be aligned, but the
|
||||
the count does not use the complete buffer.
|
||||
@@ -0,0 +1,99 @@
|
||||
#
|
||||
# STM32 Digital Temperature Sensor (DTS) configuration options.
|
||||
#
|
||||
|
||||
config STM32_DTS_REFCLK_LSE
|
||||
bool "Use LSE (32.768 kHz crystal) as DTS reference clock"
|
||||
default n
|
||||
---help---
|
||||
Select the low-speed external (LSE) oscillator as the reference clock
|
||||
for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will
|
||||
measure FM(T) pulses over N LSE cycles.
|
||||
|
||||
If disabled, the DTS will use the APB-bus clock (PCLK) as the reference
|
||||
(REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the
|
||||
calibration prescaler ≤ 1 MHz.
|
||||
|
||||
config STM32_DTS_SMP_TIME
|
||||
int "DTS sampling time (TS1_SMP_TIME[3:0])"
|
||||
default 1
|
||||
range 1 15
|
||||
---help---
|
||||
Number of reference-clock cycles (PCLK or LSE) counted per
|
||||
DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles).
|
||||
|
||||
config STM32_DTS_TRIGGER
|
||||
int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])"
|
||||
default 0
|
||||
---help---
|
||||
If non-zero, DTS will start measurements on the rising edge of
|
||||
the selected hardware line. Values match RM0481 Table 275:
|
||||
0=Software Trigger, 1=LPTIM1_CH1,
|
||||
2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved.
|
||||
|
||||
config STM32_DTS_LOW_THRESHOLD
|
||||
int "DTS low-threshold (°C)"
|
||||
default 0
|
||||
---help---
|
||||
The temperature (in whole °C) below which the DTS window comparator will
|
||||
assert the low-threshold flag (TS1_ITLF). To disable, set equal to 0.
|
||||
|
||||
config STM32_DTS_HIGH_THRESHOLD
|
||||
int "DTS high-threshold (°C)"
|
||||
default 100
|
||||
---help---
|
||||
The temperature (in whole °C) above which the DTS window comparator will
|
||||
assert the high-threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD.
|
||||
|
||||
config STM32_DTS_ITEN_ITEF
|
||||
bool "Enable DTS end-of-measurement interrupt (TS1_ITEF)"
|
||||
default y
|
||||
---help---
|
||||
Enable the synchronous “end of measurement” interrupt for the
|
||||
digital temperature sensor. When set, the driver will attach
|
||||
and unmask TS1_ITEF and will call your ISR on every fresh sample.
|
||||
|
||||
config STM32_DTS_ITEN_ITLF
|
||||
bool "Enable DTS low-threshold interrupt (TS1_ITLF)"
|
||||
default n
|
||||
---help---
|
||||
Enable the synchronous “low threshold crossed” interrupt for the
|
||||
digital temperature sensor. When set, the driver will unmask
|
||||
TS1_ITLF so you can get notified whenever the measured value
|
||||
drops below your programmed low-threshold.
|
||||
|
||||
config STM32_DTS_ITEN_ITHF
|
||||
bool "Enable DTS high-threshold interrupt (TS1_ITHF)"
|
||||
default n
|
||||
---help---
|
||||
Enable the synchronous “high threshold crossed” interrupt for the
|
||||
digital temperature sensor. When set, the driver will unmask
|
||||
TS1_ITHF so you can get notified whenever the measured value
|
||||
exceeds your programmed high-threshold.
|
||||
|
||||
config STM32_DTS_AITEN_AITEF
|
||||
bool "Enable DTS asynchronous end-of-measurement interrupt (TS1_AITEF)"
|
||||
depends on STM32_DTS_REFCLK_LSE
|
||||
default n
|
||||
---help---
|
||||
Enable the asynchronous end-of-measurement interrupt. This will
|
||||
set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup
|
||||
event when a conversion completes (in Stop/Sleep modes).
|
||||
|
||||
config STM32_DTS_AITEN_AITLF
|
||||
bool "Enable DTS asynchronous low-threshold interrupt (TS1_AITLF)"
|
||||
depends on STM32_DTS_REFCLK_LSE
|
||||
default n
|
||||
---help---
|
||||
Enable the asynchronous low-threshold comparator interrupt. This
|
||||
will set TS1_AITLEN in DTS_ITENR and generate a wakeup event
|
||||
when the measurement drops below your low threshold.
|
||||
|
||||
config STM32_DTS_AITEN_AITHF
|
||||
bool "Enable DTS asynchronous high-threshold interrupt (TS1_AITHF)"
|
||||
depends on STM32_DTS_REFCLK_LSE
|
||||
default n
|
||||
---help---
|
||||
Enable the asynchronous high-threshold comparator interrupt. This
|
||||
will set TS1_AITHEN in DTS_ITENR and generate a wakeup event
|
||||
when the measurement exceeds your high threshold.
|
||||
@@ -0,0 +1,290 @@
|
||||
#
|
||||
# STM32 common ETH options.
|
||||
#
|
||||
|
||||
config STM32_PHY_HAVE_POLLED
|
||||
bool
|
||||
|
||||
if STM32_ETHMAC
|
||||
|
||||
config STM32_PHYADDR
|
||||
int "PHY address"
|
||||
default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7
|
||||
default 0
|
||||
---help---
|
||||
The 5-bit address of the PHY on the board. Default: 1
|
||||
|
||||
config STM32_PHYINIT
|
||||
bool "Board-specific PHY Initialization"
|
||||
---help---
|
||||
Some boards require specialized initialization of the PHY before it can be used.
|
||||
This may include such things as configuring GPIOs, resetting the PHY, etc. If
|
||||
STM32_PHYINIT is defined in the configuration then the board specific logic must
|
||||
provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function
|
||||
one time before it first uses the PHY.
|
||||
|
||||
config STM32_MII
|
||||
bool "Use MII interface"
|
||||
---help---
|
||||
Support Ethernet MII interface.
|
||||
|
||||
config STM32_AUTONEG
|
||||
bool "Use autonegotiation"
|
||||
default y
|
||||
---help---
|
||||
Use PHY autonegotiation to determine speed and mode
|
||||
|
||||
if !STM32_AUTONEG
|
||||
|
||||
config STM32_ETHFD
|
||||
bool "Full duplex"
|
||||
---help---
|
||||
If STM32_AUTONEG is not defined, then this may be defined to select full duplex
|
||||
mode. Default: half-duplex
|
||||
|
||||
config STM32_ETH100MBPS
|
||||
bool "100 Mbps"
|
||||
---help---
|
||||
If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps
|
||||
speed. Default: 10 Mbps
|
||||
|
||||
endif # !STM32_AUTONEG
|
||||
|
||||
if STM32_AUTONEG
|
||||
|
||||
config STM32_PHYSR
|
||||
int "PHY Status Register Address (decimal)"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. The PHY status register
|
||||
address may diff from PHY to PHY. This configuration sets the address of
|
||||
the PHY status register.
|
||||
|
||||
config STM32_PHYSR_ALTCONFIG
|
||||
bool "PHY Status Alternate Bit Layout"
|
||||
---help---
|
||||
Different PHYs present speed and mode information in different ways. Some
|
||||
will present separate information for speed and mode (this is the default).
|
||||
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
|
||||
full/half duplex indication. This options selects an alternative representation
|
||||
where speed and mode information are combined. This might mean, for example,
|
||||
separate bits for 10HD, 100HD, 10FD and 100FD.
|
||||
|
||||
if !STM32_PHYSR_ALTCONFIG
|
||||
|
||||
config STM32_PHYSR_SPEED
|
||||
hex "PHY Speed Mask"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This provides bit mask
|
||||
for isolating the 10 or 100MBps speed indication.
|
||||
|
||||
config STM32_PHYSR_100MBPS
|
||||
hex "PHY 100Mbps Speed Value"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This provides the value
|
||||
of the speed bit(s) indicating 100MBps speed.
|
||||
|
||||
config STM32_PHYSR_MODE
|
||||
hex "PHY Mode Mask"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This provide bit mask
|
||||
for isolating the full or half duplex mode bits.
|
||||
|
||||
config STM32_PHYSR_FULLDUPLEX
|
||||
hex "PHY Full Duplex Mode Value"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This provides the
|
||||
value of the mode bits indicating full duplex mode.
|
||||
|
||||
endif # !STM32_PHYSR_ALTCONFIG
|
||||
|
||||
if STM32_PHYSR_ALTCONFIG
|
||||
|
||||
config STM32_PHYSR_ALTMODE
|
||||
hex "PHY Mode Mask"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This provide bit mask
|
||||
for isolating the speed and full/half duplex mode bits.
|
||||
|
||||
config STM32_PHYSR_10HD
|
||||
hex "10MBase-T Half Duplex Value"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This is the value
|
||||
under the bit mask that represents the 10Mbps, half duplex setting.
|
||||
|
||||
config STM32_PHYSR_100HD
|
||||
hex "100Base-T Half Duplex Value"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This is the value
|
||||
under the bit mask that represents the 100Mbps, half duplex setting.
|
||||
|
||||
config STM32_PHYSR_10FD
|
||||
hex "10Base-T Full Duplex Value"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This is the value
|
||||
under the bit mask that represents the 10Mbps, full duplex setting.
|
||||
|
||||
config STM32_PHYSR_100FD
|
||||
hex "100Base-T Full Duplex Value"
|
||||
---help---
|
||||
This must be provided if STM32_AUTONEG is defined. This is the value
|
||||
under the bit mask that represents the 100Mbps, full duplex setting.
|
||||
|
||||
endif # STM32_PHYSR_ALTCONFIG
|
||||
|
||||
endif # STM32_AUTONEG
|
||||
|
||||
config STM32_ETH_PTP
|
||||
bool "Precision Time Protocol (PTP)"
|
||||
---help---
|
||||
Enables Precision Time Protocol (PTP) hardware timer.
|
||||
|
||||
config STM32_ETH_ENHANCEDDESC
|
||||
bool "Enable enhanced RX/TX descriptors"
|
||||
depends on STM32_COMMON_LEGACY
|
||||
default n
|
||||
---help---
|
||||
Enables double-length DMA descriptors that have space for packet
|
||||
timestamps and checksum offloading.
|
||||
|
||||
config STM32_ETH_PTP_GPIO
|
||||
bool "PTP pulse-per-second output signal"
|
||||
depends on STM32_COMMON_LEGACY && STM32_ETH_PTP
|
||||
default n
|
||||
---help---
|
||||
Enables pulse-per-second output on GPIO pin.
|
||||
|
||||
config STM32_ETH_PTP_RTC_HIRES
|
||||
bool "Use PTP timer as system high-resolution RTC"
|
||||
depends on STM32_COMMON_LEGACY && STM32_ETH_PTP
|
||||
default n
|
||||
---help---
|
||||
Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source.
|
||||
This provides high resolution timestamps to clock_gettime().
|
||||
Note that PTP timer is disabled when Ethernet interface is down or
|
||||
being reset. During this time g_rtc_enabled is set to false and system
|
||||
uses the lower resolution system tick counter.
|
||||
|
||||
config STM32_ETH_TIMESTAMP_RX
|
||||
bool "Hardware timestamping of received packets"
|
||||
depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC
|
||||
select ARCH_HAVE_NETDEV_TIMESTAMP
|
||||
default n
|
||||
---help---
|
||||
Timestamp all received Ethernet packets.
|
||||
Timestamp is available to application through SO_TIMESTAMP socket option.
|
||||
|
||||
config STM32_RMII
|
||||
bool
|
||||
default !STM32_MII
|
||||
|
||||
config STM32_ETHMAC_REGDEBUG
|
||||
bool "Register-Level Debug"
|
||||
depends on DEBUG_NET_INFO
|
||||
---help---
|
||||
Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES.
|
||||
|
||||
endif # STM32_ETHMAC
|
||||
|
||||
choice
|
||||
prompt "MII clock configuration"
|
||||
depends on STM32_MII
|
||||
default STM32_MII_MCO if STM32_STM32F10XX
|
||||
default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX
|
||||
default STM32_MII_EXTCLK
|
||||
|
||||
config STM32_MII_MCO
|
||||
bool "Use MC0 as MII clock"
|
||||
depends on STM32_STM32F10XX
|
||||
---help---
|
||||
Use MCO to clock the MII interface. Default: Use MC0
|
||||
|
||||
config STM32_MII_MCO1
|
||||
bool "Use MC01 as MII clock"
|
||||
depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5)
|
||||
---help---
|
||||
Use MCO1 to clock the MII interface. Default: Use MC01
|
||||
|
||||
config STM32_MII_MCO2
|
||||
bool "Use MC02 as MII clock"
|
||||
depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5)
|
||||
---help---
|
||||
Use MCO2 to clock the MII interface. Default: Use MC01
|
||||
|
||||
config STM32_MII_EXTCLK
|
||||
bool "External MII clock"
|
||||
---help---
|
||||
Clocking is provided by external logic. Don't use MCO for MII
|
||||
clock. Default: Use MC0[1]
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "RMII clock configuration"
|
||||
depends on STM32_RMII
|
||||
default STM32_RMII_MCO if STM32_STM32F10XX
|
||||
default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX
|
||||
default STM32_RMII_EXTCLK
|
||||
|
||||
config STM32_RMII_MCO
|
||||
bool "Use MC0 as RMII clock"
|
||||
depends on STM32_STM32F10XX
|
||||
---help---
|
||||
Use MCO to clock the RMII interface. Default: Use MC0
|
||||
|
||||
config STM32_RMII_MCO1
|
||||
bool "Use MC01 as RMII clock"
|
||||
depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5)
|
||||
---help---
|
||||
Use MCO1 to clock the RMII interface. Default: Use MC01
|
||||
|
||||
config STM32_RMII_MCO2
|
||||
bool "Use MC02 as RMII clock"
|
||||
depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5)
|
||||
---help---
|
||||
Use MCO2 to clock the RMII interface. Default: Use MC01
|
||||
|
||||
config STM32_RMII_EXTCLK
|
||||
bool "External RMII clock"
|
||||
---help---
|
||||
Clocking is provided by external logic. Don't use MCO for RMII
|
||||
clock. Default: Use MC0[1]
|
||||
|
||||
endchoice
|
||||
|
||||
config STM32_PHY_POLLING
|
||||
bool "Support network monitoring by polling the PHY"
|
||||
depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_PHY_HAVE_POLLED
|
||||
select ARCH_PHY_POLLED
|
||||
---help---
|
||||
Some boards may not have an interrupt connected to the PHY.
|
||||
This option allows the network monitor to be used by polling the
|
||||
the PHY for status.
|
||||
|
||||
config STM32_ETH_HWCHECKSUM
|
||||
bool "Enable ethernet hardware checksum"
|
||||
depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC
|
||||
---help---
|
||||
Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload
|
||||
engine in the Ethernet MAC.
|
||||
When enabled, hardware generates checksums for TX and checks RX frames.
|
||||
Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS,
|
||||
NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid
|
||||
redundant verification in the network stack.
|
||||
|
||||
config STM32_NO_PHY
|
||||
bool "MAC has no PHY"
|
||||
depends on STM32_COMMON_H7_H5 && STM32_ETHMAC
|
||||
|
||||
config STM32_ETH_NRXDESC
|
||||
int "Number of RX descriptors"
|
||||
depends on STM32_COMMON_H7_H5 && STM32_ETHMAC
|
||||
default 8
|
||||
---help---
|
||||
Number of RX DMA descriptors to use.
|
||||
|
||||
config STM32_ETH_NTXDESC
|
||||
int "Number of TX descriptors"
|
||||
depends on STM32_COMMON_H7_H5 && STM32_ETHMAC
|
||||
default 4
|
||||
---help---
|
||||
Number of TX DMA descriptors to use.
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# STM32 flash configuration options.
|
||||
#
|
||||
|
||||
# Common STM32 flash size designator options.
|
||||
|
||||
config STM32_FLASH_CONFIG_DEFAULT
|
||||
bool "Default or device-derived flash size"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_4
|
||||
bool "Flash size designator 4, 16 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_6
|
||||
bool "Flash size designator 6, 32 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_8
|
||||
bool "Flash size designator 8, 64 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_B
|
||||
bool "Flash size designator B, 128 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_C
|
||||
bool "Flash size designator C, 256 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_C_320
|
||||
bool "STM32WB flash size designator C, 320 KiB variant"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_D
|
||||
bool "Flash size designator D, 384 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_E
|
||||
bool "Flash size designator E, 512 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_F
|
||||
bool "Flash size designator F, 768 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_G
|
||||
bool "Flash size designator G, 1024 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_I
|
||||
bool "Flash size designator I, 2048 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_Y
|
||||
bool "Flash size designator Y, 640 KiB"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_CONFIG_Z
|
||||
bool "Legacy STM32 flash size designator Z"
|
||||
default n
|
||||
|
||||
config STM32_FLASH_OVERRIDE
|
||||
bool "Override Flash Designator" if ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0
|
||||
default y if ARCH_CHIP_STM32F7 || STM32_COMMON_F7_H7_H5
|
||||
default y if STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB
|
||||
default y if ARCH_CHIP_STM32WL5
|
||||
default n
|
||||
|
||||
choice
|
||||
prompt "Override Flash Size Designator"
|
||||
depends on STM32_FLASH_OVERRIDE
|
||||
default STM32_FLASH_OVERRIDE_DEFAULT
|
||||
---help---
|
||||
STM32 parts numbering ends with a number or letter that designates
|
||||
the internal FLASH size. Select "Default" to use the size from
|
||||
the selected chip. Select another designator only when the part
|
||||
variant differs from the listed chip selection.
|
||||
|
||||
config STM32_FLASH_OVERRIDE_DEFAULT
|
||||
bool "Default"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_6
|
||||
bool "6 32KiB"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_8
|
||||
bool "8 64KiB"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_B
|
||||
bool "B 128KiB"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_C
|
||||
bool "C 256KiB"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_C_320
|
||||
bool "C 320KiB"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_E
|
||||
bool "E 512KiB"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_G
|
||||
bool "G 1024KiB"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_I
|
||||
bool "I 2048KiB"
|
||||
|
||||
config STM32_FLASH_OVERRIDE_Y
|
||||
bool "Y 640KiB"
|
||||
|
||||
endchoice # Override Flash Size Designator
|
||||
|
||||
config STM32_FLASH_ART_ACCELERATOR
|
||||
bool "Flash ART Accelerator"
|
||||
depends on STM32_HAVE_FLASH_ART_ACCELERATOR
|
||||
default n
|
||||
---help---
|
||||
ART Accelerator on the flash memory ITCM interface accelerates code execution
|
||||
with a system of instruction prefetch and cache lines.
|
||||
|
||||
Enable if code and/or read-only data is accessed through ITCM bus instead of
|
||||
AXIM bus.
|
||||
|
||||
config STM32_FLASH_PREFETCH
|
||||
bool "Enable FLASH Pre-fetch"
|
||||
depends on STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB
|
||||
default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446
|
||||
default y
|
||||
---help---
|
||||
Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled
|
||||
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
|
||||
properly and enabling this option may interfere with ADC accuracy.
|
||||
|
||||
config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
|
||||
bool "Workaround for FLASH data cache corruption"
|
||||
depends on STM32_FLASH_DCACHE && (STM32_STM32F20XX || STM32_STM32F4XXX || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR)))
|
||||
---help---
|
||||
Enable the workaround to fix flash data cache corruption when reading
|
||||
from one flash bank while writing on other flash bank. See your STM32
|
||||
errata to check if your STM32 is affected by this problem.
|
||||
|
||||
config STM32_PROGMEM
|
||||
bool "Flash PROGMEM support"
|
||||
depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5
|
||||
select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM
|
||||
select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM
|
||||
---help---
|
||||
Add progmem support, start block and end block options are provided to
|
||||
obtain a uniform flash memory mapping.
|
||||
|
||||
config STM32_FLASH_ICACHE
|
||||
bool "Enable FLASH Instruction Cache"
|
||||
default y
|
||||
depends on STM32_HAVE_FLASH_ICACHE
|
||||
---help---
|
||||
Enable the FLASH instruction cache.
|
||||
|
||||
config STM32_FLASH_DCACHE
|
||||
bool "Enable FLASH Data Cache"
|
||||
default y
|
||||
depends on STM32_HAVE_FLASH_DCACHE
|
||||
---help---
|
||||
Enable the FLASH data cache.
|
||||
@@ -0,0 +1,197 @@
|
||||
#
|
||||
# STM32 common FOC options.
|
||||
#
|
||||
|
||||
config STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND
|
||||
bool
|
||||
|
||||
config STM32_FOC_USE_TIM1
|
||||
bool
|
||||
select STM32_TIM1
|
||||
select STM32_TIM1_PWM
|
||||
select STM32_TIM1_CHANNEL1
|
||||
select STM32_TIM1_CHANNEL2
|
||||
select STM32_TIM1_CHANNEL3
|
||||
select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4
|
||||
select STM32_TIM1_CH1OUT
|
||||
select STM32_TIM1_CH2OUT
|
||||
select STM32_TIM1_CH3OUT
|
||||
select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4
|
||||
select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY
|
||||
select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY
|
||||
select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY
|
||||
---help---
|
||||
The TIM1 generates PWM for the FOC
|
||||
|
||||
config STM32_FOC_USE_TIM8
|
||||
bool
|
||||
select STM32_TIM8
|
||||
select STM32_TIM8_PWM
|
||||
select STM32_TIM8_CHANNEL1
|
||||
select STM32_TIM8_CHANNEL2
|
||||
select STM32_TIM8_CHANNEL3
|
||||
select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4
|
||||
select STM32_TIM8_CH1OUT
|
||||
select STM32_TIM8_CH2OUT
|
||||
select STM32_TIM8_CH3OUT
|
||||
select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4
|
||||
select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY
|
||||
select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY
|
||||
select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY
|
||||
---help---
|
||||
The TIM8 generates PWM for the FOC
|
||||
|
||||
config STM32_FOC_USE_ADC1
|
||||
bool
|
||||
select STM32_ADC1
|
||||
select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1
|
||||
select STM32_ADC1_JEXTSEL
|
||||
|
||||
config STM32_FOC_USE_ADC2
|
||||
bool
|
||||
select STM32_ADC2
|
||||
select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1
|
||||
select STM32_ADC2_JEXTSEL
|
||||
|
||||
config STM32_FOC_USE_ADC3
|
||||
bool
|
||||
select STM32_ADC3
|
||||
select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1
|
||||
select STM32_ADC3_JEXTSEL
|
||||
|
||||
#
|
||||
#
|
||||
|
||||
choice
|
||||
prompt "FOC ADC trigger selection"
|
||||
depends on STM32_FOC
|
||||
default STM32_FOC_ADC_TRGO
|
||||
|
||||
config STM32_FOC_ADC_CCR4
|
||||
bool "FOC uses CCR4 as ADC trigger"
|
||||
---help---
|
||||
This option uses the software frequency prescaler and is
|
||||
not possible for 4-phase output.
|
||||
|
||||
config STM32_FOC_ADC_TRGO
|
||||
bool "FOC uses TRGO as ADC trigger"
|
||||
depends on STM32_HAVE_IP_ADC_M3M4_V2 || ARCH_CHIP_STM32F7 || (STM32_HAVE_IP_ADC_M3M4_V1 && !STM32_FOC_FOC1)
|
||||
select STM32_PWM_TRGO
|
||||
---help---
|
||||
This option allows you to use higher PWM frequency and works for 4-phase output.
|
||||
It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL).
|
||||
|
||||
endchoice # "FOC ADC trigger selection"
|
||||
|
||||
choice
|
||||
prompt "FOC0 device ADC selection"
|
||||
depends on STM32_FOC_FOC0
|
||||
default STM32_FOC_FOC0_ADC1
|
||||
|
||||
config STM32_FOC_FOC0_ADC1
|
||||
bool "FOC0 uses ADC1"
|
||||
depends on STM32_HAVE_ADC1
|
||||
select STM32_FOC_USE_ADC1
|
||||
|
||||
config STM32_FOC_FOC0_ADC2
|
||||
bool "FOC0 uses ADC2"
|
||||
depends on STM32_HAVE_ADC2
|
||||
select STM32_FOC_USE_ADC2
|
||||
|
||||
config STM32_FOC_FOC0_ADC3
|
||||
bool "FOC0 uses ADC3"
|
||||
depends on STM32_HAVE_ADC3
|
||||
select STM32_FOC_USE_ADC3
|
||||
|
||||
config STM32_FOC_FOC0_ADC4
|
||||
bool "FOC0 uses ADC4"
|
||||
depends on STM32_HAVE_ADC4
|
||||
select STM32_FOC_USE_ADC4
|
||||
|
||||
endchoice # "FOC0 device ADC selection"
|
||||
|
||||
choice
|
||||
prompt "FOC1 device ADC selection"
|
||||
depends on STM32_FOC_FOC1
|
||||
default STM32_FOC_FOC1_ADC2
|
||||
|
||||
config STM32_FOC_FOC1_ADC1
|
||||
bool "FOC1 uses ADC1"
|
||||
depends on STM32_HAVE_ADC1
|
||||
select STM32_FOC_USE_ADC1
|
||||
|
||||
config STM32_FOC_FOC1_ADC2
|
||||
bool "FOC1 uses ADC2"
|
||||
depends on STM32_HAVE_ADC2
|
||||
select STM32_FOC_USE_ADC2
|
||||
|
||||
config STM32_FOC_FOC1_ADC3
|
||||
bool "FOC1 uses ADC3"
|
||||
depends on STM32_HAVE_ADC3
|
||||
select STM32_FOC_USE_ADC3
|
||||
|
||||
config STM32_FOC_FOC1_ADC4
|
||||
bool "FOC1 uses ADC4"
|
||||
depends on STM32_HAVE_ADC4
|
||||
select STM32_FOC_USE_ADC4
|
||||
|
||||
endchoice # "FOC0 device ADC selection"
|
||||
|
||||
menuconfig STM32_FOC
|
||||
bool "STM32 lower-half FOC support"
|
||||
depends on STM32_HAVE_COMMON_FOC || ARCH_CHIP_STM32F7
|
||||
select ARCH_IRQPRIO
|
||||
select STM32_ADC
|
||||
select STM32_PWM_MULTICHAN
|
||||
select STM32_PWM_LL_OPS
|
||||
select STM32_ADC_LL_OPS
|
||||
select STM32_ADC_CHANGE_SAMPLETIME
|
||||
select STM32_ADC_NO_STARTUP_CONV
|
||||
|
||||
config STM32_FOC_FOC0
|
||||
bool "FOC0 device (TIM1 for PWM modulation)"
|
||||
depends on STM32_FOC && STM32_HAVE_TIM1
|
||||
select STM32_FOC_USE_TIM1
|
||||
---help---
|
||||
Enable support for FOC0 device that uses TIM1 for PWM modulation
|
||||
|
||||
config STM32_FOC_FOC1
|
||||
bool "FOC1 device (TIM8 for PWM modulation)"
|
||||
depends on STM32_FOC && STM32_HAVE_TIM8
|
||||
select STM32_FOC_USE_TIM8
|
||||
---help---
|
||||
Enable support for FOC1 device that uses TIM8 for PWM modulation
|
||||
|
||||
config STM32_FOC_HAS_PWM_COMPLEMENTARY
|
||||
bool "FOC PWM has complementary outputs"
|
||||
depends on STM32_FOC
|
||||
---help---
|
||||
Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode)
|
||||
|
||||
# hidden variables and automatic configuration
|
||||
|
||||
if STM32_FOC
|
||||
|
||||
config STM32_FOC_USE_ADC4
|
||||
bool
|
||||
default n
|
||||
select STM32_ADC4
|
||||
select STM32_ADC3_JEXTSEL
|
||||
|
||||
config STM32_FOC_G4_ADCCHAN0_WORKAROUND
|
||||
bool "FOC G4 ADC channel 0 unwanted conversion workaround"
|
||||
default n
|
||||
depends on STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND
|
||||
---help---
|
||||
Some STM32G4 family chips have an issue that causes unwanted ADC channel 0
|
||||
conversion when a regular conversion is interrupted by an injected conversion.
|
||||
This FOC implementation uses injected conversion to sample phase currents
|
||||
and allows user to use regular conversion as an auxiliary analog conversion.
|
||||
In this case, there is a certain probability that regular conversion will be
|
||||
interrupted by an injected conversion that will lead to an incorrect reading
|
||||
of phase currents.
|
||||
|
||||
This workaround inserts a dummy conversion at the beginning of the injected
|
||||
sequence. For more details look at the chip errata documents.
|
||||
|
||||
endif #STM32_FOC
|
||||
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# STM32 GPIO configuration options.
|
||||
#
|
||||
|
||||
config STM32_GPIO_HAVE_PORTD
|
||||
bool
|
||||
|
||||
config STM32_GPIO_HAVE_PORTE
|
||||
bool
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,292 @@
|
||||
#
|
||||
# STM32 common HCI UART options.
|
||||
#
|
||||
|
||||
config STM32_HCIUART
|
||||
bool
|
||||
|
||||
config STM32_HCIUART_RXDMA
|
||||
bool
|
||||
|
||||
if STM32_USART1_HCIUART
|
||||
|
||||
config STM32_HCIUART1_RXBUFSIZE
|
||||
int "HCI UART1 Rx buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered as they are received. This specifies
|
||||
the size of the receive buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be received
|
||||
|
||||
config STM32_HCIUART1_TXBUFSIZE
|
||||
int "HCI UART1 Transmit buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered before being sent. This specifies
|
||||
the size of the transmit buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be sent
|
||||
|
||||
config STM32_HCIUART1_BAUD
|
||||
int "HCI UART1 initial BAUD rate"
|
||||
default 115200
|
||||
---help---
|
||||
The configured initial BAUD of the HCIR USART used during bringup.
|
||||
In most cases this initial rate can be increased by the upper half
|
||||
HCI UART driver using vendor-specifi HCI UART commands.
|
||||
|
||||
config STM32_HCIUART1_RXDMA
|
||||
bool "HCI UART1 Rx DMA"
|
||||
default n
|
||||
depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2))
|
||||
select STM32_HCIUART_RXDMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
endif # STM32_USART1_HCIUART
|
||||
|
||||
if STM32_USART2_HCIUART
|
||||
|
||||
config STM32_HCIUART2_RXBUFSIZE
|
||||
int "HCI UART2 Rx buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered as they are received. This specifies
|
||||
the size of the receive buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be received
|
||||
|
||||
config STM32_HCIUART2_TXBUFSIZE
|
||||
int "HCI UART2 Transmit buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered before being sent. This specifies
|
||||
the size of the transmit buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be sent
|
||||
|
||||
config STM32_HCIUART2_BAUD
|
||||
int "HCI UART2 initial BAUD rate"
|
||||
default 115200
|
||||
---help---
|
||||
The configured initial BAUD of the HCIR USART used during bringup.
|
||||
In most cases this initial rate can be increased by the upper half
|
||||
HCI UART driver using vendor-specifi HCI UART commands.
|
||||
|
||||
config STM32_HCIUART2_RXDMA
|
||||
bool "HCI UART2 Rx DMA"
|
||||
default n
|
||||
depends on STM32_DMA1
|
||||
select STM32_HCIUART_RXDMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
endif # STM32_USART2_HCIUART
|
||||
|
||||
if STM32_USART3_HCIUART
|
||||
|
||||
config STM32_HCIUART3_RXBUFSIZE
|
||||
int "HCI UART3 Rx buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered as they are received. This specifies
|
||||
the size of the receive buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be received
|
||||
|
||||
config STM32_HCIUART3_TXBUFSIZE
|
||||
int "HCI UART3 Transmit buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered before being sent. This specifies
|
||||
the size of the transmit buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be sent
|
||||
|
||||
config STM32_HCIUART3_BAUD
|
||||
int "HCI UART3 initial BAUD rate"
|
||||
default 115200
|
||||
---help---
|
||||
The configured initial BAUD of the HCIR USART used during bringup.
|
||||
In most cases this initial rate can be increased by the upper half
|
||||
HCI UART driver using vendor-specifi HCI UART commands.
|
||||
|
||||
config STM32_HCIUART3_RXDMA
|
||||
bool "HCI UART3 Rx DMA"
|
||||
default n
|
||||
depends on STM32_DMA1
|
||||
select STM32_HCIUART_RXDMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
endif # STM32_USART3_HCIUART
|
||||
|
||||
if STM32_USART6_HCIUART
|
||||
|
||||
config STM32_HCIUART6_RXBUFSIZE
|
||||
int "HCI UART6 Rx buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered as they are received. This specifies
|
||||
the size of the receive buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be received
|
||||
|
||||
config STM32_HCIUART6_TXBUFSIZE
|
||||
int "HCI UART6 Transmit buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered before being sent. This specifies
|
||||
the size of the transmit buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be sent
|
||||
|
||||
config STM32_HCIUART6_BAUD
|
||||
int "HCI UART6 initial BAUD rate"
|
||||
default 115200
|
||||
---help---
|
||||
The configured initial BAUD of the HCIR USART used during bringup.
|
||||
In most cases this initial rate can be increased by the upper half
|
||||
HCI UART driver using vendor-specifi HCI UART commands.
|
||||
|
||||
config STM32_HCIUART6_RXDMA
|
||||
bool "HCI UART6 Rx DMA"
|
||||
default n
|
||||
depends on STM32_DMA1
|
||||
select STM32_HCIUART_RXDMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
endif # STM32_USART6_HCIUART
|
||||
|
||||
if STM32_UART7_HCIUART
|
||||
|
||||
config STM32_HCIUART7_RXBUFSIZE
|
||||
int "HCI UART7 Rx buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered as they are received. This specifies
|
||||
the size of the receive buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be received
|
||||
|
||||
config STM32_HCIUART7_TXBUFSIZE
|
||||
int "HCI UART7 Transmit buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered before being sent. This specifies
|
||||
the size of the transmit buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be sent
|
||||
|
||||
config STM32_HCIUART7_BAUD
|
||||
int "HCI UART7 initial BAUD rate"
|
||||
default 115200
|
||||
---help---
|
||||
The configured initial BAUD of the HCIR USART used during bringup.
|
||||
In most cases this initial rate can be increased by the upper half
|
||||
HCI UART driver using vendor-specifi HCI UART commands.
|
||||
|
||||
config STM32_HCIUART7_RXDMA
|
||||
bool "HCI UART7 Rx DMA"
|
||||
default n
|
||||
depends on STM32_DMA2
|
||||
select STM32_HCIUART_RXDMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
endif # STM32_UART7_HCIUART
|
||||
|
||||
if STM32_UART8_HCIUART
|
||||
|
||||
config STM32_HCIUART8_RXBUFSIZE
|
||||
int "HCI UART8 Rx buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered as they are received. This specifies
|
||||
the size of the receive buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be received
|
||||
|
||||
config STM32_HCIUART8_TXBUFSIZE
|
||||
int "HCI UART8 Transmit buffer size"
|
||||
default 80
|
||||
---help---
|
||||
Characters are buffered before being sent. This specifies
|
||||
the size of the transmit buffer. Ideally this should be at least
|
||||
the size of the largest frame that can be sent
|
||||
|
||||
config STM32_HCIUART8_BAUD
|
||||
int "HCI UART8 initial BAUD rate"
|
||||
default 115200
|
||||
---help---
|
||||
The configured initial BAUD of the HCIR USART used during bringup.
|
||||
In most cases this initial rate can be increased by the upper half
|
||||
HCI UART driver using vendor-specifi HCI UART commands.
|
||||
|
||||
config STM32_HCIUART8_RXDMA
|
||||
bool "HCI UART8 Rx DMA"
|
||||
default n
|
||||
depends on STM32_DMA2
|
||||
select STM32_HCIUART_RXDMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
endif # STM32_UART8_HCIUART
|
||||
|
||||
menu "HCI UART Driver Configuration"
|
||||
depends on STM32_SERIALDRIVER
|
||||
|
||||
config STM32_HCIUART_RXDMA_BUFSIZE
|
||||
int "Rx DMA buffer size"
|
||||
default 32
|
||||
range 32 4096
|
||||
depends on STM32_HCIUART_RXDMA
|
||||
---help---
|
||||
The DMA buffer size when using RX DMA to emulate a FIFO.
|
||||
|
||||
When streaming data, the generic serial layer will be called
|
||||
every time the FIFO receives half or this number of bytes.
|
||||
|
||||
Value given here will be rounded up to next multiple of 4 bytes.
|
||||
|
||||
config STM32_HCIUART_RXDMAPRIO
|
||||
hex "HCI UART DMA priority"
|
||||
default 0x00001000 if STM32_STM32F10XX
|
||||
default 0x00010000 if !STM32_STM32F10XX
|
||||
depends on STM32_HCIUART_RXDMA
|
||||
---help---
|
||||
Select HCI UART DMA priority.
|
||||
|
||||
For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium,
|
||||
0x00002000 high, 0x00003000 very high. Default: medium.
|
||||
|
||||
For other STM32's, options are: 0x00000000 low, 0x00010000 medium,
|
||||
0x00020000 high, 0x00030000 very high. Default: medium.
|
||||
|
||||
config STM32_HCIUART_SW_RXFLOW
|
||||
bool "Use Software UART RTS flow control"
|
||||
default n
|
||||
---help---
|
||||
Enable UART RTS flow control using Software. Current STM32 have
|
||||
broken HW based RTS behavior (they assert nRTS after every byte
|
||||
received) Enable this setting workaround this issue by using
|
||||
software based management of RTS
|
||||
|
||||
If HCI UART DMA is enabled, this is probably the better selection
|
||||
as well. In that case, the Rx DMA buffer will avoid Rx overrun due
|
||||
to short, bursty activity. Software RTS management will probably
|
||||
result in overall better throughput and should still avoid Rx data
|
||||
overrun conditions.
|
||||
|
||||
config STM32_HCIUART_UPPER_WATERMARK
|
||||
int "RTS flow control upper watermark (%)"
|
||||
default 75
|
||||
range 2 100
|
||||
depends on STM32_HCIUART_SW_RXFLOW
|
||||
---help---
|
||||
If software RTS flow control is enable, then RTS will be asserted
|
||||
when this amount of Rx data has been buffered. The amount is
|
||||
expressed as a percentage of the Rx buffer size.
|
||||
|
||||
config STM32_HCIUART_LOWER_WATERMARK
|
||||
int "RTS flow control lower watermark (%)"
|
||||
default 25
|
||||
range 1 99
|
||||
depends on STM32_HCIUART_SW_RXFLOW
|
||||
---help---
|
||||
If software RTS flow control is enable, then RTS will be de-asserted
|
||||
when there is less than this amount ofdata in the Rx buffere. The
|
||||
amount is expressed as a percentage of the Rx buffer size.
|
||||
|
||||
endmenu # HCI UART Driver Configuration
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,313 @@
|
||||
#
|
||||
# STM32 I2C configuration options.
|
||||
#
|
||||
|
||||
# TODO: generalize H5 specific options !
|
||||
|
||||
config STM32_I2C_SLAVE
|
||||
bool
|
||||
default n
|
||||
|
||||
menu "I2C Configuration H5-specific"
|
||||
depends on STM32_HAVE_I2C_H5
|
||||
|
||||
menu "Clock Selection"
|
||||
|
||||
choice
|
||||
depends on STM32_I2C1
|
||||
prompt "I2C1 Input Clock Selection"
|
||||
default STM32_I2C1_CLK_PCLK1
|
||||
|
||||
config STM32_I2C1_CLK_CSI
|
||||
bool "CSI"
|
||||
|
||||
config STM32_I2C1_CLK_HSI
|
||||
bool "HSI"
|
||||
|
||||
config STM32_I2C1_CLK_PCLK1
|
||||
bool "PCLK1"
|
||||
|
||||
config STM32_I2C1_CLK_PLL3R
|
||||
bool "PLL3R"
|
||||
|
||||
endchoice # I2C1 Input Clock Selection
|
||||
|
||||
choice
|
||||
depends on STM32_I2C2
|
||||
prompt "I2C2 Input Clock Selection"
|
||||
default STM32_I2C2_CLK_PCLK1
|
||||
|
||||
config STM32_I2C2_CLK_CSI
|
||||
bool "CSI"
|
||||
|
||||
config STM32_I2C2_CLK_HSI
|
||||
bool "HSI"
|
||||
|
||||
config STM32_I2C2_CLK_PCLK1
|
||||
bool "PCLK1"
|
||||
|
||||
config STM32_I2C2_CLK_PLL3R
|
||||
bool "PLL3R"
|
||||
|
||||
endchoice # I2C2 Input Clock Selection
|
||||
|
||||
choice
|
||||
depends on STM32_I2C3
|
||||
prompt "I2C3 Input Clock Selection"
|
||||
default STM32_I2C3_CLK_PCLK3
|
||||
|
||||
config STM32_I2C3_CLK_CSI
|
||||
bool "CSI"
|
||||
|
||||
config STM32_I2C3_CLK_HSI
|
||||
bool "HSI"
|
||||
|
||||
config STM32_I2C3_CLK_PCLK3
|
||||
bool "PCLK3"
|
||||
|
||||
config STM32_I2C3_CLK_PLL3R
|
||||
bool "PLL3R"
|
||||
|
||||
endchoice # I2C3 Input Clock Selection
|
||||
|
||||
choice
|
||||
depends on STM32_I2C4
|
||||
prompt "I2C4 Input Clock Selection"
|
||||
default STM32_I2C4_CLK_PCLK3
|
||||
|
||||
config STM32_I2C4_CLK_CSI
|
||||
bool "CSI"
|
||||
|
||||
config STM32_I2C4_CLK_HSI
|
||||
bool "HSI"
|
||||
|
||||
config STM32_I2C4_CLK_PCLK3
|
||||
bool "PCLK3"
|
||||
|
||||
config STM32_I2C4_CLK_PLL3R
|
||||
bool "PLL3R"
|
||||
|
||||
endchoice # I2C4 Input Clock Selection
|
||||
|
||||
endmenu # Clock Selection
|
||||
|
||||
menu "Rise/Fall Override"
|
||||
|
||||
config STM32_I2C1_RF_OVERRIDE
|
||||
bool "I2C1"
|
||||
default n
|
||||
depends on STM32_I2C1
|
||||
|
||||
config STM32_I2C2_RF_OVERRIDE
|
||||
bool "I2C2"
|
||||
default n
|
||||
depends on STM32_I2C2
|
||||
|
||||
config STM32_I2C3_RF_OVERRIDE
|
||||
bool "I2C3"
|
||||
default n
|
||||
depends on STM32_I2C3
|
||||
|
||||
config STM32_I2C4_RF_OVERRIDE
|
||||
bool "I2C4"
|
||||
default n
|
||||
depends on STM32_I2C4
|
||||
|
||||
menu "Rise/Fall Values"
|
||||
|
||||
config STM32_I2C1_RISE
|
||||
int "I2C1 Rise Time (ns)"
|
||||
range 0 1000
|
||||
default 20
|
||||
depends on STM32_I2C1_RF_OVERRIDE
|
||||
|
||||
config STM32_I2C1_FALL
|
||||
int "I2C1 Fall Time (ns)"
|
||||
range 0 300
|
||||
default 20
|
||||
depends on STM32_I2C1_RF_OVERRIDE
|
||||
|
||||
config STM32_I2C2_RISE
|
||||
int "I2C2 Rise Time (ns)"
|
||||
range 0 1000
|
||||
default 20
|
||||
depends on STM32_I2C2_RF_OVERRIDE
|
||||
|
||||
config STM32_I2C2_FALL
|
||||
int "I2C2 Fall Time (ns)"
|
||||
range 0 300
|
||||
default 20
|
||||
depends on STM32_I2C2_RF_OVERRIDE
|
||||
|
||||
config STM32_I2C3_RISE
|
||||
int "I2C3 Rise Time (ns)"
|
||||
range 0 1000
|
||||
default 20
|
||||
depends on STM32_I2C3_RF_OVERRIDE
|
||||
|
||||
config STM32_I2C3_FALL
|
||||
int "I2C3 Fall Time (ns)"
|
||||
range 0 300
|
||||
default 20
|
||||
depends on STM32_I2C3_RF_OVERRIDE
|
||||
|
||||
config STM32_I2C4_RISE
|
||||
int "I2C4 Rise Time (ns)"
|
||||
range 0 1000
|
||||
default 20
|
||||
depends on STM32_I2C4_RF_OVERRIDE
|
||||
|
||||
config STM32_I2C4_FALL
|
||||
int "I2C4 Fall Time (ns)"
|
||||
range 0 300
|
||||
default 20
|
||||
depends on STM32_I2C4_RF_OVERRIDE
|
||||
|
||||
endmenu # Rise/Fall Values
|
||||
|
||||
endmenu # Rise/Fall Override
|
||||
|
||||
menu "Filtering"
|
||||
|
||||
menu "Digital Filters"
|
||||
|
||||
config STM32_I2C1_DNF
|
||||
int "I2C1 Digital Noise Filter"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on STM32_I2C1
|
||||
|
||||
config STM32_I2C2_DNF
|
||||
int "I2C2 Digital Noise Filter"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on STM32_I2C2
|
||||
|
||||
config STM32_I2C3_DNF
|
||||
int "I2C3 Digital Noise Filter"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on STM32_I2C3
|
||||
|
||||
config STM32_I2C4_DNF
|
||||
int "I2C4 Digital Noise Filter"
|
||||
range 0 15
|
||||
default 0
|
||||
depends on STM32_I2C4
|
||||
|
||||
endmenu # Digital Filters
|
||||
|
||||
menu "Analog Filters"
|
||||
|
||||
config STM32_I2C1_ANFOFF
|
||||
int "Turn off I2C1 Analog Filter (0=on, 1=off)"
|
||||
default 1
|
||||
range 0 1
|
||||
depends on STM32_I2C1
|
||||
|
||||
config STM32_I2C2_ANFOFF
|
||||
int "Turn off I2C2 Analog Filter (0=on, 1=off)"
|
||||
default 1
|
||||
range 0 1
|
||||
depends on STM32_I2C2
|
||||
|
||||
config STM32_I2C3_ANFOFF
|
||||
int "Turn off I2C3 Analog Filter (0=on, 1=off)"
|
||||
default 1
|
||||
range 0 1
|
||||
depends on STM32_I2C3
|
||||
|
||||
config STM32_I2C4_ANFOFF
|
||||
int "Turn off I2C4 Analog Filter (0=on, 1=off)"
|
||||
default 1
|
||||
range 0 1
|
||||
depends on STM32_I2C4
|
||||
|
||||
endmenu # Analog Filters
|
||||
|
||||
endmenu # Filtering
|
||||
|
||||
endmenu # "I2C Configuration"
|
||||
|
||||
if !STM32_HAVE_I2C_H5
|
||||
|
||||
config STM32_I2C_DYNTIMEO
|
||||
bool "Use dynamic timeouts"
|
||||
depends on STM32_I2C
|
||||
|
||||
config STM32_I2C_DYNTIMEO_USECPERBYTE
|
||||
int "Timeout Microseconds per Byte"
|
||||
depends on STM32_I2C && STM32_I2C_DYNTIMEO
|
||||
default 500
|
||||
|
||||
config STM32_I2C_DYNTIMEO_STARTSTOP
|
||||
int "Timeout for Start/Stop (Milliseconds)"
|
||||
depends on STM32_I2C && STM32_I2C_DYNTIMEO
|
||||
default 1000
|
||||
|
||||
config STM32_I2CTIMEOSEC
|
||||
int "Timeout seconds"
|
||||
depends on STM32_I2C
|
||||
default 0
|
||||
|
||||
config STM32_I2CTIMEOMS
|
||||
int "Timeout Milliseconds"
|
||||
depends on STM32_I2C && !STM32_I2C_DYNTIMEO
|
||||
default 500
|
||||
|
||||
config STM32_I2CTIMEOTICKS
|
||||
int "Timeout for Done and Stop (ticks)"
|
||||
depends on STM32_I2C && !STM32_I2C_DYNTIMEO
|
||||
default 500
|
||||
|
||||
config STM32_I2C_ALT
|
||||
bool "Alternate I2C implementation"
|
||||
default STM32F1_PERFORMANCELINE
|
||||
depends on !STM32_STM32F30XX && STM32_COMMON_LEGACY
|
||||
---help---
|
||||
This selection enables an alternative I2C driver. This alternate
|
||||
driver implements some rather complex workarounds for errata against
|
||||
the STM32 F103 "Performance Line". This selection is an option
|
||||
because: (1) It has not yet been fully verified and (2) It is not
|
||||
certain that he scope of this workaround is needed only for the F103.
|
||||
|
||||
config STM32_I2C_DUTY16_9
|
||||
bool "Frequency with Tlow/Thigh = 16/9"
|
||||
default n
|
||||
depends on STM32_I2C && STM32_COMMON_LEGACY
|
||||
|
||||
config STM32_I2C_DMA
|
||||
bool "I2C DMA Support"
|
||||
default n
|
||||
depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED
|
||||
---help---
|
||||
This option enables the DMA for I2C transfers.
|
||||
Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the
|
||||
I2C dma streams, else the default priority level is set to medium.
|
||||
|
||||
menu "I2C Slave Configuration"
|
||||
depends on STM32_I2C_SLAVE
|
||||
|
||||
config STM32_I2C_SLAVE_DEFAULT_TX
|
||||
hex "Default TX byte to be sent when the TX buffer is empty"
|
||||
default 0xFF
|
||||
|
||||
config STM32_I2C_SLAVE_USEWQ
|
||||
bool "Use work queue to delegate the isr completion status"
|
||||
default n
|
||||
---help---
|
||||
With the current upperhalf I2C slave driver implementation, the user
|
||||
should delegate the callback completion status using a work queue.
|
||||
However, work queues introduce a delay, so in certain scenarios
|
||||
it is better to use a custom driver without using a work queue.
|
||||
|
||||
config STM32_I2C_SLAVE_RETRANSFER
|
||||
bool "The frame is retransferred when stop is issued beforehand"
|
||||
default n
|
||||
---help---
|
||||
If stop is issued before the whole frame is transferred,
|
||||
the tx pointer is reset to 0.
|
||||
|
||||
endmenu
|
||||
|
||||
endif # !STM32_HAVE_I2C_H5
|
||||
@@ -0,0 +1,91 @@
|
||||
#
|
||||
# STM32 common IPCC options.
|
||||
#
|
||||
|
||||
config STM32_IPCC_CHAN1_RX_SIZE
|
||||
int "Channel 1 RX size"
|
||||
default 256
|
||||
depends on STM32_IPCC
|
||||
---help---
|
||||
Size of the receive buffer. Another CPU will write to this buffer and
|
||||
the currently running CPU will read from it.
|
||||
|
||||
config STM32_IPCC_CHAN1_TX_SIZE
|
||||
int "Channel 1 TX size"
|
||||
default 256
|
||||
depends on STM32_IPCC
|
||||
---help---
|
||||
Size of the send buffer. Another CPU will read from this buffer and
|
||||
the currently running CPU will write to it.
|
||||
|
||||
config STM32_IPCC_CHAN2
|
||||
bool "Enable channel 2"
|
||||
depends on STM32_IPCC
|
||||
|
||||
if STM32_IPCC_CHAN2
|
||||
|
||||
config STM32_IPCC_CHAN2_RX_SIZE
|
||||
int "Channel 2 RX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN2_TX_SIZE
|
||||
int "Channel 2 TX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN3
|
||||
bool "Enable channel 3"
|
||||
|
||||
if STM32_IPCC_CHAN3
|
||||
|
||||
config STM32_IPCC_CHAN3_RX_SIZE
|
||||
int "Channel 3 RX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN3_TX_SIZE
|
||||
int "Channel 3 TX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN4
|
||||
bool "Enable channel 4"
|
||||
|
||||
if STM32_IPCC_CHAN4
|
||||
|
||||
config STM32_IPCC_CHAN4_RX_SIZE
|
||||
int "Channel 4 RX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN4_TX_SIZE
|
||||
int "Channel 4 TX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN5
|
||||
bool "Enable channel 5"
|
||||
|
||||
if STM32_IPCC_CHAN5
|
||||
|
||||
config STM32_IPCC_CHAN5_RX_SIZE
|
||||
int "Channel 5 RX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN5_TX_SIZE
|
||||
int "Channel 5 TX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN6
|
||||
bool "Enable channel 6"
|
||||
|
||||
if STM32_IPCC_CHAN6
|
||||
|
||||
config STM32_IPCC_CHAN6_RX_SIZE
|
||||
int "Channel 6 RX size"
|
||||
default 256
|
||||
|
||||
config STM32_IPCC_CHAN6_TX_SIZE
|
||||
int "Channel 6 TX size"
|
||||
default 256
|
||||
|
||||
endif # STM32_IPCC_CHAN2
|
||||
endif # STM32_IPCC_CHAN3
|
||||
endif # STM32_IPCC_CHAN4
|
||||
endif # STM32_IPCC_CHAN5
|
||||
endif # STM32_IPCC_CHAN6
|
||||
@@ -0,0 +1,69 @@
|
||||
#
|
||||
# STM32 common LPUART options.
|
||||
#
|
||||
|
||||
config LPUART1_RXDMA
|
||||
bool
|
||||
depends on STM32_LPUART1 && LPUART1_SERIALDRIVER && STM32_DMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
choice
|
||||
prompt "LPUART1 Driver Configuration"
|
||||
depends on STM32_LPUART1
|
||||
default STM32_LPUART1_SERIALDRIVER
|
||||
|
||||
config STM32_LPUART1_SERIALDRIVER
|
||||
bool "Standard serial driver"
|
||||
select LPUART1_SERIALDRIVER
|
||||
select ARCH_HAVE_SERIAL_TERMIOS
|
||||
select STM32_SERIALDRIVER
|
||||
|
||||
config STM32_LPUART1_1WIREDRIVER
|
||||
bool "1-Wire driver"
|
||||
select STM32_1WIREDRIVER
|
||||
|
||||
endchoice # LPUART1 Driver Configuration
|
||||
|
||||
config LPUART1_RS485
|
||||
bool "RS-485 on LPUART1"
|
||||
depends on STM32_LPUART1 && LPUART1_SERIALDRIVER
|
||||
---help---
|
||||
Enable RS-485 interface on LPUART1. Your board config will have to
|
||||
provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be
|
||||
used with LPUART1_RXDMA.
|
||||
|
||||
if LPUART1_RS485
|
||||
|
||||
config LPUART1_RS485_DIR_POLARITY
|
||||
int "LPUART1 RS-485 DIR pin polarity"
|
||||
default 1
|
||||
range 0 1
|
||||
---help---
|
||||
Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which
|
||||
enables TX (0 - low / nTXEN, 1 - high / TXEN).
|
||||
|
||||
endif # LPUART1_RS485
|
||||
|
||||
if STM32_LPUART1_SERIALDRIVER
|
||||
|
||||
config LPUART1_TXDMA
|
||||
bool "LPUART1 Tx DMA"
|
||||
default n
|
||||
depends on STM32_DMA1
|
||||
---help---
|
||||
In high data rate usage, Tx DMA may reduce CPU load
|
||||
|
||||
endif # STM32_LPUART1_SERIALDRIVER
|
||||
|
||||
config LPUART1_UNCONFIG_RX_ON_CLOSE
|
||||
bool "Unconfigure LPUART1 RX pin on close"
|
||||
depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER
|
||||
|
||||
config LPUART1_UNCONFIG_TX_ON_CLOSE
|
||||
bool "Unconfigure LPUART1 TX pin on close"
|
||||
depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER
|
||||
|
||||
config LPUART1_UNCONFIG_DIR_ON_CLOSE
|
||||
bool "Unconfigure LPUART1 DIR pin on close"
|
||||
depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485
|
||||
@@ -0,0 +1,233 @@
|
||||
#
|
||||
# STM32 common LTDC options.
|
||||
#
|
||||
|
||||
choice
|
||||
prompt "Layer 1 color format"
|
||||
depends on STM32_LTDC
|
||||
default STM32_LTDC_L1_RGB565
|
||||
|
||||
config STM32_LTDC_L1_L8
|
||||
bool "8 bpp L8 (8-bit CLUT)"
|
||||
depends on STM32_FB_CMAP
|
||||
|
||||
config STM32_LTDC_L1_AL44
|
||||
bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)"
|
||||
depends on STM32_FB_CMAP
|
||||
|
||||
config STM32_LTDC_L1_AL88
|
||||
bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)"
|
||||
depends on STM32_FB_CMAP
|
||||
|
||||
config STM32_LTDC_L1_RGB565
|
||||
bool "16 bpp RGB 565"
|
||||
depends on !STM32_FB_CMAP
|
||||
|
||||
config STM32_LTDC_L1_ARGB4444
|
||||
bool "16 bpp ARGB 4444"
|
||||
depends on !STM32_FB_CMAP
|
||||
|
||||
config STM32_LTDC_L1_ARGB1555
|
||||
bool "16 bpp ARGB 1555"
|
||||
depends on !STM32_FB_CMAP
|
||||
|
||||
config STM32_LTDC_L1_RGB888
|
||||
bool "24 bpp RGB 888"
|
||||
depends on !STM32_FB_CMAP
|
||||
|
||||
config STM32_LTDC_L1_ARGB8888
|
||||
bool "32 bpp ARGB 8888"
|
||||
depends on !STM32_FB_CMAP
|
||||
|
||||
endchoice # Layer 1 color format
|
||||
|
||||
choice
|
||||
prompt "Layer 2 (top layer) color format"
|
||||
depends on STM32_LTDC && STM32_LTDC_L2
|
||||
default STM32_LTDC_L2_RGB565
|
||||
|
||||
config STM32_LTDC_L2_L8
|
||||
bool "8 bpp L8 (8-bit CLUT)"
|
||||
depends on STM32_LTDC_L1_L8
|
||||
|
||||
config STM32_LTDC_L2_AL44
|
||||
bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)"
|
||||
depends on STM32_LTDC_L1_AL44
|
||||
|
||||
config STM32_LTDC_L2_AL88
|
||||
bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)"
|
||||
depends on STM32_LTDC_L1_AL88
|
||||
|
||||
config STM32_LTDC_L2_RGB565
|
||||
bool "16 bpp RGB 565"
|
||||
depends on STM32_LTDC_L1_RGB565
|
||||
|
||||
config STM32_LTDC_L2_ARGB4444
|
||||
bool "16 bpp ARGB 4444"
|
||||
depends on STM32_LTDC_L1_ARGB4444
|
||||
|
||||
config STM32_LTDC_L2_ARGB1555
|
||||
bool "16 bpp ARGB 1555"
|
||||
depends on STM32_LTDC_L1_ARGB1555
|
||||
|
||||
config STM32_LTDC_L2_RGB888
|
||||
bool "24 bpp RGB 888"
|
||||
depends on STM32_LTDC_L1_RGB888
|
||||
|
||||
config STM32_LTDC_L2_ARGB8888
|
||||
bool "32 bpp ARGB 8888"
|
||||
depends on STM32_LTDC_L1_ARGB8888
|
||||
|
||||
endchoice # Layer 2 color format
|
||||
|
||||
if STM32_LTDC
|
||||
|
||||
config STM32_LTDC_BACKLIGHT
|
||||
bool "Backlight support"
|
||||
default y
|
||||
|
||||
config STM32_LTDC_DEFBACKLIGHT
|
||||
hex "Default backlight level"
|
||||
default 0xf0
|
||||
|
||||
config STM32_LTDC_BACKCOLOR
|
||||
hex "Background color"
|
||||
default 0x0
|
||||
---help---
|
||||
This is the background color that will be used as the LTDC
|
||||
background layer color. It is an RGB888 format value.
|
||||
|
||||
config STM32_LTDC_DITHER
|
||||
bool "Dither support"
|
||||
|
||||
config STM32_LTDC_FB_DOUBLE_BUFFER
|
||||
bool "Enable double buffering"
|
||||
depends on ARCH_CHIP_STM32H7
|
||||
default n
|
||||
---help---
|
||||
Enable double buffering to allow updates to the framebuffer while
|
||||
the display is being refreshed. This configuration requires two
|
||||
framebuffers: one active and one inactive. When the display
|
||||
refreshes, the active and inactive framebuffers are swapped,
|
||||
enabling smooth and flicker-free updates.
|
||||
|
||||
if STM32_LTDC_DITHER
|
||||
|
||||
config STM32_LTDC_DITHER_RED
|
||||
int "Dither red width"
|
||||
range 0 7
|
||||
default 2
|
||||
---help---
|
||||
This is the dither red width.
|
||||
|
||||
config STM32_LTDC_DITHER_GREEN
|
||||
int "Dither green width"
|
||||
range 0 7
|
||||
default 2
|
||||
---help---
|
||||
This is the dither green width.
|
||||
|
||||
config STM32_LTDC_DITHER_BLUE
|
||||
int "Dither blue width"
|
||||
range 0 7
|
||||
default 2
|
||||
---help---
|
||||
This is the dither blue width.
|
||||
|
||||
endif # STM32_LTDC_DITHER
|
||||
|
||||
config STM32_LTDC_FB_BASE
|
||||
hex "Framebuffer memory start address"
|
||||
default 0
|
||||
---help---
|
||||
If you are using the LTDC, then you must provide the address
|
||||
of the start of the framebuffer. This address will typically
|
||||
be in the SRAM or SDRAM memory region of the FSMC/FMC.
|
||||
|
||||
config STM32_LTDC_FB_SIZE
|
||||
int "Framebuffer memory size (bytes)"
|
||||
default 0
|
||||
---help---
|
||||
Must be the whole size of the active LTDC layer.
|
||||
|
||||
config STM32_LTDC_L1_CHROMAKEYEN
|
||||
bool "Enable chromakey support for layer 1"
|
||||
default y
|
||||
|
||||
config STM32_LTDC_L1_CHROMAKEY
|
||||
hex "Layer L1 initial chroma key"
|
||||
default 0x00000000
|
||||
|
||||
config STM32_LTDC_L1_COLOR
|
||||
hex "Layer L1 default color"
|
||||
default 0x00000000
|
||||
|
||||
config STM32_LTDC_L2
|
||||
bool "Enable Layer 2 support"
|
||||
default y
|
||||
|
||||
if STM32_LTDC_L2
|
||||
|
||||
config STM32_LTDC_L2_COLOR
|
||||
hex "Layer L2 default color"
|
||||
default 0x00000000
|
||||
|
||||
config STM32_LTDC_L2_CHROMAKEYEN
|
||||
bool "Enable chromakey support for layer 2"
|
||||
default y
|
||||
|
||||
config STM32_LTDC_L2_CHROMAKEY
|
||||
hex "Layer L2 initial chroma key"
|
||||
default 0x00000000
|
||||
|
||||
endif # STM32_LTDC_L2
|
||||
|
||||
config STM32_FB_CMAP
|
||||
bool "Color map support"
|
||||
default y
|
||||
select FB_CMAP
|
||||
---help---
|
||||
Enabling color map support is necessary for LTDC L8 format.
|
||||
|
||||
config STM32_FB_TRANSPARENCY
|
||||
bool "Transparency color map support"
|
||||
depends on STM32_FB_CMAP
|
||||
default y
|
||||
select FB_TRANSPARENCY
|
||||
---help---
|
||||
Enabling transparency color map support is necessary for LTDC L8 format.
|
||||
|
||||
config STM32_LTDC_REGDEBUG
|
||||
bool "LTDC Register level debug"
|
||||
depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7
|
||||
---help---
|
||||
Output detailed register-level LTDC device debug information.
|
||||
|
||||
endif # STM32_LTDC
|
||||
|
||||
config STM32_LTDC_USE_DSI
|
||||
bool "Use DSI as display connection"
|
||||
depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST
|
||||
---help---
|
||||
Select this if your display is connected via DSI.
|
||||
Deselect option if your display is connected via digital
|
||||
RGB+HSYNC+VSYNC
|
||||
|
||||
if STM32_LCD
|
||||
|
||||
choice
|
||||
prompt "Segment LCD Clock Source"
|
||||
default LCD_LSECLOCK
|
||||
|
||||
config LCD_LSICLOCK
|
||||
bool "Internal Low Speed Clock"
|
||||
|
||||
config LCD_LSECLOCK
|
||||
bool "External Low Speed Clock"
|
||||
|
||||
config LCD_HSECLOCK
|
||||
bool "External High Speed Clock"
|
||||
|
||||
endchoice
|
||||
|
||||
endif # STM32_LCD
|
||||
@@ -0,0 +1,168 @@
|
||||
#
|
||||
# STM32 memory configuration options.
|
||||
#
|
||||
|
||||
config STM32_SRAM5_HEAP
|
||||
bool "SRAM5 is used for heap"
|
||||
depends on STM32_SRAM5
|
||||
default n
|
||||
|
||||
config STM32_EXTERNAL_RAM
|
||||
bool "External RAM on FSMC/FMC"
|
||||
depends on STM32_FSMC || STM32_FMC
|
||||
select ARCH_HAVE_HEAP2
|
||||
---help---
|
||||
In addition to internal SRAM, external RAM may be available through the FSMC/FMC.
|
||||
|
||||
config STM32_BBSRAM_FILES
|
||||
int "Max Files to support in BBSRAM"
|
||||
depends on STM32_BBSRAM
|
||||
default 4
|
||||
|
||||
config STM32_SAVE_CRASHDUMP
|
||||
bool "Enable Saving Panic to BBSRAM"
|
||||
depends on STM32_BBSRAM
|
||||
|
||||
config STM32_DTCMEXCLUDE
|
||||
bool "Exclude DTCM SRAM from the heap"
|
||||
depends on ARMV7M_HAVE_DTCM
|
||||
default LIBC_ARCH_ELF
|
||||
---help---
|
||||
Exclude DTCM SRAM from the HEAP because it appears to be impossible
|
||||
to execute ELF modules from DTCM RAM (REVISIT!).
|
||||
|
||||
config STM32_DTCM_PROCFS
|
||||
bool "DTCM SRAM PROCFS support"
|
||||
depends on ARMV7M_DTCM && FS_PROCFS
|
||||
---help---
|
||||
Select to build in support for /proc/dtcm. Reading from /proc/dtcm
|
||||
will provide statistics about DTCM memory use similar to what you
|
||||
would get from mallinfo() for the user heap.
|
||||
|
||||
config STM32_SRAM2_HEAP
|
||||
bool "SRAM2 is used for heap"
|
||||
depends on STM32_COMMON_SRAM2_OPTIONS
|
||||
select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2
|
||||
---help---
|
||||
The STM32L4 SRAM2 region has special properties (power, protection, parity)
|
||||
which may be used by the application for special purposes. But if these
|
||||
special properties are not needed, it may be instead added to the heap for
|
||||
use by malloc().
|
||||
NOTE: you must also select an appropriate number of memory regions in the
|
||||
'Memory Management' section.
|
||||
|
||||
config STM32_SRAM2_INIT
|
||||
bool "SRAM2 is initialized to zero"
|
||||
depends on STM32_COMMON_SRAM2_OPTIONS
|
||||
---help---
|
||||
The STM32L4 SRAM2 region has parity checking. However, when the system
|
||||
powers on, the memory is in an unknown state, and reads from uninitialized
|
||||
memory can trigger parity faults from the random data. This can be
|
||||
avoided by first writing to all locations to force the parity into a valid
|
||||
state.
|
||||
However, if the SRAM2 is being used for it's battery-backed capability,
|
||||
this may be undesirable (because it will destroy the contents). In that
|
||||
case, the board should handle the initialization itself at the appropriate
|
||||
time.
|
||||
|
||||
config STM32_SRAM3_HEAP
|
||||
bool "SRAM3 is used for heap"
|
||||
depends on STM32_SRAM3
|
||||
default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR
|
||||
---help---
|
||||
Add the STM32L4 SRAM3 to the heap for use by malloc().
|
||||
NOTE: you must also select an appropriate number of memory regions in the
|
||||
'Memory Management' section.
|
||||
|
||||
config STM32_CCMEXCLUDE
|
||||
bool "Exclude CCM SRAM from the heap"
|
||||
default ARCH_DMA || LIBC_ARCH_ELF
|
||||
depends on STM32_HAVE_CCM
|
||||
---help---
|
||||
Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA
|
||||
and (2) it appears to be impossible to execute ELF modules from CCM
|
||||
RAM.
|
||||
|
||||
config STM32_CCM_PROCFS
|
||||
bool "CCM PROCFS support"
|
||||
default n
|
||||
depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER
|
||||
---help---
|
||||
Select to build in support for /proc/ccm. Reading from /proc/ccm
|
||||
will provide statistics about CCM memory use similar to what you
|
||||
would get from mallinfo() for the user heap.
|
||||
|
||||
comment "STM32WB SRAM2a and SRAM2b Options"
|
||||
depends on STM32_HAVE_SRAM2A || STM32_HAVE_SRAM2B
|
||||
|
||||
config STM32_SRAM2A_HEAP
|
||||
bool "SRAM2a is used for heap"
|
||||
depends on STM32_HAVE_SRAM2A
|
||||
default n
|
||||
|
||||
config STM32_SRAM2A_USER_BASE_OFFSET
|
||||
int "SRAM2a user application base offset"
|
||||
default 2048
|
||||
range 0 32768
|
||||
depends on STM32_SRAM2A_HEAP
|
||||
---help---
|
||||
The beginning part of the SRAM2a memory can be used by RF stack. The
|
||||
available space for the user application can be obtained from the
|
||||
release notes for STM32WB coprocessor wireless binaries.
|
||||
|
||||
config STM32_SRAM2A_USER_SIZE
|
||||
int "SRAM2a user application size"
|
||||
default 8192
|
||||
range 0 32768
|
||||
depends on STM32_SRAM2A_HEAP
|
||||
---help---
|
||||
The ending part of the SRAM2a memory contains a secure section, which
|
||||
cannot be read nor written by CPU1. The secure start address for the
|
||||
SRAM2a memory can be read from the SBRSA option byte. When CPU2 update
|
||||
support required, there must be some free sectors just below the secure
|
||||
memory to support CPU2 firmware updates requiring more sectors to be
|
||||
secure.
|
||||
|
||||
config STM32_SRAM2A_INIT
|
||||
bool "SRAM2a is initialized to zero"
|
||||
default y
|
||||
depends on STM32_SRAM2A_HEAP
|
||||
---help---
|
||||
The STM32WB SRAM2a region has parity checking. However, when the system
|
||||
powers on, the memory is in an unknown state, and reads from uninitialized
|
||||
memory can trigger parity faults from the random data. This can be
|
||||
avoided by first writing to all locations to force the parity into a valid
|
||||
state.
|
||||
However, if the SRAM2a is being retained in Standby mode, this may be
|
||||
undesirable (because it will destroy the contents). In that case, the board
|
||||
should handle the initialization itself at the appropriate time.
|
||||
|
||||
config STM32_SRAM2B_HEAP
|
||||
bool "SRAM2b is used for heap"
|
||||
depends on STM32_HAVE_SRAM2B
|
||||
default n
|
||||
|
||||
config STM32_SRAM2B_USER_SIZE
|
||||
int "SRAM2b user application size"
|
||||
default 32768
|
||||
range 0 32768
|
||||
depends on STM32_SRAM2B_HEAP
|
||||
---help---
|
||||
For any CPU2 firmware supporting the BLE protocol the ending part of
|
||||
the SRAM2b memory contains a secure section, which cannot be read nor
|
||||
written by CPU1. The secure start address for the SRAM2b memory can be
|
||||
read from the SNBRSA option byte. When CPU2 update support required,
|
||||
there must be some free sectors just below the secure memory to support
|
||||
CPU2 firmware updates requiring more sectors to be secure. The SRAM2b
|
||||
memory is all secure for any CPU2 firmware supporting the Thread protocol.
|
||||
|
||||
config STM32_SRAM2B_INIT
|
||||
bool "SRAM2b is initialized to zero"
|
||||
default y
|
||||
depends on STM32_SRAM2B_HEAP
|
||||
---help---
|
||||
The STM32WB SRAM2b region has parity checking. However, when the system
|
||||
powers on, the memory is in an unknown state, and reads from uninitialized
|
||||
memory can trigger parity faults from the random data. This can be
|
||||
avoided by first writing to all locations to force the parity into a valid
|
||||
state.
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,158 @@
|
||||
#
|
||||
# STM32 QSPI/OCTOSPI configuration options.
|
||||
#
|
||||
|
||||
choice
|
||||
prompt "DMA Channel"
|
||||
default STM32_QSPI_DMA_CHAN_1_5
|
||||
depends on ARCH_CHIP_STM32L4
|
||||
---help---
|
||||
You can choose between two DMA channels for use with QSPI:
|
||||
either DMA1 channel 5, or DMA2 channel 7.
|
||||
If you only see one choice here, it is probably because
|
||||
you have not also enabled the associated DMA controller.
|
||||
|
||||
config STM32_QSPI_DMA_CHAN_1_5
|
||||
bool "DMA1 Channel 5"
|
||||
depends on STM32_DMA1 && !STM32_DMAMUX
|
||||
---help---
|
||||
Use DMA1 channel 5 for QSPI.
|
||||
|
||||
config STM32_QSPI_DMA_CHAN_2_7
|
||||
bool "DMA2 Channel 7"
|
||||
depends on STM32_DMA2 && !STM32_DMAMUX
|
||||
---help---
|
||||
Use DMA2 channel 7 for QSPI.
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Transfer technique"
|
||||
default STM32_QSPI_DMA
|
||||
---help---
|
||||
You can choose between using polling, interrupts, or DMA to transfer data
|
||||
over the QSPI interface.
|
||||
|
||||
config STM32_QSPI_POLLING
|
||||
bool "Polling"
|
||||
---help---
|
||||
Use conventional register I/O with status polling to transfer data.
|
||||
|
||||
config STM32_QSPI_INTERRUPTS
|
||||
bool "Interrupts"
|
||||
---help---
|
||||
User interrupt driven I/O transfers.
|
||||
|
||||
config STM32_QSPI_DMA
|
||||
bool "DMA"
|
||||
depends on STM32_DMA
|
||||
---help---
|
||||
Use DMA to improve QSPI transfer performance.
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Bank selection"
|
||||
default STM32_QSPI_MODE_BANK1
|
||||
---help---
|
||||
You can choose between using polling, interrupts, or DMA to transfer data
|
||||
over the QSPI interface.
|
||||
|
||||
config STM32_QSPI_MODE_BANK1
|
||||
bool "Bank 1"
|
||||
|
||||
config STM32_QSPI_MODE_BANK2
|
||||
bool "Bank 2"
|
||||
|
||||
config STM32_QSPI_MODE_DUAL
|
||||
bool "Dual Bank"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "DMA Priority"
|
||||
depends on STM32_QSPI_DMA && STM32_DMA
|
||||
default STM32_QSPI_DMAPRIORITY_MEDIUM
|
||||
---help---
|
||||
The DMA controller supports priority levels. You are probably fine
|
||||
with the default of 'medium' except for special cases. In the event
|
||||
of contention between to channels at the same priority, the lower
|
||||
numbered channel has hardware priority over the higher numbered one.
|
||||
|
||||
config STM32_QSPI_DMAPRIORITY_VERYHIGH
|
||||
bool "Very High priority"
|
||||
depends on STM32_DMA
|
||||
---help---
|
||||
'Highest' priority.
|
||||
|
||||
config STM32_QSPI_DMAPRIORITY_HIGH
|
||||
bool "High priority"
|
||||
depends on STM32_DMA
|
||||
---help---
|
||||
'High' priority.
|
||||
|
||||
config STM32_QSPI_DMAPRIORITY_MEDIUM
|
||||
bool "Medium priority"
|
||||
depends on STM32_DMA
|
||||
---help---
|
||||
'Medium' priority.
|
||||
|
||||
config STM32_QSPI_DMAPRIORITY_LOW
|
||||
bool "Low priority"
|
||||
depends on STM32_DMA
|
||||
---help---
|
||||
'Low' priority.
|
||||
|
||||
endchoice
|
||||
|
||||
config STM32_QSPI_FLASH_SIZE
|
||||
int "Size of attached serial flash, bytes"
|
||||
default 16777216
|
||||
range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI
|
||||
range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1
|
||||
---help---
|
||||
The STM32F7 QSPI peripheral requires the size of the Flash be specified
|
||||
|
||||
config STM32_QSPI_FIFO_THESHOLD
|
||||
int "Number of bytes before asserting FIFO threshold flag"
|
||||
default 4
|
||||
range 1 16 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI
|
||||
range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1
|
||||
---help---
|
||||
The STM32F7 QSPI peripheral requires that the FIFO threshold be specified
|
||||
I would leave it at the default value of 4 unless you know what you are doing.
|
||||
|
||||
config STM32_QSPI_CSHT
|
||||
int "Number of cycles Chip Select must be inactive between transactions"
|
||||
default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1
|
||||
default 1
|
||||
range 1 8 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI
|
||||
range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1
|
||||
---help---
|
||||
The STM32F7 QSPI peripheral requires that it be specified the minimum number
|
||||
of AHB cycles that Chip Select be held inactive between transactions.
|
||||
|
||||
config STM32_QSPI_DMATHRESHOLD
|
||||
int "QSPI DMA threshold"
|
||||
depends on STM32_QSPI_DMA
|
||||
default 4
|
||||
---help---
|
||||
When QSPI DMA is enabled, small DMA transfers will still be performed
|
||||
by polling logic. This value is the threshold below which transfers
|
||||
will still be performed by conventional register status polling.
|
||||
|
||||
config STM32_QSPI_DMADEBUG
|
||||
bool "QSPI DMA transfer debug"
|
||||
depends on STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA
|
||||
---help---
|
||||
Enable special debug instrumentation to analyze QSPI DMA data transfers.
|
||||
This logic is as non-invasive as possible: It samples DMA
|
||||
registers at key points in the data transfer and then dumps all of
|
||||
the registers at the end of the transfer.
|
||||
|
||||
config STM32_QSPI_REGDEBUG
|
||||
bool "QSPI Register level debug"
|
||||
depends on DEBUG_SPI_INFO
|
||||
---help---
|
||||
Output detailed register-level QSPI device debug information.
|
||||
Requires also CONFIG_DEBUG_SPI_INFO.
|
||||
@@ -0,0 +1,93 @@
|
||||
#
|
||||
# STM32 common RTC options.
|
||||
#
|
||||
|
||||
choice
|
||||
prompt "RTC clock source"
|
||||
depends on STM32_RTC
|
||||
default STM32_RTC_LSECLOCK
|
||||
|
||||
config STM32_RTC_LSECLOCK
|
||||
bool "LSE clock"
|
||||
---help---
|
||||
Drive the RTC with the LSE clock
|
||||
|
||||
config STM32_RTC_LSICLOCK
|
||||
bool "LSI clock"
|
||||
---help---
|
||||
Drive the RTC with the LSI clock
|
||||
|
||||
config STM32_RTC_HSECLOCK
|
||||
bool "HSE clock"
|
||||
---help---
|
||||
Drive the RTC with the HSE clock, divided down to 1MHz.
|
||||
|
||||
endchoice # RTC clock source
|
||||
|
||||
config STM32_RTC_MAGIC_REG
|
||||
int "BKP register"
|
||||
depends on STM32_HAVE_RTC_MAGIC
|
||||
default 0
|
||||
range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER
|
||||
range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5
|
||||
---help---
|
||||
The BKP register used to store/check the Magic value to determine if
|
||||
RTC is already setup
|
||||
|
||||
config STM32_RTC_MAGIC
|
||||
hex "RTC Magic 1"
|
||||
depends on STM32_HAVE_RTC_MAGIC
|
||||
default 0xfacefeed
|
||||
---help---
|
||||
Value used as Magic to determine if the RTC is already setup
|
||||
|
||||
config STM32_RTC_MAGIC_TIME_SET
|
||||
hex "RTC Magic 2"
|
||||
depends on STM32_HAVE_RTC_MAGIC
|
||||
default 0xf00dface
|
||||
---help---
|
||||
Value used as Magic to determine if the RTC has been setup and has
|
||||
time set
|
||||
|
||||
config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
|
||||
bool "Automatically boost the LSE oscillator drive capability level until it starts-up"
|
||||
depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK
|
||||
---help---
|
||||
This will cycle through the values from low to high. To avoid
|
||||
damaging the crystal. We want to use the lowest setting that gets
|
||||
the OSC running. See app note AN2867
|
||||
|
||||
0 = Low drive capability (default)
|
||||
1 = Medium high drive capability
|
||||
2 = Medium low drive capability
|
||||
3 = High drive capability
|
||||
|
||||
config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
|
||||
int "LSE oscillator drive capability level at LSE start-up"
|
||||
depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK
|
||||
default 0
|
||||
range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB
|
||||
---help---
|
||||
0 = Low drive capability (default)
|
||||
1 = Medium high drive capability
|
||||
2 = Medium low drive capability
|
||||
3 = High drive capability
|
||||
|
||||
config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY
|
||||
int "LSE oscillator drive capability level after LSE start-up"
|
||||
depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5
|
||||
default 0
|
||||
range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB
|
||||
---help---
|
||||
0 = Low drive capability (default)
|
||||
1 = Medium high drive capability
|
||||
2 = Medium low drive capability
|
||||
3 = High drive capability
|
||||
|
||||
config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
|
||||
bool "Decrease LSE oscillator drive capability after LSE start-up"
|
||||
depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
|
||||
---help---
|
||||
The LSE oscillator drive capability can remain at the level used
|
||||
during LSE start-up at run-time, or it can be reduced to the
|
||||
'Low drive capability' once the LSE started up successfully.
|
||||
@@ -0,0 +1,88 @@
|
||||
#
|
||||
# STM32 common SAI options.
|
||||
#
|
||||
|
||||
choice
|
||||
prompt "Operation mode"
|
||||
depends on STM32_SAI
|
||||
default STM32_SAI_DMA
|
||||
---help---
|
||||
Select the operation mode the SAI driver should use.
|
||||
|
||||
config STM32_SAI_POLLING
|
||||
bool "Polling"
|
||||
---help---
|
||||
The SAI registers are polled for events.
|
||||
|
||||
config STM32_SAI_INTERRUPTS
|
||||
bool "Interrupt"
|
||||
---help---
|
||||
Select to enable interrupt driven SAI support.
|
||||
|
||||
config STM32_SAI_DMA
|
||||
bool "DMA"
|
||||
---help---
|
||||
Use DMA to improve SAI transfer performance.
|
||||
|
||||
endchoice # Operation mode
|
||||
|
||||
choice
|
||||
prompt "SAI1 synchronization enable"
|
||||
depends on STM32_SAI1_A && STM32_SAI1_B
|
||||
default STM32_SAI1_BOTH_ASYNC
|
||||
---help---
|
||||
Select the synchronization mode of the SAI sub-blocks
|
||||
|
||||
config STM32_SAI1_BOTH_ASYNC
|
||||
bool "Both asynchronous"
|
||||
|
||||
config STM32_SAI1_A_SYNC_WITH_B
|
||||
bool "Block A is synchronous with Block B"
|
||||
|
||||
config STM32_SAI1_B_SYNC_WITH_A
|
||||
bool "Block B is synchronous with Block A"
|
||||
|
||||
endchoice # SAI1 synchronization enable
|
||||
|
||||
choice
|
||||
prompt "SAI2 synchronization enable"
|
||||
depends on STM32_SAI2_A && STM32_SAI2_B
|
||||
default STM32_SAI2_BOTH_ASYNC
|
||||
---help---
|
||||
Select the synchronization mode of the SAI sub-blocks
|
||||
|
||||
config STM32_SAI2_BOTH_ASYNC
|
||||
bool "Both asynchronous"
|
||||
|
||||
config STM32_SAI2_A_SYNC_WITH_B
|
||||
bool "Block A is synchronous with Block B"
|
||||
|
||||
config STM32_SAI2_B_SYNC_WITH_A
|
||||
bool "Block B is synchronous with Block A"
|
||||
|
||||
endchoice # SAI2 synchronization enable
|
||||
|
||||
config STM32_SAI1PLL
|
||||
bool "SAI1PLL"
|
||||
depends on STM32_COMMON_L4_L5_U5
|
||||
---help---
|
||||
The STM32L4 has a separate PLL for the SAI1 block.
|
||||
Set this true and provide configuration parameters in
|
||||
board.h to use this PLL.
|
||||
|
||||
config STM32_SAI2PLL
|
||||
bool "SAI2PLL"
|
||||
depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2
|
||||
---help---
|
||||
The STM32L4 has a separate PLL for the SAI2 block.
|
||||
Set this true and provide configuration parameters in
|
||||
board.h to use this PLL.
|
||||
|
||||
config STM32_SAIPLL
|
||||
bool "SAIPLL"
|
||||
default n
|
||||
depends on STM32_HAVE_SAIPLL
|
||||
---help---
|
||||
The STM32F446 has a separate PLL for the SAI block.
|
||||
Set this true and provide configuration parameters in
|
||||
board.h to use this PLL.
|
||||
@@ -0,0 +1,39 @@
|
||||
#
|
||||
# STM32 common SDADC options.
|
||||
#
|
||||
|
||||
config STM32_SDADC1_HAVE_DMA
|
||||
bool
|
||||
|
||||
config STM32_SDADC2_HAVE_DMA
|
||||
bool
|
||||
|
||||
config STM32_SDADC3_HAVE_DMA
|
||||
bool
|
||||
|
||||
config STM32_SDADC1_DMA
|
||||
bool "SDADC1 DMA"
|
||||
depends on STM32_SDADC1 && STM32_SDADC1_HAVE_DMA
|
||||
default n
|
||||
---help---
|
||||
If DMA is selected, then the SDADC may be configured to support
|
||||
DMA transfer, which is advisable if multiple channels are read
|
||||
or if very high trigger frequencies are used.
|
||||
|
||||
config STM32_SDADC2_DMA
|
||||
bool "SDADC2 DMA"
|
||||
depends on STM32_SDADC2 && STM32_SDADC2_HAVE_DMA
|
||||
default n
|
||||
---help---
|
||||
If DMA is selected, then the SDADC may be configured to support
|
||||
DMA transfer, which is advisable if multiple channels are read
|
||||
or if very high trigger frequencies are used.
|
||||
|
||||
config STM32_SDADC3_DMA
|
||||
bool "SDADC3 DMA"
|
||||
depends on STM32_SDADC3 && STM32_SDADC3_HAVE_DMA
|
||||
default n
|
||||
---help---
|
||||
If DMA is selected, then the SDADC may be configured to support
|
||||
DMA transfer, which is advisable if multiple channels are read
|
||||
or if very high trigger frequencies are used.
|
||||
@@ -0,0 +1,150 @@
|
||||
#
|
||||
# STM32 common SDIO options.
|
||||
#
|
||||
|
||||
config STM32_SDMMC2_HAVE_DMAPRIO
|
||||
bool
|
||||
default y if ARCH_CHIP_STM32F7
|
||||
|
||||
config STM32_SDIO_CARD
|
||||
bool "SDIO Card support"
|
||||
depends on STM32_COMMON_LEGACY && STM32_SDIO
|
||||
default n
|
||||
---help---
|
||||
Build in additional support needed only for SDIO cards (vs. SD
|
||||
memory cards)
|
||||
|
||||
config STM32_SDIO_PULLUP
|
||||
bool "Enable internal Pull-Ups"
|
||||
depends on STM32_COMMON_LEGACY && STM32_SDIO
|
||||
default n
|
||||
---help---
|
||||
If you are using an external SDCard module that does not have the
|
||||
pull-up resistors for the SDIO interface (like the Gadgeteer SD Card
|
||||
Module) then enable this option to activate the internal pull-up
|
||||
resistors.
|
||||
|
||||
config STM32_SDIO_DMA
|
||||
bool "Support DMA data transfers"
|
||||
default STM32_DMA2
|
||||
select SDIO_DMA
|
||||
depends on STM32_COMMON_LEGACY && STM32_SDIO
|
||||
depends on STM32_DMA2
|
||||
---help---
|
||||
Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2.
|
||||
|
||||
config STM32_SDIO_DMAPRIO
|
||||
hex "SDIO DMA priority"
|
||||
default 0x00001000 if STM32_STM32F10XX
|
||||
default 0x00010000 if !STM32_STM32F10XX
|
||||
depends on STM32_COMMON_LEGACY && STM32_SDIO
|
||||
---help---
|
||||
Select SDIO DMA priority.
|
||||
|
||||
For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium,
|
||||
0x00002000 high, 0x00003000 very high. Default: medium.
|
||||
|
||||
For other STM32's, options are: 0x00000000 low, 0x00010000 medium,
|
||||
0x00020000 high, 0x00030000 very high. Default: medium.
|
||||
|
||||
config STM32_SDIO_WIDTH_D1_ONLY
|
||||
bool "Use D1 only"
|
||||
depends on STM32_COMMON_LEGACY && STM32_SDIO
|
||||
default n
|
||||
---help---
|
||||
Select 1-bit transfer mode. Default: 4-bit transfer mode.
|
||||
|
||||
config STM32_SDMMC_IDMA
|
||||
bool "Support IDMA data transfers"
|
||||
depends on ARCH_CHIP_STM32H7 && STM32_SDMMC
|
||||
default y
|
||||
select SDIO_DMA
|
||||
---help---
|
||||
Support IDMA data transfers.
|
||||
|
||||
if STM32_SDMMC
|
||||
|
||||
config STM32_SDMMC_XFRDEBUG
|
||||
bool "SDMMC transfer debug"
|
||||
depends on DEBUG_FS_INFO
|
||||
---help---
|
||||
Enable special debug instrumentation analyze SDMMC data transfers.
|
||||
This logic is as non-invasive as possible: It samples SDMMC
|
||||
registers at key points in the data transfer and then dumps all of
|
||||
the registers at the end of the transfer. If DEBUG_DMA is also
|
||||
enabled, then DMA register will be collected as well. Requires also
|
||||
DEBUG_FS and CONFIG_DEBUG_INFO.
|
||||
|
||||
config STM32_SDMMC_DMA
|
||||
bool "Support DMA data transfers"
|
||||
depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA
|
||||
select SDIO_DMA
|
||||
---help---
|
||||
Support DMA data transfers.
|
||||
|
||||
config STM32_SDMMC1_DMAPRIO
|
||||
hex "SDMMC1 DMA priority"
|
||||
depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1
|
||||
default 0x00010000 if ARCH_CHIP_STM32F7
|
||||
default 0x00001000
|
||||
---help---
|
||||
Select SDMMC1 DMA priority.
|
||||
|
||||
Options are: 0x00000000 low, 0x00010000 medium,
|
||||
0x00020000 high, 0x00030000 very high. Default: medium.
|
||||
|
||||
config SDMMC1_WIDTH_D1_ONLY
|
||||
bool "Use D1 only on SDMMC1"
|
||||
depends on STM32_SDMMC1
|
||||
---help---
|
||||
Select 1-bit transfer mode. Default: 4-bit transfer mode.
|
||||
|
||||
config SDMMC1_SDIO_MODE
|
||||
bool "SDIO Card Support"
|
||||
depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1
|
||||
---help---
|
||||
Build in additional support needed only for SDIO cards (vs. SD
|
||||
memory cards)
|
||||
|
||||
config SDMMC1_SDIO_PULLUP
|
||||
bool "Enable internal Pull-Ups"
|
||||
depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1
|
||||
---help---
|
||||
If you are using an external SDCard module that does not have the
|
||||
pull-up resistors for the SDIO interface (like the Gadgeteer SD Card
|
||||
Module) then enable this option to activate the internal pull-up
|
||||
resistors.
|
||||
|
||||
config SDMMC2_WIDTH_D1_ONLY
|
||||
bool "Use D1 only on SDMMC2"
|
||||
depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2
|
||||
---help---
|
||||
Select 1-bit transfer mode. Default: 4-bit transfer mode.
|
||||
|
||||
config SDMMC2_SDIO_MODE
|
||||
bool "SDIO Card Support"
|
||||
depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2
|
||||
---help---
|
||||
Build in additional support needed only for SDIO cards (vs. SD
|
||||
memory cards)
|
||||
|
||||
config SDMMC2_SDIO_PULLUP
|
||||
bool "Enable internal Pull-Ups"
|
||||
depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2
|
||||
---help---
|
||||
If you are using an external SDCard module that does not have the
|
||||
pull-up resistors for the SDIO interface (like the Gadgeteer SD Card
|
||||
Module) then enable this option to activate the internal pull-up
|
||||
resistors.
|
||||
|
||||
config STM32_SDMMC2_DMAPRIO
|
||||
hex "SDMMC2 DMA priority"
|
||||
default 0x00010000
|
||||
depends on STM32_SDMMC2 && STM32_SDMMC2_HAVE_DMAPRIO
|
||||
---help---
|
||||
Select SDMMC2 DMA priority.
|
||||
|
||||
Options are: 0x00000000 low, 0x00010000 medium,
|
||||
0x00020000 high, 0x00030000 very high. Default: medium.
|
||||
|
||||
endif # STM32_SDMMC
|
||||
@@ -0,0 +1,300 @@
|
||||
#
|
||||
# STM32 common SPI options.
|
||||
#
|
||||
|
||||
config STM32_SPI_DMA
|
||||
bool
|
||||
depends on STM32_HAVE_SPI_CORE_DMA
|
||||
|
||||
config STM32_SPI_INTERRUPTS
|
||||
bool "Interrupt driver SPI"
|
||||
depends on STM32_SPI
|
||||
depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2)
|
||||
---help---
|
||||
Select to enable interrupt driven SPI support. Non-interrupt-driven,
|
||||
poll-waiting is recommended if the interrupt rate would be to high in
|
||||
the interrupt driven case.
|
||||
|
||||
config STM32_SPI1_DMA
|
||||
bool "SPI1 DMA"
|
||||
depends on STM32_SPI && STM32_SPI1
|
||||
depends on STM32_HAVE_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS
|
||||
select STM32_SPI_DMA
|
||||
---help---
|
||||
Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT.
|
||||
|
||||
config STM32_SPI1_DMA_BUFFER
|
||||
int "SPI1 DMA buffer size"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA
|
||||
default 0
|
||||
---help---
|
||||
Add a properly aligned DMA buffer for RX and TX DMA for SPI1.
|
||||
|
||||
config STM32_SPI_DMATHRESHOLD
|
||||
int "SPI DMA threshold"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA
|
||||
default 4
|
||||
---help---
|
||||
When SPI DMA is enabled, small DMA transfers will still be performed
|
||||
by polling logic. But we need a threshold value to determine what
|
||||
is small.
|
||||
|
||||
config STM32_SPI2_DMA
|
||||
bool "SPI2 DMA"
|
||||
depends on STM32_SPI && STM32_SPI2
|
||||
depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS
|
||||
select STM32_SPI_DMA
|
||||
---help---
|
||||
Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT.
|
||||
|
||||
config STM32_SPI2_DMA_BUFFER
|
||||
int "SPI2 DMA buffer size"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA
|
||||
default 0
|
||||
---help---
|
||||
Add a properly aligned DMA buffer for RX and TX DMA for SPI2.
|
||||
|
||||
config STM32_SPI3_DMA
|
||||
bool "SPI3 DMA"
|
||||
depends on STM32_SPI && STM32_SPI3
|
||||
depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS
|
||||
select STM32_SPI_DMA
|
||||
---help---
|
||||
Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT.
|
||||
|
||||
config STM32_SPI3_DMA_BUFFER
|
||||
int "SPI3 DMA buffer size"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA
|
||||
default 0
|
||||
---help---
|
||||
Add a properly aligned DMA buffer for RX and TX DMA for SPI3.
|
||||
|
||||
config STM32_SPI4_DMA
|
||||
bool "SPI4 DMA"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT
|
||||
select STM32_SPI_DMA
|
||||
---help---
|
||||
Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT.
|
||||
|
||||
config STM32_SPI4_DMA_BUFFER
|
||||
int "SPI4 DMA buffer size"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA
|
||||
default 0
|
||||
---help---
|
||||
Add a properly aligned DMA buffer for RX and TX DMA for SPI4.
|
||||
|
||||
config STM32_SPI5_DMA
|
||||
bool "SPI5 DMA"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT
|
||||
select STM32_SPI_DMA
|
||||
---help---
|
||||
Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT.
|
||||
|
||||
config STM32_SPI5_DMA_BUFFER
|
||||
int "SPI5 DMA buffer size"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA
|
||||
default 0
|
||||
---help---
|
||||
Add a properly aligned DMA buffer for RX and TX DMA for SPI5.
|
||||
|
||||
config STM32_SPI6_DMA
|
||||
bool "SPI6 DMA"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT
|
||||
select STM32_SPI_DMA
|
||||
---help---
|
||||
Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT.
|
||||
|
||||
config STM32_SPI1_COMMTYPE
|
||||
int "SPI1 Operation mode"
|
||||
depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
|
||||
|
||||
config STM32_SPI2_COMMTYPE
|
||||
int "SPI2 Operation mode"
|
||||
depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
|
||||
|
||||
config STM32_SPI3_COMMTYPE
|
||||
int "SPI3 Operation mode"
|
||||
depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
|
||||
|
||||
config STM32_SPI6_DMA_BUFFER
|
||||
int "SPI6 DMA buffer size"
|
||||
depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA
|
||||
default 0
|
||||
---help---
|
||||
Add a properly aligned DMA buffer for RX and TX DMA for SPI6.
|
||||
|
||||
config STM32_SPI4_COMMTYPE
|
||||
int "SPI4 Operation mode"
|
||||
depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
|
||||
|
||||
config STM32_SPI5_COMMTYPE
|
||||
int "SPI5 Operation mode"
|
||||
depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
|
||||
|
||||
config STM32_SPI6_COMMTYPE
|
||||
int "SPI6 Operation mode"
|
||||
depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6
|
||||
default 0
|
||||
range 0 3
|
||||
---help---
|
||||
Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
|
||||
|
||||
menu "I2S Configuration"
|
||||
depends on STM32_I2S
|
||||
|
||||
config STM32_SPI2S2_DMA
|
||||
bool "SPI2S2 DMA"
|
||||
depends on STM32_SPI2 && !STM32_SPI_INTERRUPT
|
||||
select STM32_SPI_DMA
|
||||
---help---
|
||||
Use DMA to improve SPI2S2 transfer performance. Cannot be used with
|
||||
STM32_SPI_INTERRUPT.
|
||||
|
||||
config STM32_SPI2S2_DMA_BUFFER
|
||||
int "SPI2S2 DMA buffer size"
|
||||
default 0
|
||||
depends on STM32_SPI2S2_DMA
|
||||
---help---
|
||||
Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2.
|
||||
|
||||
config STM32_I2S_MAXINFLIGHT
|
||||
int "I2S queue size"
|
||||
depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S)
|
||||
default 16
|
||||
---help---
|
||||
This is the total number of transfers, both RX and TX, that can be
|
||||
enqueue before the caller is required to wait. This setting
|
||||
determines the number certain queue data structures that will be
|
||||
pre-allocated.
|
||||
|
||||
config STM32_I2S3_DATALEN
|
||||
int "Data width (bits)"
|
||||
depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3)
|
||||
default 16
|
||||
---help---
|
||||
Data width in bits. This is a default value and may be change
|
||||
via the I2S interface
|
||||
|
||||
config STM32_I2S1_MCK
|
||||
bool "I2S1_MCK"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S1
|
||||
---help---
|
||||
TBD.
|
||||
|
||||
config STM32_I2S1_RX
|
||||
bool "Enable I2S1 receiver"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S1
|
||||
---help---
|
||||
Enable I2S receipt logic
|
||||
|
||||
config STM32_I2S1_TX
|
||||
bool "Enable I2S1 transmitter"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S1
|
||||
---help---
|
||||
Enable I2S transmission logic
|
||||
|
||||
config STM32_I2S1_DATALEN
|
||||
int "I2S1 Data width (bits)"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S1
|
||||
default 16
|
||||
---help---
|
||||
Data width in bits. This is a default value and may be changed via
|
||||
the I2S interface.
|
||||
|
||||
config STM32_I2S2_MCK
|
||||
bool "I2S2_MCK"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S2
|
||||
---help---
|
||||
TBD.
|
||||
|
||||
config STM32_I2S2_RX
|
||||
bool "Enable I2S2 receiver"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S2
|
||||
---help---
|
||||
Enable I2S receipt logic
|
||||
|
||||
config STM32_I2S2_TX
|
||||
bool "Enable I2S2 transmitter"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S2
|
||||
---help---
|
||||
Enable I2S transmission logic
|
||||
|
||||
config STM32_I2S2_DATALEN
|
||||
int "I2S2 Data width (bits)"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S2
|
||||
default 16
|
||||
---help---
|
||||
Data width in bits. This is a default value and may be changed via
|
||||
the I2S interface.
|
||||
|
||||
config STM32_I2S3_MCK
|
||||
bool "I2S3_MCK"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_I2S3
|
||||
---help---
|
||||
TBD.
|
||||
|
||||
config STM32_I2S3_RX
|
||||
bool "Enable I2S receiver"
|
||||
depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3)
|
||||
---help---
|
||||
Enable I2S receipt logic
|
||||
|
||||
config STM32_I2S3_TX
|
||||
bool "Enable I2S transmitter"
|
||||
depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3)
|
||||
---help---
|
||||
Enable I2S transmission logic
|
||||
|
||||
config STM32_I2S_DMADEBUG
|
||||
bool "I2S DMA transfer debug"
|
||||
depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA)
|
||||
---help---
|
||||
Enable special debug instrumentation analyze I2S DMA data transfers.
|
||||
This logic is as non-invasive as possible: It samples DMA
|
||||
registers at key points in the data transfer and then dumps all of
|
||||
the registers at the end of the transfer.
|
||||
|
||||
config STM32_I2S_REGDEBUG
|
||||
bool "SSC Register level debug"
|
||||
depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG)
|
||||
---help---
|
||||
Output detailed register-level SSC device debug information.
|
||||
Very invasive! Requires also DEBUG.
|
||||
|
||||
config STM32_I2SPLL
|
||||
bool "I2SPLL"
|
||||
default n
|
||||
depends on STM32_HAVE_I2SPLL
|
||||
---help---
|
||||
The STM32F446 has a separate PLL for the I2S block.
|
||||
Set this true and provide configuration parameters in
|
||||
board.h to use this PLL.
|
||||
|
||||
config STM32_I2S_MCK
|
||||
bool "I2S_MCK"
|
||||
depends on STM32_I2S3
|
||||
default n
|
||||
---help---
|
||||
TBD.
|
||||
|
||||
endmenu # I2S Configuration
|
||||
@@ -0,0 +1,107 @@
|
||||
#
|
||||
# STM32 common SYSTEM options.
|
||||
#
|
||||
|
||||
config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG
|
||||
bool "Disable IDLE Sleep (WFI) in debug mode"
|
||||
depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB
|
||||
---help---
|
||||
In debug configuration, disables the WFI instruction in the IDLE loop
|
||||
to prevent the JTAG from disconnecting. With some JTAG debuggers, such
|
||||
as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI
|
||||
instruction, the debugger will disconnect, terminating the debug session.
|
||||
|
||||
choice
|
||||
prompt "JTAG Configuration"
|
||||
default STM32_JTAG_DISABLE
|
||||
---help---
|
||||
JTAG Enable settings (by default JTAG-DP and SW-DP are disabled)
|
||||
|
||||
config STM32_JTAG_DISABLE
|
||||
bool "Disable all JTAG clocking"
|
||||
|
||||
config STM32_JTAG_FULL_ENABLE
|
||||
bool "Enable full SWJ (JTAG-DP + SW-DP)"
|
||||
|
||||
config STM32_JTAG_NOJNTRST_ENABLE
|
||||
bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST"
|
||||
|
||||
config STM32_JTAG_SW_ENABLE
|
||||
bool "Set JTAG-DP disabled and SW-DP enabled"
|
||||
|
||||
endchoice
|
||||
|
||||
config STM32_DFU
|
||||
bool "DFU bootloader"
|
||||
depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !(STM32F1_VALUELINE || STM32F0_VALUELINE)
|
||||
---help---
|
||||
Configure and position code for use with the STMicro DFU bootloader. Do
|
||||
not select this option if you will load code using JTAG/SWM.
|
||||
|
||||
config STM32_TICKLESS_TIMER
|
||||
int "Tickless hardware timer"
|
||||
depends on SCHED_TICKLESS
|
||||
depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB
|
||||
default 2
|
||||
range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7
|
||||
range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB
|
||||
---help---
|
||||
If the Tickless OS feature is enabled, then one clock must be
|
||||
assigned to provided the timer needed by the OS.
|
||||
|
||||
config STM32_TICKLESS_CHANNEL
|
||||
int "Tickless timer channel"
|
||||
depends on SCHED_TICKLESS
|
||||
depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB
|
||||
default 1
|
||||
range 1 4
|
||||
---help---
|
||||
If the Tickless OS feature is enabled, the one clock must be
|
||||
assigned to provided the free-running timer needed by the OS
|
||||
and one channel on that clock is needed to handle intervals.
|
||||
|
||||
config STM32_NOEXT_VECTORS
|
||||
bool "Disable the ARMv7-M EXT vectors"
|
||||
default n
|
||||
---help---
|
||||
Sometimes you may not need any Vector support beyond SysTick
|
||||
and wish to save memory. This applies only to ARMv7-M architectures.
|
||||
|
||||
# Clock options
|
||||
|
||||
choice
|
||||
prompt "SysTick clock source"
|
||||
depends on STM32_COMMON_F0_L0_G0_C0
|
||||
default STM32_SYSTICK_CORECLK
|
||||
|
||||
config STM32_SYSTICK_CORECLK
|
||||
bool "Cortex-M0 core clock"
|
||||
|
||||
config STM32_SYSTICK_CORECLK_DIV16
|
||||
bool "Cortex-M0 core clock divided by 16"
|
||||
|
||||
endchoice
|
||||
|
||||
config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
|
||||
bool "Custom clock configuration"
|
||||
default n
|
||||
---help---
|
||||
Enables special, board-specific STM32 clock configuration.
|
||||
|
||||
# Power options
|
||||
|
||||
config STM32_FORCEPOWER
|
||||
bool "Force power"
|
||||
default n
|
||||
---help---
|
||||
Timer and I2C devices may need to the following to force power to be applied
|
||||
unconditionally at power up. (Otherwise, the device is powered when it is
|
||||
initialized).
|
||||
|
||||
# Debug MCU options
|
||||
|
||||
config STM32_DBGMCU_HAVE_TIM_FZ_IN_CR
|
||||
bool
|
||||
|
||||
config STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ
|
||||
bool
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,249 @@
|
||||
#
|
||||
# STM32 USB configuration options.
|
||||
#
|
||||
|
||||
menu "USB Full Speed Host Configuration"
|
||||
depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST
|
||||
|
||||
config STM32_USBDRD_NCHANNELS
|
||||
int "Number of host channels"
|
||||
default 8
|
||||
range 1 8
|
||||
depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST
|
||||
---help---
|
||||
Number of USB host channels to use.
|
||||
|
||||
config STM32_USBDRD_DESCSIZE
|
||||
int "Descriptor buffer size"
|
||||
default 128
|
||||
depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST
|
||||
---help---
|
||||
Size of descriptor/request buffers.
|
||||
|
||||
endmenu
|
||||
|
||||
config STM32_OTG_SOFOUTPUT
|
||||
bool "OTG SOF output"
|
||||
depends on STM32_HAVE_OTG_H7
|
||||
default n
|
||||
|
||||
config STM32_OTG_USBREGEN
|
||||
bool "Enable USB voltage regulator"
|
||||
depends on STM32_HAVE_OTG_H7
|
||||
default n
|
||||
|
||||
config STM32_USBHOST_REGDEBUG
|
||||
bool "Register-Level Debug"
|
||||
depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST
|
||||
---help---
|
||||
Enable very low-level register access debug.
|
||||
|
||||
config STM32_USBHOST_PKTDUMP
|
||||
bool "Packet Dump Debug"
|
||||
depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST
|
||||
---help---
|
||||
Dump all incoming and outgoing USB packets.
|
||||
|
||||
config STM32_USBFS_REGDEBUG
|
||||
bool "Register-Level Debug"
|
||||
depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO
|
||||
---help---
|
||||
Enable very low-level register access debug.
|
||||
|
||||
config OTG_ID_GPIO_DISABLE
|
||||
bool "Disable the use of GPIO_OTG_ID pin."
|
||||
depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS)
|
||||
---help---
|
||||
Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use
|
||||
cases to reuse this GPIO pin and ensure it is not set incorrectlty
|
||||
during OS boot.
|
||||
|
||||
menu "STM32_OTG_HS Configuration"
|
||||
depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS
|
||||
|
||||
choice
|
||||
prompt "ULPI Selection"
|
||||
default STM32_NO_ULPI
|
||||
|
||||
config STM32_NO_ULPI
|
||||
bool "No External ULPI"
|
||||
---help---
|
||||
Select to enable the presence of an external ULPI PHY
|
||||
|
||||
config STM32_EXTERNAL_ULPI
|
||||
bool "External ULPI"
|
||||
depends on STM32_HAVE_EXTERNAL_ULPI
|
||||
---help---
|
||||
Select to enable the presence of an external ULPI PHY
|
||||
|
||||
config STM32_INTERNAL_ULPI
|
||||
bool "Internal ULPI PHY"
|
||||
depends on STM32_HAVE_INTERNAL_ULPI
|
||||
---help---
|
||||
Select to enable the internal ULPI for USB HS
|
||||
|
||||
endchoice # "ULPI Selection"
|
||||
|
||||
endmenu # STM32_OTG_HS Configuration
|
||||
|
||||
menu "OTG_HS Configuration"
|
||||
depends on ARCH_CHIP_STM32H7 && STM32_OTGHS
|
||||
|
||||
config STM32_OTGHS_FS
|
||||
bool "OTGHS in FS mode"
|
||||
default n
|
||||
|
||||
choice
|
||||
prompt "ULPI Selection"
|
||||
default STM32_OTGHS_NO_ULPI
|
||||
|
||||
config STM32_OTGHS_NO_ULPI
|
||||
bool "No External ULPI on board."
|
||||
---help---
|
||||
Select to indicate that there is no external ULPI PHY. This means
|
||||
the OTG_HS peripheral must use the internal full-speed PHY and will
|
||||
be limited to full-speed mode.
|
||||
|
||||
config STM32_OTGHS_EXTERNAL_ULPI
|
||||
bool "External ULPI"
|
||||
---help---
|
||||
Select to indicate the presence of an external ULPI PHY and use it.
|
||||
|
||||
endchoice # "ULPI Selection"
|
||||
|
||||
endmenu # OTG_HS Configuration
|
||||
|
||||
menu "OTG Configuration"
|
||||
depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS)
|
||||
|
||||
choice
|
||||
prompt "STM32H7 OTGFS role"
|
||||
depends on STM32_OTGFS
|
||||
default STM32_OTGFS_USBDEV if USBDEV
|
||||
default STM32_OTGFS_HOST if !USBDEV && USBHOST
|
||||
|
||||
config STM32_OTGFS_USBDEV
|
||||
bool "OTGFS as USBDEV"
|
||||
depends on USBDEV
|
||||
|
||||
config STM32_OTGFS_HOST
|
||||
bool "OTGFS as HOST"
|
||||
depends on USBHOST
|
||||
|
||||
endchoice # "STM32H7 OTGFS role"
|
||||
|
||||
choice
|
||||
prompt "STM32H7 OTGHS role (only USBDEV supported for now)"
|
||||
depends on STM32_OTGHS
|
||||
default STM32_OTGHS_USBDEV if USBDEV
|
||||
|
||||
config STM32_OTGHS_USBDEV
|
||||
bool "OTGHS as USBDEV"
|
||||
depends on USBDEV
|
||||
|
||||
endchoice # "STM32H7 OTGHS role"
|
||||
|
||||
endmenu # OTG Configuration
|
||||
|
||||
menu "USB FS Host Configuration"
|
||||
depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST
|
||||
|
||||
config STM32_OTGFS_RXFIFO_SIZE
|
||||
int "Rx Packet Size"
|
||||
default 128
|
||||
---help---
|
||||
Size of the RX FIFO in 32-bit words. Default 128 (512 bytes)
|
||||
|
||||
config STM32_OTGFS_NPTXFIFO_SIZE
|
||||
int "Non-periodic Tx FIFO Size"
|
||||
default 96
|
||||
---help---
|
||||
Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
|
||||
|
||||
config STM32_OTGFS_PTXFIFO_SIZE
|
||||
int "Periodic Tx FIFO size"
|
||||
default 128
|
||||
---help---
|
||||
Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
|
||||
|
||||
config STM32_OTGFS_DESCSIZE
|
||||
int "Descriptor Size"
|
||||
default 128
|
||||
---help---
|
||||
Maximum size to allocate for descriptor memory descriptor. Default: 128
|
||||
|
||||
config STM32_OTGFS_SOFINTR
|
||||
bool "Enable SOF interrupts"
|
||||
default n
|
||||
---help---
|
||||
Enable SOF interrupts. Why would you ever want to do that?
|
||||
|
||||
config STM32_OTGFS_VBUS_CONTROL
|
||||
bool "Enable VBus Control"
|
||||
default y
|
||||
---help---
|
||||
Enable VBus control. Used when the board has VBus sensing and
|
||||
a power switch for the OTG FS USB port. Disable this config
|
||||
if the board lacks this USB VBus control circuitry.
|
||||
|
||||
endmenu # USB FS Host Configuration
|
||||
|
||||
menu "USB HS Host Configuration"
|
||||
depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST
|
||||
|
||||
config STM32_OTGHS_RXFIFO_SIZE
|
||||
int "Rx Packet Size"
|
||||
default 128
|
||||
---help---
|
||||
Size of the RX FIFO in 32-bit words. Default 128 (512 bytes)
|
||||
|
||||
config STM32_OTGHS_NPTXFIFO_SIZE
|
||||
int "Non-periodic Tx FIFO Size"
|
||||
default 96
|
||||
---help---
|
||||
Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
|
||||
|
||||
config STM32_OTGHS_PTXFIFO_SIZE
|
||||
int "Periodic Tx FIFO size"
|
||||
default 128
|
||||
---help---
|
||||
Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
|
||||
|
||||
config STM32_OTGHS_DESCSIZE
|
||||
int "Descriptor Size"
|
||||
default 128
|
||||
---help---
|
||||
Maximum size to allocate for descriptor memory descriptor. Default: 128
|
||||
|
||||
config STM32_OTGHS_SOFINTR
|
||||
bool "Enable SOF interrupts"
|
||||
default n
|
||||
---help---
|
||||
Enable SOF interrupts. Why would you ever want to do that?
|
||||
|
||||
config STM32_OTGHS_VBUS_CONTROL
|
||||
bool "Enable VBus Control"
|
||||
default y
|
||||
---help---
|
||||
Enable VBus control. Used when the board has VBus sensing and
|
||||
a power switch for the OTG HS USB port. Disable this config
|
||||
if the board lacks this USB VBus control circuitry.
|
||||
|
||||
endmenu # USB HS Host Configuration
|
||||
|
||||
config STM32_USBDEV_REGDEBUG
|
||||
bool "OTG USBDEV REGDEBUG"
|
||||
depends on STM32_COMMON_F7_H7 && USBDEV
|
||||
|
||||
comment "USB Device Configuration"
|
||||
|
||||
config STM32_USB_ITRMP
|
||||
bool "Re-map USB interrupt"
|
||||
default STM32_CAN1
|
||||
depends on STM32_USB && STM32_STM32F30XX
|
||||
---help---
|
||||
The legacy USB in the F1 series shared interrupt lines with USB
|
||||
device and CAN1. In the F3 series, a hardware options was added to
|
||||
either retain the legacy F1 behavior or to map the USB interrupts to
|
||||
their own dedicated vectors. The option is available only for the
|
||||
F3 family and selects the use of the dedicated USB interrupts.
|
||||
@@ -75,7 +75,7 @@ if(CONFIG_BUILD_PROTECTED)
|
||||
list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c)
|
||||
endif()
|
||||
|
||||
if(CONFIG_STM32_HAVE_IP_I2C_V1)
|
||||
if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1)
|
||||
if(CONFIG_STM32_I2C_ALT)
|
||||
list(APPEND SRCS stm32_i2c_alt.c)
|
||||
elseif(CONFIG_STM32_STM32F4XXX)
|
||||
@@ -83,7 +83,7 @@ if(CONFIG_STM32_HAVE_IP_I2C_V1)
|
||||
else()
|
||||
list(APPEND SRCS stm32_i2c.c)
|
||||
endif()
|
||||
elseif(CONFIG_STM32_HAVE_IP_I2C_V2)
|
||||
elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)
|
||||
list(APPEND SRCS stm32_i2c_v2.c)
|
||||
if(CONFIG_STM32_I2C_SLAVE)
|
||||
list(APPEND SRCS stm32_i2cslave_v2.c)
|
||||
|
||||
+439
-2192
File diff suppressed because it is too large
Load Diff
@@ -59,7 +59,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
|
||||
CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V1),y)
|
||||
ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y)
|
||||
ifeq ($(CONFIG_STM32_I2C_ALT),y)
|
||||
CHIP_CSRCS += stm32_i2c_alt.c
|
||||
else ifeq ($(CONFIG_STM32_STM32F4XXX),y)
|
||||
@@ -67,7 +67,7 @@ CHIP_CSRCS += stm32f40xxx_i2c.c
|
||||
else
|
||||
CHIP_CSRCS += stm32_i2c.c
|
||||
endif
|
||||
else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V2),y)
|
||||
else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y)
|
||||
CHIP_CSRCS += stm32_i2c_v2.c
|
||||
ifeq ($(CONFIG_STM32_I2C_SLAVE),y)
|
||||
CHIP_CSRCS += stm32_i2cslave_v2.c
|
||||
|
||||
@@ -46,18 +46,18 @@
|
||||
* too much to keep it in the same file as ADC IPv2.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && \
|
||||
defined(CONFIG_STM32_HAVE_IP_ADC_V2)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && \
|
||||
defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
|
||||
# error Only one STM32 ADC IP version must be selected
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1)
|
||||
# if defined(CONFIG_STM32_STM32L15XX)
|
||||
# include "stm32_adc_v1l1.h" /* Special case for L1 */
|
||||
# else
|
||||
# include "stm32_adc_v1.h"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_ADC_V2)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
|
||||
# if defined(CONFIG_STM32_STM32G4XXX)
|
||||
# include "stm32_adc_v2g4.h" /* Special case for G4 */
|
||||
# else
|
||||
|
||||
@@ -54,7 +54,7 @@
|
||||
* - ...
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1_BASIC)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC)
|
||||
# define HAVE_BASIC_ADC
|
||||
#else
|
||||
# undef HAVE_BASIC_ADC
|
||||
|
||||
@@ -57,7 +57,7 @@
|
||||
* TODO: definitions for basic STM32 ADC IPv2 (F0, L0)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_V2_BASIC
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2_BASIC
|
||||
# define HAVE_BASIC_ADC
|
||||
# error TODO
|
||||
#else
|
||||
|
||||
@@ -39,13 +39,13 @@
|
||||
|
||||
/* If more than one COMP IP ensure that only one is selected */
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_COMP_V1)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1)
|
||||
# if defined(CONFIG_STM32_STM32F33XX)
|
||||
# include "stm32f33xxx_comp.h"
|
||||
# else
|
||||
# error "Device not supported."
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)
|
||||
# if defined(CONFIG_STM32_STM32G4XXX)
|
||||
# include "stm32g4xxxx_comp.h"
|
||||
# else
|
||||
|
||||
@@ -36,14 +36,14 @@
|
||||
* 2. STM32 DAC IPv2: G4
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) && \
|
||||
defined(CONFIG_STM32_HAVE_IP_DAC_V2)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) && \
|
||||
defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)
|
||||
# error Only one STM32 DAC IP version must be selected
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DAC_V1)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1)
|
||||
# include "stm32_dac_v1.h"
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_DAC_V2)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)
|
||||
# if defined(CONFIG_STM32_STM32G4XXX)
|
||||
# include "stm32gxxxxx_dac.h" /* Special case for G4 */
|
||||
# else
|
||||
|
||||
@@ -39,11 +39,11 @@
|
||||
|
||||
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
|
||||
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2
|
||||
# define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
|
||||
# define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3
|
||||
# define STM32_DBGMCU_APB1_FZ1 0xe0042008 /* Debug MCU APB1 freeze 1 register */
|
||||
# define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze 2 register */
|
||||
# define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */
|
||||
@@ -72,7 +72,7 @@
|
||||
# define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
|
||||
# define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V1
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1
|
||||
# define DBGMCU_CR_IWDGSTOP (1 << 8) /* Bit 8: Independent Watchdog stopped when core is halted */
|
||||
# define DBGMCU_CR_WWDGSTOP (1 << 9) /* Bit 9: Window Watchdog stopped when core is halted */
|
||||
# define DBGMCU_CR_TIM1STOP (1 << 10) /* Bit 10: TIM1 stopped when core is halted */
|
||||
@@ -87,9 +87,9 @@
|
||||
# define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */
|
||||
# define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */
|
||||
# define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */
|
||||
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V1 */
|
||||
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 */
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2
|
||||
|
||||
/* Debug MCU APB1 freeze register */
|
||||
|
||||
@@ -147,9 +147,9 @@
|
||||
# define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */
|
||||
# define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */
|
||||
#endif
|
||||
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */
|
||||
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 */
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3
|
||||
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3
|
||||
|
||||
/* Debug MCU APB1 freeze 1 register */
|
||||
|
||||
@@ -180,7 +180,7 @@
|
||||
# define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */
|
||||
# define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */
|
||||
|
||||
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */
|
||||
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -32,9 +32,9 @@
|
||||
* 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_I2C_V1)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1)
|
||||
# include "stm32_i2c_v1.h"
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_I2C_V2)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)
|
||||
# include "stm32_i2c_v2.h"
|
||||
#else
|
||||
# error STM32 I2C IP version not specified
|
||||
|
||||
@@ -27,10 +27,10 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \
|
||||
defined(CONFIG_STM32_HAVE_IP_TIMERS_V2)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \
|
||||
defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2)
|
||||
# include "stm32_tim_v1v2.h"
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V3)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3)
|
||||
# include "stm32_tim_v3.h"
|
||||
#else
|
||||
# error "STM32 TIMER IP version not specified"
|
||||
|
||||
@@ -42,9 +42,9 @@
|
||||
* - 4-bit SMS in SMCR register
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2)
|
||||
# define HAVE_IP_TIMERS_V2
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1)
|
||||
# define HAVE_IP_TIMERS_V1
|
||||
#else
|
||||
# error
|
||||
|
||||
@@ -308,7 +308,7 @@
|
||||
|
||||
/* ADC resolution. Not supported for basic STM32 ADC IPv1 */
|
||||
|
||||
#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC
|
||||
#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC
|
||||
# define HAVE_ADC_RESOLUTION
|
||||
#else
|
||||
# undef HAVE_ADC_RESOLUTION
|
||||
@@ -316,7 +316,7 @@
|
||||
|
||||
/* ADC have common registers for all cores except basic ADC IPv1 (F1, F37x) */
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC
|
||||
# undef HAVE_ADC_CMN_REGS
|
||||
#else
|
||||
# define HAVE_ADC_CMN_REGS
|
||||
@@ -333,7 +333,7 @@
|
||||
|
||||
/* ADC DMA configuration bit support */
|
||||
|
||||
#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC
|
||||
#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC
|
||||
# define ADC_HAVE_DMACFG 1
|
||||
#else
|
||||
# undef ADC_HAVE_DMACFG
|
||||
@@ -341,7 +341,7 @@
|
||||
|
||||
/* ADC scan mode support - only for ADCv1 */
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_V1
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1
|
||||
# define ADC_HAVE_SCAN 1
|
||||
# ifndef CONFIG_STM32_ADC1_SCAN
|
||||
# define CONFIG_STM32_ADC1_SCAN 0
|
||||
|
||||
@@ -47,9 +47,9 @@
|
||||
* - STM32 COMP IP version 2: SMT32G4XXX
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_COMP_V1)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1)
|
||||
# include "stm32_comp_v1.c"
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)
|
||||
# include "stm32_comp_v2.c"
|
||||
#else
|
||||
# error "STM32 COMP IP version not supported."
|
||||
|
||||
@@ -33,9 +33,9 @@
|
||||
|
||||
#include "hardware/stm32_comp.h"
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_COMP_V1)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1)
|
||||
# include "stm32_comp_v1.h"
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)
|
||||
# include "stm32_comp_v2.h"
|
||||
#endif
|
||||
|
||||
|
||||
@@ -106,14 +106,14 @@
|
||||
|
||||
/* This is not for ADC IPv2 basic */
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) && defined(HAVE_BASIC_ADC)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) && defined(HAVE_BASIC_ADC)
|
||||
# error Not supported ADC IP core
|
||||
#endif
|
||||
|
||||
/* Multi instances support tested only on IP_ADC_V1 */
|
||||
|
||||
#if CONFIG_MOTOR_FOC_INST > 1
|
||||
# if defined(CONFIG_STM32_HAVE_IP_ADC_V2)
|
||||
# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
|
||||
# error Not tested yet
|
||||
# endif
|
||||
#endif
|
||||
@@ -141,10 +141,10 @@
|
||||
|
||||
/* Debug register for PWM timers */
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \
|
||||
defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \
|
||||
defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)
|
||||
# define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1)
|
||||
# define FOC_PWM_FZ_REG (STM32_DBGMCU_CR)
|
||||
#endif
|
||||
|
||||
@@ -154,10 +154,10 @@
|
||||
# define FOC0_PWM (1)
|
||||
# define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS)
|
||||
# define FOC0_PWM_BASE (STM32_TIM1_BASE)
|
||||
# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \
|
||||
defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3)
|
||||
# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \
|
||||
defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)
|
||||
# define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP)
|
||||
# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1)
|
||||
# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1)
|
||||
# define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP)
|
||||
# endif
|
||||
# if CONFIG_STM32_TIM1_MODE != 2
|
||||
@@ -171,10 +171,10 @@
|
||||
# define FOC1_PWM (8)
|
||||
# define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS)
|
||||
# define FOC1_PWM_BASE (STM32_TIM8_BASE)
|
||||
# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \
|
||||
defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3)
|
||||
# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \
|
||||
defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)
|
||||
# define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP)
|
||||
# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1)
|
||||
# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1)
|
||||
# define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP)
|
||||
# endif
|
||||
# if CONFIG_STM32_TIM8_MODE != 2
|
||||
@@ -248,14 +248,14 @@
|
||||
* TIMx CCR4 = (ARR - trigger_offset)
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_STM32_HAVE_IP_ADC_V2)
|
||||
# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
|
||||
# ifdef CONFIG_STM32_FOC_USE_TIM1
|
||||
# define ADC_JEXTSEL_T1CC4 (ADC12_JSQR_JEXTSEL_T1CC4)
|
||||
# endif
|
||||
# ifdef CONFIG_STM32_FOC_USE_TIM8
|
||||
# define ADC_JEXTSEL_T8CC4 (ADC12_JSQR_JEXTSEL_T8CC4)
|
||||
# endif
|
||||
# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1)
|
||||
# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1)
|
||||
# ifdef CONFIG_STM32_FOC_USE_TIM1
|
||||
# define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4)
|
||||
# endif
|
||||
@@ -314,14 +314,14 @@
|
||||
* TIMx TRGO = (ARR)
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_STM32_HAVE_IP_ADC_V2)
|
||||
# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
|
||||
# ifdef CONFIG_STM32_FOC_USE_TIM1
|
||||
# define ADC_JEXTSEL_T1TRGO (ADC12_JSQR_JEXTSEL_T1TRGO)
|
||||
# endif
|
||||
# ifdef CONFIG_STM32_FOC_USE_TIM8
|
||||
# define ADC_JEXTSEL_T8TRGO (ADC12_JSQR_JEXTSEL_T8TRGO)
|
||||
# endif
|
||||
# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1)
|
||||
# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1)
|
||||
# ifdef CONFIG_STM32_FOC_USE_TIM1
|
||||
# define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO)
|
||||
# endif
|
||||
@@ -470,11 +470,11 @@
|
||||
|
||||
/* Generalize ADC interrupt flags */
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V2)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)
|
||||
# define FOC_ADC_ISR_FOC ADC_ISR_JEOS
|
||||
# define FOC_ADC_IER_FOC ADC_IER_JEOS
|
||||
# define FOC_ADC_ISR_OVR ADC_INT_OVR
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_ADC_V1)
|
||||
#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1)
|
||||
# define FOC_ADC_ISR_FOC ADC_ISR_JEOC
|
||||
# define FOC_ADC_IER_FOC ADC_IER_JEOC
|
||||
# define FOC_ADC_ISR_OVR ADC_SR_OVR
|
||||
@@ -515,7 +515,7 @@
|
||||
|
||||
/* Common for ADCv1 */
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && !defined(HAVE_BASIC_ADC)
|
||||
# define FOC_ADC_HAVE_CMN (1)
|
||||
# ifdef CONFIG_STM32_FOC_USE_ADC1
|
||||
# define FOC_ADC1_CMN (&g_stm32_foc_adccmn123)
|
||||
@@ -530,7 +530,7 @@
|
||||
|
||||
/* Common for ADCv1 basic */
|
||||
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC)
|
||||
#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && defined(HAVE_BASIC_ADC)
|
||||
# undef FOC_ADC_HAVE_CMN
|
||||
# ifdef CONFIG_STM32_FOC_USE_ADC1
|
||||
# define FOC_ADC1_CMN (0)
|
||||
@@ -545,7 +545,7 @@
|
||||
|
||||
/* Common for ADCv2 */
|
||||
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_V2
|
||||
#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2
|
||||
# define FOC_ADC_HAVE_CMN (1)
|
||||
# ifdef CONFIG_STM32_FOC_USE_ADC1
|
||||
# define FOC_ADC1_CMN (&g_stm32_foc_adccmn12)
|
||||
@@ -895,7 +895,7 @@ static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev,
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef FOC_ADC_HAVE_CMN
|
||||
# ifdef CONFIG_STM32_HAVE_IP_ADC_V1
|
||||
# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1
|
||||
/* Common for ADC123 */
|
||||
|
||||
static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 =
|
||||
@@ -903,9 +903,9 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 =
|
||||
.cntr = 0,
|
||||
.lock = NXMUTEX_INITIALIZER,
|
||||
};
|
||||
# endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */
|
||||
# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 */
|
||||
|
||||
# ifdef CONFIG_STM32_HAVE_IP_ADC_V2
|
||||
# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2
|
||||
# if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2)
|
||||
/* Common for ADC12 */
|
||||
|
||||
@@ -924,7 +924,7 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn34 =
|
||||
.lock = NXMUTEX_INITIALIZER,
|
||||
};
|
||||
# endif /* CONFIG_STM32_HAVE_ADC3 || CONFIG_STM32_HAVE_ADC4 */
|
||||
# endif /* CONFIG_STM32_HAVE_IP_ADC_V2 */
|
||||
# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 */
|
||||
#endif /* FOC_ADC_HAVE_CMN */
|
||||
|
||||
/* STM32 specific FOC data */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user