From 297bb7b5e6063a6bff1108ce733d8c2f6fa68f73 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 21:05:28 +0200 Subject: [PATCH] arch/stm32: split common Kconfig into per-peripheral files STM32 common Kconfig into smaller files. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/Kconfig | 9607 +---------------- arch/arm/src/common/stm32/Kconfig.adc | 964 ++ arch/arm/src/common/stm32/Kconfig.ble | 221 + arch/arm/src/common/stm32/Kconfig.cache | 238 + arch/arm/src/common/stm32/Kconfig.can | 58 + arch/arm/src/common/stm32/Kconfig.comp | 387 + arch/arm/src/common/stm32/Kconfig.dac | 363 + arch/arm/src/common/stm32/Kconfig.dfsdm | 46 + arch/arm/src/common/stm32/Kconfig.dma | 118 + arch/arm/src/common/stm32/Kconfig.dts | 99 + arch/arm/src/common/stm32/Kconfig.eth | 290 + arch/arm/src/common/stm32/Kconfig.fdcan | 518 + arch/arm/src/common/stm32/Kconfig.flash | 162 + arch/arm/src/common/stm32/Kconfig.foc | 197 + arch/arm/src/common/stm32/Kconfig.gpio | 9 + arch/arm/src/common/stm32/Kconfig.have | 1191 ++ arch/arm/src/common/stm32/Kconfig.hciuart | 292 + arch/arm/src/common/stm32/Kconfig.hrtim | 583 + arch/arm/src/common/stm32/Kconfig.i2c | 313 + arch/arm/src/common/stm32/Kconfig.ipcc | 91 + arch/arm/src/common/stm32/Kconfig.lpuart | 69 + arch/arm/src/common/stm32/Kconfig.ltdc | 233 + arch/arm/src/common/stm32/Kconfig.memory | 168 + arch/arm/src/common/stm32/Kconfig.periph | 1282 +++ arch/arm/src/common/stm32/Kconfig.qspi | 158 + arch/arm/src/common/stm32/Kconfig.rtc | 93 + arch/arm/src/common/stm32/Kconfig.sai | 88 + arch/arm/src/common/stm32/Kconfig.sdadc | 39 + arch/arm/src/common/stm32/Kconfig.sdio | 150 + arch/arm/src/common/stm32/Kconfig.spi | 300 + arch/arm/src/common/stm32/Kconfig.system | 107 + arch/arm/src/common/stm32/Kconfig.tim | 4205 ++++++++ arch/arm/src/common/stm32/Kconfig.uart | 1245 +++ arch/arm/src/common/stm32/Kconfig.usb | 249 + arch/arm/src/stm32/CMakeLists.txt | 4 +- arch/arm/src/stm32/Kconfig | 2631 +---- arch/arm/src/stm32/Make.defs | 4 +- arch/arm/src/stm32/hardware/stm32_adc.h | 8 +- arch/arm/src/stm32/hardware/stm32_adc_v1.h | 2 +- arch/arm/src/stm32/hardware/stm32_adc_v2.h | 2 +- arch/arm/src/stm32/hardware/stm32_comp.h | 4 +- arch/arm/src/stm32/hardware/stm32_dac.h | 8 +- arch/arm/src/stm32/hardware/stm32_dbgmcu.h | 16 +- arch/arm/src/stm32/hardware/stm32_i2c.h | 4 +- arch/arm/src/stm32/hardware/stm32_tim.h | 6 +- arch/arm/src/stm32/hardware/stm32_tim_v1v2.h | 4 +- arch/arm/src/stm32/stm32_adc.c | 8 +- arch/arm/src/stm32/stm32_comp.c | 4 +- arch/arm/src/stm32/stm32_comp.h | 4 +- arch/arm/src/stm32/stm32_foc.c | 48 +- arch/arm/src/stm32f0l0g0/Kconfig | 154 +- .../b-l072z-lrwan1/configs/adc/defconfig | 1 + .../b-l072z-lrwan1/configs/nsh/defconfig | 1 + .../configs/nxlines_oled/defconfig | 1 + .../b-l072z-lrwan1/configs/sx127x/defconfig | 1 + boards/arm/stm32f0l0g0/common/src/board_pwm.c | 14 +- .../nucleo-c071rb/configs/adcscope/defconfig | 1 + .../nucleo-c071rb/configs/jumbo/defconfig | 1 + .../nucleo-c071rb/configs/nsh/defconfig | 1 + .../nucleo-c092rc/configs/can/defconfig | 1 + .../nucleo-c092rc/configs/cansock/defconfig | 1 + .../nucleo-c092rc/configs/jumbo/defconfig | 1 + .../nucleo-c092rc/configs/nsh/defconfig | 1 + .../nucleo-f072rb/configs/nsh/defconfig | 1 + .../nucleo-f091rc/configs/nsh/defconfig | 1 + .../nucleo-f091rc/configs/sx127x/defconfig | 1 + .../nucleo-g070rb/configs/nsh/defconfig | 1 + .../nucleo-g071rb/configs/nsh/defconfig | 1 + .../nucleo-g0b1re/configs/adc/defconfig | 1 + .../nucleo-g0b1re/configs/adc_dma/defconfig | 1 + .../nucleo-g0b1re/configs/nsh/defconfig | 1 + .../nucleo-l073rz/configs/nsh/defconfig | 1 + .../nucleo-l073rz/configs/sx127x/defconfig | 1 + .../stm32f051-discovery/configs/nsh/defconfig | 1 + .../stm32f072-discovery/configs/nsh/defconfig | 1 + .../stm32g071b-disco/configs/nsh/defconfig | 1 + .../stm32g071b-disco/configs/oled/defconfig | 1 + .../stm32l0538-disco/configs/nsh/defconfig | 1 + 78 files changed, 15202 insertions(+), 11882 deletions(-) create mode 100644 arch/arm/src/common/stm32/Kconfig.adc create mode 100644 arch/arm/src/common/stm32/Kconfig.ble create mode 100644 arch/arm/src/common/stm32/Kconfig.cache create mode 100644 arch/arm/src/common/stm32/Kconfig.can create mode 100644 arch/arm/src/common/stm32/Kconfig.comp create mode 100644 arch/arm/src/common/stm32/Kconfig.dac create mode 100644 arch/arm/src/common/stm32/Kconfig.dfsdm create mode 100644 arch/arm/src/common/stm32/Kconfig.dma create mode 100644 arch/arm/src/common/stm32/Kconfig.dts create mode 100644 arch/arm/src/common/stm32/Kconfig.eth create mode 100644 arch/arm/src/common/stm32/Kconfig.fdcan create mode 100644 arch/arm/src/common/stm32/Kconfig.flash create mode 100644 arch/arm/src/common/stm32/Kconfig.foc create mode 100644 arch/arm/src/common/stm32/Kconfig.gpio create mode 100644 arch/arm/src/common/stm32/Kconfig.have create mode 100644 arch/arm/src/common/stm32/Kconfig.hciuart create mode 100644 arch/arm/src/common/stm32/Kconfig.hrtim create mode 100644 arch/arm/src/common/stm32/Kconfig.i2c create mode 100644 arch/arm/src/common/stm32/Kconfig.ipcc create mode 100644 arch/arm/src/common/stm32/Kconfig.lpuart create mode 100644 arch/arm/src/common/stm32/Kconfig.ltdc create mode 100644 arch/arm/src/common/stm32/Kconfig.memory create mode 100644 arch/arm/src/common/stm32/Kconfig.periph create mode 100644 arch/arm/src/common/stm32/Kconfig.qspi create mode 100644 arch/arm/src/common/stm32/Kconfig.rtc create mode 100644 arch/arm/src/common/stm32/Kconfig.sai create mode 100644 arch/arm/src/common/stm32/Kconfig.sdadc create mode 100644 arch/arm/src/common/stm32/Kconfig.sdio create mode 100644 arch/arm/src/common/stm32/Kconfig.spi create mode 100644 arch/arm/src/common/stm32/Kconfig.system create mode 100644 arch/arm/src/common/stm32/Kconfig.tim create mode 100644 arch/arm/src/common/stm32/Kconfig.uart create mode 100644 arch/arm/src/common/stm32/Kconfig.usb diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig index 92853f2cf52..a21fdfa9fa8 100644 --- a/arch/arm/src/common/stm32/Kconfig +++ b/arch/arm/src/common/stm32/Kconfig @@ -2,18 +2,9 @@ # Common STM32 Kconfig options shared by STM32 families. # -menu "Common STM32 Configuration Options" +menu "STM32 Configuration Options" depends on ARCH_CHIP_STM32 -config STM32_SERIALDRIVER - bool - -config STM32_1WIREDRIVER - bool - -config STM32_HCIUART - bool - config STM32_COMMON_LEGACY bool default y if ARCH_CHIP_STM32F1 @@ -75,9501 +66,147 @@ config STM32_COMMON_SRAM2_OPTIONS default y if ARCH_CHIP_STM32L5 default y if ARCH_CHIP_STM32U5 && STM32_SRAM2 -config STM32_COMMON_USART_UNCONFIG_ON_CLOSE - bool - default y if ARCH_CHIP_STM32H5 - default y if ARCH_CHIP_STM32N6 +source "arch/arm/src/common/stm32/Kconfig.have" -choice - prompt "JTAG Configuration" - default STM32_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) +source "arch/arm/src/common/stm32/Kconfig.periph" -config STM32_JTAG_DISABLE - bool "Disable all JTAG clocking" +menu "ADC Configuration" + depends on STM32_ADC +source "arch/arm/src/common/stm32/Kconfig.adc" +endmenu # ADC Configuration -config STM32_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" +menu "SDADC Configuration" + depends on STM32_SDADC +source "arch/arm/src/common/stm32/Kconfig.sdadc" +endmenu # SDADC Configuration -config STM32_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" +menu "Cache Configuration" +source "arch/arm/src/common/stm32/Kconfig.cache" +endmenu # Cache Configuration -config STM32_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice - -choice - prompt "Select TIM1 ADC channel" - depends on STM32_TIM1_ADC - default STM32_TIM1_ADC1 - -config STM32_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM2 ADC channel" - depends on STM32_TIM2_ADC - default STM32_TIM2_ADC1 - -config STM32_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM3 ADC channel" - depends on STM32_TIM3_ADC - default STM32_TIM3_ADC1 - -config STM32_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM4 ADC channel" - depends on STM32_TIM4_ADC - default STM32_TIM4_ADC1 - -config STM32_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM5 ADC channel" - depends on STM32_TIM5_ADC - default STM32_TIM5_ADC1 - -config STM32_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM8 ADC channel" - depends on STM32_TIM8_ADC - default STM32_TIM8_ADC1 - -config STM32_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM1 DAC channel" - depends on STM32_TIM1_DAC - default STM32_TIM1_DAC1 - -config STM32_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM2 DAC channel" - depends on STM32_TIM2_DAC - default STM32_TIM2_DAC1 - -config STM32_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM3 DAC channel" - depends on STM32_TIM3_DAC - default STM32_TIM3_DAC1 - -config STM32_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM4 DAC channel" - depends on STM32_TIM4_DAC - default STM32_TIM4_DAC1 - -config STM32_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM5 DAC channel" - depends on STM32_TIM5_DAC - default STM32_TIM5_DAC1 - -config STM32_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM6 DAC channel" - depends on STM32_TIM6_DAC - default STM32_TIM6_DAC1 - -config STM32_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM7 DAC channel" - depends on STM32_TIM7_DAC - default STM32_TIM7_DAC1 - -config STM32_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM8 DAC channel" - depends on STM32_TIM8_DAC - default STM32_TIM8_DAC1 - -config STM32_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM9 DAC channel" - depends on STM32_TIM9_DAC - default STM32_TIM9_DAC1 - -config STM32_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM10 DAC channel" - depends on STM32_TIM10_DAC - default STM32_TIM10_DAC1 - -config STM32_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM11 DAC channel" - depends on STM32_TIM11_DAC - default STM32_TIM11_DAC1 - -config STM32_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM12 DAC channel" - depends on STM32_TIM12_DAC - default STM32_TIM12_DAC1 - -config STM32_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM13 DAC channel" - depends on STM32_TIM13_DAC - default STM32_TIM13_DAC1 - -config STM32_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM14 DAC channel" - depends on STM32_TIM14_DAC - default STM32_TIM14_DAC1 - -config STM32_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice - -choice - prompt "USART1 Driver Configuration" - depends on STM32_USART1 - default STM32_USART1_SERIALDRIVER - -config STM32_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART1_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART1 Driver Configuration - -choice - prompt "USART2 Driver Configuration" - depends on STM32_USART2 - default STM32_USART2_SERIALDRIVER - -config STM32_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART2_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART2 Driver Configuration - -choice - prompt "USART3 Driver Configuration" - depends on STM32_USART3 - default STM32_USART3_SERIALDRIVER - -config STM32_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART3_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART3 Driver Configuration - -choice - prompt "UART4 Driver Configuration" - depends on STM32_UART4 - default STM32_UART4_SERIALDRIVER - -config STM32_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART1 Driver Configuration - -choice - prompt "UART5 Driver Configuration" - depends on STM32_UART5 - default STM32_UART5_SERIALDRIVER - -config STM32_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -choice - prompt "USART6 Driver Configuration" - depends on STM32_USART6 - default STM32_USART6_SERIALDRIVER - -config STM32_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART6_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART6 Driver Configuration - -choice - prompt "LPUART1 Driver Configuration" - depends on STM32_LPUART1 - default STM32_LPUART1_SERIALDRIVER - -config STM32_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -choice - prompt "USART4 Driver Configuration" - depends on STM32_USART4 - default STM32_USART4_SERIALDRIVER - -config STM32_USART4_SERIALDRIVER - bool "Standard serial driver" - select USART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART4 Driver Configuration - -choice - prompt "USART5 Driver Configuration" - depends on STM32_USART5 - default STM32_USART5_SERIALDRIVER - -config STM32_USART5_SERIALDRIVER - bool "Standard serial driver" - select USART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART5 Driver Configuration - -choice - prompt "USART7 Driver Configuration" - depends on STM32_USART7 - default STM32_USART7_SERIALDRIVER - -config STM32_USART7_SERIALDRIVER - bool "Standard serial driver" - select USART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART7 Driver Configuration - -choice - prompt "USART8 Driver Configuration" - depends on STM32_USART8 - default STM32_USART8_SERIALDRIVER - -config STM32_USART8_SERIALDRIVER - bool "Standard serial driver" - select USART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART8 Driver Configuration - -choice - prompt "UART7 Driver Configuration" - depends on STM32_COMMON_LEGACY && STM32_UART7 - default STM32_UART7_SERIALDRIVER - -config STM32_UART7_SERIALDRIVER - bool "Standard serial driver" - select UART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART7_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART7 Driver Configuration - -if STM32_UART7_HCIUART - -config STM32_HCIUART7_RXBUFSIZE - int "HCI UART7 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART7_TXBUFSIZE - int "HCI UART7 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART7_BAUD - int "HCI UART7 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART7_RXDMA - bool "HCI UART7 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART7_HCIUART - -choice - prompt "UART8 Driver Configuration" - depends on STM32_COMMON_LEGACY && STM32_UART8 - default STM32_UART8_SERIALDRIVER - -config STM32_UART8_SERIALDRIVER - bool "Standard serial driver" - select UART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART8_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART8 Driver Configuration - -if STM32_UART8_HCIUART - -config STM32_HCIUART8_RXBUFSIZE - int "HCI UART8 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART8_TXBUFSIZE - int "HCI UART8 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART8_BAUD - int "HCI UART8 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART8_RXDMA - bool "HCI UART8 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART8_HCIUART - -choice - prompt "RTC clock source" - depends on STM32_RTC - default STM32_RTC_LSECLOCK - -config STM32_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice # RTC clock source - -choice - prompt "MII clock configuration" - depends on STM32_MII - default STM32_MII_MCO if STM32_STM32F10XX - default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - default STM32_MII_EXTCLK - -config STM32_MII_MCO - bool "Use MC0 as MII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the MII interface. Default: Use MC0 - -config STM32_MII_MCO1 - bool "Use MC01 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the MII interface. Default: Use MC01 - -config STM32_MII_MCO2 - bool "Use MC02 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the MII interface. Default: Use MC01 - -config STM32_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for MII - clock. Default: Use MC0[1] - -endchoice - -choice - prompt "RMII clock configuration" - depends on STM32_RMII - default STM32_RMII_MCO if STM32_STM32F10XX - default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - default STM32_RMII_EXTCLK - -config STM32_RMII_MCO - bool "Use MC0 as RMII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the RMII interface. Default: Use MC0 - -config STM32_RMII_MCO1 - bool "Use MC01 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_MCO2 - bool "Use MC02 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for RMII - clock. Default: Use MC0[1] - -endchoice - -choice - prompt "CAN character driver or SocketCAN support" +menu "CAN Configuration" depends on STM32_CAN - default STM32_CAN_CHARDRIVER +source "arch/arm/src/common/stm32/Kconfig.can" +endmenu # CAN Configuration -config STM32_CAN_CHARDRIVER - bool "STM32F7 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_CAN_SOCKET - bool "STM32F7 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support - -choice - prompt "FDCAN character driver or SocketCAN support" +menu "FDCAN Configuration" depends on STM32_FDCAN - default STM32_FDCAN_CHARDRIVER +source "arch/arm/src/common/stm32/Kconfig.fdcan" +endmenu # FDCAN Configuration -config STM32_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN +menu "DAC Configuration" + depends on STM32_DAC +source "arch/arm/src/common/stm32/Kconfig.dac" +endmenu # DAC Configuration -config STM32_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD +menu "DFSDM Configuration" + depends on STM32_DFSDM1 || STM32_MDF1 || STM32_ADF1 +source "arch/arm/src/common/stm32/Kconfig.dfsdm" +endmenu # DFSDM Configuration -endchoice # FDCAN character driver or SocketCAN support +menu "DMA Configuration" + depends on STM32_DMA || STM32_DMA2D +source "arch/arm/src/common/stm32/Kconfig.dma" +endmenu # DMA Configuration -if STM32_FDCAN1 +menu "Ethernet Configuration" + depends on STM32_ETHMAC +source "arch/arm/src/common/stm32/Kconfig.eth" +endmenu # Ethernet Configuration -choice - prompt "FDCAN1 frame format" - default STM32_FDCAN1_ISO11898_1 +menu "Flash Configuration" +source "arch/arm/src/common/stm32/Kconfig.flash" +endmenu # Flash Configuration -config STM32_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format +menu "FOC Configuration" + depends on STM32_HAVE_COMMON_FOC +source "arch/arm/src/common/stm32/Kconfig.foc" +endmenu # FOC Configuration -config STM32_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 +menu "GPIO Configuration" +source "arch/arm/src/common/stm32/Kconfig.gpio" +endmenu # GPIO Configuration -endchoice # FDCAN1 frame format +menu "I2C Configuration" + depends on STM32_I2C +source "arch/arm/src/common/stm32/Kconfig.i2c" +endmenu # I2C Configuration -choice - prompt "FDCAN1 mode" - default STM32_FDCAN1_CLASSIC +menu "IPCC Configuration" + depends on STM32_IPCC || STM32_HAVE_HSEM +source "arch/arm/src/common/stm32/Kconfig.ipcc" +endmenu # IPCC Configuration -config STM32_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode +menu "BLE Configuration" + depends on STM32_BLE || STM32_MBOX +source "arch/arm/src/common/stm32/Kconfig.ble" +endmenu # BLE Configuration -config STM32_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -endif # STM32_FDCAN1 - -if STM32_FDCAN2 - -choice - prompt "FDCAN2 frame format" - default STM32_FDCAN2_ISO11898_1 - -config STM32_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32_FDCAN2_CLASSIC - -config STM32_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode - -endif # STM32_FDCAN2 - -choice - prompt "Layer 1 color format" +menu "LTDC Configuration" depends on STM32_LTDC - default STM32_LTDC_L1_RGB565 - -config STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32_FB_CMAP - -endchoice # Layer 1 color format - -choice - prompt "Layer 2 (top layer) color format" - depends on STM32_LTDC && STM32_LTDC_L2 - default STM32_LTDC_L2_RGB565 - -config STM32_LTDC_L2_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_LTDC_L1_L8 - -config STM32_LTDC_L2_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_LTDC_L1_AL44 - -config STM32_LTDC_L2_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_LTDC_L1_AL88 - -config STM32_LTDC_L2_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - -config STM32_LTDC_L2_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - -config STM32_LTDC_L2_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB1555 - -config STM32_LTDC_L2_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - -config STM32_LTDC_L2_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - -endchoice # Layer 2 color format - -choice - prompt "Input channel sampling frequency" - depends on STM32_QENCODER_FILTER - default STM32_QENCODER_SAMPLE_FDTS_4 - -config STM32_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - prompt "Input channel event count" - depends on STM32_QENCODER_FILTER - default STM32_QENCODER_SAMPLE_EVENT_6 - -config STM32_QENCODER_SAMPLE_EVENT_1 - bool "1" - depends on STM32_QENCODER_SAMPLE_FDTS - -config STM32_QENCODER_SAMPLE_EVENT_2 - bool "2" - depends on STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_4 - bool "4" - depends on STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_5 - bool "5" - depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 - -config STM32_QENCODER_SAMPLE_EVENT_6 - bool "6" - depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_8 - bool "8" - depends on !STM32_QENCODER_SAMPLE_FDTS - -endchoice - -choice - prompt "FOC ADC trigger selection" - depends on STM32_FOC - default STM32_FOC_ADC_TRGO - -config STM32_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on STM32_HAVE_IP_ADC_V2 || (STM32_HAVE_IP_ADC_V1 && !STM32_FOC_FOC1) - select STM32_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" - -choice - prompt "FOC0 device ADC selection" - depends on STM32_FOC_FOC0 - default STM32_FOC_FOC0_ADC1 - -config STM32_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC0_ADC4 - bool "FOC0 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" - -choice - prompt "FOC1 device ADC selection" - depends on STM32_FOC_FOC1 - default STM32_FOC_FOC1_ADC2 - -config STM32_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC1_ADC4 - bool "FOC1 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" - -choice - prompt "Override Flash Size Designator" - default STM32_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32F series parts numbering (sans the package type) ends with a number or letter - that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32G071RB is chosen, the Flash configuration would be 'B', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - -config STM32_FLASH_OVERRIDE_4 - bool "4 16KiB" - -config STM32_FLASH_OVERRIDE_6 - bool "6 32KiB" - -config STM32_FLASH_OVERRIDE_8 - bool "8 64KiB" - -config STM32_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32_FLASH_OVERRIDE_D - bool "D 384KiB" - -config STM32_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32_FLASH_OVERRIDE_F - bool "F 768KiB" - -config STM32_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32_FLASH_OVERRIDE_I - bool "I 2048KiB" - -config STM32_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32_FLASH_OVERRIDE_C_256 - bool "C 256 KB" - -config STM32_FLASH_OVERRIDE_C_320 - bool "C 320 KB" - -config STM32_FLASH_OVERRIDE_E_512 - bool "E 512 KB" - -config STM32_FLASH_OVERRIDE_Y_640 - bool "Y 640 KB" - -config STM32_FLASH_OVERRIDE_G_1024 - bool "G 1024 KB" - -endchoice # Override Flash Size Designator - -choice - prompt "Select TIM15 ADC channel" - depends on STM32_TIM15_ADC - default STM32_TIM15_ADC1 - -config STM32_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -choice - prompt "Transfer technique" - depends on STM32_QSPI - default STM32_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32_QSPI_DMA - bool "DMA" - depends on STM32_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - depends on STM32_QSPI - default STM32_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - depends on STM32_QSPI && STM32_QSPI_DMA && STM32_DMA - default STM32_QSPI_DMAPRIORITY_MEDIUM - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32_DMA - ---help--- - 'Highest' priority. - -config STM32_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32_DMA - ---help--- - 'High' priority. - -config STM32_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32_DMA - ---help--- - 'Medium' priority. - -config STM32_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32_DMA - ---help--- - 'Low' priority. - -endchoice - -choice - prompt "Operation mode" - depends on STM32_SAI - default STM32_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - depends on STM32_SAI1_A && STM32_SAI1_B - default STM32_SAI1_BOTH_ASYNC - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - depends on STM32_SAI2_A && STM32_SAI2_B - default STM32_SAI2_BOTH_ASYNC - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -choice - prompt "Select ADC for use with TIM6" - depends on STM32_TIM6_ADC - default STM32_TIM6_ADC1 - -config STM32_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32_TIM6_ADC3 - bool "Use TIM6 for ADC3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -choice - prompt "LPTIM1 clock source" - default STM32_LPTIM1_CLK_APB1 - -config STM32_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" - -endchoice - -choice - prompt "LPTIM2 clock source" - default STM32_LPTIM2_CLK_APB1 - -config STM32_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" - -endchoice - -config STM32_TIM_PWM_COMMON - bool - default y if STM32_COMMON_FULL_FEATURED - -config STM32_TIM_PWM_NO_F0_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 - -config STM32_TIM_PWM_ADVANCED_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_SINGLECHAN_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_INTERNAL_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 - -config STM32_TIM_PWM_STM32PWM_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 - -config STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - bool - default y if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_CHMODE_LEGACY_COMMON - bool - default y if STM32_COMMON_LEGACY && !STM32_HAVE_IP_TIMERS_V2 - -config STM32_TIM_PWM_CHMODE_LIMITED_COMMON - bool - default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L5_U5 - -config STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 - -config STM32_ADC_TIMTRIG_TRGO2_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 - -config STM32_ADC_TIMTRIG_TRGO_COMMON - bool - default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 - -config STM32_TIM_PWM_NOUT_REQUIRES_OUT_COMMON - bool - default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5 - -config STM32_PWM_MULTICHAN_L5_TIMERS - bool - default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM - default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM - default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_PWM - default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM - default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS - -config STM32_SPI_CORE_DMA_CAPABLE - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 - default y if STM32_COMMON_F7_H7_H5 - default y if ARCH_CHIP_STM32WL5 - default y if STM32_COMMON_L4_L5_U5 && STM32_SPI - default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA - -config STM32_SPI_DMA_FAMILY_WL5 - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 - -config STM32_SPI_DMA_FAMILY - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default y if STM32_COMMON_H7_H5 - -config STM32_RTC_MAGIC_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER - default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_RTC - default y if (STM32_COMMON_L5_U5 || ARCH_CHIP_STM32WB) && STM32_RTC - -config STM32_ADC1_TIMER_FREQ_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC1_TIMER - -config STM32_ADC1_TIMTRIG_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_HAVE_ADC1_TIMER - default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_HAVE_ADC1_TIMER - -config STM32_ADC2_TIMER_FREQ_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER - default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC2_TIMER - -config STM32_ADC2_TIMTRIG_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER - default y if (STM32_COMMON_F7_H7_H5) && STM32_HAVE_ADC2_TIMER - default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC2_TIMER - -config STM32_ADC3_TIMER_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC3_TIMER - default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3_TIMER - default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC3_TIMER - -config STM32_QENCODER_TIMS_1_4 - bool - default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 - -config STM32_QENCODER_TIMS_1_8 - bool - default y if STM32_QENCODER_TIMS_1_4 - default y if STM32_TIM5 || STM32_TIM8 - -config STM32_QENCODER_MAIN_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 - default y if STM32_COMMON_L4_L5_U5 - -config STM32_QENCODER_MAIN - bool - default y if STM32_QENCODER_MAIN_COMMON && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 - -config STM32_QENCODER_STM32 - bool - default y if STM32_COMMON_LEGACY && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 - -config STM32_QENCODER_F0 - bool - default y if STM32_COMMON_F0_L0_G0_C0 && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 - -config STM32_QENCODER_16BIT_CAPABLE - bool - default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 - -config STM32_LPTIM1_CH1OUT_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 - -config STM32_LPTIM1_CH1NOUT_CAPABLE - bool - default y if STM32_LPTIM1_CH1OUT_CAPABLE && STM32_LPTIM1_CH1OUT - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 - -config STM32_LPTIM2_CH1OUT_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 - -config STM32_LPTIM2_CH1NOUT_CAPABLE - bool - default y if STM32_LPTIM2_CH1OUT_CAPABLE && STM32_LPTIM2_CH1OUT - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 - -config STM32_ADC1_DFSDM_L4_CHIP - bool - default y if STM32_STM32L496XX || STM32_STM32L4XR - -config STM32_ADC1_DFSDM_L5_CHIP - bool - default y if STM32_STM32L596XX || STM32_STM32L5XR - -config STM32_ADC1_DFSDM_U5_CHIP - bool - default y if STM32_STM32U596XX || STM32_STM32U5XR - -config STM32_ADC1_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L4_CHIP - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L5_CHIP - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_U5_CHIP - -config STM32_ADC2_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L496XX - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L596XX - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32U596XX - -config STM32_ADC3_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L496XX - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L596XX - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32U596XX - -config STM32_FLASH_CONFIG_4 - bool - -config STM32_FLASH_CONFIG_6 - bool - -config STM32_FLASH_CONFIG_8 - bool - -config STM32_FLASH_CONFIG_B - bool - -config STM32_FLASH_CONFIG_C - bool - -config STM32_FLASH_CONFIG_D - bool - -config STM32_FLASH_CONFIG_E - bool - -config STM32_FLASH_CONFIG_F - bool - -config STM32_FLASH_CONFIG_G - bool - -config STM32_FLASH_CONFIG_I - bool - -config STM32_ENERGYLITE - bool - select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY - -config STM32_VALUELINE - bool - select STM32_HAVE_USART3 if STM32_COMMON_LEGACY - select STM32_HAVE_UART4 if STM32_COMMON_LEGACY - select STM32_HAVE_UART5 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM1 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM5 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM12 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM13 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM14 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM15 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM16 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM17 if STM32_COMMON_LEGACY - select STM32_HAVE_SPI2 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY - select STM32_HAVE_USART5 if STM32_COMMON_F0_L0_G0_C0 - select STM32_HAVE_SPI2 if STM32_COMMON_F0_L0_G0_C0 - -config STM32_DFU - bool "DFU bootloader" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - -# These hidden settings determine whether a peripheral option is available -# for the selected MCU. Family Kconfigs select these from chip data. - -config STM32_HAVE_AES - bool - -config STM32_HAVE_CRYP - bool - -config STM32_HAVE_CCM - bool - -config STM32_HAVE_DMAMUX - bool - -config STM32_HAVE_USBDEV - bool - -config STM32_HAVE_USBFS - bool - -config STM32_HAVE_OTGFS - bool - -config STM32_HAVE_FMC - bool - -config STM32_HAVE_FSMC - bool - -config STM32_HAVE_SYSCFG - bool - -config STM32_HAVE_FDCAN1 - bool - -config STM32_HAVE_FDCAN2 - bool - -config STM32_HAVE_FDCAN3 - bool - -config STM32_HAVE_LTDC - bool - -config STM32_HAVE_USART2 - bool - -config STM32_HAVE_USART3 - bool - -config STM32_HAVE_UART4 - bool - -config STM32_HAVE_UART5 - bool - -config STM32_HAVE_USART6 - bool - -config STM32_HAVE_UART7 - bool - -config STM32_HAVE_UART8 - bool - -config STM32_HAVE_TIM1 - bool - -config STM32_HAVE_TIM2 - bool - -config STM32_HAVE_TIM3 - bool - -config STM32_HAVE_TIM4 - bool - -config STM32_HAVE_TIM5 - bool - -config STM32_HAVE_TIM6 - bool - -config STM32_HAVE_TIM7 - bool - -config STM32_HAVE_TIM8 - bool - -config STM32_HAVE_TIM9 - bool - -config STM32_HAVE_TIM10 - bool - -config STM32_HAVE_TIM11 - bool - -config STM32_HAVE_TIM12 - bool - -config STM32_HAVE_TIM13 - bool - -config STM32_HAVE_TIM14 - bool - -config STM32_HAVE_TIM15 - bool - -config STM32_HAVE_TIM16 - bool - -config STM32_HAVE_TIM17 - bool - -config STM32_HAVE_TSC - bool - -config STM32_HAVE_ADC2 - bool - -config STM32_HAVE_ADC3 - bool - -config STM32_HAVE_ADC4 - bool - -config STM32_HAVE_ADC5 - bool - -config STM32_HAVE_ADC1_DMA - bool - -config STM32_HAVE_ADC2_DMA - bool - -config STM32_HAVE_ADC3_DMA - bool - -config STM32_HAVE_ADC4_DMA - bool - -config STM32_HAVE_ADC5_DMA - bool - -config STM32_HAVE_ADC_OVERSAMPLE - bool - default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 - -config STM32_HAVE_ADC4_TIMER - bool - -config STM32_HAVE_ADC5_TIMER - bool - -config STM32_HAVE_CAN1 - bool - -config STM32_HAVE_CAN2 - bool - -config STM32_HAVE_CAN3 - bool - -config STM32_HAVE_COMP1 - bool - -config STM32_HAVE_COMP2 - bool - -config STM32_HAVE_COMP3 - bool - -config STM32_HAVE_COMP4 - bool - -config STM32_HAVE_COMP5 - bool - -config STM32_HAVE_COMP6 - bool - -config STM32_HAVE_COMP7 - bool - -config STM32_HAVE_CRS - bool - -config STM32_HAVE_CEC - bool - -config STM32_HAVE_CORDIC - bool - -config STM32_HAVE_DSIHOST - bool - -config STM32_HAVE_JPEG - bool - -config STM32_HAVE_INTERNAL_ULPI - bool - -config STM32_HAVE_EXTERNAL_ULPI - bool - -config STM32_HAVE_HRTIM1 - bool - -config STM32_HAVE_HRTIM1_PLLCLK - bool - -config STM32_HAVE_TIM18 - bool - -config STM32_HAVE_TIM19 - bool - -config STM32_HAVE_TIM20 - bool - -config STM32_HAVE_SDADC1 - bool - -config STM32_HAVE_SDADC2 - bool - -config STM32_HAVE_SDADC3 - bool - -config STM32_HAVE_SDADC1_DMA - bool - -config STM32_HAVE_SDADC2_DMA - bool - -config STM32_HAVE_SDADC3_DMA - bool - -config STM32_HAVE_SDIO - bool - -config STM32_HAVE_UCPD1 - bool - -config STM32_HAVE_UCPD2 - bool - -config STM32_HAVE_RTC_COUNTER - bool - -config STM32_HAVE_IP_DBGMCU_V1 - bool - -config STM32_HAVE_IP_DBGMCU_V2 - bool - -config STM32_HAVE_IP_DBGMCU_V3 - bool - -config STM32_HAVE_IP_I2C_V1 - bool - -config STM32_HAVE_IP_I2C_V2 - bool - -config STM32_HAVE_IP_DMA_V1 - bool - -config STM32_HAVE_IP_DMA_V2 - bool - -config STM32_HAVE_IP_TIMERS_V1 - bool - -config STM32_HAVE_IP_TIMERS_V2 - bool - -config STM32_HAVE_IP_TIMERS_V3 - bool - -config STM32_HAVE_IP_ADC_V1 - bool - -config STM32_HAVE_IP_ADC_V1_BASIC - bool - select STM32_HAVE_IP_ADC_V1 - -config STM32_HAVE_IP_ADC_V2 - bool - -config STM32_HAVE_IP_ADC_V2_BASIC - bool - select STM32_HAVE_IP_ADC_V2 - -config STM32_HAVE_IP_COMP_V1 - bool - -config STM32_HAVE_IP_COMP_V2 - bool - -config STM32_HAVE_IP_DAC_V1 - bool - -config STM32_HAVE_IP_DAC_V2 - bool - -config STM32_HAVE_IP_USART_V1 - bool - -config STM32_HAVE_IP_USART_V2 - bool - -config STM32_HAVE_IP_EXTI_V1 - bool - -config STM32_HAVE_IP_EXTI_V2 - bool - -config STM32_HAVE_FMAC - bool - -config STM32_HAVE_FLASH_ICACHE - bool - -config STM32_HAVE_FLASH_DCACHE - bool - -config STM32_HAVE_OVERDRIVE - bool - -config STM32_HAVE_DMA1_CHAN8 - bool - -config STM32_HAVE_DMA2_CHAN678 - bool - -config STM32_HAVE_UCPD - bool - -config STM32_HAVE_DAC1 - bool - -config STM32_HAVE_DAC2 - bool - -config STM32_HAVE_DAC3 - bool - -config STM32_HAVE_DAC4 - bool - -config STM32_HAVE_QSPI - bool - -config STM32_HAVE_RNG - bool - -config STM32_HAVE_VREFINT - bool - -config STM32_HAVE_I2C1 - bool - -config STM32_HAVE_I2C2 - bool - -config STM32_HAVE_I2C3 - bool - -config STM32_HAVE_I2C4 - bool - -config STM32_HAVE_SDMMC1 - bool - -config STM32_HAVE_SDMMC2 - bool - -config STM32_HAVE_LPTIM1 - bool - -config STM32_HAVE_LPUART1 - bool - -config STM32_HAVE_LPUART2 - bool - -config STM32_HAVE_SPI1 - bool - -config STM32_HAVE_SPI2 - bool - -config STM32_HAVE_SPI3 - bool - -config STM32_HAVE_I2S3 - bool - -config STM32_HAVE_I2S2 - bool - -config STM32_HAVE_SPI2S2 - bool - -config STM32_HAVE_SPI4 - bool - -config STM32_HAVE_SPI5 - bool - -config STM32_HAVE_SPI6 - bool - -config STM32_HAVE_SAIPLL - bool - -config STM32_HAVE_I2SPLL - bool - -config STM32_HAVE_OPAMP1 - bool - -config STM32_HAVE_OPAMP2 - bool - -config STM32_HAVE_OPAMP3 - bool - -config STM32_HAVE_OPAMP4 - bool - -config STM32_HAVE_OPAMP5 - bool - -config STM32_HAVE_OPAMP6 - bool - -config STM32_HAVE_IOCOMPENSATION - bool - -config STM32_HAVE_ICACHE - bool - -config STM32_HAVE_ETHMAC - bool - -config STM32_HAVE_ETHRNET - bool - -config STM32_HAVE_LPUART - bool - -config STM32_HAVE_SAI - bool - -config STM32_HAVE_USB - bool - -config STM32_GPIO_HAVE_PORTD - bool - -config STM32_GPIO_HAVE_PORTE - bool - -config STM32_HAVE_GPIOF - bool - -config STM32_HAVE_GPIOG - bool - -config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY - bool - -config STM32_HAVE_OTA_PARTITION - bool - -config STM32_HAVE_CM4 - bool - -config STM32_HAVE_USART4 - bool - -config STM32_HAVE_USART5 - bool - -config STM32_HAVE_USART7 - bool - -config STM32_HAVE_USART8 - bool - -config STM32_HAVE_UART9 - bool - -config STM32_HAVE_USART10 - bool - -config STM32_HAVE_USART11 - bool - -config STM32_HAVE_UART12 - bool - -config STM32_HAVE_ADC1 - bool - default y if STM32_COMMON_LEGACY - -config STM32_ADC1 - bool "ADC1" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 - select STM32_ADC if !ARCH_CHIP_STM32U5 - select STM32_HAVE_ADC1_DMA if STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC1_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC2 - bool "ADC2" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 - select STM32_ADC - select STM32_HAVE_ADC2_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC2_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC3 - bool "ADC3" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 - select STM32_ADC - select STM32_HAVE_ADC3_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC3_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC4 - bool "ADC4" - depends on (STM32_COMMON_LEGACY && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 - select STM32_ADC if STM32_COMMON_LEGACY - select STM32_HAVE_ADC4_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) - -config STM32_COMP1 - bool "COMP1" - depends on STM32_HAVE_COMP1 - select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - depends on STM32_HAVE_COMP2 - select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP2 - -config STM32_CORDIC - bool "CORDIC Accelerator" - depends on (STM32_COMMON_LEGACY && STM32_HAVE_CORDIC && MATH_CORDIC_USE_Q31) || ARCH_CHIP_STM32U5 - -config STM32_BKP - bool "BKP" - depends on (STM32_COMMON_LEGACY && STM32_STM32F10XX) || STM32_COMMON_F0_L0_G0_C0 - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - select STM32_PWR if ARCH_CHIP_STM32H7 - -config STM32_CAN1 - bool "CAN1" - depends on STM32_HAVE_CAN1 - select STM32_CAN - select CAN if !STM32_COMMON_LEGACY - -config STM32_CAN2 - bool "CAN2" - depends on STM32_HAVE_CAN2 - select STM32_CAN - select CAN if !STM32_COMMON_LEGACY - -config STM32_CAN3 - bool "CAN3" - depends on STM32_HAVE_CAN3 - select STM32_CAN - select CAN - -config STM32_AES - bool "128-bit AES" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32L4) && STM32_HAVE_AES || ARCH_CHIP_STM32U5 - select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST - -config STM32_CEC - bool "CEC" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_VALUELINE || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_CEC || ARCH_CHIP_STM32F7 - -config STM32_CRC - bool "CRC" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB - -config STM32_CRS - bool "CRS (Clock Recovery System)" - depends on STM32_HAVE_CRS - -config STM32_CRYP - bool "CRYP" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_HAVE_CRYP || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_HASH - -config STM32_DMA1 - bool "DMA1" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32WB - select STM32_DMA - select ARCH_DMA - select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - -config STM32_DMA2 - bool "DMA2" - depends on STM32_HAVE_DMA2 - select STM32_DMA - select ARCH_DMA - select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - -config STM32_DMAMUX1 - bool "DMAMUX1" - depends on STM32_HAVE_DMAMUX - select STM32_DMAMUX - -config STM32_DAC1 - bool "DAC1" - depends on STM32_HAVE_DAC1 - select STM32_DAC if !ARCH_CHIP_STM32U5 - -config STM32_DAC2 - bool "DAC2" - depends on STM32_HAVE_DAC2 - select STM32_DAC - -config STM32_DCMI - bool "DCMI" - depends on STM32_HAVE_DCMI - ---help--- - The devices embed a camera interface that can connect with camera - modules and CMOS sensors through an 8-bit to 14-bit parallel interface, - to receive video data. - -config STM32_DSIHOST - bool "DSIHOST" - depends on STM32_HAVE_DSIHOST - ---help--- - The DSI Host is a dedicated peripheral for interfacing with MIPI DSI - compliant displays. - -config STM32_ETHMAC - bool "Ethernet MAC" - depends on STM32_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32_HAVE_PHY_POLLED if !STM32_COMMON_LEGACY - -config STM32_FDCAN1 - bool "FDCAN1" - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN if !ARCH_CHIP_STM32U5 - -config STM32_FDCAN2 - bool "FDCAN2" - depends on STM32_HAVE_FDCAN2 - select STM32_FDCAN - -config STM32_FDCAN3 - bool "FDCAN3" - depends on STM32_HAVE_FDCAN3 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - depends on STM32_HAVE_FSMC - -config STM32_FMC - bool "FMC" - depends on STM32_HAVE_FMC - ---help--- - Enable Flexible Memory Controller. - To correctly configure FMC for your hardware, you will have to define - a number of macros in your board.h file. See stm32_fmc.c for directions. - -config STM32_FMAC - bool "FMAC (Filter Math Accelerator)" - depends on STM32_HAVE_FMAC - -config STM32_HASH - bool "HASH" - depends on STM32_HAVE_HASH - select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH - -config STM32_JPEG - bool "JPEG" - depends on STM32_HAVE_JPEG - ---help--- - The JPEG codec provides a hardware compressor and decompressor of JPEG - images with full management of JPEG headers. - -config STM32_I2C1 - bool "I2C1" - depends on STM32_HAVE_I2C1 - select STM32_I2C - select I2C if ARCH_CHIP_STM32WB - -config STM32_I2C2 - bool "I2C2" - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - depends on STM32_HAVE_I2C3 - select STM32_I2C - select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 - -config STM32_LPTIM1 - bool "LPTIM1" - depends on STM32_HAVE_LPTIM1 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - -config STM32_LPUART1 - bool "LPUART1" - depends on STM32_HAVE_LPUART1 - select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY - select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART - -config STM32_VREFINT - bool "Enable VREFINT" - depends on STM32_HAVE_VREFINT - -config STM32_USART4 - bool "USART4" - depends on STM32_HAVE_USART4 - select STM32_USART - -config STM32_USART5 - bool "USART5" - depends on STM32_HAVE_USART5 - select STM32_USART - -config STM32_USART7 - bool "USART7" - depends on STM32_HAVE_USART7 - select STM32_USART - -config STM32_USART8 - bool "USART8" - depends on STM32_HAVE_USART8 - select STM32_USART - -config STM32_LTDC - bool "LTDC" - depends on STM32_HAVE_LTDC - select FB - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F429 and STM32F439 devices. It is a standard parallel - video interface (HSYNC, VSYNC, etc.) for controlling TFT - LCD displays. - -config STM32_DMA2D - bool "DMA2D" - depends on STM32_HAVE_DMA2D - select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D - select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32F429 and STM32F439 devices. - -config STM32_RTC - bool "RTC" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32WB - select RTC if !ARCH_CHIP_STM32L5 - -config STM32_OTGFS - bool "OTG FS" - depends on STM32_HAVE_OTGFS - select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST - -config STM32_OTGHS - bool "OTG HS" - depends on (STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX)) || (ARCH_CHIP_STM32H7 && EXPERIMENTAL) || (ARCH_CHIP_STM32U5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX)) - select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST - -config STM32_OTGFSHS - bool "OTG FS/HS" - depends on ARCH_CHIP_STM32F7 - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32_PWR - bool "PWR" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_L5_U5 || ARCH_CHIP_STM32WB - -config STM32_QSPI - bool "QSPI (QUADSPI)" - depends on STM32_HAVE_QSPI - ---help--- - The STM32L4 QSPI block is intended to support one serial NOR flash device - -config STM32_RNG - bool "RNG" - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 - -config STM32_SDIO - bool "SDIO" - depends on (STM32_COMMON_LEGACY && !STM32_CONNECTIVITYLINE && !STM32_VALUELINE) || (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_SDIO) - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - depends on STM32_HAVE_SPI1 - select SPI if !ARCH_CHIP_STM32WL5 - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_I2S1 - bool "I2S1" - depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 - select STM32_I2S - -config STM32_I2S2 - bool "I2S2" - depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 - select STM32_I2S - -config STM32_I2S3 - bool "I2S3" - depends on STM32_HAVE_I2S3 - select I2S if STM32_COMMON_LEGACY - select STM32_I2S - -config STM32_SPI2S2 - bool "SPI2S2" - depends on STM32_HAVE_SPI2S2 - select STM32_SPI - -config STM32_SPDIFRX - bool "SPDIFRX" - depends on ARCH_CHIP_STM32F7 - -config STM32_SPI4 - bool "SPI4" - depends on STM32_HAVE_SPI4 - select SPI - select STM32_SPI - -config STM32_SPI5 - bool "SPI5" - depends on STM32_HAVE_SPI5 - select SPI - select STM32_SPI - -config STM32_SPI6 - bool "SPI6" - depends on STM32_HAVE_SPI6 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - depends on STM32_HAVE_SYSCFG - default y - -config STM32_TIM1 - bool "TIM1" - depends on STM32_HAVE_TIM1 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM2 - bool "TIM2" - depends on STM32_HAVE_TIM2 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM3 - bool "TIM3" - depends on STM32_HAVE_TIM3 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM4 - bool "TIM4" - depends on STM32_HAVE_TIM4 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM5 - bool "TIM5" - depends on STM32_HAVE_TIM5 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM6 - bool "TIM6" - depends on STM32_HAVE_TIM6 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM7 - bool "TIM7" - depends on STM32_HAVE_TIM7 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM8 - bool "TIM8" - depends on STM32_HAVE_TIM8 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM9 - bool "TIM9" - depends on STM32_HAVE_TIM9 - select STM32_TIM - -config STM32_TIM10 - bool "TIM10" - depends on STM32_HAVE_TIM10 - select STM32_TIM - -config STM32_TIM11 - bool "TIM11" - depends on STM32_HAVE_TIM11 - select STM32_TIM - -config STM32_TIM12 - bool "TIM12" - depends on STM32_HAVE_TIM12 - select STM32_TIM - -config STM32_TIM13 - bool "TIM13" - depends on STM32_HAVE_TIM13 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - depends on STM32_HAVE_TIM15 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM16 - bool "TIM16" - depends on STM32_HAVE_TIM16 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM17 - bool "TIM17" - depends on STM32_HAVE_TIM17 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TSC - bool "TSC" - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - depends on STM32_HAVE_USART1 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART2 - bool "USART2" - depends on STM32_HAVE_USART2 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART3 - bool "USART3" - depends on STM32_HAVE_USART3 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART4 - bool "UART4" - depends on STM32_HAVE_UART4 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART5 - bool "UART5" - depends on STM32_HAVE_UART5 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART6 - bool "USART6" - depends on STM32_HAVE_USART6 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART7 - bool "UART7" - depends on STM32_HAVE_UART7 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART8 - bool "UART8" - depends on STM32_HAVE_UART8 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USB - bool "USB Device" - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_USBFS - bool "USB Full Speed Device" - depends on STM32_HAVE_USBFS - select USBDEV - select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 - -config STM32_LCD - bool "Segment LCD" - depends on STM32_HAVE_LCD - select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD - -config STM32_IWDG - bool "IWDG" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - select WATCHDOG if !ARCH_CHIP_STM32U5 - -config STM32_ADC - bool - -config STM32_DAC - bool - -config STM32_DMA - bool - select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - select STM32_DMAMUX if ARCH_CHIP_STM32WB - -config STM32_DMAMUX - bool - -config STM32_SPI - bool - -config STM32_SPI_DMA - bool "SPI DMA" - depends on STM32_SPI_CORE_DMA_CAPABLE - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_I2S - bool - select STM32_SPI_DMA if STM32_COMMON_LEGACY - select STM32_SPI_DMA if ARCH_CHIP_STM32F7 - -config STM32_I2C - bool - -config STM32_CAN - bool - -config STM32_FDCAN - bool - select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 - select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 - select NET_CAN_EXTID if ARCH_CHIP_STM32H7 - select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 - -config STM32_TIM - bool - -config STM32_PWM - bool - -config STM32_COMP - bool "COMP" - depends on STM32_HAVE_COMP - select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP - -config STM32_OPAMP - bool "OPAMP" - depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - -config STM32_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - depends on STM32_HAVE_IOCOMPENSATION - select STM32_CSI if ARCH_CHIP_STM32H7 - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - -config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - depends on (STM32_COMMON_LEGACY && ((STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE)) || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR)) - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -config STM32_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 if STM32_COMMON_LEGACY - default y - ---help--- - Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled - on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch - properly and enabling this option may interfere with ADC accuracy. - -config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config STM32_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA - default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32_EXTERNAL_RAM - bool "External RAM on FSMC/FMC" - depends on (STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC)) || (ARCH_CHIP_STM32F7 && STM32_FMC) - select ARCH_HAVE_HEAP2 if STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC) - select ARCH_HAVE_HEAP2 if ARCH_CHIP_STM32F7 && STM32_FMC - ---help--- - In addition to internal SRAM, external RAM may be available through the FSMC/FMC. - -config STM32_TICKLESS_TIMER - int "Tickless hardware timer" - depends on SCHED_TICKLESS - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB - default 2 - range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32_TICKLESS_CHANNEL - int "Tickless timer channel" - depends on SCHED_TICKLESS - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -config STM32_ONESHOT - bool "TIM one-shot wrapper" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 - default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32_FREERUN - bool "TIM free-running wrapper" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 - default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - depends on STM32_ONESHOT - depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - default 1 - range 1 8 - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32_PWM_LL_OPS - bool "PWM low-level operations" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - ---help--- - Enable low-level PWM ops. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - depends on STM32_TIM1 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM1_MODE - int "TIM1 Mode" - depends on STM32_TIM1_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM1_LOCK - int "TIM1 Lock Level Configuration" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32_TIM1_TDTS - int "TIM1 t_DTS Division" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 3 Complementary Output. - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - depends on STM32_TIM1_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 - ---help--- - Enables channel 5 (not available externally) - -config STM32_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 5 output. - -config STM32_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 - ---help--- - Enables channel 6 (not available externally) - -config STM32_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 6 output. - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP - range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_PWM - bool "TIM2 PWM" - depends on STM32_TIM2 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM2_MODE - int "TIM2 Mode" - depends on STM32_TIM2_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - depends on STM32_TIM2_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_PWM - bool "TIM3 PWM" - depends on STM32_TIM3 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM3_MODE - int "TIM3 Mode" - depends on STM32_TIM3_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - depends on STM32_TIM3_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_PWM - bool "TIM4 PWM" - depends on STM32_TIM4 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM4_MODE - int "TIM4 Mode" - depends on STM32_TIM4_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - depends on STM32_TIM4_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM4_CHMODE - int "TIM4 Channel Mode" - depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_PWM - bool "TIM5 PWM" - depends on STM32_TIM5 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM5_MODE - int "TIM5 Mode" - depends on STM32_TIM5_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - depends on STM32_TIM5_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM5_CHMODE - int "TIM5 Channel Mode" - depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_PWM - bool "TIM8 PWM" - depends on STM32_TIM8 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM8_MODE - int "TIM8 Mode" - depends on STM32_TIM8_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM8_LOCK - int "TIM8 Lock Level Configuration" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32_TIM8_TDTS - int "TIM8 t_DTS Division" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -config STM32_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 3 Complementary Output. - -config STM32_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - depends on STM32_TIM8_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 - ---help--- - Enables channel 5 (not available externally) - -config STM32_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 5 output. - -config STM32_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 - ---help--- - Enables channel 6 (not available externally) - -config STM32_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 6 output. - -config STM32_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP - range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM8_CHMODE - int "TIM8 Channel Mode" - depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_PWM - bool "TIM9 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - depends on STM32_TIM9_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 2. - -config STM32_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - depends on STM32_TIM9_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) - ---help--- - Enables channel 2 output. - -config STM32_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP - range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM9_CAP - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM9_CHMODE - int "TIM9 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_PWM - bool "TIM10 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - depends on STM32_TIM10_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM10_CAP - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM10_CHMODE - int "TIM10 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_PWM - bool "TIM11 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - depends on STM32_TIM11_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM11_CAP - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM11_CHMODE - int "TIM11 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_PWM - bool "TIM12 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - depends on STM32_TIM12_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - depends on STM32_TIM12_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP - range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM12_CAP - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM12_CHMODE - int "TIM12 Channel Mode" - depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_PWM - bool "TIM13 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - depends on STM32_TIM13_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM13_CAP - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM13_CHMODE - int "TIM13 Channel Mode" - depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_PWM - bool "TIM14 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7_H5) && STM32_TIM14 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 - default 0 if STM32_COMMON_F0_L0_G0_C0 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - range 0 1 if STM32_COMMON_F0_L0_G0_C0 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - depends on STM32_TIM14_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM14_CAP - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_COMMON_F0_L0_G0_C0 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - range 0 1 if STM32_COMMON_F0_L0_G0_C0 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_PWM - bool "TIM15 PWM" - depends on STM32_TIM15 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM15_LOCK - int "TIM15 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32_TIM15_TDTS - int "TIM15 t_DTS Division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if ARCH_CHIP_STM32L4 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if ARCH_CHIP_STM32L4 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 - depends on STM32_TIM_PWM_SINGLECHAN_COMMON - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_PWM - bool "TIM16 PWM" - depends on STM32_TIM16 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM16_LOCK - int "TIM16 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32_TIM16_TDTS - int "TIM16 t_DTS division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - depends on STM32_TIM16_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_PWM - bool "TIM17 PWM" - depends on STM32_TIM17 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM17_LOCK - int "TIM17 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32_TIM17_TDTS - int "TIM17 t_DTS Division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - depends on STM32_TIM17_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - depends on STM32_PWM_MULTICHAN_CAPABLE - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32_PULSECOUNT - bool - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - depends on STM32_TIM1 - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select STM32_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - depends on !STM32_COMMON_F0_L0_G0_C0 - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - depends on !STM32_COMMON_F0_L0_G0_C0 - -config STM32_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - depends on !STM32_COMMON_F0_L0_G0_C0 - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM8_PULSECOUNT - bool "TIM8 pulse count" - depends on STM32_TIM8 - depends on STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select STM32_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32_TIM8_PULSECOUNT - -config STM32_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM8_PULSECOUNT - -config STM32_PWM_TRGO - bool "TIM PWM TRGO support" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) - ---help--- - Enable TRGO support for PWM driver - -config STM32_TIM1_ADC - bool "TIM1 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM1 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM2_ADC - bool "TIM2 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM2 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM3_ADC - bool "TIM3 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM3 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM4_ADC - bool "TIM4 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM4 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM5_ADC - bool "TIM5 ADC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_ADC) || (ARCH_CHIP_STM32F7 && STM32_TIM5 && STM32_ADC) - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM8_ADC - bool "TIM8 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM8 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_HAVE_ADC2_TIMER - bool - -config STM32_HAVE_ADC3_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - depends on STM32_ADC1_TIMER_FREQ_CAPABLE - default 100 - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - depends on STM32_ADC1_TIMTRIG_CAPABLE - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - depends on STM32_ADC2_TIMER_FREQ_CAPABLE - default 100 - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - depends on STM32_ADC2_TIMTRIG_CAPABLE - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - depends on STM32_ADC3_TIMER_CAPABLE - default 100 - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - depends on STM32_ADC3_TIMER_CAPABLE && !ARCH_CHIP_STM32L4 - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_TIM1_DAC - bool "TIM1 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM1 && STM32_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM2_DAC - bool "TIM2 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM2 && STM32_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM3_DAC - bool "TIM3 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM3 && STM32_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM4_DAC - bool "TIM4 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM4 && STM32_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM5_DAC - bool "TIM5 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM5 && STM32_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM6_DAC - bool "TIM6 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM6 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM6 && STM32_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM7_DAC - bool "TIM7 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM7 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM7 && STM32_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM8_DAC - bool "TIM8 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM8 && STM32_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM9_DAC - bool "TIM9 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM9 && STM32_DAC) - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM10_DAC - bool "TIM10 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM10 && STM32_DAC) - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM11_DAC - bool "TIM11 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM11 && STM32_DAC) - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM12_DAC - bool "TIM12 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM12 && STM32_DAC) - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM13_DAC - bool "TIM13 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM13 && STM32_DAC) - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM14_DAC - bool "TIM14 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM14 && STM32_DAC) - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM1_CAP - bool "TIM1 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM1_CLOCK - int "TIM1 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM2_CAP - bool "TIM2 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM2_CLOCK - int "TIM2 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM3_CAP - bool "TIM3 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM3_CLOCK - int "TIM3 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM4_CAP - bool "TIM4 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM4_CLOCK - int "TIM4 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM5_CAP - bool "TIM5 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM5_CLOCK - int "TIM5 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM8_CAP - bool "TIM8 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM8_CLOCK - int "TIM8 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM9_CAP - bool "TIM9 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM10_CAP - bool "TIM10 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM11_CAP - bool "TIM11 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM12_CAP - bool "TIM12 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM12_CLOCK - int "TIM12 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM13_CAP - bool "TIM13 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM13_CLOCK - int "TIM13 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM14_CAP - bool "TIM14 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM14_CLOCK - int "TIM14 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 output polarity - -config STM32_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 output IDLE - -config STM32_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 output polarity - -config STM32_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 output IDLE - -config STM32_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 output polarity - -config STM32_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 output IDLE - -config STM32_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 4 output polarity - -config STM32_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 4 output IDLE - -config STM32_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 5 output polarity - -config STM32_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 5 output IDLE - -config STM32_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 6 output polarity - -config STM32_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 6 output IDLE - -config STM32_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 1 output polarity - -config STM32_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 1 output IDLE - -config STM32_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 2 output polarity - -config STM32_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 2 output IDLE - -config STM32_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 3 output polarity - -config STM32_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 3 output IDLE - -config STM32_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 4 output polarity - -config STM32_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 4 output IDLE - -config STM32_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 1 output polarity - -config STM32_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 1 output IDLE - -config STM32_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 2 output polarity - -config STM32_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 2 output IDLE - -config STM32_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 3 output polarity - -config STM32_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 3 output IDLE - -config STM32_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 4 output polarity - -config STM32_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 4 output IDLE - -config STM32_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 1 output polarity - -config STM32_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 1 output IDLE - -config STM32_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 2 output polarity - -config STM32_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 2 output IDLE - -config STM32_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 3 output polarity - -config STM32_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 3 output IDLE - -config STM32_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 4 output polarity - -config STM32_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 4 output IDLE - -config STM32_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 1 output polarity - -config STM32_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 1 output IDLE - -config STM32_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 2 output polarity - -config STM32_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 2 output IDLE - -config STM32_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 3 output polarity - -config STM32_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 3 output IDLE - -config STM32_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 4 output polarity - -config STM32_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 4 output IDLE - -config STM32_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 output polarity - -config STM32_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 output IDLE - -config STM32_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 output polarity - -config STM32_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 output IDLE - -config STM32_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 output polarity - -config STM32_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 output IDLE - -config STM32_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 4 output polarity - -config STM32_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 4 output IDLE - -config STM32_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 5 output polarity - -config STM32_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 5 output IDLE - -config STM32_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 6 output polarity - -config STM32_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 6 output IDLE - -config STM32_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 1 output polarity - -config STM32_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 1 output IDLE - -config STM32_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 2 output polarity - -config STM32_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 2 output IDLE - -config STM32_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT - default 0 - range 0 1 - ---help--- - TIM10 Channel 1 output polarity - -config STM32_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT - default 0 - range 0 1 - ---help--- - TIM10 Channel 1 output IDLE - -config STM32_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT - default 0 - range 0 1 - ---help--- - TIM11 Channel 1 output polarity - -config STM32_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT - default 0 - range 0 1 - ---help--- - TIM11 Channel 1 output IDLE - -config STM32_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 1 output polarity - -config STM32_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 1 output IDLE - -config STM32_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 2 output polarity - -config STM32_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 2 output IDLE - -config STM32_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT - default 0 - range 0 1 - ---help--- - TIM13 Channel 1 output polarity - -config STM32_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT - default 0 - range 0 1 - ---help--- - TIM13 Channel 1 output IDLE - -config STM32_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT - default 0 - range 0 1 - ---help--- - TIM14 Channel 1 output polarity - -config STM32_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT - default 0 - range 0 1 - ---help--- - TIM14 Channel 1 output IDLE - -config STM32_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 output polarity - -config STM32_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 output IDLE - -config STM32_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 output polarity - -config STM32_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 output IDLE - -config STM32_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT - default 0 - range 0 1 - ---help--- - TIM16 Channel 1 output polarity - -config STM32_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT - default 0 - range 0 1 - ---help--- - TIM16 Channel 1 output IDLE - -config STM32_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT - default 0 - range 0 1 - ---help--- - TIM17 Channel 1 output polarity - -config STM32_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT - default 0 - range 0 1 - ---help--- - TIM17 Channel 1 output IDLE - -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC || (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - depends on STM32_ADC - default 1 if STM32_COMMON_F0_L0_G0_C0 && !STM32_ADC1_DMA - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - depends on STM32_ADC - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - depends on STM32_ADC - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - depends on STM32_ADC - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC_OVERSAMPLE - bool "Enable ADC hardware oversampling support" - depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32_ADC_OVERSAMPLE - -config STM32_ADC_TOVS - bool "Enable triggered oversampling (CFGR2.TOVS)" - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32_ADC_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2x - 1 -> 4x - 2 -> 8x - ... - 7 -> 256x - -config STM32_ADC_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32_ADC_OVERSAMPLE - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_HAVE_ADC1_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_SCAN - bool "ADC1 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) - default STM32_ADC1_DMA - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC1_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC2_DMA - bool "ADC2 DMA" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_HAVE_ADC2_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC2_SCAN - bool "ADC2 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) - default STM32_ADC2_DMA - -config STM32_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC3_DMA - bool "ADC3 DMA" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_HAVE_ADC3_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC3_SCAN - bool "ADC3 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) - default STM32_ADC3_DMA - -config STM32_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - default 0 - range 0 4 - ---help--- - Support for ADC1 injected channels. - -config STM32_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - default 0 - range 0 4 - ---help--- - Support for ADC2 injected channels. - -config STM32_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - default 0 - range 0 4 - ---help--- - Support for ADC3 injected channels. - -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - ---help--- - Enable EXTSEL for ADC1. - -config STM32_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_HAVE_ADC2_TIMER - ---help--- - Enable EXTSEL for ADC2. - -config STM32_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_HAVE_ADC3_TIMER - ---help--- - Enable EXTSEL for ADC3. - -config STM32_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - ---help--- - Enable JEXTSEL for ADC1. - -config STM32_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - ---help--- - Enable JEXTSEL for ADC2. - -config STM32_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - ---help--- - Enable JEXTSEL for ADC3. - -config STM32_USART - bool - -config USART1_RS485 - bool "RS-485 on USART1" - depends on STM32_USART1 && USART1_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -if USART1_RS485 - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART1_RS485 - -config USART1_RXDMA - bool - depends on STM32_USART1 && USART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool - depends on STM32_USART1 && USART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART2_RS485 - bool "RS-485 on USART2" - depends on STM32_USART2 && USART2_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -if USART2_RS485 - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART2_RS485 - -config USART2_RXDMA - bool - depends on STM32_USART2 && USART2_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool - depends on STM32_USART2 && USART2_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART3_RS485 - bool "RS-485 on USART3" - depends on STM32_USART3 && USART3_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -if USART3_RS485 - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART3_RS485 - -config USART3_RXDMA - bool - depends on STM32_USART3 && USART3_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool - depends on STM32_USART3 && USART3_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART4_RS485 - bool "RS-485 on UART4" - depends on STM32_UART4 && UART4_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -if UART4_RS485 - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART4_RS485 - -config UART4_RXDMA - bool - depends on STM32_UART4 && UART4_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool - depends on STM32_UART4 && UART4_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART5_RS485 - bool "RS-485 on UART5" - depends on STM32_UART5 && UART5_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -if UART5_RS485 - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART5_RS485 - -config UART5_RXDMA - bool - depends on STM32_UART5 && UART5_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool - depends on STM32_UART5 && UART5_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART6_RS485 - bool "RS-485 on USART6" - depends on STM32_USART6 && USART6_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -if USART6_RS485 - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART6_RS485 - -config USART6_RXDMA - bool - depends on STM32_USART6 && USART6_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool - depends on STM32_USART6 && USART6_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART7_RS485 - bool "RS-485 on UART7" - depends on STM32_UART7 && UART7_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -if UART7_RS485 - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART7_RS485 - -config UART7_RXDMA - bool - depends on STM32_UART7 && UART7_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool - depends on STM32_UART7 && UART7_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART8_RS485 - bool "RS-485 on UART8" - depends on STM32_UART8 && UART8_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -if UART8_RS485 - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART8_RS485 - -config UART8_RXDMA - bool - depends on STM32_UART8 && UART8_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool - depends on STM32_UART8 && UART8_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - depends on STM32_LPUART1 && LPUART1_SERIALDRIVER - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -if LPUART1_RS485 - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # LPUART1_RS485 - -config LPUART1_RXDMA - bool - depends on STM32_LPUART1 && LPUART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config STM32_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - depends on STM32_USART && SERIAL_RXDMA - range 32 4096 - default 32 - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." +source "arch/arm/src/common/stm32/Kconfig.ltdc" +endmenu # LTDC Configuration + +menu "Memory Configuration" +source "arch/arm/src/common/stm32/Kconfig.memory" +endmenu # Memory Configuration + +menu "QSPI/OCTOSPI Configuration" + depends on STM32_QSPI || STM32_QSPI1 || STM32_OCTOSPI1 || STM32_OCTOSPI2 +source "arch/arm/src/common/stm32/Kconfig.qspi" +endmenu # QSPI/OCTOSPI Configuration + +menu "RTC Configuration" + depends on STM32_RTC +source "arch/arm/src/common/stm32/Kconfig.rtc" +endmenu # RTC Configuration + +menu "SAI Configuration" +source "arch/arm/src/common/stm32/Kconfig.sai" +endmenu # SAI Configuration + +menu "SDIO/SDMMC Configuration" + depends on STM32_SDIO || STM32_SDMMC +source "arch/arm/src/common/stm32/Kconfig.sdio" +endmenu # SDIO/SDMMC Configuration + +menu "COMP Configuration" + depends on STM32_COMP +source "arch/arm/src/common/stm32/Kconfig.comp" +endmenu # COMP Configuration + +menu "DTS Configuration" + depends on STM32_DTS +source "arch/arm/src/common/stm32/Kconfig.dts" +endmenu # DTS Configuration + +menu "U[S]ART Configuration" depends on STM32_USART - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32_USART - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32_USART - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32_USART_BREAKS - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32 serial driver. - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - depends on PM - depends on STM32_USART - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -config LPUART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure LPUART1 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER - -config LPUART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure LPUART1 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER - -config LPUART1_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure LPUART1 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER - -config USART1_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART1 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 - -config USART2_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART2 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER - -config USART2_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART2 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER - -config USART2_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART2 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 - -config USART3_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART3 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER - -config USART3_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART3 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER - -config USART3_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART3 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 - -config UART4_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART4 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER - -config UART4_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART4 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER - -config UART4_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART4 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 - -config UART5_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART5 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER - -config UART5_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART5 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER - -config UART5_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART5 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 - -config USART6_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART6 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER - -config USART6_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART6 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER - -config USART6_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART6 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 - -config UART7_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART7 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER - -config UART7_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART7 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER - -config UART7_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART7 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 - -config UART8_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART8 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER - -config UART8_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART8 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER - -config UART8_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART8 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 - -config UART9_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART9 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER - -config UART9_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART9 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER - -config UART9_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART9 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 - -config USART10_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART10 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER - -config USART10_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART10 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER - -config USART10_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART10 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 - -config USART11_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART11 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER - -config USART11_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART11 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER - -config USART11_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART11 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 - -config UART12_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART12 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER - -config UART12_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART12 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER - -config UART12_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART12 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - depends on STM32_SPI - depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - depends on STM32_SPI && STM32_SPI1 - depends on STM32_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32_SPI_DMATHRESHOLD - int "SPI DMA threshold" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA - default 4 - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - depends on STM32_SPI && STM32_SPI2 - depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - depends on STM32_SPI && STM32_SPI3 - depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32_SPI4_DMA - bool "SPI4 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32_SPI5_DMA - bool "SPI5 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32_SPI6_DMA - bool "SPI6 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2S2_DMA - bool "SPI2S2 DMA" - depends on STM32_SPI2 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2S2 transfer performance. Cannot be used with - STM32_SPI_INTERRUPT. - -config STM32_SPI2S2_DMA_BUFFER - int "SPI2S2 DMA buffer size" - default 0 - depends on STM32_SPI2S2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. - -config STM32_I2S_MAXINFLIGHT - int "I2S queue size" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -config STM32_I2S3_DATALEN - int "Data width (bits)" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -config STM32_I2S1_MCK - bool "I2S1_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - TBD. - -config STM32_I2S1_RX - bool "Enable I2S1 receiver" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - Enable I2S receipt logic - -config STM32_I2S1_TX - bool "Enable I2S1 transmitter" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - Enable I2S transmission logic - -config STM32_I2S1_DATALEN - int "I2S1 Data width (bits)" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - default 16 - ---help--- - Data width in bits. This is a default value and may be changed via - the I2S interface. - -config STM32_I2S2_MCK - bool "I2S2_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - TBD. - -config STM32_I2S2_RX - bool "Enable I2S2 receiver" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - Enable I2S receipt logic - -config STM32_I2S2_TX - bool "Enable I2S2 transmitter" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - Enable I2S transmission logic - -config STM32_I2S2_DATALEN - int "I2S2 Data width (bits)" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - default 16 - ---help--- - Data width in bits. This is a default value and may be changed via - the I2S interface. - -config STM32_I2S3_MCK - bool "I2S3_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S3 - ---help--- - TBD. - -#if STM32_I2S - -config STM32_I2S3_RX - bool "Enable I2S receiver" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - ---help--- - Enable I2S receipt logic - -config STM32_I2S3_TX - bool "Enable I2S transmitter" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - ---help--- - Enable I2S transmission logic - -config STM32_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO - default 500 - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO - default 1000 - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C - default 0 - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO - default 500 - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO - default 500 - -config STM32_BBSRAM - bool "BBSRAM File Support" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM - select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM - -config STM32_BBSRAM_FILES - int "Max Files to support in BBSRAM" - depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM - default 4 - -config STM32_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM - -config STM32_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - -config STM32_RTC_MAGIC_REG - int "BKP register" - depends on STM32_RTC_MAGIC_CAPABLE - default 0 - range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER - range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32_RTC_MAGIC - hex "RTC Magic 1" - depends on STM32_RTC_MAGIC_CAPABLE - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - depends on STM32_RTC_MAGIC_CAPABLE - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -if STM32_ETHMAC - -config STM32_PHYADDR - int "PHY address" - default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32_PHYINIT - bool "Board-specific PHY Initialization" - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32_MII - bool "Use MII interface" - ---help--- - Support Ethernet MII interface. - -config STM32_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -if !STM32_AUTONEG - -config STM32_ETHFD - bool "Full duplex" - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32_ETH100MBPS - bool "100 Mbps" - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -endif # !STM32_AUTONEG - -if STM32_AUTONEG - -config STM32_PHYSR - int "PHY Status Register Address (decimal)" - ---help--- - This must be provided if STM32_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -if !STM32_PHYSR_ALTCONFIG - -config STM32_PHYSR_SPEED - hex "PHY Speed Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32_PHYSR_MODE - hex "PHY Mode Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -endif # !STM32_PHYSR_ALTCONFIG - -if STM32_PHYSR_ALTCONFIG - -config STM32_PHYSR_ALTMODE - hex "PHY Mode Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32_PHYSR_100HD - hex "100Base-T Half Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32_PHYSR_10FD - hex "10Base-T Full Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32_PHYSR_100FD - hex "100Base-T Full Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -endif # STM32_PHYSR_ALTCONFIG - -endif # STM32_AUTONEG - -config STM32_ETH_PTP - bool "Precision Time Protocol (PTP)" - ---help--- - Enables Precision Time Protocol (PTP) hardware timer. - -config STM32_ETH_ENHANCEDDESC - bool "Enable enhanced RX/TX descriptors" - depends on STM32_COMMON_LEGACY - default n - ---help--- - Enables double-length DMA descriptors that have space for packet - timestamps and checksum offloading. - -config STM32_ETH_PTP_GPIO - bool "PTP pulse-per-second output signal" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP - default n - ---help--- - Enables pulse-per-second output on GPIO pin. - -config STM32_ETH_PTP_RTC_HIRES - bool "Use PTP timer as system high-resolution RTC" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP - default n - ---help--- - Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. - This provides high resolution timestamps to clock_gettime(). - Note that PTP timer is disabled when Ethernet interface is down or - being reset. During this time g_rtc_enabled is set to false and system - uses the lower resolution system tick counter. - -config STM32_ETH_TIMESTAMP_RX - bool "Hardware timestamping of received packets" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC - select ARCH_HAVE_NETDEV_TIMESTAMP - default n - ---help--- - Timestamp all received Ethernet packets. - Timestamp is available to application through SO_TIMESTAMP socket option. - -config STM32_RMII - bool - default !STM32_MII - -config STM32_ETHMAC_REGDEBUG - bool "Register-Level Debug" - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. - -endif # STM32_ETHMAC - -config STM32_USBHOST_REGDEBUG - bool "Register-Level Debug" - depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST - ---help--- - Enable very low-level register access debug. - -config STM32_USBHOST_PKTDUMP - bool "Packet Dump Debug" - depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST - ---help--- - Dump all incoming and outgoing USB packets. - -config STM32_USBFS_REGDEBUG - bool "Register-Level Debug" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -menu "STM32_OTG_HS Configuration" - depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS - -choice - prompt "ULPI Selection" - default STM32_NO_ULPI - -config STM32_NO_ULPI - bool "No External ULPI" - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32_EXTERNAL_ULPI - bool "External ULPI" - depends on STM32_HAVE_EXTERNAL_ULPI - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32_INTERNAL_ULPI - bool "Internal ULPI PHY" - depends on STM32_HAVE_INTERNAL_ULPI - ---help--- - Select to enable the internal ULPI for USB HS - -endchoice # "ULPI Selection" - -endmenu # STM32_OTG_HS Configuration - -menu "OTG_HS Configuration" - depends on ARCH_CHIP_STM32H7 && STM32_OTGHS - -config STM32_OTGHS_FS - bool "OTGHS in FS mode" - default n - -choice - prompt "ULPI Selection" - default STM32_OTGHS_NO_ULPI - -config STM32_OTGHS_NO_ULPI - bool "No External ULPI on board." - ---help--- - Select to indicate that there is no external ULPI PHY. This means - the OTG_HS peripheral must use the internal full-speed PHY and will - be limited to full-speed mode. - -config STM32_OTGHS_EXTERNAL_ULPI - bool "External ULPI" - ---help--- - Select to indicate the presence of an external ULPI PHY and use it. - -endchoice # "ULPI Selection" - -endmenu # OTG_HS Configuration - -menu "OTG Configuration" - depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) - -choice - prompt "STM32H7 OTGFS role" - depends on STM32_OTGFS - default STM32_OTGFS_USBDEV if USBDEV - default STM32_OTGFS_HOST if !USBDEV && USBHOST - -config STM32_OTGFS_USBDEV - bool "OTGFS as USBDEV" - depends on USBDEV - -config STM32_OTGFS_HOST - bool "OTGFS as HOST" - depends on USBHOST - -endchoice # "STM32H7 OTGFS role" - -choice - prompt "STM32H7 OTGHS role (only USBDEV supported for now)" - depends on STM32_OTGHS - default STM32_OTGHS_USBDEV if USBDEV - -config STM32_OTGHS_USBDEV - bool "OTGHS as USBDEV" - depends on USBDEV - -endchoice # "STM32H7 OTGHS role" - -endmenu # OTG Configuration - -config STM32_USBHOST - bool "Enable USB Host Support" - depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) - default n - select USBHOST - -menu "USB FS Host Configuration" - depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST - -config STM32_OTGFS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGFS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGFS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGFS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG FS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu # USB FS Host Configuration - -menu "USB HS Host Configuration" - depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST - -config STM32_OTGHS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGHS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGHS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGHS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG HS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu # USB HS Host Configuration - -config STM32_CAN1_BAUD - int "CAN1 BAUD" - depends on STM32_CAN1 - default 250000 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. - -config STM32_CAN2_BAUD - int "CAN2 BAUD" - depends on STM32_CAN2 - default 250000 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. - -config STM32_CAN3_BAUD - int "CAN3 BAUD" - depends on STM32_CAN3 - default 250000 - ---help--- - CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. - -config STM32_CAN_TSEG1 - int "TSEG1 quanta" - depends on STM32_CAN - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32_CAN_TSEG2 - int "TSEG2 quanta" - depends on STM32_CAN - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32_CAN_REGDEBUG - bool "CAN Register level debug" - depends on STM32_CAN && DEBUG_CAN_INFO - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_REGDEBUG - bool "FDCAN register-level debug" - depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - depends on STM32_FDCAN - -config STM32_FDCAN_LOOPBACK - bool "Enable FDCAN loopback mode" - depends on ARCH_CHIP_STM32H7 && STM32_FDCAN - default n - ---help--- - Enable the FDCAN local loopback mode for testing purposes. - Requires a further choice of internal or external loopback mode. - -choice - prompt "FDCAN Loopback Mode" - depends on STM32_FDCAN_LOOPBACK - default STM32_FDCAN_LOOPBACK_INTERNAL - -config STM32_FDCAN_LOOPBACK_INTERNAL - bool "Internal loopback mode" - ---help--- - Enable internal loopback mode, where both Tx and Rx are - disconnected from the CAN bus. This can be used for a "Hot Selftest", - meaning the FDCAN can be used without affecting a running CAN bus. - - All transmitted frames are treated as received frames and processed - accordingly. - -config STM32_FDCAN_LOOPBACK_EXTERNAL - bool "External loopback mode" - ---help--- - Enable external loopback mode, where the Rx pin is disconnected from - the CAN bus but the Tx pin remains connected. - - All transmitted frames are treated as received frames and processed - accordingly. - -endchoice # FDCAN Loopback Mode - -choice - prompt "FDCAN WorkQueue Selection" - depends on ARCH_CHIP_STM32H7 && STM32_FDCAN - default STM32_FDCAN_LPWORK - -config STM32_FDCAN_LPWORK - bool "Use LP work queue" - ---help--- - Use the low-priority (LP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -config STM32_FDCAN_HPWORK - bool "Use HP work queue" - ---help--- - Use the high-priority (HP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -endchoice # FDCAN WorkQueue Selection - -if STM32_FDCAN1 - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -config STM32_FDCAN1_BITRATE - int "FDCAN1 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_AUTO_BIT_TIMING - bool "FDCAN1 automatic bit timing" - depends on ARCH_CHIP_STM32H5 - default y - ---help--- - Automatically determine FDCAN1 bit timing (nominal and data) - based on bitrate. - -if !STM32_FDCAN1_AUTO_BIT_TIMING - -comment "FDCAN1 nominal bit timing" - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -endif # !STM32_FDCAN1_AUTO_BIT_TIMING - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - default 2000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING - -comment "FDCAN1 data bit timing" - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING - -endif # STM32_FDCAN1 - -if STM32_FDCAN2 - -config STM32_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -config STM32_FDCAN2_BITRATE - int "FDCAN2 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. - -config STM32_FDCAN2_AUTO_BIT_TIMING - bool "FDCAN2 automatic bit timing" - depends on ARCH_CHIP_STM32H5 - default y - ---help--- - Automatically determine FDCAN2 bit timing (nominal and data) - based on bitrate. - -if !STM32_FDCAN2_AUTO_BIT_TIMING - -comment "FDCAN2 nominal bit timing" - -config STM32_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -endif # !STM32_FDCAN2_AUTO_BIT_TIMING - -config STM32_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - depends on CAN_FD && STM32_FDCAN2_FD_BRS - default 2000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING - -comment "FDCAN2 data bit timing" - -config STM32_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING - -endif # STM32_FDCAN2 - -if STM32_FDCAN3 - -choice - prompt "FDCAN3 frame format" - default STM32_FDCAN3_ISO11898_1 - -config STM32_FDCAN3_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN3_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN3 frame format - -choice - prompt "FDCAN3 mode" - default STM32_FDCAN3_CLASSIC - -config STM32_FDCAN3_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN3_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN3_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN3 mode - -config STM32_FDCAN3_LOOPBACK - bool "Enable FDCAN3 loopback mode" - default n - ---help--- - Enable the FDCAN3 local loopback mode for testing purposes. - -config STM32_FDCAN3_BITRATE - int "FDCAN3 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. - -comment "FDCAN3 nominal bit timing" - -config STM32_FDCAN3_NTSEG1 - int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NTSEG2 - int "FDCAN3 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NSJW - int "FDCAN3 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DBITRATE - int "FDCAN3 data bitrate" - depends on CAN_FD && STM32_FDCAN3_FD_BRS - default 2000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN3_FD_BRS - -comment "FDCAN3 data bit timing" - -config STM32_FDCAN3_DTSEG1 - int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DTSEG2 - int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DSJW - int "FDCAN3 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN3_FD_BRS - -endif # STM32_FDCAN3 - -if STM32_LTDC - -config STM32_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value. - -config STM32_LTDC_DITHER - bool "Dither support" - -config STM32_LTDC_FB_DOUBLE_BUFFER - bool "Enable double buffering" - depends on ARCH_CHIP_STM32H7 - default n - ---help--- - Enable double buffering to allow updates to the framebuffer while - the display is being refreshed. This configuration requires two - framebuffers: one active and one inactive. When the display - refreshes, the active and inactive framebuffers are swapped, - enabling smooth and flicker-free updates. - -if STM32_LTDC_DITHER - -config STM32_LTDC_DITHER_RED - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32_LTDC_DITHER_GREEN - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32_LTDC_DITHER_BLUE - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -endif # STM32_LTDC_DITHER - -config STM32_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -config STM32_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32_LTDC_L2 - -config STM32_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -endif # STM32_LTDC_L2 - -config STM32_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - Enabling color map support is necessary for LTDC L8 format. - -config STM32_FB_TRANSPARENCY - bool "Transparency color map support" - depends on STM32_FB_CMAP - default y - select FB_TRANSPARENCY - ---help--- - Enabling transparency color map support is necessary for LTDC L8 format. - -config STM32_LTDC_REGDEBUG - bool "LTDC Register level debug" - depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 - ---help--- - Output detailed register-level LTDC device debug information. - -endif # STM32_LTDC - -if STM32_DMA2D - -config STM32_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -config STM32_DMA2D_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 - default y - -config STM32_DMA2D_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 - default y - -config STM32_DMA2D_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 - default y - -config STM32_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - default y - -config STM32_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - default y - -config STM32_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB15555 - default y - -config STM32_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - default y - -config STM32_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - default y - -config STM32_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - ---help--- - Output detailed register-level DMA2D device debug information. - -endif # STM32_DMA2D - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - depends on STM32_QENCODER_16BIT_CAPABLE - ---help--- - Disable the extension of 16-bit timers to 32-bit via interrupt-based - overflow tracking. When enabled, timers will use their native hardware - counter width (16-bit or 32-bit). This reduces interrupt overhead but - limits the position range for 16-bit timers. - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - depends on STM32_QENCODER_16BIT_CAPABLE - ---help--- - Enable support for quadrature encoder index pin. The index pin can be - used to reset the encoder position to a known value when the index - pulse is detected. - -config STM32_TIM1_QE - bool "TIM1 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM1) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM2_QE - bool "TIM2 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM2) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM3_QE - bool "TIM3 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM3) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM4_QE - bool "TIM4 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM4) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -config STM32_TIM4_QEPSC - int "TIM4 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM5_QE - bool "TIM5 QE" - depends on STM32_QENCODER_MAIN && STM32_TIM5 - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -config STM32_TIM5_QEPSC - int "TIM5 QE pulse prescaler" - depends on STM32_QENCODER_MAIN && STM32_TIM5_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM8_QE - bool "TIM8 QE" - depends on STM32_QENCODER_MAIN && STM32_TIM8 - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -config STM32_TIM8_QEPSC - int "TIM8 QE pulse prescaler" - depends on STM32_QENCODER_MAIN && STM32_TIM8_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 - default y - ---help--- - Enable input filtering on quadrature encoder channels to reduce noise. - -menuconfig STM32_FOC - bool "STM32 lower-half FOC support" - depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - select ARCH_IRQPRIO - select STM32_ADC - select STM32_PWM_MULTICHAN - select STM32_PWM_LL_OPS - select STM32_ADC_LL_OPS - select STM32_ADC_CHANGE_SAMPLETIME - select STM32_ADC_NO_STARTUP_CONV - -config STM32_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM1) || (ARCH_CHIP_STM32F7 && STM32_FOC) - select STM32_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM8) || (ARCH_CHIP_STM32F7 && STM32_FOC) - select STM32_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -config STM32_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_FOC - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32_FOC_USE_TIM1 - bool - select STM32_TIM1 - select STM32_TIM1_PWM - select STM32_TIM1_CHANNEL1 - select STM32_TIM1_CHANNEL2 - select STM32_TIM1_CHANNEL3 - select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1OUT - select STM32_TIM1_CH2OUT - select STM32_TIM1_CH3OUT - select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32_FOC_USE_TIM8 - bool - select STM32_TIM8 - select STM32_TIM8_PWM - select STM32_TIM8_CHANNEL1 - select STM32_TIM8_CHANNEL2 - select STM32_TIM8_CHANNEL3 - select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1OUT - select STM32_TIM8_CH2OUT - select STM32_TIM8_CH3OUT - select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32_FOC_USE_ADC1 - bool - select STM32_ADC1 - select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC1_JEXTSEL - -config STM32_FOC_USE_ADC2 - bool - select STM32_ADC2 - select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC2_JEXTSEL - -config STM32_FOC_USE_ADC3 - bool - select STM32_ADC3 - select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC3_JEXTSEL - -config STM32_PROGMEM - bool "Flash PROGMEM support" - depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 - select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM - select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - -config STM32_HAVE_HSI48 - bool - -config STM32_HAVE_LCD - bool - -config STM32_HAVE_DMA2 - bool - -config STM32_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -config STM32_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -config STM32_TIM15_ADC - bool "TIM15 ADC" - depends on (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART1_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART1) - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART2_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART2) - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config STM32_SPI1_COMMTYPE - int "SPI1 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI2_COMMTYPE - int "SPI2 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI3_COMMTYPE - int "SPI3 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_IO_CONFIG_R - bool - select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_V - bool - select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_I - bool - -config STM32_IO_CONFIG_Z - bool - -config STM32_IO_CONFIG_B - bool - -config STM32_IO_CONFIG_A - bool - -config STM32_HAVE_PHY_POLLED - bool - -config STM32_HAVE_DCMI - bool - -config STM32_HAVE_DMA2D - bool - -config STM32_HAVE_HASH - bool - -config STM32_HAVE_DFSDM1 - bool - -config STM32_HAVE_SAI1 - bool - -config STM32_HAVE_SAI2 - bool - -config STM32_SAI - bool - -menu "SDIO Configuration" - depends on STM32_COMMON_LEGACY && STM32_SDIO - -config STM32_SDIO_CARD - bool "SDIO Card support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config STM32_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config STM32_SDIO_DMA - bool "Support DMA data transfers" - default STM32_DMA2 - select SDIO_DMA - depends on STM32_DMA2 - ---help--- - Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. - -config STM32_SDIO_DMAPRIO - hex "SDIO DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - ---help--- - Select SDIO DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_SDIO_WIDTH_D1_ONLY - bool "Use D1 only" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDIO Configuration - -config STM32_SDMMC - bool - -config STM32_DFSDM1 - bool "DFSDM1" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 - select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 - -config STM32_I2C4 - bool "I2C4" - depends on STM32_HAVE_I2C4 - select STM32_I2C - -config STM32_QUADSPI - bool "QuadSPI" - depends on STM32_COMMON_F7_H7 - -config STM32_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - depends on STM32_COMMON_F7_H7 && USBDEV - -config STM32_SAI1 - bool "SAI1" - depends on STM32_HAVE_SAI1 - -config STM32_SAI1_A - bool "SAI1 Block A" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI1_B - bool "SAI1 Block B" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI2 - bool "SAI2" - depends on STM32_HAVE_SAI2 - -config STM32_SAI2_A - bool "SAI2 Block A" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI2_B - bool "SAI2 Block B" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SDMMC1 - bool "SDMMC1" - depends on STM32_HAVE_SDMMC1 - select STM32_SDMMC if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 - select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 - select SCHED_HPWORK if ARCH_CHIP_STM32L4 - select STM32_SAI1PLL if ARCH_CHIP_STM32L4 - -config STM32_SDMMC2 - bool "SDMMC2" - depends on STM32_HAVE_SDMMC2 - select STM32_SDMMC if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 - select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 - -config STM32_SDMMC_IDMA - bool "Support IDMA data transfers" - depends on ARCH_CHIP_STM32H7 && STM32_SDMMC - default y - select SDIO_DMA - ---help--- - Support IDMA data transfers. - -config STM32_USART_INVERT - bool "Signal Invert Support" - depends on STM32_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32F7 serial driver. - -config STM32_USART_SWAP - bool "Swap RX/TX pins support" - depends on STM32_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32F7 serial driver. - -config STM32_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 16777216 - range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires the size of the Flash be specified - -config STM32_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 4 - range 1 16 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - default 1 - range 1 8 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -config STM32_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA - default 4 - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on STM32_COMMON_F7_H7 && STM32_QUADSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -config STM32_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -if STM32_SDMMC - -config STM32_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32_SDMMC_DMA - bool "Support DMA data transfers" - depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA - select SDIO_DMA - ---help--- - Support DMA data transfers. - -config STM32_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 - default 0x00010000 if ARCH_CHIP_STM32F7 - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - depends on STM32_SDMMC1 - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endif # STM32_SDMMC - -config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK - default 0 - range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 - default 0 - range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - depends on STM32_COMMON_F7_H7 - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - depends on STM32_COMMON_F7_H7 && ARMV7M_HAVE_DTCM - default LIBC_ARCH_ELF - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - depends on STM32_COMMON_F7_H7 && ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -config STM32_PHY_POLLING - bool "Support network monitoring by polling the PHY" - depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32_LTDC_USE_DSI - bool "Use DSI as display connection" - depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32_HAVE_SMPS - bool - -config STM32_HAVE_ETHERNET - bool - -config STM32_LPTIM - bool - -config STM32_LPTIM2 - bool "LPTIM2" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - -config STM32_LPTIM3 - bool "LPTIM3" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 - select STM32_LPTIM if ARCH_CHIP_STM32H7 - -config STM32_LPTIM4 - bool "LPTIM4" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 - select STM32_LPTIM if ARCH_CHIP_STM32H7 - -config STM32_LPTIM5 - bool "LPTIM5" - depends on ARCH_CHIP_STM32H7 - select STM32_LPTIM - -config STM32_SPI4_COMMTYPE - int "SPI4 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI5_COMMTYPE - int "SPI5 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI6_COMMTYPE - int "SPI6 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_TIM6_ADC - bool "TIM6 ADC" - depends on (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM6 && STM32_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIMX_CAP - bool "Helpers for Capture Drivers" - depends on ARCH_CHIP_STM32H7 - default n - -config STM32_TIM15_CAP - bool "TIM15 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM15 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 - ---help--- - Reserve timer 15 for use by the capture driver. - -config STM32_TIM16_CAP - bool "TIM16 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM16 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 - ---help--- - Reserve timer 16 for use by the capture driver. - -config STM32_TIM17_CAP - bool "TIM17 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM17 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 - ---help--- - Reserve timer 17 for use by the capture driver. - -config STM32_TIM15_CLOCK - int "TIM15 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_TIM16_CLOCK - int "TIM16 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_TIM17_CLOCK - int "TIM17 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM1_CAP - bool "LPTIM1 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 1 for use by the capture driver. - -config STM32_LPTIM1_CLOCK - int "LPTIM1 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM2_CAP - bool "LPTIM2 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 2 for use by the capture driver. - -config STM32_LPTIM2_CLOCK - int "LPTIM2 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM1_CHANNEL - int "LPTIM1 Capture Input Channel" - depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) - default 1 - range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP - range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN - ---help--- - Specifies the timer input channel {1,2} for LPTIM1. - -config STM32_LPTIM2_CHANNEL - int "LPTIM2 Capture Input Channel" - depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) - default 1 - range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP - range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN - ---help--- - Specifies the timer input channel {1,2} for LPTIM2. - -config STM32_LPTIM3_CAP - bool "LPTIM3 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 3 for use by the capture driver. - -config STM32_LPTIM3_CHANNEL - int "LPTIM3 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM3. - -config STM32_LPTIM3_CLOCK - int "LPTIM3 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM4_CAP - bool "LPTIM4 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 4 for use by the capture driver. - -config STM32_LPTIM4_CHANNEL - int "LPTIM4 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM4. - -config STM32_LPTIM4_CLOCK - int "LPTIM4 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM5_CAP - bool "LPTIM5 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 5 for use by the capture driver. - -config STM32_LPTIM5_CHANNEL - int "LPTIM5 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM5. - -config STM32_LPTIM5_CLOCK - int "LPTIM5 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_ETH_NRXDESC - int "Number of RX descriptors" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32_ETH_NTXDESC - int "Number of TX descriptors" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32_ETH_HWCHECKSUM - bool "Enable ethernet hardware checksum" - depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC - ---help--- - Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload - engine in the Ethernet MAC. - When enabled, hardware generates checksums for TX and checks RX frames. - Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, - NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid - redundant verification in the network stack. - -config STM32_NO_PHY - bool "MAC has no PHY" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - -config STM32_IO_CONFIG_K - bool - -config STM32_IO_CONFIG_T - bool - -config STM32_IO_CONFIG_C - bool - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_J - bool - -config STM32_IO_CONFIG_M - bool - -config STM32_IO_CONFIG_Q - bool - -config STM32_SRAM2_HEAP - bool "SRAM2 is used for heap" - depends on STM32_COMMON_SRAM2_OPTIONS - select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 - ---help--- - The STM32L4 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32_SRAM2_INIT - bool "SRAM2 is initialized to zero" - depends on STM32_COMMON_SRAM2_OPTIONS - ---help--- - The STM32L4 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on (ARCH_CHIP_STM32L4 && STM32_STM32L4XR) || (ARCH_CHIP_STM32U5 && STM32_SRAM3) - default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR - ---help--- - Add the STM32L4 SRAM3 to the heap for use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32_HAVE_COMP - bool - -config STM32_HAVE_USART1 - bool - -config STM32_SAI1PLL - bool "SAI1PLL" - depends on STM32_COMMON_L4_L5_U5 - ---help--- - The STM32L4 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_SAI2PLL - bool "SAI2PLL" - depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 - ---help--- - The STM32L4 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT - default 2 - range 1 8 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32_TICKLESS_FREERUN - int "Tickless free-running timer channel" - depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN - default 5 - range 1 8 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -config STM32_LPTIM1_PWM - bool "LPTIM1 PWM" - depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_LPTIM2_PWM - bool "LPTIM2 PWM" - depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - depends on STM32_LPTIM1_CH1OUT_CAPABLE - ---help--- - Enables channel 1 output. - -config STM32_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - depends on STM32_LPTIM1_CH1NOUT_CAPABLE - ---help--- - Enables channel 1 complementary output. - -config STM32_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - depends on STM32_LPTIM2_CH1OUT_CAPABLE - ---help--- - Enables channel 1 output. - -config STM32_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - depends on STM32_LPTIM2_CH1NOUT_CAPABLE - ---help--- - Enables channel 1 complementary output. - -config STM32_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32_ADC1_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32_ADC2_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32_ADC3_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -config STM32_DAC1_DMA - bool "DAC1 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -config STM32_DAC1_TIMER - int "DAC1 timer" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - range 2 8 - -config STM32_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - default 1 - -config STM32_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32_DAC2_DMA - bool "DAC2 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -config STM32_DAC2_TIMER - int "DAC2 timer" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 0 - range 2 8 - -config STM32_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 1 - -config STM32_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 - ---help--- - Route DAC2 output to ADC input instead of external pin. - -config STM32_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 - select STM32_DFSDM - -config STM32_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 - select STM32_DFSDM - -config STM32_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) - select STM32_DFSDM - -config STM32_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) - select STM32_DFSDM - -config STM32_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -config STM32_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_IPCC - bool "IPCC" - depends on ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 - select IPCC if ARCH_CHIP_STM32WL5 - ---help--- - IPCC - Inter Processor Communication Controller. A very simple - character device stream driver to exchange data between - CM0 and CM4. - -config STM32_IPCC_CHAN1_RX_SIZE - int "Channel 1 RX size" - default 256 - depends on STM32_IPCC - ---help--- - Size of the receive buffer. Another CPU will write to this buffer and - the currently running CPU will read from it. - -config STM32_IPCC_CHAN1_TX_SIZE - int "Channel 1 TX size" - default 256 - depends on STM32_IPCC - ---help--- - Size of the send buffer. Another CPU will read from this buffer and - the currently running CPU will write to it. - -config STM32_IPCC_CHAN2 - bool "Enable channel 2" - depends on STM32_IPCC - -if STM32_IPCC_CHAN2 - -config STM32_IPCC_CHAN2_RX_SIZE - int "Channel 2 RX size" - default 256 - -config STM32_IPCC_CHAN2_TX_SIZE - int "Channel 2 TX size" - default 256 - -config STM32_IPCC_CHAN3 - bool "Enable channel 3" - -if STM32_IPCC_CHAN3 - -config STM32_IPCC_CHAN3_RX_SIZE - int "Channel 3 RX size" - default 256 - -config STM32_IPCC_CHAN3_TX_SIZE - int "Channel 3 TX size" - default 256 - -config STM32_IPCC_CHAN4 - bool "Enable channel 4" - -if STM32_IPCC_CHAN4 - -config STM32_IPCC_CHAN4_RX_SIZE - int "Channel 4 RX size" - default 256 - -config STM32_IPCC_CHAN4_TX_SIZE - int "Channel 4 TX size" - default 256 - -config STM32_IPCC_CHAN5 - bool "Enable channel 5" - -if STM32_IPCC_CHAN5 - -config STM32_IPCC_CHAN5_RX_SIZE - int "Channel 5 RX size" - default 256 - -config STM32_IPCC_CHAN5_TX_SIZE - int "Channel 5 TX size" - default 256 - -config STM32_IPCC_CHAN6 - bool "Enable channel 6" - -if STM32_IPCC_CHAN6 - -config STM32_IPCC_CHAN6_RX_SIZE - int "Channel 6 RX size" - default 256 - -config STM32_IPCC_CHAN6_TX_SIZE - int "Channel 6 TX size" - default 256 - -endif # STM32_IPCC_CHAN2 -endif # STM32_IPCC_CHAN3 -endif # STM32_IPCC_CHAN4 -endif # STM32_IPCC_CHAN5 -endif # STM32_IPCC_CHAN6 +source "arch/arm/src/common/stm32/Kconfig.uart" +endmenu # U[S]ART Configuration + +menu "SPI/I2S Configuration" + depends on STM32_SPI || STM32_I2S +source "arch/arm/src/common/stm32/Kconfig.spi" +endmenu # SPI/I2S Configuration + +menu "System Configuration" +source "arch/arm/src/common/stm32/Kconfig.system" +endmenu # System Configuration + +menu "Timer Configuration" + depends on STM32_TIM || STM32_LPTIM +source "arch/arm/src/common/stm32/Kconfig.tim" +endmenu # Timer Configuration + +menu "HRTIM Configuration" + depends on STM32_HRTIM +source "arch/arm/src/common/stm32/Kconfig.hrtim" +endmenu # HRTIM Configuration + +menu "USB Configuration" + depends on STM32_USB || STM32_USBFS || STM32_OTGFS || STM32_OTGHS || STM32_OTGFSHS +source "arch/arm/src/common/stm32/Kconfig.usb" +endmenu # USB Configuration endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/common/stm32/Kconfig.adc b/arch/arm/src/common/stm32/Kconfig.adc new file mode 100644 index 00000000000..2c7040df2bb --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.adc @@ -0,0 +1,964 @@ +# +# STM32 ADC configuration options. +# + +# TODO: The options below are a special case for the legacy family-local +# stm32l4_adc.c driver (selected by STM32_HAVE_ADC_L4). They must be migrated +# to the common ADC interface used by stm32_adc_m3m4_v1v2.c (STM32_ADCx_EXTSEL / +# STM32_ADCx_JEXTSEL / STM32_ADCx_INJECTED_CHAN) and removed from here. + +config STM32_ADC1_HAVE_TIMER_FREQ + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC1_HAVE_TIMER + default y if (STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC1_HAVE_TIMER + +config STM32_ADC1_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC1_HAVE_TIMER + default y if (STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7) && STM32_ADC1_HAVE_TIMER + default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_ADC1_HAVE_TIMER + +config STM32_ADC2_HAVE_TIMER_FREQ + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC2_HAVE_TIMER + default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC2_HAVE_TIMER + +config STM32_ADC2_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC2_HAVE_TIMER + default y if (STM32_COMMON_F7_H7_H5) && STM32_ADC2_HAVE_TIMER + default y if STM32_COMMON_L5_U5 && STM32_ADC2_HAVE_TIMER + +config STM32_ADC3_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC3_HAVE_TIMER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC3_HAVE_TIMER + default y if STM32_COMMON_L5_U5 && STM32_ADC3_HAVE_TIMER + +config STM32_ADC1_HAVE_DMA + bool + +config STM32_ADC2_HAVE_DMA + bool + +config STM32_ADC3_HAVE_DMA + bool + +config STM32_ADC4_HAVE_DMA + bool + +config STM32_ADC5_HAVE_DMA + bool + +config STM32_ADC4_HAVE_TIMER + bool + +config STM32_ADC5_HAVE_TIMER + bool + +config STM32_ADC1_HAVE_OUTPUT_DFSDM + bool + +config STM32_ADC2_HAVE_OUTPUT_DFSDM + bool + +config STM32_ADC3_HAVE_OUTPUT_DFSDM + bool + +config STM32_ADC1_HAVE_TIMER + bool + +config STM32_ADC2_HAVE_TIMER + bool + +config STM32_ADC3_HAVE_TIMER + bool + +menu "STM32L4 ADC Configuration" + depends on STM32_HAVE_ADC_L4 && STM32_ADC + +config STM32_ADC_SMPR + int "ADC sample time" + default 0 + range 0 7 + ---help--- + ADC sample time + 0 - 2.5 ADC clock cycles + 1 - 6.5 ADC clock cycles + 2 - 12.5 ADC clock cycles + 3 - 24.5 ADC clock cycles + 4 - 47.5 ADC clock cycles + 5 - 92.5 ADC clock cycles + 6 - 247.5 ADC clock cycles + 7 - 640.5 ADC clock cycles + +config STM32_ADC1_INJ_CHAN + int "ADC1 configured injected channels" + depends on STM32_ADC1 + range 0 4 + default 0 + ---help--- + Number of configured ADC1 injected channels. + +config STM32_ADC2_INJ_CHAN + int "ADC2 configured injected channels" + depends on STM32_ADC2 + range 0 4 + default 0 + ---help--- + Number of configured ADC2 injected channels. + +config STM32_ADC3_INJ_CHAN + int "ADC3 configured injected channels" + depends on STM32_ADC3 + range 0 4 + default 0 + ---help--- + Number of configured ADC3 injected channels. + +menu "STM32L4 ADCx triggering Configuration" + +config STM32_ADC1_EXTTRIG + int "ADC1 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC1 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC1_EXTTRIG > 0 + +config STM32_ADC_L4_ADC1_EXTSEL + int "ADC1 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +config STM32_ADC2_EXTTRIG + int "ADC2 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC2 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC2_EXTTRIG > 0 + +config STM32_ADC_L4_ADC2_EXTSEL + int "ADC2 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +config STM32_ADC3_EXTTRIG + int "ADC3 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC3 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC3_EXTTRIG > 0 + +config STM32_ADC_L4_ADC3_EXTSEL + int "ADC3 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +if STM32_ADC1_INJ_CHAN > 0 + +config STM32_ADC1_JEXTTRIG + int "ADC1 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC1 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC1_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC1_JEXTSEL + int "ADC1 External Trigger Selection for injected group" + default 0 + range 0 15 + depends on STM32_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +if STM32_ADC2_INJ_CHAN > 0 + +config STM32_ADC2_JEXTTRIG + int "ADC2 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC2 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC2_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC2_JEXTSEL + int "ADC2 External Trigger Selection for injected group" + default 0 + range 0 5 + depends on STM32_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +if STM32_ADC3_INJ_CHAN > 0 + +config STM32_ADC3_JEXTTRIG + int "ADC3 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC3 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC3_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC3_JEXTSEL + int "ADC3 External Trigger Selection for injected group" + default 0 + range 0 5 + depends on STM32_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +endmenu #STM32L4 ADCx triggering Configuration + +endmenu + +menu "ADC Configuration" + depends on STM32_HAVE_ADC_H5 && STM32_ADC + +config STM32_ADC1_OVERSAMPLE + bool "Enable ADC1 hardware oversampling support" + depends on STM32_ADC1 + default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC1_OVERSAMPLE + +config STM32_ADC1_TROVS + bool "Enable triggered oversampling (CFGR2.TROVS)" + default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC1_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× + +config STM32_ADC1_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC1_OVERSAMPLE + +config STM32_ADC1_WDG1 + bool "Enable STM32H5 ADC1 Watchdog 1" + depends on STM32_ADC1 + default n + ---help--- + Enable STM32H5 ADC1 Watchdog 1. + +config STM32_ADC1_WDG1_FLT + int "Set ADC1 Watchdog 1 Filter" + depends on STM32_ADC1_WDG1 + default 0 + range 0 7 + ---help--- + N+1 watchdog events generates an interrupt. + Default: 0. + +config STM32_ADC1_WDG1_LOWTHRESH + int "Set ADC1 Watchdog 1 Low Threshold" + depends on STM32_ADC1_WDG1 + default 0 + range 0 4095 + ---help--- + Set the ADC1 Watchdog 1 low threshold value. + Default: 0. + +config STM32_ADC1_WDG1_HIGHTHRESH + int "Set ADC1 Watchdog 1 High Threshold" + depends on STM32_ADC1_WDG1 + default 4095 + range 0 4095 + ---help--- + Set the ADC1 Watchdog 1 high threshold value. + Default: 4095. + +config STM32_ADC1_WDG1_SGL + bool "Enable STM32H5 ADC1 Watchdog 1 on a single channel" + depends on STM32_ADC1_WDG1 + default n + ---help--- + This option determines if ADC1 Watchdog 1 is enabled on all + channels or just a single channel. + +config STM32_ADC1_WDG1_CHAN + int "STM32H5 ADC1 Watchdog 1 Channel Selection" + depends on STM32_ADC1_WDG1_SGL + default 0 + range 0 19 + ---help--- + Select the channel to enable for ADC1 Watchdog 1. + +config STM32_ADC2_OVERSAMPLE + bool "Enable ADC2 hardware oversampling support" + depends on STM32_ADC2 + default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC2_OVERSAMPLE + +config STM32_ADC2_TROVS + bool "Enable triggered oversampling (CFGR2.TROVS)" + default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC2_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× + +config STM32_ADC2_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC2_OVERSAMPLE + +config STM32_ADC2_WDG1 + bool "Enable STM32H5 ADC2 Watchdog 1" + depends on STM32_ADC2 + default n + ---help--- + Enable STM32H5 ADC2 Watchdog 1. + +config STM32_ADC2_WDG1_FLT + int "Set ADC2 Watchdog 1 Filter" + depends on STM32_ADC2_WDG1 + default 0 + range 0 7 + ---help--- + N+1 watchdog events generates an interrupt. + Default: 0. + +config STM32_ADC2_WDG1_LOWTHRESH + int "Set ADC2 Watchdog 1 Low Threshold" + depends on STM32_ADC2_WDG1 + default 0 + range 0 4095 + ---help--- + Set the ADC2 Watchdog 1 low threshold value. + Default: 0. + +config STM32_ADC2_WDG1_HIGHTHRESH + int "Set ADC2 Watchdog 1 High Threshold" + depends on STM32_ADC2_WDG1 + default 4095 + range 0 4095 + ---help--- + Set the ADC2 Watchdog 1 high threshold value. + Default: 4095. + +config STM32_ADC2_WDG1_SGL + bool "Enable STM32H5 ADC2 Watchdog 1 on a single channel" + depends on STM32_ADC2_WDG1 + default n + ---help--- + This option determines if ADC2 Watchdog 1 is enabled on all + channels or just a single channel. + +config STM32_ADC2_WDG1_CHAN + int "STM32H5 ADC2 Watchdog 1 Channel Selection" + depends on STM32_ADC2_WDG1_SGL + default 0 + range 0 19 + ---help--- + Select the channel to enable for ADC2 Watchdog 1. + +endmenu # ADC Configuration + +config STM32_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + depends on STM32_ADC1_HAVE_TIMER_FREQ + default 100 + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + depends on STM32_ADC1_HAVE_TIMTRIG + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + depends on STM32_ADC2_HAVE_TIMER_FREQ + default 100 + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + depends on STM32_ADC2_HAVE_TIMTRIG + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + depends on STM32_ADC3_HAVE_TIMTRIG + default 100 + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + depends on STM32_ADC3_HAVE_TIMTRIG && !ARCH_CHIP_STM32L4 + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC1_RESOLUTION + int "ADC1 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 + default 0 + range 0 3 + ---help--- + ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC2_RESOLUTION + int "ADC2 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 + default 0 + range 0 3 + ---help--- + ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC3_RESOLUTION + int "ADC3 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 + default 0 + range 0 3 + ---help--- + ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC_MAX_SAMPLES + int "The maximum number of channels that can be sampled" + depends on STM32_ADC + default 1 if STM32_HAVE_IP_ADC_M0_V1 && !STM32_ADC1_DMA + default 16 + ---help--- + The maximum number of samples which can be handled without + overrun depends on various factors. This is the user's + responsibility to correctly select this value. + Since the interface to update the sampling time is available + for all supported devices, the user can change the default + values in the board initialization logic and avoid ADC overrun. + +config STM32_ADC_NO_STARTUP_CONV + bool "Do not start conversion when opening ADC device" + depends on STM32_ADC + ---help--- + Do not start conversion when opening ADC device. + +config STM32_ADC_NOIRQ + bool "Do not use default ADC interrupts" + depends on STM32_ADC + ---help--- + Do not use default ADC interrupts handlers. + +config STM32_ADC_LL_OPS + bool "ADC low-level operations" + depends on STM32_ADC + ---help--- + Enable low-level ADC ops. + +config STM32_ADC_CHANGE_SAMPLETIME + bool "ADC sample time configuration" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS + ---help--- + Enable ADC sample time configuration (SMPRx registers). + +config STM32_ADC_OVERSAMPLE + bool "Enable ADC hardware oversampling support" + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC_OVERSAMPLE + +config STM32_ADC_TOVS + bool "Enable triggered oversampling (CFGR2.TOVS)" + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2x + 1 -> 4x + 2 -> 8x + ... + 7 -> 256x + +config STM32_ADC_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC_OVERSAMPLE + +config STM32_ADC1_DMA + bool "ADC1 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_ADC1_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC1_SCAN + bool "ADC1 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) + default STM32_ADC1_DMA + +config STM32_ADC1_DMA_CFG + int "ADC1 DMA configuration" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode + +config STM32_ADC1_DMA_BATCH + int "ADC1 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC1_ANIOC_TRIGGER + int "ADC1 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC2_DMA + bool "ADC2 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_ADC2_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC2_SCAN + bool "ADC2 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) + default STM32_ADC2_DMA + +config STM32_ADC2_DMA_CFG + int "ADC2 DMA configuration" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode + +config STM32_ADC2_DMA_BATCH + int "ADC2 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC2_ANIOC_TRIGGER + int "ADC2 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC3_DMA + bool "ADC3 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_ADC3_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC3_SCAN + bool "ADC3 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) + default STM32_ADC3_DMA + +config STM32_ADC3_DMA_CFG + int "ADC3 DMA configuration" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode + +config STM32_ADC3_DMA_BATCH + int "ADC3 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC3_ANIOC_TRIGGER + int "ADC3 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC1_INJECTED_CHAN + int "ADC1 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 0 + range 0 4 + ---help--- + Support for ADC1 injected channels. + +config STM32_ADC2_INJECTED_CHAN + int "ADC2 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 0 + range 0 4 + ---help--- + Support for ADC2 injected channels. + +config STM32_ADC3_INJECTED_CHAN + int "ADC3 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 0 + range 0 4 + ---help--- + Support for ADC3 injected channels. + +config STM32_ADC1_EXTSEL + bool "ADC1 external trigger for regular group" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_ADC1_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC1. + +config STM32_ADC2_EXTSEL + bool "ADC2 external trigger for regular group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_ADC2_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC2. + +config STM32_ADC3_EXTSEL + bool "ADC3 external trigger for regular group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_ADC3_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC3. + +config STM32_ADC1_JEXTSEL + bool "ADC1 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + ---help--- + Enable JEXTSEL for ADC1. + +config STM32_ADC2_JEXTSEL + bool "ADC2 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + ---help--- + Enable JEXTSEL for ADC2. + +config STM32_ADC3_JEXTSEL + bool "ADC3 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + ---help--- + Enable JEXTSEL for ADC3. + +config STM32_DAC1_OUTPUT_ADC + bool "DAC1 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + Route DAC1 output to ADC input instead of external pin. + +config STM32_DAC2_OUTPUT_ADC + bool "DAC2 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + Route DAC2 output to ADC input instead of external pin. + +config STM32_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32_ADC1_HAVE_OUTPUT_DFSDM && STM32_ADC1 && STM32_DFSDM1 + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32_ADC2_HAVE_OUTPUT_DFSDM && STM32_ADC2 && STM32_DFSDM1 + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32_ADC3_HAVE_OUTPUT_DFSDM && STM32_ADC3 && STM32_DFSDM1 + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +config STM32_ADC4_RESOLUTION + int "ADC4 resolution" + depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC5_RESOLUTION + int "ADC5 resolution" + depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC4_DMA + bool "ADC4 DMA" + depends on STM32_ADC4 && STM32_ADC4_HAVE_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC4_DMA_CFG + int "ADC4 DMA configuration" + depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode + +config STM32_ADC4_DMA_BATCH + int "ADC4 DMA number of conversions" + depends on STM32_ADC4 && STM32_ADC4_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC4_ANIOC_TRIGGER + int "ADC4 software trigger (ANIOC_TRIGGER) configuration" + depends on STM32_ADC4 + range 1 3 + default 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC5_DMA + bool "ADC5 DMA" + depends on STM32_ADC5 && STM32_ADC5_HAVE_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC5_DMA_CFG + int "ADC5 DMA configuration" + depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode + +config STM32_ADC5_DMA_BATCH + int "ADC5 DMA number of conversions" + depends on STM32_ADC5 && STM32_ADC5_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC4_INJECTED_CHAN + int "ADC4 injected channels" + depends on STM32_ADC4 + range 0 4 + default 0 + ---help--- + Support for ADC4 injected channels. + +config STM32_ADC5_INJECTED_CHAN + int "ADC5 injected channels" + depends on STM32_ADC5 + range 0 4 + default 0 + ---help--- + Support for ADC5 injected channels. + +config STM32_ADC4_EXTSEL + bool "ADC4 external trigger for regular group" + depends on STM32_ADC4 && !STM32_ADC4_HAVE_TIMER + default n + ---help--- + Enable EXTSEL for ADC4. + +config STM32_ADC5_EXTSEL + bool "ADC5 external trigger for regular group" + depends on STM32_ADC5 && !STM32_ADC5_HAVE_TIMER + default n + ---help--- + Enable EXTSEL for ADC5. + +config STM32_ADC4_JEXTSEL + bool "ADC4 external trigger for injected group" + depends on STM32_ADC4 + default n + ---help--- + Enable JEXTSEL for ADC4. + +config STM32_ADC5_JEXTSEL + bool "ADC5 external trigger for injected group" + depends on STM32_ADC5 + default n + ---help--- + Enable JEXTSEL for ADC5. + +config STM32_ADC1_CONTINUOUS + bool "Enable ADC1 Continuous Conversion Mode" + default n + depends on STM32_ADC1 && STM32_HAVE_IP_ADC_M0_V1 + ---help--- + If enabled, the ADC will operate in continuous conversion mode. + Otherwise, it will perform single conversions. + Note: Continuous and discontinuous mode cannot be defined at + the same time diff --git a/arch/arm/src/common/stm32/Kconfig.ble b/arch/arm/src/common/stm32/Kconfig.ble new file mode 100644 index 00000000000..dd91f1fe662 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ble @@ -0,0 +1,221 @@ +# +# STM32 common BLE options. +# + +if STM32_BLE + +config STM32_BLE_C2HOST + bool "Enable CPU2 HOST stack" + default n + ---help--- + The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and + control it using vendor ACL protocol. However, it is not expected to enable + this option in the current implementation. + +config STM32_BLE_MAX_CONN + int "Maximum BLE simultaneous connections" + range 1 8 + default 2 + +config STM32_BLE_GATT_MAX_ATTR_NUM + int "GATT attributes max count" + range 9 255 + default 64 + +config STM32_BLE_GATT_MAX_SVC_NUM + int "GATT services max count" + range 2 64 + default 8 + +config STM32_BLE_GATT_ATTR_BUF_SIZE + int "GATT attributes storage buf size" + default 1344 + ---help--- + Size of the storage area for attribute values. Hardcoded in CPU2 firmware. + +config STM32_BLE_DLE + bool "Support Data Length Extension (DLE)" + default y + +config STM32_BLE_MAX_ATT_MTU + int "Maximum supported attribute MTU" + range 23 512 + default 156 + +config STM32_BLE_SLAVE_SCA + int "Sleep clock accuracy in slave mode [PPM]" + default 500 + ---help--- + Sleep clock accuracy (ppm value) in slave mode. + +choice + prompt "Sleep clock accuracy in master mode" + default STM32_BLE_MASTER_SCA_0 + ---help--- + Sleep clock accuracy in master mode. + +config STM32_BLE_MASTER_SCA_0 + bool "251-500 ppm" + +config STM32_BLE_MASTER_SCA_1 + bool "151-250 ppm" + +config STM32_BLE_MASTER_SCA_2 + bool "101-150 ppm" + +config STM32_BLE_MASTER_SCA_3 + bool "76-100 ppm" + +config STM32_BLE_MASTER_SCA_4 + bool "51-75 ppm" + +config STM32_BLE_MASTER_SCA_5 + bool "31-50 ppm" + +config STM32_BLE_MASTER_SCA_6 + bool "21-30 ppm" + +config STM32_BLE_MASTER_SCA_7 + bool "0-20 ppm" + +endchoice # Sleep clock accuracy in master mode + +config STM32_BLE_MASTER_SCA + int + default 7 if STM32_BLE_MASTER_SCA_7 + default 6 if STM32_BLE_MASTER_SCA_6 + default 5 if STM32_BLE_MASTER_SCA_5 + default 4 if STM32_BLE_MASTER_SCA_4 + default 3 if STM32_BLE_MASTER_SCA_3 + default 2 if STM32_BLE_MASTER_SCA_2 + default 1 if STM32_BLE_MASTER_SCA_1 + default 0 + +choice + prompt "Low speed clock source" + default STM32_BLE_LS_CLK_SRC_LSE + ---help--- + Low speed 32 kHz clock source. + +config STM32_BLE_LS_CLK_SRC_LSE + bool "LSE" + +config STM32_BLE_LS_CLK_SRC_HSE + bool "HSE" + +endchoice # Low speed clock source + +config STM32_BLE_LS_CLK_SRC + int + default 1 if STM32_BLE_LS_CLKSRC_HSE + default 0 + +config STM32_BLE_MAX_CONN_EVT_LENGTH + hex "Max connection event length" + default 0xffffffff + ---help--- + Maximum duration of a slave connection event in units of 625/256us (~2.44us). + +config STM32_BLE_HSE_STARTUP + hex "HSE startup time" + default 0x148 + ---help--- + HSE startup time in units of 625/256us (~2.44us). + +config STM32_BLE_VITERBI + bool "Enable Viterbi algorithm" + default y + ---help--- + Enable Viterbi algorithm implementation + +config STM32_BLE_MAX_INITOR_COC_NUM + int "Max number of connection-oriented channels" + range 0 64 + default 32 + ---help--- + Maximum number of connection-oriented channels in initiator mode. + +config STM32_BLE_SVC_CHANGED_CHAR + bool "Enable service changed characteristic" + default n + +config STM32_BLE_WRITABLE_DEVICE_NAME + bool "Writable device name" + default y + +config STM32_BLE_CHAN_SEL_ALG2 + bool "Enable channel selection algorithm 2" + default n + +choice + prompt "Power class" + default STM32_BLE_POWER_CLASS_2_3 + +config STM32_BLE_POWER_CLASS_2_3 + bool "Power Class 2-3" + +config STM32_BLE_POWER_CLASS_1 + bool "Power Class 1" + +endchoice # Power class + +config STM32_BLE_MIN_TX_POWER + int "Minimum transmit power [dBm]" + range -127 20 + default 0 + +config STM32_BLE_MAX_TX_POWER + int "Maximum transmit power [dBm]" + range -127 20 + default 0 + +choice + prompt "AGC RSSI model" + default STM32_BLE_AGC_RSSI_LEGACY + +config STM32_BLE_AGC_RSSI_LEGACY + bool "AGC RSSI Legacy" + +config STM32_BLE_AGC_RSSI_IMPROVED + bool "AGC RSSI Improved" + +endchoice # AGC RSSI model + +config STM32_BLE_ADVERTISING + bool "Support advertising" + default y + +config STM32_BLE_SCANNING + bool "Support scanning" + default y + +config STM32_BLE_LE_2M_PHY + bool "Support LE 2M PHY" + default y + +config STM32_BLE_LE_CODED_PHY + bool "Support LE Coded PHY" + default STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55 + depends on STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55 + +config STM32_BLE_FICR_STATIC_ADDR + bool "Configure factory generated static random address" + default n + +config STM32_BLE_PUB_ADDR + hex "Configure BT public address" + default 0x0000000000 + +endif # STM32_BLE + +if STM32_MBOX + +config STM32_MBOX_TX_CMD_QUEUE_LEN + int "Mailbox TX command queue length" + default 2 + +config STM32_MBOX_RX_EVT_QUEUE_LEN + int "Mailbox RX event queue length" + default 5 + +endif # STM32_MBOX diff --git a/arch/arm/src/common/stm32/Kconfig.cache b/arch/arm/src/common/stm32/Kconfig.cache new file mode 100644 index 00000000000..ba13237abd0 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.cache @@ -0,0 +1,238 @@ +# +# STM32 cache configuration options. +# + +menu "ICACHE Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_MONITOR_EN + bool "Enable ICACHE Hit/Miss Counters" + default n + +config STM32_ICACHE_DIRECT + bool "Enable 1-Way Direct Mapped Cache (N-Way = default)" + default n + +menu "ICACHE Interrupt Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_INV_INT + bool "Enable interrupts on full invalidation completion." + default n + +config STM32_ICACHE_ERR_INT + bool "Enable interrupts on occurrences of cache errors." + default n + +endmenu # ICACHE Interrupt Configuration + +menu "ICACHE Region Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_REGION0 + bool "Enable Configuration of ICACHE Region 0" + default n + +config STM32_ICACHE_REGION1 + bool "Enable Configuration of ICACHE Region 1" + default n + +config STM32_ICACHE_REGION2 + bool "Enable Configuration of ICACHE Region 2" + default n + +config STM32_ICACHE_REGION3 + bool "Enable Configuration of ICACHE Region 3" + default n + +menu "Region 0 Configuration" + depends on STM32_ICACHE_REGION0 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION0_BADDR + hex "ICACHE Region 0 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION0 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 0. + +config STM32_ICACHE_REGION0_RSIZE + int "ICACHE Region 0 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION0 + ---help--- + Set the size of Region 0. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION0_REMAPADDR + hex "ICACHE Region 0 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION0 + ---help--- + Set bits [31:21] of ICACHE Region 0 Remap Address.. + +config STM32_ICACHE_REGION0_MSTSEL + int "ICACHE Region 0 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION0 + ---help--- + Select ICACHE Region 0 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION0_HBURST + int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION0 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 0 Configuration + +menu "Region 1 Configuration" + depends on STM32_ICACHE_REGION1 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION1_BADDR + hex "ICACHE Region 1 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION1 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 1. + +config STM32_ICACHE_REGION1_RSIZE + int "ICACHE Region 1 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION1 + ---help--- + Set the size of Region 1. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION1_REMAPADDR + hex "ICACHE Region 1 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION1 + ---help--- + Set bits [31:21] of ICACHE Region 1 Remap Address.. + +config STM32_ICACHE_REGION1_MSTSEL + int "ICACHE Region 1 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION1 + ---help--- + Select ICACHE Region 1 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION1_HBURST + int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION1 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 1 Configuration + +menu "Region 2 Configuration" + depends on STM32_ICACHE_REGION2 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION2_BADDR + hex "ICACHE Region 2 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION2 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 2. + +config STM32_ICACHE_REGION2_RSIZE + int "ICACHE Region 2 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION2 + ---help--- + Set the size of Region 2. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION2_REMAPADDR + hex "ICACHE Region 2 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION2 + ---help--- + Set bits [31:21] of ICACHE Region 2 Remap Address.. + +config STM32_ICACHE_REGION2_MSTSEL + int "ICACHE Region 2 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION2 + ---help--- + Select ICACHE Region 2 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION2_HBURST + int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION2 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 2 Configuration + +menu "Region 3 Configuration" + depends on STM32_ICACHE_REGION3 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION3_BADDR + hex "ICACHE Region 3 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION3 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 3. + +config STM32_ICACHE_REGION3_RSIZE + int "ICACHE Region 3 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION3 + ---help--- + Set the size of Region 3. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION3_REMAPADDR + hex "ICACHE Region 3 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION3 + ---help--- + Set bits [31:21] of ICACHE Region 3 Remap Address.. + +config STM32_ICACHE_REGION3_MSTSEL + int "ICACHE Region 3 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION3 + ---help--- + Select ICACHE Region 3 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION3_HBURST + int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION3 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 3 Configuration + +endmenu # ICACHE Region Configuration + +endmenu # ICACHE Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.can b/arch/arm/src/common/stm32/Kconfig.can new file mode 100644 index 00000000000..2bb08577c80 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.can @@ -0,0 +1,58 @@ +# +# STM32 CAN configuration options. +# + +choice + prompt "CAN character driver or SocketCAN support" + default STM32_CAN_CHARDRIVER + +config STM32_CAN_CHARDRIVER + bool "STM32 CAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_CAN_SOCKET + bool "STM32 CAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + +endchoice # CAN character driver or SocketCAN support + +config STM32_CAN1_BAUD + int "CAN1 BAUD" + depends on STM32_CAN1 + default 250000 + ---help--- + CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + +config STM32_CAN2_BAUD + int "CAN2 BAUD" + depends on STM32_CAN2 + default 250000 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + +config STM32_CAN3_BAUD + int "CAN3 BAUD" + depends on STM32_CAN3 + default 250000 + ---help--- + CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. + +config STM32_CAN_TSEG1 + int "TSEG1 quanta" + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config STM32_CAN_TSEG2 + int "TSEG2 quanta" + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config STM32_CAN_REGDEBUG + bool "CAN Register level debug" + depends on DEBUG_CAN_INFO + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. diff --git a/arch/arm/src/common/stm32/Kconfig.comp b/arch/arm/src/common/stm32/Kconfig.comp new file mode 100644 index 00000000000..57c4c8a5d1a --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.comp @@ -0,0 +1,387 @@ +# +# STM32 analog comparator (COMP) configuration options. +# + +# COMP supported only for M3M4 for now + +if STM32_HAVE_IP_COMP_M3M4_V2 + +if STM32_COMP1 + +config STM32_COMP1_OUT + bool "COMP1 GPIO Output" + default n + ---help--- + Enables COMP1 output. + +config STM32_COMP1_INM + int "COMP1 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP1 inverting input pin. + +config STM32_COMP1_INP + int "COMP1 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP1 non-inverting input pin. + +config STM32_COMP1_POL + int "COMP1 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP1 output polarity. + +config STM32_COMP1_HYST + int "COMP1 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP1. + +config STM32_COMP1_BLANKSEL + int "COMP1 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP1. + +config STM32_COMP1_LOCK + int "COMP1 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP1 + +if STM32_COMP2 + +config STM32_COMP2_OUT + bool "COMP2 GPIO Output" + default n + ---help--- + Enables COMP2 output. + +config STM32_COMP2_INM + int "COMP2 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP2 inverting input pin. + +config STM32_COMP2_INP + int "COMP2 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP2 non-inverting input pin. + +config STM32_COMP2_POL + int "COMP2 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP2 output polarity. + +config STM32_COMP2_HYST + int "COMP2 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP2. + +config STM32_COMP2_BLANKSEL + int "COMP2 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP2. + +config STM32_COMP2_LOCK + int "COMP2 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP2 + +if STM32_COMP3 + +config STM32_COMP3_OUT + bool "COMP3 GPIO Output" + default n + ---help--- + Enables COMP3 output. + +config STM32_COMP3_INM + int "COMP3 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP3 inverting input pin. + +config STM32_COMP3_INP + int "COMP3 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP3 non-inverting input pin. + +config STM32_COMP3_POL + int "COMP3 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP3 output polarity. + +config STM32_COMP3_HYST + int "COMP3 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP3. + +config STM32_COMP3_BLANKSEL + int "COMP3 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP3. + +config STM32_COMP3_LOCK + int "COMP3 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP3 + +if STM32_COMP4 + +config STM32_COMP4_OUT + bool "COMP4 GPIO Output" + default n + ---help--- + Enables COMP4 output. + +config STM32_COMP4_INM + int "COMP4 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP4 inverting input pin. + +config STM32_COMP4_INP + int "COMP4 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP4 non-inverting input pin. + +config STM32_COMP4_POL + int "COMP4 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP4 output polarity. + +config STM32_COMP4_HYST + int "COMP4 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP4. + +config STM32_COMP4_BLANKSEL + int "COMP4 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP4. + +config STM32_COMP4_LOCK + int "COMP4 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP4 + +if STM32_COMP5 + +config STM32_COMP5_OUT + bool "COMP5 GPIO Output" + default n + ---help--- + Enables COMP5 output. + +config STM32_COMP5_INM + int "COMP5 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP5 inverting input pin. + +config STM32_COMP5_INP + int "COMP5 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP5 non-inverting input pin. + +config STM32_COMP5_POL + int "COMP5 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP5 output polarity. + +config STM32_COMP5_HYST + int "COMP5 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP5. + +config STM32_COMP5_BLANKSEL + int "COMP5 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP5. + +config STM32_COMP5_LOCK + int "COMP5 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP5 + +if STM32_COMP6 + +config STM32_COMP6_OUT + bool "COMP6 GPIO Output" + default n + ---help--- + Enables COMP6 output. + +config STM32_COMP6_INM + int "COMP6 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP6 inverting input pin. + +config STM32_COMP6_INP + int "COMP6 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP6 non-inverting input pin. + +config STM32_COMP6_POL + int "COMP6 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP6 output polarity. + +config STM32_COMP6_HYST + int "COMP6 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP6. + +config STM32_COMP6_BLANKSEL + int "COMP6 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP6. + +config STM32_COMP6_LOCK + int "COMP6 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP6 + +if STM32_COMP7 + +config STM32_COMP7_OUT + bool "COMP7 GPIO Output" + default n + ---help--- + Enables COMP7 output. + +config STM32_COMP7_INM + int "COMP7 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP7 inverting input pin. + +config STM32_COMP7_INP + int "COMP7 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP7 non-inverting input pin. + +config STM32_COMP7_POL + int "COMP7 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP7 output polarity. + +config STM32_COMP7_HYST + int "COMP7 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP7. + +config STM32_COMP7_BLANKSEL + int "COMP7 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP7. + +config STM32_COMP7_LOCK + int "COMP7 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP7 + +endif # STM32_HAVE_IP_COMP_M3M4_V2 diff --git a/arch/arm/src/common/stm32/Kconfig.dac b/arch/arm/src/common/stm32/Kconfig.dac new file mode 100644 index 00000000000..92a88c2e601 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dac @@ -0,0 +1,363 @@ +# +# STM32 DAC configuration options. +# + +config STM32_DAC_LL_OPS + bool "DAC low-level operations" + default n + ---help--- + Enable low-level DAC ops. + +config STM32_DAC1_DMA + bool "DAC1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC1_TIMER + int "DAC1 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA + range 2 8 + +config STM32_DAC1_TIMER_FREQUENCY + int "DAC1 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA + default 100 + ---help--- + DAC1 output frequency. Default: 100Hz + +config STM32_DAC1_DMA_BUFFER_SIZE + int "DAC1 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA + default 1 + +config STM32_DAC2_DMA + bool "DAC2 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC2_TIMER + int "DAC2 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA + default 0 + range 2 8 + +config STM32_DAC2_TIMER_FREQUENCY + int "DAC2 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA + default 100 + ---help--- + DAC2 output frequency. Default: 100Hz + +config STM32_DAC2_DMA_BUFFER_SIZE + int "DAC2 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA + default 1 + +menu "DAC Configuration" + depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 + +config STM32_DAC1CH1_MODE + int "DAC1CH1 channel mode" + depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC1CH1_DMA + bool "DAC1CH1 DMA" + depends on STM32_DAC1CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC1CH1_DMA + +config STM32_DAC1CH1_DMA_BUFFER_SIZE + int "DAC1CH1 DMA buffer size" + default 256 + +config STM32_DAC1CH1_DMA_EXTERNAL + bool "DAC1CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC1CH1_HRTIM_TRG1 + bool "DAC1CH1 HRTIM Trigger 1" + default n + +config STM32_DAC1CH1_HRTIM_TRG2 + bool "DAC1CH1 HRTIM Trigger 2" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC1CH1_TIMER + int "DAC1CH1 timer" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + range 2 8 + +config STM32_DAC1CH1_TIMER_FREQUENCY + int "DAC1CH1 timer frequency" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC1CH2_MODE + int "DAC1CH2 channel mode" + depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC1CH2_DMA + bool "DAC1CH2 DMA" + depends on STM32_DAC1CH2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC1CH2_DMA + +config STM32_DAC1CH2_DMA_BUFFER_SIZE + int "DAC1CH2 DMA buffer size" + default 256 + +config STM32_DAC1CH2_DMA_EXTERNAL + bool "DAC1CH2 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC1CH2_HRTIM_TRG1 + bool "DAC1CH2 HRTIM Trigger 1" + default n + +config STM32_DAC1CH2_HRTIM_TRG2 + bool "DAC1CH2 HRTIM Trigger 2" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC1CH2_TIMER + int "DAC1CH2 timer" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + range 2 8 + +config STM32_DAC1CH2_TIMER_FREQUENCY + int "DAC1CH2 timer frequency" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC2CH1_MODE + int "DAC2CH1 channel mode" + depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC2CH1_DMA + bool "DAC2CH1 DMA" + depends on STM32_DAC2CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC2CH1_DMA + +config STM32_DAC2CH1_DMA_BUFFER_SIZE + int "DAC2CH1 DMA buffer size" + default 256 + +config STM32_DAC2CH1_DMA_EXTERNAL + bool "DAC2CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC2CH1_HRTIM_TRG3 + bool "DAC2CH1 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC2CH1_TIMER + int "DAC2CH1 timer" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC2CH1_TIMER_FREQUENCY + int "DAC2CH1 timer frequency" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC3CH1_MODE + int "DAC3CH1 channel mode" + depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC3CH1_DMA + bool "DAC3CH1 DMA" + depends on STM32_DAC3CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC3CH1_DMA + +config STM32_DAC3CH1_DMA_BUFFER_SIZE + int "DAC3CH1 DMA buffer size" + default 256 + +config STM32_DAC3CH1_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC3CH1_HRTIM_TRG3 + bool "DAC3CH1 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC3CH1_TIMER + int "DAC3CH1 timer" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC3CH1_TIMER_FREQUENCY + int "DAC3CH1 timer frequency" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC3CH2_MODE + int "DAC3CH2 channel mode" + depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC3CH2_DMA + bool "DAC3CH2 DMA" + depends on STM32_DAC3CH2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC3CH2_DMA + +config STM32_DAC3CH2_DMA_BUFFER_SIZE + int "DAC3CH2 DMA buffer size" + default 256 + +config STM32_DAC3CH2_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC3CH2_HRTIM_TRG3 + bool "DAC3CH2 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC3CH2_TIMER + int "DAC3CH2 timer" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC3CH2_TIMER_FREQUENCY + int "DAC3CH2 timer frequency" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + +endif + +endmenu diff --git a/arch/arm/src/common/stm32/Kconfig.dfsdm b/arch/arm/src/common/stm32/Kconfig.dfsdm new file mode 100644 index 00000000000..49b02ad721d --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dfsdm @@ -0,0 +1,46 @@ +# +# STM32 digital filter configuration options. +# + +config STM32_ADC1_DFSDM_L4_CHIP + bool + default y if STM32_STM32L496XX || STM32_STM32L4XR + select STM32_ADC1_HAVE_OUTPUT_DFSDM + +config STM32_ADC1_DFSDM_L5_CHIP + bool + default y if STM32_STM32L596XX || STM32_STM32L5XR + select STM32_ADC1_HAVE_OUTPUT_DFSDM + +config STM32_ADC1_DFSDM_U5_CHIP + bool + default y if STM32_STM32U596XX || STM32_STM32U5XR + select STM32_ADC1_HAVE_OUTPUT_DFSDM + +config STM32_DFSDM1_FLT0 + bool "DFSDM1 Filter 0" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT1 + bool "DFSDM1 Filter 1" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT2 + bool "DFSDM1 Filter 2" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_FLT3 + bool "DFSDM1 Filter 3" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_DMA + bool "DFSDM1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM + ---help--- + If DMA is selected, then the DFSDM may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. diff --git a/arch/arm/src/common/stm32/Kconfig.dma b/arch/arm/src/common/stm32/Kconfig.dma new file mode 100644 index 00000000000..dcf96574021 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dma @@ -0,0 +1,118 @@ +# +# STM32 DMA configuration options. +# + +config STM32_DMA1_HAVE_CHAN8 + bool + default y if STM32_STM32G47XX + +config STM32_DMA2_HAVE_CHAN678 + bool + default y if STM32_STM32G47XX + +config STM32_DMACAPABLE + bool "Workaround non-DMA capable memory" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA + default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA + ---help--- + This option enables the DMA interface stm32_dmacapable that can be + used to check if it is possible to do DMA from the selected address. + Drivers then may use this information to determine if they should + attempt the DMA or fall back to a different transfer method. + +if STM32_DMA2D + +config STM32_DMA2D_NLAYERS + int "Number DMA2D overlays" + default 1 + range 1 256 + ---help--- + Number of supported DMA2D layer. + +config STM32_DMA2D_LAYER_SHARED + bool "Overlays shared memory region" + ---help--- + Several overlays can share the same memory region. + Setup a whole memory area (usually multiple size of the visible screen) + allows image preprocessing before they become visible by blit operation. + +config STM32_DMA2D_LAYER_PPLINE + int "Pixel per line" + default 1 + range 1 65535 + ---help--- + If you are using the DMA2D, then you must provide the pixel per line or + width of the overlay. + +config STM32_DMA2D_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the DMA2D, then you must provide the address + of the start of the DMA2D overlays framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_DMA2D_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of all DMA2D overlays. + +config STM32_DMA2D_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 + default y + +config STM32_DMA2D_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 + default y + +config STM32_DMA2D_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 + default y + +config STM32_DMA2D_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + default y + +config STM32_DMA2D_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + default y + +config STM32_DMA2D_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB15555 + default y + +config STM32_DMA2D_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + default y + +config STM32_DMA2D_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + default y + +config STM32_DMA2D_REGDEBUG + bool "DMA2D Register level debug" + depends on DEBUG_INFO && DEBUG_LCD + ---help--- + Output detailed register-level DMA2D device debug information. + +endif # STM32_DMA2D + +config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED + bool "Do not disqualify DMA capability based on cache alignment" + depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH + ---help--- + This option configures the stm32_dmacapable to not disqualify + DMA operations on memory that is not dcache aligned based solely + on the starting address and byte count. + + Use this when ALL buffer extents are known to be aligned, but the + the count does not use the complete buffer. diff --git a/arch/arm/src/common/stm32/Kconfig.dts b/arch/arm/src/common/stm32/Kconfig.dts new file mode 100644 index 00000000000..eef17dd24d8 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dts @@ -0,0 +1,99 @@ +# +# STM32 Digital Temperature Sensor (DTS) configuration options. +# + +config STM32_DTS_REFCLK_LSE + bool "Use LSE (32.768 kHz crystal) as DTS reference clock" + default n + ---help--- + Select the low-speed external (LSE) oscillator as the reference clock + for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will + measure FM(T) pulses over N LSE cycles. + + If disabled, the DTS will use the APB-bus clock (PCLK) as the reference + (REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the + calibration prescaler ≤ 1 MHz. + +config STM32_DTS_SMP_TIME + int "DTS sampling time (TS1_SMP_TIME[3:0])" + default 1 + range 1 15 + ---help--- + Number of reference-clock cycles (PCLK or LSE) counted per + DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles). + +config STM32_DTS_TRIGGER + int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])" + default 0 + ---help--- + If non-zero, DTS will start measurements on the rising edge of + the selected hardware line. Values match RM0481 Table 275: + 0=Software Trigger, 1=LPTIM1_CH1, + 2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved. + +config STM32_DTS_LOW_THRESHOLD + int "DTS low-threshold (°C)" + default 0 + ---help--- + The temperature (in whole °C) below which the DTS window comparator will + assert the low-threshold flag (TS1_ITLF). To disable, set equal to 0. + +config STM32_DTS_HIGH_THRESHOLD + int "DTS high-threshold (°C)" + default 100 + ---help--- + The temperature (in whole °C) above which the DTS window comparator will + assert the high-threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD. + +config STM32_DTS_ITEN_ITEF + bool "Enable DTS end-of-measurement interrupt (TS1_ITEF)" + default y + ---help--- + Enable the synchronous “end of measurement” interrupt for the + digital temperature sensor. When set, the driver will attach + and unmask TS1_ITEF and will call your ISR on every fresh sample. + +config STM32_DTS_ITEN_ITLF + bool "Enable DTS low-threshold interrupt (TS1_ITLF)" + default n + ---help--- + Enable the synchronous “low threshold crossed” interrupt for the + digital temperature sensor. When set, the driver will unmask + TS1_ITLF so you can get notified whenever the measured value + drops below your programmed low-threshold. + +config STM32_DTS_ITEN_ITHF + bool "Enable DTS high-threshold interrupt (TS1_ITHF)" + default n + ---help--- + Enable the synchronous “high threshold crossed” interrupt for the + digital temperature sensor. When set, the driver will unmask + TS1_ITHF so you can get notified whenever the measured value + exceeds your programmed high-threshold. + +config STM32_DTS_AITEN_AITEF + bool "Enable DTS asynchronous end-of-measurement interrupt (TS1_AITEF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous end-of-measurement interrupt. This will + set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup + event when a conversion completes (in Stop/Sleep modes). + +config STM32_DTS_AITEN_AITLF + bool "Enable DTS asynchronous low-threshold interrupt (TS1_AITLF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous low-threshold comparator interrupt. This + will set TS1_AITLEN in DTS_ITENR and generate a wakeup event + when the measurement drops below your low threshold. + +config STM32_DTS_AITEN_AITHF + bool "Enable DTS asynchronous high-threshold interrupt (TS1_AITHF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous high-threshold comparator interrupt. This + will set TS1_AITHEN in DTS_ITENR and generate a wakeup event + when the measurement exceeds your high threshold. diff --git a/arch/arm/src/common/stm32/Kconfig.eth b/arch/arm/src/common/stm32/Kconfig.eth new file mode 100644 index 00000000000..e90f665e08d --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.eth @@ -0,0 +1,290 @@ +# +# STM32 common ETH options. +# + +config STM32_PHY_HAVE_POLLED + bool + +if STM32_ETHMAC + +config STM32_PHYADDR + int "PHY address" + default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default 0 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config STM32_PHYINIT + bool "Board-specific PHY Initialization" + ---help--- + Some boards require specialized initialization of the PHY before it can be used. + This may include such things as configuring GPIOs, resetting the PHY, etc. If + STM32_PHYINIT is defined in the configuration then the board specific logic must + provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function + one time before it first uses the PHY. + +config STM32_MII + bool "Use MII interface" + ---help--- + Support Ethernet MII interface. + +config STM32_AUTONEG + bool "Use autonegotiation" + default y + ---help--- + Use PHY autonegotiation to determine speed and mode + +if !STM32_AUTONEG + +config STM32_ETHFD + bool "Full duplex" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select full duplex + mode. Default: half-duplex + +config STM32_ETH100MBPS + bool "100 Mbps" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps + speed. Default: 10 Mbps + +endif # !STM32_AUTONEG + +if STM32_AUTONEG + +config STM32_PHYSR + int "PHY Status Register Address (decimal)" + ---help--- + This must be provided if STM32_AUTONEG is defined. The PHY status register + address may diff from PHY to PHY. This configuration sets the address of + the PHY status register. + +config STM32_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +if !STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_SPEED + hex "PHY Speed Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides bit mask + for isolating the 10 or 100MBps speed indication. + +config STM32_PHYSR_100MBPS + hex "PHY 100Mbps Speed Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the value + of the speed bit(s) indicating 100MBps speed. + +config STM32_PHYSR_MODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the full or half duplex mode bits. + +config STM32_PHYSR_FULLDUPLEX + hex "PHY Full Duplex Mode Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the + value of the mode bits indicating full duplex mode. + +endif # !STM32_PHYSR_ALTCONFIG + +if STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_ALTMODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config STM32_PHYSR_10HD + hex "10MBase-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config STM32_PHYSR_100HD + hex "100Base-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config STM32_PHYSR_10FD + hex "10Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config STM32_PHYSR_100FD + hex "100Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + +endif # STM32_PHYSR_ALTCONFIG + +endif # STM32_AUTONEG + +config STM32_ETH_PTP + bool "Precision Time Protocol (PTP)" + ---help--- + Enables Precision Time Protocol (PTP) hardware timer. + +config STM32_ETH_ENHANCEDDESC + bool "Enable enhanced RX/TX descriptors" + depends on STM32_COMMON_LEGACY + default n + ---help--- + Enables double-length DMA descriptors that have space for packet + timestamps and checksum offloading. + +config STM32_ETH_PTP_GPIO + bool "PTP pulse-per-second output signal" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Enables pulse-per-second output on GPIO pin. + +config STM32_ETH_PTP_RTC_HIRES + bool "Use PTP timer as system high-resolution RTC" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. + This provides high resolution timestamps to clock_gettime(). + Note that PTP timer is disabled when Ethernet interface is down or + being reset. During this time g_rtc_enabled is set to false and system + uses the lower resolution system tick counter. + +config STM32_ETH_TIMESTAMP_RX + bool "Hardware timestamping of received packets" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC + select ARCH_HAVE_NETDEV_TIMESTAMP + default n + ---help--- + Timestamp all received Ethernet packets. + Timestamp is available to application through SO_TIMESTAMP socket option. + +config STM32_RMII + bool + default !STM32_MII + +config STM32_ETHMAC_REGDEBUG + bool "Register-Level Debug" + depends on DEBUG_NET_INFO + ---help--- + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + +endif # STM32_ETHMAC + +choice + prompt "MII clock configuration" + depends on STM32_MII + default STM32_MII_MCO if STM32_STM32F10XX + default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_MII_EXTCLK + +config STM32_MII_MCO + bool "Use MC0 as MII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the MII interface. Default: Use MC0 + +config STM32_MII_MCO1 + bool "Use MC01 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO1 to clock the MII interface. Default: Use MC01 + +config STM32_MII_MCO2 + bool "Use MC02 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO2 to clock the MII interface. Default: Use MC01 + +config STM32_MII_EXTCLK + bool "External MII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for MII + clock. Default: Use MC0[1] + +endchoice + +choice + prompt "RMII clock configuration" + depends on STM32_RMII + default STM32_RMII_MCO if STM32_STM32F10XX + default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_RMII_EXTCLK + +config STM32_RMII_MCO + bool "Use MC0 as RMII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the RMII interface. Default: Use MC0 + +config STM32_RMII_MCO1 + bool "Use MC01 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO1 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_MCO2 + bool "Use MC02 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO2 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_EXTCLK + bool "External RMII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for RMII + clock. Default: Use MC0[1] + +endchoice + +config STM32_PHY_POLLING + bool "Support network monitoring by polling the PHY" + depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_PHY_HAVE_POLLED + select ARCH_PHY_POLLED + ---help--- + Some boards may not have an interrupt connected to the PHY. + This option allows the network monitor to be used by polling the + the PHY for status. + +config STM32_ETH_HWCHECKSUM + bool "Enable ethernet hardware checksum" + depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC + ---help--- + Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload + engine in the Ethernet MAC. + When enabled, hardware generates checksums for TX and checks RX frames. + Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, + NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid + redundant verification in the network stack. + +config STM32_NO_PHY + bool "MAC has no PHY" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + +config STM32_ETH_NRXDESC + int "Number of RX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 8 + ---help--- + Number of RX DMA descriptors to use. + +config STM32_ETH_NTXDESC + int "Number of TX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 4 + ---help--- + Number of TX DMA descriptors to use. diff --git a/arch/arm/src/common/stm32/Kconfig.fdcan b/arch/arm/src/common/stm32/Kconfig.fdcan new file mode 100644 index 00000000000..7910ef3b354 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.fdcan @@ -0,0 +1,518 @@ +# +# STM32 FDCAN configuration options. +# + +menu "FDCAN Driver Configuration" + depends on STM32_HAVE_FDCAN_H7 && (STM32_FDCAN1 || STM32_FDCAN2 || STM32_FDCAN3) + +menu "FDCAN1 Configuration" + depends on STM32_FDCAN1 + +config FDCAN1_BITRATE + int "FDCAN1 CAN bitrate" + depends on !NET_CAN_CANFD + default 100000 + +config FDCAN1_ARBI_BITRATE + int "FDCAN1 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 100000 + +config FDCAN1_DATA_BITRATE + int "FDCAN1 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN1 + +menu "FDCAN2 Configuration" + depends on STM32_FDCAN2 + +config FDCAN2_BITRATE + int "FDCAN2 CAN bitrate" + depends on !NET_CAN_CANFD + default 100000 + +config FDCAN2_ARBI_BITRATE + int "FDCAN2 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 100000 + +config FDCAN2_DATA_BITRATE + int "FDCAN2 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN2 + +menu "FDCAN3 Configuration" + depends on STM32_FDCAN3 + +config FDCAN3_BITRATE + int "FDCAN3 CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FDCAN3_ARBI_BITRATE + int "FDCAN3 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FDCAN3_DATA_BITRATE + int "FDCAN3 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN3 + +endmenu # FDCAN Driver + +choice + prompt "FDCAN character driver or SocketCAN support" + depends on STM32_FDCAN + default STM32_FDCAN_CHARDRIVER + +config STM32_FDCAN_CHARDRIVER + bool "STM32 FDCAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_FDCAN_SOCKET + bool "STM32 FDCAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + select NET_CAN_HAVE_CANFD + +endchoice # FDCAN character driver or SocketCAN support + +if STM32_FDCAN1 + +choice + prompt "FDCAN1 frame format" + default STM32_FDCAN1_ISO11898_1 + +config STM32_FDCAN1_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN1_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN1 frame format + +choice + prompt "FDCAN1 mode" + default STM32_FDCAN1_CLASSIC + +config STM32_FDCAN1_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN1_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN1_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN1 mode + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +choice + prompt "FDCAN2 frame format" + default STM32_FDCAN2_ISO11898_1 + +config STM32_FDCAN2_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN2_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN2 frame format + +choice + prompt "FDCAN2 mode" + default STM32_FDCAN2_CLASSIC + +config STM32_FDCAN2_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN2_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN2_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN2 mode + +endif # STM32_FDCAN2 + +config STM32_FDCAN_REGDEBUG + bool "FDCAN register-level debug" + depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_QUEUE_MODE + bool "FDCAN QUEUE mode (vs FIFO mode)" + depends on STM32_FDCAN + +config STM32_FDCAN_LOOPBACK + bool "Enable FDCAN loopback mode" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default n + ---help--- + Enable the FDCAN local loopback mode for testing purposes. + Requires a further choice of internal or external loopback mode. + +choice + prompt "FDCAN Loopback Mode" + depends on STM32_FDCAN_LOOPBACK + default STM32_FDCAN_LOOPBACK_INTERNAL + +config STM32_FDCAN_LOOPBACK_INTERNAL + bool "Internal loopback mode" + ---help--- + Enable internal loopback mode, where both Tx and Rx are + disconnected from the CAN bus. This can be used for a "Hot Selftest", + meaning the FDCAN can be used without affecting a running CAN bus. + + All transmitted frames are treated as received frames and processed + accordingly. + +config STM32_FDCAN_LOOPBACK_EXTERNAL + bool "External loopback mode" + ---help--- + Enable external loopback mode, where the Rx pin is disconnected from + the CAN bus but the Tx pin remains connected. + + All transmitted frames are treated as received frames and processed + accordingly. + +endchoice # FDCAN Loopback Mode + +choice + prompt "FDCAN WorkQueue Selection" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default STM32_FDCAN_LPWORK + +config STM32_FDCAN_LPWORK + bool "Use LP work queue" + ---help--- + Use the low-priority (LP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +config STM32_FDCAN_HPWORK + bool "Use HP work queue" + ---help--- + Use the high-priority (HP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +endchoice # FDCAN WorkQueue Selection + +if STM32_FDCAN1 + +config STM32_FDCAN1_LOOPBACK + bool "Enable FDCAN1 loopback mode" + ---help--- + Enable the FDCAN1 local loopback mode for testing purposes. + +config STM32_FDCAN1_BITRATE + int "FDCAN1 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. + +config STM32_FDCAN1_AUTO_BIT_TIMING + bool "FDCAN1 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN1 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 nominal bit timing" + +config STM32_FDCAN1_NTSEG1 + int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NTSEG2 + int "FDCAN1 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NSJW + int "FDCAN1 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN1_AUTO_BIT_TIMING + +config STM32_FDCAN1_DBITRATE + int "FDCAN1 data bitrate" + depends on CAN_FD && STM32_FDCAN1_FD_BRS + default 2000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 data bit timing" + +config STM32_FDCAN1_DTSEG1 + int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DTSEG2 + int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DSJW + int "FDCAN1 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +config STM32_FDCAN2_LOOPBACK + bool "Enable FDCAN2 loopback mode" + ---help--- + Enable the FDCAN2 local loopback mode for testing purposes. + +config STM32_FDCAN2_BITRATE + int "FDCAN2 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. + +config STM32_FDCAN2_AUTO_BIT_TIMING + bool "FDCAN2 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN2 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 nominal bit timing" + +config STM32_FDCAN2_NTSEG1 + int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NTSEG2 + int "FDCAN2 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NSJW + int "FDCAN2 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN2_AUTO_BIT_TIMING + +config STM32_FDCAN2_DBITRATE + int "FDCAN2 data bitrate" + depends on CAN_FD && STM32_FDCAN2_FD_BRS + default 2000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 data bit timing" + +config STM32_FDCAN2_DTSEG1 + int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DTSEG2 + int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DSJW + int "FDCAN2 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +endif # STM32_FDCAN2 + +if STM32_FDCAN3 + +choice + prompt "FDCAN3 frame format" + default STM32_FDCAN3_ISO11898_1 + +config STM32_FDCAN3_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN3_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN3 frame format + +choice + prompt "FDCAN3 mode" + default STM32_FDCAN3_CLASSIC + +config STM32_FDCAN3_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN3_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN3_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN3 mode + +config STM32_FDCAN3_LOOPBACK + bool "Enable FDCAN3 loopback mode" + default n + ---help--- + Enable the FDCAN3 local loopback mode for testing purposes. + +config STM32_FDCAN3_BITRATE + int "FDCAN3 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. + +comment "FDCAN3 nominal bit timing" + +config STM32_FDCAN3_NTSEG1 + int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NTSEG2 + int "FDCAN3 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NSJW + int "FDCAN3 synchronization jump width" + default 1 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DBITRATE + int "FDCAN3 data bitrate" + depends on CAN_FD && STM32_FDCAN3_FD_BRS + default 2000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN3_FD_BRS + +comment "FDCAN3 data bit timing" + +config STM32_FDCAN3_DTSEG1 + int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DTSEG2 + int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DSJW + int "FDCAN3 fast synchronization jump width" + default 2 + range 1 15 if STM32_STM32G4XXX + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN3_FD_BRS + +endif # STM32_FDCAN3 diff --git a/arch/arm/src/common/stm32/Kconfig.flash b/arch/arm/src/common/stm32/Kconfig.flash new file mode 100644 index 00000000000..1dc3d64bae9 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.flash @@ -0,0 +1,162 @@ +# +# STM32 flash configuration options. +# + +# Common STM32 flash size designator options. + +config STM32_FLASH_CONFIG_DEFAULT + bool "Default or device-derived flash size" + default n + +config STM32_FLASH_CONFIG_4 + bool "Flash size designator 4, 16 KiB" + default n + +config STM32_FLASH_CONFIG_6 + bool "Flash size designator 6, 32 KiB" + default n + +config STM32_FLASH_CONFIG_8 + bool "Flash size designator 8, 64 KiB" + default n + +config STM32_FLASH_CONFIG_B + bool "Flash size designator B, 128 KiB" + default n + +config STM32_FLASH_CONFIG_C + bool "Flash size designator C, 256 KiB" + default n + +config STM32_FLASH_CONFIG_C_320 + bool "STM32WB flash size designator C, 320 KiB variant" + default n + +config STM32_FLASH_CONFIG_D + bool "Flash size designator D, 384 KiB" + default n + +config STM32_FLASH_CONFIG_E + bool "Flash size designator E, 512 KiB" + default n + +config STM32_FLASH_CONFIG_F + bool "Flash size designator F, 768 KiB" + default n + +config STM32_FLASH_CONFIG_G + bool "Flash size designator G, 1024 KiB" + default n + +config STM32_FLASH_CONFIG_I + bool "Flash size designator I, 2048 KiB" + default n + +config STM32_FLASH_CONFIG_Y + bool "Flash size designator Y, 640 KiB" + default n + +config STM32_FLASH_CONFIG_Z + bool "Legacy STM32 flash size designator Z" + default n + +config STM32_FLASH_OVERRIDE + bool "Override Flash Designator" if ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + default y if ARCH_CHIP_STM32F7 || STM32_COMMON_F7_H7_H5 + default y if STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default y if ARCH_CHIP_STM32WL5 + default n + +choice + prompt "Override Flash Size Designator" + depends on STM32_FLASH_OVERRIDE + default STM32_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32 parts numbering ends with a number or letter that designates + the internal FLASH size. Select "Default" to use the size from + the selected chip. Select another designator only when the part + variant differs from the listed chip selection. + +config STM32_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32_FLASH_OVERRIDE_6 + bool "6 32KiB" + +config STM32_FLASH_OVERRIDE_8 + bool "8 64KiB" + +config STM32_FLASH_OVERRIDE_B + bool "B 128KiB" + +config STM32_FLASH_OVERRIDE_C + bool "C 256KiB" + +config STM32_FLASH_OVERRIDE_C_320 + bool "C 320KiB" + +config STM32_FLASH_OVERRIDE_E + bool "E 512KiB" + +config STM32_FLASH_OVERRIDE_G + bool "G 1024KiB" + +config STM32_FLASH_OVERRIDE_I + bool "I 2048KiB" + +config STM32_FLASH_OVERRIDE_Y + bool "Y 640KiB" + +endchoice # Override Flash Size Designator + +config STM32_FLASH_ART_ACCELERATOR + bool "Flash ART Accelerator" + depends on STM32_HAVE_FLASH_ART_ACCELERATOR + default n + ---help--- + ART Accelerator on the flash memory ITCM interface accelerates code execution + with a system of instruction prefetch and cache lines. + + Enable if code and/or read-only data is accessed through ITCM bus instead of + AXIM bus. + +config STM32_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + depends on STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 + default y + ---help--- + Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled + on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch + properly and enabling this option may interfere with ADC accuracy. + +config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW + bool "Workaround for FLASH data cache corruption" + depends on STM32_FLASH_DCACHE && (STM32_STM32F20XX || STM32_STM32F4XXX || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR))) + ---help--- + Enable the workaround to fix flash data cache corruption when reading + from one flash bank while writing on other flash bank. See your STM32 + errata to check if your STM32 is affected by this problem. + +config STM32_PROGMEM + bool "Flash PROGMEM support" + depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 + select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + ---help--- + Add progmem support, start block and end block options are provided to + obtain a uniform flash memory mapping. + +config STM32_FLASH_ICACHE + bool "Enable FLASH Instruction Cache" + default y + depends on STM32_HAVE_FLASH_ICACHE + ---help--- + Enable the FLASH instruction cache. + +config STM32_FLASH_DCACHE + bool "Enable FLASH Data Cache" + default y + depends on STM32_HAVE_FLASH_DCACHE + ---help--- + Enable the FLASH data cache. diff --git a/arch/arm/src/common/stm32/Kconfig.foc b/arch/arm/src/common/stm32/Kconfig.foc new file mode 100644 index 00000000000..79e61e292e4 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.foc @@ -0,0 +1,197 @@ +# +# STM32 common FOC options. +# + +config STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + bool + +config STM32_FOC_USE_TIM1 + bool + select STM32_TIM1 + select STM32_TIM1_PWM + select STM32_TIM1_CHANNEL1 + select STM32_TIM1_CHANNEL2 + select STM32_TIM1_CHANNEL3 + select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1OUT + select STM32_TIM1_CH2OUT + select STM32_TIM1_CH3OUT + select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM1 generates PWM for the FOC + +config STM32_FOC_USE_TIM8 + bool + select STM32_TIM8 + select STM32_TIM8_PWM + select STM32_TIM8_CHANNEL1 + select STM32_TIM8_CHANNEL2 + select STM32_TIM8_CHANNEL3 + select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1OUT + select STM32_TIM8_CH2OUT + select STM32_TIM8_CH3OUT + select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM8 generates PWM for the FOC + +config STM32_FOC_USE_ADC1 + bool + select STM32_ADC1 + select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC1_JEXTSEL + +config STM32_FOC_USE_ADC2 + bool + select STM32_ADC2 + select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC2_JEXTSEL + +config STM32_FOC_USE_ADC3 + bool + select STM32_ADC3 + select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC3_JEXTSEL + +# +# + +choice + prompt "FOC ADC trigger selection" + depends on STM32_FOC + default STM32_FOC_ADC_TRGO + +config STM32_FOC_ADC_CCR4 + bool "FOC uses CCR4 as ADC trigger" + ---help--- + This option uses the software frequency prescaler and is + not possible for 4-phase output. + +config STM32_FOC_ADC_TRGO + bool "FOC uses TRGO as ADC trigger" + depends on STM32_HAVE_IP_ADC_M3M4_V2 || ARCH_CHIP_STM32F7 || (STM32_HAVE_IP_ADC_M3M4_V1 && !STM32_FOC_FOC1) + select STM32_PWM_TRGO + ---help--- + This option allows you to use higher PWM frequency and works for 4-phase output. + It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). + +endchoice # "FOC ADC trigger selection" + +choice + prompt "FOC0 device ADC selection" + depends on STM32_FOC_FOC0 + default STM32_FOC_FOC0_ADC1 + +config STM32_FOC_FOC0_ADC1 + bool "FOC0 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC0_ADC2 + bool "FOC0 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC0_ADC3 + bool "FOC0 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC0_ADC4 + bool "FOC0 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +choice + prompt "FOC1 device ADC selection" + depends on STM32_FOC_FOC1 + default STM32_FOC_FOC1_ADC2 + +config STM32_FOC_FOC1_ADC1 + bool "FOC1 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC1_ADC2 + bool "FOC1 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC1_ADC3 + bool "FOC1 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC1_ADC4 + bool "FOC1 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +menuconfig STM32_FOC + bool "STM32 lower-half FOC support" + depends on STM32_HAVE_COMMON_FOC || ARCH_CHIP_STM32F7 + select ARCH_IRQPRIO + select STM32_ADC + select STM32_PWM_MULTICHAN + select STM32_PWM_LL_OPS + select STM32_ADC_LL_OPS + select STM32_ADC_CHANGE_SAMPLETIME + select STM32_ADC_NO_STARTUP_CONV + +config STM32_FOC_FOC0 + bool "FOC0 device (TIM1 for PWM modulation)" + depends on STM32_FOC && STM32_HAVE_TIM1 + select STM32_FOC_USE_TIM1 + ---help--- + Enable support for FOC0 device that uses TIM1 for PWM modulation + +config STM32_FOC_FOC1 + bool "FOC1 device (TIM8 for PWM modulation)" + depends on STM32_FOC && STM32_HAVE_TIM8 + select STM32_FOC_USE_TIM8 + ---help--- + Enable support for FOC1 device that uses TIM8 for PWM modulation + +config STM32_FOC_HAS_PWM_COMPLEMENTARY + bool "FOC PWM has complementary outputs" + depends on STM32_FOC + ---help--- + Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) + +# hidden variables and automatic configuration + +if STM32_FOC + +config STM32_FOC_USE_ADC4 + bool + default n + select STM32_ADC4 + select STM32_ADC3_JEXTSEL + +config STM32_FOC_G4_ADCCHAN0_WORKAROUND + bool "FOC G4 ADC channel 0 unwanted conversion workaround" + default n + depends on STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + ---help--- + Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 + conversion when a regular conversion is interrupted by an injected conversion. + This FOC implementation uses injected conversion to sample phase currents + and allows user to use regular conversion as an auxiliary analog conversion. + In this case, there is a certain probability that regular conversion will be + interrupted by an injected conversion that will lead to an incorrect reading + of phase currents. + + This workaround inserts a dummy conversion at the beginning of the injected + sequence. For more details look at the chip errata documents. + +endif #STM32_FOC diff --git a/arch/arm/src/common/stm32/Kconfig.gpio b/arch/arm/src/common/stm32/Kconfig.gpio new file mode 100644 index 00000000000..f7d3b676683 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.gpio @@ -0,0 +1,9 @@ +# +# STM32 GPIO configuration options. +# + +config STM32_GPIO_HAVE_PORTD + bool + +config STM32_GPIO_HAVE_PORTE + bool diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have new file mode 100644 index 00000000000..2772bd7cd82 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -0,0 +1,1191 @@ +# +# STM32 hidden hardware-capability flags (single source of truth). +# + +# All STM32_HAVE_* / STM32_HAVE_IP_* symbols are defined here. They are +# prompt-less bool selectors describing what hardware exists on a chip and +# which IP-core version a peripheral uses. Family Kconfig files +# (arch/arm/src/stm32/Kconfig) "select" these symbols to describe their +# silicon; never add a prompt here. User-visible peripheral selection lives +# in Kconfig.periph and per-peripheral options in Kconfig.. +# +# Naming: an STM32_HAVE_IP__V symbol names the IP-core VERSION only; +# it must NOT encode the CPU core, because a given IP version is the same +# silicon regardless of whether it sits next to a Cortex-M0 or M3/M4 core (e.g. +# SPI v2 is SPI v2 on both STM32F0 and STM32F4). When a core-specific driver +# .c file or register header has to be chosen, use the standard NuttX core +# symbols (CONFIG_ARCH_CORTEXM0 for M0, CONFIG_ARCH_CORTEXM3 / ARCH_CORTEXM4 +# otherwise) -- not an STM32_HAVE_IP_* symbol. +# +# Two-level selection is intentional and must NOT be "cleaned up" as a +# duplicate: some peripherals use a "register-set" symbol that picks the +# hardware header (e.g. STM32_HAVE_IP_FLASH_M3M4_V1 -> hardware/stm32_flash.h, +# STM32_HAVE_IP_DMA_V1/_V2 -> hardware/stm32_dma.h) AND a separate +# "driver-variant" symbol that picks the .c file in Make.defs (e.g. +# STM32_HAVE_IP_FLASH_M3M4_F2F4, STM32_HAVE_IP_DMA_V2_STREAM). A family +# legitimately selects one of each. +# +# Within a single mutually-exclusive group (the #elif dispatch in +# hardware/stm32_.h and the else-if chain in Make.defs), a family must +# select exactly one member; the dispatch headers carry #error guards that +# enforce this at build time. +# + +# ADC capabilities + +config STM32_HAVE_ADC_TIMTRIG_TRGO2 + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_ADC_TIMTRIG_TRGO + bool + default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 + +config STM32_HAVE_TIM_ADC_CHANNEL + bool + +config STM32_HAVE_ADC_L4 + bool + +config STM32_HAVE_ADC_H5 + bool + +config STM32_HAVE_ADC2 + bool + +config STM32_HAVE_ADC3 + bool + +config STM32_HAVE_ADC4 + bool + +config STM32_HAVE_ADC5 + bool + +config STM32_HAVE_ADC_OVERSAMPLE + bool + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 + +config STM32_HAVE_SDADC1 + bool + +config STM32_HAVE_SDADC2 + bool + +config STM32_HAVE_SDADC3 + bool + +config STM32_HAVE_IP_SDADC_M3M4_V1 + bool + +config STM32_HAVE_IP_ADC_M3M4_V1 + bool + select STM32_HAVE_ADC1 + +config STM32_HAVE_IP_ADC_M3M4_V1_BASIC + bool + select STM32_HAVE_IP_ADC_M3M4_V1 + +config STM32_HAVE_IP_ADC_M3M4_V2 + bool + select STM32_HAVE_ADC1 + +config STM32_HAVE_IP_ADC_M3M4_V2_BASIC + bool + select STM32_HAVE_IP_ADC_M3M4_V2 + +config STM32_HAVE_IP_ADC_M0_V1 + bool + +config STM32_HAVE_ADC1 + bool + +# BLE capabilities + +config STM32_HAVE_BLE + bool + +# CACHE capabilities + +config STM32_HAVE_DCACHE1 + bool + +config STM32_HAVE_ICACHE + bool + +# CAN capabilities + +config STM32_HAVE_CAN1 + bool + +config STM32_HAVE_CAN2 + bool + +config STM32_HAVE_CAN3 + bool + +config STM32_HAVE_IP_CAN_BXCAN_M0_V1 + bool + +config STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + bool + +# CEC capabilities + +config STM32_HAVE_CEC + bool + +# CLOCK capabilities + +config STM32_HAVE_CSI + bool + +config STM32_HAVE_CRS + bool + +config STM32_HAVE_HSI48 + bool + +config STM32_HAVE_IP_HSI48_M0_V1 + bool + +# COMP capabilities + +config STM32_HAVE_COMP1 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP2 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP3 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP4 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP5 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP6 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP7 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_IP_COMP_M3M4_V1 + bool + +config STM32_HAVE_IP_COMP_M3M4_V2 + bool + +config STM32_HAVE_IP_COMP_M0_V1 + bool + +config STM32_HAVE_COMP + bool + select STM32_HAVE_SYSCFG + +# CORDIC capabilities + +config STM32_HAVE_CORDIC + bool + +config STM32_HAVE_FMAC + bool + +config STM32_HAVE_IP_CORDIC_M3M4_V1 + bool + +# DAC capabilities + +config STM32_HAVE_DAC_LL_OPS + bool + +config STM32_HAVE_IP_DAC_M3M4_V1 + bool + +config STM32_HAVE_IP_DAC_M3M4_V2 + bool + +config STM32_HAVE_IP_DAC_M0_V1 + bool + +config STM32_HAVE_DAC1 + bool + +config STM32_HAVE_DAC2 + bool + +config STM32_HAVE_DAC3 + bool + +config STM32_HAVE_DAC4 + bool + +# DBGMCU capabilities + +config STM32_HAVE_IP_DBGMCU_M0_V1 + bool + +config STM32_HAVE_IP_DBGMCU_M3M4_V1 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_CR + +config STM32_HAVE_IP_DBGMCU_M3M4_V2 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + +config STM32_HAVE_IP_DBGMCU_M3M4_V3 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + +# DCMI capabilities + +config STM32_HAVE_DCMI_PSSI + bool + +config STM32_HAVE_DCMI + bool + +config STM32_HAVE_IP_DCMI_V1 + bool + +# DFSDM capabilities + +config STM32_HAVE_MDF1 + bool + +config STM32_HAVE_ADF1 + bool + +config STM32_HAVE_DFSDM1 + bool + +# DMA capabilities + +config STM32_HAVE_MDMA + bool + +config STM32_HAVE_BDMA + bool + +config STM32_HAVE_GPADMA1 + bool + +config STM32_HAVE_LPDMA1 + bool + +config STM32_HAVE_DMA1 + bool + +config STM32_HAVE_DMA2 + bool + +config STM32_HAVE_DMA2D + bool + +config STM32_HAVE_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V1 + bool + +config STM32_HAVE_IP_DMA_V2 + bool + +config STM32_HAVE_IP_DMA_V1_7CH + bool + +config STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V1_8CH + bool + +config STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V2_STREAM + bool + +config STM32_HAVE_IP_DMA2D_M3M4_V1 + bool + +# DTS capabilities + +config STM32_HAVE_DTS + bool + +# ETH capabilities + +config STM32_HAVE_ETHMAC + bool + +config STM32_HAVE_IP_ETHMAC_M3M4_V1 + bool + +config STM32_HAVE_ETHRNET + bool + +config STM32_HAVE_ETHERNET + bool + +# FDCAN capabilities + +config STM32_HAVE_FDCAN_H7 + bool + +config STM32_HAVE_FDCAN1 + bool + +config STM32_HAVE_FDCAN2 + bool + +config STM32_HAVE_FDCAN3 + bool + +config STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + bool + +config STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + bool + +# FLASH capabilities + +config STM32_HAVE_FLASH_ART_ACCELERATOR + bool + +config STM32_HAVE_FLASH + bool + +config STM32_HAVE_OTA_PARTITION + bool + +config STM32_HAVE_IP_FLASH_M0_V1 + bool + +config STM32_HAVE_IP_FLASH_M3M4_V1 + bool + +config STM32_HAVE_IP_FLASH_M0_G0C0 + bool + +config STM32_HAVE_IP_FLASH_M3M4_L1 + bool + +config STM32_HAVE_IP_FLASH_M3M4_F1F3 + bool + +config STM32_HAVE_IP_FLASH_M3M4_F2F4 + bool + +config STM32_HAVE_IP_FLASH_M3M4_G4 + bool + +config STM32_HAVE_OTFDEC1 + bool + +config STM32_HAVE_OTFDEC2 + bool + +config STM32_HAVE_FLASH_ICACHE + bool + +config STM32_HAVE_FLASH_DCACHE + bool + +# FOC capabilities + +config STM32_HAVE_COMMON_FOC + bool + +# GPIO capabilities + +config STM32_HAVE_LPGPIO1 + bool + +config STM32_HAVE_GPIOF + bool + +config STM32_HAVE_GPIOG + bool + +# HRTIM capabilities + +config STM32_HAVE_HRTIM1 + bool + +config STM32_HAVE_IP_HRTIM_M3M4_V1 + bool + +# I2C capabilities + +config STM32_HAVE_I2C_H5 + bool + +config STM32_HAVE_I2C5 + bool + +config STM32_HAVE_I2C6 + bool + +config STM32_HAVE_IP_I2C_M3M4_V1 + bool + +config STM32_HAVE_IP_I2C_M3M4_V2 + bool + +config STM32_HAVE_IP_I2C_M0_V1 + bool + +config STM32_HAVE_I2C1 + bool + +config STM32_HAVE_I2C2 + bool + +config STM32_HAVE_I2C3 + bool + +config STM32_HAVE_I2C4 + bool + +# IPCC capabilities + +config STM32_HAVE_HSEM + bool + +config STM32_HAVE_CM4 + bool + +config STM32_HAVE_MBOX + bool + +config STM32_HAVE_IPCC + bool + +# JPEG capabilities + +config STM32_HAVE_JPEG + bool + +# LPUART capabilities + +config STM32_HAVE_LPUART1 + bool + +config STM32_HAVE_LPUART2 + bool + +config STM32_HAVE_LPUART + bool + +# LTDC capabilities + +config STM32_HAVE_LTDC + bool + +config STM32_HAVE_IP_LTDC_M3M4_V1 + bool + +config STM32_HAVE_DSIHOST + bool + +config STM32_HAVE_LCD + bool + +# MEMORY capabilities + +config STM32_HAVE_RAMCFG + bool + +config STM32_HAVE_SRAM1 + bool + +config STM32_HAVE_SRAM2 + bool + +config STM32_HAVE_SRAM3 + bool + +config STM32_HAVE_SRAM5 + bool + +config STM32_HAVE_CCM + bool + +config STM32_HAVE_FMC + bool + +config STM32_HAVE_FSMC + bool + +config STM32_HAVE_IP_CCM_M3M4_V1 + bool + +config STM32_HAVE_IP_FMC_M3M4_V1 + bool + +config STM32_HAVE_IP_FSMC_M3M4_V1 + bool + +config STM32_HAVE_IP_BBSRAM_M3M4_V1 + bool + +config STM32_HAVE_IP_BKP_M3M4_V1 + bool + +config STM32_HAVE_BKPSRAM + bool + +config STM32_HAVE_BKP + bool + +config STM32_HAVE_COMMON_WASTE + bool + default y if STM32_COMMON_LEGACY + +config STM32_HAVE_IP_DFUMODE_M3M4_V1 + bool + +config STM32_HAVE_SRAM2A + bool + +config STM32_HAVE_SRAM2B + bool + +# OPAMP capabilities + +config STM32_HAVE_OPAMP1 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP2 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP3 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP4 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP5 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP6 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_IP_OPAMP_M3M4_V1 + bool + +# POWER capabilities + +config STM32_HAVE_PWR + bool + +config STM32_HAVE_OVERDRIVE + bool + +config STM32_HAVE_VREF + bool + +config STM32_HAVE_VREFINT + bool + +config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY + bool + +config STM32_HAVE_IP_PWR_M0_V1 + bool + +config STM32_HAVE_IP_PWR_G0 + bool + +config STM32_HAVE_IP_PWR_M3M4_V1 + bool + +config STM32_HAVE_SMPS + bool + +# QSPI capabilities + +config STM32_HAVE_QSPI1 + bool + +config STM32_HAVE_OCTOSPIM + bool + +config STM32_HAVE_OCTOSPI1 + bool + +config STM32_HAVE_OCTOSPI2 + bool + +config STM32_HAVE_QSPI + bool + +# CRC capabilities + +config STM32_HAVE_CRC + bool + +# RNG capabilities + +config STM32_HAVE_RNG + bool + +config STM32_HAVE_IP_RNG_M0_V1 + bool + +config STM32_HAVE_IP_RNG_M3M4_V1 + bool + +# RTC capabilities + +config STM32_HAVE_RTC + bool + +config STM32_HAVE_RTC_MAGIC + bool + +config STM32_HAVE_RTCAPB + bool + +config STM32_HAVE_RTC_COUNTER + bool + +config STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + bool + +config STM32_HAVE_IP_RTCC_M0_V1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_V1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_L1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_F4 + bool + +config STM32_HAVE_IP_RTC_M3M4_V1 + bool + +config STM32_HAVE_RTC_SUBSECONDS + bool + select ARCH_HAVE_RTC_SUBSECONDS + +# SAI capabilities + +config STM32_HAVE_SAIPLL + bool + +config STM32_HAVE_SAI + bool + +config STM32_HAVE_I2S3 + bool + +config STM32_HAVE_I2S2 + bool + +config STM32_HAVE_SPI2S2 + bool + +config STM32_HAVE_I2SPLL + bool + +config STM32_HAVE_IP_I2S_M3M4_V1 + bool + +config STM32_HAVE_SAI1 + bool + +config STM32_HAVE_SAI2 + bool + +# SDIO capabilities + +config STM32_HAVE_SDIO + bool + +config STM32_HAVE_SDMMC1 + bool + +config STM32_HAVE_SDMMC2 + bool + +config STM32_HAVE_IP_SDIO_M3M4_V1 + bool + +# SECURITY capabilities + +config STM32_HAVE_FIREWALL + bool + +config STM32_HAVE_GTZC1 + bool + +config STM32_HAVE_GTZC2 + bool + +config STM32_HAVE_PKA + bool + +config STM32_HAVE_SAES + bool + +config STM32_HAVE_AES + bool + +config STM32_HAVE_CRYP + bool + +config STM32_HAVE_IP_AES_M0_V1 + bool + +config STM32_HAVE_IP_AES_M3M4_V1 + bool + +config STM32_HAVE_IP_CRYPTO_M3M4_V1 + bool + +config STM32_HAVE_IP_CRYPTO_H7 + bool + +config STM32_HAVE_HASH + bool + +# SPI capabilities + +config STM32_HAVE_SPI_CORE_DMA + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if ARCH_CHIP_STM32WL5 + default y if STM32_COMMON_L4_L5_U5 && STM32_SPI + default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA + +config STM32_HAVE_SPI_DMA_FAMILY_WL5 + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 + +config STM32_HAVE_SPI_DMA_FAMILY + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 + +config STM32_HAVE_IP_SPI_V1 + bool + +config STM32_HAVE_IP_SPI_V2 + bool + +config STM32_HAVE_IP_SPI_V3 + bool + +config STM32_HAVE_IP_SPI_V4 + bool + +config STM32_HAVE_SPI1 + bool + +config STM32_HAVE_SPI2 + bool + +config STM32_HAVE_SPI3 + bool + +config STM32_HAVE_SPI4 + bool + +config STM32_HAVE_SPI5 + bool + +config STM32_HAVE_SPI6 + bool + +# SYSTEM capabilities + +config STM32_HAVE_IP_EXTI_V1 + bool + +config STM32_HAVE_IP_EXTI_V2 + bool + +config STM32_HAVE_IP_GPIO_M0_V1 + bool + +config STM32_HAVE_IP_GPIO_M3M4_V1 + bool + +config STM32_HAVE_SYSCFG + bool + +config STM32_HAVE_IP_SYSCFG_M3M4_V1 + bool + +config STM32_HAVE_IOCOMPENSATION + bool + +# TIM capabilities + +config STM32_HAVE_TIM_PWM + bool + default y if STM32_COMMON_FULL_FEATURED + +config STM32_HAVE_TIM_PWM_NO_F0 + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_HAVE_TIM_PWM_ADVANCED + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_SINGLECHAN + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_INTERNAL + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7_H5 + +config STM32_HAVE_TIM_PWM_STM32PWM + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + +config STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + bool + default y if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_CHMODE_LEGACY + bool + default y if STM32_HAVE_IP_TIMERS && !STM32_HAVE_IP_TIMERS_M3M4_V2 + +config STM32_HAVE_TIM_PWM_CHMODE_LIMITED + bool + default y if STM32_HAVE_IP_TIMERS_M0_V1 || STM32_COMMON_L5_U5 + +config STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + bool + default y if STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_HAVE_TIM_PWM_NOUT_REQUIRES_OUT + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_PWM_MULTICHAN + bool + default y if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_PWM + default y if (STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7) && STM32_PWM + default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM + default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS + +config STM32_HAVE_QENCODER_MAIN + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_QENCODER_16BIT + bool + default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 + +config STM32_ENERGYLITE + bool + select STM32_HAVE_TIM6 if STM32_HAVE_IP_TIMERS + select STM32_HAVE_TIM7 if STM32_HAVE_IP_TIMERS + +config STM32_HAVE_LPTIM_CHANNEL + bool + +config STM32_HAVE_IP_TIMERS + bool + +config STM32_HAVE_IP_TIMERS_M3M4_V1 + bool + select STM32_HAVE_IP_TIMERS + +config STM32_HAVE_IP_TIMERS_M3M4_V2 + bool + select STM32_HAVE_IP_TIMERS + +config STM32_HAVE_IP_TIMERS_M3M4_V3 + bool + select STM32_HAVE_IP_TIMERS + +config STM32_HAVE_IP_TIMERS_M0_V1 + bool + select STM32_HAVE_IP_TIMERS + +config STM32_HAVE_TIM_ADC_TRIGGER + bool + default y if STM32_HAVE_IP_ADC_M3M4_V1 + default y if STM32_HAVE_IP_ADC_M3M4_V2 + default y if STM32_HAVE_IP_ADC_M0_V1 + default y if STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_H5_L5_U5 + default y if ARCH_CHIP_STM32F7 + default y if ARCH_CHIP_STM32H7 + +config STM32_HAVE_TIM_DAC_TRIGGER + bool + default y if STM32_COMMON_LEGACY + default y if ARCH_CHIP_STM32F7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_TIM1 + bool + +config STM32_HAVE_TIM2 + bool + +config STM32_HAVE_TIM3 + bool + +config STM32_HAVE_TIM4 + bool + +config STM32_HAVE_TIM5 + bool + +config STM32_HAVE_TIM6 + bool + +config STM32_HAVE_TIM7 + bool + +config STM32_HAVE_TIM8 + bool + +config STM32_HAVE_TIM9 + bool + +config STM32_HAVE_TIM10 + bool + +config STM32_HAVE_TIM11 + bool + +config STM32_HAVE_TIM12 + bool + +config STM32_HAVE_TIM13 + bool + +config STM32_HAVE_TIM14 + bool + +config STM32_HAVE_TIM15 + bool + +config STM32_HAVE_TIM16 + bool + +config STM32_HAVE_TIM17 + bool + +config STM32_HAVE_TIM18 + bool + +config STM32_HAVE_TIM19 + bool + +config STM32_HAVE_TIM20 + bool + +config STM32_HAVE_LPTIM1 + bool + +config STM32_HAVE_LPTIM2 + bool + +config STM32_HAVE_LPTIM3 + bool + +config STM32_HAVE_LPTIM4 + bool + +config STM32_HAVE_IP_ONESHOT_M3M4_V1 + bool + +config STM32_HAVE_IP_FREERUN_M3M4_V1 + bool + +# TSC capabilities + +config STM32_HAVE_TSC + bool + +# UART capabilities + +config STM32_HAVE_SWPMI + bool + +config STM32_HAVE_USART_H5 + bool + +config STM32_HAVE_USART_RXFIFO_THRESHOLD + bool + +config STM32_HAVE_USART_UNCONFIG_ON_CLOSE + bool + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32N6 + +config STM32_HAVE_USART2 + bool + +config STM32_HAVE_USART3 + bool + +config STM32_HAVE_UART4 + bool + +config STM32_HAVE_UART5 + bool + +config STM32_HAVE_USART6 + bool + +config STM32_HAVE_UART7 + bool + +config STM32_HAVE_UART8 + bool + +config STM32_HAVE_IP_USART + bool + +config STM32_HAVE_IP_USART_V1 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V2 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V3 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V4 + bool + select STM32_HAVE_IP_USART + select STM32_HAVE_USART_RXFIFO_THRESHOLD + +config STM32_HAVE_USART4 + bool + +config STM32_HAVE_USART5 + bool + +config STM32_HAVE_USART7 + bool + +config STM32_HAVE_USART8 + bool + +config STM32_HAVE_UART9 + bool + +config STM32_HAVE_USART10 + bool + +config STM32_HAVE_USART11 + bool + +config STM32_HAVE_UART12 + bool + +config STM32_HAVE_USART1 + bool + +# UID capabilities + +config STM32_HAVE_IP_UID_M0_V1 + bool + +config STM32_HAVE_IP_UID_M3M4_V1 + bool + +# USB capabilities + +config STM32_HAVE_USBFS_MODE + bool + +config STM32_HAVE_USBDRD_HOST + bool + +config STM32_HAVE_OTG_H7 + bool + +config STM32_HAVE_INTERNAL_ULPI + bool + +config STM32_HAVE_EXTERNAL_ULPI + bool + +config STM32_HAVE_UCPD + bool + +config STM32_HAVE_UCPD1 + bool + +config STM32_HAVE_UCPD2 + bool + +config STM32_HAVE_USBDEV + bool + +config STM32_HAVE_IP_USBDEV_M0_V1 + bool + +config STM32_HAVE_IP_USBDEV_M3M4_V1 + bool + +config STM32_HAVE_USBFS + bool + +config STM32_HAVE_IP_USBFS_M3M4_V1 + bool + +config STM32_HAVE_OTGFS + bool + +config STM32_HAVE_OTGHS + bool + +config STM32_HAVE_IP_OTGFS_M3M4_V1 + bool + +config STM32_HAVE_IP_OTGHS_M3M4_V1 + bool + +config STM32_HAVE_COMMON_USBHOST_DEBUG + bool + default y if STM32_COMMON_LEGACY + +config STM32_HAVE_USB + bool + +# WDG capabilities + +config STM32_HAVE_IP_WDG_M0_V1 + bool + +config STM32_HAVE_IP_WDG_M3M4_V1 + bool diff --git a/arch/arm/src/common/stm32/Kconfig.hciuart b/arch/arm/src/common/stm32/Kconfig.hciuart new file mode 100644 index 00000000000..81fb4fcb448 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.hciuart @@ -0,0 +1,292 @@ +# +# STM32 common HCI UART options. +# + +config STM32_HCIUART + bool + +config STM32_HCIUART_RXDMA + bool + +if STM32_USART1_HCIUART + +config STM32_HCIUART1_RXBUFSIZE + int "HCI UART1 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART1_TXBUFSIZE + int "HCI UART1 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART1_BAUD + int "HCI UART1 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART1_RXDMA + bool "HCI UART1 Rx DMA" + default n + depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART1_HCIUART + +if STM32_USART2_HCIUART + +config STM32_HCIUART2_RXBUFSIZE + int "HCI UART2 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART2_TXBUFSIZE + int "HCI UART2 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART2_BAUD + int "HCI UART2 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART2_RXDMA + bool "HCI UART2 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART2_HCIUART + +if STM32_USART3_HCIUART + +config STM32_HCIUART3_RXBUFSIZE + int "HCI UART3 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART3_TXBUFSIZE + int "HCI UART3 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART3_BAUD + int "HCI UART3 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART3_RXDMA + bool "HCI UART3 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART3_HCIUART + +if STM32_USART6_HCIUART + +config STM32_HCIUART6_RXBUFSIZE + int "HCI UART6 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART6_TXBUFSIZE + int "HCI UART6 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART6_BAUD + int "HCI UART6 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART6_RXDMA + bool "HCI UART6 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART6_HCIUART + +if STM32_UART7_HCIUART + +config STM32_HCIUART7_RXBUFSIZE + int "HCI UART7 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART7_TXBUFSIZE + int "HCI UART7 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART7_BAUD + int "HCI UART7 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART7_RXDMA + bool "HCI UART7 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART7_HCIUART + +if STM32_UART8_HCIUART + +config STM32_HCIUART8_RXBUFSIZE + int "HCI UART8 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART8_TXBUFSIZE + int "HCI UART8 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART8_BAUD + int "HCI UART8 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART8_RXDMA + bool "HCI UART8 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART8_HCIUART + +menu "HCI UART Driver Configuration" + depends on STM32_SERIALDRIVER + +config STM32_HCIUART_RXDMA_BUFSIZE + int "Rx DMA buffer size" + default 32 + range 32 4096 + depends on STM32_HCIUART_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_HCIUART_RXDMAPRIO + hex "HCI UART DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_HCIUART_RXDMA + ---help--- + Select HCI UART DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_HCIUART_SW_RXFLOW + bool "Use Software UART RTS flow control" + default n + ---help--- + Enable UART RTS flow control using Software. Current STM32 have + broken HW based RTS behavior (they assert nRTS after every byte + received) Enable this setting workaround this issue by using + software based management of RTS + + If HCI UART DMA is enabled, this is probably the better selection + as well. In that case, the Rx DMA buffer will avoid Rx overrun due + to short, bursty activity. Software RTS management will probably + result in overall better throughput and should still avoid Rx data + overrun conditions. + +config STM32_HCIUART_UPPER_WATERMARK + int "RTS flow control upper watermark (%)" + default 75 + range 2 100 + depends on STM32_HCIUART_SW_RXFLOW + ---help--- + If software RTS flow control is enable, then RTS will be asserted + when this amount of Rx data has been buffered. The amount is + expressed as a percentage of the Rx buffer size. + +config STM32_HCIUART_LOWER_WATERMARK + int "RTS flow control lower watermark (%)" + default 25 + range 1 99 + depends on STM32_HCIUART_SW_RXFLOW + ---help--- + If software RTS flow control is enable, then RTS will be de-asserted + when there is less than this amount ofdata in the Rx buffere. The + amount is expressed as a percentage of the Rx buffer size. + +endmenu # HCI UART Driver Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.hrtim b/arch/arm/src/common/stm32/Kconfig.hrtim new file mode 100644 index 00000000000..ec2378f35b7 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.hrtim @@ -0,0 +1,583 @@ +# +# STM32 HRTIM configuration options. +# + +config STM32_HRTIM1_HAVE_PLLCLK + bool + default y if STM32_STM32F33XX + +config STM32_HRTIM_DISABLE_CHARDRV + bool "HRTIM Disable Character Driver" + default n + ---help--- + In most cases we do not need HRTIM Character Driver, so we can disable it + and save some memory. + +config STM32_HRTIM_NO_ENABLE_TIMERS + bool "Do not enable HRTIM timers at startup" + default n + ---help--- + Do not enable HRTIM timers at startup + +menuconfig STM32_HRTIM_ADC + bool "HRTIM ADC Triggering" + default n + ---help--- + Enable HRTIM ADC Triggering support. + +if STM32_HRTIM_ADC + +config STM32_HRTIM_ADC1_TRG1 + bool "HRTIM ADC1 Trigger 1" + default n + +config STM32_HRTIM_ADC1_TRG2 + bool "HRTIM ADC1 Trigger 2" + default n + +config STM32_HRTIM_ADC1_TRG3 + bool "HRTIM ADC1 Trigger 3" + default n + +config STM32_HRTIM_ADC1_TRG4 + bool "HRTIM ADC1 Trigger 4" + default n + +config STM32_HRTIM_ADC2_TRG1 + bool "HRTIM ADC2 Trigger 1" + default n + +config STM32_HRTIM_ADC2_TRG2 + bool "HRTIM ADC2 Trigger 2" + default n + +config STM32_HRTIM_ADC2_TRG3 + bool "HRTIM ADC2 Trigger 3" + default n + +config STM32_HRTIM_ADC2_TRG4 + bool "HRTIM ADC2 Trigger 4" + default n + +endif # STM32_HRTIM_ADC + +config STM32_HRTIM_DAC + bool "HRTIM DAC Triggering" + default n + ---help--- + Enable HRTIM DAC Triggering support. + +config STM32_HRTIM_PWM + bool "HRTIM PWM Outputs" + default n + ---help--- + Enable HRTIM PWM Outputs support. + +config STM32_HRTIM_CAP + bool "HRTIM Capture" + default n + ---help--- + Enable HRTIM Capture support. + +config STM32_HRTIM_INTERRUPTS + bool "HRTIM Interrupts" + default n + ---help--- + Enable HRTIM Interrupts support. + +config STM32_HRTIM_BURST + bool "HRTIM Burst Mode" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Burst Mode support for PWM outputs. + +config STM32_HRTIM_DEADTIME + bool "HRTIM Dead-time" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Deadtime support for PWM outputs. + +config STM32_HRTIM_PUSHPULL + bool "HRTIM Push-Pull Mode" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Push-Pull Mode support for PWM outputs. + +config STM32_HRTIM_CHOPPER + bool "HRTIM Chopper" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Chopper Mode for PWM outputs. + +config STM32_HRTIM_DMA + bool "HRTIM DMA" + default n + +config STM32_HRTIM_DMABURST + bool "HRTIM DMA Burst" + default n + +config STM32_HRTIM_AUTODELAY + bool "HRTIM Autodelay" + depends on STM32_HRTIM_PWM + default n + +menuconfig STM32_HRTIM_EVENTS + bool "HRTIM Events Configuration" + default n + ---help--- + Enable HRTIM Events support. + +if STM32_HRTIM_EVENTS + +config STM32_HRTIM_EEV1 + bool "HRTIM EEV1" + default n + +config STM32_HRTIM_EEV2 + bool "HRTIM EEV2" + default n + +config STM32_HRTIM_EEV3 + bool "HRTIM EEV3" + default n + +config STM32_HRTIM_EEV4 + bool "HRTIM EEV4" + default n + +config STM32_HRTIM_EEV5 + bool "HRTIM EEV5" + default n + +config STM32_HRTIM_EEV6 + bool "HRTIM EEV6" + default n + +config STM32_HRTIM_EEV7 + bool "HRTIM EEV7" + default n + +config STM32_HRTIM_EEV8 + bool "HRTIM EEV8" + default n + +config STM32_HRTIM_EEV9 + bool "HRTIM EEV9" + default n + +config STM32_HRTIM_EEV10 + bool "HRTIM EEV10" + default n + +endif # STM32_HRTIM_EVENTS + +menuconfig STM32_HRTIM_FAULTS + bool "HRTIM Faults Configuration" + default n + ---help--- + Enable HRTIM Faults support. + +if STM32_HRTIM_FAULTS + +config STM32_HRTIM_FAULT1 + bool "HRTIM Fault 1" + default n + +config STM32_HRTIM_FAULT2 + bool "HRTIM Fault 2" + default n + +config STM32_HRTIM_FAULT3 + bool "HRTIM Fault 3" + default n + +config STM32_HRTIM_FAULT4 + bool "HRTIM Fault 4" + default n + +endif # STM32_HRTIM_FAULTS + +config STM32_HRTIM_CLK_FROM_PLL + bool "HRTIM Clock from PLL" + default n + depends on STM32_HRTIM1_HAVE_PLLCLK + ---help--- + Set PLL as the clock source for HRTIM. + This configuration requires the following conditions: + 1) system clock is PLL, + 2) SYSCLK and PCLK2 ratio must be 1 o 2. + +menu "HRTIM Master Configuration" + depends on STM32_HRTIM_MASTER + +config STM32_HRTIM_MASTER_DAC + bool "HRTIM Master DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_MASTER_DMA + bool "HRTIM MASTER DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_MASTER_IRQ + bool "HRTIM MASTER Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +endmenu # "HRTIM Master Configuration" + +menu "HRTIM Timer A Configuration" + depends on STM32_HRTIM_TIMA + +config STM32_HRTIM_TIMA_CAP + bool "HRTIM TIMA Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMA_DAC + bool "HRTIM TIMA DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMA_DMA + bool "HRTIM TIMA DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMA_IRQ + bool "HRTIM TIMA Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMA_PWM + bool "HRTIM TIMA PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMA_PWM_CH1 + bool "HRTIM TIMA PWM Output 1" + default n + depends on STM32_HRTIM_TIMA_PWM + +config STM32_HRTIM_TIMA_PWM_CH2 + bool "HRTIM TIMA PWM Output 2" + default n + depends on STM32_HRTIM_TIMA_PWM + +config STM32_HRTIM_TIMA_BURST + bool "HRTIM TIMA Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_BURST_CH1 + bool "HRTIM TIMA Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) + +config STM32_HRTIM_TIMA_BURST_CH2 + bool "HRTIM TIMA Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) + +config STM32_HRTIM_TIMA_CHOP + bool "HRTIM TIMA PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_DT + bool "HRTIM TIMA PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_PSHPLL + bool "HRTIM TIMA PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) + +endmenu # "HRTIM Timer A Configuration" + +menu "HRTIM Timer B Configuration" + depends on STM32_HRTIM_TIMB + +config STM32_HRTIM_TIMB_CAP + bool "HRTIM TIMB Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMB_DAC + bool "HRTIM TIMB DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMB_DMA + bool "HRTIM TIMB DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMB_IRQ + bool "HRTIM TIMB Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMB_PWM + bool "HRTIM TIMB PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMB_PWM_CH1 + bool "HRTIM TIMB PWM Output 1" + default n + depends on STM32_HRTIM_TIMB_PWM + +config STM32_HRTIM_TIMB_PWM_CH2 + bool "HRTIM TIMB PWM Output 2" + default n + depends on STM32_HRTIM_TIMB_PWM + +config STM32_HRTIM_TIMB_BURST + bool "HRTIM TIMB Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_BURST_CH1 + bool "HRTIM TIMB Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) + +config STM32_HRTIM_TIMB_BURST_CH2 + bool "HRTIM TIMB Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) + +config STM32_HRTIM_TIMB_CHOP + bool "HRTIM TIMB PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_DT + bool "HRTIM TIMB PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_PSHPLL + bool "HRTIM TIMB PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) + +endmenu # "HRTIM Timer B Configuration" + +menu "HRTIM Timer C Configuration" + depends on STM32_HRTIM_TIMC + +config STM32_HRTIM_TIMC_CAP + bool "HRTIM TIMC Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMC_DAC + bool "HRTIM TIMC DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMC_DMA + bool "HRTIM TIMC DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMC_IRQ + bool "HRTIM TIMC Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMC_PWM + bool "HRTIM TIMC PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMC_PWM_CH1 + bool "HRTIM TIMC PWM Output 1" + default n + depends on STM32_HRTIM_TIMC_PWM + +config STM32_HRTIM_TIMC_PWM_CH2 + bool "HRTIM TIMC PWM Output 2" + default n + depends on STM32_HRTIM_TIMC_PWM + +config STM32_HRTIM_TIMC_BURST + bool "HRTIM TIMC Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_BURST_CH1 + bool "HRTIM TIMC Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) + +config STM32_HRTIM_TIMC_BURST_CH2 + bool "HRTIM TIMC Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) + +config STM32_HRTIM_TIMC_CHOP + bool "HRTIM TIMC PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_DT + bool "HRTIM TIMC PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_PSHPLL + bool "HRTIM TIMC PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) + +endmenu # "HRTIM Timer C Configuration" + +menu "HRTIM Timer D Configuration" + depends on STM32_HRTIM_TIMD + +config STM32_HRTIM_TIMD_CAP + bool "HRTIM TIMD Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMD_DAC + bool "HRTIM TIMD DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMD_DMA + bool "HRTIM TIMD DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMD_IRQ + bool "HRTIM TIMD Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMD_PWM + bool "HRTIM TIMD PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMD_PWM_CH1 + bool "HRTIM TIMD PWM Output 1" + default n + depends on STM32_HRTIM_TIMD_PWM + +config STM32_HRTIM_TIMD_PWM_CH2 + bool "HRTIM TIMD PWM Output 2" + default n + depends on STM32_HRTIM_TIMD_PWM + +config STM32_HRTIM_TIMD_BURST + bool "HRTIM TIMD Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_BURST_CH1 + bool "HRTIM TIMD Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) + +config STM32_HRTIM_TIMD_BURST_CH2 + bool "HRTIM TIMD Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) + +config STM32_HRTIM_TIMD_CHOP + bool "HRTIM TIMD PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_DT + bool "HRTIM TIMD PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_PSHPLL + bool "HRTIM TIMD PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) + +endmenu # "HRTIM Timer D Configuration" + +menu "HRTIM Timer E Configuration" + depends on STM32_HRTIM_TIME + +config STM32_HRTIM_TIME_CAP + bool "HRTIM TIME Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIME_DAC + bool "HRTIM TIME DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIME_DMA + bool "HRTIM TIME DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIME_IRQ + bool "HRTIM TIME Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIME_PWM + bool "HRTIM TIME PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIME_PWM_CH1 + bool "HRTIM TIME PWM Output 1" + default n + depends on STM32_HRTIM_TIME_PWM + +config STM32_HRTIM_TIME_PWM_CH2 + bool "HRTIM TIME PWM Output 2" + default n + depends on STM32_HRTIM_TIME_PWM + +config STM32_HRTIM_TIME_BURST + bool "HRTIM TIME Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_BURST_CH1 + bool "HRTIM TIME Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) + +config STM32_HRTIM_TIME_BURST_CH2 + bool "HRTIM TIME Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) + +config STM32_HRTIM_TIME_CHOP + bool "HRTIM TIME PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_DT + bool "HRTIM TIME PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_PSHPLL + bool "HRTIM TIME PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) + +endmenu # "HRTIM Timer E Configuration" diff --git a/arch/arm/src/common/stm32/Kconfig.i2c b/arch/arm/src/common/stm32/Kconfig.i2c new file mode 100644 index 00000000000..e3af19f3c7b --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.i2c @@ -0,0 +1,313 @@ +# +# STM32 I2C configuration options. +# + +# TODO: generalize H5 specific options ! + +config STM32_I2C_SLAVE + bool + default n + +menu "I2C Configuration H5-specific" + depends on STM32_HAVE_I2C_H5 + +menu "Clock Selection" + +choice + depends on STM32_I2C1 + prompt "I2C1 Input Clock Selection" + default STM32_I2C1_CLK_PCLK1 + +config STM32_I2C1_CLK_CSI + bool "CSI" + +config STM32_I2C1_CLK_HSI + bool "HSI" + +config STM32_I2C1_CLK_PCLK1 + bool "PCLK1" + +config STM32_I2C1_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C1 Input Clock Selection + +choice + depends on STM32_I2C2 + prompt "I2C2 Input Clock Selection" + default STM32_I2C2_CLK_PCLK1 + +config STM32_I2C2_CLK_CSI + bool "CSI" + +config STM32_I2C2_CLK_HSI + bool "HSI" + +config STM32_I2C2_CLK_PCLK1 + bool "PCLK1" + +config STM32_I2C2_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C2 Input Clock Selection + +choice + depends on STM32_I2C3 + prompt "I2C3 Input Clock Selection" + default STM32_I2C3_CLK_PCLK3 + +config STM32_I2C3_CLK_CSI + bool "CSI" + +config STM32_I2C3_CLK_HSI + bool "HSI" + +config STM32_I2C3_CLK_PCLK3 + bool "PCLK3" + +config STM32_I2C3_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C3 Input Clock Selection + +choice + depends on STM32_I2C4 + prompt "I2C4 Input Clock Selection" + default STM32_I2C4_CLK_PCLK3 + +config STM32_I2C4_CLK_CSI + bool "CSI" + +config STM32_I2C4_CLK_HSI + bool "HSI" + +config STM32_I2C4_CLK_PCLK3 + bool "PCLK3" + +config STM32_I2C4_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C4 Input Clock Selection + +endmenu # Clock Selection + +menu "Rise/Fall Override" + +config STM32_I2C1_RF_OVERRIDE + bool "I2C1" + default n + depends on STM32_I2C1 + +config STM32_I2C2_RF_OVERRIDE + bool "I2C2" + default n + depends on STM32_I2C2 + +config STM32_I2C3_RF_OVERRIDE + bool "I2C3" + default n + depends on STM32_I2C3 + +config STM32_I2C4_RF_OVERRIDE + bool "I2C4" + default n + depends on STM32_I2C4 + +menu "Rise/Fall Values" + +config STM32_I2C1_RISE + int "I2C1 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C1_RF_OVERRIDE + +config STM32_I2C1_FALL + int "I2C1 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C1_RF_OVERRIDE + +config STM32_I2C2_RISE + int "I2C2 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C2_RF_OVERRIDE + +config STM32_I2C2_FALL + int "I2C2 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C2_RF_OVERRIDE + +config STM32_I2C3_RISE + int "I2C3 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C3_RF_OVERRIDE + +config STM32_I2C3_FALL + int "I2C3 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C3_RF_OVERRIDE + +config STM32_I2C4_RISE + int "I2C4 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C4_RF_OVERRIDE + +config STM32_I2C4_FALL + int "I2C4 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C4_RF_OVERRIDE + +endmenu # Rise/Fall Values + +endmenu # Rise/Fall Override + +menu "Filtering" + +menu "Digital Filters" + +config STM32_I2C1_DNF + int "I2C1 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C1 + +config STM32_I2C2_DNF + int "I2C2 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C2 + +config STM32_I2C3_DNF + int "I2C3 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C3 + +config STM32_I2C4_DNF + int "I2C4 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C4 + +endmenu # Digital Filters + +menu "Analog Filters" + +config STM32_I2C1_ANFOFF + int "Turn off I2C1 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C1 + +config STM32_I2C2_ANFOFF + int "Turn off I2C2 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C2 + +config STM32_I2C3_ANFOFF + int "Turn off I2C3 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C3 + +config STM32_I2C4_ANFOFF + int "Turn off I2C4 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C4 + +endmenu # Analog Filters + +endmenu # Filtering + +endmenu # "I2C Configuration" + +if !STM32_HAVE_I2C_H5 + +config STM32_I2C_DYNTIMEO + bool "Use dynamic timeouts" + depends on STM32_I2C + +config STM32_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + depends on STM32_I2C && STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + depends on STM32_I2C && STM32_I2C_DYNTIMEO + default 1000 + +config STM32_I2CTIMEOSEC + int "Timeout seconds" + depends on STM32_I2C + default 0 + +config STM32_I2CTIMEOMS + int "Timeout Milliseconds" + depends on STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + depends on STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_ALT + bool "Alternate I2C implementation" + default STM32F1_PERFORMANCELINE + depends on !STM32_STM32F30XX && STM32_COMMON_LEGACY + ---help--- + This selection enables an alternative I2C driver. This alternate + driver implements some rather complex workarounds for errata against + the STM32 F103 "Performance Line". This selection is an option + because: (1) It has not yet been fully verified and (2) It is not + certain that he scope of this workaround is needed only for the F103. + +config STM32_I2C_DUTY16_9 + bool "Frequency with Tlow/Thigh = 16/9" + default n + depends on STM32_I2C && STM32_COMMON_LEGACY + +config STM32_I2C_DMA + bool "I2C DMA Support" + default n + depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED + ---help--- + This option enables the DMA for I2C transfers. + Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the + I2C dma streams, else the default priority level is set to medium. + +menu "I2C Slave Configuration" + depends on STM32_I2C_SLAVE + +config STM32_I2C_SLAVE_DEFAULT_TX + hex "Default TX byte to be sent when the TX buffer is empty" + default 0xFF + +config STM32_I2C_SLAVE_USEWQ + bool "Use work queue to delegate the isr completion status" + default n + ---help--- + With the current upperhalf I2C slave driver implementation, the user + should delegate the callback completion status using a work queue. + However, work queues introduce a delay, so in certain scenarios + it is better to use a custom driver without using a work queue. + +config STM32_I2C_SLAVE_RETRANSFER + bool "The frame is retransferred when stop is issued beforehand" + default n + ---help--- + If stop is issued before the whole frame is transferred, + the tx pointer is reset to 0. + +endmenu + +endif # !STM32_HAVE_I2C_H5 \ No newline at end of file diff --git a/arch/arm/src/common/stm32/Kconfig.ipcc b/arch/arm/src/common/stm32/Kconfig.ipcc new file mode 100644 index 00000000000..da34bba96d2 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ipcc @@ -0,0 +1,91 @@ +# +# STM32 common IPCC options. +# + +config STM32_IPCC_CHAN1_RX_SIZE + int "Channel 1 RX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the receive buffer. Another CPU will write to this buffer and + the currently running CPU will read from it. + +config STM32_IPCC_CHAN1_TX_SIZE + int "Channel 1 TX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the send buffer. Another CPU will read from this buffer and + the currently running CPU will write to it. + +config STM32_IPCC_CHAN2 + bool "Enable channel 2" + depends on STM32_IPCC + +if STM32_IPCC_CHAN2 + +config STM32_IPCC_CHAN2_RX_SIZE + int "Channel 2 RX size" + default 256 + +config STM32_IPCC_CHAN2_TX_SIZE + int "Channel 2 TX size" + default 256 + +config STM32_IPCC_CHAN3 + bool "Enable channel 3" + +if STM32_IPCC_CHAN3 + +config STM32_IPCC_CHAN3_RX_SIZE + int "Channel 3 RX size" + default 256 + +config STM32_IPCC_CHAN3_TX_SIZE + int "Channel 3 TX size" + default 256 + +config STM32_IPCC_CHAN4 + bool "Enable channel 4" + +if STM32_IPCC_CHAN4 + +config STM32_IPCC_CHAN4_RX_SIZE + int "Channel 4 RX size" + default 256 + +config STM32_IPCC_CHAN4_TX_SIZE + int "Channel 4 TX size" + default 256 + +config STM32_IPCC_CHAN5 + bool "Enable channel 5" + +if STM32_IPCC_CHAN5 + +config STM32_IPCC_CHAN5_RX_SIZE + int "Channel 5 RX size" + default 256 + +config STM32_IPCC_CHAN5_TX_SIZE + int "Channel 5 TX size" + default 256 + +config STM32_IPCC_CHAN6 + bool "Enable channel 6" + +if STM32_IPCC_CHAN6 + +config STM32_IPCC_CHAN6_RX_SIZE + int "Channel 6 RX size" + default 256 + +config STM32_IPCC_CHAN6_TX_SIZE + int "Channel 6 TX size" + default 256 + +endif # STM32_IPCC_CHAN2 +endif # STM32_IPCC_CHAN3 +endif # STM32_IPCC_CHAN4 +endif # STM32_IPCC_CHAN5 +endif # STM32_IPCC_CHAN6 diff --git a/arch/arm/src/common/stm32/Kconfig.lpuart b/arch/arm/src/common/stm32/Kconfig.lpuart new file mode 100644 index 00000000000..98f5c9f83ca --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.lpuart @@ -0,0 +1,69 @@ +# +# STM32 common LPUART options. +# + +config LPUART1_RXDMA + bool + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +choice + prompt "LPUART1 Driver Configuration" + depends on STM32_LPUART1 + default STM32_LPUART1_SERIALDRIVER + +config STM32_LPUART1_SERIALDRIVER + bool "Standard serial driver" + select LPUART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_LPUART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # LPUART1 Driver Configuration + +config LPUART1_RS485 + bool "RS-485 on LPUART1" + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on LPUART1. Your board config will have to + provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be + used with LPUART1_RXDMA. + +if LPUART1_RS485 + +config LPUART1_RS485_DIR_POLARITY + int "LPUART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # LPUART1_RS485 + +if STM32_LPUART1_SERIALDRIVER + +config LPUART1_TXDMA + bool "LPUART1 Tx DMA" + default n + depends on STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +endif # STM32_LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure LPUART1 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure LPUART1 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure LPUART1 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 diff --git a/arch/arm/src/common/stm32/Kconfig.ltdc b/arch/arm/src/common/stm32/Kconfig.ltdc new file mode 100644 index 00000000000..27d3d9c1b76 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ltdc @@ -0,0 +1,233 @@ +# +# STM32 common LTDC options. +# + +choice + prompt "Layer 1 color format" + depends on STM32_LTDC + default STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L1_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_RGB565 + bool "16 bpp RGB 565" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB4444 + bool "16 bpp ARGB 4444" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB1555 + bool "16 bpp ARGB 1555" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_RGB888 + bool "24 bpp RGB 888" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB8888 + bool "32 bpp ARGB 8888" + depends on !STM32_FB_CMAP + +endchoice # Layer 1 color format + +choice + prompt "Layer 2 (top layer) color format" + depends on STM32_LTDC && STM32_LTDC_L2 + default STM32_LTDC_L2_RGB565 + +config STM32_LTDC_L2_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_LTDC_L1_L8 + +config STM32_LTDC_L2_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_LTDC_L1_AL44 + +config STM32_LTDC_L2_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_LTDC_L1_AL88 + +config STM32_LTDC_L2_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L2_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + +config STM32_LTDC_L2_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB1555 + +config STM32_LTDC_L2_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + +config STM32_LTDC_L2_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + +endchoice # Layer 2 color format + +if STM32_LTDC + +config STM32_LTDC_BACKLIGHT + bool "Backlight support" + default y + +config STM32_LTDC_DEFBACKLIGHT + hex "Default backlight level" + default 0xf0 + +config STM32_LTDC_BACKCOLOR + hex "Background color" + default 0x0 + ---help--- + This is the background color that will be used as the LTDC + background layer color. It is an RGB888 format value. + +config STM32_LTDC_DITHER + bool "Dither support" + +config STM32_LTDC_FB_DOUBLE_BUFFER + bool "Enable double buffering" + depends on ARCH_CHIP_STM32H7 + default n + ---help--- + Enable double buffering to allow updates to the framebuffer while + the display is being refreshed. This configuration requires two + framebuffers: one active and one inactive. When the display + refreshes, the active and inactive framebuffers are swapped, + enabling smooth and flicker-free updates. + +if STM32_LTDC_DITHER + +config STM32_LTDC_DITHER_RED + int "Dither red width" + range 0 7 + default 2 + ---help--- + This is the dither red width. + +config STM32_LTDC_DITHER_GREEN + int "Dither green width" + range 0 7 + default 2 + ---help--- + This is the dither green width. + +config STM32_LTDC_DITHER_BLUE + int "Dither blue width" + range 0 7 + default 2 + ---help--- + This is the dither blue width. + +endif # STM32_LTDC_DITHER + +config STM32_LTDC_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the LTDC, then you must provide the address + of the start of the framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_LTDC_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of the active LTDC layer. + +config STM32_LTDC_L1_CHROMAKEYEN + bool "Enable chromakey support for layer 1" + default y + +config STM32_LTDC_L1_CHROMAKEY + hex "Layer L1 initial chroma key" + default 0x00000000 + +config STM32_LTDC_L1_COLOR + hex "Layer L1 default color" + default 0x00000000 + +config STM32_LTDC_L2 + bool "Enable Layer 2 support" + default y + +if STM32_LTDC_L2 + +config STM32_LTDC_L2_COLOR + hex "Layer L2 default color" + default 0x00000000 + +config STM32_LTDC_L2_CHROMAKEYEN + bool "Enable chromakey support for layer 2" + default y + +config STM32_LTDC_L2_CHROMAKEY + hex "Layer L2 initial chroma key" + default 0x00000000 + +endif # STM32_LTDC_L2 + +config STM32_FB_CMAP + bool "Color map support" + default y + select FB_CMAP + ---help--- + Enabling color map support is necessary for LTDC L8 format. + +config STM32_FB_TRANSPARENCY + bool "Transparency color map support" + depends on STM32_FB_CMAP + default y + select FB_TRANSPARENCY + ---help--- + Enabling transparency color map support is necessary for LTDC L8 format. + +config STM32_LTDC_REGDEBUG + bool "LTDC Register level debug" + depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 + ---help--- + Output detailed register-level LTDC device debug information. + +endif # STM32_LTDC + +config STM32_LTDC_USE_DSI + bool "Use DSI as display connection" + depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST + ---help--- + Select this if your display is connected via DSI. + Deselect option if your display is connected via digital + RGB+HSYNC+VSYNC + +if STM32_LCD + +choice + prompt "Segment LCD Clock Source" + default LCD_LSECLOCK + +config LCD_LSICLOCK + bool "Internal Low Speed Clock" + +config LCD_LSECLOCK + bool "External Low Speed Clock" + +config LCD_HSECLOCK + bool "External High Speed Clock" + +endchoice + +endif # STM32_LCD diff --git a/arch/arm/src/common/stm32/Kconfig.memory b/arch/arm/src/common/stm32/Kconfig.memory new file mode 100644 index 00000000000..7ab6138be10 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.memory @@ -0,0 +1,168 @@ +# +# STM32 memory configuration options. +# + +config STM32_SRAM5_HEAP + bool "SRAM5 is used for heap" + depends on STM32_SRAM5 + default n + +config STM32_EXTERNAL_RAM + bool "External RAM on FSMC/FMC" + depends on STM32_FSMC || STM32_FMC + select ARCH_HAVE_HEAP2 + ---help--- + In addition to internal SRAM, external RAM may be available through the FSMC/FMC. + +config STM32_BBSRAM_FILES + int "Max Files to support in BBSRAM" + depends on STM32_BBSRAM + default 4 + +config STM32_SAVE_CRASHDUMP + bool "Enable Saving Panic to BBSRAM" + depends on STM32_BBSRAM + +config STM32_DTCMEXCLUDE + bool "Exclude DTCM SRAM from the heap" + depends on ARMV7M_HAVE_DTCM + default LIBC_ARCH_ELF + ---help--- + Exclude DTCM SRAM from the HEAP because it appears to be impossible + to execute ELF modules from DTCM RAM (REVISIT!). + +config STM32_DTCM_PROCFS + bool "DTCM SRAM PROCFS support" + depends on ARMV7M_DTCM && FS_PROCFS + ---help--- + Select to build in support for /proc/dtcm. Reading from /proc/dtcm + will provide statistics about DTCM memory use similar to what you + would get from mallinfo() for the user heap. + +config STM32_SRAM2_HEAP + bool "SRAM2 is used for heap" + depends on STM32_COMMON_SRAM2_OPTIONS + select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 + ---help--- + The STM32L4 SRAM2 region has special properties (power, protection, parity) + which may be used by the application for special purposes. But if these + special properties are not needed, it may be instead added to the heap for + use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_SRAM2_INIT + bool "SRAM2 is initialized to zero" + depends on STM32_COMMON_SRAM2_OPTIONS + ---help--- + The STM32L4 SRAM2 region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2 is being used for it's battery-backed capability, + this may be undesirable (because it will destroy the contents). In that + case, the board should handle the initialization itself at the appropriate + time. + +config STM32_SRAM3_HEAP + bool "SRAM3 is used for heap" + depends on STM32_SRAM3 + default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR + ---help--- + Add the STM32L4 SRAM3 to the heap for use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_CCMEXCLUDE + bool "Exclude CCM SRAM from the heap" + default ARCH_DMA || LIBC_ARCH_ELF + depends on STM32_HAVE_CCM + ---help--- + Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA + and (2) it appears to be impossible to execute ELF modules from CCM + RAM. + +config STM32_CCM_PROCFS + bool "CCM PROCFS support" + default n + depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER + ---help--- + Select to build in support for /proc/ccm. Reading from /proc/ccm + will provide statistics about CCM memory use similar to what you + would get from mallinfo() for the user heap. + +comment "STM32WB SRAM2a and SRAM2b Options" + depends on STM32_HAVE_SRAM2A || STM32_HAVE_SRAM2B + +config STM32_SRAM2A_HEAP + bool "SRAM2a is used for heap" + depends on STM32_HAVE_SRAM2A + default n + +config STM32_SRAM2A_USER_BASE_OFFSET + int "SRAM2a user application base offset" + default 2048 + range 0 32768 + depends on STM32_SRAM2A_HEAP + ---help--- + The beginning part of the SRAM2a memory can be used by RF stack. The + available space for the user application can be obtained from the + release notes for STM32WB coprocessor wireless binaries. + +config STM32_SRAM2A_USER_SIZE + int "SRAM2a user application size" + default 8192 + range 0 32768 + depends on STM32_SRAM2A_HEAP + ---help--- + The ending part of the SRAM2a memory contains a secure section, which + cannot be read nor written by CPU1. The secure start address for the + SRAM2a memory can be read from the SBRSA option byte. When CPU2 update + support required, there must be some free sectors just below the secure + memory to support CPU2 firmware updates requiring more sectors to be + secure. + +config STM32_SRAM2A_INIT + bool "SRAM2a is initialized to zero" + default y + depends on STM32_SRAM2A_HEAP + ---help--- + The STM32WB SRAM2a region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2a is being retained in Standby mode, this may be + undesirable (because it will destroy the contents). In that case, the board + should handle the initialization itself at the appropriate time. + +config STM32_SRAM2B_HEAP + bool "SRAM2b is used for heap" + depends on STM32_HAVE_SRAM2B + default n + +config STM32_SRAM2B_USER_SIZE + int "SRAM2b user application size" + default 32768 + range 0 32768 + depends on STM32_SRAM2B_HEAP + ---help--- + For any CPU2 firmware supporting the BLE protocol the ending part of + the SRAM2b memory contains a secure section, which cannot be read nor + written by CPU1. The secure start address for the SRAM2b memory can be + read from the SNBRSA option byte. When CPU2 update support required, + there must be some free sectors just below the secure memory to support + CPU2 firmware updates requiring more sectors to be secure. The SRAM2b + memory is all secure for any CPU2 firmware supporting the Thread protocol. + +config STM32_SRAM2B_INIT + bool "SRAM2b is initialized to zero" + default y + depends on STM32_SRAM2B_HEAP + ---help--- + The STM32WB SRAM2b region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. diff --git a/arch/arm/src/common/stm32/Kconfig.periph b/arch/arm/src/common/stm32/Kconfig.periph new file mode 100644 index 00000000000..5df4ec848c8 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.periph @@ -0,0 +1,1282 @@ +# +# STM32 common peripheral selection options. +# + +menu "STM32 Peripheral Support" + +config STM32_OPAMP + bool + depends on STM32_HAVE_IP_OPAMP_M3M4_V1 + select STM32_SYSCFG + +config STM32_COMP + bool + depends on STM32_HAVE_COMP + select STM32_SYSCFG + select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP + +config STM32_ADC + bool + +config STM32_SDADC + bool + default n + +config STM32_CAN + bool + +config STM32_FDCAN + bool + select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 + select NET_CAN_EXTID if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 + +config STM32_DAC + bool + +config STM32_DMA + bool + select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + select STM32_DMAMUX if ARCH_CHIP_STM32WB + +config STM32_DMAMUX + bool + +config STM32_I2C + bool + +config STM32_SPI + bool + +config STM32_TIM + bool + +config STM32_LPTIM + bool + +config STM32_HRTIM + bool + +config STM32_USART + bool + +config STM32_SERIALDRIVER + bool + +config STM32_SAI + bool + +config STM32_I2S + bool + select STM32_SPI_DMA if STM32_COMMON_LEGACY + select STM32_SPI_DMA if ARCH_CHIP_STM32F7 + +config STM32_SDMMC + bool + +config STM32_DFSDM + bool + default n + +config STM32_MBOX + bool + depends on STM32_HAVE_MBOX + default n + select STM32_IPCC + +# DMA peripherals + +config STM32_MDMA + bool "MDMA" + default n + depends on STM32_HAVE_MDMA && EXPERIMENTAL + select STM32_DMA + select ARCH_DMA + +config STM32_BDMA + bool "BDMA" + default n + depends on STM32_HAVE_BDMA && EXPERIMENTAL + select STM32_DMA + select ARCH_DMA + +config STM32_GPADMA1 + depends on STM32_HAVE_GPADMA1 + bool "GPADMA1" + default n + +config STM32_LPDMA1 + depends on STM32_HAVE_LPDMA1 + bool "LPDMA1" + default n + +config STM32_DMA1 + bool "DMA1" + depends on STM32_HAVE_DMA1 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMA2 + bool "DMA2" + depends on STM32_HAVE_DMA2 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMAMUX1 + bool "DMAMUX1" + depends on STM32_HAVE_DMAMUX + select STM32_DMAMUX + +config STM32_DMA2D + bool "DMA2D" + depends on STM32_HAVE_DMA2D + select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32F429 and STM32F439 devices. + +# CLOCK peripherals + +config STM32_CSI + bool "CSI Low-speed internal oscillator (4MHz)" + depends on STM32_HAVE_CSI + default n + +config STM32_HSI48 + bool "HSI48 High-speed 48MHz internal oscillator" + depends on STM32_HAVE_HSI48 + default n + +config STM32_CRS + bool "CRS (Clock Recovery System)" + depends on STM32_HAVE_CRS + +# POWER peripherals + +config STM32_VREF + depends on STM32_HAVE_VREF + bool "VREF" + default n + +config STM32_BKPSRAM + bool "Enable BKP RAM Domain" + depends on STM32_HAVE_BKPSRAM + select STM32_PWR if ARCH_CHIP_STM32H7 + +config STM32_VREFINT + bool "Enable VREFINT" + depends on STM32_HAVE_VREFINT + +config STM32_PWR + bool "PWR" + depends on STM32_HAVE_PWR + +# MEMORY peripherals + +config STM32_RAMCFG + depends on STM32_HAVE_RAMCFG + bool "RAMCFG" + default n + +config STM32_SRAM1 + depends on STM32_HAVE_SRAM1 + bool "SRAM1" + default y + +config STM32_SRAM2 + depends on STM32_HAVE_SRAM2 + bool "SRAM2" + default n + +config STM32_SRAM3 + bool "SRAM3" + default n + depends on STM32_HAVE_SRAM3 && (STM32_STM32U575XX || STM32_STM32U585XX || STM32_STM32U59XX || STM32_STM32U59AXX || \ + STM32_STM32U5A5XX || STM32_STM32U5A9XX) + +config STM32_SRAM5 + bool "SRAM5" + default n + depends on STM32_HAVE_SRAM5 && (STM32_STM32U575XX || STM32_STM32U585XX || STM32_STM32U59XX || STM32_STM32U59AXX || \ + STM32_STM32U5A5XX || STM32_STM32U5A9XX) + +config STM32_BKP + bool "BKP" + depends on STM32_HAVE_BKP + +config STM32_FSMC + bool "FSMC" + depends on STM32_HAVE_FSMC + +config STM32_FMC + bool "FMC" + depends on STM32_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. + +config STM32_BBSRAM + bool "BBSRAM File Support" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM + select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM + +config STM32_CCMDATARAM + bool "CMD/DATA RAM" + default n + depends on STM32_STM32F4XXX + +# FLASH peripherals + +config STM32_FLASH + depends on STM32_HAVE_FLASH + bool "FLASH" + default n + +# GPIO peripherals + +config STM32_LPGPIO1 + depends on STM32_HAVE_LPGPIO1 + bool "LPGPIO1" + default n + +config STM32_SYSCFG + bool "SYSCFG" + depends on STM32_HAVE_SYSCFG + default y + +# SECURITY peripherals + +config STM32_FIREWALL + bool "FIREWALL" + default y + depends on STM32_HAVE_FIREWALL && STM32_SYSCFG + +config STM32_GTZC1 + depends on STM32_HAVE_GTZC1 + bool "GTZC1" + default n + +config STM32_GTZC2 + depends on STM32_HAVE_GTZC2 + bool "GTZC2" + default n + +config STM32_PKA + depends on STM32_HAVE_PKA + bool "PKA" + default n + +config STM32_SAES + depends on STM32_HAVE_SAES + bool "SAES" + default n + +config STM32_OTFDEC1 + depends on STM32_HAVE_OTFDEC1 + bool "OTFDEC1" + default n + +config STM32_OTFDEC2 + depends on STM32_HAVE_OTFDEC2 + bool "OTFDEC2" + default n + +config STM32_CRC + bool "CRC" + depends on STM32_HAVE_CRC + +config STM32_AES + bool "128-bit AES" + depends on STM32_HAVE_IP_AES_M0_V1 || STM32_HAVE_IP_AES_M3M4_V1 + select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + +config STM32_CRYP + bool "CRYP" + depends on STM32_HAVE_CRYP + depends on STM32_HAVE_IP_CRYPTO_M3M4_V1 || STM32_HAVE_IP_CRYPTO_H7 + +config STM32_HASH + bool "HASH" + depends on STM32_HAVE_HASH + select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH + +# BLE peripherals + +menuconfig STM32_BLE + bool "BLE" + depends on STM32_HAVE_BLE + default n + select STM32_MBOX + ---help--- + Enable BLE support. + +# CACHE peripherals + +config STM32_ICACHE + bool "ICACHE" + default n + depends on STM32_HAVE_ICACHE + +config STM32_DCACHE1 + depends on STM32_HAVE_DCACHE1 + bool "DCACHE1" + default n + +# RTC peripherals + +config STM32_RTCAPB + depends on STM32_HAVE_RTCAPB + bool "RTCAPB" + default n + +config STM32_RTC + bool "RTC" + depends on STM32_HAVE_RTC + select RTC if !ARCH_CHIP_STM32L5 + +# RNG peripherals + +config STM32_RNG + bool "RNG" + depends on STM32_HAVE_RNG + select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 + +# WDG peripherals + +config STM32_IWDG + bool "IWDG" + depends on STM32_HAVE_IP_WDG_M0_V1 || STM32_HAVE_IP_WDG_M3M4_V1 + select WATCHDOG + +config STM32_WWDG + bool "WWDG" + depends on STM32_HAVE_IP_WDG_M0_V1 || STM32_HAVE_IP_WDG_M3M4_V1 + select WATCHDOG if !ARCH_CHIP_STM32U5 + +# ADC peripherals + +config STM32_ADC1 + bool "ADC1" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + select STM32_ADC if !ARCH_CHIP_STM32U5 + select STM32_ADC1_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC1_HAVE_DMA if ARCH_CHIP_STM32F7 + select STM32_ADC1_HAVE_DMA if STM32_HAVE_IP_ADC_M0_V1 + select STM32_ADC1_HAVE_DMA if STM32_STM32F30XX || STM32_STM32F33XX + +config STM32_ADC2 + bool "ADC2" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 + select STM32_ADC + select STM32_ADC2_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC2_HAVE_DMA if ARCH_CHIP_STM32F7 + select STM32_ADC2_HAVE_DMA if STM32_STM32F302 || STM32_STM32F303 || STM32_STM32F33XX + +config STM32_ADC3 + bool "ADC3" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 + select STM32_ADC + select STM32_ADC3_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC3_HAVE_DMA if ARCH_CHIP_STM32F7 + +config STM32_ADC4 + bool "ADC4" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 + select STM32_ADC if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) + select STM32_ADC4_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_ADC5 + bool "ADC5" + default n + select STM32_ADC + depends on STM32_HAVE_ADC5 + select STM32_ADC5_HAVE_DMA if STM32_DMA2 + select STM32_ADC5_HAVE_DMA if STM32_DMAMUX + +config STM32_SDADC1 + bool "SDADC1" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC1 + select STM32_SDADC1_HAVE_DMA if STM32_DMA2 + +config STM32_SDADC2 + bool "SDADC2" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC2 + select STM32_SDADC2_HAVE_DMA if STM32_DMA2 + +config STM32_SDADC3 + bool "SDADC3" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC3 + select STM32_SDADC3_HAVE_DMA if STM32_DMA2 + +# DAC peripherals + +config STM32_DAC1 + bool "DAC1" + depends on STM32_HAVE_DAC1 + select STM32_DAC if !ARCH_CHIP_STM32U5 + +config STM32_DAC2 + bool "DAC2" + depends on STM32_HAVE_DAC2 + select STM32_DAC + +config STM32_DAC1CH1 + bool "DAC1CH1" + default n + depends on STM32_DAC1 + +config STM32_DAC1CH2 + bool "DAC1CH2" + default n + depends on STM32_DAC1 + +config STM32_DAC2CH1 + bool "DAC2CH1" + default n + depends on STM32_DAC2 + +config STM32_DAC3 + bool "DAC3" + default n + depends on STM32_HAVE_DAC3 + select STM32_DAC + +config STM32_DAC3CH1 + bool "DAC3CH1 Internal" + default n + depends on STM32_DAC3 + +config STM32_DAC3CH2 + bool "DAC3CH2 Internal" + default n + depends on STM32_DAC3 + +config STM32_DAC4 + bool "DAC4" + default n + depends on STM32_HAVE_DAC4 + select STM32_DAC + +config STM32_DAC4CH1 + bool "DAC4CH1 Internal" + default n + depends on STM32_DAC4 + +config STM32_DAC4CH2 + bool "DAC4CH2 Internal" + default n + depends on STM32_DAC4 + +# DFSDM peripherals + +config STM32_MDF1 + depends on STM32_HAVE_MDF1 + bool "MDF1" + default n + +config STM32_ADF1 + depends on STM32_HAVE_ADF1 + bool "ADF1" + default n + +config STM32_DFSDM1 + bool "DFSDM1" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 + +# CAN peripherals + +config STM32_CAN1 + bool "CAN1" + depends on STM32_HAVE_CAN1 + select STM32_CAN + select CAN + +config STM32_CAN2 + bool "CAN2" + depends on STM32_HAVE_CAN2 + select STM32_CAN + select CAN + +config STM32_CAN3 + bool "CAN3" + depends on STM32_HAVE_CAN3 + select STM32_CAN + select CAN + +config STM32_FDCAN1 + bool "FDCAN1" + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN if !ARCH_CHIP_STM32U5 + +config STM32_FDCAN2 + bool "FDCAN2" + depends on STM32_HAVE_FDCAN2 + select STM32_FDCAN + +config STM32_FDCAN3 + bool "FDCAN3" + depends on STM32_HAVE_FDCAN3 + select STM32_FDCAN + +# I2C peripherals + +config STM32_I2C5 + bool "I2C5" + depends on STM32_HAVE_I2C5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX) + default n + select STM32_I2C + +config STM32_I2C6 + bool "I2C6" + depends on STM32_HAVE_I2C6 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX) + default n + select STM32_I2C + +config STM32_I2C1 + bool "I2C1" + depends on STM32_HAVE_I2C1 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB + +config STM32_I2C2 + bool "I2C2" + depends on STM32_HAVE_I2C2 + select STM32_I2C + +config STM32_I2C3 + bool "I2C3" + depends on STM32_HAVE_I2C3 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 + +config STM32_I2C4 + bool "I2C4" + depends on STM32_HAVE_I2C4 + select STM32_I2C + +# +# + +config STM32_I2C1_SLAVE + bool "I2C1 Slave" + default n + depends on !STM32_I2C1 && I2C_SLAVE + select STM32_I2C_SLAVE + +config STM32_I2C2_SLAVE + bool "I2C2 Slave" + default n + depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE + select STM32_I2C_SLAVE + +config STM32_I2C3_SLAVE + bool "I2C3 Slave" + default n + depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE + select STM32_I2C_SLAVE + +# SPI peripherals + +config STM32_SPI1 + bool "SPI1" + depends on STM32_HAVE_SPI1 + select SPI if !ARCH_CHIP_STM32WL5 + select STM32_SPI + +config STM32_SPI2 + bool "SPI2" + depends on STM32_HAVE_SPI2 + select SPI + select STM32_SPI + +config STM32_SPI3 + bool "SPI3" + depends on STM32_HAVE_SPI3 + select SPI + select STM32_SPI + +config STM32_SPI4 + bool "SPI4" + depends on STM32_HAVE_SPI4 + select SPI + select STM32_SPI + +config STM32_SPI5 + bool "SPI5" + depends on STM32_HAVE_SPI5 + select SPI + select STM32_SPI + +config STM32_SPI6 + bool "SPI6" + depends on STM32_HAVE_SPI6 + select SPI + select STM32_SPI + +# SERIAL peripherals + +config STM32_UART9 + bool "UART9" + default n + depends on STM32_HAVE_UART9 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_UART12 + bool "UART12" + default n + depends on STM32_HAVE_UART12 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_USART10 + bool "USART10" + default n + depends on STM32_HAVE_USART10 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_USART11 + bool "USART11" + default n + depends on STM32_HAVE_USART11 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_SWPMI + bool "SWPMI" + depends on STM32_HAVE_SWPMI + default n + +config STM32_LPUART1 + bool "LPUART1" + depends on STM32_HAVE_LPUART1 + select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART + +config STM32_USART4 + bool "USART4" + depends on STM32_HAVE_USART4 + select STM32_USART + +config STM32_USART5 + bool "USART5" + depends on STM32_HAVE_USART5 + select STM32_USART + +config STM32_USART7 + bool "USART7" + depends on STM32_HAVE_USART7 + select STM32_USART + +config STM32_USART8 + bool "USART8" + depends on STM32_HAVE_USART8 + select STM32_USART + +config STM32_USART1 + bool "USART1" + depends on STM32_HAVE_USART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART2 + bool "USART2" + depends on STM32_HAVE_USART2 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART3 + bool "USART3" + depends on STM32_HAVE_USART3 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART4 + bool "UART4" + depends on STM32_HAVE_UART4 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART5 + bool "UART5" + depends on STM32_HAVE_UART5 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART6 + bool "USART6" + depends on STM32_HAVE_USART6 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART7 + bool "UART7" + depends on STM32_HAVE_UART7 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART8 + bool "UART8" + depends on STM32_HAVE_UART8 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 + +# TIM peripherals + +config STM32_LPTIM1 + bool "LPTIM1" + depends on STM32_HAVE_LPTIM1 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_TIM1 + bool "TIM1" + depends on STM32_HAVE_TIM1 + select STM32_TIM + +config STM32_TIM2 + bool "TIM2" + depends on STM32_HAVE_TIM2 + select STM32_TIM + +config STM32_TIM3 + bool "TIM3" + depends on STM32_HAVE_TIM3 + select STM32_TIM + +config STM32_TIM4 + bool "TIM4" + depends on STM32_HAVE_TIM4 + select STM32_TIM + +config STM32_TIM5 + bool "TIM5" + depends on STM32_HAVE_TIM5 + select STM32_TIM + +config STM32_TIM6 + bool "TIM6" + depends on STM32_HAVE_TIM6 + select STM32_TIM + +config STM32_TIM7 + bool "TIM7" + depends on STM32_HAVE_TIM7 + select STM32_TIM + +config STM32_TIM8 + bool "TIM8" + depends on STM32_HAVE_TIM8 + select STM32_TIM + +config STM32_TIM9 + bool "TIM9" + depends on STM32_HAVE_TIM9 + select STM32_TIM + +config STM32_TIM10 + bool "TIM10" + depends on STM32_HAVE_TIM10 + select STM32_TIM + +config STM32_TIM11 + bool "TIM11" + depends on STM32_HAVE_TIM11 + select STM32_TIM + +config STM32_TIM12 + bool "TIM12" + depends on STM32_HAVE_TIM12 + select STM32_TIM + +config STM32_TIM13 + bool "TIM13" + depends on STM32_HAVE_TIM13 + select STM32_TIM + +config STM32_TIM14 + bool "TIM14" + depends on STM32_HAVE_TIM14 + select STM32_TIM + +config STM32_TIM15 + bool "TIM15" + depends on STM32_HAVE_TIM15 + select STM32_TIM + +config STM32_TIM16 + bool "TIM16" + depends on STM32_HAVE_TIM16 + select STM32_TIM + +config STM32_TIM17 + bool "TIM17" + depends on STM32_HAVE_TIM17 + select STM32_TIM + +config STM32_LPTIM2 + bool "LPTIM2" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPTIM3 + bool "LPTIM3" + depends on STM32_HAVE_LPTIM3 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM4 + bool "LPTIM4" + depends on STM32_HAVE_LPTIM4 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM5 + bool "LPTIM5" + depends on ARCH_CHIP_STM32H7 + select STM32_LPTIM + +config STM32_HRTIM1 + bool "HRTIM1" + default n + depends on STM32_HAVE_HRTIM1 + select STM32_HRTIM + +config STM32_HRTIM_MASTER + bool "HRTIM MASTER" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Master Timer + +config STM32_HRTIM_TIMA + bool "HRTIM TIMA" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer A + +config STM32_HRTIM_TIMB + bool "HRTIM TIMB" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer B + +config STM32_HRTIM_TIMC + bool "HRTIM TIMC" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer C + +config STM32_HRTIM_TIMD + bool "HRTIM TIMD" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer D + +config STM32_HRTIM_TIME + bool "HRTIM TIME" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer E + +# USB peripherals + +choice STM32_USBFS_MODE + prompt "USB FS Mode" + depends on STM32_HAVE_USBFS_MODE && STM32_HAVE_USBFS + default STM32_USBFS_NONE + ---help--- + Select the operating mode for the USB_DRD_FS peripheral. + The hardware supports Device or Host, but not simultaneously. + +config STM32_USBFS_NONE + bool "Disabled" + +config STM32_USBFS_DEVICE + bool "USB Device" + select STM32_USBFS + select USBDEV + +config STM32_USBFS_HOST + bool "USB Host" + select USBHOST_HAVE_ASYNCH + select USBHOST + ---help--- + Enable USB host mode for USB_DRD_FS peripheral. + +endchoice + +config STM32_OTGFS + bool "OTG FS" + depends on STM32_HAVE_OTGFS + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGHS + bool "OTG HS" + depends on STM32_HAVE_OTGHS && (!ARCH_CHIP_STM32H7 || EXPERIMENTAL) + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGFSHS + bool "OTG FS/HS" + depends on ARCH_CHIP_STM32F7 + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32_USB + bool "USB Device" + depends on STM32_HAVE_USBDEV + select USBDEV + +config STM32_USBFS + bool "USB Full Speed Device" + depends on STM32_HAVE_USBFS + select USBDEV + select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 + +config STM32_USBHOST + bool "Enable USB Host Support" + depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) + default n + select USBHOST + +config STM32_UCPD + bool "UCPD (USB Type C Power Delivery)" + default n + depends on STM32_HAVE_UCPD + select USBDEV + +config STM32_UCPD1 + depends on STM32_HAVE_UCPD1 + bool "UCPD1" + default n + +# CEC peripherals + +config STM32_CEC + bool "CEC" + depends on STM32_HAVE_CEC + +# SDIO peripherals + +config STM32_SDIO + bool "SDIO" + depends on (STM32_COMMON_LEGACY && !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE) + select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select ARCH_HAVE_SDIO_PREFLIGHT + +config STM32_SDMMC1 + bool "SDMMC1" + depends on STM32_HAVE_SDMMC1 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 + select SCHED_HPWORK if ARCH_CHIP_STM32L4 + select STM32_SAI1PLL if ARCH_CHIP_STM32L4 + +config STM32_SDMMC2 + bool "SDMMC2" + depends on STM32_HAVE_SDMMC2 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 + +# SAI peripherals + +config STM32_SPDIFRX + bool "SPDIFRX" + depends on ARCH_CHIP_STM32F7 + +config STM32_I2S1 + bool "I2S1" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 + select STM32_I2S + +config STM32_I2S2 + bool "I2S2" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 + select STM32_I2S + +config STM32_I2S3 + bool "I2S3" + depends on STM32_HAVE_I2S3 + select I2S if STM32_COMMON_LEGACY + select STM32_I2S + +config STM32_SPI2S2 + bool "SPI2S2" + depends on STM32_HAVE_SPI2S2 + select STM32_SPI + +config STM32_SAI1 + bool "SAI1" + depends on STM32_HAVE_SAI1 + +config STM32_SAI1_A + bool "SAI1 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI1_B + bool "SAI1 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2 + bool "SAI2" + depends on STM32_HAVE_SAI2 + +config STM32_SAI2_A + bool "SAI2 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2_B + bool "SAI2 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +# QSPI peripherals + +config STM32_QSPI1 + bool "QSPI1" + depends on STM32_HAVE_QSPI1 + default n + +config STM32_OCTOSPIM + depends on STM32_HAVE_OCTOSPIM + bool "OCTOSPIM" + default n + +config STM32_OCTOSPI1 + depends on STM32_HAVE_OCTOSPI1 + bool "OCTOSPI1" + default n + +config STM32_OCTOSPI2 + depends on STM32_HAVE_OCTOSPI2 + bool "OCTOSPI2" + default n + +config STM32_QSPI + bool "QSPI (QUADSPI)" + depends on STM32_HAVE_QSPI || STM32_COMMON_F7_H7 + ---help--- + The STM32L4 QSPI block is intended to support one serial NOR flash device + +# ETH peripherals + +config STM32_ETHMAC + bool "Ethernet MAC" + depends on STM32_HAVE_ETHERNET + select NETDEVICES + select ARCH_HAVE_PHY + select STM32_PHY_HAVE_POLLED if !STM32_COMMON_LEGACY + +# CORDIC peripherals + +config STM32_CORDIC + bool "CORDIC Accelerator" + depends on STM32_HAVE_IP_CORDIC_M3M4_V1 && MATH_CORDIC_USE_Q31 + +config STM32_FMAC + bool "FMAC (Filter Math Accelerator)" + depends on STM32_HAVE_FMAC + +# SENSOR peripherals + +config STM32_DTS + bool "DTS" + depends on STM32_HAVE_DTS + default n + ---help--- + Enable support for the on‑die digital temperature sensor (DTS) + built into STM32H5 devices. When enabled, the driver will register + a `/dev/sensor_tempX` device using the common NuttX sensor framework. + +config STM32_DCMI_PSSI + depends on STM32_HAVE_DCMI_PSSI + bool "DCMI_PSSI" + default n + +config STM32_DCMI + bool "DCMI" + depends on STM32_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32_SYSCFG_IOCOMPENSATION + bool "SYSCFG I/O Compensation" + depends on STM32_HAVE_IOCOMPENSATION + select STM32_CSI if ARCH_CHIP_STM32H7 + ---help--- + By default the I/O compensation cell is not used. However when the I/O + output buffer speed is configured in 50 MHz or 100 MHz mode, it is + recommended to use the compensation cell for slew rate control on I/O + tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. + + The I/O compensation cell can be used only when the supply voltage ranges + from 2.4 to 3.6 V. + +config STM32_JPEG + bool "JPEG" + depends on STM32_HAVE_JPEG + ---help--- + The JPEG codec provides a hardware compressor and decompressor of JPEG + images with full management of JPEG headers. + +config STM32_TSC + bool "TSC" + depends on STM32_HAVE_TSC + +config STM32_COMP1 + bool "COMP1" + select STM32_COMP + depends on STM32_HAVE_COMP1 + +config STM32_COMP2 + bool "COMP2" + select STM32_COMP + depends on STM32_HAVE_COMP2 + +config STM32_COMP3 + bool "COMP3" + default n + select STM32_COMP + depends on STM32_HAVE_COMP3 + +config STM32_COMP4 + bool "COMP4" + default n + select STM32_COMP + depends on STM32_HAVE_COMP4 + +config STM32_COMP5 + bool "COMP5" + default n + select STM32_COMP + depends on STM32_HAVE_COMP5 + +config STM32_COMP6 + bool "COMP6" + default n + select STM32_COMP + depends on STM32_HAVE_COMP6 + +config STM32_COMP7 + bool "COMP7" + default n + select STM32_COMP + depends on STM32_HAVE_COMP7 + +config STM32_OPAMP1 + bool "OPAMP1" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP1 + +config STM32_OPAMP2 + bool "OPAMP2" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP2 + +config STM32_OPAMP3 + bool "OPAMP3" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP3 + +config STM32_OPAMP4 + bool "OPAMP4" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP4 + +# IPCC peripherals + +config STM32_IPCC + bool "IPCC" + depends on STM32_HAVE_IPCC + select IPCC if ARCH_CHIP_STM32WL5 + ---help--- + IPCC - Inter Processor Communication Controller. A very simple + character device stream driver to exchange data between + CM0 and CM4. + +config STM32_HSEM + bool "Hardware semaphore" + depends on STM32_HAVE_HSEM + default n + +# Display peripherals + +config STM32_LCD + bool "Segment LCD" + depends on STM32_HAVE_LCD + select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD + +config STM32_DSIHOST + bool "DSIHOST" + depends on STM32_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI DSI + compliant displays. + +config STM32_LTDC + bool "LTDC" + depends on STM32_HAVE_LTDC + select FB + ---help--- + The STM32 LTDC is an LCD-TFT Display Controller available on + the STM32F429 and STM32F439 devices. It is a standard parallel + video interface (HSYNC, VSYNC, etc.) for controlling TFT + LCD displays. + +endmenu # STM32 Peripheral Support diff --git a/arch/arm/src/common/stm32/Kconfig.qspi b/arch/arm/src/common/stm32/Kconfig.qspi new file mode 100644 index 00000000000..98344097cd5 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.qspi @@ -0,0 +1,158 @@ +# +# STM32 QSPI/OCTOSPI configuration options. +# + +choice + prompt "DMA Channel" + default STM32_QSPI_DMA_CHAN_1_5 + depends on ARCH_CHIP_STM32L4 + ---help--- + You can choose between two DMA channels for use with QSPI: + either DMA1 channel 5, or DMA2 channel 7. + If you only see one choice here, it is probably because + you have not also enabled the associated DMA controller. + +config STM32_QSPI_DMA_CHAN_1_5 + bool "DMA1 Channel 5" + depends on STM32_DMA1 && !STM32_DMAMUX + ---help--- + Use DMA1 channel 5 for QSPI. + +config STM32_QSPI_DMA_CHAN_2_7 + bool "DMA2 Channel 7" + depends on STM32_DMA2 && !STM32_DMAMUX + ---help--- + Use DMA2 channel 7 for QSPI. + +endchoice + +choice + prompt "Transfer technique" + default STM32_QSPI_DMA + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_POLLING + bool "Polling" + ---help--- + Use conventional register I/O with status polling to transfer data. + +config STM32_QSPI_INTERRUPTS + bool "Interrupts" + ---help--- + User interrupt driven I/O transfers. + +config STM32_QSPI_DMA + bool "DMA" + depends on STM32_DMA + ---help--- + Use DMA to improve QSPI transfer performance. + +endchoice + +choice + prompt "Bank selection" + default STM32_QSPI_MODE_BANK1 + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_MODE_BANK1 + bool "Bank 1" + +config STM32_QSPI_MODE_BANK2 + bool "Bank 2" + +config STM32_QSPI_MODE_DUAL + bool "Dual Bank" + +endchoice + +choice + prompt "DMA Priority" + depends on STM32_QSPI_DMA && STM32_DMA + default STM32_QSPI_DMAPRIORITY_MEDIUM + ---help--- + The DMA controller supports priority levels. You are probably fine + with the default of 'medium' except for special cases. In the event + of contention between to channels at the same priority, the lower + numbered channel has hardware priority over the higher numbered one. + +config STM32_QSPI_DMAPRIORITY_VERYHIGH + bool "Very High priority" + depends on STM32_DMA + ---help--- + 'Highest' priority. + +config STM32_QSPI_DMAPRIORITY_HIGH + bool "High priority" + depends on STM32_DMA + ---help--- + 'High' priority. + +config STM32_QSPI_DMAPRIORITY_MEDIUM + bool "Medium priority" + depends on STM32_DMA + ---help--- + 'Medium' priority. + +config STM32_QSPI_DMAPRIORITY_LOW + bool "Low priority" + depends on STM32_DMA + ---help--- + 'Low' priority. + +endchoice + +config STM32_QSPI_FLASH_SIZE + int "Size of attached serial flash, bytes" + default 16777216 + range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires the size of the Flash be specified + +config STM32_QSPI_FIFO_THESHOLD + int "Number of bytes before asserting FIFO threshold flag" + default 4 + range 1 16 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that the FIFO threshold be specified + I would leave it at the default value of 4 unless you know what you are doing. + +config STM32_QSPI_CSHT + int "Number of cycles Chip Select must be inactive between transactions" + default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + default 1 + range 1 8 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that it be specified the minimum number + of AHB cycles that Chip Select be held inactive between transactions. + +config STM32_QSPI_DMATHRESHOLD + int "QSPI DMA threshold" + depends on STM32_QSPI_DMA + default 4 + ---help--- + When QSPI DMA is enabled, small DMA transfers will still be performed + by polling logic. This value is the threshold below which transfers + will still be performed by conventional register status polling. + +config STM32_QSPI_DMADEBUG + bool "QSPI DMA transfer debug" + depends on STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA + ---help--- + Enable special debug instrumentation to analyze QSPI DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_QSPI_REGDEBUG + bool "QSPI Register level debug" + depends on DEBUG_SPI_INFO + ---help--- + Output detailed register-level QSPI device debug information. + Requires also CONFIG_DEBUG_SPI_INFO. diff --git a/arch/arm/src/common/stm32/Kconfig.rtc b/arch/arm/src/common/stm32/Kconfig.rtc new file mode 100644 index 00000000000..b81e7986007 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.rtc @@ -0,0 +1,93 @@ +# +# STM32 common RTC options. +# + +choice + prompt "RTC clock source" + depends on STM32_RTC + default STM32_RTC_LSECLOCK + +config STM32_RTC_LSECLOCK + bool "LSE clock" + ---help--- + Drive the RTC with the LSE clock + +config STM32_RTC_LSICLOCK + bool "LSI clock" + ---help--- + Drive the RTC with the LSI clock + +config STM32_RTC_HSECLOCK + bool "HSE clock" + ---help--- + Drive the RTC with the HSE clock, divided down to 1MHz. + +endchoice # RTC clock source + +config STM32_RTC_MAGIC_REG + int "BKP register" + depends on STM32_HAVE_RTC_MAGIC + default 0 + range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config STM32_RTC_MAGIC + hex "RTC Magic 1" + depends on STM32_HAVE_RTC_MAGIC + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +config STM32_RTC_MAGIC_TIME_SET + hex "RTC Magic 2" + depends on STM32_HAVE_RTC_MAGIC + default 0xf00dface + ---help--- + Value used as Magic to determine if the RTC has been setup and has + time set + +config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" + depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK + ---help--- + This will cycle through the values from low to high. To avoid + damaging the crystal. We want to use the lowest setting that gets + the OSC running. See app note AN2867 + + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY + int "LSE oscillator drive capability level at LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY + int "LSE oscillator drive capability level after LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + bool "Decrease LSE oscillator drive capability after LSE start-up" + depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + The LSE oscillator drive capability can remain at the level used + during LSE start-up at run-time, or it can be reduced to the + 'Low drive capability' once the LSE started up successfully. diff --git a/arch/arm/src/common/stm32/Kconfig.sai b/arch/arm/src/common/stm32/Kconfig.sai new file mode 100644 index 00000000000..67a8c8ef710 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sai @@ -0,0 +1,88 @@ +# +# STM32 common SAI options. +# + +choice + prompt "Operation mode" + depends on STM32_SAI + default STM32_SAI_DMA + ---help--- + Select the operation mode the SAI driver should use. + +config STM32_SAI_POLLING + bool "Polling" + ---help--- + The SAI registers are polled for events. + +config STM32_SAI_INTERRUPTS + bool "Interrupt" + ---help--- + Select to enable interrupt driven SAI support. + +config STM32_SAI_DMA + bool "DMA" + ---help--- + Use DMA to improve SAI transfer performance. + +endchoice # Operation mode + +choice + prompt "SAI1 synchronization enable" + depends on STM32_SAI1_A && STM32_SAI1_B + default STM32_SAI1_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI1_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI1_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI1_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI1 synchronization enable + +choice + prompt "SAI2 synchronization enable" + depends on STM32_SAI2_A && STM32_SAI2_B + default STM32_SAI2_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI2_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI2_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI2_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI2 synchronization enable + +config STM32_SAI1PLL + bool "SAI1PLL" + depends on STM32_COMMON_L4_L5_U5 + ---help--- + The STM32L4 has a separate PLL for the SAI1 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAI2PLL + bool "SAI2PLL" + depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 + ---help--- + The STM32L4 has a separate PLL for the SAI2 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAIPLL + bool "SAIPLL" + default n + depends on STM32_HAVE_SAIPLL + ---help--- + The STM32F446 has a separate PLL for the SAI block. + Set this true and provide configuration parameters in + board.h to use this PLL. diff --git a/arch/arm/src/common/stm32/Kconfig.sdadc b/arch/arm/src/common/stm32/Kconfig.sdadc new file mode 100644 index 00000000000..c2295fd5fe0 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sdadc @@ -0,0 +1,39 @@ +# +# STM32 common SDADC options. +# + +config STM32_SDADC1_HAVE_DMA + bool + +config STM32_SDADC2_HAVE_DMA + bool + +config STM32_SDADC3_HAVE_DMA + bool + +config STM32_SDADC1_DMA + bool "SDADC1 DMA" + depends on STM32_SDADC1 && STM32_SDADC1_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC2_DMA + bool "SDADC2 DMA" + depends on STM32_SDADC2 && STM32_SDADC2_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC3_DMA + bool "SDADC3 DMA" + depends on STM32_SDADC3 && STM32_SDADC3_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. diff --git a/arch/arm/src/common/stm32/Kconfig.sdio b/arch/arm/src/common/stm32/Kconfig.sdio new file mode 100644 index 00000000000..7e11939f9e5 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sdio @@ -0,0 +1,150 @@ +# +# STM32 common SDIO options. +# + +config STM32_SDMMC2_HAVE_DMAPRIO + bool + default y if ARCH_CHIP_STM32F7 + +config STM32_SDIO_CARD + bool "SDIO Card support" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config STM32_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDIO_DMA + bool "Support DMA data transfers" + default STM32_DMA2 + select SDIO_DMA + depends on STM32_COMMON_LEGACY && STM32_SDIO + depends on STM32_DMA2 + ---help--- + Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. + +config STM32_SDIO_DMAPRIO + hex "SDIO DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_COMMON_LEGACY && STM32_SDIO + ---help--- + Select SDIO DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_SDIO_WIDTH_D1_ONLY + bool "Use D1 only" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config STM32_SDMMC_IDMA + bool "Support IDMA data transfers" + depends on ARCH_CHIP_STM32H7 && STM32_SDMMC + default y + select SDIO_DMA + ---help--- + Support IDMA data transfers. + +if STM32_SDMMC + +config STM32_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +config STM32_SDMMC_DMA + bool "Support DMA data transfers" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config STM32_SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 + default 0x00010000 if ARCH_CHIP_STM32F7 + default 0x00001000 + ---help--- + Select SDMMC1 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + depends on STM32_SDMMC1 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC1_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC1_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config SDMMC2_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC2" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC2_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC2_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDMMC2_DMAPRIO + hex "SDMMC2 DMA priority" + default 0x00010000 + depends on STM32_SDMMC2 && STM32_SDMMC2_HAVE_DMAPRIO + ---help--- + Select SDMMC2 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +endif # STM32_SDMMC diff --git a/arch/arm/src/common/stm32/Kconfig.spi b/arch/arm/src/common/stm32/Kconfig.spi new file mode 100644 index 00000000000..cf360f805c9 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.spi @@ -0,0 +1,300 @@ +# +# STM32 common SPI options. +# + +config STM32_SPI_DMA + bool + depends on STM32_HAVE_SPI_CORE_DMA + +config STM32_SPI_INTERRUPTS + bool "Interrupt driver SPI" + depends on STM32_SPI + depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) + ---help--- + Select to enable interrupt driven SPI support. Non-interrupt-driven, + poll-waiting is recommended if the interrupt rate would be to high in + the interrupt driven case. + +config STM32_SPI1_DMA + bool "SPI1 DMA" + depends on STM32_SPI && STM32_SPI1 + depends on STM32_HAVE_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_DMA_BUFFER + int "SPI1 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI1. + +config STM32_SPI_DMATHRESHOLD + int "SPI DMA threshold" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA + default 4 + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config STM32_SPI2_DMA + bool "SPI2 DMA" + depends on STM32_SPI && STM32_SPI2 + depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2_DMA_BUFFER + int "SPI2 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2. + +config STM32_SPI3_DMA + bool "SPI3 DMA" + depends on STM32_SPI && STM32_SPI3 + depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI3_DMA_BUFFER + int "SPI3 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI3. + +config STM32_SPI4_DMA + bool "SPI4 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI4_DMA_BUFFER + int "SPI4 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI4. + +config STM32_SPI5_DMA + bool "SPI5 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI5_DMA_BUFFER + int "SPI5 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI5. + +config STM32_SPI6_DMA + bool "SPI6 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_COMMTYPE + int "SPI1 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI2_COMMTYPE + int "SPI2 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI3_COMMTYPE + int "SPI3 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_DMA_BUFFER + int "SPI6 DMA buffer size" + depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI6. + +config STM32_SPI4_COMMTYPE + int "SPI4 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI5_COMMTYPE + int "SPI5 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_COMMTYPE + int "SPI6 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +menu "I2S Configuration" + depends on STM32_I2S + +config STM32_SPI2S2_DMA + bool "SPI2S2 DMA" + depends on STM32_SPI2 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2S2 transfer performance. Cannot be used with + STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA_BUFFER + int "SPI2S2 DMA buffer size" + default 0 + depends on STM32_SPI2S2_DMA + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. + +config STM32_I2S_MAXINFLIGHT + int "I2S queue size" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) + default 16 + ---help--- + This is the total number of transfers, both RX and TX, that can be + enqueue before the caller is required to wait. This setting + determines the number certain queue data structures that will be + pre-allocated. + +config STM32_I2S3_DATALEN + int "Data width (bits)" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +config STM32_I2S1_MCK + bool "I2S1_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + TBD. + +config STM32_I2S1_RX + bool "Enable I2S1 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S receipt logic + +config STM32_I2S1_TX + bool "Enable I2S1 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S transmission logic + +config STM32_I2S1_DATALEN + int "I2S1 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S2_MCK + bool "I2S2_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + TBD. + +config STM32_I2S2_RX + bool "Enable I2S2 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S receipt logic + +config STM32_I2S2_TX + bool "Enable I2S2 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S transmission logic + +config STM32_I2S2_DATALEN + int "I2S2 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S3_MCK + bool "I2S3_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S3 + ---help--- + TBD. + +config STM32_I2S3_RX + bool "Enable I2S receiver" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S receipt logic + +config STM32_I2S3_TX + bool "Enable I2S transmitter" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S transmission logic + +config STM32_I2S_DMADEBUG + bool "I2S DMA transfer debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) + ---help--- + Enable special debug instrumentation analyze I2S DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_I2S_REGDEBUG + bool "SSC Register level debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) + ---help--- + Output detailed register-level SSC device debug information. + Very invasive! Requires also DEBUG. + +config STM32_I2SPLL + bool "I2SPLL" + default n + depends on STM32_HAVE_I2SPLL + ---help--- + The STM32F446 has a separate PLL for the I2S block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_I2S_MCK + bool "I2S_MCK" + depends on STM32_I2S3 + default n + ---help--- + TBD. + +endmenu # I2S Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.system b/arch/arm/src/common/stm32/Kconfig.system new file mode 100644 index 00000000000..2398b1b534c --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.system @@ -0,0 +1,107 @@ +# +# STM32 common SYSTEM options. +# + +config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG + bool "Disable IDLE Sleep (WFI) in debug mode" + depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + ---help--- + In debug configuration, disables the WFI instruction in the IDLE loop + to prevent the JTAG from disconnecting. With some JTAG debuggers, such + as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI + instruction, the debugger will disconnect, terminating the debug session. + +choice + prompt "JTAG Configuration" + default STM32_JTAG_DISABLE + ---help--- + JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) + +config STM32_JTAG_DISABLE + bool "Disable all JTAG clocking" + +config STM32_JTAG_FULL_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP)" + +config STM32_JTAG_NOJNTRST_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" + +config STM32_JTAG_SW_ENABLE + bool "Set JTAG-DP disabled and SW-DP enabled" + +endchoice + +config STM32_DFU + bool "DFU bootloader" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !(STM32F1_VALUELINE || STM32F0_VALUELINE) + ---help--- + Configure and position code for use with the STMicro DFU bootloader. Do + not select this option if you will load code using JTAG/SWM. + +config STM32_TICKLESS_TIMER + int "Tickless hardware timer" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 2 + range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provided the timer needed by the OS. + +config STM32_TICKLESS_CHANNEL + int "Tickless timer channel" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 1 + range 1 4 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS + and one channel on that clock is needed to handle intervals. + +config STM32_NOEXT_VECTORS + bool "Disable the ARMv7-M EXT vectors" + default n + ---help--- + Sometimes you may not need any Vector support beyond SysTick + and wish to save memory. This applies only to ARMv7-M architectures. + +# Clock options + +choice + prompt "SysTick clock source" + depends on STM32_COMMON_F0_L0_G0_C0 + default STM32_SYSTICK_CORECLK + +config STM32_SYSTICK_CORECLK + bool "Cortex-M0 core clock" + +config STM32_SYSTICK_CORECLK_DIV16 + bool "Cortex-M0 core clock divided by 16" + +endchoice + +config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" + default n + ---help--- + Enables special, board-specific STM32 clock configuration. + +# Power options + +config STM32_FORCEPOWER + bool "Force power" + default n + ---help--- + Timer and I2C devices may need to the following to force power to be applied + unconditionally at power up. (Otherwise, the device is powered when it is + initialized). + +# Debug MCU options + +config STM32_DBGMCU_HAVE_TIM_FZ_IN_CR + bool + +config STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + bool diff --git a/arch/arm/src/common/stm32/Kconfig.tim b/arch/arm/src/common/stm32/Kconfig.tim new file mode 100644 index 00000000000..c130c6b774b --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.tim @@ -0,0 +1,4205 @@ +# +# STM32 timer configuration options. +# + +config STM32_LPTIM1_HAVE_CH1OUT + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM1_HAVE_CH1NOUT + bool + default y if STM32_LPTIM1_HAVE_CH1OUT && STM32_LPTIM1_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM2_HAVE_CH1OUT + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_LPTIM2_HAVE_CH1NOUT + bool + default y if STM32_LPTIM2_HAVE_CH1OUT && STM32_LPTIM2_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_CAP + bool + default n + +config STM32_PULSECOUNT + bool + depends on STM32_HAVE_IP_TIMERS || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select ARCH_HAVE_PULSECOUNT + select PULSECOUNT + +config STM32_QE + bool + default n + +config STM32_PWM_MULTICHAN_L5_TIMERS + bool + default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM + default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM + default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + +config STM32_QENCODER_TIMS_1_4 + bool + default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 + +config STM32_QENCODER_TIMS_1_8 + bool + default y if STM32_QENCODER_TIMS_1_4 + default y if STM32_TIM5 || STM32_TIM8 + +config STM32_QENCODER_MAIN + bool + default y if STM32_HAVE_QENCODER_MAIN && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_STM32 + bool + default y if STM32_HAVE_IP_TIMERS && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_F0 + bool + default y if STM32_HAVE_IP_TIMERS && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 + +config STM32_PWM + bool + +menu "Timer Configuration" + depends on STM32_HAVE_LPTIM_CHANNEL || STM32_HAVE_TIM_ADC_CHANNEL + +if STM32_LPTIM1_PWM + +if STM32_PWM_MULTICHAN + +config STM32_LPTIM1_CHANNEL1 + bool "LPTIM1 Channel 1" + depends on STM32_HAVE_LPTIM_CHANNEL + default n + ---help--- + Enables channel 1. + +endif # STM32_PWM_MULTICHAN + +endif # STM32_LPTIM1_PWM + +if STM32_LPTIM2_PWM + +if STM32_PWM_MULTICHAN + +config STM32_LPTIM2_CHANNEL1 + bool "LPTIM2 Channel 1" + depends on STM32_HAVE_LPTIM_CHANNEL + default n + ---help--- + Enables channel 1. + +endif # STM32_PWM_MULTICHAN + +endif # STM32_LPTIM2_PWM + +config STM32_TIM1_ADC_CHAN + int "TIM1 channel" + default 1 + range 1 4 + depends on STM32_TIM1_ADC + ---help--- + Values 1:CC1 2:CC2 3:CC3 4:CC4 + +config STM32_TIM2_ADC_CHAN + int "TIM2 channel" + default 1 + range 1 4 + depends on STM32_TIM2_ADC + ---help--- + Values 1:CC1 2:CC2 3:CC3 4:CC4 + +config STM32_TIM3_ADC_CHAN + int "TIM3 channel" + default 1 + range 1 4 + depends on STM32_TIM3_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM4_ADC_CHAN + int "TIM4 channel" + default 1 + range 1 4 + depends on STM32_TIM4_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM6_ADC_CHAN + int "TIM6 channel" + default 1 + range 1 4 + depends on STM32_TIM6_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM8_ADC_CHAN + int "TIM8 channel" + default 1 + range 1 4 + depends on STM32_TIM8_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM15_ADC_CHAN + int "TIM15 channel" + default 1 + range 1 4 + depends on STM32_TIM15_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +endmenu # Timer Configuration + +config STM32_TIMX_CAP + bool "Helpers for Capture Drivers" + depends on ARCH_CHIP_STM32H7 + default n + +choice + prompt "Select TIM1 ADC channel" + depends on STM32_TIM1_ADC + default STM32_TIM1_ADC1 + +config STM32_TIM1_ADC1 + bool "TIM1 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC1 + +config STM32_TIM1_ADC2 + bool "TIM1 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC2 + +config STM32_TIM1_ADC3 + bool "TIM1 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM2 ADC channel" + depends on STM32_TIM2_ADC + default STM32_TIM2_ADC1 + +config STM32_TIM2_ADC1 + bool "TIM2 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC1 + +config STM32_TIM2_ADC2 + bool "TIM2 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC2 + +config STM32_TIM2_ADC3 + bool "TIM2 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM3 ADC channel" + depends on STM32_TIM3_ADC + default STM32_TIM3_ADC1 + +config STM32_TIM3_ADC1 + bool "TIM3 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC1 + +config STM32_TIM3_ADC2 + bool "TIM3 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC2 + +config STM32_TIM3_ADC3 + bool "TIM3 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM4 ADC channel" + depends on STM32_TIM4_ADC + default STM32_TIM4_ADC1 + +config STM32_TIM4_ADC1 + bool "TIM4 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC1 + +config STM32_TIM4_ADC2 + bool "TIM4 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC2 + +config STM32_TIM4_ADC3 + bool "TIM4 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM5 ADC channel" + depends on STM32_TIM5_ADC + default STM32_TIM5_ADC1 + +config STM32_TIM5_ADC1 + bool "TIM5 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC1 + +config STM32_TIM5_ADC2 + bool "TIM5 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC2 + +config STM32_TIM5_ADC3 + bool "TIM5 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM8 ADC channel" + depends on STM32_TIM8_ADC + default STM32_TIM8_ADC1 + +config STM32_TIM8_ADC1 + bool "TIM8 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC1 + +config STM32_TIM8_ADC2 + bool "TIM8 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC2 + +config STM32_TIM8_ADC3 + bool "TIM8 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM15 ADC channel" + depends on STM32_TIM15_ADC + default STM32_TIM15_ADC1 + +config STM32_TIM15_ADC1 + bool "TIM15 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC1 + +config STM32_TIM15_ADC2 + bool "TIM15 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC2 + +config STM32_TIM15_ADC3 + bool "TIM15 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC3 + +endchoice + +choice + prompt "Select ADC for use with TIM6" + depends on STM32_TIM6_ADC + default STM32_TIM6_ADC1 + +config STM32_TIM6_ADC1 + bool "Use TIM6 for ADC1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC1 + +config STM32_TIM6_ADC2 + bool "Use TIM6 for ADC2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC2 + +config STM32_TIM6_ADC3 + bool "Use TIM6 for ADC3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC3 + +endchoice + +config STM32_TIM1_ADC + bool "TIM1 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM1 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM2_ADC + bool "TIM2 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM2 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM3_ADC + bool "TIM3 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM3 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM4_ADC + bool "TIM4 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM4 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM5_ADC + bool "TIM5 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM5 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM8_ADC + bool "TIM8 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM8 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM15_ADC + bool "TIM15 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM15 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + +config STM32_TIM6_ADC + bool "TIM6 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM6 && STM32_ADC + ---help--- + Reserve timer 6 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM1 DAC channel" + depends on STM32_TIM1_DAC + default STM32_TIM1_DAC1 + +config STM32_TIM1_DAC1 + bool "TIM1 DAC channel 1" + ---help--- + Reserve TIM1 to trigger DAC1 + +config STM32_TIM1_DAC2 + bool "TIM1 DAC channel 2" + ---help--- + Reserve TIM1 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM2 DAC channel" + depends on STM32_TIM2_DAC + default STM32_TIM2_DAC1 + +config STM32_TIM2_DAC1 + bool "TIM2 DAC channel 1" + ---help--- + Reserve TIM2 to trigger DAC1 + +config STM32_TIM2_DAC2 + bool "TIM2 DAC channel 2" + ---help--- + Reserve TIM2 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM3 DAC channel" + depends on STM32_TIM3_DAC + default STM32_TIM3_DAC1 + +config STM32_TIM3_DAC1 + bool "TIM3 DAC channel 1" + ---help--- + Reserve TIM3 to trigger DAC1 + +config STM32_TIM3_DAC2 + bool "TIM3 DAC channel 2" + ---help--- + Reserve TIM3 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM4 DAC channel" + depends on STM32_TIM4_DAC + default STM32_TIM4_DAC1 + +config STM32_TIM4_DAC1 + bool "TIM4 DAC channel 1" + ---help--- + Reserve TIM4 to trigger DAC1 + +config STM32_TIM4_DAC2 + bool "TIM4 DAC channel 2" + ---help--- + Reserve TIM4 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM5 DAC channel" + depends on STM32_TIM5_DAC + default STM32_TIM5_DAC1 + +config STM32_TIM5_DAC1 + bool "TIM5 DAC channel 1" + ---help--- + Reserve TIM5 to trigger DAC1 + +config STM32_TIM5_DAC2 + bool "TIM5 DAC channel 2" + ---help--- + Reserve TIM5 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM6 DAC channel" + depends on STM32_TIM6_DAC + default STM32_TIM6_DAC1 + +config STM32_TIM6_DAC1 + bool "TIM6 DAC channel 1" + ---help--- + Reserve TIM6 to trigger DAC1 + +config STM32_TIM6_DAC2 + bool "TIM6 DAC channel 2" + ---help--- + Reserve TIM6 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM7 DAC channel" + depends on STM32_TIM7_DAC + default STM32_TIM7_DAC1 + +config STM32_TIM7_DAC1 + bool "TIM7 DAC channel 1" + ---help--- + Reserve TIM7 to trigger DAC1 + +config STM32_TIM7_DAC2 + bool "TIM7 DAC channel 2" + ---help--- + Reserve TIM7 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM8 DAC channel" + depends on STM32_TIM8_DAC + default STM32_TIM8_DAC1 + +config STM32_TIM8_DAC1 + bool "TIM8 DAC channel 1" + ---help--- + Reserve TIM8 to trigger DAC1 + +config STM32_TIM8_DAC2 + bool "TIM8 DAC channel 2" + ---help--- + Reserve TIM8 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM9 DAC channel" + depends on STM32_TIM9_DAC + default STM32_TIM9_DAC1 + +config STM32_TIM9_DAC1 + bool "TIM9 DAC channel 1" + ---help--- + Reserve TIM9 to trigger DAC1 + +config STM32_TIM9_DAC2 + bool "TIM9 DAC channel 2" + ---help--- + Reserve TIM9 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM10 DAC channel" + depends on STM32_TIM10_DAC + default STM32_TIM10_DAC1 + +config STM32_TIM10_DAC1 + bool "TIM10 DAC channel 1" + ---help--- + Reserve TIM10 to trigger DAC1 + +config STM32_TIM10_DAC2 + bool "TIM10 DAC channel 2" + ---help--- + Reserve TIM10 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM11 DAC channel" + depends on STM32_TIM11_DAC + default STM32_TIM11_DAC1 + +config STM32_TIM11_DAC1 + bool "TIM11 DAC channel 1" + ---help--- + Reserve TIM11 to trigger DAC1 + +config STM32_TIM11_DAC2 + bool "TIM11 DAC channel 2" + ---help--- + Reserve TIM11 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM12 DAC channel" + depends on STM32_TIM12_DAC + default STM32_TIM12_DAC1 + +config STM32_TIM12_DAC1 + bool "TIM12 DAC channel 1" + ---help--- + Reserve TIM12 to trigger DAC1 + +config STM32_TIM12_DAC2 + bool "TIM12 DAC channel 2" + ---help--- + Reserve TIM12 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM13 DAC channel" + depends on STM32_TIM13_DAC + default STM32_TIM13_DAC1 + +config STM32_TIM13_DAC1 + bool "TIM13 DAC channel 1" + ---help--- + Reserve TIM13 to trigger DAC1 + +config STM32_TIM13_DAC2 + bool "TIM13 DAC channel 2" + ---help--- + Reserve TIM13 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM14 DAC channel" + depends on STM32_TIM14_DAC + default STM32_TIM14_DAC1 + +config STM32_TIM14_DAC1 + bool "TIM14 DAC channel 1" + ---help--- + Reserve TIM14 to trigger DAC1 + +config STM32_TIM14_DAC2 + bool "TIM14 DAC channel 2" + ---help--- + Reserve TIM14 to trigger DAC2 + +endchoice + +config STM32_TIM1_DAC + bool "TIM1 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM1 && STM32_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM2_DAC + bool "TIM2 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM2 && STM32_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM3_DAC + bool "TIM3 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM3 && STM32_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM4_DAC + bool "TIM4 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM4 && STM32_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM5_DAC + bool "TIM5 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM5 && STM32_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM6_DAC + bool "TIM6 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM6 && STM32_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM7_DAC + bool "TIM7 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM7 && STM32_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM8_DAC + bool "TIM8 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM8 && STM32_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM9_DAC + bool "TIM9 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM9 && STM32_DAC + ---help--- + Reserve timer 9 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM9 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM10_DAC + bool "TIM10 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM10 && STM32_DAC + ---help--- + Reserve timer 10 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM10 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM11_DAC + bool "TIM11 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM11 && STM32_DAC + ---help--- + Reserve timer 11 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM11 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM12_DAC + bool "TIM12 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM12 && STM32_DAC + ---help--- + Reserve timer 12 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM12 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM13_DAC + bool "TIM13 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM13 && STM32_DAC + ---help--- + Reserve timer 13 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM13 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM14_DAC + bool "TIM14 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM14 && STM32_DAC + ---help--- + Reserve timer 14 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM14 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Input channel sampling frequency" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_FDTS_4 + +config STM32_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice + +choice + prompt "Input channel event count" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_EVENT_6 + +config STM32_QENCODER_SAMPLE_EVENT_1 + bool "1" + depends on STM32_QENCODER_SAMPLE_FDTS + +config STM32_QENCODER_SAMPLE_EVENT_2 + bool "2" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_4 + bool "4" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_5 + bool "5" + depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 + +config STM32_QENCODER_SAMPLE_EVENT_6 + bool "6" + depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_8 + bool "8" + depends on !STM32_QENCODER_SAMPLE_FDTS + +endchoice + +choice + prompt "LPTIM1 clock source" + default STM32_LPTIM1_CLK_APB1 + +config STM32_LPTIM1_CLK_APB1 + bool "Clock LPTIM1 from APB1" + +config STM32_LPTIM1_CLK_LSE + bool "Clock LPTIM1 from LSE" + +config STM32_LPTIM1_CLK_LSI + bool "Clock LPTIM1 from LSI" + +config STM32_LPTIM1_CLK_HSI + bool "Clock LPTIM1 from HSI" + +endchoice + +choice + prompt "LPTIM2 clock source" + default STM32_LPTIM2_CLK_APB1 + +config STM32_LPTIM2_CLK_APB1 + bool "Clock LPTIM2 from APB1" + +config STM32_LPTIM2_CLK_LSE + bool "Clock LPTIM2 from LSE" + +config STM32_LPTIM2_CLK_LSI + bool "Clock LPTIM2 from LSI" + +config STM32_LPTIM2_CLK_HSI + bool "Clock LPTIM2 from HSI" + +endchoice + +config STM32_ONESHOT + bool "TIM one-shot wrapper" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32_FREERUN + bool "TIM free-running wrapper" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +config STM32_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + depends on STM32_ONESHOT + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default 1 + range 1 8 + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +config STM32_PWM_LL_OPS + bool "PWM low-level operations" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + ---help--- + Enable low-level PWM ops. + +config STM32_TIM1_PWM + bool "TIM1 PWM" + depends on STM32_TIM1 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM1_MODE + int "TIM1 Mode" + depends on STM32_TIM1_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM1_LOCK + int "TIM1 Lock Level Configuration" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 3 + ---help--- + Timer 1 lock level configuration + +config STM32_TIM1_TDTS + int "TIM1 t_DTS Division" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 2 + ---help--- + Timer 1 dead-time and sampling clock (t_DTS) division + +config STM32_TIM1_DEADTIME + int "TIM1 Initial Dead-time" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 255 + ---help--- + Timer 1 initial dead-time + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + depends on STM32_TIM1_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM1_CHANNEL5 + bool "TIM1 Channel 5 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM1_CH5MODE + int "TIM1 Channel 5 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH5OUT + bool "TIM1 Channel 5 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 5 output. + +config STM32_TIM1_CHANNEL6 + bool "TIM1 Channel 6 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM1_CH6MODE + int "TIM1 Channel 6 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH6OUT + bool "TIM1 Channel 6 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 6 output. + +config STM32_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_PWM + bool "TIM2 PWM" + depends on STM32_TIM2 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM2_MODE + int "TIM2 Mode" + depends on STM32_TIM2_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + depends on STM32_TIM2_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_PWM + bool "TIM3 PWM" + depends on STM32_TIM3 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM3_MODE + int "TIM3 Mode" + depends on STM32_TIM3_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + depends on STM32_TIM3_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_PWM + bool "TIM4 PWM" + depends on STM32_TIM4 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM4_MODE + int "TIM4 Mode" + depends on STM32_TIM4_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + depends on STM32_TIM4_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_PWM + bool "TIM5 PWM" + depends on STM32_TIM5 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM5_MODE + int "TIM5 Mode" + depends on STM32_TIM5_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + depends on STM32_TIM5_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_PWM + bool "TIM8 PWM" + depends on STM32_TIM8 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM8_MODE + int "TIM8 Mode" + depends on STM32_TIM8_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM8_LOCK + int "TIM8 Lock Level Configuration" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 3 + ---help--- + Timer 8 lock level configuration + +config STM32_TIM8_DEADTIME + int "TIM8 Initial Dead-time" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 255 + ---help--- + Timer 8 initial dead-time + +config STM32_TIM8_TDTS + int "TIM8 t_DTS Division" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 2 + ---help--- + Timer 8 dead-time and sampling clock (t_DTS) division + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + depends on STM32_TIM8_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM8_CHANNEL5 + bool "TIM8 Channel 5 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM8_CH5MODE + int "TIM8 Channel 5 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH5OUT + bool "TIM8 Channel 5 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 5 output. + +config STM32_TIM8_CHANNEL6 + bool "TIM8 Channel 6 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM8_CH6MODE + int "TIM8 Channel 6 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH6OUT + bool "TIM8 Channel 6 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 6 output. + +config STM32_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_PWM + bool "TIM9 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 9 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM9 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 2. + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) + ---help--- + Enables channel 2 output. + +config STM32_TIM9_CHANNEL + int "TIM9 PWM Output Channel" + depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CAP + range 1 2 if !STM32_HAVE_IP_TIMERS || !STM32_TIM9_CAP + ---help--- + If TIM9 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_PWM + bool "TIM10 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 10 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM10 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + depends on STM32_TIM10_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM10_CHANNEL + int "TIM10 PWM Output Channel" + depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM10_CAP + ---help--- + If TIM10 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_PWM + bool "TIM11 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 11 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM11 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + depends on STM32_TIM11_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM11_CHANNEL + int "TIM11 PWM Output Channel" + depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM11_CAP + ---help--- + If TIM11 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_PWM + bool "TIM12 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 12 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM12 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 2 output. + +config STM32_TIM12_CHANNEL + int "TIM12 PWM Output Channel" + depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP + range 1 2 if !STM32_HAVE_IP_TIMERS || !STM32_TIM12_CAP + ---help--- + If TIM12 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_PWM + bool "TIM13 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 13 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM13 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + depends on STM32_TIM13_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM13_CHANNEL + int "TIM13 PWM Output Channel" + depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM13_CAP + ---help--- + If TIM13 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_PWM + bool "TIM14 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 || (STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 14 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM14 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 + default 0 if STM32_HAVE_IP_TIMERS + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + range 0 1 if STM32_HAVE_IP_TIMERS + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + depends on STM32_TIM14_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM14_CHANNEL + int "TIM14 PWM Output Channel" + depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM14_CAP + ---help--- + If TIM14 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_IP_TIMERS + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + range 0 1 if STM32_HAVE_IP_TIMERS + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_PWM + bool "TIM15 PWM" + depends on STM32_TIM15 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM15_LOCK + int "TIM15 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 3 + ---help--- + Timer 15 lock level configuration + +config STM32_TIM15_TDTS + int "TIM15 t_DTS Division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 2 + ---help--- + Timer 15 dead-time and sampling clock (t_DTS) division + +config STM32_TIM15_DEADTIME + int "TIM15 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 255 + ---help--- + Timer 15 initial dead-time + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM15_CH2NOUT + bool "TIM15 Channel 2 Complementary Output" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 + depends on STM32_HAVE_TIM_PWM_SINGLECHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_PWM + bool "TIM16 PWM" + depends on STM32_TIM16 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM16_LOCK + int "TIM16 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 3 + ---help--- + Timer 16 lock level configuration + +config STM32_TIM16_TDTS + int "TIM16 t_DTS division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 2 + ---help--- + Timer 16 dead-time and sampling clock (t_DTS) division + +config STM32_TIM16_DEADTIME + int "TIM16 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 255 + ---help--- + Timer 16 initial dead-time + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + depends on STM32_TIM16_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_PWM + bool "TIM17 PWM" + depends on STM32_TIM17 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM17_LOCK + int "TIM17 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 3 + ---help--- + Timer 17 lock level configuration + +config STM32_TIM17_TDTS + int "TIM17 t_DTS Division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 2 + ---help--- + Timer 17 dead-time and sampling clock (t_DTS) division + +config STM32_TIM17_DEADTIME + int "TIM17 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 255 + ---help--- + Timer 17 initial dead-time + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + depends on STM32_TIM17_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + depends on STM32_HAVE_PWM_MULTICHAN + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32_TIM1_PULSECOUNT + bool "TIM1 pulse count" + depends on STM32_TIM1 + depends on STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 1 for pulse count output. + +if STM32_TIM1_PULSECOUNT + +config STM32_TIM1_PULSECOUNT_TDTS + int "TIM1 pulse count clock division" + default 0 + range 0 2 + depends on !STM32_HAVE_IP_TIMERS + +config STM32_TIM1_PULSECOUNT_CHANNEL + int "TIM1 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM1_PULSECOUNT_POL + int "TIM1 pulse count output polarity" + default 0 + range 0 1 + depends on !STM32_HAVE_IP_TIMERS + +config STM32_TIM1_PULSECOUNT_IDLE + int "TIM1 pulse count idle state" + default 0 + range 0 1 + depends on !STM32_HAVE_IP_TIMERS + +endif # STM32_TIM1_PULSECOUNT + +config STM32_TIM8_PULSECOUNT + bool "TIM8 pulse count" + depends on STM32_TIM8 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 8 for pulse count output. + +if STM32_TIM8_PULSECOUNT + +config STM32_TIM8_PULSECOUNT_TDTS + int "TIM8 pulse count clock division" + default 0 + range 0 2 + +config STM32_TIM8_PULSECOUNT_CHANNEL + int "TIM8 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM8_PULSECOUNT_POL + int "TIM8 pulse count output polarity" + default 0 + range 0 1 + +config STM32_TIM8_PULSECOUNT_IDLE + int "TIM8 pulse count idle state" + default 0 + range 0 1 + +endif # STM32_TIM8_PULSECOUNT + +config STM32_PWM_TRGO + bool "TIM PWM TRGO support" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) + ---help--- + Enable TRGO support for PWM driver + +config STM32_TIM1_CAP + bool "TIM1 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM1_CLOCK + int "TIM1 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM2_CAP + bool "TIM2 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM2_CLOCK + int "TIM2 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM3_CAP + bool "TIM3 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM3_CLOCK + int "TIM3 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM4_CAP + bool "TIM4 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM4_CLOCK + int "TIM4 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM5_CAP + bool "TIM5 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM5_CLOCK + int "TIM5 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM8_CAP + bool "TIM8 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM8_CLOCK + int "TIM8 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM9_CAP + bool "TIM9 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM10_CAP + bool "TIM10 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM11_CAP + bool "TIM11 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CAP + bool "TIM12 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CLOCK + int "TIM12 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM13_CAP + bool "TIM13 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM13_CLOCK + int "TIM13 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM14_CAP + bool "TIM14 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM14_CLOCK + int "TIM14 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM1_CH1POL + int "TIM1 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output polarity + +config STM32_TIM1_CH1IDLE + int "TIM1 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output IDLE + +config STM32_TIM1_CH1NPOL + int "TIM1 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output polarity + +config STM32_TIM1_CH1NIDLE + int "TIM1 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output IDLE + +config STM32_TIM1_CH2POL + int "TIM1 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output polarity + +config STM32_TIM1_CH2IDLE + int "TIM1 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output IDLE + +config STM32_TIM1_CH2NPOL + int "TIM1 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output polarity + +config STM32_TIM1_CH2NIDLE + int "TIM1 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output IDLE + +config STM32_TIM1_CH3POL + int "TIM1 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output polarity + +config STM32_TIM1_CH3IDLE + int "TIM1 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output IDLE + +config STM32_TIM1_CH3NPOL + int "TIM1 Channel 3 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output polarity + +config STM32_TIM1_CH3NIDLE + int "TIM1 Channel 3 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output IDLE + +config STM32_TIM1_CH4POL + int "TIM1 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output polarity + +config STM32_TIM1_CH4IDLE + int "TIM1 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output IDLE + +config STM32_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output polarity + +config STM32_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output IDLE + +config STM32_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output polarity + +config STM32_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output IDLE + +config STM32_TIM2_CH1POL + int "TIM2 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output polarity + +config STM32_TIM2_CH1IDLE + int "TIM2 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output IDLE + +config STM32_TIM2_CH2POL + int "TIM2 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output polarity + +config STM32_TIM2_CH2IDLE + int "TIM2 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output IDLE + +config STM32_TIM2_CH3POL + int "TIM2 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output polarity + +config STM32_TIM2_CH3IDLE + int "TIM2 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output IDLE + +config STM32_TIM2_CH4POL + int "TIM2 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output polarity + +config STM32_TIM2_CH4IDLE + int "TIM2 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output IDLE + +config STM32_TIM3_CH1POL + int "TIM3 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output polarity + +config STM32_TIM3_CH1IDLE + int "TIM3 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output IDLE + +config STM32_TIM3_CH2POL + int "TIM3 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output polarity + +config STM32_TIM3_CH2IDLE + int "TIM3 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output IDLE + +config STM32_TIM3_CH3POL + int "TIM3 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output polarity + +config STM32_TIM3_CH3IDLE + int "TIM3 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output IDLE + +config STM32_TIM3_CH4POL + int "TIM3 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output polarity + +config STM32_TIM3_CH4IDLE + int "TIM3 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output IDLE + +config STM32_TIM4_CH1POL + int "TIM4 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output polarity + +config STM32_TIM4_CH1IDLE + int "TIM4 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output IDLE + +config STM32_TIM4_CH2POL + int "TIM4 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output polarity + +config STM32_TIM4_CH2IDLE + int "TIM4 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output IDLE + +config STM32_TIM4_CH3POL + int "TIM4 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output polarity + +config STM32_TIM4_CH3IDLE + int "TIM4 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output IDLE + +config STM32_TIM4_CH4POL + int "TIM4 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output polarity + +config STM32_TIM4_CH4IDLE + int "TIM4 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output IDLE + +config STM32_TIM5_CH1POL + int "TIM5 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output polarity + +config STM32_TIM5_CH1IDLE + int "TIM5 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output IDLE + +config STM32_TIM5_CH2POL + int "TIM5 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output polarity + +config STM32_TIM5_CH2IDLE + int "TIM5 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output IDLE + +config STM32_TIM5_CH3POL + int "TIM5 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output polarity + +config STM32_TIM5_CH3IDLE + int "TIM5 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output IDLE + +config STM32_TIM5_CH4POL + int "TIM5 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output polarity + +config STM32_TIM5_CH4IDLE + int "TIM5 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output IDLE + +config STM32_TIM8_CH1POL + int "TIM8 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output polarity + +config STM32_TIM8_CH1IDLE + int "TIM8 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output IDLE + +config STM32_TIM8_CH1NPOL + int "TIM8 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output polarity + +config STM32_TIM8_CH1NIDLE + int "TIM8 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output IDLE + +config STM32_TIM8_CH2POL + int "TIM8 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output polarity + +config STM32_TIM8_CH2IDLE + int "TIM8 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output IDLE + +config STM32_TIM8_CH2NPOL + int "TIM8 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output polarity + +config STM32_TIM8_CH2NIDLE + int "TIM8 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output IDLE + +config STM32_TIM8_CH3POL + int "TIM8 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output polarity + +config STM32_TIM8_CH3IDLE + int "TIM8 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output IDLE + +config STM32_TIM8_CH3NPOL + int "TIM8 Channel 3 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output polarity + +config STM32_TIM8_CH3NIDLE + int "TIM8 Channel 3 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output IDLE + +config STM32_TIM8_CH4POL + int "TIM8 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output polarity + +config STM32_TIM8_CH4IDLE + int "TIM8 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output IDLE + +config STM32_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output polarity + +config STM32_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output IDLE + +config STM32_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output polarity + +config STM32_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output IDLE + +config STM32_TIM9_CH1POL + int "TIM9 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output polarity + +config STM32_TIM9_CH1IDLE + int "TIM9 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output IDLE + +config STM32_TIM9_CH2POL + int "TIM9 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output polarity + +config STM32_TIM9_CH2IDLE + int "TIM9 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output IDLE + +config STM32_TIM10_CH1POL + int "TIM10 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output polarity + +config STM32_TIM10_CH1IDLE + int "TIM10 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output IDLE + +config STM32_TIM11_CH1POL + int "TIM11 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output polarity + +config STM32_TIM11_CH1IDLE + int "TIM11 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output IDLE + +config STM32_TIM12_CH1POL + int "TIM12 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output polarity + +config STM32_TIM12_CH1IDLE + int "TIM12 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output IDLE + +config STM32_TIM12_CH2POL + int "TIM12 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output polarity + +config STM32_TIM12_CH2IDLE + int "TIM12 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output IDLE + +config STM32_TIM13_CH1POL + int "TIM13 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output polarity + +config STM32_TIM13_CH1IDLE + int "TIM13 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output IDLE + +config STM32_TIM14_CH1POL + int "TIM14 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output polarity + +config STM32_TIM14_CH1IDLE + int "TIM14 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output IDLE + +config STM32_TIM15_CH1POL + int "TIM15 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output polarity + +config STM32_TIM15_CH1IDLE + int "TIM15 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output IDLE + +config STM32_TIM15_CH1NPOL + int "TIM15 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output polarity + +config STM32_TIM15_CH1NIDLE + int "TIM15 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output IDLE + +config STM32_TIM15_CH2POL + int "TIM15 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output polarity + +config STM32_TIM15_CH2IDLE + int "TIM15 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output IDLE + +config STM32_TIM15_CH2NPOL + int "TIM15 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output polarity + +config STM32_TIM15_CH2NIDLE + int "TIM15 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output IDLE + +config STM32_TIM16_CH1POL + int "TIM16 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output polarity + +config STM32_TIM16_CH1IDLE + int "TIM16 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output IDLE + +config STM32_TIM17_CH1POL + int "TIM17 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output polarity + +config STM32_TIM17_CH1IDLE + int "TIM17 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output IDLE + +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS + bool "Disable QEncoder timers extension from 16-bit to 32-bit" + depends on STM32_HAVE_QENCODER_16BIT + ---help--- + Disable the extension of 16-bit timers to 32-bit via interrupt-based + overflow tracking. When enabled, timers will use their native hardware + counter width (16-bit or 32-bit). This reduces interrupt overhead but + limits the position range for 16-bit timers. + +config STM32_QENCODER_INDEX_PIN + bool "Enable QEncoder timers support for index pin" + depends on STM32_HAVE_QENCODER_16BIT + ---help--- + Enable support for quadrature encoder index pin. The index pin can be + used to reset the encoder position to a known value when the index + pulse is detected. + +config STM32_TIM1_QE + bool "TIM1 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_HAVE_IP_TIMERS && STM32_TIM1) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +config STM32_TIM1_QEPSC + int "TIM1 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM2_QE + bool "TIM2 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_HAVE_IP_TIMERS && STM32_TIM2) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +config STM32_TIM2_QEPSC + int "TIM2 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM3_QE + bool "TIM3 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_HAVE_IP_TIMERS && STM32_TIM3) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +config STM32_TIM3_QEPSC + int "TIM3 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM4_QE + bool "TIM4 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_HAVE_IP_TIMERS && STM32_TIM4) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +config STM32_TIM4_QEPSC + int "TIM4 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM5_QE + bool "TIM5 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM5 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +config STM32_TIM5_QEPSC + int "TIM5 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM5_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM8_QE + bool "TIM8 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM8 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +config STM32_TIM8_QEPSC + int "TIM8 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM8_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 + default y + ---help--- + Enable input filtering on quadrature encoder channels to reduce noise. + +config STM32_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + depends on (STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + depends on (STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM15_CAP + bool "TIM15 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM15 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 + ---help--- + Reserve timer 15 for use by the capture driver. + +config STM32_TIM16_CAP + bool "TIM16 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM16 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 + ---help--- + Reserve timer 16 for use by the capture driver. + +config STM32_TIM17_CAP + bool "TIM17 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM17 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 + ---help--- + Reserve timer 17 for use by the capture driver. + +config STM32_TIM15_CLOCK + int "TIM15 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM16_CLOCK + int "TIM16 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM17_CLOCK + int "TIM17 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CAP + bool "LPTIM1 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 1 for use by the capture driver. + +config STM32_LPTIM1_CLOCK + int "LPTIM1 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM2_CAP + bool "LPTIM2 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 2 for use by the capture driver. + +config STM32_LPTIM2_CLOCK + int "LPTIM2 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CHANNEL + int "LPTIM1 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM1. + +config STM32_LPTIM2_CHANNEL + int "LPTIM2 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM2. + +config STM32_LPTIM3_CAP + bool "LPTIM3 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 3 for use by the capture driver. + +config STM32_LPTIM3_CHANNEL + int "LPTIM3 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM3. + +config STM32_LPTIM3_CLOCK + int "LPTIM3 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM4_CAP + bool "LPTIM4 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 4 for use by the capture driver. + +config STM32_LPTIM4_CHANNEL + int "LPTIM4 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM4. + +config STM32_LPTIM4_CLOCK + int "LPTIM4 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM5_CAP + bool "LPTIM5 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 5 for use by the capture driver. + +config STM32_LPTIM5_CHANNEL + int "LPTIM5 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM5. + +config STM32_LPTIM5_CLOCK + int "LPTIM5 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT + default 2 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the one-shot timer needed by the OS. + +config STM32_TICKLESS_FREERUN + int "Tickless free-running timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN + default 5 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the free-running timer needed by the OS. + +config STM32_LPTIM1_PWM + bool "LPTIM1 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 + select PWM + ---help--- + Reserve low-power timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM2_PWM + bool "LPTIM2 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 + select PWM + ---help--- + Reserve low-power timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM1_CH1OUT + bool "LPTIM1 Channel 1 Output" + depends on STM32_LPTIM1_HAVE_CH1OUT + ---help--- + Enables channel 1 output. + +config STM32_LPTIM1_CH1NOUT + bool "LPTIM1 Channel 1 Complementary Output" + depends on STM32_LPTIM1_HAVE_CH1NOUT + ---help--- + Enables channel 1 complementary output. + +config STM32_LPTIM2_CH1OUT + bool "LPTIM2 Channel 1 Output" + depends on STM32_LPTIM2_HAVE_CH1OUT + ---help--- + Enables channel 1 output. + +config STM32_LPTIM2_CH1NOUT + bool "LPTIM2 Channel 1 Complementary Output" + depends on STM32_LPTIM2_HAVE_CH1NOUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM2_CHANNEL5 + bool "TIM2 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM3_CHANNEL5 + bool "TIM3 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM4_CHANNEL5 + bool "TIM4 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM5_CHANNEL5 + bool "TIM5 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +menu "Timer Configuration" + depends on STM32_TIM + +if STM32_TIM9_CAP + +config STM32_TIM9_CLOCK + int "TIM9 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM9_CAP + +if STM32_TIM10_CAP + +config STM32_TIM10_CLOCK + int "TIM10 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM10_CAP + +if STM32_TIM11_CAP + +config STM32_TIM11_CLOCK + int "TIM11 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM11_CAP + +endmenu # Timer Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.uart b/arch/arm/src/common/stm32/Kconfig.uart new file mode 100644 index 00000000000..05836690894 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.uart @@ -0,0 +1,1245 @@ +# +# STM32 USART/UART configuration options. +# + +config STM32_USART1_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F37XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32G4XXX && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if ARCH_CHIP_STM32WB && (STM32_DMA) + +config STM32_USART1_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F37XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32G4XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART2_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMAMUX) + +config STM32_USART2_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART3_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMAMUX) + +config STM32_USART3_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_UART4_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_UART4_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_UART5_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_UART5_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART6_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + +config STM32_USART6_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + +config STM32_UART7_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART7_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART8_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART8_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_1WIREDRIVER + bool + +config USART1_RXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER && STM32_USART1_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART1_TXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER && STM32_USART1_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART2_RXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER && STM32_USART2_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART2_TXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER && STM32_USART2_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART3_RXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER && STM32_USART3_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART3_TXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER && STM32_USART3_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART4_RXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER && STM32_UART4_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART4_TXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER && STM32_UART4_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART5_RXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER && STM32_UART5_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART5_TXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER && STM32_UART5_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART6_RXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER && STM32_USART6_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART6_TXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER && STM32_USART6_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART7_RXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER && STM32_UART7_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART7_TXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER && STM32_UART7_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART8_RXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER && STM32_UART8_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART8_TXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER && STM32_UART8_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config STM32_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + depends on STM32_USART + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some boards and a serial console in other boards, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +choice + prompt "USART1 Driver Configuration" + depends on STM32_USART1 + default STM32_USART1_SERIALDRIVER + +config STM32_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART1_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART1 Driver Configuration + +choice + prompt "USART2 Driver Configuration" + depends on STM32_USART2 + default STM32_USART2_SERIALDRIVER + +config STM32_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART2_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART2 Driver Configuration + +choice + prompt "USART3 Driver Configuration" + depends on STM32_USART3 + default STM32_USART3_SERIALDRIVER + +config STM32_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART3_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART3 Driver Configuration + +choice + prompt "UART4 Driver Configuration" + depends on STM32_UART4 + default STM32_UART4_SERIALDRIVER + +config STM32_UART4_SERIALDRIVER + bool "Standard serial driver" + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART1 Driver Configuration + +choice + prompt "UART5 Driver Configuration" + depends on STM32_UART5 + default STM32_UART5_SERIALDRIVER + +config STM32_UART5_SERIALDRIVER + bool "Standard serial driver" + select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART5 Driver Configuration + +choice + prompt "USART6 Driver Configuration" + depends on STM32_USART6 + default STM32_USART6_SERIALDRIVER + +config STM32_USART6_SERIALDRIVER + bool "Standard serial driver" + select USART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART6_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART6_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART6 Driver Configuration + +choice + prompt "USART4 Driver Configuration" + depends on STM32_USART4 + default STM32_USART4_SERIALDRIVER + +config STM32_USART4_SERIALDRIVER + bool "Standard serial driver" + select USART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART4 Driver Configuration + +choice + prompt "USART5 Driver Configuration" + depends on STM32_USART5 + default STM32_USART5_SERIALDRIVER + +config STM32_USART5_SERIALDRIVER + bool "Standard serial driver" + select USART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART5 Driver Configuration + +choice + prompt "USART7 Driver Configuration" + depends on STM32_USART7 + default STM32_USART7_SERIALDRIVER + +config STM32_USART7_SERIALDRIVER + bool "Standard serial driver" + select USART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART7 Driver Configuration + +choice + prompt "USART8 Driver Configuration" + depends on STM32_USART8 + default STM32_USART8_SERIALDRIVER + +config STM32_USART8_SERIALDRIVER + bool "Standard serial driver" + select USART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART8 Driver Configuration + +choice + prompt "UART7 Driver Configuration" + depends on STM32_HAVE_IP_USART && STM32_UART7 + default STM32_UART7_SERIALDRIVER + +config STM32_UART7_SERIALDRIVER + bool "Standard serial driver" + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART7_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART7 Driver Configuration + +choice + prompt "UART8 Driver Configuration" + depends on STM32_HAVE_IP_USART && STM32_UART8 + default STM32_UART8_SERIALDRIVER + +config STM32_UART8_SERIALDRIVER + bool "Standard serial driver" + select UART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART8_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART8 Driver Configuration + +config USART1_RS485 + bool "RS-485 on USART1" + depends on STM32_USART1 && USART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be + used with USART1_RXDMA. + +if USART1_RS485 + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART1_RS485 + +config USART2_RS485 + bool "RS-485 on USART2" + depends on STM32_USART2 && USART2_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be + used with USART2_RXDMA. + +if USART2_RS485 + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART2_RS485 + +config USART3_RS485 + bool "RS-485 on USART3" + depends on STM32_USART3 && USART3_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be + used with USART3_RXDMA. + +if USART3_RS485 + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART3_RS485 + +config UART4_RS485 + bool "RS-485 on UART4" + depends on STM32_UART4 && UART4_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART4. Your board config will have to + provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be + used with UART4_RXDMA. + +if UART4_RS485 + +config UART4_RS485_DIR_POLARITY + int "UART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART4_RS485 + +config UART5_RS485 + bool "RS-485 on UART5" + depends on STM32_UART5 && UART5_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART5. Your board config will have to + provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be + used with UART5_RXDMA. + +if UART5_RS485 + +config UART5_RS485_DIR_POLARITY + int "UART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART5_RS485 + +config USART6_RS485 + bool "RS-485 on USART6" + depends on STM32_USART6 && USART6_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART6. Your board config will have to + provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be + used with USART6_RXDMA. + +if USART6_RS485 + +config USART6_RS485_DIR_POLARITY + int "USART6 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART6_RS485 + +config UART7_RS485 + bool "RS-485 on UART7" + depends on STM32_UART7 && UART7_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART7. Your board config will have to + provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be + used with UART7_RXDMA. + +if UART7_RS485 + +config UART7_RS485_DIR_POLARITY + int "UART7 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART7_RS485 + +config UART8_RS485 + bool "RS-485 on UART8" + depends on STM32_UART8 && UART8_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART8. Your board config will have to + provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be + used with UART8_RXDMA. + +if UART8_RS485 + +config UART8_RS485_DIR_POLARITY + int "UART8 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART8_RS485 + +if UART9_SERIALDRIVER + +config UART9_RS485 + bool "RS-485 on UART9" + default n + depends on STM32_UART9 + ---help--- + Enable RS-485 interface on UART9. Your board config will have to + provide GPIO_UART9_RS485_DIR pin definition. Currently it cannot be + used with UART9_RXDMA. + +config UART9_RS485_DIR_POLARITY + int "UART9 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART9_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART9. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART9_RXDMA + bool "UART9 RX DMA" + default n + depends on STM32_UART9 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART9_SERIALDRIVER + +if USART10_SERIALDRIVER + +config USART10_RS485 + bool "RS-485 on USART10" + default n + depends on STM32_USART10 + ---help--- + Enable RS-485 interface on USART10. Your board config will have to + provide GPIO_USART10_RS485_DIR pin definition. Currently it cannot be + used with USART10_RXDMA. + +config USART10_RS485_DIR_POLARITY + int "USART10 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART10_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART10. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART10_RXDMA + bool "USART10 RX DMA" + default n + depends on STM32_USART10 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART10_SERIALDRIVER + +if USART11_SERIALDRIVER + +config USART11_RS485 + bool "RS-485 on USART11" + default n + depends on STM32_USART11 + ---help--- + Enable RS-485 interface on USART11. Your board config will have to + provide GPIO_USART11_RS485_DIR pin definition. Currently it cannot be + used with USART11_RXDMA. + +config USART11_RS485_DIR_POLARITY + int "USART11 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART11_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART11. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART11_RXDMA + bool "USART11 RX DMA" + default n + depends on STM32_USART11 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART11_SERIALDRIVER + +if UART12_SERIALDRIVER + +config UART12_RS485 + bool "RS-485 on UART12" + default n + depends on STM32_UART12 + ---help--- + Enable RS-485 interface on UART12. Your board config will have to + provide GPIO_UART12_RS485_DIR pin definition. Currently it cannot be + used with UART12_RXDMA. + +config UART12_RS485_DIR_POLARITY + int "UART12 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART12_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART12. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART12_RXDMA + bool "UART12 RX DMA" + default n + depends on STM32_UART12 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART12_SERIALDRIVER + +config STM32_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + depends on STM32_USART && SERIAL_RXDMA + range 32 4096 + default 32 + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_FLOWCONTROL_BROKEN + bool "Use Software UART RTS flow control" + depends on STM32_USART + ---help--- + Enable UART RTS flow control using Software. Because STM + Current STM32 have broken HW based RTS behavior (they assert + nRTS after every byte received) Enable this setting workaround + this issue by using software based management of RTS + +config STM32_USART_BREAKS + bool "Add TIOxSBRK to support sending Breaks" + depends on STM32_USART + ---help--- + Add TIOCxBRK routines to send a line break per the STM32 manual, the + break will be a pulse based on the value M. This is not a BSD compatible + break. + +config STM32_SERIALBRK_BSDCOMPAT + bool "Use GPIO To send Break" + depends on STM32_USART_BREAKS + ---help--- + Enable using GPIO on the TX pin to send a BSD compatible break: + TIOCSBRK will start the break and TIOCCBRK will end the break. + The current STM32 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. + +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + +config STM32_PM_SERIAL_ACTIVITY + int "PM serial activity" + depends on PM + depends on STM32_USART + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +config USART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART1 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART1 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART1 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 + +config USART2_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART2 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART2 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART2 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 + +config USART3_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART3 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART3 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART3 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 + +config UART4_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART4 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART4 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART4 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 + +config UART5_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART5 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART5 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART5 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 + +config USART6_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART6 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART6 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART6 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 + +config UART7_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART7 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART7 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART7 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 + +config UART8_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART8 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART8 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART8 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 + +config UART9_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART9 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART9 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART9 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 + +config USART10_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART10 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART10 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART10 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 + +config USART11_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART11 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART11 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART11 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 + +config UART12_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART12 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART12 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART12 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 + +config USART1_RXFIFO_THRES + int "USART1 Rx FIFO Threshold" + depends on STM32_HAVE_USART_RXFIFO_THRESHOLD && STM32_USART && STM32_USART1_SERIALDRIVER + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config USART2_RXFIFO_THRES + int "USART2 Rx FIFO Threshold" + depends on STM32_HAVE_USART_RXFIFO_THRESHOLD && STM32_USART && STM32_USART2_SERIALDRIVER + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +if STM32_USART3 + +config USART3_RXFIFO_THRES + int "USART3 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_USART3 + +if STM32_UART4 + +config UART4_RXFIFO_THRES + int "UART4 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART4 + +if STM32_UART5 + +config UART5_RXFIFO_THRES + int "UART5 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART5 + +if STM32_USART6 + +config USART6_RXFIFO_THRES + int "USART6 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_USART + +if STM32_UART7 + +config UART7_RXFIFO_THRES + int "UART7 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART7 + +if STM32_UART8 + +config UART8_RXFIFO_THRES + int "UART8 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART8 + +config STM32_USART_INVERT + bool "Signal Invert Support" + depends on STM32_USART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the STM32F7 serial driver. + +config STM32_USART_SWAP + bool "Swap RX/TX pins support" + depends on STM32_USART + ---help--- + Enable RX/TX pin swapping support. The option enables support for the + TIOCSSWAP ioctl in the STM32F7 serial driver. + +source "arch/arm/src/common/stm32/Kconfig.lpuart" +source "arch/arm/src/common/stm32/Kconfig.hciuart" diff --git a/arch/arm/src/common/stm32/Kconfig.usb b/arch/arm/src/common/stm32/Kconfig.usb new file mode 100644 index 00000000000..7f4c969114e --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.usb @@ -0,0 +1,249 @@ +# +# STM32 USB configuration options. +# + +menu "USB Full Speed Host Configuration" + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + +config STM32_USBDRD_NCHANNELS + int "Number of host channels" + default 8 + range 1 8 + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + ---help--- + Number of USB host channels to use. + +config STM32_USBDRD_DESCSIZE + int "Descriptor buffer size" + default 128 + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + ---help--- + Size of descriptor/request buffers. + +endmenu + +config STM32_OTG_SOFOUTPUT + bool "OTG SOF output" + depends on STM32_HAVE_OTG_H7 + default n + +config STM32_OTG_USBREGEN + bool "Enable USB voltage regulator" + depends on STM32_HAVE_OTG_H7 + default n + +config STM32_USBHOST_REGDEBUG + bool "Register-Level Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Enable very low-level register access debug. + +config STM32_USBHOST_PKTDUMP + bool "Packet Dump Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Dump all incoming and outgoing USB packets. + +config STM32_USBFS_REGDEBUG + bool "Register-Level Debug" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO + ---help--- + Enable very low-level register access debug. + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + ---help--- + Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +menu "STM32_OTG_HS Configuration" + depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS + +choice + prompt "ULPI Selection" + default STM32_NO_ULPI + +config STM32_NO_ULPI + bool "No External ULPI" + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_EXTERNAL_ULPI + bool "External ULPI" + depends on STM32_HAVE_EXTERNAL_ULPI + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_INTERNAL_ULPI + bool "Internal ULPI PHY" + depends on STM32_HAVE_INTERNAL_ULPI + ---help--- + Select to enable the internal ULPI for USB HS + +endchoice # "ULPI Selection" + +endmenu # STM32_OTG_HS Configuration + +menu "OTG_HS Configuration" + depends on ARCH_CHIP_STM32H7 && STM32_OTGHS + +config STM32_OTGHS_FS + bool "OTGHS in FS mode" + default n + +choice + prompt "ULPI Selection" + default STM32_OTGHS_NO_ULPI + +config STM32_OTGHS_NO_ULPI + bool "No External ULPI on board." + ---help--- + Select to indicate that there is no external ULPI PHY. This means + the OTG_HS peripheral must use the internal full-speed PHY and will + be limited to full-speed mode. + +config STM32_OTGHS_EXTERNAL_ULPI + bool "External ULPI" + ---help--- + Select to indicate the presence of an external ULPI PHY and use it. + +endchoice # "ULPI Selection" + +endmenu # OTG_HS Configuration + +menu "OTG Configuration" + depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + +choice + prompt "STM32H7 OTGFS role" + depends on STM32_OTGFS + default STM32_OTGFS_USBDEV if USBDEV + default STM32_OTGFS_HOST if !USBDEV && USBHOST + +config STM32_OTGFS_USBDEV + bool "OTGFS as USBDEV" + depends on USBDEV + +config STM32_OTGFS_HOST + bool "OTGFS as HOST" + depends on USBHOST + +endchoice # "STM32H7 OTGFS role" + +choice + prompt "STM32H7 OTGHS role (only USBDEV supported for now)" + depends on STM32_OTGHS + default STM32_OTGHS_USBDEV if USBDEV + +config STM32_OTGHS_USBDEV + bool "OTGHS as USBDEV" + depends on USBDEV + +endchoice # "STM32H7 OTGHS role" + +endmenu # OTG Configuration + +menu "USB FS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST + +config STM32_OTGFS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGFS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGFS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGFS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG FS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB FS Host Configuration + +menu "USB HS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST + +config STM32_OTGHS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGHS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGHS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGHS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG HS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB HS Host Configuration + +config STM32_USBDEV_REGDEBUG + bool "OTG USBDEV REGDEBUG" + depends on STM32_COMMON_F7_H7 && USBDEV + +comment "USB Device Configuration" + +config STM32_USB_ITRMP + bool "Re-map USB interrupt" + default STM32_CAN1 + depends on STM32_USB && STM32_STM32F30XX + ---help--- + The legacy USB in the F1 series shared interrupt lines with USB + device and CAN1. In the F3 series, a hardware options was added to + either retain the legacy F1 behavior or to map the USB interrupts to + their own dedicated vectors. The option is available only for the + F3 family and selects the use of the dedicated USB interrupts. diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt index a725dcc6f90..6c370d70d10 100644 --- a/arch/arm/src/stm32/CMakeLists.txt +++ b/arch/arm/src/stm32/CMakeLists.txt @@ -75,7 +75,7 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) endif() -if(CONFIG_STM32_HAVE_IP_I2C_V1) +if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) if(CONFIG_STM32_I2C_ALT) list(APPEND SRCS stm32_i2c_alt.c) elseif(CONFIG_STM32_STM32F4XXX) @@ -83,7 +83,7 @@ if(CONFIG_STM32_HAVE_IP_I2C_V1) else() list(APPEND SRCS stm32_i2c.c) endif() -elseif(CONFIG_STM32_HAVE_IP_I2C_V2) +elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) list(APPEND SRCS stm32_i2c_v2.c) if(CONFIG_STM32_I2C_SLAVE) list(APPEND SRCS stm32_i2cslave_v2.c) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 939486a1bc4..4288bf0a6de 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1234,8 +1234,54 @@ config STM32_FLASH_CONFIG_Z bool config STM32_STM32L15XX + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_L1 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM3 select STM32_ENERGYLITE select STM32_HAVE_USBDEV @@ -1252,28 +1298,71 @@ config STM32_STM32L15XX select STM32_HAVE_ADC2 select STM32_HAVE_USART3 select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 config STM32_STM32F10XX + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 if !STM32F1_VALUELINE || STM32F1_HIGHDENSITY + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG if STM32F1_CONNECTIVITYLINE + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_BKP + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 if !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM3 select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_RTC_COUNTER select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 - select STM32_HAVE_IP_DBGMCU_V1 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1_BASIC - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 config STM32_CONNECTIVITYLINE bool @@ -1371,8 +1460,58 @@ config STM32_LOWDENSITY select STM32_HAVE_CAN1 if !STM32_VALUELINE config STM32_STM32F20XX + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_DCMI + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM3 select STM32_HAVE_FLASH_ICACHE select STM32_HAVE_FLASH_DCACHE @@ -1408,12 +1547,12 @@ config STM32_STM32F20XX select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 config STM32_STM32F205 bool @@ -1426,11 +1565,54 @@ config STM32_STM32F207 select STM32_HAVE_ETHMAC config STM32_STM32F30XX + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM4 select ARCH_HAVE_FPU - select STM32_HAVE_ADC1_DMA select STM32_HAVE_CAN1 select STM32_HAVE_DAC1 select STM32_HAVE_TIM1 @@ -1441,18 +1623,17 @@ config STM32_STM32F30XX select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 select STM32_HAVE_TSC - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 + select STM32_HAVE_IP_I2C_M3M4_V2 config STM32_STM32F302 bool default n select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 @@ -1463,17 +1644,60 @@ config STM32_STM32F303 bool default n select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA select STM32_HAVE_CCM select STM32_HAVE_TIM7 config STM32_STM32F33XX + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART2 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_HRTIM1 - select STM32_HAVE_HRTIM1_PLLCLK select STM32_HAVE_COMP2 select STM32_HAVE_COMP4 select STM32_HAVE_COMP6 @@ -1488,23 +1712,65 @@ config STM32_STM32F33XX select STM32_HAVE_TIM17 select STM32_HAVE_TSC select STM32_HAVE_ADC2 - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_ADC2_DMA select STM32_HAVE_CAN1 select STM32_HAVE_DAC1 select STM32_HAVE_DAC2 select STM32_HAVE_USART3 - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_COMP_V1 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_COMP_M3M4_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 + select STM32_HAVE_IP_I2C_M3M4_V2 config STM32_STM32F37XX + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_IP_SDADC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_USBDEV @@ -1528,16 +1794,68 @@ config STM32_STM32F37XX select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 select STM32_HAVE_USART3 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1_BASIC - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 + select STM32_HAVE_IP_I2C_M3M4_V2 config STM32_STM32F4XXX + select STM32_HAVE_OTGHS + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_DCMI + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_F4 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_LTDC_M3M4_V1 if STM32_HAVE_LTDC + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n select ARCH_CORTEXM4 + select STM32_HAVE_PWR select ARCH_HAVE_FPU select STM32_HAVE_FLASH_ICACHE select STM32_HAVE_FLASH_DCACHE @@ -1545,12 +1863,12 @@ config STM32_STM32F4XXX select STM32_HAVE_SPI2 select STM32_HAVE_I2C2 select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 config STM32_STM32F401xBC bool @@ -1760,6 +2078,8 @@ config STM32_STM32F427 # This is really 429/439, but we treat the two the same. config STM32_STM32F429 + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 bool default n select STM32_HAVE_OVERDRIVE @@ -1841,6 +2161,8 @@ config STM32_STM32F446 # This is really 469/479, but we treat the two the same. config STM32_STM32F469 + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 bool default n select STM32_HAVE_OVERDRIVE @@ -1884,18 +2206,68 @@ config STM32_STM32F469 select STM32_HAVE_I2C3 config STM32_STM32G4XXX + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_CORDIC_M3M4_V1 if STM32_HAVE_CORDIC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_G4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_DBGMCU_V3 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_COMP_V2 - select STM32_HAVE_IP_DAC_V2 + select STM32_HAVE_IP_DBGMCU_M3M4_V3 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_COMP_M3M4_V2 + select STM32_HAVE_IP_DAC_M3M4_V2 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - select STM32_HAVE_IP_TIMERS_V3 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V3 config STM32_STM32G4_CAT2 bool @@ -2025,8 +2397,8 @@ config STM32_STM32G47XX select STM32_HAVE_DAC2 select STM32_HAVE_DAC3 select STM32_HAVE_DAC4 - select STM32_HAVE_DMA1_CHAN8 - select STM32_HAVE_DMA2_CHAN678 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 select STM32_HAVE_FSMC select STM32_HAVE_FMAC select STM32_HAVE_FDCAN1 @@ -2100,269 +2472,27 @@ config STM32_STM32G474V select STM32_HAVE_UART4 select STM32_HAVE_UART5 -menu "STM32 Peripheral Support" +# --- restored family-specific symbols over-deleted by move-to-common (split recreates per-family) --- +if ARCH_CHIP_STM32 -# These are the peripheral selections proper - -config STM32_ADC5 - bool "ADC5" - default n - select STM32_ADC - depends on STM32_HAVE_ADC5 - select STM32_HAVE_ADC5_DMA if STM32_DMA2 - select STM32_HAVE_ADC5_DMA if STM32_DMAMUX - -config STM32_SDADC1 - bool "SDADC1" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC1_DMA if STM32_DMA2 - -config STM32_SDADC2 - bool "SDADC2" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC2_DMA if STM32_DMA2 - -config STM32_SDADC3 - bool "SDADC3" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC3 - select STM32_HAVE_SDADC3_DMA if STM32_DMA2 - -config STM32_COMP3 - bool "COMP3" - default n - select STM32_COMP - depends on STM32_HAVE_COMP3 - -config STM32_COMP4 - bool "COMP4" - default n - select STM32_COMP - depends on STM32_HAVE_COMP4 - -config STM32_COMP5 - bool "COMP5" - default n - select STM32_COMP - depends on STM32_HAVE_COMP5 - -config STM32_COMP6 - bool "COMP6" - default n - select STM32_COMP - depends on STM32_HAVE_COMP6 - -config STM32_COMP7 - bool "COMP7" - default n - select STM32_COMP - depends on STM32_HAVE_COMP7 - -config STM32_CCMDATARAM - bool "CMD/DATA RAM" - default n - depends on STM32_STM32F4XXX - -if STM32_DAC1 - -config STM32_DAC1CH1 - bool "DAC1CH1" - default n - -config STM32_DAC1CH2 - bool "DAC1CH2" - default n - -endif #STM32_DAC1 - -if STM32_DAC2 - -config STM32_DAC2CH1 - bool "DAC2CH1" - default n - -endif #STM32_DAC2 - -config STM32_DAC3 - bool "DAC3" - default n - depends on STM32_HAVE_DAC3 - select STM32_DAC - -if STM32_DAC3 - -config STM32_DAC3CH1 - bool "DAC3CH1 Internal" - default n - -config STM32_DAC3CH2 - bool "DAC3CH2 Internal" - default n - -endif #STM32_DAC3 - -config STM32_DAC4 - bool "DAC4" - default n - depends on STM32_HAVE_DAC4 - select STM32_DAC - -if STM32_DAC4 - -config STM32_DAC4CH1 - bool "DAC4CH1 Internal" - default n - -config STM32_DAC4CH2 - bool "DAC4CH2 Internal" - default n - -endif #STM32_DAC4 - -config STM32_HRTIM +config STM32_VALUELINE bool default n - -config STM32_HRTIM1 - bool "HRTIM1" - default n - depends on STM32_HAVE_HRTIM1 - select STM32_HRTIM - -if STM32_HRTIM1 - -config STM32_HRTIM_MASTER - bool "HRTIM MASTER" - default n - ---help--- - Enable HRTIM Master Timer - -config STM32_HRTIM_TIMA - bool "HRTIM TIMA" - default n - ---help--- - Enable HRTIM Timer A - -config STM32_HRTIM_TIMB - bool "HRTIM TIMB" - default n - ---help--- - Enable HRTIM Timer B - -config STM32_HRTIM_TIMC - bool "HRTIM TIMC" - default n - ---help--- - Enable HRTIM Timer C - -config STM32_HRTIM_TIMD - bool "HRTIM TIMD" - default n - ---help--- - Enable HRTIM Timer D - -config STM32_HRTIM_TIME - bool "HRTIM TIME" - default n - ---help--- - Enable HRTIM Timer E - -endif # STM32_HRTIM - -config STM32_I2C1_SLAVE - bool "I2C1 Slave" - default n - depends on !STM32_I2C1 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_I2C2_SLAVE - bool "I2C2 Slave" - default n - depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_I2C3_SLAVE - bool "I2C3 Slave" - default n - depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_OPAMP1 - bool "OPAMP1" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP1 - -config STM32_OPAMP2 - bool "OPAMP2" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP2 - -config STM32_OPAMP3 - bool "OPAMP3" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP3 - -config STM32_OPAMP4 - bool "OPAMP4" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP4 - -config STM32_UCPD - bool "UCPD (USB Type C Power Delivery)" - default n - depends on STM32_HAVE_UCPD - select USBDEV - -if STM32_LCD - -choice - prompt "Segment LCD Clock Source" - default LCD_LSECLOCK - -config LCD_LSICLOCK - bool "Internal Low Speed Clock" - -config LCD_LSECLOCK - bool "External Low Speed Clock" - -config LCD_HSECLOCK - bool "External High Speed Clock" - -endchoice -endif # STM32_LCD - -endmenu - -config STM32_SDADC - bool - default n - -config STM32_I2C_SLAVE - bool - default n - -config STM32_CAP - bool - default n - -config STM32_NOEXT_VECTORS - bool "Disable the ARMv7-M EXT vectors" - default n - ---help--- - Sometimes you may not need any Vector support beyond SysTick - and wish to save memory. This applies only to ARMv7-M architectures. - -menu "Alternate Pin Mapping" - depends on STM32_STM32F10XX || STM32_CONNECTIVITYLINE + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_SPI2 if STM32_HIGHDENSITY + select STM32_HAVE_SPI3 if STM32_HIGHDENSITY choice prompt "CAN1 Alternate Pin Mappings" @@ -2542,1887 +2672,4 @@ config STM32_USART3_PARTIAL_REMAP endchoice -endmenu - -config STM32_FLASH_ICACHE - bool "Enable FLASH Instruction Cache" - default y - depends on STM32_HAVE_FLASH_ICACHE - ---help--- - Enable the FLASH instruction cache. - -config STM32_FLASH_DCACHE - bool "Enable FLASH Data Cache" - default y - depends on STM32_HAVE_FLASH_DCACHE - ---help--- - Enable the FLASH data cache. - -config STM32_FORCEPOWER - bool "Force power" - default n - ---help--- - Timer and I2C devices may need to the following to force power to be applied - unconditionally at power up. (Otherwise, the device is powered when it is - initialized). - -config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32_SAIPLL - bool "SAIPLL" - default n - depends on STM32_HAVE_SAIPLL - ---help--- - The STM32F446 has a separate PLL for the SAI block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_I2SPLL - bool "I2SPLL" - default n - depends on STM32_HAVE_I2SPLL - ---help--- - The STM32F446 has a separate PLL for the I2S block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_CCMEXCLUDE - bool "Exclude CCM SRAM from the heap" - default ARCH_DMA || LIBC_ARCH_ELF - depends on STM32_HAVE_CCM - ---help--- - Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA - and (2) it appears to be impossible to execute ELF modules from CCM - RAM. - -config STM32_CCM_PROCFS - bool "CCM PROCFS support" - default n - depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER - ---help--- - Select to build in support for /proc/ccm. Reading from /proc/ccm - will provide statistics about CCM memory use similar to what you - would get from mallinfo() for the user heap. - -menu "Timer Configuration" - depends on STM32_TIM - -if STM32_TIM9_CAP - -config STM32_TIM9_CLOCK - int "TIM9 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM9_CAP - -if STM32_TIM10_CAP - -config STM32_TIM10_CLOCK - int "TIM10 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM10_CAP - -if STM32_TIM11_CAP - -config STM32_TIM11_CLOCK - int "TIM11 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM11_CAP - -endmenu # Timer Configuration - -menu "HRTIM Configuration" - depends on STM32_HRTIM - -config STM32_HRTIM_DISABLE_CHARDRV - bool "HRTIM Disable Character Driver" - default n - ---help--- - In most cases we do not need HRTIM Character Driver, so we can disable it - and save some memory. - -config STM32_HRTIM_NO_ENABLE_TIMERS - bool "Do not enable HRTIM timers at startup" - default n - ---help--- - Do not enable HRTIM timers at startup - -menuconfig STM32_HRTIM_ADC - bool "HRTIM ADC Triggering" - default n - ---help--- - Enable HRTIM ADC Triggering support. - -if STM32_HRTIM_ADC - -config STM32_HRTIM_ADC1_TRG1 - bool "HRTIM ADC1 Trigger 1" - default n - -config STM32_HRTIM_ADC1_TRG2 - bool "HRTIM ADC1 Trigger 2" - default n - -config STM32_HRTIM_ADC1_TRG3 - bool "HRTIM ADC1 Trigger 3" - default n - -config STM32_HRTIM_ADC1_TRG4 - bool "HRTIM ADC1 Trigger 4" - default n - -config STM32_HRTIM_ADC2_TRG1 - bool "HRTIM ADC2 Trigger 1" - default n - -config STM32_HRTIM_ADC2_TRG2 - bool "HRTIM ADC2 Trigger 2" - default n - -config STM32_HRTIM_ADC2_TRG3 - bool "HRTIM ADC2 Trigger 3" - default n - -config STM32_HRTIM_ADC2_TRG4 - bool "HRTIM ADC2 Trigger 4" - default n - -endif # STM32_HRTIM_ADC - -config STM32_HRTIM_DAC - bool "HRTIM DAC Triggering" - default n - ---help--- - Enable HRTIM DAC Triggering support. - -config STM32_HRTIM_PWM - bool "HRTIM PWM Outputs" - default n - ---help--- - Enable HRTIM PWM Outputs support. - -config STM32_HRTIM_CAP - bool "HRTIM Capture" - default n - ---help--- - Enable HRTIM Capture support. - -config STM32_HRTIM_INTERRUPTS - bool "HRTIM Interrupts" - default n - ---help--- - Enable HRTIM Interrupts support. - -config STM32_HRTIM_BURST - bool "HRTIM Burst Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Burst Mode support for PWM outputs. - -config STM32_HRTIM_DEADTIME - bool "HRTIM Dead-time" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Deadtime support for PWM outputs. - -config STM32_HRTIM_PUSHPULL - bool "HRTIM Push-Pull Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Push-Pull Mode support for PWM outputs. - -config STM32_HRTIM_CHOPPER - bool "HRTIM Chopper" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Chopper Mode for PWM outputs. - -config STM32_HRTIM_DMA - bool "HRTIM DMA" - default n - -config STM32_HRTIM_DMABURST - bool "HRTIM DMA Burst" - default n - -config STM32_HRTIM_AUTODELAY - bool "HRTIM Autodelay" - depends on STM32_HRTIM_PWM - default n - -menuconfig STM32_HRTIM_EVENTS - bool "HRTIM Events Configuration" - default n - ---help--- - Enable HRTIM Events support. - -if STM32_HRTIM_EVENTS - -config STM32_HRTIM_EEV1 - bool "HRTIM EEV1" - default n - -config STM32_HRTIM_EEV2 - bool "HRTIM EEV2" - default n - -config STM32_HRTIM_EEV3 - bool "HRTIM EEV3" - default n - -config STM32_HRTIM_EEV4 - bool "HRTIM EEV4" - default n - -config STM32_HRTIM_EEV5 - bool "HRTIM EEV5" - default n - -config STM32_HRTIM_EEV6 - bool "HRTIM EEV6" - default n - -config STM32_HRTIM_EEV7 - bool "HRTIM EEV7" - default n - -config STM32_HRTIM_EEV8 - bool "HRTIM EEV8" - default n - -config STM32_HRTIM_EEV9 - bool "HRTIM EEV9" - default n - -config STM32_HRTIM_EEV10 - bool "HRTIM EEV10" - default n - -endif # STM32_HRTIM_EVENTS - -menuconfig STM32_HRTIM_FAULTS - bool "HRTIM Faults Configuration" - default n - ---help--- - Enable HRTIM Faults support. - -if STM32_HRTIM_FAULTS - -config STM32_HRTIM_FAULT1 - bool "HRTIM Fault 1" - default n - -config STM32_HRTIM_FAULT2 - bool "HRTIM Fault 2" - default n - -config STM32_HRTIM_FAULT3 - bool "HRTIM Fault 3" - default n - -config STM32_HRTIM_FAULT4 - bool "HRTIM Fault 4" - default n - -endif # STM32_HRTIM_FAULTS - -config STM32_HRTIM_CLK_FROM_PLL - bool "HRTIM Clock from PLL" - default n - depends on STM32_HAVE_HRTIM1_PLLCLK - ---help--- - Set PLL as the clock source for HRTIM. - This configuration requires the following conditions: - 1) system clock is PLL, - 2) SYSCLK and PCLK2 ratio must be 1 o 2. - -menu "HRTIM Master Configuration" - depends on STM32_HRTIM_MASTER - -config STM32_HRTIM_MASTER_DAC - bool "HRTIM Master DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_MASTER_DMA - bool "HRTIM MASTER DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_MASTER_IRQ - bool "HRTIM MASTER Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -endmenu # "HRTIM Master Configuration" - -menu "HRTIM Timer A Configuration" - depends on STM32_HRTIM_TIMA - -config STM32_HRTIM_TIMA_CAP - bool "HRTIM TIMA Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMA_DAC - bool "HRTIM TIMA DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMA_DMA - bool "HRTIM TIMA DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMA_IRQ - bool "HRTIM TIMA Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMA_PWM - bool "HRTIM TIMA PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMA_PWM_CH1 - bool "HRTIM TIMA PWM Output 1" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_PWM_CH2 - bool "HRTIM TIMA PWM Output 2" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_BURST - bool "HRTIM TIMA Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_BURST_CH1 - bool "HRTIM TIMA Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) - -config STM32_HRTIM_TIMA_BURST_CH2 - bool "HRTIM TIMA Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) - -config STM32_HRTIM_TIMA_CHOP - bool "HRTIM TIMA PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_DT - bool "HRTIM TIMA PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_PSHPLL - bool "HRTIM TIMA PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) - -endmenu # "HRTIM Timer A Configuration" - -menu "HRTIM Timer B Configuration" - depends on STM32_HRTIM_TIMB - -config STM32_HRTIM_TIMB_CAP - bool "HRTIM TIMB Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMB_DAC - bool "HRTIM TIMB DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMB_DMA - bool "HRTIM TIMB DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMB_IRQ - bool "HRTIM TIMB Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMB_PWM - bool "HRTIM TIMB PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMB_PWM_CH1 - bool "HRTIM TIMB PWM Output 1" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_PWM_CH2 - bool "HRTIM TIMB PWM Output 2" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_BURST - bool "HRTIM TIMB Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_BURST_CH1 - bool "HRTIM TIMB Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) - -config STM32_HRTIM_TIMB_BURST_CH2 - bool "HRTIM TIMB Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) - -config STM32_HRTIM_TIMB_CHOP - bool "HRTIM TIMB PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_DT - bool "HRTIM TIMB PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_PSHPLL - bool "HRTIM TIMB PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) - -endmenu # "HRTIM Timer B Configuration" - -menu "HRTIM Timer C Configuration" - depends on STM32_HRTIM_TIMC - -config STM32_HRTIM_TIMC_CAP - bool "HRTIM TIMC Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMC_DAC - bool "HRTIM TIMC DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMC_DMA - bool "HRTIM TIMC DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMC_IRQ - bool "HRTIM TIMC Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMC_PWM - bool "HRTIM TIMC PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMC_PWM_CH1 - bool "HRTIM TIMC PWM Output 1" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_PWM_CH2 - bool "HRTIM TIMC PWM Output 2" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_BURST - bool "HRTIM TIMC Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_BURST_CH1 - bool "HRTIM TIMC Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) - -config STM32_HRTIM_TIMC_BURST_CH2 - bool "HRTIM TIMC Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) - -config STM32_HRTIM_TIMC_CHOP - bool "HRTIM TIMC PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_DT - bool "HRTIM TIMC PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_PSHPLL - bool "HRTIM TIMC PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) - -endmenu # "HRTIM Timer C Configuration" - -menu "HRTIM Timer D Configuration" - depends on STM32_HRTIM_TIMD - -config STM32_HRTIM_TIMD_CAP - bool "HRTIM TIMD Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMD_DAC - bool "HRTIM TIMD DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMD_DMA - bool "HRTIM TIMD DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMD_IRQ - bool "HRTIM TIMD Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMD_PWM - bool "HRTIM TIMD PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMD_PWM_CH1 - bool "HRTIM TIMD PWM Output 1" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_PWM_CH2 - bool "HRTIM TIMD PWM Output 2" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_BURST - bool "HRTIM TIMD Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_BURST_CH1 - bool "HRTIM TIMD Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) - -config STM32_HRTIM_TIMD_BURST_CH2 - bool "HRTIM TIMD Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) - -config STM32_HRTIM_TIMD_CHOP - bool "HRTIM TIMD PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_DT - bool "HRTIM TIMD PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_PSHPLL - bool "HRTIM TIMD PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) - -endmenu # "HRTIM Timer D Configuration" - -menu "HRTIM Timer E Configuration" - depends on STM32_HRTIM_TIME - -config STM32_HRTIM_TIME_CAP - bool "HRTIM TIME Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIME_DAC - bool "HRTIM TIME DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIME_DMA - bool "HRTIM TIME DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIME_IRQ - bool "HRTIM TIME Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIME_PWM - bool "HRTIM TIME PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIME_PWM_CH1 - bool "HRTIM TIME PWM Output 1" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_PWM_CH2 - bool "HRTIM TIME PWM Output 2" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_BURST - bool "HRTIM TIME Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_BURST_CH1 - bool "HRTIM TIME Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) - -config STM32_HRTIM_TIME_BURST_CH2 - bool "HRTIM TIME Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) - -config STM32_HRTIM_TIME_CHOP - bool "HRTIM TIME PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_DT - bool "HRTIM TIME PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_PSHPLL - bool "HRTIM TIME PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) - -endmenu # "HRTIM Timer E Configuration" - -endmenu # "HRTIM Configuration" - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC4_RESOLUTION - int "ADC4 resolution" - depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC5_RESOLUTION - int "ADC5 resolution" - depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC4_DMA - bool "ADC4 DMA" - depends on STM32_ADC4 && STM32_HAVE_ADC4_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC4_DMA_CFG - int "ADC4 DMA configuration" - depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode - -config STM32_ADC4_DMA_BATCH - int "ADC4 DMA number of conversions" - depends on STM32_ADC4 && STM32_ADC4_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC4_ANIOC_TRIGGER - int "ADC4 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC4 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC5_DMA - bool "ADC5 DMA" - depends on STM32_ADC5 && STM32_HAVE_ADC5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC5_DMA_CFG - int "ADC5 DMA configuration" - depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode - -config STM32_ADC5_DMA_BATCH - int "ADC5 DMA number of conversions" - depends on STM32_ADC5 && STM32_ADC5_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC4_INJECTED_CHAN - int "ADC4 injected channels" - depends on STM32_ADC4 - range 0 4 - default 0 - ---help--- - Support for ADC4 injected channels. - -config STM32_ADC5_INJECTED_CHAN - int "ADC5 injected channels" - depends on STM32_ADC5 - range 0 4 - default 0 - ---help--- - Support for ADC5 injected channels. - -config STM32_ADC4_EXTSEL - bool "ADC4 external trigger for regular group" - depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER - default n - ---help--- - Enable EXTSEL for ADC4. - -config STM32_ADC5_EXTSEL - bool "ADC5 external trigger for regular group" - depends on STM32_ADC5 && !STM32_HAVE_ADC5_TIMER - default n - ---help--- - Enable EXTSEL for ADC5. - -config STM32_ADC4_JEXTSEL - bool "ADC4 external trigger for injected group" - depends on STM32_ADC4 - default n - ---help--- - Enable JEXTSEL for ADC4. - -config STM32_ADC5_JEXTSEL - bool "ADC5 external trigger for injected group" - depends on STM32_ADC5 - default n - ---help--- - Enable JEXTSEL for ADC5. - -endmenu - -menu "COMP Configuration" - depends on STM32_COMP && STM32_HAVE_IP_COMP_V2 - -config STM32_COMP1_OUT - bool "COMP1 GPIO Output" - depends on STM32_COMP1 - default n - ---help--- - Enables COMP1 output. - -config STM32_COMP1_INM - int "COMP1 inverting input assignment" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects COMP1 inverting input pin. - -config STM32_COMP1_INP - int "COMP1 non-inverting input assignment" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 non-inverting input pin. - -config STM32_COMP1_POL - int "COMP1 polarity" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 output polarity. - -config STM32_COMP1_HYST - int "COMP1 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP1. - -config STM32_COMP1_BLANKSEL - int "COMP1 blanking signal select" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP1. - -config STM32_COMP1_LOCK - int "COMP1 COMP_CxCSR register lock" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP2_OUT - bool "COMP2 GPIO Output" - depends on STM32_COMP2 - default n - ---help--- - Enables COMP2 output. - -config STM32_COMP2_INM - int "COMP2 inverting input assignment" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects COMP2 inverting input pin. - -config STM32_COMP2_INP - int "COMP2 non-inverting input assignment" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 non-inverting input pin. - -config STM32_COMP2_POL - int "COMP2 polarity" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 output polarity. - -config STM32_COMP2_HYST - int "COMP2 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP2. - -config STM32_COMP2_BLANKSEL - int "COMP2 blanking signal select" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP2. - -config STM32_COMP2_LOCK - int "COMP2 COMP_CxCSR register lock" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP3_OUT - bool "COMP3 GPIO Output" - depends on STM32_COMP3 - default n - ---help--- - Enables COMP3 output. - -config STM32_COMP3_INM - int "COMP3 inverting input assignment" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects COMP3 inverting input pin. - -config STM32_COMP3_INP - int "COMP3 non-inverting input assignment" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 non-inverting input pin. - -config STM32_COMP3_POL - int "COMP3 polarity" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 output polarity. - -config STM32_COMP3_HYST - int "COMP3 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP3. - -config STM32_COMP3_BLANKSEL - int "COMP3 blanking signal select" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP3. - -config STM32_COMP3_LOCK - int "COMP3 COMP_CxCSR register lock" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP4_OUT - bool "COMP4 GPIO Output" - depends on STM32_COMP4 - default n - ---help--- - Enables COMP4 output. - -config STM32_COMP4_INM - int "COMP4 inverting input assignment" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects COMP4 inverting input pin. - -config STM32_COMP4_INP - int "COMP4 non-inverting input assignment" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 non-inverting input pin. - -config STM32_COMP4_POL - int "COMP4 polarity" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 output polarity. - -config STM32_COMP4_HYST - int "COMP4 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP4. - -config STM32_COMP4_BLANKSEL - int "COMP4 blanking signal select" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP4. - -config STM32_COMP4_LOCK - int "COMP4 COMP_CxCSR register lock" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP5_OUT - bool "COMP5 GPIO Output" - depends on STM32_COMP5 - default n - ---help--- - Enables COMP5 output. - -config STM32_COMP5_INM - int "COMP5 inverting input assignment" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects COMP5 inverting input pin. - -config STM32_COMP5_INP - int "COMP5 non-inverting input assignment" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 non-inverting input pin. - -config STM32_COMP5_POL - int "COMP5 polarity" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 output polarity. - -config STM32_COMP5_HYST - int "COMP5 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP5. - -config STM32_COMP5_BLANKSEL - int "COMP5 blanking signal select" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP5. - -config STM32_COMP5_LOCK - int "COMP5 COMP_CxCSR register lock" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP6_OUT - bool "COMP6 GPIO Output" - depends on STM32_COMP6 - default n - ---help--- - Enables COMP6 output. - -config STM32_COMP6_INM - int "COMP6 inverting input assignment" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects COMP6 inverting input pin. - -config STM32_COMP6_INP - int "COMP6 non-inverting input assignment" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 non-inverting input pin. - -config STM32_COMP6_POL - int "COMP6 polarity" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 output polarity. - -config STM32_COMP6_HYST - int "COMP6 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP6. - -config STM32_COMP6_BLANKSEL - int "COMP6 blanking signal select" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP6. - -config STM32_COMP6_LOCK - int "COMP6 COMP_CxCSR register lock" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP7_OUT - bool "COMP7 GPIO Output" - depends on STM32_COMP7 - default n - ---help--- - Enables COMP7 output. - -config STM32_COMP7_INM - int "COMP7 inverting input assignment" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects COMP7 inverting input pin. - -config STM32_COMP7_INP - int "COMP7 non-inverting input assignment" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 non-inverting input pin. - -config STM32_COMP7_POL - int "COMP7 polarity" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 output polarity. - -config STM32_COMP7_HYST - int "COMP7 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP7. - -config STM32_COMP7_BLANKSEL - int "COMP7 blanking signal select" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP7. - -config STM32_COMP7_LOCK - int "COMP7 COMP_CxCSR register lock" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -endmenu - -menu "SDADC Configuration" - depends on STM32_SDADC - -config STM32_SDADC1_DMA - bool "SDADC1 DMA" - depends on STM32_SDADC1 && STM32_HAVE_SDADC1_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC2_DMA - bool "SDADC2 DMA" - depends on STM32_SDADC2 && STM32_HAVE_SDADC2_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC3_DMA - bool "SDADC3 DMA" - depends on STM32_SDADC3 && STM32_HAVE_SDADC3_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -menu "DAC Configuration" - depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 - -config STM32_DAC1CH1_MODE - int "DAC1CH1 channel mode" - depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH1_DMA - bool "DAC1CH1 DMA" - depends on STM32_DAC1CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH1_DMA - -config STM32_DAC1CH1_DMA_BUFFER_SIZE - int "DAC1CH1 DMA buffer size" - default 256 - -config STM32_DAC1CH1_DMA_EXTERNAL - bool "DAC1CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH1_HRTIM_TRG1 - bool "DAC1CH1 HRTIM Trigger 1" - default n - -config STM32_DAC1CH1_HRTIM_TRG2 - bool "DAC1CH1 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH1_TIMER - int "DAC1CH1 timer" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH1_TIMER_FREQUENCY - int "DAC1CH1 timer frequency" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - default 0 - endif - -config STM32_DAC1CH2_MODE - int "DAC1CH2 channel mode" - depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH2_DMA - bool "DAC1CH2 DMA" - depends on STM32_DAC1CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH2_DMA - -config STM32_DAC1CH2_DMA_BUFFER_SIZE - int "DAC1CH2 DMA buffer size" - default 256 - -config STM32_DAC1CH2_DMA_EXTERNAL - bool "DAC1CH2 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH2_HRTIM_TRG1 - bool "DAC1CH2 HRTIM Trigger 1" - default n - -config STM32_DAC1CH2_HRTIM_TRG2 - bool "DAC1CH2 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH2_TIMER - int "DAC1CH2 timer" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH2_TIMER_FREQUENCY - int "DAC1CH2 timer frequency" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC2CH1_MODE - int "DAC2CH1 channel mode" - depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC2CH1_DMA - bool "DAC2CH1 DMA" - depends on STM32_DAC2CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC2CH1_DMA - -config STM32_DAC2CH1_DMA_BUFFER_SIZE - int "DAC2CH1 DMA buffer size" - default 256 - -config STM32_DAC2CH1_DMA_EXTERNAL - bool "DAC2CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC2CH1_HRTIM_TRG3 - bool "DAC2CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC2CH1_TIMER - int "DAC2CH1 timer" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC2CH1_TIMER_FREQUENCY - int "DAC2CH1 timer frequency" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH1_MODE - int "DAC3CH1 channel mode" - depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH1_DMA - bool "DAC3CH1 DMA" - depends on STM32_DAC3CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH1_DMA - -config STM32_DAC3CH1_DMA_BUFFER_SIZE - int "DAC3CH1 DMA buffer size" - default 256 - -config STM32_DAC3CH1_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH1_HRTIM_TRG3 - bool "DAC3CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH1_TIMER - int "DAC3CH1 timer" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH1_TIMER_FREQUENCY - int "DAC3CH1 timer frequency" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH2_MODE - int "DAC3CH2 channel mode" - depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH2_DMA - bool "DAC3CH2 DMA" - depends on STM32_DAC3CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH2_DMA - -config STM32_DAC3CH2_DMA_BUFFER_SIZE - int "DAC3CH2 DMA buffer size" - default 256 - -config STM32_DAC3CH2_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH2_HRTIM_TRG3 - bool "DAC3CH2 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH2_TIMER - int "DAC3CH2 timer" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH2_TIMER_FREQUENCY - int "DAC3CH2 timer frequency" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - -endif - -endmenu - -config STM32_HCIUART_RXDMA - bool - default n - -menu "U[S]ART Configuration" - depends on STM32_USART - -comment "U[S]ART Device Configuration" - -if STM32_USART1_HCIUART - -config STM32_HCIUART1_RXBUFSIZE - int "HCI UART1 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART1_TXBUFSIZE - int "HCI UART1 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART1_BAUD - int "HCI UART1 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART1_RXDMA - bool "HCI UART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART1_HCIUART - -if STM32_USART2_HCIUART - -config STM32_HCIUART2_RXBUFSIZE - int "HCI UART2 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART2_TXBUFSIZE - int "HCI UART2 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART2_BAUD - int "HCI UART2 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART2_RXDMA - bool "HCI UART2 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART2_HCIUART - -if STM32_USART3_HCIUART - -config STM32_HCIUART3_RXBUFSIZE - int "HCI UART3 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART3_TXBUFSIZE - int "HCI UART3 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART3_BAUD - int "HCI UART3 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART3_RXDMA - bool "HCI UART3 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART3_HCIUART - -if STM32_USART6_HCIUART - -config STM32_HCIUART6_RXBUFSIZE - int "HCI UART6 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART6_TXBUFSIZE - int "HCI UART6 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART6_BAUD - int "HCI UART6 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART6_RXDMA - bool "HCI UART6 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART6_HCIUART - -if STM32_LPUART1_SERIALDRIVER - -config LPUART1_TXDMA - bool "LPUART1 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_LPUART1_SERIALDRIVER - -menu "HCI UART Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_HCIUART_RXDMA_BUFSIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - depends on STM32_HCIUART_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_HCIUART_RXDMAPRIO - hex "HCI UART DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - depends on STM32_HCIUART_RXDMA - ---help--- - Select HCI UART DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_HCIUART_SW_RXFLOW - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Current STM32 have - broken HW based RTS behavior (they assert nRTS after every byte - received) Enable this setting workaround this issue by using - software based management of RTS - - If HCI UART DMA is enabled, this is probably the better selection - as well. In that case, the Rx DMA buffer will avoid Rx overrun due - to short, bursty activity. Software RTS management will probably - result in overall better throughput and should still avoid Rx data - overrun conditions. - -config STM32_HCIUART_UPPER_WATERMARK - int "RTS flow control upper watermark (%)" - default 75 - range 2 100 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be asserted - when this amount of Rx data has been buffered. The amount is - expressed as a percentage of the Rx buffer size. - -config STM32_HCIUART_LOWER_WATERMARK - int "RTS flow control lower watermark (%)" - default 25 - range 1 99 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be de-asserted - when there is less than this amount ofdata in the Rx buffere. The - amount is expressed as a percentage of the Rx buffer size. - -endmenu # HCI UART Driver Configuration - -endmenu # U[S]ART Configuration - -menu "I2S Configuration" - depends on STM32_I2S3 - -config STM32_I2S_MCK - bool "I2S_MCK" - default n - ---help--- - TBD. - -comment "I2S3 Configuration" - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32_I2C - -config STM32_I2C_ALT - bool "Alternate I2C implementation" - default STM32_PERFORMANCELINE - depends on !STM32_STM32F30XX - ---help--- - This selection enables an alternative I2C driver. This alternate - driver implements some rather complex workarounds for errata against - the STM32 F103 "Performance Line". This selection is an option - because: (1) It has not yet been fully verified and (2) It is not - certain that he scope of this workaround is needed only for the F103. - -config STM32_I2C_DUTY16_9 - bool "Frequency with Tlow/Thigh = 16/9" - default n - depends on STM32_I2C - -config STM32_I2C_DMA - bool "I2C DMA Support" - default n - depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED - ---help--- - This option enables the DMA for I2C transfers. - Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the - I2C dma streams, else the default priority level is set to medium. - -endmenu - -menu "I2C Slave Configuration" - depends on STM32_I2C_SLAVE - -config STM32_I2C_SLAVE_DEFAULT_TX - hex "Default TX byte to be sent when the TX buffer is empty" - default 0xFF - -config STM32_I2C_SLAVE_USEWQ - bool "Use work queue to delegate the isr completion status" - default n - ---help--- - With the current upperhalf I2C slave driver implementation, the user - should delegate the callback completion status using a work queue. - However, work queues introduce a delay, so in certain scenarios - it is better to use a custom driver without using a work queue. - -config STM32_I2C_SLAVE_RETRANSFER - bool "The frame is retransferred when stop is issued beforehand" - default n - ---help--- - If stop is issued before the whole frame is transferred, - the tx pointer is reset to 0. - -endmenu - -comment "USB Device Configuration" - -config STM32_USB_ITRMP - bool "Re-map USB interrupt" - default STM32_CAN1 - depends on STM32_USB && STM32_STM32F30XX - ---help--- - The legacy USB in the F1 series shared interrupt lines with USB - device and CAN1. In the F3 series, a hardware options was added to - either retain the legacy F1 behavior or to map the USB interrupts to - their own dedicated vectors. The option is available only for the - F3 family and selects the use of the dedicated USB interrupts. - -config STM32_QE - bool - default n - -if STM32_FOC - -config STM32_FOC_USE_ADC4 - bool - default n - select STM32_ADC4 - select STM32_ADC3_JEXTSEL - -config STM32_FOC_G4_ADCCHAN0_WORKAROUND - bool "FOC G4 ADC channel 0 unwanted conversion workaround" - default n - depends on STM32_STM32G4XXX - ---help--- - Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 - conversion when a regular conversion is interrupted by an injected conversion. - This FOC implementation uses injected conversion to sample phase currents - and allows user to use regular conversion as an auxiliary analog conversion. - In this case, there is a certain probability that regular conversion will be - interrupted by an injected conversion that will lead to an incorrect reading - of phase currents. - - This workaround inserts a dummy conversion at the beginning of the injected - sequence. For more details look at the chip errata documents. - -endif #STM32_FOC diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 32c30a76ee7..0f0b7e4cd0f 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -59,7 +59,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V1),y) +ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) ifeq ($(CONFIG_STM32_I2C_ALT),y) CHIP_CSRCS += stm32_i2c_alt.c else ifeq ($(CONFIG_STM32_STM32F4XXX),y) @@ -67,7 +67,7 @@ CHIP_CSRCS += stm32f40xxx_i2c.c else CHIP_CSRCS += stm32_i2c.c endif -else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V2),y) +else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y) CHIP_CSRCS += stm32_i2c_v2.c ifeq ($(CONFIG_STM32_I2C_SLAVE),y) CHIP_CSRCS += stm32_i2cslave_v2.c diff --git a/arch/arm/src/stm32/hardware/stm32_adc.h b/arch/arm/src/stm32/hardware/stm32_adc.h index 4bfee933c6e..49df6093b60 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc.h +++ b/arch/arm/src/stm32/hardware/stm32_adc.h @@ -46,18 +46,18 @@ * too much to keep it in the same file as ADC IPv2. */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && \ - defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && \ + defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # error Only one STM32 ADC IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # if defined(CONFIG_STM32_STM32L15XX) # include "stm32_adc_v1l1.h" /* Special case for L1 */ # else # include "stm32_adc_v1.h" # endif -#elif defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) # include "stm32_adc_v2g4.h" /* Special case for G4 */ # else diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1.h index 2d4432ca128..d1ba76649c3 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1.h +++ b/arch/arm/src/stm32/hardware/stm32_adc_v1.h @@ -54,7 +54,7 @@ * - ... */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1_BASIC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC) # define HAVE_BASIC_ADC #else # undef HAVE_BASIC_ADC diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/stm32/hardware/stm32_adc_v2.h index 09a83fa13bf..6e62bb59a74 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h +++ b/arch/arm/src/stm32/hardware/stm32_adc_v2.h @@ -57,7 +57,7 @@ * TODO: definitions for basic STM32 ADC IPv2 (F0, L0) */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V2_BASIC +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2_BASIC # define HAVE_BASIC_ADC # error TODO #else diff --git a/arch/arm/src/stm32/hardware/stm32_comp.h b/arch/arm/src/stm32/hardware/stm32_comp.h index 414f7e62739..b950d622b07 100644 --- a/arch/arm/src/stm32/hardware/stm32_comp.h +++ b/arch/arm/src/stm32/hardware/stm32_comp.h @@ -39,13 +39,13 @@ /* If more than one COMP IP ensure that only one is selected */ -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # if defined(CONFIG_STM32_STM32F33XX) # include "stm32f33xxx_comp.h" # else # error "Device not supported." # endif -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) # include "stm32g4xxxx_comp.h" # else diff --git a/arch/arm/src/stm32/hardware/stm32_dac.h b/arch/arm/src/stm32/hardware/stm32_dac.h index b04b56b3d16..34aa92ce260 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac.h +++ b/arch/arm/src/stm32/hardware/stm32_dac.h @@ -36,14 +36,14 @@ * 2. STM32 DAC IPv2: G4 */ -#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) && \ - defined(CONFIG_STM32_HAVE_IP_DAC_V2) +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) && \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) # error Only one STM32 DAC IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # include "stm32_dac_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DAC_V2) +#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) # include "stm32gxxxxx_dac.h" /* Special case for G4 */ # else diff --git a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h index d1b6946f8bd..ce905d218d7 100644 --- a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h @@ -39,11 +39,11 @@ #define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ #define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 # define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ # define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ #endif -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 # define STM32_DBGMCU_APB1_FZ1 0xe0042008 /* Debug MCU APB1 freeze 1 register */ # define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze 2 register */ # define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */ @@ -72,7 +72,7 @@ # define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ # define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V1 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 # define DBGMCU_CR_IWDGSTOP (1 << 8) /* Bit 8: Independent Watchdog stopped when core is halted */ # define DBGMCU_CR_WWDGSTOP (1 << 9) /* Bit 9: Window Watchdog stopped when core is halted */ # define DBGMCU_CR_TIM1STOP (1 << 10) /* Bit 10: TIM1 stopped when core is halted */ @@ -87,9 +87,9 @@ # define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */ # define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */ # define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */ -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V1 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 /* Debug MCU APB1 freeze register */ @@ -147,9 +147,9 @@ # define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */ # define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */ #endif -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 /* Debug MCU APB1 freeze 1 register */ @@ -180,7 +180,7 @@ # define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */ # define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */ -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 */ /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32/hardware/stm32_i2c.h b/arch/arm/src/stm32/hardware/stm32_i2c.h index 18c5f75cfa5..dd0a6f68872 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32/hardware/stm32_i2c.h @@ -32,9 +32,9 @@ * 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4 */ -#if defined(CONFIG_STM32_HAVE_IP_I2C_V1) +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) # include "stm32_i2c_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_I2C_V2) +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) # include "stm32_i2c_v2.h" #else # error STM32 I2C IP version not specified diff --git a/arch/arm/src/stm32/hardware/stm32_tim.h b/arch/arm/src/stm32/hardware/stm32_tim.h index 7adb23e6567..3815bf402db 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim.h +++ b/arch/arm/src/stm32/hardware/stm32_tim.h @@ -27,10 +27,10 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) # include "stm32_tim_v1v2.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V3) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) # include "stm32_tim_v3.h" #else # error "STM32 TIMER IP version not specified" diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h index bc1408b4847..44b35d1140f 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h @@ -42,9 +42,9 @@ * - 4-bit SMS in SMCR register */ -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) # define HAVE_IP_TIMERS_V2 -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) # define HAVE_IP_TIMERS_V1 #else # error diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index cd53b780eb4..331b4f1b795 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -308,7 +308,7 @@ /* ADC resolution. Not supported for basic STM32 ADC IPv1 */ -#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # define HAVE_ADC_RESOLUTION #else # undef HAVE_ADC_RESOLUTION @@ -316,7 +316,7 @@ /* ADC have common registers for all cores except basic ADC IPv1 (F1, F37x) */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # undef HAVE_ADC_CMN_REGS #else # define HAVE_ADC_CMN_REGS @@ -333,7 +333,7 @@ /* ADC DMA configuration bit support */ -#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # define ADC_HAVE_DMACFG 1 #else # undef ADC_HAVE_DMACFG @@ -341,7 +341,7 @@ /* ADC scan mode support - only for ADCv1 */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V1 +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 # define ADC_HAVE_SCAN 1 # ifndef CONFIG_STM32_ADC1_SCAN # define CONFIG_STM32_ADC1_SCAN 0 diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c index 2f25d07a5a3..b095de41efa 100644 --- a/arch/arm/src/stm32/stm32_comp.c +++ b/arch/arm/src/stm32/stm32_comp.c @@ -47,9 +47,9 @@ * - STM32 COMP IP version 2: SMT32G4XXX */ -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # include "stm32_comp_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # include "stm32_comp_v2.c" #else # error "STM32 COMP IP version not supported." diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h index 5f3ae2c74e9..02e74e84972 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/stm32/stm32_comp.h @@ -33,9 +33,9 @@ #include "hardware/stm32_comp.h" -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # include "stm32_comp_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # include "stm32_comp_v2.h" #endif diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/stm32/stm32_foc.c index edced961d9a..4982a812b12 100644 --- a/arch/arm/src/stm32/stm32_foc.c +++ b/arch/arm/src/stm32/stm32_foc.c @@ -106,14 +106,14 @@ /* This is not for ADC IPv2 basic */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) && defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) && defined(HAVE_BASIC_ADC) # error Not supported ADC IP core #endif /* Multi instances support tested only on IP_ADC_V1 */ #if CONFIG_MOTOR_FOC_INST > 1 -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # error Not tested yet # endif #endif @@ -141,10 +141,10 @@ /* Debug register for PWM timers */ -#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) # define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ) -#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) # define FOC_PWM_FZ_REG (STM32_DBGMCU_CR) #endif @@ -154,10 +154,10 @@ # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) # define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP) # endif # if CONFIG_STM32_TIM1_MODE != 2 @@ -171,10 +171,10 @@ # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) # define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP) # endif # if CONFIG_STM32_TIM8_MODE != 2 @@ -248,14 +248,14 @@ * TIMx CCR4 = (ARR - trigger_offset) */ -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC12_JSQR_JEXTSEL_T1CC4) # endif # ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8CC4 (ADC12_JSQR_JEXTSEL_T8CC4) # endif -# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) # endif @@ -314,14 +314,14 @@ * TIMx TRGO = (ARR) */ -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC12_JSQR_JEXTSEL_T1TRGO) # endif # ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8TRGO (ADC12_JSQR_JEXTSEL_T8TRGO) # endif -# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) # endif @@ -470,11 +470,11 @@ /* Generalize ADC interrupt flags */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # define FOC_ADC_ISR_FOC ADC_ISR_JEOS # define FOC_ADC_IER_FOC ADC_IER_JEOS # define FOC_ADC_ISR_OVR ADC_INT_OVR -#elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # define FOC_ADC_ISR_FOC ADC_ISR_JEOC # define FOC_ADC_IER_FOC ADC_IER_JEOC # define FOC_ADC_ISR_OVR ADC_SR_OVR @@ -515,7 +515,7 @@ /* Common for ADCv1 */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && !defined(HAVE_BASIC_ADC) # define FOC_ADC_HAVE_CMN (1) # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (&g_stm32_foc_adccmn123) @@ -530,7 +530,7 @@ /* Common for ADCv1 basic */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && defined(HAVE_BASIC_ADC) # undef FOC_ADC_HAVE_CMN # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (0) @@ -545,7 +545,7 @@ /* Common for ADCv2 */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V2 +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 # define FOC_ADC_HAVE_CMN (1) # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (&g_stm32_foc_adccmn12) @@ -895,7 +895,7 @@ static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, ****************************************************************************/ #ifdef FOC_ADC_HAVE_CMN -# ifdef CONFIG_STM32_HAVE_IP_ADC_V1 +# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 /* Common for ADC123 */ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = @@ -903,9 +903,9 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = .cntr = 0, .lock = NXMUTEX_INITIALIZER, }; -# endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */ +# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 */ -# ifdef CONFIG_STM32_HAVE_IP_ADC_V2 +# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 # if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2) /* Common for ADC12 */ @@ -924,7 +924,7 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn34 = .lock = NXMUTEX_INITIALIZER, }; # endif /* CONFIG_STM32_HAVE_ADC3 || CONFIG_STM32_HAVE_ADC4 */ -# endif /* CONFIG_STM32_HAVE_IP_ADC_V2 */ +# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 */ #endif /* FOC_ADC_HAVE_CMN */ /* STM32 specific FOC data */ diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 3680c9a8ac3..7ba32284fb0 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -1053,6 +1053,7 @@ config STM32_FLASH_OVERRIDE config STM32_STM32F0 bool default n + select STM32_HAVE_PWR select STM32_HAVE_USART3 select STM32_HAVE_USART4 select STM32_HAVE_TIM1 @@ -1064,14 +1065,19 @@ config STM32_STM32F0 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 - select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V1 select STM32_HAVE_IP_EXTI_V1 config STM32_STM32G0 bool default n - select STM32_HAVE_ADC1_DMA + select STM32_HAVE_PWR + select STM32_HAVE_DMA1 + select STM32_HAVE_ADC1 + select STM32_HAVE_USART_RXFIFO_THRESHOLD + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_WDG_M0_V1 select STM32_HAVE_DMAMUX select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_EXTI_V2 @@ -1086,20 +1092,29 @@ config STM32_STM32G0 config STM32_STM32L0 bool default n + select STM32_HAVE_PWR + select STM32_HAVE_ADC1 + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_DMA1 select STM32_ENERGYLITE select STM32_HAVE_LCD select STM32_HAVE_VREFINT - select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V1 select STM32_HAVE_IP_EXTI_V1 config STM32_STM32C0 bool default n + select STM32_HAVE_PWR + select STM32_HAVE_USART_RXFIFO_THRESHOLD + select STM32_HAVE_DMA1 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_ADC1 + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_TIMERS_M0_V1 select STM32_HAVE_SPI2 select STM32_HAVE_I2C2 select STM32_HAVE_DMAMUX - select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_EXTI_V2 select STM32_HAVE_TIM1 @@ -1401,134 +1416,3 @@ config ARCH_CHIP_STM32C092XX select STM32_HAVE_USART3 select STM32_HAVE_USART4 select STM32_HAVE_FDCAN1 - -choice - prompt "SysTick clock source" - default STM32_SYSTICK_CORECLK - -config STM32_SYSTICK_CORECLK - bool "Cortex-M0 core clock" - -config STM32_SYSTICK_CORECLK_DIV16 - bool "Cortex-M0 core clock divided by 16" - -endchoice # SysTick clock source - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32_HAVE_VREFINT - bool - default n - -config STM32_HAVE_USART4 - bool - default n - -config STM32_HAVE_USART5 - bool - default n - -config STM32_HAVE_USART7 - bool - default n - -config STM32_HAVE_USART8 - bool - default n - -config STM32_HAVE_LPUART2 - bool - default n - -config STM32_HAVE_ADC_OVERSAMPLE - bool - default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 - -config STM32_HAVE_CEC - bool - default n - -config STM32_HAVE_SDIO - bool - default n - -config STM32_HAVE_I2S2 - bool - default n - -config STM32_HAVE_UCPD1 - bool - default n - -config STM32_HAVE_UCPD2 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32_HAVE_IP_USART_V1 - bool - default n - -config STM32_HAVE_IP_USART_V2 - bool - default n - -config STM32_HAVE_IP_EXTI_V1 - bool - default n - -config STM32_HAVE_IP_EXTI_V2 - bool - default n - -# These are the peripheral selections proper - -config STM32_VREFINT - bool "Enable VREFINT" - default n - depends on STM32_HAVE_VREFINT - -config STM32_USART4 - bool "USART4" - default n - depends on STM32_HAVE_USART4 - select STM32_USART - -config STM32_USART5 - bool "USART5" - default n - depends on STM32_HAVE_USART5 - select STM32_USART - -config STM32_USART7 - bool "USART7" - default n - depends on STM32_HAVE_USART7 - select STM32_USART - -config STM32_USART8 - bool "USART8" - default n - depends on STM32_HAVE_USART8 - select STM32_USART - -endmenu # STM32 Peripheral Support - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC1_CONTINUOUS - bool "Enable ADC1 Continuous Conversion Mode" - default n - depends on STM32_ADC1 - ---help--- - If enabled, the ADC will operate in continuous conversion mode. - Otherwise, it will perform single conversions. - Note: Continuous and discontinuous mode cannot be defined at - the same time - -endmenu # ADC Configuration diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig index a9c565cda42..faac0bde227 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig index 6b40188837b..b51bbbb4f4a 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig index d7167b38ab3..6be6bf998c4 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig index c2004420019..cfe38151ba5 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/common/src/board_pwm.c b/boards/arm/stm32f0l0g0/common/src/board_pwm.c index 793b0398537..d26772a5dc1 100644 --- a/boards/arm/stm32f0l0g0/common/src/board_pwm.c +++ b/boards/arm/stm32f0l0g0/common/src/board_pwm.c @@ -55,7 +55,7 @@ int stm32_pwm_setup(void) if (!initialized) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM pwm = stm32_pwminitialize(1); if (pwm == NULL) { @@ -71,7 +71,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM pwm = stm32_pwminitialize(2); if (pwm == NULL) { @@ -87,7 +87,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM pwm = stm32_pwminitialize(3); if (pwm == NULL) { @@ -103,7 +103,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM pwm = stm32_pwminitialize(14); if (pwm == NULL) { @@ -119,7 +119,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM pwm = stm32_pwminitialize(15); if (pwm == NULL) { @@ -135,7 +135,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM pwm = stm32_pwminitialize(16); if (pwm == NULL) { @@ -151,7 +151,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM pwm = stm32_pwminitialize(17); if (pwm == NULL) { diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig index d7d1b1380ec..3803bc20d69 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig index 6f04583925b..06f620204ed 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig index ede50792f32..105e69b35bd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig index af46d19b5c7..d9a948b94c4 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig index 9a9e901e2bd..6a9589eea45 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig index 8728028d0dc..c135e688fcc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig index 49856182e00..665917285bf 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig index b5de6c951e8..e65551b343e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_ARCH_BOARD="nucleo-f072rb" CONFIG_ARCH_BOARD_NUCLEO_F072RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F072RB=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig index 10d566c6b7d..23fbeaa2d4d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_ARCH_BOARD="nucleo-f091rc" CONFIG_ARCH_BOARD_NUCLEO_F091RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F091RC=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig index aac6d738084..f38d694fe4b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f091rc" CONFIG_ARCH_BOARD_NUCLEO_F091RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F091RC=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig index 9b43266c335..5381c3dce05 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-g070rb" CONFIG_ARCH_BOARD_NUCLEO_G070RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G070RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig index 58d337a3690..8960d71e898 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g071rb" CONFIG_ARCH_BOARD_NUCLEO_G071RB=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig index 565ff0d9dd1..afc8179b09e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig index 539f7b5141c..2cffd2d94c1 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig index 5eea859d573..e093b5b2a67 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig index c04c43cd46e..9633c3b48c0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l073rz" CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L073RZ=y CONFIG_ARCH_CHIP_STM32L073XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig index fc8331e8670..38cc3a0d14e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-l073rz" CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L073RZ=y CONFIG_ARCH_CHIP_STM32L073XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig index 22a9310041d..cfea4a1858a 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f051-discovery" CONFIG_ARCH_BOARD_STM32F051_DISCOVERY=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F051R8=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig index 7fc5f309f92..9a218ef1cc1 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f072-discovery" CONFIG_ARCH_BOARD_STM32F072_DISCOVERY=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F072RB=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig index 693e2684eb6..2c85c18f603 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32g071b-disco" CONFIG_ARCH_BOARD_STM32G071B_DISCO=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig index 727e0620e56..a0e1eef8c5b 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="stm32g071b-disco" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32G071B_DISCO=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig index f761d37e14e..ce9e752caa6 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32l0538-disco" CONFIG_ARCH_BOARD_STM32L0538_DISCO=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L053C8=y CONFIG_ARCH_CHIP_STM32L053XX=y CONFIG_ARCH_CHIP_STM32L0=y