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Merged in raiden00/nuttx (pull request #477)
Master * stm32f33xxx_hrtim.h: add some comments * stm32_hrtim: add burst mode configuration, rename some definitions * smps.h: add private data to the smps_s structure * stm32_hrtim: cosmetics Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
committed by
Gregory Nutt
Gregory Nutt
parent
860ff78d55
commit
23edfe2557
@@ -1030,36 +1030,41 @@
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/* Timer X Output Register */
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#define HRTIM_TIMOUT_POL1 (1 << 1) /* Bit 1 */
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#define HRTIM_TIMOUT_IDLEM1 (1 << 2) /* Bit 2 */
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#define HRTIM_TIMOUT_IDLES1 (1 << 3) /* Bit 3 */
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#define HRTIM_TIMOUT_FAULT1_SHIFT 4 /* Bit 4-5 */
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#define HRTIM_TIMOUT_POL1 (1 << 1) /* Bit 1: Output 1 polarity */
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#define HRTIM_TIMOUT_IDLEM1 (1 << 2) /* Bit 2: Output 1 IDLE mode */
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#define HRTIM_TIMOUT_IDLES1 (1 << 3) /* Bit 3: Output 1 IDLE state*/
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#define HRTIM_TIMOUT_FAULT1_SHIFT 4 /* Bit 4-5: Output 1 Fault state */
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#define HRTIM_TIMOUT_FAULT1_MASK (3 << HRTIM_TIMOUT_FAULT1_SHIFT)
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# define HRTIM_TIMOUT_FAULT1_0 (0 << HRTIM_TIMOUT_FAULT1_SHIFT)
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# define HRTIM_TIMOUT_FAULT1_1 (1 << HRTIM_TIMOUT_FAULT1_SHIFT)
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# define HRTIM_TIMOUT_FAULT1_2 (2 << HRTIM_TIMOUT_FAULT1_SHIFT)
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# define HRTIM_TIMOUT_FAULT1_3 (3 << HRTIM_TIMOUT_FAULT1_SHIFT)
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#define HRTIM_TIMOUT_CHP1 (1 << 3) /* Bit 1 */
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#define HRTIM_TIMOUT_DIDL1 (1 << 3) /* Bit 1 */
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#define HRTIM_TIMOUT_DTEN (1 << 3) /* Bit 1 */
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#define HRTIM_TIMOUT_DLYPRTEN (1 << 3) /* Bit 1 */
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#define HRTIM_TIMOUT_DLYPRT_SHIFT 10 /* Bits 10-12*/
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# define HRTIM_TIMOUT_FAULT1_0 (0 << HRTIM_TIMOUT_FAULT1_SHIFT) /* 00: No action */
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# define HRTIM_TIMOUT_FAULT1_1 (1 << HRTIM_TIMOUT_FAULT1_SHIFT) /* 01: Active */
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# define HRTIM_TIMOUT_FAULT1_2 (2 << HRTIM_TIMOUT_FAULT1_SHIFT) /* 10: Inactive */
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# define HRTIM_TIMOUT_FAULT1_3 (3 << HRTIM_TIMOUT_FAULT1_SHIFT) /* 11: High-Z */
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#define HRTIM_TIMOUT_CHP1 (1 << 6) /* Bit 6: Output 1 Chopper enable */
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#define HRTIM_TIMOUT_DIDL1 (1 << 7) /* Bit 7: Output 1 Deadtime upon burst mode IDLE entry */
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#define HRTIM_TIMOUT_DTEN (1 << 8) /* Bit 8: Deadtime enable */
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#define HRTIM_TIMOUT_DLYPRTEN (1 << 9) /* Bit 9: Delayed Protection enable */
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#define HRTIM_TIMOUT_DLYPRT_SHIFT 10 /* Bits 10-12: Delayed Protection*/
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#define HRTIM_TIMOUT_DLYPRT_MASK (3 << HRTIM_TIMOUT_DLYPRT_SHIFT)
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# define HRTIM_TIMOUT_DLYPRT_0 (0 << HRTIM_TIMOUT_DLYPRT_SHIFT)
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# define HRTIM_TIMOUT_DLYPRT_1 (1 << HRTIM_TIMOUT_DLYPRT_SHIFT)
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# define HRTIM_TIMOUT_DLYPRT_2 (2 << HRTIM_TIMOUT_DLYPRT_SHIFT)
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# define HRTIM_TIMOUT_DLYPRT_3 (3 << HRTIM_TIMOUT_DLYPRT_SHIFT)
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#define HRTIM_TIMOUT_POL2 (1 << 17) /* Bit 17 */
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#define HRTIM_TIMOUT_IDLEM2 (1 << 18) /* Bit 18 */
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#define HRTIM_TIMOUT_IDLES2 (1 << 19) /* Bit 19 */
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#define HRTIM_TIMOUT_FAULT2_SHIFT 20 /* Bit 20-21 */
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# define HRTIM_TIMOUT_DLYPRT_0 (0 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 000: */
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# define HRTIM_TIMOUT_DLYPRT_1 (1 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 001: */
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# define HRTIM_TIMOUT_DLYPRT_2 (2 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 010: */
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# define HRTIM_TIMOUT_DLYPRT_3 (3 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 011: */
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# define HRTIM_TIMOUT_DLYPRT_4 (4 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 100: */
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# define HRTIM_TIMOUT_DLYPRT_5 (5 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 101: */
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# define HRTIM_TIMOUT_DLYPRT_6 (6 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 110: */
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# define HRTIM_TIMOUT_DLYPRT_7 (7 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 111: */
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/* Bit 12-16: Resered */
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#define HRTIM_TIMOUT_POL2 (1 << 17) /* Bit 17: Output 2 polarity */
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#define HRTIM_TIMOUT_IDLEM2 (1 << 18) /* Bit 18: Output 2 IDLE mode */
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#define HRTIM_TIMOUT_IDLES2 (1 << 19) /* Bit 19: Output 2 IDLE state */
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#define HRTIM_TIMOUT_FAULT2_SHIFT 20 /* Bit 20-21: Output 2 Fault state */
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#define HRTIM_TIMOUT_FAULT2_MASK (3 << HRTIM_TIMOUT_FAULT2_SHIFT)
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# define HRTIM_TIMOUT_FAULT2_0 (0 << HRTIM_TIMOUT_FAULT2_SHIFT)
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# define HRTIM_TIMOUT_FAULT2_1 (1 << HRTIM_TIMOUT_FAULT2_SHIFT)
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# define HRTIM_TIMOUT_FAULT2_2 (2 << HRTIM_TIMOUT_FAULT2_SHIFT)
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# define HRTIM_TIMOUT_FAULT2_3 (3 << HRTIM_TIMOUT_FAULT2_SHIFT)
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#define HRTIM_TIMOUT_CHP2 (1 << 22) /* Bit 22 */
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#define HRTIM_TIMOUT_DIDL2 (1 << 23) /* Bit 23 */
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# define HRTIM_TIMOUT_FAULT2_0 (0 << HRTIM_TIMOUT_FAULT2_SHIFT) /* 00: No action*/
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# define HRTIM_TIMOUT_FAULT2_1 (1 << HRTIM_TIMOUT_FAULT2_SHIFT) /* 01: Active */
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# define HRTIM_TIMOUT_FAULT2_2 (2 << HRTIM_TIMOUT_FAULT2_SHIFT) /* 10: Inactive */
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# define HRTIM_TIMOUT_FAULT2_3 (3 << HRTIM_TIMOUT_FAULT2_SHIFT) /* 11: High-Z*/
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#define HRTIM_TIMOUT_CHP2 (1 << 22) /* Bit 22: Output 2 Chopper enable */
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#define HRTIM_TIMOUT_DIDL2 (1 << 23) /* Bit 23: Output 2 Deadtime upon burst mode IDLE entry */
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/* Timer X Fault Register */
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File diff suppressed because it is too large
Load Diff
@@ -65,41 +65,55 @@
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#if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \
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defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \
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defined(CONFIG_STM32_HRTIM_TIME_PWM)
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# define HRTIM_HAVE_PWM 1
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# ifndef CONFIG_STM32_HRTIM_PWM
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# error "CONFIG_STM32_HRTIM_PWM must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \
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defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \
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defined(CONFIG_STM32_HRTIM_TIME_CAP)
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# define HRTIM_HAVE_CAPTURE 1
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# ifndef CONFIG_STM32_HRTIM_CAPTURE
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# error "CONFIG_STM32_HRTIM_CAPTURE must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \
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defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \
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defined(CONFIG_STM32_HRTIM_TIME_DT)
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# define HRTIM_HAVE_DEADTIME 1
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# ifndef CONFIG_STM32_HRTIM_DEADTIME
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# error "CONFIG_STM32_HRTIM_DEADTIME must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \
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defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \
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defined(CONFIG_STM32_HRTIM_TIME_CHOP)
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# define HRTIM_HAVE_CHOPPER 1
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# ifndef CONFIG_STM32_HRTIM_CHOPPER
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# error "CONFIG_STM32_HRTIM_CHOPPER must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_TIMA_BURST) || defined(CONFIG_STM32_HRTIM_TIMB_BURST) || \
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defined(CONFIG_STM32_HRTIM_TIMC_BURST) || defined(CONFIG_STM32_HRTIM_TIMD_BURST) || \
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defined(CONFIG_STM32_HRTIM_TIME_BURST)
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# define HRTIM_HAVE_BURST_MODE 1
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# ifndef CONFIG_STM32_HRTIM_BURST
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# error "CONFIG_STM32_HRTIM_BURST must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_SCOUT) || defined(CONFIG_STM32_HRTIM_SCIN)
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# define HRTIM_HAVE_SYNC 1
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# ifndef CONFIG_STM32_HRTIM_SYNC
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# error "CONFIG_STM32_HRTIM_SYNC must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_FAULT1) || defined(CONFIG_STM32_HRTIM_FAULT2) || \
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defined(CONFIG_STM32_HRTIM_FAULT3) || defined(CONFIG_STM32_HRTIM_FAULT4) || \
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defined(CONFIG_STM32_HRTIM_FAULT5)
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# define HRTIM_HAVE_FAULTS 1
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# ifndef CONFIG_STM32_HRTIM_FAULTS
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# error "CONFIG_STM32_HRTIM_FAULTS must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_EEV1) || defined(CONFIG_STM32_HRTIM_EEV2) || \
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@@ -107,19 +121,25 @@
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defined(CONFIG_STM32_HRTIM_EEV5) || defined(CONFIG_STM32_HRTIM_EEV6) || \
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defined(CONFIG_STM32_HRTIM_EEV7) || defined(CONFIG_STM32_HRTIM_EEV8) || \
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defined(CONFIG_STM32_HRTIM_EEV9) || defined(CONFIG_STM32_HRTIM_EEV10)
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# define HRTIM_HAVE_EEV 1
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# ifndef CONFIG_STM32_HRTIM_EVENTS
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# error "CONFIG_STM32_HRTIM_EVENTS must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \
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defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \
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defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \
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defined(CONFIG_STM32_HRTIM_CMN_IRQ)
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# define HRTIM_HAVE_INTERRUPTS 1
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# ifndef CONFIG_STM32_HRTIM_INTERRUPTS
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# error "CONFIG_STM32_HRTIM_INTERRUPTS must be set"
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# endif
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#endif
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#if defined(CONFIG_STM32_HRTIM_ADC_TRG1) || defined(CONFIG_STM32_HRTIM_ADC_TRG2) || \
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defined(CONFIG_STM32_HRTIM_ADC_TRG3) || defined(CONFIG_STM32_HRTIM_ADC_TRG4)
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# define HRTIM_HAVE_ADC 1
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# ifndef CONFIG_STM32_HRTIM_ADC
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# error "CONFIG_STM32_HRTIM_ADC must be set"
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# endif
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#endif
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/* TIMX PWM configuration checking */
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@@ -716,16 +736,16 @@ enum stm32_irq_cmn_e
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enum stm32_hrtim_dma_e
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{
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HRTIM_DMA_CMP1 = (1 << 0), /* Common: Compare 1 DMA request */
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HRTIM_DMA_CMP2 = (1 << 1), /* Common: Compare 2 DMA request */
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HRTIM_DMA_CMP3 = (1 << 2), /* Common: Compare 3 DMA request */
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HRTIM_DMA_CMP4 = (1 << 3), /* Common:Compare 4 DMA request */
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HRTIM_DMA_REP = (1 << 4), /* Common: Repetition DMA request */
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HRTIM_DMA_SYNC = (1 << 5), /* Master: Sync Input DMA request */
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HRTIM_DMA_UPD = (1 << 6), /* Common: Update DMA reques */
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HRTIM_DMA_CPT1 = (1 << 7), /* Slaves: Capture 1 DMA reques */
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HRTIM_DMA_CPT2 = (1 << 8), /* Slaves: Capture 2 DMA reques */
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HRTIM_DMA_SET1 = (1 << 9), /* Slaves: Output 1 Set DMA reques */
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HRTIM_DMA_CMP1 = (1 << 0), /* Common: Compare 1 DMA request */
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HRTIM_DMA_CMP2 = (1 << 1), /* Common: Compare 2 DMA request */
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HRTIM_DMA_CMP3 = (1 << 2), /* Common: Compare 3 DMA request */
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HRTIM_DMA_CMP4 = (1 << 3), /* Common:Compare 4 DMA request */
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HRTIM_DMA_REP = (1 << 4), /* Common: Repetition DMA request */
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HRTIM_DMA_SYNC = (1 << 5), /* Master: Sync Input DMA request */
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HRTIM_DMA_UPD = (1 << 6), /* Common: Update DMA reques */
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HRTIM_DMA_CPT1 = (1 << 7), /* Slaves: Capture 1 DMA reques */
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HRTIM_DMA_CPT2 = (1 << 8), /* Slaves: Capture 2 DMA reques */
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HRTIM_DMA_SET1 = (1 << 9), /* Slaves: Output 1 Set DMA reques */
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HRTIM_DMA_RST1 = (1 << 10), /* Slaves: Output 1 Reset DMA reques */
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HRTIM_DMA_SET2 = (1 << 11), /* Slaves: Output 2 Set DMA reques */
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HRTIM_DMA_RST2 = (1 << 12), /* Slaves: Output 2 Reset DMA reques */
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@@ -733,6 +753,90 @@ enum stm32_hrtim_dma_e
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HRTIM_DMA_DLYPRT = (1 << 14) /* Slaves: Delayed Protection DMA reques */
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};
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/* HRTIM Output IDLE state */
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enum stm32_hrtim_idle_state
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{
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HRTIM_IDLE_INACTIVE = 0, /* Output inactive during IDLE state */
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HRTIM_IDLE_ACTIVE = 1 /* Output active during IDLE state */
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};
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/* HRTIM Burst Mode clock source */
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enum stm32_hrtim_burst_source_e
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{
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HRTIM_BURST_CLOCK_MASTER = 0, /* Master timer counter reset/roll-over */
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HRTIM_BURST_CLOCK_TIMA = 1, /* Timer A counter reset/roll-over */
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HRTIM_BURST_CLOCK_TIMB = 2, /* Timer B counter reset/roll-over */
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HRTIM_BURST_CLOCK_TIMC = 3, /* Timer C counter reset/roll-over */
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HRTIM_BURST_CLOCK_TIMD = 4, /* Timer D counter reset/roll-over */
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HRTIM_BURST_CLOCK_TIME = 5, /* Timer E counter reset/roll-over */
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HRTIM_BURST_CLOCK_EV1 = 6, /* On-chip Event 1 */
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HRTIM_BURST_CLOCK_EV2 = 7, /* On-chip Event 2 */
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HRTIM_BURST_CLOCK_EV3 = 8, /* On-chip Event 3 */
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HRTIM_BURST_CLOCK_EV4 = 9, /* On-chip Event 4 */
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HRTIM_BURST_CLOCK_HRTIM = 10 /* Prescaled f_HRTIM clock */
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};
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/* HRTIM Burst Mode prescaler for fHRTIM clock */
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enum stm32_hrtim_burst_precaler_e
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{
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HRTIM_BURST_PRESCALER_0 = 0,
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HRTIM_BURST_PRESCALER_2 = 1,
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HRTIM_BURST_PRESCALER_4 = 2,
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HRTIM_BURST_PRESCALER_8 = 3,
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HRTIM_BURST_PRESCALER_16 = 4,
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HRTIM_BURST_PRESCALER_32 = 5,
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HRTIM_BURST_PRESCALER_64 = 6,
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HRTIM_BURST_PRESCALER_128 = 7,
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HRTIM_BURST_PRESCALER_256 = 8,
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HRTIM_BURST_PRESCALER_512 = 9,
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HRTIM_BURST_PRESCALER_1024 = 10,
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HRTIM_BURST_PRESCALER_2048 = 11,
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HRTIM_BURST_PRESCALER_4096 = 12,
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HRTIM_BURST_PRESCALER_8192 = 13,
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HRTIM_BURST_PRESCALER_16384 = 14,
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HRTIM_BURST_PRESCALER_32768 = 15
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};
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/* HRTIM Burst Mode triggers */
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enum stm32_hrtim_burst_triggers_e
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{
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HRTIM_BURST_TRG_MSTRST = (1 << 1),
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HRTIM_BURST_TRG_MSTREP = (1 << 2),
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HRTIM_BURST_TRG_MSTCMP1 = (1 << 3),
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HRTIM_BURST_TRG_MSTCMP2 = (1 << 4),
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HRTIM_BURST_TRG_MSTCMP3 = (1 << 5),
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HRTIM_BURST_TRG_MSTCMP4 = (1 << 6),
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HRTIM_BURST_TRG_TARST = (1 << 7),
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HRTIM_BURST_TRG_TAREP = (1 << 8),
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HRTIM_BURST_TRG_TACMP1 = (1 << 9),
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HRTIM_BURST_TRG_TACMP2 = (1 << 10),
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HRTIM_BURST_TRG_TBRST = (1 << 11),
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HRTIM_BURST_TRG_TBREP = (1 << 12),
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HRTIM_BURST_TRG_TBCMP1 = (1 << 13),
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HRTIM_BURST_TRG_TBCMP2 = (1 << 14),
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HRTIM_BURST_TRG_TCRST = (1 << 15),
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HRTIM_BURST_TRG_TCREP = (1 << 16),
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HRTIM_BURST_TRG_TCCMP1 = (1 << 17),
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HRTIM_BURST_TRG_TCCMP2 = (1 << 18),
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HRTIM_BURST_TRG_TDRST = (1 << 19),
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HRTIM_BURST_TRG_TDREP = (1 << 20),
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HRTIM_BURST_TRG_TDCMP1 = (1 << 21),
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HRTIM_BURST_TRG_TDCMP2 = (1 << 22),
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HRTIM_BURST_TRG_TERST = (1 << 23),
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HRTIM_BURST_TRG_TEREP = (1 << 24),
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HRTIM_BURST_TRG_TECMP1 = (1 << 25),
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HRTIM_BURST_TRG_TECMP2 = (1 << 26),
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HRTIM_BURST_TRG_TAEEV7 = (1 << 27),
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HRTIM_BURST_TRG_TDEEV8 = (1 << 28),
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HRTIM_BURST_TRG_EEV7 = (1 << 29),
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HRTIM_BURST_TRG_EEV8 = (1 << 30),
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HRTIM_BURST_TRG_OCHPEV = (1 << 31),
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};
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/* HRTIM vtable */
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struct hrtim_dev_s;
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@@ -744,13 +848,20 @@ struct stm32_hrtim_ops_s
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uint16_t (*per_get)(FAR struct hrtim_dev_s *dev, uint8_t timer);
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uint16_t (*cmp_get)(FAR struct hrtim_dev_s *dev, uint8_t timer,
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uint8_t index);
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#ifdef HRTIM_HAVE_INTERRUPTS
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#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
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void (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
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#endif
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#ifdef HRTIM_HAVE_PWM
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#ifdef CONFIG_STM32_HRTIM_PWM
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int (*outputs_enable)(FAR struct hrtim_dev_s *dev, uint16_t outputs,
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bool state);
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#endif
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#ifdef CONFIG_STM32_HRTIM_BURST
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int (*burst_enable)(FAR struct hrtim_dev_s *dev, bool state);
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int (*burst_cmp_set)(FAR struct hrtim_dev_s *dev, uint16_t cmp);
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int (*burst_per_set)(FAR struct hrtim_dev_s *dev, uint16_t per);
|
||||
uint16_t (*burst_cmp_get)(FAR struct hrtim_dev_s *dev);
|
||||
uint16_t (*burst_per_get)(FAR struct hrtim_dev_s *dev);
|
||||
#endif
|
||||
};
|
||||
|
||||
/* HRTIM device structure */
|
||||
@@ -808,7 +919,9 @@ FAR struct hrtim_dev_s* stm32_hrtiminitialize(void);
|
||||
* Name: hrtim_register
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV
|
||||
int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -190,6 +190,7 @@ struct smps_s
|
||||
struct smps_limits_s limits; /* SMPS absolute limits */
|
||||
struct smps_params_s param; /* SMPS settings */
|
||||
struct smps_state_s state; /* SMPS state */
|
||||
FAR void *priv; /* Private data */
|
||||
};
|
||||
|
||||
/* SMPS operations used to call from the upper-half, generic SMPS driver
|
||||
|
||||
Reference in New Issue
Block a user