diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h index fcf56524188..5842822ccf8 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h @@ -1030,36 +1030,41 @@ /* Timer X Output Register */ -#define HRTIM_TIMOUT_POL1 (1 << 1) /* Bit 1 */ -#define HRTIM_TIMOUT_IDLEM1 (1 << 2) /* Bit 2 */ -#define HRTIM_TIMOUT_IDLES1 (1 << 3) /* Bit 3 */ -#define HRTIM_TIMOUT_FAULT1_SHIFT 4 /* Bit 4-5 */ +#define HRTIM_TIMOUT_POL1 (1 << 1) /* Bit 1: Output 1 polarity */ +#define HRTIM_TIMOUT_IDLEM1 (1 << 2) /* Bit 2: Output 1 IDLE mode */ +#define HRTIM_TIMOUT_IDLES1 (1 << 3) /* Bit 3: Output 1 IDLE state*/ +#define HRTIM_TIMOUT_FAULT1_SHIFT 4 /* Bit 4-5: Output 1 Fault state */ #define HRTIM_TIMOUT_FAULT1_MASK (3 << HRTIM_TIMOUT_FAULT1_SHIFT) -# define HRTIM_TIMOUT_FAULT1_0 (0 << HRTIM_TIMOUT_FAULT1_SHIFT) -# define HRTIM_TIMOUT_FAULT1_1 (1 << HRTIM_TIMOUT_FAULT1_SHIFT) -# define HRTIM_TIMOUT_FAULT1_2 (2 << HRTIM_TIMOUT_FAULT1_SHIFT) -# define HRTIM_TIMOUT_FAULT1_3 (3 << HRTIM_TIMOUT_FAULT1_SHIFT) -#define HRTIM_TIMOUT_CHP1 (1 << 3) /* Bit 1 */ -#define HRTIM_TIMOUT_DIDL1 (1 << 3) /* Bit 1 */ -#define HRTIM_TIMOUT_DTEN (1 << 3) /* Bit 1 */ -#define HRTIM_TIMOUT_DLYPRTEN (1 << 3) /* Bit 1 */ -#define HRTIM_TIMOUT_DLYPRT_SHIFT 10 /* Bits 10-12*/ +# define HRTIM_TIMOUT_FAULT1_0 (0 << HRTIM_TIMOUT_FAULT1_SHIFT) /* 00: No action */ +# define HRTIM_TIMOUT_FAULT1_1 (1 << HRTIM_TIMOUT_FAULT1_SHIFT) /* 01: Active */ +# define HRTIM_TIMOUT_FAULT1_2 (2 << HRTIM_TIMOUT_FAULT1_SHIFT) /* 10: Inactive */ +# define HRTIM_TIMOUT_FAULT1_3 (3 << HRTIM_TIMOUT_FAULT1_SHIFT) /* 11: High-Z */ +#define HRTIM_TIMOUT_CHP1 (1 << 6) /* Bit 6: Output 1 Chopper enable */ +#define HRTIM_TIMOUT_DIDL1 (1 << 7) /* Bit 7: Output 1 Deadtime upon burst mode IDLE entry */ +#define HRTIM_TIMOUT_DTEN (1 << 8) /* Bit 8: Deadtime enable */ +#define HRTIM_TIMOUT_DLYPRTEN (1 << 9) /* Bit 9: Delayed Protection enable */ +#define HRTIM_TIMOUT_DLYPRT_SHIFT 10 /* Bits 10-12: Delayed Protection*/ #define HRTIM_TIMOUT_DLYPRT_MASK (3 << HRTIM_TIMOUT_DLYPRT_SHIFT) -# define HRTIM_TIMOUT_DLYPRT_0 (0 << HRTIM_TIMOUT_DLYPRT_SHIFT) -# define HRTIM_TIMOUT_DLYPRT_1 (1 << HRTIM_TIMOUT_DLYPRT_SHIFT) -# define HRTIM_TIMOUT_DLYPRT_2 (2 << HRTIM_TIMOUT_DLYPRT_SHIFT) -# define HRTIM_TIMOUT_DLYPRT_3 (3 << HRTIM_TIMOUT_DLYPRT_SHIFT) -#define HRTIM_TIMOUT_POL2 (1 << 17) /* Bit 17 */ -#define HRTIM_TIMOUT_IDLEM2 (1 << 18) /* Bit 18 */ -#define HRTIM_TIMOUT_IDLES2 (1 << 19) /* Bit 19 */ -#define HRTIM_TIMOUT_FAULT2_SHIFT 20 /* Bit 20-21 */ +# define HRTIM_TIMOUT_DLYPRT_0 (0 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 000: */ +# define HRTIM_TIMOUT_DLYPRT_1 (1 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 001: */ +# define HRTIM_TIMOUT_DLYPRT_2 (2 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 010: */ +# define HRTIM_TIMOUT_DLYPRT_3 (3 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 011: */ +# define HRTIM_TIMOUT_DLYPRT_4 (4 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 100: */ +# define HRTIM_TIMOUT_DLYPRT_5 (5 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 101: */ +# define HRTIM_TIMOUT_DLYPRT_6 (6 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 110: */ +# define HRTIM_TIMOUT_DLYPRT_7 (7 << HRTIM_TIMOUT_DLYPRT_SHIFT) /* 111: */ + /* Bit 12-16: Resered */ +#define HRTIM_TIMOUT_POL2 (1 << 17) /* Bit 17: Output 2 polarity */ +#define HRTIM_TIMOUT_IDLEM2 (1 << 18) /* Bit 18: Output 2 IDLE mode */ +#define HRTIM_TIMOUT_IDLES2 (1 << 19) /* Bit 19: Output 2 IDLE state */ +#define HRTIM_TIMOUT_FAULT2_SHIFT 20 /* Bit 20-21: Output 2 Fault state */ #define HRTIM_TIMOUT_FAULT2_MASK (3 << HRTIM_TIMOUT_FAULT2_SHIFT) -# define HRTIM_TIMOUT_FAULT2_0 (0 << HRTIM_TIMOUT_FAULT2_SHIFT) -# define HRTIM_TIMOUT_FAULT2_1 (1 << HRTIM_TIMOUT_FAULT2_SHIFT) -# define HRTIM_TIMOUT_FAULT2_2 (2 << HRTIM_TIMOUT_FAULT2_SHIFT) -# define HRTIM_TIMOUT_FAULT2_3 (3 << HRTIM_TIMOUT_FAULT2_SHIFT) -#define HRTIM_TIMOUT_CHP2 (1 << 22) /* Bit 22 */ -#define HRTIM_TIMOUT_DIDL2 (1 << 23) /* Bit 23 */ +# define HRTIM_TIMOUT_FAULT2_0 (0 << HRTIM_TIMOUT_FAULT2_SHIFT) /* 00: No action*/ +# define HRTIM_TIMOUT_FAULT2_1 (1 << HRTIM_TIMOUT_FAULT2_SHIFT) /* 01: Active */ +# define HRTIM_TIMOUT_FAULT2_2 (2 << HRTIM_TIMOUT_FAULT2_SHIFT) /* 10: Inactive */ +# define HRTIM_TIMOUT_FAULT2_3 (3 << HRTIM_TIMOUT_FAULT2_SHIFT) /* 11: High-Z*/ +#define HRTIM_TIMOUT_CHP2 (1 << 22) /* Bit 22: Output 2 Chopper enable */ +#define HRTIM_TIMOUT_DIDL2 (1 << 23) /* Bit 23: Output 2 Deadtime upon burst mode IDLE entry */ /* Timer X Fault Register */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index 1edb332a4fa..495b5e3ee2a 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -90,7 +90,7 @@ # endif #endif -#ifdef HRTIM_HAVE_ADC +#ifdef CONFIG_STM32_HRTIM_ADC # error HRTIM ADC Triggering not supported yet #endif @@ -109,23 +109,19 @@ # endif #endif -#ifdef HRTIM_HAVE_CAPTURE +#ifdef CONFIG_STM32_HRTIM_CAPTURE # error HRTIM Capture not supported yet #endif -#ifdef HRTIM_HAVE_DEADTIME +#ifdef CONFIG_STM32_HRTIM_DEADTIME # error HRTIM Deadtime not supported yet #endif -#ifdef HRTIM_HAVE_CHOPPER +#ifdef CONFIG_STM32_HRTIM_CHOPPER # error HRTIM Chopper not supported yet #endif -#ifdef HRTIM_HAVE_BURST -# error HRTIM Burst mode not supported yet -#endif - -#ifdef HRTIM_HAVE_INTERRUPTS +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS # error HRTIM Interrupts not supported yet #endif @@ -239,7 +235,7 @@ * Private Types ****************************************************************************/ -#ifdef HRTIM_HAVE_PWM +#ifdef CONFIG_STM32_HRTIM_PWM /* HRTIM Slave Timer Single Output Set/Reset Configuration */ @@ -251,7 +247,7 @@ struct stm32_hrtim_timout_s /* HRTIM Slave Timer Chopper Configuration */ -#ifdef HRTIM_HAVE_CHOPPER +#ifdef CONFIG_STM32_HRTIM_CHOPPER struct stm32_hrtim_chopper_s { uint16_t start:4; /* Chopper start pulsewidth */ @@ -263,7 +259,7 @@ struct stm32_hrtim_chopper_s /* HRTIM Slave Timer Deadtime Configuration */ -#ifdef HRTIM_HAVE_DEADTIME +#ifdef CONFIG_STM32_HRTIM_DEADTIME struct stm32_hrtim_deadtime_s { uint8_t falling_lock:2; /* Deadtime falling value and sign lock */ @@ -273,6 +269,17 @@ struct stm32_hrtim_deadtime_s }; #endif +/* HRTIM Timer Burst Mode Configuration */ + +struct stm32_hrtim_tim_burst_s +{ + uint8_t ch1_en:1; /* Enable burst mode operation for CH1 */ + uint8_t ch1_state:1; /* CH1 IDLE state */ + uint8_t ch2_en:1; /* Enable burst mode operation for CH2 */ + uint8_t ch2_state:1; /* CH2 IDLE state */ + uint8_t res:4; +}; + /* HRTIM Timer PWM structure */ struct stm32_hrtim_pwm_s @@ -280,17 +287,20 @@ struct stm32_hrtim_pwm_s struct stm32_hrtim_timout_s ch1; /* Channel 1 Set/Reset configuration*/ struct stm32_hrtim_timout_s ch2; /* Channel 2 Set/Reset configuration */ -#ifdef HRTIM_HAVE_CHOPPER +#ifdef CONFIG_STM32_HRTIM_BURST + struct stm32_hrtim_tim_burst_s burst; +#endif +#ifdef CONFIG_STM32_HRTIM_CHOPPER struct stm32_hrtim_chopper_s chp; #endif -#ifdef HRTIM_HAVE_DEADTIME +#ifdef CONFIG_STM32_HRTIM_DEADTIME struct stm32_hrtim_deadtime_s dt; #endif }; #endif -#ifdef HRTIM_HAVE_CAPTURE +#ifdef CONFIG_STM32_HRTIM_CAPTURE struct stm32_hrtim_capture_s { uint32_t reserved; /* Reserved */ @@ -308,7 +318,7 @@ struct stm32_hrtim_timcmn_s uint8_t mode; /* Timer mode */ uint8_t dac:2; /* DAC triggering */ uint8_t reserved:6; -#ifdef HRTIM_HAVE_INTERRUPTS +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS uint16_t irq; /* interrupts configuration */ #endif #ifdef CONFIG_STM32_HRTIM_DMA @@ -338,26 +348,26 @@ struct stm32_hrtim_master_priv_s struct stm32_hrtim_slave_priv_s { -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_FAULTS uint8_t flt; /* Faults configuration. * First five bits are fault sources, * last bit is lock configuration. */ -#ifdef HRTIM_HAVE_AUTO_DELAYED +#ifdef CONFIG_STM32_HRTIM_AUTODELAYED uint8_t auto_delayed; /* Auto-delayed mode configuration */ #endif #endif uint16_t update; /* Update configuration */ uint32_t reset; /* Timer reset events */ -#ifdef HRTIM_HAVE_PWM +#ifdef CONFIG_STM32_HRTIM_PWM struct stm32_hrtim_pwm_s pwm; /* PWM configuration */ #endif -#ifdef HRTIM_HAVE_CAPTURE +#ifdef CONFIG_STM32_HRTIM_CAPTURE struct stm32_hrtim_capture_s cap; /* Capture configuration */ #endif }; -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_FAULTS /* Structure describes single HRTIM Fault configuration */ @@ -392,7 +402,7 @@ struct stm32_hrtim_faults_s }; #endif -#ifdef HRTIM_HAVE_EEV +#ifdef CONFIG_STM32_HRTIM_EVENTS /* Structure describes single HRTIM External Event configuration */ @@ -443,7 +453,7 @@ struct stm32_hrtim_eev_s }; #endif -#ifdef HRTIM_HAVE_ADC +#ifdef CONFIG_STM32_HRTIM_ADC /* Structure describes HRTIM ADC triggering configuration */ @@ -466,10 +476,12 @@ struct stm32_hrtim_adc_s /* Structure describes HRTIM Burst mode configuratione */ -#ifdef HRTIM_HAVE_BURST_MODE +#ifdef CONFIG_STM32_HRTIM_BURST struct stm32_hrtim_burst_s { - uint32_t reserved; /* reserved for future */ + uint8_t clk:4; /* Burst mode clock source */ + uint8_t presc:4; /* Prescaler for f_HRTIM clock*/ + uint32_t trg; /* Burst mode triggers */ }; #endif @@ -494,16 +506,16 @@ struct stm32_hrtim_s #ifdef CONFIG_STM32_HRTIM_TIME struct stm32_hrtim_tim_s *time; /* HRTIM Timer E */ #endif -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_FAULTS struct stm32_hrtim_faults_s *flt; /* Faults configuration */ #endif -#ifdef HRTIM_HAVE_EEV +#ifdef CONFIG_STM32_HRTIM_EVENTS struct stm32_hrtim_eev_s *eev; /* External Events configuration */ #endif -#ifdef HRTIM_HAVE_ADC +#ifdef CONFIG_STM32_HRTIM_ADC struct stm32_hrtim_adc_s *adc; /* ADC triggering configuration */ #endif -#ifdef HRTIM_HAVE_BURST_MODE +#ifdef CONFIG_STM32_HRTIM_BURST struct stm32_hrtim_burst_s *burst; /* Burst mode configuration */ #endif #ifdef CONFIG_STM32_HRTIM_CMN_IRQ @@ -515,11 +527,14 @@ struct stm32_hrtim_s * Private Function Prototypes ****************************************************************************/ +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV + /* HRTIM Driver Methods */ static int stm32_hrtim_open(FAR struct file *filep); static int stm32_hrtim_close(FAR struct file *filep); static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +#endif /* HRTIM Register access */ @@ -528,7 +543,7 @@ static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, static uint32_t hrtim_cmn_getreg(FAR struct stm32_hrtim_s *priv, uint32_t offset); static void hrtim_cmn_putreg(FAR struct stm32_hrtim_s *priv, uint32_t offset, uint32_t value); -static void hrtim_modifyreg(FAR struct stm32_hrtim_s *priv, uint32_t offset, +static void hrtim_cmn_modifyreg(FAR struct stm32_hrtim_s *priv, uint32_t offset, uint32_t clrbits, uint32_t setbits); static void hrtim_tim_putreg(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint32_t offset, uint32_t value); @@ -549,21 +564,22 @@ static int hrtim_dll_cal(FAR struct stm32_hrtim_s *priv); static int hrtim_tim_clock_config(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint8_t pre); static int hrtim_tim_clocks_config(FAR struct stm32_hrtim_s *priv); -#if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) +#if defined(CONFIG_STM32_HRTIM_CAPTURE) || defined(CONFIG_STM32_HRTIM_PWM) || \ + defined(CONFIG_STM32_HRTIM_SYNC) static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv); #endif -#if defined(HRTIM_HAVE_CAPTURE) +#if defined(CONFIG_STM32_HRTIM_CAPTURE) static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv); #endif -#if defined(HRTIM_HAVE_SYNC) +#if defined(CONFIG_STM32_HRTIM_SYNC) static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv); #endif -#if defined(HRTIM_HAVE_PWM) +#if defined(CONFIG_STM32_HRTIM_PWM) static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv); static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs, bool state); #endif -#ifdef HRTIM_HAVE_ADC +#ifdef CONFIG_STM32_HRTIM_ADC static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv); #endif #ifdef CONFIG_STM32_HRTIM_DAC @@ -574,16 +590,27 @@ static int hrtim_dma_cfg(FAR struct stm32_hrtim_s *priv); static int hrtim_tim_dma_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer, uint16_t dma); #endif -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_DEADTIME +static int hrtim_deadtime_config(FAR struct stm32_hrtim_s *priv); +#endif +#ifdef CONFIG_STM32_HRTIM_BURST +int hrtim_burst_enable(FAR struct hrtim_dev_s *dev, bool state); +int hrtim_burst_cmp_update(FAR struct hrtim_dev_s *dev, uint16_t cmp); +int hrtim_burst_per_update(FAR struct hrtim_dev_s *dev, uint16_t per); +uint16_t hrtim_burst_cmp_get(FAR struct hrtim_dev_s *dev); +uint16_t hrtim_burst_per_get (FAR struct hrtim_dev_s *dev); +static int hrtim_burst_config(FAR struct stm32_hrtim_s *priv); +#endif +#ifdef CONFIG_STM32_HRTIM_FAULTS static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv); static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); static int hrtim_tim_faults_cfg(FAR struct stm32_hrtim_s *priv, uint8_t timer); #endif -#ifdef HRTIM_HAVE_EEV +#ifdef CONFIG_STM32_HRTIM_EVENTS static int hrtim_events_config(FAR struct stm32_hrtim_s *priv); static int hrtim_eev_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index); #endif -#ifdef HRTIM_HAVE_INTERRUPTS +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv); void hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); #endif @@ -613,6 +640,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv); * Private Data ****************************************************************************/ +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV static const struct file_operations hrtim_fops = { stm32_hrtim_open, /* open */ @@ -628,6 +656,7 @@ static const struct file_operations hrtim_fops = , NULL /* unlink */ #endif }; +#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ /* Master Timer data */ @@ -681,6 +710,23 @@ static struct stm32_hrtim_slave_priv_s g_tima_priv = .rst = HRTIM_TIMA_CH2_RST }, #endif +#ifdef CONFIG_STM32_HRTIM_TIMA_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIMA_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIMA_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIMA_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIMA_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif #ifdef CONFIG_STM32_HRTIM_TIMA_CHOP .chp = { @@ -755,6 +801,23 @@ static struct stm32_hrtim_slave_priv_s g_timb_priv = .rst = HRTIM_TIMB_CH2_RST }, #endif +#ifdef CONFIG_STM32_HRTIM_TIMB_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIMB_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIMB_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIMB_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIMB_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif #ifdef CONFIG_STM32_HRTIM_TIMB_CHOP .chp = { @@ -829,6 +892,23 @@ static struct stm32_hrtim_slave_priv_s g_timc_priv = .rst = HRTIM_TIMC_CH2_RST }, #endif +#ifdef CONFIG_STM32_HRTIM_TIMC_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIMC_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIMC_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIMC_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIMC_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif #ifdef CONFIG_STM32_HRTIM_TIMC_CHOP .chp = { @@ -903,6 +983,23 @@ static struct stm32_hrtim_slave_priv_s g_timd_priv = .rst = HRTIM_TIMD_CH2_RST }, #endif +#ifdef CONFIG_STM32_HRTIM_TIMD_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIMD_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIMD_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIMD_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIMD_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif #ifdef CONFIG_STM32_HRTIM_TIMD_CHOP .chp = { @@ -977,6 +1074,23 @@ static struct stm32_hrtim_slave_priv_s g_time_priv = .rst = HRTIM_TIME_CH2_RST }, #endif +#ifdef CONFIG_STM32_HRTIM_TIME_BURST + .burst = + { +# ifdef CONFIG_STM32_HRTIM_TIME_BURST_CH1 + .ch1_en = 1, + .ch1_state = HRTIM_TIME_CH1_IDLE_STATE, +# else + .ch1_en = 0, +# endif +# ifdef CONFIG_STM32_HRTIM_TIME_BURST_CH2 + .ch2_en = 1, + .ch2_state = HRTIM_TIME_CH2_IDLE_STATE +# else + .ch2_en = 0, +# endif + }, +#endif #ifdef CONFIG_STM32_HRTIM_TIME_CHOP .chp = { @@ -1028,7 +1142,7 @@ static struct stm32_hrtim_tim_s g_time = /* Faults data */ -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_FAULTS struct stm32_hrtim_faults_s g_flt = { #ifdef CONFIG_STM32_HRTIM_FAULT1 @@ -1081,7 +1195,7 @@ struct stm32_hrtim_faults_s g_flt = /* External Events data */ -#ifdef HRTIM_HAVE_EEV +#ifdef CONFIG_STM32_HRTIM_EVENTS struct stm32_hrtim_eev_s g_eev = { #ifdef CONFIG_STM32_HRTIM_EEV1 @@ -1190,7 +1304,7 @@ struct stm32_hrtim_eev_s g_eev = /* ADC triggering data */ -#ifdef HRTIM_HAVE_ADC +#ifdef CONFIG_STM32_HRTIM_ADC struct stm32_hrtim_adc_s g_adc = { #ifdef CONFIG_STM32_HRTIM_ADC_TRG1 @@ -1210,10 +1324,12 @@ struct stm32_hrtim_adc_s g_adc = /* Burst mode data */ -#ifdef HRTIM_HAVE_BURST_MODE +#ifdef CONFIG_STM32_HRTIM_BURST struct stm32_hrtim_burst_s g_burst = { - .reserved = 0 + .clk = HRTIM_BURST_CLOCK, + .presc = HRTIM_BURST_PRESCALER, + .trg = HRTIM_BURST_TRIGGERS }; #endif @@ -1238,17 +1354,17 @@ static struct stm32_hrtim_s g_hrtim1priv = #ifdef CONFIG_STM32_HRTIM_TIME .time = &g_time, #endif -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_FAULTS .flt = &g_flt, #endif -#ifdef HRTIM_HAVE_EEV +#ifdef CONFIG_STM32_HRTIM_EVENTS .eev = &g_eev, #endif -#ifdef HRTIM_HAVE_ADC +#ifdef CONFIG_STM32_HRTIM_ADC .adc = &g_adc, #endif -#ifdef HRTIM_HAVE_BURST_MODE - .adc = &g_burst, +#ifdef CONFIG_STM32_HRTIM_BURST + .burst = &g_burst, #endif #ifdef CONFIG_STM32_HRTIM_CMN_IRQ .irq = HRTIM_IRQ_COMMON, @@ -1263,12 +1379,19 @@ static const struct stm32_hrtim_ops_s g_hrtim1ops = .per_update = hrtim_per_update, .per_get = hrtim_per_get, .cmp_get = hrtim_cmp_get, -#ifdef HRTIM_HAVE_INTERRUPTS +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS .irq_ack = hrtim_irq_ack, #endif -#ifdef HRTIM_HAVE_PWM +#ifdef CONFIG_STM32_HRTIM_PWM .outputs_enable = hrtim_outputs_enable, #endif +#ifdef CONFIG_STM32_HRTIM_BURST + .burst_enable = hrtim_burst_enable, + .burst_cmp_set = hrtim_burst_cmp_update, + .burst_per_set = hrtim_burst_per_update, + .burst_cmp_get = hrtim_burst_cmp_get, + .burst_per_get = hrtim_burst_per_get, +#endif }; /* HRTIM device structure */ @@ -1284,6 +1407,8 @@ struct hrtim_dev_s g_hrtim1dev = * Private Functions ****************************************************************************/ +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV + /**************************************************************************** * Name: stm32_hrtim_open * @@ -1350,6 +1475,8 @@ static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg) return ret; } +#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ + /**************************************************************************** * Name: stm32_modifyreg32 * @@ -1431,7 +1558,7 @@ static void hrtim_cmn_putreg(FAR struct stm32_hrtim_s *priv, uint32_t offset, * ****************************************************************************/ -static void hrtim_modifyreg(FAR struct stm32_hrtim_s *priv, uint32_t offset, +static void hrtim_cmn_modifyreg(FAR struct stm32_hrtim_s *priv, uint32_t offset, uint32_t clrbits, uint32_t setbits) { hrtim_cmn_putreg(priv, offset, (hrtim_cmn_getreg(priv, offset) & ~clrbits) | setbits); @@ -1850,13 +1977,14 @@ errout: * ****************************************************************************/ -#if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) +#if defined(CONFIG_STM32_HRTIM_CAPTURE) || defined(CONFIG_STM32_HRTIM_PWM) || \ + defined(CONFIG_STM32_HRTIM_SYNC) static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) { -#ifdef HRTIM_HAVE_EEV +#ifdef CONFIG_STM32_HRTIM_EVENTS FAR struct stm32_hrtim_eev_s* eev = priv->eev; #endif -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_FAULTS FAR struct stm32_hrtim_faults_s* flt = priv->flt; #endif @@ -2048,7 +2176,7 @@ static int hrtim_gpios_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -#if defined(HRTIM_HAVE_CAPTURE) +#if defined(CONFIG_STM32_HRTIM_CAPTURE) static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv) { #warning "hrtim_inputs_config: missing logic" @@ -2077,7 +2205,7 @@ static int hrtim_inputs_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -#if defined(HRTIM_HAVE_SYNC) +#if defined(CONFIG_STM32_HRTIM_SYNC) static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv) { #warning "hrtim_synch_config: missing logic" @@ -2099,7 +2227,7 @@ static int hrtim_synch_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -#if defined(HRTIM_HAVE_PWM) +#if defined(CONFIG_STM32_HRTIM_PWM) static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t timer) { FAR struct stm32_hrtim_tim_s* tim; @@ -2147,6 +2275,47 @@ static int hrtim_tim_outputs_config(FAR struct stm32_hrtim_s *priv, uint8_t time regval = slave->pwm.ch2.rst; hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RST2R_OFFSET, regval); +#ifdef CONFIG_STM32_HRTIM_BURST + + /* Configure IDLE state for output 1 */ + + if (slave->pwm.burst.ch1_en) + { + regval = 0; + + /* Set IDLE mode */ + + regval |= HRTIM_TIMOUT_IDLEM1; + + /* Set Idle state */ + + regval |= ((slave->pwm.burst.ch1_state & HRTIM_IDLE_ACTIVE) ? HRTIM_TIMOUT_IDLES1 : 0); + + /* Write register */ + + hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, regval); + } + + /* Configure IDLE state for output 2 */ + + if (slave->pwm.burst.ch2_en) + { + regval = 0; + + /* Set IDLE mode */ + + regval |= HRTIM_TIMOUT_IDLEM1; + + /* Set Idle state */ + + regval |= ((slave->pwm.burst.ch2_state & HRTIM_IDLE_ACTIVE) ? HRTIM_TIMOUT_IDLES1 : 0); + + /* Write register */ + + hrtim_tim_modifyreg(priv, timer, STM32_HRTIM_TIM_OUTR_OFFSET, 0, regval); + } +#endif + errout: return ret; } @@ -2166,7 +2335,7 @@ errout: * ****************************************************************************/ -#if defined(HRTIM_HAVE_PWM) +#if defined(CONFIG_STM32_HRTIM_PWM) static int hrtim_outputs_config(FAR struct stm32_hrtim_s *priv) { int ret = OK; @@ -2280,7 +2449,7 @@ static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs, * ****************************************************************************/ -#ifdef HRTIM_HAVE_ADC +#ifdef CONFIG_STM32_HRTIM_ADC static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv) { @@ -2467,7 +2636,142 @@ static int hrtim_dma_cfg(FAR struct stm32_hrtim_s *priv) } #endif /* CONFIG_STM32_HRTIM_DAM */ -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_DEADTIME + +/**************************************************************************** + * Name: hrtim_deadtime_config + ****************************************************************************/ + +static int hrtim_deadtime_config(FAR struct stm32_hrtim_s *priv) +{ + return OK; +} + +#endif /* CONFIG_STM32_HRTIM_DEADTIME */ + +#ifdef CONFIG_STM32_HRTIM_BURST + +/**************************************************************************** + * Name: hrtim_burst_enable + ****************************************************************************/ + +int hrtim_burst_enable(FAR struct hrtim_dev_s *dev, bool state) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + + if (state) + { + /* Software start */ + + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET, 0, HRTIM_BMTRGR_SW); + } + else + { + /* Software termination */ + + hrtim_cmn_modifyreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, HRTIM_BMCR_BMSTAT, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: hrtim_burst_cmp_update + ****************************************************************************/ + +int hrtim_burst_cmp_update(FAR struct hrtim_dev_s *dev, uint16_t cmp) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET, cmp); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_burst_per_update + ****************************************************************************/ + +int hrtim_burst_per_update(FAR struct hrtim_dev_s *dev, uint16_t per) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET, per); + + return OK; +} + +/**************************************************************************** + * Name: hrtim_burst_cmp_get + ****************************************************************************/ + +uint16_t hrtim_burst_cmp_get(FAR struct hrtim_dev_s *dev) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + + return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMCMPR_OFFSET);; +} + +/**************************************************************************** + * Name: hrtim_burst_per_get + ****************************************************************************/ + +uint16_t hrtim_burst_per_get(FAR struct hrtim_dev_s *dev) +{ + FAR struct stm32_hrtim_s *priv = (FAR struct stm32_hrtim_s *)dev->hd_priv; + + return (uint16_t)hrtim_cmn_getreg(priv, STM32_HRTIM_CMN_BMPER_OFFSET); +} + +/**************************************************************************** + * Name: hrtim_burst_config + ****************************************************************************/ + +static int hrtim_burst_config(FAR struct stm32_hrtim_s *priv) +{ + FAR struct stm32_hrtim_burst_s *burst = priv->burst; + uint32_t regval = 0; + + /* Configure triggers */ + + regval = burst->trg; + + /* Write triggers register */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMTRGR_OFFSET, regval); + + /* TODO: timers mode configuration */ + + regval = 0; + + /* Configure burst mode clock source */ + + regval |= (burst->clk << HRTIM_BMCR_BMCLK_SHIFT); + + /* Configure burst mode prescaler if f_HRTIM clock */ + + if (burst->clk == HRTIM_BURST_CLOCK_HRTIM) + { + regval |= (burst->presc << HRTIM_BMCR_BMPRSC_SHIFT); + } + + /* Set continuous mode */ + + regval |= HRTIM_BMCR_BMOM; + + /* Enable burst mode */ + + regval |= HRTIM_BMCR_BME; + + /* Write Burst Mode CR */ + + hrtim_cmn_putreg(priv, STM32_HRTIM_CMN_BMCR_OFFSET, regval); + + return OK; +} +#endif + +#ifdef CONFIG_STM32_HRTIM_FAULTS /**************************************************************************** * Name: hrtim_tim_faults_cfg @@ -2724,7 +3028,7 @@ static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv) } #endif -#ifdef HRTIM_HAVE_EEV +#ifdef CONFIG_STM32_HRTIM_EVENTS /**************************************************************************** * Name: hrtim_eev_cfg @@ -2970,7 +3274,7 @@ static int hrtim_events_config(FAR struct stm32_hrtim_s *priv) return OK; } -#endif /* HRTIM_HAVE_FAULTS */ +#endif /* CONFIG_STM32_HRTIM_FAULTS */ /**************************************************************************** * Name: hrtim_irq_config @@ -2986,7 +3290,7 @@ static int hrtim_events_config(FAR struct stm32_hrtim_s *priv) * ****************************************************************************/ -#ifdef HRTIM_HAVE_INTERRUPTS +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS static int hrtim_irq_config(FAR struct stm32_hrtim_s *priv) { #warning "hrtim_irq_config: missing logic" @@ -2997,7 +3301,7 @@ void hrtim_irq_ack(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); { #warning "hrtim_irq_ack: missing logic" } -#endif /* HRTIM_HAVE_INTERRUPTS */ +#endif /* CONFIG_STM32_HRTIM_INTERRUPTS */ /**************************************************************************** * Name: hrtim_tim_mode_set @@ -3444,13 +3748,14 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure auto-delayed mode */ -#ifdef HRTIM_HAVE_AUTODELAYED +#ifdef CONFIG_STM32_HRTIM_AUTODELAYED hrtim_autodelayed_config(priv); #endif /* Configure HRTIM GPIOs */ -#if defined(HRTIM_HAVE_CAPTURE) || defined(HRTIM_HAVE_PWM) || defined(HRTIM_HAVE_SYNC) +#if defined(CONFIG_STM32_HRTIM_CAPTURE) || defined(CONFIG_STM32_HRTIM_PWM) || \ + defined(CONFIG_STM32_HRTIM_SYNC) ret = hrtim_gpios_config(priv); if (ret != OK) { @@ -3461,7 +3766,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure HRTIM inputs */ -#if defined(HRTIM_HAVE_CAPTURE) +#if defined(CONFIG_STM32_HRTIM_CAPTURE) ret = hrtim_inputs_config(priv); if (ret != OK) { @@ -3472,7 +3777,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure Synchronisation IOs */ -#if defined(HRTIM_HAVE_SYNC) +#if defined(CONFIG_STM32_HRTIM_SYNC) ret = hrtim_synch_config(priv); if (ret != OK) { @@ -3483,7 +3788,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure HRTIM outputs GPIOs */ -#if defined(HRTIM_HAVE_PWM) +#if defined(CONFIG_STM32_HRTIM_PWM) ret = hrtim_outputs_config(priv); if (ret != OK) { @@ -3494,7 +3799,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure ADC triggers */ -#ifdef HRTIM_HAVE_ADC +#ifdef CONFIG_STM32_HRTIM_ADC ret = hrtim_adc_config(priv); if (ret != OK) { @@ -3516,7 +3821,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure Faults */ -#ifdef HRTIM_HAVE_FAULTS +#ifdef CONFIG_STM32_HRTIM_FAULTS ret = hrtim_faults_config(priv); if (ret != OK) { @@ -3527,7 +3832,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure External Events */ -#ifdef HRTIM_HAVE_EEV +#ifdef CONFIG_STM32_HRTIM_EVENTS ret = hrtim_events_config(priv); if (ret != OK) { @@ -3538,7 +3843,7 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) /* Configure interrupts */ -#ifdef HRTIM_HAVE_INTERRUPTS +#ifdef CONFIG_STM32_HRTIM_INTERRUTPS ret = hrtim_irq_config(priv); if (ret != OK) { @@ -3547,6 +3852,8 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) } #endif + /* Configure DMA */ + #ifdef CONFIG_STM32_HRTIM_DMA ret = hrtim_dma_cfg(priv); if (ret != OK) @@ -3556,6 +3863,17 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) } #endif + /* Configure burst mode */ + +#ifdef CONFIG_STM32_HRTIM_BURST + ret = hrtim_burst_config(priv); + if (ret != OK) + { + tmrerr("ERROR: HRTIM burst mode configuration failed!\n"); + goto errout; + } +#endif + /* Enable Master Timer */ #ifdef CONFIG_STM32_HRTIM_MASTER @@ -3643,6 +3961,7 @@ FAR struct hrtim_dev_s* stm32_hrtiminitialize(void) * Name: hrtim_register ****************************************************************************/ +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev) { int ret ; @@ -3665,6 +3984,7 @@ int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev) return ret; } +#endif /* CONFIG_STM32_HRTIM_DISABLE_CHARDRV */ #endif /* CONFIG_STM32_STM32F33XX */ #endif /* CONFIG_STM32_HRTIM1 */ diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index 4f562044cd1..ffd36232a5a 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -65,41 +65,55 @@ #if defined(CONFIG_STM32_HRTIM_TIMA_PWM) || defined(CONFIG_STM32_HRTIM_TIMB_PWM) || \ defined(CONFIG_STM32_HRTIM_TIMC_PWM) || defined(CONFIG_STM32_HRTIM_TIMD_PWM) || \ defined(CONFIG_STM32_HRTIM_TIME_PWM) -# define HRTIM_HAVE_PWM 1 +# ifndef CONFIG_STM32_HRTIM_PWM +# error "CONFIG_STM32_HRTIM_PWM must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_TIMA_CAP) || defined(CONFIG_STM32_HRTIM_TIMB_CAP) || \ defined(CONFIG_STM32_HRTIM_TIMC_CAP) || defined(CONFIG_STM32_HRTIM_TIMD_CAP) || \ defined(CONFIG_STM32_HRTIM_TIME_CAP) -# define HRTIM_HAVE_CAPTURE 1 +# ifndef CONFIG_STM32_HRTIM_CAPTURE +# error "CONFIG_STM32_HRTIM_CAPTURE must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_TIMA_DT) || defined(CONFIG_STM32_HRTIM_TIMB_DT) || \ defined(CONFIG_STM32_HRTIM_TIMC_DT) || defined(CONFIG_STM32_HRTIM_TIMD_DT) || \ defined(CONFIG_STM32_HRTIM_TIME_DT) -# define HRTIM_HAVE_DEADTIME 1 +# ifndef CONFIG_STM32_HRTIM_DEADTIME +# error "CONFIG_STM32_HRTIM_DEADTIME must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_TIMA_CHOP) || defined(CONFIG_STM32_HRTIM_TIMB_CHOP) || \ defined(CONFIG_STM32_HRTIM_TIMC_CHOP) || defined(CONFIG_STM32_HRTIM_TIMD_CHOP) || \ defined(CONFIG_STM32_HRTIM_TIME_CHOP) -# define HRTIM_HAVE_CHOPPER 1 +# ifndef CONFIG_STM32_HRTIM_CHOPPER +# error "CONFIG_STM32_HRTIM_CHOPPER must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_TIMA_BURST) || defined(CONFIG_STM32_HRTIM_TIMB_BURST) || \ defined(CONFIG_STM32_HRTIM_TIMC_BURST) || defined(CONFIG_STM32_HRTIM_TIMD_BURST) || \ defined(CONFIG_STM32_HRTIM_TIME_BURST) -# define HRTIM_HAVE_BURST_MODE 1 +# ifndef CONFIG_STM32_HRTIM_BURST +# error "CONFIG_STM32_HRTIM_BURST must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_SCOUT) || defined(CONFIG_STM32_HRTIM_SCIN) -# define HRTIM_HAVE_SYNC 1 +# ifndef CONFIG_STM32_HRTIM_SYNC +# error "CONFIG_STM32_HRTIM_SYNC must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_FAULT1) || defined(CONFIG_STM32_HRTIM_FAULT2) || \ defined(CONFIG_STM32_HRTIM_FAULT3) || defined(CONFIG_STM32_HRTIM_FAULT4) || \ defined(CONFIG_STM32_HRTIM_FAULT5) -# define HRTIM_HAVE_FAULTS 1 +# ifndef CONFIG_STM32_HRTIM_FAULTS +# error "CONFIG_STM32_HRTIM_FAULTS must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_EEV1) || defined(CONFIG_STM32_HRTIM_EEV2) || \ @@ -107,19 +121,25 @@ defined(CONFIG_STM32_HRTIM_EEV5) || defined(CONFIG_STM32_HRTIM_EEV6) || \ defined(CONFIG_STM32_HRTIM_EEV7) || defined(CONFIG_STM32_HRTIM_EEV8) || \ defined(CONFIG_STM32_HRTIM_EEV9) || defined(CONFIG_STM32_HRTIM_EEV10) -# define HRTIM_HAVE_EEV 1 +# ifndef CONFIG_STM32_HRTIM_EVENTS +# error "CONFIG_STM32_HRTIM_EVENTS must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_MASTER_IRQ) || defined(CONFIG_STM32_HRTIM_TIMA_IRQ) || \ defined(CONFIG_STM32_HRTIM_TIMB_IRQ) || defined(CONFIG_STM32_HRTIM_TIMC_IRQ) || \ defined(CONFIG_STM32_HRTIM_TIMD_IRQ) || defined(CONFIG_STM32_HRTIM_TIME_IRQ) || \ defined(CONFIG_STM32_HRTIM_CMN_IRQ) -# define HRTIM_HAVE_INTERRUPTS 1 +# ifndef CONFIG_STM32_HRTIM_INTERRUPTS +# error "CONFIG_STM32_HRTIM_INTERRUPTS must be set" +# endif #endif #if defined(CONFIG_STM32_HRTIM_ADC_TRG1) || defined(CONFIG_STM32_HRTIM_ADC_TRG2) || \ defined(CONFIG_STM32_HRTIM_ADC_TRG3) || defined(CONFIG_STM32_HRTIM_ADC_TRG4) -# define HRTIM_HAVE_ADC 1 +# ifndef CONFIG_STM32_HRTIM_ADC +# error "CONFIG_STM32_HRTIM_ADC must be set" +# endif #endif /* TIMX PWM configuration checking */ @@ -716,16 +736,16 @@ enum stm32_irq_cmn_e enum stm32_hrtim_dma_e { - HRTIM_DMA_CMP1 = (1 << 0), /* Common: Compare 1 DMA request */ - HRTIM_DMA_CMP2 = (1 << 1), /* Common: Compare 2 DMA request */ - HRTIM_DMA_CMP3 = (1 << 2), /* Common: Compare 3 DMA request */ - HRTIM_DMA_CMP4 = (1 << 3), /* Common:Compare 4 DMA request */ - HRTIM_DMA_REP = (1 << 4), /* Common: Repetition DMA request */ - HRTIM_DMA_SYNC = (1 << 5), /* Master: Sync Input DMA request */ - HRTIM_DMA_UPD = (1 << 6), /* Common: Update DMA reques */ - HRTIM_DMA_CPT1 = (1 << 7), /* Slaves: Capture 1 DMA reques */ - HRTIM_DMA_CPT2 = (1 << 8), /* Slaves: Capture 2 DMA reques */ - HRTIM_DMA_SET1 = (1 << 9), /* Slaves: Output 1 Set DMA reques */ + HRTIM_DMA_CMP1 = (1 << 0), /* Common: Compare 1 DMA request */ + HRTIM_DMA_CMP2 = (1 << 1), /* Common: Compare 2 DMA request */ + HRTIM_DMA_CMP3 = (1 << 2), /* Common: Compare 3 DMA request */ + HRTIM_DMA_CMP4 = (1 << 3), /* Common:Compare 4 DMA request */ + HRTIM_DMA_REP = (1 << 4), /* Common: Repetition DMA request */ + HRTIM_DMA_SYNC = (1 << 5), /* Master: Sync Input DMA request */ + HRTIM_DMA_UPD = (1 << 6), /* Common: Update DMA reques */ + HRTIM_DMA_CPT1 = (1 << 7), /* Slaves: Capture 1 DMA reques */ + HRTIM_DMA_CPT2 = (1 << 8), /* Slaves: Capture 2 DMA reques */ + HRTIM_DMA_SET1 = (1 << 9), /* Slaves: Output 1 Set DMA reques */ HRTIM_DMA_RST1 = (1 << 10), /* Slaves: Output 1 Reset DMA reques */ HRTIM_DMA_SET2 = (1 << 11), /* Slaves: Output 2 Set DMA reques */ HRTIM_DMA_RST2 = (1 << 12), /* Slaves: Output 2 Reset DMA reques */ @@ -733,6 +753,90 @@ enum stm32_hrtim_dma_e HRTIM_DMA_DLYPRT = (1 << 14) /* Slaves: Delayed Protection DMA reques */ }; +/* HRTIM Output IDLE state */ + +enum stm32_hrtim_idle_state +{ + HRTIM_IDLE_INACTIVE = 0, /* Output inactive during IDLE state */ + HRTIM_IDLE_ACTIVE = 1 /* Output active during IDLE state */ +}; + +/* HRTIM Burst Mode clock source */ + +enum stm32_hrtim_burst_source_e +{ + HRTIM_BURST_CLOCK_MASTER = 0, /* Master timer counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIMA = 1, /* Timer A counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIMB = 2, /* Timer B counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIMC = 3, /* Timer C counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIMD = 4, /* Timer D counter reset/roll-over */ + HRTIM_BURST_CLOCK_TIME = 5, /* Timer E counter reset/roll-over */ + HRTIM_BURST_CLOCK_EV1 = 6, /* On-chip Event 1 */ + HRTIM_BURST_CLOCK_EV2 = 7, /* On-chip Event 2 */ + HRTIM_BURST_CLOCK_EV3 = 8, /* On-chip Event 3 */ + HRTIM_BURST_CLOCK_EV4 = 9, /* On-chip Event 4 */ + HRTIM_BURST_CLOCK_HRTIM = 10 /* Prescaled f_HRTIM clock */ +}; + +/* HRTIM Burst Mode prescaler for fHRTIM clock */ + +enum stm32_hrtim_burst_precaler_e +{ + HRTIM_BURST_PRESCALER_0 = 0, + HRTIM_BURST_PRESCALER_2 = 1, + HRTIM_BURST_PRESCALER_4 = 2, + HRTIM_BURST_PRESCALER_8 = 3, + HRTIM_BURST_PRESCALER_16 = 4, + HRTIM_BURST_PRESCALER_32 = 5, + HRTIM_BURST_PRESCALER_64 = 6, + HRTIM_BURST_PRESCALER_128 = 7, + HRTIM_BURST_PRESCALER_256 = 8, + HRTIM_BURST_PRESCALER_512 = 9, + HRTIM_BURST_PRESCALER_1024 = 10, + HRTIM_BURST_PRESCALER_2048 = 11, + HRTIM_BURST_PRESCALER_4096 = 12, + HRTIM_BURST_PRESCALER_8192 = 13, + HRTIM_BURST_PRESCALER_16384 = 14, + HRTIM_BURST_PRESCALER_32768 = 15 +}; + +/* HRTIM Burst Mode triggers */ + +enum stm32_hrtim_burst_triggers_e +{ + HRTIM_BURST_TRG_MSTRST = (1 << 1), + HRTIM_BURST_TRG_MSTREP = (1 << 2), + HRTIM_BURST_TRG_MSTCMP1 = (1 << 3), + HRTIM_BURST_TRG_MSTCMP2 = (1 << 4), + HRTIM_BURST_TRG_MSTCMP3 = (1 << 5), + HRTIM_BURST_TRG_MSTCMP4 = (1 << 6), + HRTIM_BURST_TRG_TARST = (1 << 7), + HRTIM_BURST_TRG_TAREP = (1 << 8), + HRTIM_BURST_TRG_TACMP1 = (1 << 9), + HRTIM_BURST_TRG_TACMP2 = (1 << 10), + HRTIM_BURST_TRG_TBRST = (1 << 11), + HRTIM_BURST_TRG_TBREP = (1 << 12), + HRTIM_BURST_TRG_TBCMP1 = (1 << 13), + HRTIM_BURST_TRG_TBCMP2 = (1 << 14), + HRTIM_BURST_TRG_TCRST = (1 << 15), + HRTIM_BURST_TRG_TCREP = (1 << 16), + HRTIM_BURST_TRG_TCCMP1 = (1 << 17), + HRTIM_BURST_TRG_TCCMP2 = (1 << 18), + HRTIM_BURST_TRG_TDRST = (1 << 19), + HRTIM_BURST_TRG_TDREP = (1 << 20), + HRTIM_BURST_TRG_TDCMP1 = (1 << 21), + HRTIM_BURST_TRG_TDCMP2 = (1 << 22), + HRTIM_BURST_TRG_TERST = (1 << 23), + HRTIM_BURST_TRG_TEREP = (1 << 24), + HRTIM_BURST_TRG_TECMP1 = (1 << 25), + HRTIM_BURST_TRG_TECMP2 = (1 << 26), + HRTIM_BURST_TRG_TAEEV7 = (1 << 27), + HRTIM_BURST_TRG_TDEEV8 = (1 << 28), + HRTIM_BURST_TRG_EEV7 = (1 << 29), + HRTIM_BURST_TRG_EEV8 = (1 << 30), + HRTIM_BURST_TRG_OCHPEV = (1 << 31), +}; + /* HRTIM vtable */ struct hrtim_dev_s; @@ -744,13 +848,20 @@ struct stm32_hrtim_ops_s uint16_t (*per_get)(FAR struct hrtim_dev_s *dev, uint8_t timer); uint16_t (*cmp_get)(FAR struct hrtim_dev_s *dev, uint8_t timer, uint8_t index); -#ifdef HRTIM_HAVE_INTERRUPTS +#ifdef CONFIG_STM32_HRTIM_INTERRUPTS void (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source); #endif -#ifdef HRTIM_HAVE_PWM +#ifdef CONFIG_STM32_HRTIM_PWM int (*outputs_enable)(FAR struct hrtim_dev_s *dev, uint16_t outputs, bool state); #endif +#ifdef CONFIG_STM32_HRTIM_BURST + int (*burst_enable)(FAR struct hrtim_dev_s *dev, bool state); + int (*burst_cmp_set)(FAR struct hrtim_dev_s *dev, uint16_t cmp); + int (*burst_per_set)(FAR struct hrtim_dev_s *dev, uint16_t per); + uint16_t (*burst_cmp_get)(FAR struct hrtim_dev_s *dev); + uint16_t (*burst_per_get)(FAR struct hrtim_dev_s *dev); +#endif }; /* HRTIM device structure */ @@ -808,7 +919,9 @@ FAR struct hrtim_dev_s* stm32_hrtiminitialize(void); * Name: hrtim_register ****************************************************************************/ +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev); +#endif #undef EXTERN #ifdef __cplusplus diff --git a/include/nuttx/power/smps.h b/include/nuttx/power/smps.h index 8fb1b592ea8..d1eface593d 100644 --- a/include/nuttx/power/smps.h +++ b/include/nuttx/power/smps.h @@ -190,6 +190,7 @@ struct smps_s struct smps_limits_s limits; /* SMPS absolute limits */ struct smps_params_s param; /* SMPS settings */ struct smps_state_s state; /* SMPS state */ + FAR void *priv; /* Private data */ }; /* SMPS operations used to call from the upper-half, generic SMPS driver