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Squashed commit of the following:
arch/arm/src/kinetis: The K28F Kinetis MPU is almost the same as the K66F MPU.
arch/arm/src/kinetis: The K28F Kinetis FMC is the same as the K66F FMC.
This commit is contained in:
Gregory Nutt
@@ -1,7 +1,7 @@
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/********************************************************************************************
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* arch/arm/src/kinetis/chip/kinetis_fmc.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -44,16 +44,16 @@
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#include "chip.h"
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/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
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* by the logic in chip.h.
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/* This file is just a wrapper around FMC header files for the Kinetis family selected by
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* the logic in chip.h.
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*/
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#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
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# include "chip/kinetis_k20k40k60fmc.h"
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#elif defined(KINETIS_K64)
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# include "chip/kinetis_k64fmc.h"
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#elif defined(KINETIS_K66)
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# include "chip/kinetis_k66fmc.h"
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#elif defined(KINETIS_K28) || defined(KINETIS_K66)
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# include "chip/kinetis_k28k66fmc.h"
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#else
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# error "No FMC definitions for this Kinetis part"
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#endif
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+44
-12
@@ -1,7 +1,7 @@
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/****************************************************************************************************
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* arch/arm/src/kinetis/chip/kinetis_k64k66mpu.h
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* arch/arm/src/kinetis/chip/kinetis_k28k64k66mpu.h
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*
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* Copyright (C) 2011, 2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011, 2017-2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@@ -34,8 +34,8 @@
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64K66MPU_H
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#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64K66MPU_H
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#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K64K66MPU_H
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#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K64K66MPU_H
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/****************************************************************************************************
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* Included Files
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@@ -51,7 +51,7 @@
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/* Register Offsets *********************************************************************************/
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#define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */
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#define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */
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#define KINETIS_MPU_EAR_OFFSET(n) (0x0010+((n)<<3)) /* Error Address Register, Slave Port n */
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#define KINETIS_MPU_EDR_OFFSET(n) (0x0014+((n)<<3)) /* Error Detail Register, Slave Port n */
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@@ -67,6 +67,13 @@
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#define KINETIS_MPU_EAR4_OFFSET 0x0030 /* Error Address Register, Slave Port 4 */
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#define KINETIS_MPU_EDR4_OFFSET 0x0034 /* Error Detail Register, Slave Port 4 */
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#if defined(KINETIS_K28)
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# define KINETIS_MPU_EAR5_OFFSET 0x0038 /* Error Address Register, Slave Port 5 */
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# define KINETIS_MPU_EDR5_OFFSET 0x003c /* Error Detail Register, Slave Port 5 */
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# define KINETIS_MPU_EAR6_OFFSET 0x0040 /* Error Address Register, Slave Port 6 */
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# define KINETIS_MPU_EDR6_OFFSET 0x0044 /* Error Detail Register, Slave Port 6 */
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#endif
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#define KINETIS_MPU_RGD_WORD_OFFSET(n,m) (x0400+((n)<<4)+((m)<< 2) /* Region Descriptor n, Word m */
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#define KINETIS_MPU_RGD0_WORD0_OFFSET 0x0400 /* Region Descriptor 0, Word 0 */
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@@ -151,6 +158,13 @@
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#define KINETIS_MPU_EAR4 (KINETIS_MPU_BASE+KINETIS_MPU_EAR4_OFFSET)
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#define KINETIS_MPU_EDR4 (KINETIS_MPU_BASE+KINETIS_MPU_EDR4_OFFSET)
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#if defined(KINETIS_K28)
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# define KINETIS_MPU_EAR5 (KINETIS_MPU_BASE+KINETIS_MPU_EAR5_OFFSET)
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# define KINETIS_MPU_EDR5 (KINETIS_MPU_BASE+KINETIS_MPU_EDR5_OFFSET)
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# define KINETIS_MPU_EAR6 (KINETIS_MPU_BASE+KINETIS_MPU_EAR6_OFFSET)
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# define KINETIS_MPU_EDR7 (KINETIS_MPU_BASE+KINETIS_MPU_EDR6_OFFSET)
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#endif
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#define KINETIS_MPU_RGD_WORD(n,m) (KINETIS_MPU_BASE+KINETIS_MPU_RGD_WORD_OFFSET(n,m))
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#define KINETIS_MPU_RGD0_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD0_OFFSET)
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@@ -255,7 +269,10 @@
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# define MPU_EDR_EATTR_SUPDATA (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */
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#define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error master number */
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#define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT)
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/* Bits 8-15: Reserved */
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#if defined(KINETIS_K28)
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# define MPU_EDR_EPID_SHIFT (8) /* Bits 8-15: Error Process Identification */
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# define MPU_EDR_EPID_MASK (0xff << MPU_EDR_EPID_SHIFT)
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#endif
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#define MPU_EDR_EACD_SHIFT (26) /* Bits 16-31: Error access control detail */
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#define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT)
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@@ -312,29 +329,44 @@
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/* Region Descriptor n, Word 3 */
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#define MPU_RGD_WORD3_VLD (1 << 0) /* Bit 0: Valid */
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/* Bits 1-31: Reserved */
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/* Bits 1-15: Reserved */
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#if defined(KINETIS_K28)
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# define MPU_EDR_PIDMASK_SHIFT (16) /* Bits 16-23: Process Identifier Mask */
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# define MPU_EDR_PIDMASK_MASK (0xff << MPU_EDR_EPID_SHIFT)
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# define MPU_EDR_PID_SHIFT (24) /* Bits 24-31: Process Identifier */
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# define MPU_EDR_PID_MASK (0xff << MPU_EDR_EPID_SHIFT)
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#endif
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/* Region Descriptor Alternate Access Control n */
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#define MPU_RGD_RBDACC_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */
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#define MPU_RGD_RBDACC_M0UM_MASK (7 << MPU_RGD_RBDACC_M0UM_SHIFT)
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#define MPU_RGD_RBDACC_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */
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#define MPU_RGD_RBDACC_M0SM_MASK (3 << MPU_RGD_RBDACC_M0SM_SHIFT)
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/* Bit 5: Reserved */
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#if defined(KINETIS_K28)
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# define MPU_RGD_RBDACC_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier Enable */
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#endif
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#define MPU_RGD_RBDACC_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */
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#define MPU_RGD_RBDACC_M1UM_MASK (7 << MPU_RGD_RBDACC_M1UM_SHIFT)
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#define MPU_RGD_RBDACC_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */
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#define MPU_RGD_RBDACC_M1SM_MASK (3 << MPU_RGD_RBDACC_M1SM_SHIFT)
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/* Bit 11: Reserved */
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#if defined(KINETIS_K28)
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# define MPU_RGD_RBDACC_M1PE (1 << 11) /* Bit 11: Bus Master 1 Process Identifier Enable */
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#endif
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#define MPU_RGD_RBDACC_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */
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#define MPU_RGD_RBDACC_M2UM_MASK (7 << MPU_RGD_RBDACC_M2UM_SHIFT)
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#define MPU_RGD_RBDACC_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */
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#define MPU_RGD_RBDACC_M2SM_MASK (3 << MPU_RGD_RBDACC_M2SM_SHIFT)
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/* Bit 17: Reserved */
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#if defined(KINETIS_K28)
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# define MPU_RGD_RBDACC_M2PE (1 << 17) /* Bit 17: Bus Master 2 Process Identifier Enable */
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#endif
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#define MPU_RGD_RBDACC_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */
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#define MPU_RGD_RBDACC_M3UM_MASK (7 << MPU_RGD_RBDACC_M3UM_SHIFT)
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#define MPU_RGD_RBDACC_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */
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#define MPU_RGD_RBDACC_M3SM_MASK (3 << MPU_RGD_RBDACC_M3SM_SHIFT)
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/* Bit 23: Reserved */
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#if defined(KINETIS_K28)
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# define MPU_RGD_RBDACC_M3PE (1 << 23) /* Bit 23: Bus Master 3 Process Identifier Enable */
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#endif
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#define MPU_RGD_RBDACC_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */
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#define MPU_RGD_RBDACC_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */
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#define MPU_RGD_RBDACC_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */
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@@ -356,4 +388,4 @@
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* Public Functions
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****************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64K66MPU_H */
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#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K64K66MPU_H */
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+6
-6
@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/kinetis/kinetis_k66fmc.h
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* arch/arm/src/kinetis/kinetis_k28k66fmc.h
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*
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* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2016-2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@@ -34,8 +34,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66FMC_H
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#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66FMC_H
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#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K66FMC_H
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#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K66FMC_H
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/************************************************************************************
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* Included Files
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@@ -306,7 +306,7 @@
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# define FMC_PFB01CR_CRC_ALL (0 << FMC_PFB01CR_CRC_SHIFT) /* LRU all four ways */
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# define FMC_PFB01CR_CRC_I01D23 (2 << FMC_PFB01CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */
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# define FMC_PFB01CR_CRC_I012D3 (3 << FMC_PFB01CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */
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/* Bits 8-16: Reserved */
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/* Bits 8-16: Reserved */
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#define FMC_PFB01CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */
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#define FMC_PFB01CR_B0MW_MASK (3 << FMC_PFB01CR_B0MW_SHIFT)
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# define FMC_PFB01CR_B0MW_32BITS (0 << FMC_PFB01CR_B0MW_SHIFT) /* 32 bits */
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@@ -361,4 +361,4 @@
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66FMC_H */
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#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K66FMC_H */
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@@ -1,7 +1,7 @@
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/********************************************************************************************
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* arch/arm/src/kinetis/chip/kinetis_mpu.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -44,14 +44,14 @@
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#include "chip.h"
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/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
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* by the logic in chip.h.
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/* This file is just a wrapper around MPU header files for the Kinetis family selected by the
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* in chip.h.
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*/
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#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
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# include "chip/kinetis_k20k40k60mpu.h"
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#elif defined(KINETIS_K64) || defined(KINETIS_K66)
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# include "chip/kinetis_k64k66mpu.h"
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#elif defined(KINETIS_K28) || defined(KINETIS_K64) || defined(KINETIS_K66)
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# include "chip/kinetis_k28k64k66mpu.h"
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#else
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# error "No MPU definitions for this Kinetis part"
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#endif
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