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arch/risc-v/esp32[c6]: Add LP_UART support
Add LP_UART support for esp32c6 Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
This commit is contained in:
Eren Terzioglu
committed by
Xiang Xiao
Xiang Xiao
parent
880c8e5d26
commit
1c48c0cba7
@@ -261,6 +261,10 @@ config ESPRESSIF_UART
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bool
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default n
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config ESPRESSIF_LP_UART
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bool
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default n
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config ESPRESSIF_UART0
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bool "UART0"
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default y
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@@ -275,6 +279,15 @@ config ESPRESSIF_UART1
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select UART1_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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config ESPRESSIF_LP_UART0
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bool "LP UART0"
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default n
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depends on ARCH_CHIP_ESP32C6
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select ESPRESSIF_UART
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select ESPRESSIF_LP_UART
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select LPUART0_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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config ESPRESSIF_TWAI
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bool "TWAI (CAN)"
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default n
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@@ -40,7 +40,9 @@
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/* Are any UARTs enabled? */
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#undef HAVE_UART_DEVICE
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#if defined(CONFIG_ESPRESSIF_UART0) || defined(CONFIG_ESPRESSIF_UART1)
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#if defined(CONFIG_ESPRESSIF_UART0) || \
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defined(CONFIG_ESPRESSIF_UART1) || \
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defined(CONFIG_ESPRESSIF_LP_UART0)
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# define HAVE_UART_DEVICE 1 /* Flag to indicate a UART has been selected */
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#endif
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@@ -61,15 +63,23 @@
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#undef CONSOLE_UART
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#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_UART0)
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_LPUART0_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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# define CONSOLE_UART 1
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_UART1)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_LPUART0_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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# define CONSOLE_UART 1
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#elif defined(CONFIG_LPUART0_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_LP_UART0)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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# define CONSOLE_UART 1
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#else
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_LPUART0_SERIAL_CONSOLE
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#endif
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#ifdef CONFIG_ESPRESSIF_USBSERIAL
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@@ -51,6 +51,23 @@
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#include "hal/uart_hal.h"
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#include "periph_ctrl.h"
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#include "soc/gpio_sig_map.h"
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#ifdef CONFIG_ESPRESSIF_LP_UART
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# include "lp_core_uart.h"
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# include "soc/uart_pins.h"
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# include "hal/rtc_io_hal.h"
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# include "soc/uart_periph.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_ESPRESSIF_LP_UART
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# define ESP_LP_UART0_ID LP_UART_NUM_0
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# define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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# define ESP_LP_UART0_ID UART_NUM_MAX
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#endif /* CONFIG_ESPRESSIF_LP_UART */
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/****************************************************************************
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* Private Types
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@@ -110,6 +127,7 @@ struct esp_uart_s g_uart0_config =
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.rs485_dir_polarity = true,
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#endif
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#endif
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.clk_src = UART_SCLK_DEFAULT,
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.hal = &g_uart0_hal,
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.lock = SP_UNLOCKED
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};
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@@ -164,13 +182,117 @@ struct esp_uart_s g_uart1_config =
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.rs485_dir_polarity = true,
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#endif
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#endif
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.clk_src = UART_SCLK_DEFAULT,
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.hal = &g_uart1_hal,
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.lock = SP_UNLOCKED
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};
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#endif /* CONFIG_ESPRESSIF_UART1 */
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#ifdef CONFIG_ESPRESSIF_LP_UART0
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static uart_hal_context_t g_lp_uart0_hal =
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{
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.dev = (hal_uart_dev_t *)&LP_UART
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};
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struct esp_uart_s g_lp_uart0_config =
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{
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.source = LP_UART_INTR_SOURCE,
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.cpuint = -ENOMEM,
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.int_pri = ESP_IRQ_PRIORITY_DEFAULT,
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.id = ESP_LP_UART0_ID,
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.irq = ESP_IRQ_LP_UART,
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.baud = CONFIG_LPUART0_BAUD,
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.stop_b2 = CONFIG_LPUART0_2STOP,
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.bits = CONFIG_LPUART0_BITS,
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.parity = CONFIG_LPUART0_PARITY,
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.txpin = LP_UART_DEFAULT_TX_GPIO_NUM,
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.txsig = LP_U0TXD_MUX_FUNC,
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.rxpin = LP_UART_DEFAULT_RX_GPIO_NUM,
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.rxsig = LP_U0RXD_MUX_FUNC,
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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.rtspin = LP_UART_DEFAULT_RTS_GPIO_NUM,
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.rtssig = LP_U0RTS_MUX_FUNC,
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#ifdef CONFIG_LPUART0_IFLOWCONTROL
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.iflow = true, /* input flow control (RTS) enabled */
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#else
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.iflow = false, /* input flow control (RTS) disabled */
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#endif
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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.ctspin = LP_UART_DEFAULT_CTS_GPIO_NUM,
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.ctssig = LP_U0CTS_MUX_FUNC,
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#ifdef CONFIG_LPUART0_OFLOWCONTROL
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.oflow = true, /* output flow control (CTS) enabled */
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#else
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.oflow = false, /* output flow control (CTS) disabled */
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#endif
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#endif
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.clk_src = LP_UART_SCLK_DEFAULT,
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.hal = &g_lp_uart0_hal,
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.lock = SP_UNLOCKED
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};
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#endif /* CONFIG_ESPRESSIF_LP_UART0 */
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#endif /* HAVE_UART_DEVICE */
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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#ifdef CONFIG_ESPRESSIF_LP_UART
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/****************************************************************************
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* Name: esp_lowputc_lp_uart_config_io
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*
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* Description:
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* Configures LP UART pin.
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*
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* Parameters:
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* priv - Pointer to the private driver struct.
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* pin - Pin number to configure.
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* direction - Pin direction to configure.
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* idx - Pin idx to configure.
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*
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* Return Value:
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* None.
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*
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****************************************************************************/
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static void esp_lowputc_lp_uart_config_io(const struct esp_uart_s *priv,
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int8_t pin,
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rtc_gpio_mode_t direction,
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uint32_t idx)
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{
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irqstate_t flags = spin_lock_irqsave(&priv->lock);
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int lp_pin = rtc_io_num_map[pin];
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DEBUGASSERT(lp_pin != -1);
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#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
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RTCIO_RCC_ATOMIC()
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{
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rtcio_ll_enable_io_clock(true);
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}
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#endif
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rtcio_hal_function_select(lp_pin, RTCIO_LL_FUNC_RTC);
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rtcio_hal_set_direction(pin, direction);
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const uart_periph_sig_t *upin =
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&uart_periph_signal[LP_UART_NUM_0].pins[idx];
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#if !SOC_LP_GPIO_MATRIX_SUPPORTED
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rtcio_hal_iomux_func_sel(lp_pin, upin->iomux_func);
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#else
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/* ToDo: Add LP UART for LP GPIO Matrix supported devices (e.g ESP32-P4) */
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#endif /* SOC_LP_GPIO_MATRIX_SUPPORTED */
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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#endif /* CONFIG_ESPRESSIF_LP_UART */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@@ -206,7 +328,10 @@ void esp_lowputc_send_byte(const struct esp_uart_s *priv, char byte)
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void esp_lowputc_enable_sysclk(const struct esp_uart_s *priv)
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{
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periph_module_enable(PERIPH_UART0_MODULE + priv->id);
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if (priv->id < ESP_LP_UART0_ID)
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{
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periph_module_enable(PERIPH_UART0_MODULE + priv->id);
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}
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}
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/****************************************************************************
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@@ -284,26 +409,28 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv)
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{
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/* Configure the pins */
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esp_configgpio(priv->rxpin, INPUT | PULLUP);
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esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
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if (priv->id < ESP_LP_UART0_ID)
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{
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esp_configgpio(priv->rxpin, INPUT | PULLUP);
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esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
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esp_configgpio(priv->txpin, OUTPUT);
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esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
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esp_configgpio(priv->txpin, OUTPUT);
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esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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if (priv->iflow)
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{
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esp_configgpio(priv->rtspin, OUTPUT);
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esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0);
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}
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if (priv->iflow)
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{
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esp_configgpio(priv->rtspin, OUTPUT);
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esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0);
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}
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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if (priv->oflow)
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{
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esp_configgpio(priv->ctspin, INPUT | PULLUP);
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esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
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}
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if (priv->oflow)
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{
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esp_configgpio(priv->ctspin, INPUT | PULLUP);
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esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
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}
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#endif
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#ifdef HAVE_RS485
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@@ -314,6 +441,41 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv)
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esp_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
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}
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#endif
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}
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#ifdef CONFIG_ESPRESSIF_LP_UART
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else
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{
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esp_lowputc_lp_uart_config_io(priv,
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priv->rxpin,
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RTC_GPIO_MODE_INPUT_ONLY,
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SOC_UART_RX_PIN_IDX);
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esp_lowputc_lp_uart_config_io(priv,
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priv->txpin,
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RTC_GPIO_MODE_OUTPUT_ONLY,
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SOC_UART_TX_PIN_IDX);
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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if (priv->iflow)
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{
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esp_lowputc_lp_uart_config_io(priv,
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priv->rtspin,
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RTC_GPIO_MODE_OUTPUT_ONLY,
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SOC_UART_RTS_PIN_IDX);
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}
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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if (priv->oflow)
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{
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esp_lowputc_lp_uart_config_io(priv,
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priv->ctspin,
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RTC_GPIO_MODE_INPUT_ONLY,
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SOC_UART_CTS_PIN_IDX);
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}
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#endif
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}
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#endif /* CONFIG_ESPRESSIF_LP_UART */
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}
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/****************************************************************************
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@@ -357,6 +519,8 @@ void riscv_lowputc(char ch)
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struct esp_uart_s *priv = &g_uart0_config;
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# elif defined (CONFIG_UART1_SERIAL_CONSOLE)
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struct esp_uart_s *priv = &g_uart1_config;
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# elif defined (CONFIG_LPUART0_SERIAL_CONSOLE)
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struct esp_uart_s *priv = &g_lp_uart0_config;
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# endif
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/* Wait until the TX FIFO has space to insert new char */
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@@ -393,5 +557,10 @@ void esp_lowsetup(void)
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esp_lowputc_config_pins(&g_uart1_config);
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#endif
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#ifdef CONFIG_ESPRESSIF_LP_UART0
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esp_lowputc_enable_sysclk(&g_lp_uart0_config);
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esp_lowputc_config_pins(&g_lp_uart0_config);
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#endif
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#endif /* !CONFIG_SUPPRESS_UART_CONFIG */
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}
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@@ -80,12 +80,14 @@ struct esp_uart_s
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uint8_t rs485_dir_gpio; /* UART RS-485 DIR GPIO pin cfg */
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bool rs485_dir_polarity; /* UART RS-485 DIR TXEN polarity */
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#endif
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soc_module_clk_t clk_src; /* Clock source */
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uart_hal_context_t *hal; /* HAL context */
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spinlock_t lock; /* Spinlock */
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};
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extern struct esp_uart_s g_uart0_config;
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extern struct esp_uart_s g_uart1_config;
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extern struct esp_uart_s g_lp_uart0_config;
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/****************************************************************************
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* Public Function Prototypes
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@@ -57,11 +57,22 @@
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#include "esp_clk_tree.h"
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#include "hal/uart_hal.h"
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#include "soc/clk_tree_defs.h"
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#include "periph_ctrl.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_ESPRESSIF_LP_UART
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# define LP_UART_SRC_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
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# define LP_UART_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
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# define LP_UART_RXBUFSIZE SOC_LP_UART_FIFO_LEN
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# define LP_UART_TXBUFSIZE SOC_LP_UART_FIFO_LEN
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# define ESP_LP_UART0_ID LP_UART_NUM_0
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#else
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# define ESP_LP_UART0_ID UART_NUM_MAX
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#endif
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/* The console is enabled and it's not the syslog device, so it should be a
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* serial device.
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*/
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@@ -89,15 +100,22 @@
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# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
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# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
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# define UART1_ASSIGNED 1
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# elif defined(CONFIG_LPUART0_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_lp_uart0_dev /* LPUART0 is console */
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# define TTYS0_DEV g_lp_uart0_dev /* LPUART0 is ttyS0 */
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# define LPUART0_ASSIGNED 1
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# endif /* CONFIG_UART0_SERIAL_CONSOLE */
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#else /* No UART console */
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# undef CONSOLE_DEV
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# if defined(CONFIG_ESPRESSIF_UART0)
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# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
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# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
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# define UART0_ASSIGNED 1
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# elif defined(CONFIG_ESPRESSIF_UART1)
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# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
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# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
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# define UART1_ASSIGNED 1
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# elif defined(CONFIG_ESPRESSIF_LP_UART0)
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# define TTYS0_DEV g_lp_uart0_dev /* LPUART0 is ttyS0 */
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# define LPUART0_ASSIGNED 1
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# endif
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#endif /* CONSOLE_UART */
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@@ -114,6 +132,22 @@
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#elif defined(CONFIG_ESPRESSIF_UART1) && !defined(UART1_ASSIGNED)
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# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
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# define UART1_ASSIGNED 1
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#elif defined(CONFIG_ESPRESSIF_LP_UART0) && !defined(LPUART0_ASSIGNED)
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# define TTYS1_DEV g_lp_uart0_dev /* LPUART0 is ttyS1 */
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# define LPUART0_ASSIGNED 1
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#endif
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/* Pick ttyS2 */
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#if defined(CONFIG_ESPRESSIF_UART0) && !defined(UART0_ASSIGNED)
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# define TTYS2_DEV g_uart0_dev /* UART0 is ttyS2 */
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# define UART0_ASSIGNED 1
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#elif defined(CONFIG_ESPRESSIF_UART1) && !defined(UART1_ASSIGNED)
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# define TTYS2_DEV g_uart1_dev /* UART1 is ttyS2 */
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# define UART1_ASSIGNED 1
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#elif defined(CONFIG_ESPRESSIF_LP_UART0) && !defined(LPUART0_ASSIGNED)
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# define TTYS2_DEV g_lp_uart0_dev /* LPUART0 is ttyS2 */
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# define LPUART0_ASSIGNED 1
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#endif
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#ifdef HAVE_UART_DEVICE
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@@ -237,6 +271,39 @@ static uart_dev_t g_uart1_dev =
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#endif
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/* LP UART */
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#ifdef CONFIG_ESPRESSIF_LP_UART0
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static char g_lp_uart0_rxbuffer[LP_UART_RXBUFSIZE];
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static char g_lp_uart0_txbuffer[LP_UART_TXBUFSIZE];
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/* Fill only the requested fields */
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static uart_dev_t g_lp_uart0_dev =
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{
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#ifdef CONFIG_LPUART0_SERIAL_CONSOLE
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.isconsole = true,
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#else
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.isconsole = false,
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#endif
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.xmit =
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{
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.size = LP_UART_TXBUFSIZE,
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.buffer = g_lp_uart0_txbuffer,
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},
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.recv =
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{
|
||||
.size = LP_UART_RXBUFSIZE,
|
||||
.buffer = g_lp_uart0_rxbuffer,
|
||||
},
|
||||
|
||||
.ops = &g_uart_ops,
|
||||
.priv = &g_lp_uart0_config
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_ESPRESSIF_UART */
|
||||
|
||||
/****************************************************************************
|
||||
@@ -392,16 +459,46 @@ static int esp_setup(uart_dev_t *dev)
|
||||
|
||||
esp_lowputc_enable_sysclk(priv);
|
||||
|
||||
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_DEFAULT,
|
||||
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)priv->clk_src,
|
||||
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
|
||||
&sclk_freq);
|
||||
|
||||
/* Initialize UART module */
|
||||
#ifdef CONFIG_ESPRESSIF_LP_UART
|
||||
if (priv->id >= LP_UART_NUM_0)
|
||||
{
|
||||
/* Enable LP UART bus clock */
|
||||
|
||||
LP_UART_SRC_CLK_ATOMIC()
|
||||
{
|
||||
lp_uart_ll_enable_bus_clock(0, true);
|
||||
lp_uart_ll_set_source_clk(priv->hal->dev, sclk_freq);
|
||||
lp_uart_ll_sclk_enable(0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
uart_hal_init(priv->hal, priv->id);
|
||||
uart_hal_set_mode(priv->hal, UART_MODE_UART);
|
||||
uart_hal_set_sclk(priv->hal, UART_SCLK_DEFAULT);
|
||||
uart_hal_set_baudrate(priv->hal, priv->baud, sclk_freq);
|
||||
if (priv->id < ESP_LP_UART0_ID)
|
||||
{
|
||||
uart_hal_set_sclk(priv->hal, UART_SCLK_DEFAULT);
|
||||
uart_hal_set_baudrate(priv->hal, priv->baud, sclk_freq);
|
||||
}
|
||||
#ifdef CONFIG_ESPRESSIF_LP_UART
|
||||
else
|
||||
{
|
||||
/* Override protocol parameters from the configuration */
|
||||
|
||||
if (!lp_uart_ll_set_baudrate(priv->hal->dev, priv->baud, sclk_freq))
|
||||
{
|
||||
/* Unachievable baud rate */
|
||||
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
uart_hal_set_parity(priv->hal, priv->parity);
|
||||
set_data_length(priv);
|
||||
set_stop_length(priv);
|
||||
@@ -1136,12 +1233,20 @@ void riscv_earlyserialinit(void)
|
||||
esp_lowputc_disable_all_uart_int(TTYS1_DEV.priv, NULL);
|
||||
#endif
|
||||
|
||||
#ifdef TTYS2_DEV
|
||||
esp_lowputc_disable_all_uart_int(TTYS2_DEV.priv, NULL);
|
||||
#endif
|
||||
|
||||
/* Configure console in early step.
|
||||
* Setup for other serials will be performed when the serial driver is
|
||||
* open.
|
||||
*/
|
||||
|
||||
#ifdef CONSOLE_UART
|
||||
#if defined(CONSOLE_UART) && !defined(CONFIG_LPUART0_SERIAL_CONSOLE)
|
||||
/* To use LPUART as console properly, device
|
||||
* needs finish booting process completely
|
||||
*/
|
||||
|
||||
esp_setup(&CONSOLE_DEV);
|
||||
#endif
|
||||
}
|
||||
@@ -1166,6 +1271,13 @@ void riscv_earlyserialinit(void)
|
||||
void riscv_serialinit(void)
|
||||
{
|
||||
#ifdef HAVE_SERIAL_CONSOLE
|
||||
# ifdef CONFIG_LPUART0_SERIAL_CONSOLE
|
||||
/* To use LPUART as console properly, device
|
||||
* needs finish booting process completely
|
||||
*/
|
||||
|
||||
esp_setup(&CONSOLE_DEV);
|
||||
# endif
|
||||
uart_register("/dev/console", &CONSOLE_DEV);
|
||||
#endif
|
||||
|
||||
@@ -1177,6 +1289,10 @@ void riscv_serialinit(void)
|
||||
uart_register("/dev/ttyS1", &TTYS1_DEV);
|
||||
#endif
|
||||
|
||||
#ifdef TTYS2_DEV
|
||||
uart_register("/dev/ttyS2", &TTYS2_DEV);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ESPRESSIF_USBSERIAL
|
||||
uart_register("/dev/ttyACM0", &TTYACM0_DEV);
|
||||
#endif
|
||||
|
||||
@@ -75,6 +75,9 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
|
||||
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register
|
||||
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
|
||||
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
|
||||
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp
|
||||
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core
|
||||
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)include
|
||||
|
||||
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
|
||||
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
|
||||
@@ -176,6 +179,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rtc_io_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal_iram.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c
|
||||
@@ -203,7 +207,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
|
||||
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)gpio.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c
|
||||
@@ -227,7 +233,6 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
|
||||
|
||||
Reference in New Issue
Block a user