diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig
index 99dc5a6f340..0c8d3ef27dd 100644
--- a/arch/risc-v/src/common/espressif/Kconfig
+++ b/arch/risc-v/src/common/espressif/Kconfig
@@ -261,6 +261,10 @@ config ESPRESSIF_UART
 	bool
 	default n
 
+config ESPRESSIF_LP_UART
+	bool
+	default n
+
 config ESPRESSIF_UART0
 	bool "UART0"
 	default y
@@ -275,6 +279,15 @@ config ESPRESSIF_UART1
 	select UART1_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
+config ESPRESSIF_LP_UART0
+	bool "LP UART0"
+	default n
+	depends on ARCH_CHIP_ESP32C6
+	select ESPRESSIF_UART
+	select ESPRESSIF_LP_UART
+	select LPUART0_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
 config ESPRESSIF_TWAI
 	bool "TWAI (CAN)"
 	default n
diff --git a/arch/risc-v/src/common/espressif/esp_config.h b/arch/risc-v/src/common/espressif/esp_config.h
index 5ad2603f486..9e1466fa7ea 100644
--- a/arch/risc-v/src/common/espressif/esp_config.h
+++ b/arch/risc-v/src/common/espressif/esp_config.h
@@ -40,7 +40,9 @@
 /* Are any UARTs enabled? */
 
 #undef HAVE_UART_DEVICE
-#if defined(CONFIG_ESPRESSIF_UART0) || defined(CONFIG_ESPRESSIF_UART1)
+#if defined(CONFIG_ESPRESSIF_UART0) || \
+    defined(CONFIG_ESPRESSIF_UART1) || \
+    defined(CONFIG_ESPRESSIF_LP_UART0)
 #  define HAVE_UART_DEVICE 1 /* Flag to indicate a UART has been selected */
 #endif
 
@@ -61,15 +63,23 @@
 #undef CONSOLE_UART
 #if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_UART0)
 #  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART0_SERIAL_CONSOLE
 #  define HAVE_SERIAL_CONSOLE 1
 #  define CONSOLE_UART 1
 #elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_UART1)
 #  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_LPUART0_SERIAL_CONSOLE
+#  define HAVE_SERIAL_CONSOLE 1
+#  define CONSOLE_UART 1
+#elif defined(CONFIG_LPUART0_SERIAL_CONSOLE) && defined(CONFIG_ESPRESSIF_LP_UART0)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
 #  define HAVE_SERIAL_CONSOLE 1
 #  define CONSOLE_UART 1
 #else
 #  undef CONFIG_UART0_SERIAL_CONSOLE
 #  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_LPUART0_SERIAL_CONSOLE
 #endif
 
 #ifdef CONFIG_ESPRESSIF_USBSERIAL
diff --git a/arch/risc-v/src/common/espressif/esp_lowputc.c b/arch/risc-v/src/common/espressif/esp_lowputc.c
index f0dfe79af78..c9d22a8e62d 100644
--- a/arch/risc-v/src/common/espressif/esp_lowputc.c
+++ b/arch/risc-v/src/common/espressif/esp_lowputc.c
@@ -51,6 +51,23 @@
 #include "hal/uart_hal.h"
 #include "periph_ctrl.h"
 #include "soc/gpio_sig_map.h"
+#ifdef CONFIG_ESPRESSIF_LP_UART
+#  include "lp_core_uart.h"
+#  include "soc/uart_pins.h"
+#  include "hal/rtc_io_hal.h"
+#  include "soc/uart_periph.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_LP_UART
+#  define ESP_LP_UART0_ID     LP_UART_NUM_0
+#  define RTCIO_RCC_ATOMIC()  PERIPH_RCC_ATOMIC()
+#else
+#  define ESP_LP_UART0_ID     UART_NUM_MAX
+#endif /* CONFIG_ESPRESSIF_LP_UART */
 
 /****************************************************************************
  * Private Types
@@ -110,6 +127,7 @@ struct esp_uart_s g_uart0_config =
   .rs485_dir_polarity = true,
 #endif
 #endif
+  .clk_src = UART_SCLK_DEFAULT,
   .hal = &g_uart0_hal,
   .lock = SP_UNLOCKED
 };
@@ -164,13 +182,117 @@ struct esp_uart_s g_uart1_config =
   .rs485_dir_polarity = true,
 #endif
 #endif
+  .clk_src = UART_SCLK_DEFAULT,
   .hal = &g_uart1_hal,
   .lock = SP_UNLOCKED
 };
 
 #endif /* CONFIG_ESPRESSIF_UART1 */
+
+#ifdef CONFIG_ESPRESSIF_LP_UART0
+
+static uart_hal_context_t g_lp_uart0_hal =
+{
+  .dev = (hal_uart_dev_t *)&LP_UART
+};
+
+struct esp_uart_s g_lp_uart0_config =
+{
+  .source = LP_UART_INTR_SOURCE,
+  .cpuint = -ENOMEM,
+  .int_pri = ESP_IRQ_PRIORITY_DEFAULT,
+  .id = ESP_LP_UART0_ID,
+  .irq = ESP_IRQ_LP_UART,
+  .baud = CONFIG_LPUART0_BAUD,
+  .stop_b2 = CONFIG_LPUART0_2STOP,
+  .bits = CONFIG_LPUART0_BITS,
+  .parity = CONFIG_LPUART0_PARITY,
+  .txpin = LP_UART_DEFAULT_TX_GPIO_NUM,
+  .txsig = LP_U0TXD_MUX_FUNC,
+  .rxpin = LP_UART_DEFAULT_RX_GPIO_NUM,
+  .rxsig = LP_U0RXD_MUX_FUNC,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  .rtspin = LP_UART_DEFAULT_RTS_GPIO_NUM,
+  .rtssig = LP_U0RTS_MUX_FUNC,
+#ifdef CONFIG_LPUART0_IFLOWCONTROL
+  .iflow  = true,    /* input flow control (RTS) enabled */
+#else
+  .iflow  = false,   /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  .ctspin = LP_UART_DEFAULT_CTS_GPIO_NUM,
+  .ctssig = LP_U0CTS_MUX_FUNC,
+#ifdef CONFIG_LPUART0_OFLOWCONTROL
+  .oflow  = true,    /* output flow control (CTS) enabled */
+#else
+  .oflow  = false,   /* output flow control (CTS) disabled */
+#endif
+#endif
+  .clk_src = LP_UART_SCLK_DEFAULT,
+  .hal = &g_lp_uart0_hal,
+  .lock = SP_UNLOCKED
+};
+
+#endif /* CONFIG_ESPRESSIF_LP_UART0 */
+
 #endif /* HAVE_UART_DEVICE */
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_LP_UART
+/****************************************************************************
+ * Name: esp_lowputc_lp_uart_config_io
+ *
+ * Description:
+ *   Configures LP UART pin.
+ *
+ * Parameters:
+ *   priv      - Pointer to the private driver struct.
+ *   pin       - Pin number to configure.
+ *   direction - Pin direction to configure.
+ *   idx       - Pin idx to configure.
+ *
+ * Return Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+static void esp_lowputc_lp_uart_config_io(const struct esp_uart_s *priv,
+                                          int8_t pin,
+                                          rtc_gpio_mode_t direction,
+                                          uint32_t idx)
+{
+  irqstate_t flags = spin_lock_irqsave(&priv->lock);
+  int lp_pin = rtc_io_num_map[pin];
+
+  DEBUGASSERT(lp_pin != -1);
+
+#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
+  RTCIO_RCC_ATOMIC()
+    {
+      rtcio_ll_enable_io_clock(true);
+    }
+
+#endif
+  rtcio_hal_function_select(lp_pin, RTCIO_LL_FUNC_RTC);
+  rtcio_hal_set_direction(pin, direction);
+
+  const uart_periph_sig_t *upin =
+    &uart_periph_signal[LP_UART_NUM_0].pins[idx];
+#if !SOC_LP_GPIO_MATRIX_SUPPORTED
+  rtcio_hal_iomux_func_sel(lp_pin, upin->iomux_func);
+#else
+  /* ToDo: Add LP UART for LP GPIO Matrix supported devices (e.g ESP32-P4) */
+#endif /* SOC_LP_GPIO_MATRIX_SUPPORTED */
+
+  spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+#endif /* CONFIG_ESPRESSIF_LP_UART */
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -206,7 +328,10 @@ void esp_lowputc_send_byte(const struct esp_uart_s *priv, char byte)
 
 void esp_lowputc_enable_sysclk(const struct esp_uart_s *priv)
 {
-  periph_module_enable(PERIPH_UART0_MODULE + priv->id);
+  if (priv->id < ESP_LP_UART0_ID)
+    {
+      periph_module_enable(PERIPH_UART0_MODULE + priv->id);
+    }
 }
 
 /****************************************************************************
@@ -284,26 +409,28 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv)
 {
   /* Configure the pins */
 
-  esp_configgpio(priv->rxpin, INPUT | PULLUP);
-  esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
+  if (priv->id < ESP_LP_UART0_ID)
+    {
+      esp_configgpio(priv->rxpin, INPUT | PULLUP);
+      esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
 
-  esp_configgpio(priv->txpin, OUTPUT);
-  esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
+      esp_configgpio(priv->txpin, OUTPUT);
+      esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
 
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
-  if (priv->iflow)
-    {
-      esp_configgpio(priv->rtspin, OUTPUT);
-      esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0);
-    }
+      if (priv->iflow)
+        {
+          esp_configgpio(priv->rtspin, OUTPUT);
+          esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0);
+        }
 
 #endif
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
-  if (priv->oflow)
-    {
-      esp_configgpio(priv->ctspin, INPUT | PULLUP);
-      esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
-    }
+      if (priv->oflow)
+        {
+          esp_configgpio(priv->ctspin, INPUT | PULLUP);
+          esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
+        }
 #endif
 
 #ifdef HAVE_RS485
@@ -314,6 +441,41 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv)
       esp_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
     }
 #endif
+    }
+#ifdef CONFIG_ESPRESSIF_LP_UART
+  else
+    {
+      esp_lowputc_lp_uart_config_io(priv,
+                                    priv->rxpin,
+                                    RTC_GPIO_MODE_INPUT_ONLY,
+                                    SOC_UART_RX_PIN_IDX);
+
+      esp_lowputc_lp_uart_config_io(priv,
+                                    priv->txpin,
+                                    RTC_GPIO_MODE_OUTPUT_ONLY,
+                                    SOC_UART_TX_PIN_IDX);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+      if (priv->iflow)
+        {
+          esp_lowputc_lp_uart_config_io(priv,
+                                        priv->rtspin,
+                                        RTC_GPIO_MODE_OUTPUT_ONLY,
+                                        SOC_UART_RTS_PIN_IDX);
+        }
+#endif
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+      if (priv->oflow)
+        {
+          esp_lowputc_lp_uart_config_io(priv,
+                                        priv->ctspin,
+                                        RTC_GPIO_MODE_INPUT_ONLY,
+                                        SOC_UART_CTS_PIN_IDX);
+        }
+#endif
+    }
+#endif /* CONFIG_ESPRESSIF_LP_UART */
 }
 
 /****************************************************************************
@@ -357,6 +519,8 @@ void riscv_lowputc(char ch)
   struct esp_uart_s *priv = &g_uart0_config;
 #  elif defined (CONFIG_UART1_SERIAL_CONSOLE)
   struct esp_uart_s *priv = &g_uart1_config;
+#  elif defined (CONFIG_LPUART0_SERIAL_CONSOLE)
+  struct esp_uart_s *priv = &g_lp_uart0_config;
 #  endif
 
   /* Wait until the TX FIFO has space to insert new char */
@@ -393,5 +557,10 @@ void esp_lowsetup(void)
   esp_lowputc_config_pins(&g_uart1_config);
 #endif
 
+#ifdef CONFIG_ESPRESSIF_LP_UART0
+  esp_lowputc_enable_sysclk(&g_lp_uart0_config);
+  esp_lowputc_config_pins(&g_lp_uart0_config);
+#endif
+
 #endif /* !CONFIG_SUPPRESS_UART_CONFIG */
 }
diff --git a/arch/risc-v/src/common/espressif/esp_lowputc.h b/arch/risc-v/src/common/espressif/esp_lowputc.h
index b3a217021ff..382b22152cb 100644
--- a/arch/risc-v/src/common/espressif/esp_lowputc.h
+++ b/arch/risc-v/src/common/espressif/esp_lowputc.h
@@ -80,12 +80,14 @@ struct esp_uart_s
   uint8_t  rs485_dir_gpio;     /* UART RS-485 DIR GPIO pin cfg */
   bool     rs485_dir_polarity; /* UART RS-485 DIR TXEN polarity */
 #endif
+  soc_module_clk_t    clk_src;   /* Clock source */
   uart_hal_context_t *hal;       /* HAL context */
   spinlock_t          lock;      /* Spinlock */
 };
 
 extern struct esp_uart_s g_uart0_config;
 extern struct esp_uart_s g_uart1_config;
+extern struct esp_uart_s g_lp_uart0_config;
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/risc-v/src/common/espressif/esp_serial.c b/arch/risc-v/src/common/espressif/esp_serial.c
index de3e32c8a1f..25b37c09601 100644
--- a/arch/risc-v/src/common/espressif/esp_serial.c
+++ b/arch/risc-v/src/common/espressif/esp_serial.c
@@ -57,11 +57,22 @@
 #include "esp_clk_tree.h"
 #include "hal/uart_hal.h"
 #include "soc/clk_tree_defs.h"
+#include "periph_ctrl.h"
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
+#ifdef CONFIG_ESPRESSIF_LP_UART
+#  define LP_UART_SRC_CLK_ATOMIC()    PERIPH_RCC_ATOMIC()
+#  define LP_UART_BUS_CLK_ATOMIC()    PERIPH_RCC_ATOMIC()
+#  define LP_UART_RXBUFSIZE           SOC_LP_UART_FIFO_LEN
+#  define LP_UART_TXBUFSIZE           SOC_LP_UART_FIFO_LEN
+#  define ESP_LP_UART0_ID             LP_UART_NUM_0
+#else
+#  define ESP_LP_UART0_ID             UART_NUM_MAX
+#endif
+
 /* The console is enabled and it's not the syslog device, so it should be a
  * serial device.
  */
@@ -89,15 +100,22 @@
 #    define CONSOLE_DEV         g_uart1_dev  /* UART1 is console */
 #    define TTYS0_DEV           g_uart1_dev  /* UART1 is ttyS0 */
 #    define UART1_ASSIGNED      1
+#  elif defined(CONFIG_LPUART0_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_lp_uart0_dev  /* LPUART0 is console */
+#    define TTYS0_DEV           g_lp_uart0_dev  /* LPUART0 is ttyS0 */
+#    define LPUART0_ASSIGNED    1
 #  endif /* CONFIG_UART0_SERIAL_CONSOLE */
 #else /* No UART console */
 #  undef  CONSOLE_DEV
 #  if defined(CONFIG_ESPRESSIF_UART0)
-#    define TTYS0_DEV           g_uart0_dev  /* UART0 is ttyS0 */
+#    define TTYS0_DEV           g_uart0_dev   /* UART0 is ttyS0 */
 #    define UART0_ASSIGNED      1
 #  elif defined(CONFIG_ESPRESSIF_UART1)
-#    define TTYS0_DEV           g_uart1_dev  /* UART1 is ttyS0 */
+#    define TTYS0_DEV           g_uart1_dev   /* UART1 is ttyS0 */
 #    define UART1_ASSIGNED      1
+#  elif defined(CONFIG_ESPRESSIF_LP_UART0)
+#    define TTYS0_DEV           g_lp_uart0_dev /* LPUART0 is ttyS0 */
+#    define LPUART0_ASSIGNED    1
 #  endif
 #endif /* CONSOLE_UART */
 
@@ -114,6 +132,22 @@
 #elif defined(CONFIG_ESPRESSIF_UART1) && !defined(UART1_ASSIGNED)
 #  define TTYS1_DEV           g_uart1_dev  /* UART1 is ttyS1 */
 #  define UART1_ASSIGNED      1
+#elif defined(CONFIG_ESPRESSIF_LP_UART0) && !defined(LPUART0_ASSIGNED)
+#  define TTYS1_DEV           g_lp_uart0_dev  /* LPUART0 is ttyS1 */
+#  define LPUART0_ASSIGNED    1
+#endif
+
+/* Pick ttyS2 */
+
+#if defined(CONFIG_ESPRESSIF_UART0) && !defined(UART0_ASSIGNED)
+#  define TTYS2_DEV           g_uart0_dev  /* UART0 is ttyS2 */
+#  define UART0_ASSIGNED      1
+#elif defined(CONFIG_ESPRESSIF_UART1) && !defined(UART1_ASSIGNED)
+#  define TTYS2_DEV           g_uart1_dev  /* UART1 is ttyS2 */
+#  define UART1_ASSIGNED      1
+#elif defined(CONFIG_ESPRESSIF_LP_UART0) && !defined(LPUART0_ASSIGNED)
+#  define TTYS2_DEV           g_lp_uart0_dev  /* LPUART0 is ttyS2 */
+#  define LPUART0_ASSIGNED    1
 #endif
 
 #ifdef HAVE_UART_DEVICE
@@ -237,6 +271,39 @@ static uart_dev_t g_uart1_dev =
 
 #endif
 
+/* LP UART */
+
+#ifdef CONFIG_ESPRESSIF_LP_UART0
+
+static char g_lp_uart0_rxbuffer[LP_UART_RXBUFSIZE];
+static char g_lp_uart0_txbuffer[LP_UART_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_lp_uart0_dev =
+{
+#ifdef CONFIG_LPUART0_SERIAL_CONSOLE
+  .isconsole = true,
+#else
+  .isconsole = false,
+#endif
+  .xmit =
+    {
+      .size   = LP_UART_TXBUFSIZE,
+      .buffer = g_lp_uart0_txbuffer,
+    },
+  .recv =
+    {
+      .size   = LP_UART_RXBUFSIZE,
+      .buffer = g_lp_uart0_rxbuffer,
+    },
+
+  .ops = &g_uart_ops,
+  .priv = &g_lp_uart0_config
+};
+
+#endif
+
 #endif /* CONFIG_ESPRESSIF_UART */
 
 /****************************************************************************
@@ -392,16 +459,46 @@ static int esp_setup(uart_dev_t *dev)
 
   esp_lowputc_enable_sysclk(priv);
 
-  esp_clk_tree_src_get_freq_hz((soc_module_clk_t)UART_SCLK_DEFAULT,
+  esp_clk_tree_src_get_freq_hz((soc_module_clk_t)priv->clk_src,
                            ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
                            &sclk_freq);
 
   /* Initialize UART module */
+#ifdef CONFIG_ESPRESSIF_LP_UART
+  if (priv->id >= LP_UART_NUM_0)
+    {
+      /* Enable LP UART bus clock */
+
+      LP_UART_SRC_CLK_ATOMIC()
+        {
+          lp_uart_ll_enable_bus_clock(0, true);
+          lp_uart_ll_set_source_clk(priv->hal->dev, sclk_freq);
+          lp_uart_ll_sclk_enable(0);
+        }
+    }
+#endif
 
   uart_hal_init(priv->hal, priv->id);
   uart_hal_set_mode(priv->hal, UART_MODE_UART);
-  uart_hal_set_sclk(priv->hal, UART_SCLK_DEFAULT);
-  uart_hal_set_baudrate(priv->hal, priv->baud, sclk_freq);
+  if (priv->id < ESP_LP_UART0_ID)
+    {
+      uart_hal_set_sclk(priv->hal, UART_SCLK_DEFAULT);
+      uart_hal_set_baudrate(priv->hal, priv->baud, sclk_freq);
+    }
+#ifdef CONFIG_ESPRESSIF_LP_UART
+  else
+    {
+      /* Override protocol parameters from the configuration */
+
+      if (!lp_uart_ll_set_baudrate(priv->hal->dev, priv->baud, sclk_freq))
+        {
+          /* Unachievable baud rate */
+
+          return ESP_FAIL;
+        }
+    }
+#endif
+
   uart_hal_set_parity(priv->hal, priv->parity);
   set_data_length(priv);
   set_stop_length(priv);
@@ -1136,12 +1233,20 @@ void riscv_earlyserialinit(void)
   esp_lowputc_disable_all_uart_int(TTYS1_DEV.priv, NULL);
 #endif
 
+#ifdef TTYS2_DEV
+  esp_lowputc_disable_all_uart_int(TTYS2_DEV.priv, NULL);
+#endif
+
   /* Configure console in early step.
    * Setup for other serials will be performed when the serial driver is
    * open.
    */
 
-#ifdef CONSOLE_UART
+#if defined(CONSOLE_UART) && !defined(CONFIG_LPUART0_SERIAL_CONSOLE)
+  /* To use LPUART as console properly, device
+   * needs finish booting process completely
+   */
+
   esp_setup(&CONSOLE_DEV);
 #endif
 }
@@ -1166,6 +1271,13 @@ void riscv_earlyserialinit(void)
 void riscv_serialinit(void)
 {
 #ifdef HAVE_SERIAL_CONSOLE
+#  ifdef CONFIG_LPUART0_SERIAL_CONSOLE
+  /* To use LPUART as console properly, device
+   * needs finish booting process completely
+   */
+
+  esp_setup(&CONSOLE_DEV);
+#  endif
   uart_register("/dev/console", &CONSOLE_DEV);
 #endif
 
@@ -1177,6 +1289,10 @@ void riscv_serialinit(void)
   uart_register("/dev/ttyS1", &TTYS1_DEV);
 #endif
 
+#ifdef TTYS2_DEV
+  uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
+
 #ifdef CONFIG_ESPRESSIF_USBSERIAL
   uart_register("/dev/ttyACM0", &TTYACM0_DEV);
 #endif
diff --git a/arch/risc-v/src/esp32c6/hal_esp32c6.mk b/arch/risc-v/src/esp32c6/hal_esp32c6.mk
index 941d8036705..920729f18e1 100644
--- a/arch/risc-v/src/esp32c6/hal_esp32c6.mk
+++ b/arch/risc-v/src/esp32c6/hal_esp32c6.mk
@@ -75,6 +75,9 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)include
 
 ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
   INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
@@ -176,6 +179,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rtc_io_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal_iram.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c
@@ -203,7 +207,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
 
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)gpio.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c
@@ -227,7 +233,6 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
   CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c
   CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
   CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
-  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
   CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
   CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
   CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c