Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-07 01:05:54 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

arch: arm: imx: fix nxstyle errors

Browse Source 
Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2021-03-24 09:21:23 +01:00
committed by Xiang Xiao
parent 188a76f1f9
commit 01cde40bdc
117 changed files with 2726 additions and 1861 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/imx1/chip.h
+8 -8
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_CHIP_H
#define __ARCH_ARM_IMX_CHIP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include "imx_memorymap.h"
#include "imx_system.h"
@@ -39,12 +39,12 @@
#include "imx_eim.h"
#include "imx_aitc.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_CHIP_H */
arch/arm/src/imx1/imx_aitc.h
+11 -12
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_aitc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_AITC_H
#define __ARCH_ARM_IMX_AITC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* AITC Register Offsets ************************************************************/
/* AITC Register Offsets ****************************************************/
#define AITC_INTCNTL_OFFSET 0x0000 /* Interrupt Control Register */
#define AITC_NIMASK_OFFSET 0x0004 /* Normal Interrupt Mask Register */
@@ -59,7 +59,7 @@
#define AITC_FIPNDH_OFFSET 0x0060
#define AITC_FIPNDL_OFFSET 0x0064
/* AITC Register Addresses **********************************************************/
/* AITC Register Addresses **************************************************/
#define IMX_AITC_INTCNTL (IMX_AITC_VBASE + AITC_INTCNTL_OFFSET)
#define IMX_AITC_NIMASK (IMX_AITC_VBASE + AITC_NIMASK_OFFSET)
@@ -89,16 +89,15 @@
#define IMX_AITC_FIPNDH (IMX_AITC_VBASE + AITC_FIPNDH_OFFSET)
#define IMX_AITC_FIPNDL (IMX_AITC_VBASE + AITC_FIPNDL_OFFSET)
/* AITC Register Bit Definitions ****************************************************/
/* AITC Register Bit Definitions ********************************************/
#define AITC_NIVECSR_NIPRILVL_SHIFT 0 /* Bits 15–0: Priority of highest priority interrupt */
#define AITC_NIVECSR_NIPRILVL_MASK (0x0000ffff << AITC_NIVECSR_NIPRILVL_SHIFT);
#define AITC_NIVECSR_NIVECTOR_SHIFT 16 /* Bits 31–16: Vector index of highest priority interrupt */
#define AITC_NIVECSR_NIVECTOR_MASK (0x0000ffff << AITC_NIVECSR_NIVECTOR_SHIFT);
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_AITC_H */
arch/arm/src/imx1/imx_allocateheap.c
+2 -2
View File
@@ -75,8 +75,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
/* If a bootloader that copies us to DRAM, but not to the beginning of DRAM,
* then recover that memory by adding another memory region.
/* If a bootloader that copies us to DRAM, but not to the beginning of
* DRAM, then recover that memory by adding another memory region.
*/
#if !defined(CONFIG_BOOT_RUNFROMFLASH) && !defined(CONFIG_BOOT_COPYTORAM)
arch/arm/src/imx1/imx_boot.c
+45 -38
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,11 +16,11 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
@@ -31,13 +31,13 @@
#include <nuttx/board.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Private Types
************************************************************************************/
****************************************************************************/
struct section_mapping_s
{
@@ -47,16 +47,16 @@ struct section_mapping_s
uint32_t nsections; /* Number of mappings in the region */
};
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
extern uint32_t _vector_start; /* Beginning of vector block */
extern uint32_t _vector_end; /* End+1 of vector block */
/************************************************************************************
/****************************************************************************
* Private Data
************************************************************************************/
****************************************************************************/
/* Mapping of the external memory regions will probably have to be made board
* specific.
@@ -82,26 +82,28 @@ static const struct section_mapping_s section_mapping[] =
#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/* All i.MX architectures must provide the following entry point. This entry point
* is called early in the initialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
/* All i.MX architectures must provide the following entry point.
* This entry point is called early in the initialization -- after all memory
* has been configured and mapped but before any devices have been
* initialized.
*/
void imx_board_initialize(void);
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: up_setlevel1entry
************************************************************************************/
****************************************************************************/
static inline void up_setlevel1entry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags)
static inline void up_setlevel1entry(uint32_t paddr,
uint32_t vaddr, uint32_t mmuflags)
{
uint32_t *pgtable = (uint32_t *)PGTABLE_BASE_VADDR;
uint32_t index = vaddr >> 20;
@@ -111,13 +113,14 @@ static inline void up_setlevel1entry(uint32_t paddr, uint32_t vaddr, uint32_t mm
pgtable[index] = (paddr | mmuflags);
}
/************************************************************************************
/****************************************************************************
* Name: up_setupmappings
************************************************************************************/
****************************************************************************/
static void up_setupmappings(void)
{
int i, j;
int i;
int j;
for (i = 0; i < NMAPPINGS; i++)
{
@@ -134,30 +137,34 @@ static void up_setupmappings(void)
}
}
/************************************************************************************
/****************************************************************************
* Name: up_copyvectorblock
************************************************************************************/
****************************************************************************/
static void up_copyvectorblock(void)
{
/* There are three operational memory configurations:
*
* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case:
* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y).
* In this case:
*
* - Our vectors must be located at the beginning of FLASH and will
* also be mapped to address zero (because of the i.MX's "double map image."
* also be mapped to address zero (because of the i.MX's
* "double map image."
* - There is nothing to be done here in this case.
*
* 2. We boot in FLASH but copy ourselves to DRAM from better performance.
* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y). In this case:
* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y).
* In this case:
*
* - Our code image is in FLASH and we boot to FLASH initially, then copy
* ourself to DRAM, and
* - Our code image is in FLASH and we boot to FLASH initially,
* then copy ourself to DRAM, and
* - DRAM will be mapped to address zero.
* - There is nothing to be done here in this case.
*
* 3. There is bootloader that copies us to DRAM, but probably not to the beginning
* of DRAM (say to 0x0900:0000) (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n).
* 3. There is bootloader that copies us to DRAM, but probably not to the
* beginning of DRAM (say to 0x0900:0000)
* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n).
* In this case:
*
* - DRAM will be mapped to address zero.
@@ -176,14 +183,14 @@ static void up_copyvectorblock(void)
#endif
}
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
void arm_boot(void)
{
/* __start provided the basic MMU mappings for SDRAM. Now provide mappings for all
* IO regions (Including the vector region).
/* __start provided the basic MMU mappings for SDRAM. Now provide
* mappings for all IO regions (Including the vector region).
*/
up_setupmappings();
arch/arm/src/imx1/imx_cspi.h
+39 -36
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_cspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_CSPI_H
#define __ARCH_ARM_IMX_CSPI_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
@@ -31,11 +31,11 @@
# include <nuttx/spi/spi.h>
#endif
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* CSPI Register Offsets ************************************************************/
/* CSPI Register Offsets ****************************************************/
#define CSPI_RXD_OFFSET 0x0000 /* Receive Data Register */
#define CSPI_TXD_OFFSET 0x0004 /* Transmit Data Register */
@@ -46,7 +46,7 @@
#define CSPI_DMA_OFFSET 0x0018 /* DMA Control Register */
#define CSPI_RESET_OFFSET 0x001c /* Soft Reset Register */
/* CSPI Register Addresses **********************************************************/
/* CSPI Register Addresses **************************************************/
/* CSPI1 */
@@ -70,7 +70,7 @@
#define IMX_CSPI2_SPIDMA (IMX_CSPI2_VBASE + CSPI_DMA_OFFSET)
#define IMX_CSPI2_SPIRESET (IMX_CSPI2_VBASE + CSPI_RESET_OFFSET)
/* CSPI Register Bit Definitions ****************************************************/
/* CSPI Register Bit Definitions ********************************************/
/* CSPI Control Register */
@@ -141,13 +141,13 @@
#define CSPI_RESET_START (1 << 0) /* Bit 0: Execute soft reset */
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@@ -158,9 +158,9 @@ extern "C"
#define EXTERN extern
#endif /* __cplusplus */
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
struct spi_dev_s; /* Forward reference */
@@ -173,10 +173,10 @@ struct spi_dev_s; /* Forward reference */
* prior to calling this function. Specifically: GPIOs should have
* been configured for output, and all chip selects disabled.
*
* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However,
* If multiple devices on on the bus, then multiple chip selects will be
* required. Therefore, all GPIO chip management is deferred to board-
* specific logic.
* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select.
* However, If multiple devices on on the bus, then multiple chip selects
* will be required. Therefore, all GPIO chip management is deferred to
* board- specific logic.
*
* Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
@@ -189,23 +189,26 @@ struct spi_dev_s; /* Forward reference */
FAR struct spi_dev_s *imx_spibus_initialize(int port);
/****************************************************************************
* The external functions, imx_spiselect, imx_spistatus, and imx_cmddaa must be
* provided by board-specific logic. These are implementations of the select and
* status methods of the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including imx_spibus_initialize()) are
* provided by common logic. To use this common SPI logic on your board:
* The external functions, imx_spiselect, imx_spistatus, and imx_cmddaa must
* be provided by board-specific logic. These are implementations of the
* select and status methods of the SPI interface defined by struct spi_ops_s
* (see include/nuttx/spi/spi.h).
* All other methods (including imx_spibus_initialize()) are provided by
* common logic. To use this common SPI logic on your board:
*
* 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific
* logic. This function will perform chip selection and status operations using
* GPIOs in the way your board is configured.
* 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the
* imx_spicmddata() function in your board-specific logic. This function will
* perform cmd/data selection operations using GPIOs in the way your board is
* configured.
* 3. Add a call to imx_spibus_initialize() in your low level initialization logic
* 4. The handle returned by imx_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(),
* for example, will bind the SPI driver to the SPI MMC/SD driver).
* 1. Provide imx_spiselect() and imx_spistatus() functions in your
* board-specific logic. This function will perform chip selection and
* status operations using GPIOs in the way your board is configured.
* 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide
* the imx_spicmddata() function in your board-specific logic. This
* function will perform cmd/data selection operations using GPIOs in
* the way your board is configured.
* 3. Add a call to imx_spibus_initialize() in your low level
* initialization logic
* 4. The handle returned by imx_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
arch/arm/src/imx1/imx_decodeirq.c
+17 -16
View File
@@ -1,4 +1,4 @@
/********************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_decodeirq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,11 +16,11 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************/
****************************************************************************/
/********************************************************************************
/****************************************************************************
* Included Files
********************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -36,25 +36,25 @@
#include "group/group.h"
/********************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************/
****************************************************************************/
/********************************************************************************
/****************************************************************************
* Public Data
********************************************************************************/
****************************************************************************/
/********************************************************************************
/****************************************************************************
* Private Data
********************************************************************************/
****************************************************************************/
/********************************************************************************
/****************************************************************************
* Private Functions
********************************************************************************/
****************************************************************************/
/********************************************************************************
/****************************************************************************
* Public Functions
********************************************************************************/
****************************************************************************/
uint32_t *arm_decodeirq(uint32_t *regs)
{
@@ -90,8 +90,9 @@ uint32_t *arm_decodeirq(uint32_t *regs)
irq = regval >> AITC_NIVECSR_NIVECTOR_SHIFT;
/* If irq < 64, then this is the IRQ. If there is no pending interrupt,
* then irq will be >= 64 (it will be 0xffff for illegal source).
/* If irq < 64, then this is the IRQ.
* If there is no pending interrupt, then irq will be >= 64
* (it will be 0xffff for illegal source).
*/
if (irq < NR_IRQS)
arch/arm/src/imx1/imx_dma.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_DMA_H
#define __ARCH_ARM_IMX_DMA_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* DMA Register Offsets *************************************************************/
/* DMA Register Offsets *****************************************************/
#define DMA_SYS_OFFSET 0x0000
#define DMA_M2D_OFFSET 0x0040
@@ -78,7 +78,7 @@
#define DMA_TDIPR_OFFSET 0x000c
#define DMA_TFIFOB_OFFSET 0x0010
/* DMA Register Addresses ***********************************************************/
/* DMA Register Addresses ***************************************************/
#define IMX_DMA_SYS_BASE (IMX_DMA_VBASE + DMA_SYS_OFFSET)
#define IMX_DMA_M2D_BASE (IMX_DMA_VBASE + DMA_M2D_OFFSET)
@@ -226,10 +226,10 @@
#define IMX_DMA_TDIPR (DMA_TST_BASE + DMA_TDIPR_OFFSET)
#define IMX_DMA_TFIFOB (DMA_TST_BASE + DMA_TFIFOB_OFFSET)
/* DMA Register Bit Definitions *****************************************************/
/* DMA Register Bit Definitions *********************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_DMA_H */
arch/arm/src/imx1/imx_eim.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_eim.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_WIEM_H
#define __ARCH_ARM_IMX_WIEM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* EIM Register Offsets ************************************************************/
/* EIM Register Offsets *****************************************************/
#define EIM_CS0H_OFFSET 0x00
#define EIM_CS0L_OFFSET 0x04
@@ -45,7 +45,7 @@
#define EIM_CS5L_OFFSET 0x2c
#define EIM_WEIM_OFFSET 0x30
/* EIM Register Addresses ***********************************************************/
/* EIM Register Addresses ***************************************************/
#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET)
#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET)
@@ -61,10 +61,10 @@
#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET)
#define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET)
/* EIM Register Bit Definitions *****************************************************/
/* EIM Register Bit Definitions *********************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_EIM_H */
arch/arm/src/imx1/imx_gpio.h
+13 -13
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX1_IMX_GPIO_H
#define __ARCH_ARM_SRC_IMX1_IMX_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include "arm_arch.h" /* getreg32(), putreg32() */
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO Register Offsets ************************************************************/
/* GPIO Register Offsets ****************************************************/
#define GPIO_DDIR_OFFSET 0x0000 /* Data Direction Register */
#define GPIO_OCR1_OFFSET 0x0004 /* Output Configuration Register 1 */
@@ -65,7 +65,7 @@
#define GPIOD 3 /* Port D index */
#define GPIO_PT_OFFSET(n) (GPIO_PTA_OFFSET + (n)*0x0100)
/* GPIO Register Addresses **********************************************************/
/* GPIO Register Addresses **************************************************/
#define IMX_PTA_VBASE (IMX_GPIO_VBASE + GPIO_PTA_OFFSET)
#define IMX_PTB_VBASE (IMX_GPIO_VBASE + GPIO_PTB_OFFSET)
@@ -163,18 +163,18 @@
#define IMX_GPIO_SWR(n) (IMX_PT_VBASE(n) + GPIO_SWR_OFFSET)
#define IMX_GPIO_PUEN(n) (IMX_PT_VBASE(n) + GPIO_PUEN_OFFSET)
/* GPIO Register Bit Definitions ****************************************************/
/* GPIO Register Bit Definitions ********************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_IMX1_IMX_GPIO_H */
#ifndef __ASSEMBLY__
/* Handler circular include... This file includes arm_arch.h, but this file is
* included by arm_arch.h (via chip.h) BEFORE getreg32 is defined.
/* Handler circular include... This file includes arm_arch.h, but this file
* is included by arm_arch.h (via chip.h) BEFORE getreg32 is defined.
*/
#if !defined(__ARCH_ARM_IMX_GPIOHELPERS_H) && defined(getreg32)
arch/arm/src/imx1/imx_i2c.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_I2C_H
#define __ARCH_ARM_IMX_I2C_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* I2C Register Offsets *************************************************************/
/* I2C Register Offsets *****************************************************/
#define I2C_IADR_OFFSET 0x0000
#define I2C_IFDR_OFFSET 0x0004
@@ -37,7 +37,7 @@
#define I2C_I2SR_OFFSET 0x000c
#define I2C_I2DR_OFFSET 0x0010
/* I2C Register Addresses ***********************************************************/
/* I2C Register Addresses ***************************************************/
#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET)
#define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET)
@@ -45,10 +45,10 @@
#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET)
#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET)
/* I2C Register Bit Definitions *****************************************************/
/* I2C Register Bit Definitions *********************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_I2C_H */
arch/arm/src/imx1/imx_memorymap.h
+39 -30
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_MEMORYMAP_H
#define __ARCH_ARM_IMX_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include "arm.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Physical Memory Map **************************************************************/
/* Physical Memory Map ******************************************************/
/* -0x000fffff
* Double Map Image 1Mb
* -0x001fffff
* Bootstrap ROM 1Mb
*/
/* -0x000fffff Double Map Image 1Mb */
/* -0x001fffff Bootstrap ROM 1Mb */
#define IMX_PERIPHERALS_PSECTION 0x00200000 /* -0x002fffff Peripherals 1Mb */
#define IMX_ESRAM_PSECTION 0x00300000 /* -0x003fffff Embedded SRAM 128Kb */
#define IMX_SDRAM0_PSECTION 0x08000000 /* -0x0bffffff SDRAM0 (CSD0) 64Mb */
@@ -46,11 +50,11 @@
#define IMX_CS4_PSECTION 0x15000000 /* -0x15ffffff CS4 16Mb */
#define IMX_CS5_PSECTION 0x16000000 /* -0x16ffffff CS5 16Mb */
/* Sizes of Address Sections ********************************************************/
/* Sizes of Address Sections ************************************************/
/* Mapped sections */
#define IMX_PERIPHERALS_NSECTIONS 1 /* 1Mb 1 section */
#define IMX_SDRAM0_NSECTIONS 16 /* 16Mb Based on CONFIG_RAM_SIZE */
#define IMX_SDRAM0_NSECTIONS 16 /* 16Mb Based on CONFIG_RAM_SIZE */
#define IMX_SDRAM1_NSECTIONS 0 /* 64Mb (Not mapped) */
#define IMX_FLASH_NSECTIONS 32 /* 64Mb Based on CONFIG_FLASH_SIZE */
#define IMX_CS1_NSECTIONS 16 /* 16Mb */
@@ -59,14 +63,16 @@
#define IMX_CS4_NSECTIONS 16 /* 16Mb */
#define IMX_CS5_NSECTIONS 16 /* 16Mb */
/* Virtual Memory Map ***************************************************************/
/* Virtual Memory Map *******************************************************/
/* There are three operational memory configurations:
*
* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case:
* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y).
* In this case:
*
* - Our vectors must be located at the beginning of FLASH and will
* also be mapped to address zero (because of the i.MX's "double map image."
* also be mapped to address zero (because of the i.MX's "double map
* image."
* - All vector addresses are FLASH absolute addresses,
* - DRAM cannot reside at address zero,
* - Vectors at address zero (CR_V is not set),
@@ -80,30 +86,33 @@
* ourself to DRAM,
* - DRAM will be mapped to address zero,
* - The RESET vector is a FLASH absolute address,
* - All other vectors are absulte and reference functions in the final mapped SDRAM address
* - All other vectors are absulte and reference functions in the final
* mapped SDRAM address
* - Vectors at address zero (CR_V is not set), and
* - The boot logic must configure SDRAM.
*
* 3. There is bootloader that copies us to DRAM, but probably not to the beginning
* of DRAM (say to 0x0900:0000) (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n).
* 3. There is bootloader that copies us to DRAM, but probably not to the
* beginning of DRAM (say to 0x0900:0000)
* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n).
* In this case:
*
* - DRAM will be mapped to address zero,
* - Interrupt vectors will be copied to address zero,
* - Memory between the end of the vector area (say 0x0800:0400) and the beginning
* of the page table (0x0900:0000) will be given to the memory manager as a second
* memory region,
* - All vectors are absulte and reference functions in the final mapped SDRAM address
* - Memory between the end of the vector area (say 0x0800:0400) and the
* beginning of the page table (0x0900:0000) will be given to the memory
* manager as a second memory region,
* - All vectors are absulte and reference functions in the final mapped
* SDRAM address
* - Vectors at address zero (CR_V is not set), and
* - We must assume that the bootloader has configured SDRAM.
*/
#ifdef CONFIG_BOOT_RUNFROMFLASH
/* Use the identity mapping */
/* Use the identity mapping */
# define IMX_SDRAM_VSECTION 0x08000000 /* -(+CONFIG_RAM_SIZE) */
#else
/* Map SDRAM to address zero */
/* Map SDRAM to address zero */
# define IMX_SDRAM_VSECTION 0x00000000 /* -(+CONFIG_RAM_SIZE) */
#endif
@@ -122,7 +131,7 @@
#define VECTOR_BASE 0x00000000
/* Peripheral Register Offsets ******************************************************/
/* Peripheral Register Offsets **********************************************/
#define IMX_AIPI1_OFFSET 0x00000000 /* -0x00000fff AIPI1 4Kb */
#define IMX_WDOG_OFFSET 0x00001000 /* -0x00001fff WatchDog 4Kb */
@@ -160,7 +169,7 @@
#define IMX_CSI_OFFSET 0x00024000 /* -0x00024fff CSI 4Kb */
/* -0x000fffff Reserved 876Kb */
/* Peripheral Register Offsets ******************************************************/
/* Peripheral Register Offsets **********************************************/
#define IMX_AIPI1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AIPI1_OFFSET)
#define IMX_WDOG_VBASE (IMX_PERIPHERALS_VSECTION + IMX_WDOG_OFFSET)
@@ -195,10 +204,10 @@
#define IMX_AITC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AITC_OFFSET)
#define IMX_CSI_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CSI_OFFSET)
/* Memory Mapping Info **************************************************************/
/* Memory Mapping Info ******************************************************/
/* The NuttX entry point starts at an offset from the virtual beginning of DRAM.
* This offset reserves space for the MMU page cache.
/* The NuttX entry point starts at an offset from the virtual beginning of
* DRAM. This offset reserves space for the MMU page cache.
*/
#define NUTTX_START_VADDR ((CONFIG_RAM_NUTTXENTRY & 0xfff00000) | PGTABLE_SIZE)
@@ -237,8 +246,8 @@
#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_VEND-PGTABLE_COARSE_VBASE)
#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_MEMORYMAP_H */
arch/arm/src/imx1/imx_rtc.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_RTC_H
#define __ARCH_ARM_IMX_RTC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* RTC Register Offsets *************************************************************/
/* RTC Register Offsets *****************************************************/
#define RTC_HOURMIN_OFFSET 0x0000
#define RTC_SECOND_OFFSET 0x0004
@@ -45,7 +45,7 @@
#define RTC_TEST2_OFFSET 0x002c
#define RTC_TEST3_OFFSET 0x0030
/* RTC Register Addresses ***********************************************************/
/* RTC Register Addresses ***************************************************/
#define IMX_RTC_HOURMIN (IMX_RTC_VBASE + RTC_HOURMIN_OFFSET)
#define IMX_RTC_SECOND (IMX_RTC_VBASE + RTC_SECOND_OFFSET)
@@ -61,10 +61,10 @@
#define IMX_RTC_TEST2 (IMX_RTC_VBASE + RTC_TEST2_OFFSET)
#define IMX_RTC_TEST3 (IMX_RTC_VBASE + RTC_TEST3_OFFSET)
/* RTC Register Bit Definitions *****************************************************/
/* RTC Register Bit Definitions *********************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_RTC_H */
arch/arm/src/imx1/imx_spi.c
+6 -2
View File
@@ -393,7 +393,9 @@ static int spi_performtx(struct imx_spidev_s *priv)
}
else
{
/* Yes.. The transfer is complete, disable Tx FIFO empty interrupt */
/* Yes..
* The transfer is complete, disable Tx FIFO empty interrupt
*/
regval = spi_getreg(priv, CSPI_INTCS_OFFSET);
regval &= ~CSPI_INTCS_TEEN;
@@ -1118,7 +1120,9 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port)
#endif
nxsem_init(&priv->exclsem, 0, 1);
/* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */
/* Initialize control register:
* min frequency, ignore ready, master mode, mode=0, 8-bit
*/
spi_putreg(priv, CSPI_CTRL_OFFSET,
CSPI_CTRL_DIV512 | /* Lowest frequency */
arch/arm/src/imx1/imx_system.h
+23 -24
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_system.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,26 +16,26 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_SYSTEM_H
#define __ARCH_ARM_IMX_SYSTEM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* AIPI Register Offsets ************************************************************/
/* AIPI Register Offsets ****************************************************/
#define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */
#define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */
#define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */
/* AIPI Register Addresses **********************************************************/
/* AIPI Register Addresses **************************************************/
#define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET)
#define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET)
@@ -45,9 +45,9 @@
#define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET)
#define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET)
/* AIPI Register Bit Definitions ****************************************************/
/* AIPI Register Bit Definitions ********************************************/
/* PLL Register Offsets *************************************************************/
/* PLL Register Offsets *****************************************************/
#define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */
#define PLL_MPCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */
@@ -56,7 +56,7 @@
#define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */
#define PLL_PCDR_OFFSET 0x0020 /* Peripheral Clock Divider Register */
/* PLL Register Addresses ***********************************************************/
/* PLL Register Addresses ***************************************************/
#define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET)
#define IMX_PLL_MPCTL0 (IMX_PLL_VBASE + PLL_MPCTL0_OFFSET)
@@ -65,10 +65,10 @@
#define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET)
#define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET)
/* PLL Register Bit Definitions *****************************************************/
/* PLL Register Bit Definitions *********************************************/
#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */
#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */
#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */
#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */
#define PLL_CSCR_BCLKDIV_SHIFT 10 /* Bits 13–10: BClock Divider */
#define PLL_CSCR_BCLKDIV_MASK (15 << PLL_CSCR_BCLK_DIV_SHIFT)
#define PLL_CSCR_PRESC (1 << 15) /* Bit 15: MPU PLL clock prescaler */
@@ -123,24 +123,23 @@
#define PLL_PCDR_PCLKDIV3_SHIFT 16 /* Bits 22–16: Peripheral Clock Divider 3 */
#define PLL_PCDR_PCLKDIV3_MASK (0x7f << PLL_PCDR_PCLKDIV3_SHIFT)
/* PLL Helper Macros ****************************************************************/
/* PLL Helper Macros ********************************************************/
/* SC Register Offsets **************************************************************/
/* SC Register Offsets ******************************************************/
#define SC_RSR_OFFSET 0x0000 /* Reset Source Register */
#define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */
#define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */
#define SC_GPCR_OFFSET 0x000c /* Global Peripheral Control Register */
/* SC Register Addresses ************************************************************/
/* SC Register Addresses ****************************************************/
#define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET)
#define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET)
#define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET)
#define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET)
/* SC Register Bit Definitions ******************************************************/
/* SC Register Bit Definitions **********************************************/
#define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */
#define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */
@@ -153,20 +152,20 @@
#define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin
* (AOUT of Port D[9]) */
/* SDRAMC Register Offsets **********************************************************/
/* SDRAMC Register Offsets **************************************************/
#define SDRAMC_SDCTL0_OFFSET 0x0000
#define SDRAMC_SDCTL1_OFFSET 0x0004
/* SDRAMC Register Addresses ********************************************************/
/* SDRAMC Register Addresses ************************************************/
#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET)
#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET))
/* SDRAMC Register Bit Definitions **************************************************/
/* SDRAMC Register Bit Definitions ******************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_SYSTEM_H */
arch/arm/src/imx1/imx_timer.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_timer.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_TIMER_H
#define __ARCH_ARM_IMX_TIMER_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Timer Register Offsets ***********************************************************/
/* Timer Register Offsets ***************************************************/
#define TIMER_TCTL_OFFSET 0x0000 /* Timer control register */
#define TIMER_TPRER_OFFSET 0x0004 /* Timer prescaler register */
@@ -38,7 +38,7 @@
#define TIMER_TCN_OFFSET 0x0010 /* Timer counter register */
#define TIMER_TSTAT_OFFSET 0x0014 /* Timer status register */
/* Timer Register Addresses *********************************************************/
/* Timer Register Addresses *************************************************/
#define IMX_TIMER1_TCTL (IMX_TIMER1_VBASE + TIMER_TCTL_OFFSET)
#define IMX_TIMER1_TPRER (IMX_TIMER1_VBASE + TIMER_TPRER_OFFSET)
@@ -54,7 +54,7 @@
#define IMX_TIMER2_TCN (IMX_TIMER2_VBASE + TIMER_TCN_OFFSET)
#define IMX_TIMER2_TSTAT (IMX_TIMER2_VBASE + TIMER_TSTAT_OFFSET)
/* Timer Register Bit Definitions ***************************************************/
/* Timer Register Bit Definitions *******************************************/
/* Timer Control Register */
@@ -82,8 +82,8 @@
#define TIMER_TSTAT_COMP (1 << 0) /* Bit 0: Compare Event */
#define TIMER_TSTAT_CAPT (1 << 1) /* Bit 1: Capture Event */
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_TIMER_H */
arch/arm/src/imx1/imx_timerisr.c
+1 -1
View File
@@ -118,7 +118,7 @@ void up_timer_initialize(void)
* (defined in board.h) is the number of counts in millisecond, so:
*/
putreg32(MSEC2TICK(IMX_PERCLK1_FREQ / 1000), IMX_TIMER1_TCMP);
putreg32(MSEC2TICK(IMX_PERCLK1_FREQ / 1000), IMX_TIMER1_TCMP);
/* Configure to provide timer COMP interrupts when TCN increments
* to TCMP.
arch/arm/src/imx1/imx_uart.h
+10 -10
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX1_CHIP_IMX_UART_H
#define __ARCH_ARM_SRC_IMX1_CHIP_IMX_UART_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* UART Register Offsets ************************************************************/
/* UART Register Offsets ****************************************************/
#define UART_RXD0 0x0000 /* UART receiver register 0 */
#define UART_RXD1 0x0004 /* UART receiver register 1 */
@@ -61,7 +61,7 @@
#define UART_BMPR4 0x00cc /* UART BRM modulator preset register 4 */
#define UART_UTS 0x00d0 /* UART test register */
/* UART Register Bit Definitions ****************************************************/
/* UART Register Bit Definitions ********************************************/
/* UART Receiver Register */
@@ -205,8 +205,8 @@
#define UART_UTS_LOOP (1 << 12) /* Bit 12: Loop TX and RX for Test */
#define UART_UTS_FRCPERR (1 << 13) /* Bit 13: Force Parity Error */
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_IMX1_CHIP_IMX_UART_H */
arch/arm/src/imx1/imx_usbd.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_usbd.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,20 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_USBD_H
#define __ARCH_ARM_IMX_USBD_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* USBD Register Offsets ************************************************************/
/* USBD Register Offsets ****************************************************/
#define USBD_FRAME_OFFSET 0x0000
#define USBD_SPEC_OFFSET 0x0004
@@ -61,7 +61,7 @@
#define USBD_EP_FRDP_OFFSET 0x0024
#define USBD_EP_FRWP_OFFSET 0x0028
/* USBD Register Addresses **********************************************************/
/* USBD Register Addresses **************************************************/
#define IMX_USBD_FRAME (IMX_USBD_VBASE + USBD_FRAME_OFFSET)
#define IMX_USBD_SPEC (IMX_USBD_VBASE + USBD_SPEC_OFFSET)
@@ -165,7 +165,7 @@
#define IMX_USBD_EP_FRDP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRDP_OFFSET)
#define IMX_USBD_EP_FRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRWP_OFFSET)
/* USBD Register Bit Definitions ****************************************************/
/* USBD Register Bit Definitions ********************************************/
/* USBD FRAME Register */
@@ -298,8 +298,8 @@
#define USBD_EPCTRL_FRAME (1 << 27) /* Bit 27: Frame Mode */
#define USBD_EPCTRL_WFR (1 << 28) /* Bit 29: Write Frame End */
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_USBD_H */
arch/arm/src/imx1/imx_wdog.h
+12 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx1/imx_wdog.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,32 +16,32 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX_WDOG_H
#define __ARCH_ARM_IMX_WDOG_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* WDOG Register Offsets ************************************************************/
/* WDOG Register Offsets ****************************************************/
#define WDOG_WCR_OFFSET 0x0000 /* Watchdog Control Register */
#define WDOG_WSR_OFFSET 0x0004 /* Watchdog Service Register */
#define WDOG_WSTR_OFFSET 0x0008 /* Watchdog Status Register */
/* WDOG Register Addresses **********************************************************/
/* WDOG Register Addresses **************************************************/
#define IMX_WDOG_WCR (IMX_WDOG_VBASE + WDOG_WCR_OFFSET)
#define IMX_WDOG_WSR (IMX_WDOG_VBASE + WDOG_WSR_OFFSET)
#define IMX_WDOG_WSTRT (IMX_WDOG_VBASE + WDOG_WSTR_OFFSET)
/* WDOG Register Bit Definitions ****************************************************/
/* WDOG Register Bit Definitions ********************************************/
/* Watchdog Control Register */
@@ -50,6 +50,7 @@
#define WDOG_WCR_SWR (1 << 2) /* Bit 2: Software Reset Enable */
#define WDOG_WCR_TMD (1 << 3) /* Bit 3: Test Mode Enable */
#define WDOG_WCR_WIE (1 << 4) /* Bit 4: Watchdog Interrupt Enable */
#define WDOG_WCR_WT_SHIFT 8 /* Bit 8-14: Watchdog Timeout */
#define WDOG_WCR_WT_MASK (0x7f << WDOG_WCR_WT_SHIFT)
#define WDOG_WCR_WHALT (1 << 15) /* Bit 15: Watchdog Halt */
@@ -59,8 +60,8 @@
#define WDOG_WSR_SHIFT 0 /* Bit 0-15: Watchdog Service Register */
#define WDOG_WT_MASK (0xffff << WDOG_WSR_SHIFT)
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_IMX_WDOG_H */
arch/arm/src/imx6/hardware/imx_ccm.h
+86 -32
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_ccm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,28 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* Reference:
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual",
* Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale.
*/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_CCM_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_CCM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* CCM Register Offsets *************************************************************/
/* CCM Register Offsets *****************************************************/
#define IMX_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */
#define IMX_CCM_CCDR_OFFSET 0x0004 /* CCM Control Divider Register */
@@ -71,7 +71,7 @@
#define IMX_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */
#define IMX_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Override Register */
/* CCM Register Addresses ***********************************************************/
/* CCM Register Addresses ***************************************************/
#define IMX_CCM_CCR (IMX_CCM_VBASE+IMX_CCM_CCR_OFFSET)
#define IMX_CCM_CCDR (IMX_CCM_VBASE+IMX_CCM_CCDR_OFFSET)
@@ -105,7 +105,7 @@
#define IMX_CCM_CCGR6 (IMX_CCM_VBASE+IMX_CCM_CCGR6_OFFSET)
#define IMX_CCM_CMEOR (IMX_CCM_VBASE+IMX_CCM_CMEOR_OFFSET)
/* CCM Register Bit Definitions *****************************************************/
/* CCM Register Bit Definitions *********************************************/
/* CCM Control Register */
@@ -188,12 +188,14 @@
# define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL3_SWCLK (1 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
# define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL2_PFD1 (2 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD1 */
# define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL2_PFD2 (3 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
#define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for gpu3d_shader clock multiplexer */
#define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (3 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT)
# define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MMDC_CH0 (0 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clk */
# define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_PLL3_SWCLK (1 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
# define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_PLL2_PFD1 (2 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD1 */
# define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_PLL3_PFD0 (3 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD0 */
#define CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) /* Bit 10: Selector for pcie_axi clock multiplexer */
#define CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) /* Bit 11: Selector for vdoaxi clock multiplexer */
#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */
@@ -201,23 +203,27 @@
# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SWCLK (0 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
# define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK (1 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) /* Derive clock from osc_clk (pll1_ref_clk) */
# define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BYPASS (2 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) /* Derive clock from pll2_bypass_clk */
#define CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for VPU axi clock multiplexer */
#define CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (3 << CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT)
# define CCM_CBCMR_VPU_AXI_CLK_SEL_AXI (0 << CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT) /* Derive clock from AXI */
# define CCM_CBCMR_VPU_AXI_CLK_SEL_PLL2_PFD2 (1 << CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CBCMR_VPU_AXI_CLK_SEL_PLL2_PFD0 (2 << CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
#define CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT (16) /* Bits 16-17: Selector for open vg (GPU2D Core) clock multiplexer */
#define CCM_CBCMR_GPU2D_CORE_CLK_SEL_MASK (3 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT)
# define CCM_CBCMR_GPU2D_CORE_CLK_SEL_AXI (0 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) /* Derive clock from AXI */
# define CCM_CBCMR_GPU2D_CORE_CLK_SEL_PLL3_SWCLK (1 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
# define CCM_CBCMR_GPU2D_CORE_CLK_SEL_PLL2_PFD0 (2 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
# define CCM_CBCMR_GPU2D_CORE_CLK_SEL_PLL2_PFD2 (3 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)
# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) /* Derive clock from PLL2 */
# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 (1 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 (2 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
# define CCM_CBCMR_PRE_PERIPH_CLK_SEL_DIV_PLL2_PFD2 (3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) /* Derive clock from divided (/2) PLL2 PFD2 */
#define CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) /* Bit 20: Selector for periph2_clk2 clock multiplexer */
#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT (21) /* Bits 21-22: Selector for pre_periph2 clock multiplexer */
#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (3 << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT)
@@ -225,6 +231,7 @@
# define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_PLL2_PFD2 (1 << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_PLL2_PFD0 (2 << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
# define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_DIV_PLL2_PFD2 (3 << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT) /* Derive clock from divided (/2) PLL2 PFD2 */
#define CCM_CBCMR_GPU2D_CORE_CLK_PODF_SHIFT (23) /* Bits 23-25: Divider for gpu2d_core clock */
#define CCM_CBCMR_GPU2D_CORE_CLK_PODF_MASK (7 << CCM_CBCMR_GPU2D_CORE_CLK_PODF_SHIFT)
# define CCM_CBCMR_GPU2D_CORE_CLK_PODF(n) ((uint32_t)(n) << CCM_CBCMR_GPU2D_CORE_CLK_PODF_SHIFT)
@@ -240,21 +247,25 @@
#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */
#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT)
# define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCMR1_SSI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for ssi1 clock multiplexer */
#define CCM_CSCMR1_SSI1_CLK_SEL_MASK (3 << CCM_CSCMR1_SSI1_CLK_SEL_SHIFT)
# define CCM_CSCMR1_SSI1_CLK_SEL_PLL3_PFD2 (0 << CCM_CSCMR1_SSI1_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */
# define CCM_CSCMR1_SSI1_CLK_SEL_PLL3_PFD3 (1 << CCM_CSCMR1_SSI1_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */
# define CCM_CSCMR1_SSI1_CLK_SEL_PLL4 (2 << CCM_CSCMR1_SSI1_CLK_SEL_SHIFT) /* Derive clock from PLL4 */
#define CCM_CSCMR1_SSI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for ssi2 clock multiplexer */
#define CCM_CSCMR1_SSI2_CLK_SEL_MASK (3 << CCM_CSCMR1_SSI2_CLK_SEL_SHIFT)
# define CCM_CSCMR1_SSI2_CLK_SEL_PLL3_PFD2 (0 << CCM_CSCMR1_SSI2_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */
# define CCM_CSCMR1_SSI2_CLK_SEL_PLL3_PFD3 (1 << CCM_CSCMR1_SSI2_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */
# define CCM_CSCMR1_SSI2_CLK_SEL_PLL4 (2 << CCM_CSCMR1_SSI2_CLK_SEL_SHIFT) /* Derive clock from PLL4 */
#define CCM_CSCMR1_SSI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for ssi3 clock multiplexer */
#define CCM_CSCMR1_SSI3_CLK_SEL_MASK (3 << CCM_CSCMR1_SSI3_CLK_SEL_SHIFT)
# define CCM_CSCMR1_SSI3_CLK_SEL_PLL3_PFD2 (0 << CCM_CSCMR1_SSI3_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */
# define CCM_CSCMR1_SSI3_CLK_SEL_PLL3_PFD3 (1 << CCM_CSCMR1_SSI3_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */
# define CCM_CSCMR1_SSI3_CLK_SEL_PLL4 (2 << CCM_CSCMR1_SSI3_CLK_SEL_SHIFT) /* Derive clock from PLL4 */
#define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */
#define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */
#define CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) /* Bit 18: Selector for usdhc3 clock multiplexer */
@@ -280,12 +291,14 @@
#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT (23) /* Bits 23-25: Divider for aclk_eim_slow clock root */
#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK (7 << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT)
# define CCM_CSCMR1_ACLK_EIM_SLOW_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCMR1_ACLK_SEL_SHIFT (27) /* Bits 27-28: Selector for aclk root clock multiplexer */
#define CCM_CSCMR1_ACLK_SEL_MASK (3 << CCM_CSCMR1_ACLK_SEL_SHIFT)
# define CCM_CSCMR1_ACLK_SEL_PLL2_PFD2 (0 << CCM_CSCMR1_ACLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CSCMR1_ACLK_SEL_PLL3_SWCLK (1 << CCM_CSCMR1_ACLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
# define CCM_CSCMR1_ACLK_SEL_AXI (2 << CCM_CSCMR1_ACLK_SEL_SHIFT) /* Derive clock from AXI */
# define CCM_CSCMR1_ACLK_SEL_PLL2_PFD0 (3 << CCM_CSCMR1_ACLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT (29) /* Bits 29-30: Selector for aclk_eim_slow root clock multiplexer */
#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK (3 << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT)
# define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_AXI (0 << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT) /* Derive clock from AXI */
@@ -298,6 +311,7 @@
#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */
#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)
# define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) /* Bit 10: Control for divider of ldb clock for IPU di0 */
#define CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) /* Bit 11: Control for divider of ldb clock for IPU di1 */
#define CCM_CSCMR2_ESAI_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for esai clock multiplexer */
@@ -312,18 +326,23 @@
#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */
#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT)
# define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */
#define CCM_CSCDR1_USDHC1_PODF_MASK (7 << CCM_CSCDR1_USDHC1_PODF_SHIFT)
# define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */
#define CCM_CSCDR1_USDHC2_PODF_MASK (7 << CCM_CSCDR1_USDHC2_PODF_SHIFT)
# define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCDR1_USDHC3_PODF_SHIFT (19) /* Bits 19-21: Divider for usdhc3 clock podf */
#define CCM_CSCDR1_USDHC3_PODF_MASK (7 << CCM_CSCDR1_USDHC3_PODF_SHIFT)
# define CCM_CSCDR1_USDHC3_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC3_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCDR1_USDHC4_PODF_SHIFT (22) /* Bits 22-24: Divider for usdhc4 clock pred */
#define CCM_CSCDR1_USDHC4_PODF_MASK (7 << CCM_CSCDR1_USDHC4_PODF_SHIFT)
# define CCM_CSCDR1_USDHC4_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC4_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCDR1_VPU_AXI_PODF_SHIFT (25) /* Bits 25-27: Divider for vpu axi clock podf */
#define CCM_CSCDR1_VPU_AXI_PODF_MASK (7 << CCM_CSCDR1_VPU_AXI_PODF_SHIFT)
# define CCM_CSCDR1_VPU_AXI_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_VPU_AXI_PODF_SHIFT) /* n=(divisor-1) */
@@ -336,15 +355,18 @@
#define CCM_CS1CDR_SSI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for ssi1 clock pred */
#define CCM_CS1CDR_SSI1_CLK_PRED_MASK (7 << CCM_CS1CDR_SSI1_CLK_PRED_SHIFT)
# define CCM_CS1CDR_SSI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SSI1_CLK_PRED_SHIFT) /* n=(divisor-1) */
#define CCM_CS1CDR_ESAI_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for esai clock pred */
#define CCM_CS1CDR_ESAI_CLK_PRED_MASK (7 << CCM_CS1CDR_ESAI_CLK_PRED_SHIFT)
# define CCM_CS1CDR_ESAI_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_ESAI_CLK_PRED_SHIFT) /* n=(divisor-1) */
#define CCM_CS1CDR_SSI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for ssi3 clock podf */
#define CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SSI3_CLK_PODF_SHIFT)
# define CCM_CS1CDR_SSI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SSI3_CLK_PODF_SHIFT)
#define CCM_CS1CDR_SSI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for ssi3 clock pred */
#define CCM_CS1CDR_SSI3_CLK_PRED_MASK (7 << CCM_CS1CDR_SSI3_CLK_PRED_SHIFT)
# define CCM_CS1CDR_SSI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SSI3_CLK_PRED_SHIFT) /* n=(divisor-1) */
#define CCM_CS1CDR_ESAI_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for esai clock podf */
#define CCM_CS1CDR_ESAI_CLK_PODF_MASK (7 << CCM_CS1CDR_ESAI_CLK_PODF_SHIFT)
# define CCM_CS1CDR_ESAI_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_ESAI_CLK_PODF_SHIFT) /* n=(divisor-1) */
@@ -354,9 +376,11 @@
#define CCM_CS2CDR_SSI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for ssi2 clock podf */
#define CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SSI2_CLK_PODF_SHIFT)
# define CCM_CS2CDR_SSI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SSI2_CLK_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CS2CDR_SSI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for ssi2 clock pred */
#define CCM_CS2CDR_SSI2_CLK_PRED_MASK (7 << CCM_CS2CDR_SSI2_CLK_PRED_SHIFT)
# define CCM_CS2CDR_SSI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SSI2_CLK_PRED_SHIFT) /* n=(divisor-1) */
#define CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for ldb_di1 clock multiplexer */
#define CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (7 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT)
# define CCM_CS2CDR_LDB_DI0_CLK_SEL_PLL5 (0 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) /* Derive from PLL5 clock */
@@ -364,6 +388,7 @@
# define CCM_CS2CDR_LDB_DI0_CLK_SEL_PLL2_PFD2 (2 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CS2CDR_LDB_DI0_CLK_SEL_MMDC_CH1 (3 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch1 clock */
# define CCM_CS2CDR_LDB_DI0_CLK_SEL_PLL3_SWCLK (4 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
#define CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT (12) /* Bits 12-14: Selector for ldb_di1 clock multiplexer */
#define CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (7 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT)
# define CCM_CS2CDR_LDB_DI1_CLK_SEL_PLL5 (0 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) /* Derive PLL5 clock */
@@ -371,15 +396,18 @@
# define CCM_CS2CDR_LDB_DI1_CLK_SEL_PLL2_PFD2 (2 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CS2CDR_LDB_DI1_CLK_SEL_MMDC_CH1 (3 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch1 clock */
# define CCM_CS2CDR_LDB_DI1_CLK_SEL_PLL3_SWCLK (4 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
#define CCM_CS2CDR_ENFC_CLK_SEL_SHIFT (16) /* Bits 16-17: Selector for enfc clock multiplexer */
#define CCM_CS2CDR_ENFC_CLK_SEL_MASK (3 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT)
# define CCM_CS2CDR_ENFC_CLK_SEL_PLL2_PFD0 (0 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
# define CCM_CS2CDR_ENFC_CLK_SEL_PLL2 (1 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) /* Derive clock from PLL2 */
# define CCM_CS2CDR_ENFC_CLK_SEL_PLL3_SWCLK (2 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
# define CCM_CS2CDR_ENFC_CLK_SEL_PLL2_PFD2 (3 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
#define CCM_CS2CDR_ENFC_CLK_PRED_SHIFT (18) /* Bits 18-20: Divider for enfc clock pred divider */
#define CCM_CS2CDR_ENFC_CLK_PRED_MASK (7 << CCM_CS2CDR_ENFC_CLK_PRED_SHIFT)
# define CCM_CS2CDR_ENFC_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_ENFC_CLK_PRED_SHIFT) /* n=(divisor-1) */
#define CCM_CS2CDR_ENFC_CLK_PODF_SHIFT (21) /* Bits 21-26: Divider for enfc clock divider */
#define CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3f << CCM_CS2CDR_ENFC_CLK_PODF_SHIFT)
# define CCM_CS2CDR_ENFC_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_ENFC_CLK_PODF_SHIFT)
@@ -392,24 +420,30 @@
# define CCM_CDCDR_SPDIF1_CLK_SEL_PLL3_PFD2 (1 << CCM_CDCDR_SPDIF1_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */
# define CCM_CDCDR_SPDIF1_CLK_SEL_PLL3_PFD3 (2 << CCM_CDCDR_SPDIF1_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */
# define CCM_CDCDR_SPDIF1_CLK_SEL_PLL3_SWCLK (3 << CCM_CDCDR_SPDIF1_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
#define CCM_CDCDR_SPDIF1_CLK_PODF_SHIFT (9) /* Bits 9-11: Divider for spdif1 clock podf */
#define CCM_CDCDR_SPDIF1_CLK_PODF_MASK (7 << CCM_CDCDR_SPDIF1_CLK_PODF_SHIFT)
# define CCM_CDCDR_SPDIF1_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF1_CLK_PODF_SHIFT) /* n=0,7 (divisor-1) */
#define CCM_CDCDR_SPDIF1_CLK_PRED_SHIFT (12) /* Bits 12-14: Divider for spdif1 clock pred */
#define CCM_CDCDR_SPDIF1_CLK_PRED_MASK (7 << CCM_CDCDR_SPDIF1_CLK_PRED_SHIFT)
# define CCM_CDCDR_SPDIF1_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF1_CLK_PRED_SHIFT) /* n=0,1,2,7 (divisor-1) */
#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */
#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
# define CCM_CDCDR_SPDIF0_CLK_SEL_DIV_PLL4 (0 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL4 divided clock */
# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 (1 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */
# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD3 (2 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */
# define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_SWCLK (3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */
#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)
# define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) /* n=0,7 (divisor-1) */
#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */
#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)
# define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) /* n=0,1,2,7 (divisor-1) */
#define CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) /* Bit 28: Selector for hsi_tx clock multiplexer */
#define CCM_CDCDR_HSI_TX_PODF_SHIFT (29) /* Bits 29-31: Divider for hsi_tx clock podf */
#define CCM_CDCDR_HSI_TX_PODF_MASK (7 << CCM_CDCDR_HSI_TX_PODF_SHIFT)
@@ -424,9 +458,11 @@
# define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_IPP_DI1_CLK (2 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */
# define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI0_CLK (3 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */
# define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI1_CLK (4 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */
#define CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT (3) /* Bits 3-5: Divider for ipu1_di0 clock divider */
#define CCM_CHSCCDR_IPU1_DI0_PODF_MASK (7 << CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT)
# define CCM_CHSCCDR_IPU1_DI0_PODF(n) ((uint32_t)(n) << CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT (6) /* Bits 6-8: Selector for ipu1 di0 root clock pre-multiplexer */
#define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (7 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT)
# define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MMDC_CH0 (0 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */
@@ -435,6 +471,7 @@
# define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL2_PFD0 (3 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
# define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL2_PFD2 (4 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL3_PFD1 (5 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */
#define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for ipu1 di1 root clock multiplexer */
#define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (7 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT)
# define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_DIV_IPU1 (0 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) /* Derive clock from divided pre-muxed ipu1 di1 clock */
@@ -442,9 +479,11 @@
# define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_IPP_DI1_CLK (2 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */
# define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_LDB_DI0_CLK (3 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */
# define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_LDB_DI1_CLK (4 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */
#define CCM_CHSCCDR_IPU1_DI1_PODF_SHIFT (12) /* Bits 12-14: Divider for ipu1_di clock divider */
#define CCM_CHSCCDR_IPU1_DI1_PODF_MASK (7 << CCM_CHSCCDR_IPU1_DI1_PODF_SHIFT)
# define CCM_CHSCCDR_IPU1_DI1_PODF(n) ((uint32_t)(n) << CCM_CHSCCDR_IPU1_DI1_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for ipu1 di1 root clock pre-multiplexer */
#define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (7 << CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_SHIFT)
# define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MMDC_CH0 (0 << CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */
@@ -463,9 +502,11 @@
# define CCM_CSCDR2_IPU2_DI0_CLK_SEL_IPP_DI1_CLK (2 << CCM_CSCDR2_IPU2_DI0_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */
# define CCM_CSCDR2_IPU2_DI0_CLK_SEL_LDB_DI0_CLK (3 << CCM_CSCDR2_IPU2_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */
# define CCM_CSCDR2_IPU2_DI0_CLK_SEL_LDB_DI1_CLK (4 << CCM_CSCDR2_IPU2_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */
#define CCM_CSCDR2_IPU2_DI0_PODF_SHIFT (3) /* Bits 3-5: Divider for ipu2_di0 clock divider */
#define CCM_CSCDR2_IPU2_DI0_PODF_MASK (7 << CCM_CSCDR2_IPU2_DI0_PODF_SHIFT)
# define CCM_CSCDR2_IPU2_DI0_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_IPU2_DI0_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT (6) /* Bits 6-8: Selector for ipu2 di0 root clock pre-multiplexer */
#define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (7 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT)
#define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MMDC_CH0 (0 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */
@@ -474,6 +515,7 @@
#define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_PLL2_PFD (3 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
#define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_PLL2_PFD2 (4 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
#define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_PLL3_PFD1 (5 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */
#define CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for ipu1 di2 root clock multiplexer */
#define CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (7 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT)
# define CCM_CSCDR2_IPU2_DI1_CLK_SEL_DIV_IPU1 (0 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) /* Derive clock from divided pre-muxed ipu1 di1 clock */
@@ -481,9 +523,11 @@
# define CCM_CSCDR2_IPU2_DI1_CLK_SEL_IPP_DI1_CLK (2 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */
# define CCM_CSCDR2_IPU2_DI1_CLK_SEL_LDB_DI0_CLK (3 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */
# define CCM_CSCDR2_IPU2_DI1_CLK_SEL_LDB_DI1_CLK (4 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */
#define CCM_CSCDR2_IPU2_DI1_PODF_SHIFT (12) /* Bits 12-14: Divider for ipu2_di1 clock divider */
#define CCM_CSCDR2_IPU2_DI1_PODF_MASK (7 << CCM_CSCDR2_IPU2_DI1_PODF_SHIFT)
# define CCM_CSCDR2_IPU2_DI1_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_IPU2_DI1_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for ipu2 di1 root clock pre-multiplexer */
#define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (7 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT)
# define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MMDC_CH0 (0 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */
@@ -492,6 +536,7 @@
# define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_PLL2_PFD0 (3 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */
# define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_PLL2_PFD2 (4 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_PLL3_PFD1 (5 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */
#define CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for ecspi clock podf */
#define CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3f << CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT)
# define CCM_CSCDR2_ECSPI_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT) /* n=(divisor-1) */
@@ -504,15 +549,18 @@
# define CCM_CSCDR3_IPU1_HSP_CLK_SEL_PLL2_PFD2 (1 << CCM_CSCDR3_IPU1_HSP_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CSCDR3_IPU1_HSP_CLK_SEL_PLL3_120M (2 << CCM_CSCDR3_IPU1_HSP_CLK_SEL_SHIFT) /* Derive clock from pll3_120M */
# define CCM_CSCDR3_IPU1_HSP_CLK_SEL_PLL3_PFD1 (3 << CCM_CSCDR3_IPU1_HSP_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */
#define CCM_CSCDR3_IPU1_HSP_PODF_SHIFT (11) /* Bits 11-13: Divider for ipu1_hsp clock */
#define CCM_CSCDR3_IPU1_HSP_PODF_MASK (7 << CCM_CSCDR3_IPU1_HSP_PODF_SHIFT)
# define CCM_CSCDR3_IPU1_HSP_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_IPU1_HSP_PODF_SHIFT) /* n=(divisor-1) */
#define CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for ipu2_hsp clock multiplexer */
#define CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (3 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT)
# define CCM_CSCDR3_IPU2_HSP_CLK_SEL_MMDC_CH0 (0 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */
# define CCM_CSCDR3_IPU2_HSP_CLK_SEL_PLL2_PFD2 (1 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
# define CCM_CSCDR3_IPU2_HSP_CLK_SEL_PLL3_120M (2 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) /* Derive clock from pll3_120M */
# define CCM_CSCDR3_IPU2_HSP_CLK_SEL_PLL3_PFD1 (3 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */
#define CCM_CSCDR3_IPU2_HSP_PODF_SHIFT (16) /* Bits 16-18: Divider for ipu2_hsp clock */
#define CCM_CSCDR3_IPU2_HSP_PODF_MASK (7 << CCM_CSCDR3_IPU2_HSP_PODF_SHIFT)
# define CCM_CSCDR3_IPU2_HSP_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_IPU2_HSP_PODF_SHIFT) /* n=(divisor-1) */
@@ -536,6 +584,7 @@
# define CCM_CLPCR_LPM_RUNMODE (0 << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */
# define CCM_CLPCR_LPM_WAITMODE (1 << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */
# define CCM_CLPCR_LPM_STOPMODE (2 << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */
#define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */
#define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: Control closing of external reference oscillator clock */
@@ -546,6 +595,7 @@
# define CCM_CLPCR_STBY_COUNT_3 (1 << CCM_CLPCR_STBY_COUNT_SHIFT) /* Wait (3*pmic_delay_scaler)+1 ckil clocks */
# define CCM_CLPCR_STBY_COUNT_7 (2 << CCM_CLPCR_STBY_COUNT_SHIFT) /* Wait (7*pmic_delay_scaler)+1 ckil clocks */
# define CCM_CLPCR_STBY_COUNT_15 (3 << CCM_CLPCR_STBY_COUNT_SHIFT) /* Wait (15*pmic_delay_scaler)+1 ckil clocks */
#define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: Control powering down of on chip oscillator */
#define CCM_CLPCR_WB_PER_AT_LPM (1 << 16) /* Bit 16: Enable periphery charge pump for well biasing at low power mode */
#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS (1 << 19) /* Bit 19: Bypass handshake with mmdc_ch0 on next entrance to low power mode */
@@ -574,39 +624,41 @@
#define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */
#define CCM_CCOSR_CLKO1_SEL_MASK (15 << CCM_CCOSR_CLKO1_SEL_SHIFT)
# define CCM_CCOSR_CLKO1_SEL_PLL3_SW_CLK (0 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll3_sw_clk (/2) */
# define CCM_CCOSR_CLKO1_SEL_PLL2_MAIN_CLK (1 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll2_main_clk (/2) */
# define CCM_CCOSR_CLKO1_SEL_PLL1_MAIN_CLK (2 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll1_main_clk (/2) */
# define CCM_CCOSR_CLKO1_SEL_PLL5_MAIN_CLK (3 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll5_main_clk (/2) */
# define CCM_CCOSR_CLKO1_SEL_VIDEO_27M_CLK_ROOT (4 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* video_27M_clk_root */
# define CCM_CCOSR_CLKO1_SEL_AXI_CLK_ROOT (5 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* axi_clk_root */
# define CCM_CCOSR_CLKO1_SEL_ENFC_CLK_ROOT (6 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* enfc_clk_root */
# define CCM_CCOSR_CLKO1_SEL_IPU1_DI0_CLK_ROOT (7 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu1_di0_clk_root */
# define CCM_CCOSR_CLKO1_SEL_IPU1_DI1_CLK_ROOT (8 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu1_di1_clk_root */
# define CCM_CCOSR_CLKO1_SEL_IPU2_DI0_CLK_ROOT (9 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu2_di0_clk_root */
# define CCM_CCOSR_CLKO1_SEL_PLL3_SW_CLK (0 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll3_sw_clk (/2) */
# define CCM_CCOSR_CLKO1_SEL_PLL2_MAIN_CLK (1 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll2_main_clk (/2) */
# define CCM_CCOSR_CLKO1_SEL_PLL1_MAIN_CLK (2 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll1_main_clk (/2) */
# define CCM_CCOSR_CLKO1_SEL_PLL5_MAIN_CLK (3 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll5_main_clk (/2) */
# define CCM_CCOSR_CLKO1_SEL_VIDEO_27M_CLK_ROOT (4 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* video_27M_clk_root */
# define CCM_CCOSR_CLKO1_SEL_AXI_CLK_ROOT (5 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* axi_clk_root */
# define CCM_CCOSR_CLKO1_SEL_ENFC_CLK_ROOT (6 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* enfc_clk_root */
# define CCM_CCOSR_CLKO1_SEL_IPU1_DI0_CLK_ROOT (7 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu1_di0_clk_root */
# define CCM_CCOSR_CLKO1_SEL_IPU1_DI1_CLK_ROOT (8 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu1_di1_clk_root */
# define CCM_CCOSR_CLKO1_SEL_IPU2_DI0_CLK_ROOT (9 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu2_di0_clk_root */
# define CCM_CCOSR_CLKO1_SEL_IPU2_DI1_CLK_ROOT (10 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu2_di1_clk_root */
# define CCM_CCOSR_CLKO1_SEL_AHB_CLK_ROOT (11 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ahb_clk_root */
# define CCM_CCOSR_CLKO1_SEL_IPG_CLK_ROOT (12 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipg_clk_root */
# define CCM_CCOSR_CLKO1_SEL_PERCLK_ROOT (13 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* perclk_root */
# define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK_ROOT (14 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ckil_sync_clk_root */
# define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK (15 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll4_main_clk */
#define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */
#define CCM_CCOSR_CLKO1_DIV_MASK (7 << CCM_CCOSR_CLKO1_DIV_SHIFT)
# define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) /* n=(divisor-1) */
#define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */
#define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */
#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */
#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */
#define CCM_CCOSR_CLKO2_SEL_MASK (0x1f << CCM_CCOSR_CLKO2_SEL_SHIFT)
# define CCM_CCOSR_CLKO2_SEL_MMDC_CH0_CLK_ROOT (0 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* mmdc_ch0_clk_root */
# define CCM_CCOSR_CLKO2_SEL_MMDC_CH1_CLK_ROOT (1 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* mmdc_ch1_clk_root */
# define CCM_CCOSR_CLKO2_SEL_USDHC4_CLK_ROOT (2 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc4_clk_root */
# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK_ROOT (3 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc1_clk_root */
# define CCM_CCOSR_CLKO2_SEL_GPU2D_AXI_CLK_ROOT (4 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* gpu2d_axi_clk_root */
# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK_ROOT (5 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* wrck_clk_root */
# define CCM_CCOSR_CLKO2_SEL_ECSPI_CLK_ROOT (6 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* ecspi_clk_root */
# define CCM_CCOSR_CLKO2_SEL_GPU3D_AXI_CLK_ROOT (7 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* gpu3d_axi_clk_root */
# define CCM_CCOSR_CLKO2_SEL_USDHC3_CLK_ROOT (8 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc3_clk_root */
# define CCM_CCOSR_CLKO2_SEL_125M_CLK_ROOT (9 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* 125M_clk_root */
# define CCM_CCOSR_CLKO2_SEL_MMDC_CH0_CLK_ROOT (0 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* mmdc_ch0_clk_root */
# define CCM_CCOSR_CLKO2_SEL_MMDC_CH1_CLK_ROOT (1 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* mmdc_ch1_clk_root */
# define CCM_CCOSR_CLKO2_SEL_USDHC4_CLK_ROOT (2 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc4_clk_root */
# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK_ROOT (3 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc1_clk_root */
# define CCM_CCOSR_CLKO2_SEL_GPU2D_AXI_CLK_ROOT (4 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* gpu2d_axi_clk_root */
# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK_ROOT (5 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* wrck_clk_root */
# define CCM_CCOSR_CLKO2_SEL_ECSPI_CLK_ROOT (6 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* ecspi_clk_root */
# define CCM_CCOSR_CLKO2_SEL_GPU3D_AXI_CLK_ROOT (7 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* gpu3d_axi_clk_root */
# define CCM_CCOSR_CLKO2_SEL_USDHC3_CLK_ROOT (8 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc3_clk_root */
# define CCM_CCOSR_CLKO2_SEL_125M_CLK_ROOT (9 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* 125M_clk_root */
# define CCM_CCOSR_CLKO2_SEL_ARM_CLK_ROOT (10 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* arm_clk_root */
# define CCM_CCOSR_CLKO2_SEL_IPU1_HSP_CLK_ROOT (11 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* ipu1_hsp_clk_root */
# define CCM_CCOSR_CLKO2_SEL_IPU2_HSP_CLK_ROOT (12 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* ipu2_hsp_clk_root */
@@ -629,9 +681,11 @@
# define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK_ROOT (29 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* spdif0_clk_root */
# define CCM_CCOSR_CLKO2_SEL_SPDIF1_CLK_ROOT (30 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* spdif1_clk_root */
# define CCM_CCOSR_CLKO2_SEL_HSI_TX_CLK_ROOT (31 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* hsi_tx_clk_root */
#define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */
#define CCM_CCOSR_CLKO2_DIV_MASK (7 << CCM_CCOSR_CLKO2_DIV_SHIFT)
# define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) /* n=(divisor-1) */
#define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */
/* CCM General Purpose Register */
arch/arm/src/imx6/hardware/imx_ecspi.h
+25 -14
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_ecspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* ECSPI Register Offsets ***********************************************************/
/* ECSPI Register Offsets ***************************************************/
#define ECSPI_RXDATA_OFFSET 0x0000 /* Receive Data Register */
#define ECSPI_TXDATA_OFFSET 0x0004 /* Transmit Data Register */
@@ -45,7 +45,7 @@
#define ECSPI_TESTREG_OFFSET 0x0020 /* Test Control Register */
#define ECSPI_MSGDATA_OFFSET 0x0040 /* Message Data Register */
/* ECSPI Register Addresses *********************************************************/
/* ECSPI Register Addresses *************************************************/
/* ECSPI1 */
@@ -112,7 +112,7 @@
#define IMX_ECSPI5_TESTREG (IMX_ECSPI5_VBASE + ECSPI_TESTREG_OFFSET)
#define IMX_ECSPI5_MSGDATA (IMX_ECSPI5_VBASE + ECSPI_MSGDATA_OFFSET)
/* ECSPI Register Bit Definitions ***************************************************/
/* ECSPI Register Bit Definitions *******************************************/
/* Control Register */
@@ -120,12 +120,13 @@
#define ECSPI_CONREG_HT (1 << 1) /* Bit 1: Hardware trigger enable */
#define ECSPI_CONREG_XCH (1 << 2) /* Bit 2: SPI Exchange bit */
#define ECSPI_CONREG_SMC (1 << 3) /* Bit 3: Start mode control */
#define ECSPI_CONREG_CHMODE_SHIFT (4) /* Bits 4-7: SPI Channel mode */
#define ECSPI_CONREG_CHMODE_SHIFT (4) /* Bits 4-7: SPI Channel mode */
#define ECSPI_CONREG_CHMODE_MASK (15 << ECSPI_CONREG_CHMODE_SHIFT)
# define ECSPI_CONREG_CH0MASTER (1 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 0 master mode */
# define ECSPI_CONREG_CH1MASTER (2 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 1 master mode */
# define ECSPI_CONREG_CH2MASTER (4 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 2 master mode */
# define ECSPI_CONREG_CH3MASTER (8 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 3 master mode */
#define ECSPI_CONREG_POSTDIV_SHIFT (8) /* Bits 8-11: SPI Post divider (exponent) */
#define ECSPI_CONREG_POSTDIV_MASK (15 << ECSPI_CONREG_POSTDIV_SHIFT)
# define ECSPI_CONREG_POSTDIV_EXP(n) ((uint32_t)(n) << ECSPI_CONREG_POSTDIV_SHIFT)
@@ -145,20 +146,24 @@
# define ECSPI_CONREG_POSTDIV_8192 (13 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*13 */
# define ECSPI_CONREG_POSTDIV_16384 (14 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*14 */
# define ECSPI_CONREG_POSTDIV_32768 (15 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*15 */
#define ECSPI_CONREG_PREDIV_SHIFT (12) /* Bits 12-15: SPI Pre divider (minus 1) */
#define ECSPI_CONREG_PREDIV_MASK (15 << ECSPI_CONREG_PREDIV_SHIFT)
# define ECSPI_CONREG_PREDIV(n) ((uint32_t)(n) << ECSPI_CONREG_PREDIV_SHIFT)
#define ECSPI_CONREG_DRCTL_SHIFT 16 /* Bits 16-17: SPI Data ready control */
#define ECSPI_CONREG_DRCTL_MASK (3 << ECSPI_CONREG_DRCTL_SHIFT)
# define ECSPI_CONREG_DRCTL_IGNRDY (0 << ECSPI_CONREG_DRCTL_SHIFT)
# define ECSPI_CONREG_DRCTL_FALLING (1 << ECSPI_CONREG_DRCTL_SHIFT)
# define ECSPI_CONREG_DRCTL_ACTVLOW (2 << ECSPI_CONREG_DRCTL_SHIFT)
#define ECSPI_CONREG_CHSEL_SHIFT (18) /* Bits 18-19: SPI Channel select bits */
#define ECSPI_CONREG_CHSEL_MASK (3 << ECSPI_CONREG_CHSEL_SHIFT)
# define ECSPI_CONREG_CHSEL_SS0 (0 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 0 select (SS0) */
# define ECSPI_CONREG_CHSEL_SS1 (1 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 1 select (SS1) */
# define ECSPI_CONREG_CHSEL_SS2 (2 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 2 select (SS2) */
# define ECSPI_CONREG_CHSEL_SS3 (3 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 3 select (SS3) */
#define ECSPI_CONREG_BURSTLEN_SHIFT (20) /* Bits 20-31: Burst length */
#define ECSPI_CONREG_BURSTLEN_MASK (0xfff << ECSPI_CONREG_BURSTLEN_SHIFT)
# define ECSPI_CONREG_BURSTLEN(n) ((uint32_t)(n) << ECSPI_CONREG_BURSTLEN_SHIFT)
@@ -171,36 +176,42 @@
# define ECSPI_CONFIGREG_CH1PHA (2 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 1 SCLK Phase */
# define ECSPI_CONFIGREG_CH2PHA (4 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 2 SCLK Phase */
# define ECSPI_CONFIGREG_CH3PHA (8 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 3 SCLK Phase */
#define ECSPI_CONFIGREG_SCLKPOL_SHIFT (4) /* Bits 4-7: SPI Clock polarity control */
#define ECSPI_CONFIGREG_SCLKPOL_MASK (15 << ECSPI_CONFIGREG_SCLKPOL_SHIFT)
# define ECSPI_CONFIGREG_CH0POL (1 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 0 SCLK polarity */
# define ECSPI_CONFIGREG_CH1POL (2 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 1 SCLK polarity */
# define ECSPI_CONFIGREG_CH2POL (4 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 2 SCLK polarity */
# define ECSPI_CONFIGREG_CH3POL (8 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 3 SCLK polarity */
#define ECSPI_CONFIGREG_SSCTL_SHIFT (8) /* Bits 8-11: SPI SS Wave form select */
#define ECSPI_CONFIGREG_SSCTL_MASK (15 << ECSPI_CONFIGREG_SSCTL_SHIFT)
# define ECSPI_CONFIGREG_CH0SSCTRL (1 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 0 SS control */
# define ECSPI_CONFIGREG_CH1SSCTRL (2 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 1 SS control */
# define ECSPI_CONFIGREG_CH2SSCTRL (4 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 2 SS control */
# define ECSPI_CONFIGREG_CH3SSCTRL (8 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 3 SS control */
#define ECSPI_CONFIGREG_SSPOL_SHIFT (12) /* Bits 12-15: SPI SS Polarity select */
#define ECSPI_CONFIGREG_SSPOL_MASK (15 << ECSPI_CONFIGREG_SSPOL_SHIFT)
# define ECSPI_CONFIGREG_CH0SSPOL (1 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 0 SS polarity */
# define ECSPI_CONFIGREG_CH1SSPOL (2 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 1 SS polarity */
# define ECSPI_CONFIGREG_CH2SSPOL (4 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 2 SS polarity */
# define ECSPI_CONFIGREG_CH3SSPOL (8 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 3 SS polarity */
#define ECSPI_CONFIGREG_DATCTL_SHIFT (16) /* Bits 16-19: Data control */
#define ECSPI_CONFIGREG_DATCTL_MASK (15 << ECSPI_CONFIGREG_DATCTL_SHIFT)
# define ECSPI_CONFIGREG_CH0DATLOW (1 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 0 SS low when inactive */
# define ECSPI_CONFIGREG_CH1DATLOW (2 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 1 SS low when inactive */
# define ECSPI_CONFIGREG_CH2DATLOW (4 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 2 SS low when inactive */
# define ECSPI_CONFIGREG_CH3DATLOW (8 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 3 SS low when inactive */
#define ECSPI_CONFIGREG_SCLKCTL_SHIFT (20) /* Bits 20-23: SCLK Control */
#define ECSPI_CONFIGREG_SCLKCTL_MASK (15 << ECSPI_CONFIGREG_SCLKCTL_SHIFT)
# define ECSPI_CONFIGREG_CH0SCLKLOW (1 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 0 SCLK low when inactive */
# define ECSPI_CONFIGREG_CH1SCLKLOW (2 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 1 SCLK low when inactive */
# define ECSPI_CONFIGREG_CH2SCLKLOW (4 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 2 SCLK low when inactive */
# define ECSPI_CONFIGREG_CH3SCLKLOW (8 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 3 SCLK low when inactive */
#define ECSPI_CONFIGREG_HTLEN_SHIFT (24) /* Bits 24-28: HT Length */
#define ECSPI_CONFIGREG_HTLEN_MASK (15 << ECSPI_CONFIGREG_HTLEN_SHIFT)
# define ECSPI_CONFIGREG_HTLEN(n) ((uint32_t)(n) << ECSPI_CONFIGREG_HTLEN_SHIFT)
@@ -264,12 +275,12 @@
/* Message Data Register (32-bit message data) */
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H */
arch/arm/src/imx6/hardware/imx_enet.h
+13 -13
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_enet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,26 +16,26 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_ENET_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_ENET_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define IMX_ENET_HAS_DBSWAP 1
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define IMX_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */
#define IMX_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */
@@ -96,7 +96,7 @@
#define IMX_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */
#define IMX_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define IMX_ENET_EIR (IMX_ENET_VBASE+IMX_ENET_EIR_OFFSET)
#define IMX_ENET_EIMR (IMX_ENET_VBASE+IMX_ENET_EIMR_OFFSET)
@@ -149,7 +149,7 @@
#define IMX_ENET_TCSR3 (IMX_ENET_VBASE+IMX_ENET_TCSR3_OFFSET)
#define IMX_ENET_TCCR3 (IMX_ENET_VBASE+IMX_ENET_TCCR3_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Interrupt Event Register, Interrupt Mask Register */
@@ -490,7 +490,7 @@
/* Timer Compare Capture Register (32-bit compare value) */
/* Buffer Descriptors ***************************************************************/
/* Buffer Descriptors *******************************************************/
/* Endian-independent descriptor offsets */
@@ -637,11 +637,11 @@
# define RXDESC_BDU (1 << 7)
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/* Buffer Descriptors ***************************************************************/
/* Buffer Descriptors *******************************************************/
/* Legacy Buffer Descriptor */
arch/arm/src/imx6/hardware/imx_gpio.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,26 +16,26 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* Reference:
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual",
* Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale.
*/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPIO_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define GPIO1 0 /* Port 1 index */
#define GPIO2 1 /* Port 2 index */
@@ -48,7 +48,7 @@
#define IMX_GPIO_NPORTS 7 /* Seven total ports */
#define IMX_GPIO_NPINS 32 /* Up to 32 pins per port */
/* GPIO Register Offsets ************************************************************/
/* GPIO Register Offsets ****************************************************/
#define IMX_GPIO_DR_OFFSET 0x0000 /* Data Register */
#define IMX_GPIO_GDIR_OFFSET 0x0004 /* Data Direction Register */
@@ -59,7 +59,7 @@
#define IMX_GPIO_ISR_OFFSET 0x0018 /* Interrupt Status Register */
#define IMX_GPIO_EDGE_OFFSET 0x001c /* Interrupt Status Register */
/* GPIO Register Addresses **********************************************************/
/* GPIO Register Addresses **************************************************/
#define IMX_GPIO_DR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_DR_OFFSET)
#define IMX_GPIO_GDIR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_GDIR_OFFSET)
@@ -133,7 +133,7 @@
#define IMX_GPIO7_ISR (IMX_GPIO7_VBASE+IMX_GPIO_ISR_OFFSET)
#define IMX_GPIO7_EDGE (IMX_GPIO7_VBASE+IMX_GPIO_EDGE_OFFSET)
/* GPIO Register Bit Definitions ****************************************************/
/* GPIO Register Bit Definitions ********************************************/
/* Most registers are laid out simply with one bit per pin */
arch/arm/src/imx6/hardware/imx_gpt.h
+19 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_gpt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,28 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* Reference:
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual",
* Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale.
*/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPT Register Offsets ************************************************************/
/* GPT Register Offsets *****************************************************/
#define IMX_GPT_CR_OFFSET 0x0000 /* GPT Control Register */
#define IMX_GPT_PR_OFFSET 0x0004 /* GPT Prescaler Register */
@@ -50,7 +50,7 @@
#define IMX_GPT_ICR2_OFFSET 0x0020 /* GPT Input Capture Register 2 */
#define IMX_GPT_CNT_OFFSET 0x0024 /* GPT Counter Register */
/* GPT Register Addresses **********************************************************/
/* GPT Register Addresses ***************************************************/
#define IMX_GPT_CR (IMX_GPT_VBASE+IMX_GPT_CR_OFFSET)
#define IMX_GPT_PR (IMX_GPT_VBASE+IMX_GPT_PR_OFFSET)
@@ -63,7 +63,7 @@
#define IMX_GPT_ICR2 (IMX_GPT_VBASE+IMX_GPT_ICR2_OFFSET)
#define IMX_GPT_CNT (IMX_GPT_VBASE+IMX_GPT_CNT_OFFSET)
/* GPT Register Bit Definitions ****************************************************/
/* GPT Register Bit Definitions *********************************************/
/* GPT Control Register */
@@ -82,6 +82,7 @@
# define GPT_CR_CLKSRC_LFREF (4 << GPT_CR_CLKSRC_SHIFT) /* Low Frequency Reference Clock */
# define GPT_CR_CLKSRC_OSCDIV8 (5 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator divided by 8 as Reference Clock */
# define GPT_CR_CLKSRC_OSC (7 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator as Reference Clock */
#define GPT_CR_FFR (1 << 9) /* Bit 9: Free-Run or Restart mode */
#define GPT_CR_SWR (1 << 15) /* Bit 15: Software reset */
#define GPT_CR_IM1_SHIFT (16) /* Bits 16-17: Input Capture Channel 1 operating mode */
@@ -90,12 +91,14 @@
# define GPT_CR_IM1_RISING (1 << GPT_CR_IM1_SHIFT) /* Capture on rising edge only */
# define GPT_CR_IM1_FALLING (2 << GPT_CR_IM1_SHIFT) /* Capture on falling edge only */
# define GPT_CR_IM1_BOTH (3 << GPT_CR_IM1_SHIFT) /* Capture on both edges */
#define GPT_CR_IM2_SHIFT (18) /* Bits 18-19: Input Capture Channel 2 operating mode */
#define GPT_CR_IM2_MASK (3 << GPT_CR_IM2_SHIFT)
# define GPT_CR_IM2_DISABLED (0 << GPT_CR_IM2_SHIFT) /* Capture disabled */
# define GPT_CR_IM2_RISING (1 << GPT_CR_IM2_SHIFT) /* Capture on rising edge only */
# define GPT_CR_IM2_FALLING (2 << GPT_CR_IM2_SHIFT) /* Capture on falling edge only */
# define GPT_CR_IM2_BOTH (3 << GPT_CR_IM2_SHIFT) /* Capture on both edges */
#define GPT_CR_OM1_SHIFT (22) /* Bits 20-22: Output Compare Channel 1 operating mode */
#define GPT_CR_OM1_MASK (7 << GPT_CR_OM1_SHIFT)
# define GPT_CR_OM1_DISCON (0 << GPT_CR_OM1_SHIFT) /* Output disconnected */
@@ -103,6 +106,7 @@
# define GPT_CR_OM1_CLEAR (2 << GPT_CR_OM1_SHIFT) /* Clear output pin */
# define GPT_CR_OM1_SET (3 << GPT_CR_OM1_SHIFT) /* Set output pin */
# define GPT_CR_OM1_PULSE (4 << GPT_CR_OM1_SHIFT) /* Generate an active low pulse */
#define GPT_CR_OM2_SHIFT (23) /* Bits 23-25: Output Compare Channel 2 operating mode */
#define GPT_CR_OM2_MASK (7 << GPT_CR_OM2_SHIFT)
# define GPT_CR_OM2_DISCON (0 << GPT_CR_OM2_SHIFT) /* Output disconnected */
@@ -110,6 +114,7 @@
# define GPT_CR_OM2_CLEAR (2 << GPT_CR_OM2_SHIFT) /* Clear output pin */
# define GPT_CR_OM2_SET (3 << GPT_CR_OM2_SHIFT) /* Set output pin */
# define GPT_CR_OM2_PULSE (4 << GPT_CR_OM2_SHIFT) /* Generate an active low pulse */
#define GPT_CR_OM3_SHIFT (26) /* Bits 26-28: Output Compare Channel 3 operating mode */
#define GPT_CR_OM3_MASK (7 << GPT_CR_OM3_SHIFT)
# define GPT_CR_OM3_DISCON (0 << GPT_CR_OM3_SHIFT) /* Output disconnected */
@@ -117,6 +122,7 @@
# define GPT_CR_OM3_CLEAR (2 << GPT_CR_OM3_SHIFT) /* Clear output pin */
# define GPT_CR_OM3_SET (3 << GPT_CR_OM3_SHIFT) /* Set output pin */
# define GPT_CR_OM3_PULSE (4 << GPT_CR_OM3_SHIFT) /* Generate an active low pulse */
#define GPT_CR_FO1 (1 << 29) /* FO1 Force Output Compare Channel 1 */
#define GPT_CR_FO2 (1 << 30) /* FO2 Force Output Compare Channel 2 */
#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
@@ -137,7 +143,9 @@
#define GPT_INT_ALL 0x0000003f
/* GPT Output Compare Register 1,2,3 -- 32-bit compare registers */
/* GPT Input Capture Register 1,2 -- 32-bit capture registers */
/* GPT Counter Register -- 32-bit counter */
#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H */
arch/arm/src/imx6/hardware/imx_iomuxc.h
+26 -14
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_iomuxc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,34 +16,35 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* Reference:
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual",
* Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale.
*/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_IOMUXC_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_IOMUXC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx_memorymap.h"
/* These definitions derive from specifications for the i.MX 6Quad/6Dual and require
* review and modification in order to support other family members.
/* These definitions derive from specifications for the i.MX 6Quad/6Dual and
* require review and modification in order to support other family members.
*/
#if defined(CONFIG_ARCH_CHIP_IMX6_6QUAD) || defined(CONFIG_ARCH_CHIP_IMX6_6DUAL)
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* IOMUXC Register Offsets **************************************************/
/* IOMUXC Register Offsets **********************************************************/
/* General Purpose Registers */
#define IMX_IOMUXC_GPR0_OFFSET 0x0000
@@ -62,6 +63,7 @@
#define IMX_IOMUXC_GPR13_OFFSET 0x0034
/* Pad Mux Registers */
/* Pad Mux Register Indices (used by software for table lookups) */
#define IMX_PADMUX_SD2_DATA1_INDEX 0
@@ -467,6 +469,7 @@
#define IMX_PADMUX_SD2_DATA3_OFFSET 0x035c
/* Pad Control Registers */
/* Pad Mux Register Indices (used by software for table lookups) */
#define IMX_PADCTL_SD2_DATA1_INDEX 0
@@ -1112,7 +1115,8 @@
#define IMX_INPUT_USB_H1_OC_OFFSET 0x0948
#define IMX_INPUT_USDHC1_WP_ON_OFFSET 0x094c
/* IOMUXC Register Addresses ********************************************************/
/* IOMUXC Register Addresses ************************************************/
/* General Purpose Registers */
#define IMX_IOMUXC_GPR0 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR0_OFFSET)
@@ -1722,7 +1726,7 @@
#define IMX_INPUT_USB_H1_OC (IMX_IOMUXC_VBASE+IMX_INPUT_USB_H1_OC_OFFSET)
#define IMX_INPUT_USDHC1_WP_ON (IMX_IOMUXC_VBASE+IMX_INPUT_USDHC1_WP_ON_OFFSET)
/* IOMUXC Register Bit Definitions **************************************************/
/* IOMUXC Register Bit Definitions ******************************************/
/* General Purpose Register 0 (GPR0) */
@@ -2063,6 +2067,7 @@
#define GPR10_LOCK_DBG_EN (1 << 29)
/* General Purpose Register 11 (GPR11) -- Contains no fields of interest. */
/* General Purpose Register 12 (GPR12) */
#define GPR12_USDHC_DBG_MUX_SHIFT (2)
@@ -2087,7 +2092,7 @@
# define GPR12_DIA_STATUS_BUS_SELECT(n) ((uint32_t)(n) << GPR12_DIA_STATUS_BUS_SELECT_SHIFT)
#define GPR12_PCIE_CTL_7_SHIFT (21)
#define GPR12_PCIE_CTL_7_MASK (7 << GPR12_PCIE_CTL_7_SHIFT)
#define GPR12_PCIE_CTL_7(n) ((uint32_t)(n) << GPR12_PCIE_CTL_7_SHIFT)
# define GPR12_PCIE_CTL_7(n) ((uint32_t)(n) << GPR12_PCIE_CTL_7_SHIFT)
#define GPR12_ARMP_APB_CLK_EN (1 << 24)
#define GPR12_ARMP_ATB_CLK_EN (1 << 25)
#define GPR12_ARMP_AHB_CLK_EN (1 << 26)
@@ -2227,6 +2232,7 @@
#define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */
#define PADCTL_DSE_MASK (7 << PADCTL_DSE_SHIFT)
# define PADCTL_DSE(n) ((uint32_t)(n) << PADCTL_DSE_SHIFT) /* n=DRIVE_* */
# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */
# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
@@ -2235,25 +2241,31 @@
# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
#define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */
#define PADCTL_SPEED_MASK (3 << PADCTL_SPEED_SHIFT)
# define PADCTL_SPEED(n) ((uint32_t)(n) << PADCTL_SPEED_SHIFT) /* n=SPEED_* */
# define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */
# define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */
# define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */
#define PADCTL_ODE (1 << 11) /* Bit 11: Open Drain Enable Field */
#define PADCTL_PKE (1 << 12) /* Bit 12: Pull / Keep Enable Field */
#define PADCTL_PUE (1 << 13) /* Bit 13: Pull / Keep Select Field */
#define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */
#define PADCTL_PUS_MASK (3 << PADCTL_PUS_SHIFT)
# define PADCTL_PUS(n) ((uint32_t)(n) << PADCTL_PUS_SHIFT) /* n=PULL_* */
# define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */
# define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */
# define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */
# define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */
#define PADCTL_HYS (1 << 16) /* Bit 16: Hysteresis Enable Field */
/* Pad Group Control Registers */
/* Select Input Registers */
#endif /* CONFIG_ARCH_CHIP_IMX6_6QUAD || CONFIG_ARCH_CHIP_IMX6_6DUAL */
arch/arm/src/imx6/hardware/imx_memorymap.h
+28 -22
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,19 +16,19 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* Reference:
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual",
* Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale.
*/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/imx6/chip.h>
@@ -36,24 +36,24 @@
/* i.MX6 Virtual (mapped) Memory Map
*
* board_memorymap.h contains special mappings that are needed when a ROM
* memory map is used. It is included in this odd location because it depends
* on some the virtual address definitions provided above.
* memory map is used. It is included in this odd location because it
* depends on some the virtual address definitions provided above.
*/
#include <arch/board/board_memorymap.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Decimal configuration values may exceed 2Gb and, hence, overflow to negative
* values unless we force them to unsigned long:
/* Decimal configuration values may exceed 2Gb and, hence, overflow to
* negative values unless we force them to unsigned long:
*/
#define __CONCAT(a,b) a ## b
#define MKULONG(a) __CONCAT(a,ul)
/* Overview *************************************************************************
/* Overview *****************************************************************
*
* i.MX6 Physical (unmapped) Memory Map
* - i.MX6 System 1MB PSECTIONS
@@ -90,9 +90,9 @@
* Page table start addresses
* Base address of the interrupt vector table
*
************************************************************************************/
****************************************************************************/
/* i.MX6 Physical (unmapped) Memory Map *********************************************/
/* i.MX6 Physical (unmapped) Memory Map *************************************/
/* i.MX6 System PSECTIONS */
@@ -755,7 +755,12 @@
# define NUTTX_RAM_SIZE (NUTTX_RAM_PEND - NUTTX_RAM_PADDR)
#else /* CONFIG_IMX6_BOOT_NOR */
/* Must be CONFIG_IMX6_BOOT_OCRAM || CONFIG_IMX6_BOOT_SDRAM || CONFIG_IMX6_BOOT_SRAM */
/* Must be
* CONFIG_IMX6_BOOT_OCRAM ||
* CONFIG_IMX6_BOOT_SDRAM ||
* CONFIG_IMX6_BOOT_SRAM
*/
/* Otherwise we are running from some kind of RAM (OCRAM, SRAM, or SDRAM).
* Setup the RAM region as the NUTTX .txt, .bss, and .data region.
@@ -894,11 +899,11 @@
*
* (4GB address range / 4 KB per page ) * 4 bytes per entry = 4MB
*
* 16KB of memory is reserved hold the page table for the virtual mappings. A
* portion of this table is not accessible in the virtual address space (for
* normal operation with a one-to-one address mapping). There is this large
* hole in the physcal address space for which there will never be level 1
* mappings:
* 16KB of memory is reserved hold the page table for the virtual mappings.
* A portion of this table is not accessible in the virtual address space
* (for normal operation with a one-to-one address mapping). There is this
* large hole in the physcal address space for which there will never be
* level 1 mappings:
*
* 0x80000000-0xefffffff: Undefined (1.75 GB)
*
@@ -985,7 +990,8 @@
*
* IMX_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
* IMX_VECTOR_VSRAM - Virtual address of vector table in SRAM
* IMX_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
* IMX_VECTOR_VADDR - Virtual address of vector table
* (0x00000000 or 0xffff0000)
*/
#define VECTOR_TABLE_SIZE 0x00010000
arch/arm/src/imx6/hardware/imx_pinmux.h
+21 -16
View File
@@ -1,4 +1,4 @@
/*****************************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,35 +16,40 @@
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************************************/
****************************************************************************/
/* Reference:
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual,"
* Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale.
*/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_PINMUX_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_PINMUX_H
/*****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
*****************************************************************************************************/
****************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however,
* will use the pin selection without the numeric suffix. Additional definitions are required in the
* board.h file. For example, if UART1 RXD connects via the SD3_DATA6 pin, then the following
* definition should appear in the board.h header file for that board:
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file.
* For example, if UART1 RXD connects via the SD3_DATA6 pin, then the
* following definition should appear in the board.h header file for that
* board:
*
* #define GPIO_UART1_RX_DATA GPIO_UART1_RX_DATA_1
*
* The driver will then automatically configere to use the SD3_DATA6 pin for UART RXD.
* The driver will then automatically configere to use the SD3_DATA6 pin for
* UART RXD.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific IOMUX options such as frequency, open-drain,
* push-pull, and pull-up/down! Just the basics are defined for most pins in this file. See the
* upper imx_gpio.h and imx_iomuxc.h header files for available definitions.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific IOMUX options such as
* frequency, open-drain, push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file. See the upper imx_gpio.h and
* imx_iomuxc.h header files for available definitions.
*/
/* ARM */
@@ -661,7 +666,7 @@
#define GPIO_KEY_ROW7_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA09_INDEX))
#define GPIO_KEY_ROW7_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA0_INDEX))
/* MediaLB (MLB)*/
/* MediaLB (MLB) */
#define GPIO_MLB_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_ENET_TX_DATA1_INDEX))
#define GPIO_MLB_CLK_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO03_INDEX))
arch/arm/src/imx6/hardware/imx_src.h
+69 -41
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_src.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,28 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
/* Reference:
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual,"
* Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale.
*/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_SRC_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_SRC_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx_memorymap.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* SRC Register Offsets *****************************************************************************/
/* SRC Register Offsets *****************************************************/
#define IMX_SRC_SCR_OFFSET 0x0000 /* SRC Control Register */
#define IMX_SRC_SBMR1_OFFSET 0x0004 /* SRC Boot Mode Register 1 */
@@ -56,7 +56,7 @@
#define IMX_SRC_GPR9_OFFSET 0x0040 /* SRC General Purpose Register 9 */
#define IMX_SRC_GPR10_OFFSET 0x0044 /* SRC General Purpose Register 10 */
/* SRC Register Addresses ***************************************************************************/
/* SRC Register Addresses ***************************************************/
#define IMX_SRC_SCR (IMX_SRC_VBASE+IMX_SRC_SCR_OFFSET)
#define IMX_SRC_SBMR1 (IMX_SRC_VBASE+IMX_SRC_SBMR1_OFFSET)
@@ -75,41 +75,43 @@
#define IMX_SRC_GPR9 (IMX_SRC_VBASE+IMX_SRC_GPR9_OFFSET)
#define IMX_SRC_GPR10 (IMX_SRC_VBASE+IMX_SRC_GPR10_OFFSET)
/* SRC Register Bit Definitions *********************************************************************/
/* SRC Register Bit Definitions *********************************************/
/* SRC Control Register: Reset value 0x00000521 */
#define SRC_SCR_WARM_RESET_ENABLE (1 << 0) /* Bit 0: WARM reset enable bit */
#define SRC_SCR_SW_GPU_RST (1 << 1) /* Bit 1: Software reset for GPU */
#define SRC_SCR_SW_VPU_RST (1 << 2) /* Bit 2: Software reset for VPU */
#define SRC_SCR_SW_IPU1_RST (1 << 3) /* Bit 3: Software reset for IPU1 */
#define SRC_SCR_SW_OPEN_VG_RST (1 << 4) /* Bit 4: Software reset for open_vg */
#define SRC_SCR_WARM_RESET_ENABLE (1 << 0) /* Bit 0: WARM reset enable bit */
#define SRC_SCR_SW_GPU_RST (1 << 1) /* Bit 1: Software reset for GPU */
#define SRC_SCR_SW_VPU_RST (1 << 2) /* Bit 2: Software reset for VPU */
#define SRC_SCR_SW_IPU1_RST (1 << 3) /* Bit 3: Software reset for IPU1 */
#define SRC_SCR_SW_OPEN_VG_RST (1 << 4) /* Bit 4: Software reset for open_vg */
#define SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT (5) /* Bits 5-6: XTALI cycles before bypassing the MMDC ack */
#define SRC_SCR_WARM_RST_BYPASS_COUNT_MASK (3 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT)
# define SRC_SCR_WARM_RST_BYPASS_COUNT_NONE (0 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* Counter not used */
# define SRC_SCR_WARM_RST_BYPASS_COUNT_16 (1 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 16 XTALI cycles before WARM to COLD reset */
# define SRC_SCR_WARM_RST_BYPASS_COUNT_32 (2 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 32 XTALI cycles before WARM to COLD reset */
# define SRC_SCR_WARM_RST_BYPASS_COUNT_64 (3 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 64 XTALI cycles before WARM to COLD reset */
#define SRC_SCR_MASK_WDOG_RST_SHIFT (7) /* Bits 7-10: Mask wdog_rst_b source */
#define SRC_SCR_MASK_WDOG_RST_MASK (15 << SRC_SCR_MASK_WDOG_RST_SHIFT)
# define SRC_SCR_MASK_WDOG_RST_MASKED (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) /* wdog_rst_b is masked */
# define SRC_SCR_MASK_WDOG_RST_UNMASKED (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) /* wdog_rst_b is not masked */
#define SRC_SCR_EIM_RST (1 << 11) /* Bit 11: EIM reset is needed in order to reconfigure the eim chip select */
#define SRC_SCR_SW_IPU2_RST (1 << 12) /* Bit 12: Software reset for ipu2 */
#define SRC_SCR_CORE0_RST (1 << 13) /* Bit 13: Software reset for core0 */
#define SRC_SCR_CORE1_RST (1 << 14) /* Bit 14: Software reset for core1 */
#define SRC_SCR_CORE2_RST (1 << 15) /* Bit 15: Software reset for core2 */
#define SRC_SCR_CORE3_RST (1 << 16) /* Bit 16: Software reset for core3 */
#define SRC_SCR_CORE0_DBG_RST (1 << 17) /* Bit 17: Software reset for core0 debug */
#define SRC_SCR_CORE1_DBG_RST (1 << 18) /* Bit 18: Software reset for core1 debug */
#define SRC_SCR_CORE2_DBG_RST (1 << 19) /* Bit 19: Software reset for core2 debug */
#define SRC_SCR_CORE3_DBG_RST (1 << 20) /* Bit 20: Software reset for core3 debug */
#define SRC_SCR_CORES_DBG_RST (1 << 21) /* Bit 21: Software reset for debug of arm platform */
#define SRC_SCR_CORE1_ENABLE (1 << 22) /* Bit 22: core1 enable */
#define SRC_SCR_CORE2_ENABLE (1 << 23) /* Bit 23: core2 enable */
#define SRC_SCR_CORE3_ENABLE (1 << 24) /* Bit 24: core3 enable */
#define SRC_SCR_DBG_RST_MSK_PG (1 << 25) /* Bit 25: No debug resets after core power gating event */
/* Bits 26-31: Reserved */
#define SRC_SCR_EIM_RST (1 << 11) /* Bit 11: EIM reset is needed in order to reconfigure the eim chip select */
#define SRC_SCR_SW_IPU2_RST (1 << 12) /* Bit 12: Software reset for ipu2 */
#define SRC_SCR_CORE0_RST (1 << 13) /* Bit 13: Software reset for core0 */
#define SRC_SCR_CORE1_RST (1 << 14) /* Bit 14: Software reset for core1 */
#define SRC_SCR_CORE2_RST (1 << 15) /* Bit 15: Software reset for core2 */
#define SRC_SCR_CORE3_RST (1 << 16) /* Bit 16: Software reset for core3 */
#define SRC_SCR_CORE0_DBG_RST (1 << 17) /* Bit 17: Software reset for core0 debug */
#define SRC_SCR_CORE1_DBG_RST (1 << 18) /* Bit 18: Software reset for core1 debug */
#define SRC_SCR_CORE2_DBG_RST (1 << 19) /* Bit 19: Software reset for core2 debug */
#define SRC_SCR_CORE3_DBG_RST (1 << 20) /* Bit 20: Software reset for core3 debug */
#define SRC_SCR_CORES_DBG_RST (1 << 21) /* Bit 21: Software reset for debug of arm platform */
#define SRC_SCR_CORE1_ENABLE (1 << 22) /* Bit 22: core1 enable */
#define SRC_SCR_CORE2_ENABLE (1 << 23) /* Bit 23: core2 enable */
#define SRC_SCR_CORE3_ENABLE (1 << 24) /* Bit 24: core3 enable */
#define SRC_SCR_DBG_RST_MSK_PG (1 << 25) /* Bit 25: No debug resets after core power gating event */
/* Bits 26-31: Reserved */
/* SRC Boot Mode Register 1 */
@@ -173,15 +175,41 @@
#define SRC_SBMR2_BMOD_MASK (3 << SRC_SBMR2_BMOD_SHIFT)
/* Bits 26-31: Reserved */
/* SRC General Purpose Register 1: 32-bit PERSISTENT_ENTRY0: core0 entry function for waking-up from low power mode */
/* SRC General Purpose Register 2: 32-bit PERSISTENT_ARG0: core0 entry function argument */
/* SRC General Purpose Register 3: 32-bit PERSISTENT_ENTRY1: core1 entry function for waking-up from low power mode */
/* SRC General Purpose Register 4: 32-bit PERSISTENT_ARG1: core1 entry function argument */
/* SRC General Purpose Register 5: 32-bit PERSISTENT_ENTRY2: core2 entry function for waking-up from low power mode */
/* SRC General Purpose Register 6: 32-bit PERSISTENT_ARG2: core1 entry function argument */
/* SRC General Purpose Register 7: 32-bit PERSISTENT_ENTRY3: core3 entry function for waking-up from low power mode */
/* SRC General Purpose Register 8: 32-bit PERSISTENT_ARG3: core3 entry function argument */
/* SRC General Purpose Register 9: Reserved */
/* SRC General Purpose Register 1: 32-bit PERSISTENT_ENTRY0:
* core0 entry function for waking-up from low power mode
*/
/* SRC General Purpose Register 2: 32-bit PERSISTENT_ARG0:
* core0 entry function argument
*/
/* SRC General Purpose Register 3: 32-bit PERSISTENT_ENTRY1:
* core1 entry function for waking-up from low power mode
*/
/* SRC General Purpose Register 4: 32-bit PERSISTENT_ARG1:
* core1 entry function argument
*/
/* SRC General Purpose Register 5: 32-bit PERSISTENT_ENTRY2:
* core2 entry function for waking-up from low power mode
*/
/* SRC General Purpose Register 6: 32-bit PERSISTENT_ARG2:
* core1 entry function argument
*/
/* SRC General Purpose Register 7: 32-bit PERSISTENT_ENTRY3:
* core3 entry function for waking-up from low power mode
*/
/* SRC General Purpose Register 8: 32-bit PERSISTENT_ARG3:
* core3 entry function argument
*/
/* SRC General Purpose Register 9:
* Reserved
*/
/* SRC General Purpose Register 10 */
arch/arm/src/imx6/hardware/imx_uart.h
+14 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/hardware/imx_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,28 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* Reference:
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
* IMX6DQRM, Rev. 3, 07/2015, FreeScale.
* "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual",
* Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale.
*/
#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_UART_H
#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_UART_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* UART Register Offsets ************************************************************/
/* UART Register Offsets ****************************************************/
#define UART_RXD_OFFSET 0x0000 /* UART receiver register */
#define UART_TXD_OFFSET 0x0040 /* UART receiver register */
@@ -57,7 +57,7 @@
#define UART_UTS_OFFSET 0x00b4 /* UART test register */
#define UART_UMCR_OFFSET 0x00b8 /* UART RS-485 Mode Control Register */
/* UART Register Addresses **********************************************************/
/* UART Register Addresses **************************************************/
#define UART1_RXD (IMX_UART1_VBASE+UART_RXD_OFFSET)
#define UART1_TXD (IMX_UART1_VBASE+UART_TXD_OFFSET)
@@ -149,7 +149,7 @@
#define UART5_UTS (IMX_UART5_VBASE+UART_UTS_OFFSET)
#define UART5_UMCR (IMX_UART5_VBASE+UART_UMCR_OFFSET)
/* UART Register Bit Definitions ****************************************************/
/* UART Register Bit Definitions ********************************************/
/* UART Receiver Register */
@@ -185,6 +185,7 @@
# define UART_UCR1_ICD_8FRMS (1 << UART_UCR1_ICD_SHIFT) /* Idle for more than 8 frames */
# define UART_UCR1_ICD_16FRMS (2 << UART_UCR1_ICD_SHIFT) /* Idle for more than 16 frames */
# define UART_UCR1_ICD_32FRMS (3 << UART_UCR1_ICD_SHIFT) /* Idle for more than 32 frames */
#define UART_UCR1_IDEN (1 << 12) /* Bit 12: Idle condition detected interrupt enable */
#define UART_UCR1_TRDYEN (1 << 13) /* Bit 13: Transmitter ready interrupt enable */
#define UART_UCR1_ADBR (1 << 14) /* Bit 14: Automatic detection of baud rate */
@@ -206,6 +207,7 @@
# define UART_UCR2_RTEC_RISE (0 << UART_UCR2_RTEC_SHIFT) /* Interrupt on rising edge */
# define UART_UCR2_RTEC_FALL (1 << UART_UCR2_RTEC_SHIFT) /* Interrupt on falling edge */
# define UART_UCR2_RTEC_BOTH (2 << UART_UCR2_RTEC_SHIFT) /* Interrupt on any edge */
#define UART_UCR2_ESCEN (1 << 11) /* Bit 11: Escape enable */
#define UART_UCR2_CTS (1 << 12) /* Bit 12: Clear To Send pin */
#define UART_UCR2_CTSC (1 << 13) /* Bit 13: CTS Pin control */
@@ -264,6 +266,7 @@
# define UART_UFCR_RFDIV2 (4 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 2 */
# define UART_UFCR_RFDIV1 (5 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 1 */
# define UART_UFCR_RFDIV7 (6 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 7 */
#define UART_UFCR_TXTL_SHIFT 10 /* Bits 10-15: Transmitter Trigger Level */
#define UART_UFCR_TXTL_MASK (0x3f << UART_UFCR_TXTL_SHIFT)
# define UART_UFCR_TXTL(n) ((uint32_t)(n) << UART_UFCR_TXTL_SHIFT)
arch/arm/src/imx6/imx_boot.c
+6 -5
View File
@@ -212,8 +212,8 @@ static void imx_vectormapping(void)
* Description:
* Copy the interrupt block to its final destination. Vectors are already
* positioned at the beginning of the text region and only need to be
* copied in the case where we are using high vectors or where the beginning
* of the text region cannot be remapped to address zero.
* copied in the case where we are using high vectors or where the
* beginning of the text region cannot be remapped to address zero.
*
****************************************************************************/
@@ -232,8 +232,8 @@ static void imx_copyvectorblock(void)
imx_vectorpermissions(MMU_L2_VECTRWFLAGS);
#endif
/* Copy the vectors into OCRAM at the address that will be mapped to the vector
* address:
/* Copy the vectors into OCRAM at the address that will be mapped to the
* vector address:
*
* IMX_VECTOR_PADDR - Unmapped, physical address of vector table in OCRAM
* IMX_VECTOR_VSRAM - Virtual address of vector table in OCRAM
@@ -505,7 +505,8 @@ void arm_boot(void)
/* Now we can enable all other CPUs. The enabled CPUs will start execution
* at __cpuN_start and, after very low-level CPU initialization has been
* performed, will branch to arm_cpu_boot() (see arch/arm/src/armv7-a/smp.h)
* performed, will branch to arm_cpu_boot()
* (see arch/arm/src/armv7-a/smp.h)
*/
imx_cpu_enable();
arch/arm/src/imx6/imx_config.h
+1 -1
View File
@@ -31,7 +31,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration **********************************************************/
/* Configuration ************************************************************/
/* Is there a UART enabled? */
arch/arm/src/imx6/imx_cpuboot.c
+3 -3
View File
@@ -227,9 +227,9 @@ void imx_cpu_enable(void)
*
* Description:
* Continues the C-level initialization started by the assembly language
* __cpu[n]_start function. At a minimum, this function needs to initialize
* interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to
* issue an SGI.
* __cpu[n]_start function. At a minimum, this function needs to
* initialize interrupt handling and, perhaps, wait on WFI for
* arm_cpu_start() to issue an SGI.
*
* This function must be provided by the each ARMv7-A MCU and implement
* MCU-specific initialization logic.
arch/arm/src/imx6/imx_ecspi.c
+6 -2
View File
@@ -509,7 +509,9 @@ static int spi_performtx(struct imx_spidev_s *priv)
}
else
{
/* Yes.. The transfer is complete, disable Tx FIFO empty interrupt */
/* Yes..
* The transfer is complete, disable Tx FIFO empty interrupt
*/
regval = spi_getreg(priv, ECSPI_INTREG_OFFSET);
regval &= ~ECSPI_INT_TE;
@@ -1295,7 +1297,9 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port)
#endif
nxsem_init(&priv->exclsem, 0, 1);
/* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */
/* Initialize control register:
* min frequency, ignore ready, master mode, mode=0, 8-bit
*/
spi_putreg(priv, ECSPI_CONREG_OFFSET,
ECSPI_CONREG_DIV512 | /* Lowest frequency */
arch/arm/src/imx6/imx_ecspi.h
+44 -36
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/imx_ecspi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_IMX6_ECSPI_H
#define __ARCH_ARM_IMX6_ECSPI_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -33,13 +33,13 @@
#include "hardware/imx_ecspi.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@@ -50,13 +50,13 @@ extern "C"
#define EXTERN extern
#endif /* __cplusplus */
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
struct spi_dev_s; /* Forward reference */
/************************************************************************************
/****************************************************************************
* Name: imx_spibus_initialize
*
* Description:
@@ -65,7 +65,7 @@ struct spi_dev_s; /* Forward reference */
* prior to calling this function. Specifically: GPIOs should have
* been configured for output, and all chip selects disabled.
*
* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However,
* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However,
* If multiple devices on on the bus, then multiple chip selects will be
* required. Therefore, all GPIO chip management is deferred to board-
* specific logic.
@@ -76,33 +76,37 @@ struct spi_dev_s; /* Forward reference */
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
************************************************************************************/
****************************************************************************/
FAR struct spi_dev_s *imx_spibus_initialize(int port);
/************************************************************************************
* The external functions, imx_spiselect, imx_spistatus, and imx_cmddata must be
* provided by board-specific logic. These are implementations of the select and
* status methods of the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including imx_spibus_initialize()) are
* provided by common logic. To use this common SPI logic on your board:
/****************************************************************************
* The external functions, imx_spiselect, imx_spistatus, and imx_cmddata must
* be provided by board-specific logic. These are implementations of the
* select and status methods of the SPI interface defined by struct spi_ops_s
* (see include/nuttx/spi/spi.h). All other methods (including
* imx_spibus_initialize()) are provided by common logic.
* To use this common SPI logic on your board:
*
* 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific
* logic. This function will perform chip selection and status operations using
* GPIOs in the way your board is configured.
* 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the
* imx_spicmddata() function in your board-specific logic. This function will
* perform cmd/data selection operations using GPIOs in the way your board is
* configured.
* 3. Add a call to imx_spibus_initialize() in your low level initialization logic
* 4. The handle returned by imx_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(),
* for example, will bind the SPI driver to the SPI MMC/SD driver).
* 1. Provide imx_spiselect() and imx_spistatus() functions in your
* board-specific logic. This function will perform chip selection and
* status operations using GPIOs in the way your board is configured.
* 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide
* the imx_spicmddata() function in your board-specific logic. This
* function will perform cmd/data selection operations using GPIOs in
* the way your board is configured.
* 3. Add a call to imx_spibus_initialize() in your low level
* initialization logic
* 4. The handle returned by imx_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_IMX6_ECSPI1
void imx_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
void imx_spi1select(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t imx_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
@@ -110,7 +114,8 @@ int imx_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_IMX6_ECSPI2
void imx_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
void imx_spi2select(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t imx_spi2status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
@@ -118,7 +123,8 @@ int imx_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_IMX6_ECSPI3
void imx_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
void imx_spi3select(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t imx_spi3status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
@@ -126,7 +132,8 @@ int imx_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_IMX6_ECSPI4
void imx_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
void imx_spi4select(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t imx_spi4status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
@@ -134,7 +141,8 @@ int imx_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_IMX6_ECSPI5
void imx_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
void imx_spi5select(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t imx_spi5status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int imx_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
arch/arm/src/imx6/imx_enet.h
+18 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/imx_enet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX6_IMX_ENET_H
#define __ARCH_ARM_SRC_IMX6_IMX_ENET_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,17 +31,17 @@
#ifdef CONFIG_IMX_ENET
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Definitions for use with imx_phy_boardinitialize */
#define EMAC_INTF 0
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -54,7 +54,7 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Function: up_netinitialize
*
* Description:
@@ -72,19 +72,20 @@ extern "C"
* Assumptions:
* Called very early in the initialization sequence.
*
************************************************************************************/
****************************************************************************/
void up_netinitialize(void);
/************************************************************************************
/****************************************************************************
* Function: imx_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can be
* used. This may include such things as configuring GPIOs, resetting the PHY,
* etc. If CONFIG_IMX_ENET_PHYINIT is defined in the configuration then the
* board specific logic must provide imx_phyinitialize(); The i.MX RT Ethernet
* driver will call this function one time before it first uses the PHY.
* Some boards require specialized initialization of the PHY before it can
* be used. This may include such things as configuring GPIOs, resetting
* the PHY, etc. If CONFIG_IMX_ENET_PHYINIT is defined in the
* configuration then the board specific logic must provide
* imx_phyinitialize(); The i.MX RT Ethernet driver will call this
* function one time before it first uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
@@ -92,7 +93,7 @@ void up_netinitialize(void);
* Returned Value:
* OK on success; Negated errno on failure.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_IMX_ENET_PHYINIT
int imx_phy_boardinitialize(int intf);
arch/arm/src/imx6/imx_gpio.c
+5 -5
View File
@@ -318,7 +318,7 @@ static const uint8_t g_gpio7_padmux[IMX_GPIO_NPINS] =
IMX_PADMUX_INVALID, /* GPIO6 Pin 31 */
};
static FAR const uint8_t *g_gpio_padmux[IMX_GPIO_NPORTS+1] =
static FAR const uint8_t *g_gpio_padmux[IMX_GPIO_NPORTS + 1] =
{
g_gpio1_padmux, /* GPIO1 */
g_gpio2_padmux, /* GPIO2 */
@@ -559,13 +559,13 @@ int imx_config_gpio(gpio_pinset_t pinset)
return ret;
}
/************************************************************************************
/****************************************************************************
* Name: imx_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
****************************************************************************/
void imx_gpio_write(gpio_pinset_t pinset, bool value)
{
@@ -578,13 +578,13 @@ void imx_gpio_write(gpio_pinset_t pinset, bool value)
leave_critical_section(flags);
}
/************************************************************************************
/****************************************************************************
* Name: imx_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
****************************************************************************/
bool imx_gpio_read(gpio_pinset_t pinset)
{
arch/arm/src/imx6/imx_gpio.h
+33 -30
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/imx_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX6_IMX_GPIO_H
#define __ARCH_ARM_SRC_IMX6_IMX_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -32,9 +32,10 @@
#include "hardware/imx_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* 32-bit Encoding:
*
* ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM
@@ -154,17 +155,17 @@
#define GPIO_IOMUX_SHIFT (0) /* Bits 0-15: IOMUX pin configuration */
#define GPIO_IOMUX_MASK (0xffff << GPIO_IOMUX_SHIFT)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/* The smallest integer type that can hold the GPIO encoding */
typedef uint32_t gpio_pinset_t;
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -175,17 +176,18 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: imx_gpioirq_initialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for GPIO pins.
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_IMX6_GPIO_IRQ
void imx_gpioirq_initialize(void);
@@ -193,43 +195,43 @@ void imx_gpioirq_initialize(void);
# define imx_gpio_irqinitialize()
#endif
/************************************************************************************
/****************************************************************************
* Name: imx_config_gpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
************************************************************************************/
****************************************************************************/
int imx_config_gpio(gpio_pinset_t pinset);
/************************************************************************************
/****************************************************************************
* Name: imx_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
****************************************************************************/
void imx_gpio_write(gpio_pinset_t pinset, bool value);
/************************************************************************************
/****************************************************************************
* Name: imx_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
****************************************************************************/
bool imx_gpio_read(gpio_pinset_t pinset);
/************************************************************************************
/****************************************************************************
* Name: imx_gpioirq
*
* Description:
* Configure an interrupt for the specified GPIO pin.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_IMX6_GPIO_IRQ
void imx_gpioirq(gpio_pinset_t pinset);
@@ -237,13 +239,13 @@ void imx_gpioirq(gpio_pinset_t pinset);
# define imx_gpioirq(pinset)
#endif
/************************************************************************************
/****************************************************************************
* Name: imx_gpioirq_enable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_IMX6_GPIO_IRQ
void imx_gpioirq_enable(int irq);
@@ -251,13 +253,13 @@ void imx_gpioirq_enable(int irq);
# define imx_gpioirq_enable(irq)
#endif
/************************************************************************************
/****************************************************************************
* Name: imx_gpioirq_disable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_IMX6_GPIO_IRQ
void imx_gpioirq_disable(int irq);
@@ -265,13 +267,14 @@ void imx_gpioirq_disable(int irq);
# define imx_gpioirq_disable(irq)
#endif
/************************************************************************************
/****************************************************************************
* Function: imx_dump_gpio
*
* Description:
* Dump all GPIO registers associated with the base address of the provided pinset.
* Dump all GPIO registers associated with the base address of the provided
* pinset.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
int imx_dump_gpio(uint32_t pinset, const char *msg);
arch/arm/src/imx6/imx_iomuxc.c
+114 -57
View File
@@ -35,6 +35,7 @@
/****************************************************************************
* Private Data
****************************************************************************/
/* This table is indexed by the Pad Mux register index and provides the index
* to the corresponding Pad Control register.
*
@@ -47,7 +48,9 @@
static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] =
{
/* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */
/* The first mappings are simple 1-to-1 mappings.
* This may be a little wasteful
*/
IMX_PADCTL_SD2_DATA1_INDEX, /* IMX_PADMUX_SD2_DATA1_INDEX */
IMX_PADCTL_SD2_DATA2_INDEX, /* IMX_PADMUX_SD2_DATA2_INDEX */
@@ -139,7 +142,6 @@ static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] =
IMX_PADCTL_DISP0_DATA14_INDEX, /* IMX_PADMUX_DISP0_DATA14_INDEX */
IMX_PADCTL_DISP0_DATA15_INDEX, /* IMX_PADMUX_DISP0_DATA15_INDEX */
IMX_PADCTL_DISP0_DATA16_INDEX, /* IMX_PADMUX_DISP0_DATA16_INDEX */
IMX_PADCTL_DISP0_DATA17_INDEX, /* IMX_PADMUX_DISP0_DATA17_INDEX */
IMX_PADCTL_DISP0_DATA18_INDEX, /* IMX_PADMUX_DISP0_DATA18_INDEX */
@@ -159,55 +161,103 @@ static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] =
IMX_PADCTL_ENET_TX_DATA0_INDEX, /* IMX_PADMUX_ENET_TX_DATA0_INDEX */
IMX_PADCTL_ENET_MDC_INDEX, /* IMX_PADMUX_ENET_MDC_INDEX */
/* There is then a group of Pad Control registers with no Pad Mux register counterpart */
/* There is then a group of Pad Control registers with no Pad Mux register
* counterpart
*/
/* IMX_PADCTL_DRAM_SDQS5_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM5_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM4_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS4_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS3_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM3_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS2_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM2_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR00_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR01_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR02_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR03_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR04_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR05_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR06_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR07_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR08_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR09_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR10_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR11_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR12_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR13_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR14_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR15_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_CAS_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_CS0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_CS1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_RAS_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_RESET_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDBA0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDBA1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDCLK0_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDBA2_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDCKE0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDCLK1_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDCKE1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ODT0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ODT1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDWE_B_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS0_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS1_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS6_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM6_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS7_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM7_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS5_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM5_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM4_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS4_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS3_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM3_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS2_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM2_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR00_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR01_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR02_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR03_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR04_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR05_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR06_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR07_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR08_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR09_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR10_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR11_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR12_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR13_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR14_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ADDR15_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_CAS_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_CS0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_CS1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_RAS_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_RESET_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDBA0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDBA1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDCLK0_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDBA2_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDCKE0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDCLK1_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDCKE1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ODT0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_ODT1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDWE_B_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS0_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM0_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS1_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM1_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS6_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM6_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_SDQS7_P_INDEX - No counterpart */
/* IMX_PADCTL_DRAM_DQM7_INDEX - No counterpart */
/* The mapping is again 1-to-1 with an offset for the above registers that
* have no Pad Mux register counterpart.
@@ -258,14 +308,21 @@ static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] =
IMX_PADCTL_CSI0_DATA18_INDEX, /* IMX_PADMUX_CSI0_DATA18_INDEX */
IMX_PADCTL_CSI0_DATA19_INDEX, /* IMX_PADMUX_CSI0_DATA19_INDEX */
/* There is a second group of Pad Control registers with no Pad Mux register counterpart */
/* There is a second group of Pad Control registers with no Pad Mux
* register counterpart
*/
/* IMX_PADCTL_JTAG_TMS_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_MOD_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TRSTB_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TDI_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TCK_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TDO_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TMS_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_MOD_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TRSTB_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TDI_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TCK_INDEX - No counterpart */
/* IMX_PADCTL_JTAG_TDO_INDEX - No counterpart */
/* The mapping is again 1-to-1 with an offset for the above registers that
* have no Pad Mux register counterpart.
arch/arm/src/imx6/imx_iomuxc.h
+2 -1
View File
@@ -34,6 +34,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* 16-bit Encoding:
*
* .... RRRR ODDD LSST
@@ -121,7 +122,7 @@
* Public Types
****************************************************************************/
/* The smallest integer type that can hold the IOMUX encoding */
/* The smallest integer type that can hold the IOMUX encoding */
typedef uint16_t iomux_pinset_t;
arch/arm/src/imx6/imx_lowputc.c
+25 -18
View File
@@ -46,6 +46,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifdef IMX_HAVE_UART_CONSOLE
@@ -83,6 +84,7 @@
#endif
/* Clocking *****************************************************************/
/* the UART module receives two clocks, a peripheral_clock (ipg_clk) and the
* module_clock (ipg_perclk). The peripheral_clock is used as write clock
* of the TxFIFO, read clock of the RxFIFO and synchronization of the modem
@@ -280,13 +282,13 @@ void imx_lowsetup(void)
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
}
/************************************************************************************
/****************************************************************************
* Name: imx_uart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
************************************************************************************/
****************************************************************************/
#ifdef IMX_HAVE_UART
int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config)
@@ -400,7 +402,7 @@ int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config)
*/
tmp = ((uint64_t)refclk << (16 - 4)) / config->baud;
DEBUGASSERT(tmp < 0x0000000100000000LL);
DEBUGASSERT(tmp < 0x0000000100000000ll);
ratio = (b16_t)tmp;
/* Pick a scale factor that gives us about 14 bits of accuracy.
@@ -559,26 +561,29 @@ int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config)
}
#endif /* IMX_HAVE_UART */
/************************************************************************************
/****************************************************************************
* Name: imx_lowputc
*
* Description:
* Output a byte with as few system dependencies as possible. This will even work
* BEFORE the console is initialized if we are booting from U-Boot (and the same
* UART is used for the console, of course.)
* Output a byte with as few system dependencies as possible. This will
* even work BEFORE the console is initialized if we are booting from
* U-Boot (and the same UART is used for the console, of course.)
*
************************************************************************************/
****************************************************************************/
#if defined(IMX_HAVE_UART) && defined(CONFIG_DEBUG_FEATURES)
void imx_lowputc(int ch)
{
/* Poll the TX fifo trigger level bit of the UART status register. When the TXFE
* bit is non-zero, the TX Buffer FIFO is empty.
/* Poll the TX fifo trigger level bit of the UART status register. When the
* TXFE bit is non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & UART_USR2_TXFE) == 0);
while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) &
UART_USR2_TXFE) == 0);
/* If the character to output is a newline, then pre-pend a carriage return */
/* If the character to output is a newline, then pre-pend a carriage
* return
*/
if (ch == '\n')
{
@@ -586,21 +591,23 @@ void imx_lowputc(int ch)
putreg32((uint32_t)'\r', IMX_CONSOLE_VBASE + UART_TXD_OFFSET);
/* Wait for the tranmsit register to be emptied. When the TXFE bit is non-zero,
* the TX Buffer FIFO is empty.
/* Wait for the tranmsit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & UART_USR2_TXFE) == 0);
while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) &
UART_USR2_TXFE) == 0);
}
/* Send the character by writing it into the UART_TXD register. */
putreg32((uint32_t)ch, IMX_CONSOLE_VBASE + UART_TXD_OFFSET);
/* Wait for the tranmsit register to be emptied. When the TXFE bit is non-zero,
* the TX Buffer FIFO is empty.
/* Wait for the tranmsit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & UART_USR2_TXFE) == 0);
while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) &
UART_USR2_TXFE) == 0);
}
#endif
arch/arm/src/imx6/imx_lowputc.h
+9 -8
View File
@@ -68,27 +68,28 @@ struct uart_config_s
void imx_lowsetup(void);
/************************************************************************************
/****************************************************************************
* Name: imx_uart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
************************************************************************************/
****************************************************************************/
#ifdef IMX_HAVE_UART
int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config);
int imx_uart_configure(uint32_t base,
FAR const struct uart_config_s *config);
#endif
/************************************************************************************
/****************************************************************************
* Name: imx_lowputc
*
* Description:
* Output a byte with as few system dependencies as possible. This will even work
* BEFORE the console is initialized if we are booting from U-Boot (and the same
* UART is used for the console, of course.)
* Output a byte with as few system dependencies as possible.
* This will even work BEFORE the console is initialized if we are booting
* from U-Boot (and the same UART is used for the console, of course.)
*
************************************************************************************/
****************************************************************************/
#if defined(IMX_HAVE_UART) && defined(CONFIG_DEBUG_FEATURES)
void imx_lowputc(int ch);
arch/arm/src/imx6/imx_memorymap.c
+20 -16
View File
@@ -59,10 +59,10 @@ const struct section_mapping_s g_section_mapping[] =
* reset, and until the Remap command is performed, the OCRAM is accessible
* at address 0x0090 0000.
*
* If we are executing from external SDRAM, then a secondary bootloader must
* have loaded us into SDRAM. In this case, simply set the VBAR register
* to the address of the vector table (not necessary at the beginning
* or SDRAM).
* If we are executing from external SDRAM, then a secondary bootloader
* must have loaded us into SDRAM. In this case, simply set the VBAR
* register to the address of the vector table (not necessary at the
* beginning or SDRAM).
*/
{ IMX_ROMCP_PSECTION, IMX_ROMCP_VSECTION, /* Boot ROM (ROMCP) */
@@ -118,18 +118,19 @@ const struct section_mapping_s g_section_mapping[] =
#endif
/* i.MX6 External SDRAM Memory. The SDRAM is not usable until it has been
* initialized. If we are running out of SDRAM now, we can assume that some
* second level boot loader has properly configured SRAM for us. In that
* case, we set the MMU flags for the final, fully cache-able state.
* initialized. If we are running out of SDRAM now, we can assume that
* some second level boot loader has properly configured SRAM for us.
* In that case, we set the MMU flags for the final, fully cache-able
* state.
*
* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
* need not be repeated here.
*
* If we are running from OCRAM or NOR flash, then we will need to configure
* the SDRAM ourselves. In this case, we set the MMU flags to the strongly
* ordered, non-cacheable state. We need this direct access to SDRAM in
* order to configure it. Once SDRAM has been initialized, it will be re-
* configured in its final state.
* If we are running from OCRAM or NOR flash, then we will need to
* configure the SDRAM ourselves. In this case, we set the MMU flags to
* the strongly ordered, non-cacheable state. We need this direct access
* to SDRAM in order to configure it. Once SDRAM has been initialized, it
* will be re- configured in its final state.
*/
#ifdef NEED_SDRAM_MAPPING
@@ -145,9 +146,9 @@ const struct section_mapping_s g_section_mapping[] =
/* LCDC Framebuffer. This entry reprograms a part of one of the above
* regions, making it non-cacheable and non-buffereable.
*
* If SDRAM will be reconfigured, then we will defer setup of the framebuffer
* until after the SDRAM remapping (since the framebuffer problem resides) in
* SDRAM.
* If SDRAM will be reconfigured, then we will defer setup of the
* framebuffer until after the SDRAM remapping (since the framebuffer
* problem resides) in SDRAM.
*/
#if defined(CONFIG_IMX6_LCDC) && !defined(NEED_SDRAM_REMAPPING)
@@ -192,7 +193,6 @@ const struct section_mapping_s g_operational_mapping[] =
MMU_IOFLAGS, IMX6_LCDC_FBNSECTIONS
},
#endif
};
/* The number of entries in the operational mapping table */
@@ -203,3 +203,7 @@ const struct section_mapping_s g_operational_mapping[] =
const size_t g_num_opmappings = NREMAPPINGS;
#endif /* NEED_SDRAM_REMAPPING */
/****************************************************************************
* Public Functions
****************************************************************************/
arch/arm/src/imx6/imx_memorymap.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imx6/imx_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX6_IMX_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMX6_IMX_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/imx6/chip.h>
#include "mmu.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* The vectors are, by default, positioned at the beginning of the text
* section. Under what conditions do we have to remap these vectors?
@@ -48,8 +48,8 @@
* is required because the vectors are position at the beginning of the
* boot memory at link time and no additional MMU mapping required.
*
* 2) We are not using a ROM page table. We cannot set any custom mappings in
* the case and the build must conform to the ROM page table properties
* 2) We are not using a ROM page table. We cannot set any custom mappings
* in the case and the build must conform to the ROM page table properties
*/
#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_ARCH_ROMPGTABLE)
@@ -74,11 +74,11 @@
# define NEED_SDRAM_REMAPPING 1
#endif
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/* This table describes how to map a set of 1Mb pages to space the physical
/* This table describes how to map a set of 1Mb pages to space the physical
* address space of the i.MX6.
*/
arch/arm/src/imx6/imx_timerisr.c
+3 -1
View File
@@ -38,7 +38,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The Peripheral Clock (ipg_clk) is selected as the GPT clock source. NOTE
/* The Peripheral Clock (ipg_clk) is selected as the GPT clock source.
* NOTE
* that the ipg_clk may be turned off in low power modes, stopping the timer
* which is probably what you want.
*
arch/arm/src/imxrt/chip.h
+19 -18
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware files
* should then include this file for the proper setup.
/* Include the memory map and the chip definitions file.
* Other chip hardware files should then include this file for the proper
* setup.
*/
#include <arch/irq.h>
#include <arch/imxrt/chip.h>
#include "hardware/imxrt_memorymap.h"
/* If the common ARMv7-M vector handling logic is used, then it expects the following
* definition in this file that provides the number of supported vectors external
* interrupts.
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported
* vectors external interrupts.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS IMXRT_IRQ_NEXTINT
@@ -47,20 +48,20 @@
#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */
#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_H */
arch/arm/src/imxrt/hardware/imxrt_adc.h
+13 -10
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define IMXRT_ADC_HC0_OFFSET 0x0000 /* Control register for hardware triggers */
#define IMXRT_ADC_HC1_OFFSET 0x0004 /* Control register for hardware triggers */
@@ -58,7 +58,7 @@
#define IMXRT_ADC_OFS_OFFSET 0x0054 /* Offset correction value register */
#define IMXRT_ADC_CAL_OFFSET 0x0058 /* Calibration value register */
/* Register addresses ***************************************************************/
/* Register addresses *******************************************************/
/* ADC1 Register Addresses */
@@ -112,7 +112,7 @@
#define IMXRT_ADC2_OFS (IMXRT_ADC2_BASE + IMXRT_ADC_OFS_OFFSET) /* ADC2 Offset correction value register */
#define IMXRT_ADC2_CAL (IMXRT_ADC2_BASE + IMXRT_ADC_CAL_OFFSET) /* ADC2 Calibration value register */
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Control register for hardware & SW triggers for n=0,1..7 */
@@ -139,7 +139,10 @@
# define ADC_HC_ADCH_VREFSH (25 << ADC_HC_ADCH_SHIFT) /* internal channel, for ADC self-test, hard connected to VRH internally */
# define ADC_HC_ADCH_DIS (31 << ADC_HC_ADCH_SHIFT) /* */
/* Bits: 5-6 Reserved */
/* Bits: 5-6
* Reserved
*/
#define ADC_HC_AIEN (1 << 7) /* Bit: 7 Conversion Complete Interrupt Enable/Disable Control */
/* Bits: 8-31 Reserved */
arch/arm/src/imxrt/hardware/imxrt_ccm.h
+4 -4
View File
@@ -1,4 +1,4 @@
/*****************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_ccm.h
*
* Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
@@ -33,14 +33,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_CCM_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_CCM_H
/*****************************************************************************
/****************************************************************************
* Included Files
*****************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
arch/arm/src/imxrt/hardware/imxrt_daisy.h
+8 -8
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_daisy.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,29 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DAISY_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DAISY_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: imxrt_daisy_select
*
* Description:
* Initialize logic to support a daisy chain input selection for GPIO pins.
*
************************************************************************************/
****************************************************************************/
void imxrt_daisy_select(unsigned int index, unsigned int alt);
arch/arm/src/imxrt/hardware/imxrt_dcdc.h
+9 -9
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_dcdc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -31,37 +31,37 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DCDC_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DCDC_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register offsets *********************************************************************************/
/* Register offsets *********************************************************/
#define IMXRT_DCDC_REG0_OFFSET 0x0000 /* DCDC Register 0 */
#define IMXRT_DCDC_REG1_OFFSET 0x0004 /* DCDC Register 1 */
#define IMXRT_DCDC_REG2_OFFSET 0x0008 /* DCDC Register 2 */
#define IMXRT_DCDC_REG3_OFFSET 0x000c /* DCDC Register 3 */
/* Register addresses *******************************************************************************/
/* Register addresses *******************************************************/
#define IMXRT_DCDC_REG0 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG0_OFFSET)
#define IMXRT_DCDC_REG1 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG1_OFFSET)
#define IMXRT_DCDC_REG2 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG2_OFFSET)
#define IMXRT_DCDC_REG3 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG3_OFFSET)
/* Register bit definitions *************************************************************************/
/* Register bit definitions *************************************************/
/* Register 0 */
arch/arm/src/imxrt/hardware/imxrt_edma.h
+35 -15
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_edma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_EDMA_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_EDMA_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
#define IMXRT_EDMA_NCHANNELS 32
/* eDMA Register Offsets ****************************************************************************/
/* eDMA Register Offsets ****************************************************/
#define IMXRT_EDMA_CR_OFFSET 0x0000 /* Control */
#define IMXRT_EDMA_ES_OFFSET 0x0004 /* Error Status */
@@ -499,7 +499,7 @@
#define IMXRT_EDMA_TCD31_CSR_OFFSET 0x13fc /* TCD Control and Status */
#define IMXRT_EDMA_TCD31_BITER_ELINK_OFFSET 0x13fe /* TCD Beginning Minor Loop Link, Major Loop Count */
/* eDMA Register Addresses **************************************************************************/
/* eDMA Register Addresses **************************************************/
#define IMXRT_EDMA_CR (IMXRT_EDMA_BASE + IMXRT_EDMA_CR_OFFSET)
#define IMXRT_EDMA_ES (IMXRT_EDMA_BASE + IMXRT_EDMA_ES_OFFSET)
@@ -952,9 +952,10 @@
#define IMXRT_EDMA_TCD31_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_CSR_OFFSET)
#define IMXRT_EDMA_TCD31_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_BITER_ELINK_OFFSET)
/* eDMA Bit-Field Definitions ***********************************************************************/
/* eDMA Bit-Field Definitions ***********************************************/
/* Control */
/* Bit 0: Reserved */
#define EDMA_CR_EDBG (1 << 1) /* Bit 1: Enable Debug */
#define EDMA_CR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration */
@@ -1085,10 +1086,12 @@
#define EDMA_HRS(n) ((uint32_t)1 << (n)) /* Bit n: Hardware Request Status
* Channel n */
/* Enable Asynchronous Request in Stop */
#define EDMA_EARS(n) ((uint32_t)1 << (n)) /* Bit n: Enable asynchronous DMA
* request in stop mode for channel n */
/* Channel n Priority */
#define EDMA_DCHPRI_CHPRI_SHIFT (0) /* Bits 0-3: Channel n Arbitration Priority */
@@ -1101,6 +1104,7 @@
#define EDMA_DCHPRI_ECP (1 << 7) /* Bit 7: Enable Channel Preemption */
/* TCD Source Address (32-bit address) */
/* TCD Signed Source Address Offset (16-bit offset) */
/* TCD Transfer Attributes */
@@ -1119,6 +1123,7 @@
# define EDMA_TCD_ATTR_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */
# define EDMA_TCD_ATTR_DSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 64-bit */
# define EDMA_TCD_ATTR_DSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-byte burst */
#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo */
#define EDMA_TCD_ATTR_DMOD_MASK (31 << EDMA_TCD_ATTR_DMOD_SHIFT)
# define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT)
@@ -1130,14 +1135,17 @@
# define EDMA_TCD_ATTR_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
# define EDMA_TCD_ATTR_SSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
# define EDMA_TCD_ATTR_SSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte burst */
#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo */
#define EDMA_TCD_ATTR_SMOD_MASK (31 << EDMA_TCD_ATTR_SMOD_SHIFT)
# define EDMA_TCD_ATTR_SMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SMOD_SHIFT)
/* TCD Signed Minor Loop Offset / Byte Count */
/* Minor Byte Count (Minor Loop Mapping Disabled -- 32-bit byte count) */
/* TCD Signed Minor Loop Offset / Byte Count */
/* Minor Byte Count (Minor Loop Mapping Enabled, offset disabled) */
#define EDMA_TCD_NBYTES_ML_NBYTES_SHIFT (0) /* Bits 0-29: Minor Byte Transfer Count */
@@ -1147,6 +1155,7 @@
#define EDMA_TCD_NBYTES_ML_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */
/* TCD Signed Minor Loop Offset / Byte Count */
/* Minor Byte Count (Minor Loop Mapping Enabled, offset enabled) */
#define EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT (0) /* Bits 0-9: Minor Byte Transfer Count */
@@ -1159,7 +1168,9 @@
#define EDMA_TCD_NBYTES_MLOFF_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */
/* TCD Last Source Address Adjustment (32-bit address adjustment) */
/* TCD Destination Address (32-bit address) */
/* TCD Signed Destination Address Offset (32-bit signed address offset) */
/* TCD Current Minor Loop Link, Major Loop Count (Channel linking disabled) */
@@ -1182,7 +1193,9 @@
#define EDMA_TCD_CITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
* on minor-loop complete */
/* TCD Last Destination Address Adjustment/Scatter Gather Address (32-bit address) */
/* TCD Last Destination Address Adjustment/Scatter Gather Address
* (32-bit address)
*/
/* TCD Control and Status */
@@ -1209,7 +1222,9 @@
# define EDMA_TCD_CSR_BWC_8CYCLES (3 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8
* cycles after each R/W */
/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking disabled) */
/* TCD Beginning Minor Loop Link, Major Loop Count
* (Channel linking disabled)
*/
#define EDMA_TCD_BITER_BITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */
#define EDMA_TCD_BITER_BITER_MASK (0x7fff << EDMA_TCD_BITER_BITER_SHIFT)
@@ -1217,7 +1232,9 @@
#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
* on minor-loop complete */
/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking enabled) */
/* TCD Beginning Minor Loop Link, Major Loop Count
* (Channel linking enabled)
*/
#define EDMA_TCD_BITER_ELINK_BITER_SHIFT (0) /* Bit 0-8: Current major iteration count */
#define EDMA_TCD_BITER_ELINK_BITER_MASK (0x1ff << EDMA_TCD_BITER_ELINK_BITER_SHIFT)
@@ -1225,15 +1242,18 @@
#define EDMA_TCD_BITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-13: Link Channel Number */
#define EDMA_TCD_BITER_ELINK_LINKCH_MASK (31 << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT)
# define EDMA_TCD_BITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT)
/* Bit 14: Reserved */
#define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
* on minor-loop complete */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/* In-memory representation of the 32-byte Transfer Control Descriptor (TCD) */
/* In-memory representation of
* the 32-byte Transfer Control Descriptor (TCD)
*/
struct imxrt_edmatcd_s
{

Some files were not shown because too many files have changed in this diff Show More