diff --git a/arch/arm/src/imx1/chip.h b/arch/arm/src/imx1/chip.h index 38ed5abcea6..ce028cdb87f 100644 --- a/arch/arm/src/imx1/chip.h +++ b/arch/arm/src/imx1/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_CHIP_H #define __ARCH_ARM_IMX_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include "imx_memorymap.h" #include "imx_system.h" @@ -39,12 +39,12 @@ #include "imx_eim.h" #include "imx_aitc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_CHIP_H */ diff --git a/arch/arm/src/imx1/imx_aitc.h b/arch/arm/src/imx1/imx_aitc.h index 6264c1d694c..7409f8847d8 100644 --- a/arch/arm/src/imx1/imx_aitc.h +++ b/arch/arm/src/imx1/imx_aitc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_aitc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_AITC_H #define __ARCH_ARM_IMX_AITC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* AITC Register Offsets ************************************************************/ +/* AITC Register Offsets ****************************************************/ #define AITC_INTCNTL_OFFSET 0x0000 /* Interrupt Control Register */ #define AITC_NIMASK_OFFSET 0x0004 /* Normal Interrupt Mask Register */ @@ -59,7 +59,7 @@ #define AITC_FIPNDH_OFFSET 0x0060 #define AITC_FIPNDL_OFFSET 0x0064 -/* AITC Register Addresses **********************************************************/ +/* AITC Register Addresses **************************************************/ #define IMX_AITC_INTCNTL (IMX_AITC_VBASE + AITC_INTCNTL_OFFSET) #define IMX_AITC_NIMASK (IMX_AITC_VBASE + AITC_NIMASK_OFFSET) @@ -89,16 +89,15 @@ #define IMX_AITC_FIPNDH (IMX_AITC_VBASE + AITC_FIPNDH_OFFSET) #define IMX_AITC_FIPNDL (IMX_AITC_VBASE + AITC_FIPNDL_OFFSET) -/* AITC Register Bit Definitions ****************************************************/ - +/* AITC Register Bit Definitions ********************************************/ #define AITC_NIVECSR_NIPRILVL_SHIFT 0 /* Bits 15–0: Priority of highest priority interrupt */ #define AITC_NIVECSR_NIPRILVL_MASK (0x0000ffff << AITC_NIVECSR_NIPRILVL_SHIFT); #define AITC_NIVECSR_NIVECTOR_SHIFT 16 /* Bits 31–16: Vector index of highest priority interrupt */ #define AITC_NIVECSR_NIVECTOR_MASK (0x0000ffff << AITC_NIVECSR_NIVECTOR_SHIFT); -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_AITC_H */ diff --git a/arch/arm/src/imx1/imx_allocateheap.c b/arch/arm/src/imx1/imx_allocateheap.c index b12c67683bf..d9fbfe7e5fb 100644 --- a/arch/arm/src/imx1/imx_allocateheap.c +++ b/arch/arm/src/imx1/imx_allocateheap.c @@ -75,8 +75,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { - /* If a bootloader that copies us to DRAM, but not to the beginning of DRAM, - * then recover that memory by adding another memory region. + /* If a bootloader that copies us to DRAM, but not to the beginning of + * DRAM, then recover that memory by adding another memory region. */ #if !defined(CONFIG_BOOT_RUNFROMFLASH) && !defined(CONFIG_BOOT_COPYTORAM) diff --git a/arch/arm/src/imx1/imx_boot.c b/arch/arm/src/imx1/imx_boot.c index c097d025db0..7b39f4b061d 100644 --- a/arch/arm/src/imx1/imx_boot.c +++ b/arch/arm/src/imx1/imx_boot.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_boot.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -31,13 +31,13 @@ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ struct section_mapping_s { @@ -47,16 +47,16 @@ struct section_mapping_s uint32_t nsections; /* Number of mappings in the region */ }; -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ extern uint32_t _vector_start; /* Beginning of vector block */ extern uint32_t _vector_end; /* End+1 of vector block */ -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ /* Mapping of the external memory regions will probably have to be made board * specific. @@ -82,26 +82,28 @@ static const struct section_mapping_s section_mapping[] = #define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s)) -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/* All i.MX architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. +/* All i.MX architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. */ void imx_board_initialize(void); -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: up_setlevel1entry - ************************************************************************************/ + ****************************************************************************/ -static inline void up_setlevel1entry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags) +static inline void up_setlevel1entry(uint32_t paddr, + uint32_t vaddr, uint32_t mmuflags) { uint32_t *pgtable = (uint32_t *)PGTABLE_BASE_VADDR; uint32_t index = vaddr >> 20; @@ -111,13 +113,14 @@ static inline void up_setlevel1entry(uint32_t paddr, uint32_t vaddr, uint32_t mm pgtable[index] = (paddr | mmuflags); } -/************************************************************************************ +/**************************************************************************** * Name: up_setupmappings - ************************************************************************************/ + ****************************************************************************/ static void up_setupmappings(void) { - int i, j; + int i; + int j; for (i = 0; i < NMAPPINGS; i++) { @@ -134,30 +137,34 @@ static void up_setupmappings(void) } } -/************************************************************************************ +/**************************************************************************** * Name: up_copyvectorblock - ************************************************************************************/ + ****************************************************************************/ static void up_copyvectorblock(void) { /* There are three operational memory configurations: * - * 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case: + * 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). + * In this case: * * - Our vectors must be located at the beginning of FLASH and will - * also be mapped to address zero (because of the i.MX's "double map image." + * also be mapped to address zero (because of the i.MX's + * "double map image." * - There is nothing to be done here in this case. * * 2. We boot in FLASH but copy ourselves to DRAM from better performance. - * (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y). In this case: + * (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y). + * In this case: * - * - Our code image is in FLASH and we boot to FLASH initially, then copy - * ourself to DRAM, and + * - Our code image is in FLASH and we boot to FLASH initially, + * then copy ourself to DRAM, and * - DRAM will be mapped to address zero. * - There is nothing to be done here in this case. * - * 3. There is bootloader that copies us to DRAM, but probably not to the beginning - * of DRAM (say to 0x0900:0000) (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n). + * 3. There is bootloader that copies us to DRAM, but probably not to the + * beginning of DRAM (say to 0x0900:0000) + * (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n). * In this case: * * - DRAM will be mapped to address zero. @@ -176,14 +183,14 @@ static void up_copyvectorblock(void) #endif } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ void arm_boot(void) { - /* __start provided the basic MMU mappings for SDRAM. Now provide mappings for all - * IO regions (Including the vector region). + /* __start provided the basic MMU mappings for SDRAM. Now provide + * mappings for all IO regions (Including the vector region). */ up_setupmappings(); diff --git a/arch/arm/src/imx1/imx_cspi.h b/arch/arm/src/imx1/imx_cspi.h index b21c86c4752..3674c87c792 100644 --- a/arch/arm/src/imx1/imx_cspi.h +++ b/arch/arm/src/imx1/imx_cspi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_cspi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_CSPI_H #define __ARCH_ARM_IMX_CSPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ # include @@ -31,11 +31,11 @@ # include #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* CSPI Register Offsets ************************************************************/ +/* CSPI Register Offsets ****************************************************/ #define CSPI_RXD_OFFSET 0x0000 /* Receive Data Register */ #define CSPI_TXD_OFFSET 0x0004 /* Transmit Data Register */ @@ -46,7 +46,7 @@ #define CSPI_DMA_OFFSET 0x0018 /* DMA Control Register */ #define CSPI_RESET_OFFSET 0x001c /* Soft Reset Register */ -/* CSPI Register Addresses **********************************************************/ +/* CSPI Register Addresses **************************************************/ /* CSPI1 */ @@ -70,7 +70,7 @@ #define IMX_CSPI2_SPIDMA (IMX_CSPI2_VBASE + CSPI_DMA_OFFSET) #define IMX_CSPI2_SPIRESET (IMX_CSPI2_VBASE + CSPI_RESET_OFFSET) -/* CSPI Register Bit Definitions ****************************************************/ +/* CSPI Register Bit Definitions ********************************************/ /* CSPI Control Register */ @@ -141,13 +141,13 @@ #define CSPI_RESET_START (1 << 0) /* Bit 0: Execute soft reset */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ #ifdef __cplusplus @@ -158,9 +158,9 @@ extern "C" #define EXTERN extern #endif /* __cplusplus */ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ struct spi_dev_s; /* Forward reference */ @@ -173,10 +173,10 @@ struct spi_dev_s; /* Forward reference */ * prior to calling this function. Specifically: GPIOs should have * been configured for output, and all chip selects disabled. * - * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, - * If multiple devices on on the bus, then multiple chip selects will be - * required. Therefore, all GPIO chip management is deferred to board- - * specific logic. + * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. + * However, If multiple devices on on the bus, then multiple chip selects + * will be required. Therefore, all GPIO chip management is deferred to + * board- specific logic. * * Input Parameters: * Port number (for hardware that has multiple SPI interfaces) @@ -189,23 +189,26 @@ struct spi_dev_s; /* Forward reference */ FAR struct spi_dev_s *imx_spibus_initialize(int port); /**************************************************************************** - * The external functions, imx_spiselect, imx_spistatus, and imx_cmddaa must be - * provided by board-specific logic. These are implementations of the select and - * status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including imx_spibus_initialize()) are - * provided by common logic. To use this common SPI logic on your board: + * The external functions, imx_spiselect, imx_spistatus, and imx_cmddaa must + * be provided by board-specific logic. These are implementations of the + * select and status methods of the SPI interface defined by struct spi_ops_s + * (see include/nuttx/spi/spi.h). + * All other methods (including imx_spibus_initialize()) are provided by + * common logic. To use this common SPI logic on your board: * - * 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific - * logic. This function will perform chip selection and status operations using - * GPIOs in the way your board is configured. - * 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the - * imx_spicmddata() function in your board-specific logic. This function will - * perform cmd/data selection operations using GPIOs in the way your board is - * configured. - * 3. Add a call to imx_spibus_initialize() in your low level initialization logic - * 4. The handle returned by imx_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), - * for example, will bind the SPI driver to the SPI MMC/SD driver). + * 1. Provide imx_spiselect() and imx_spistatus() functions in your + * board-specific logic. This function will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide + * the imx_spicmddata() function in your board-specific logic. This + * function will perform cmd/data selection operations using GPIOs in + * the way your board is configured. + * 3. Add a call to imx_spibus_initialize() in your low level + * initialization logic + * 4. The handle returned by imx_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). * ****************************************************************************/ diff --git a/arch/arm/src/imx1/imx_decodeirq.c b/arch/arm/src/imx1/imx_decodeirq.c index 950432dc029..f25d9d7e740 100644 --- a/arch/arm/src/imx1/imx_decodeirq.c +++ b/arch/arm/src/imx1/imx_decodeirq.c @@ -1,4 +1,4 @@ -/******************************************************************************** +/**************************************************************************** * arch/arm/src/imx1/imx_decodeirq.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************/ + ****************************************************************************/ -/******************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************/ + ****************************************************************************/ #include @@ -36,25 +36,25 @@ #include "group/group.h" -/******************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************/ + ****************************************************************************/ -/******************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************/ + ****************************************************************************/ -/******************************************************************************** +/**************************************************************************** * Private Data - ********************************************************************************/ + ****************************************************************************/ -/******************************************************************************** +/**************************************************************************** * Private Functions - ********************************************************************************/ + ****************************************************************************/ -/******************************************************************************** +/**************************************************************************** * Public Functions - ********************************************************************************/ + ****************************************************************************/ uint32_t *arm_decodeirq(uint32_t *regs) { @@ -90,8 +90,9 @@ uint32_t *arm_decodeirq(uint32_t *regs) irq = regval >> AITC_NIVECSR_NIVECTOR_SHIFT; - /* If irq < 64, then this is the IRQ. If there is no pending interrupt, - * then irq will be >= 64 (it will be 0xffff for illegal source). + /* If irq < 64, then this is the IRQ. + * If there is no pending interrupt, then irq will be >= 64 + * (it will be 0xffff for illegal source). */ if (irq < NR_IRQS) diff --git a/arch/arm/src/imx1/imx_dma.h b/arch/arm/src/imx1/imx_dma.h index f46f269c42d..3e4dda2af47 100644 --- a/arch/arm/src/imx1/imx_dma.h +++ b/arch/arm/src/imx1/imx_dma.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_dma.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_DMA_H #define __ARCH_ARM_IMX_DMA_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* DMA Register Offsets *************************************************************/ +/* DMA Register Offsets *****************************************************/ #define DMA_SYS_OFFSET 0x0000 #define DMA_M2D_OFFSET 0x0040 @@ -78,7 +78,7 @@ #define DMA_TDIPR_OFFSET 0x000c #define DMA_TFIFOB_OFFSET 0x0010 -/* DMA Register Addresses ***********************************************************/ +/* DMA Register Addresses ***************************************************/ #define IMX_DMA_SYS_BASE (IMX_DMA_VBASE + DMA_SYS_OFFSET) #define IMX_DMA_M2D_BASE (IMX_DMA_VBASE + DMA_M2D_OFFSET) @@ -226,10 +226,10 @@ #define IMX_DMA_TDIPR (DMA_TST_BASE + DMA_TDIPR_OFFSET) #define IMX_DMA_TFIFOB (DMA_TST_BASE + DMA_TFIFOB_OFFSET) -/* DMA Register Bit Definitions *****************************************************/ +/* DMA Register Bit Definitions *********************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_DMA_H */ diff --git a/arch/arm/src/imx1/imx_eim.h b/arch/arm/src/imx1/imx_eim.h index b2c27a2a613..a2092068cab 100644 --- a/arch/arm/src/imx1/imx_eim.h +++ b/arch/arm/src/imx1/imx_eim.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_eim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_WIEM_H #define __ARCH_ARM_IMX_WIEM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* EIM Register Offsets ************************************************************/ +/* EIM Register Offsets *****************************************************/ #define EIM_CS0H_OFFSET 0x00 #define EIM_CS0L_OFFSET 0x04 @@ -45,7 +45,7 @@ #define EIM_CS5L_OFFSET 0x2c #define EIM_WEIM_OFFSET 0x30 -/* EIM Register Addresses ***********************************************************/ +/* EIM Register Addresses ***************************************************/ #define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET) #define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET) @@ -61,10 +61,10 @@ #define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET) #define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET) -/* EIM Register Bit Definitions *****************************************************/ +/* EIM Register Bit Definitions *********************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_EIM_H */ diff --git a/arch/arm/src/imx1/imx_gpio.h b/arch/arm/src/imx1/imx_gpio.h index ce62e878718..43d04475e93 100644 --- a/arch/arm/src/imx1/imx_gpio.h +++ b/arch/arm/src/imx1/imx_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMX1_IMX_GPIO_H #define __ARCH_ARM_SRC_IMX1_IMX_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ # include #endif #include "arm_arch.h" /* getreg32(), putreg32() */ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPIO Register Offsets ************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define GPIO_DDIR_OFFSET 0x0000 /* Data Direction Register */ #define GPIO_OCR1_OFFSET 0x0004 /* Output Configuration Register 1 */ @@ -65,7 +65,7 @@ #define GPIOD 3 /* Port D index */ #define GPIO_PT_OFFSET(n) (GPIO_PTA_OFFSET + (n)*0x0100) -/* GPIO Register Addresses **********************************************************/ +/* GPIO Register Addresses **************************************************/ #define IMX_PTA_VBASE (IMX_GPIO_VBASE + GPIO_PTA_OFFSET) #define IMX_PTB_VBASE (IMX_GPIO_VBASE + GPIO_PTB_OFFSET) @@ -163,18 +163,18 @@ #define IMX_GPIO_SWR(n) (IMX_PT_VBASE(n) + GPIO_SWR_OFFSET) #define IMX_GPIO_PUEN(n) (IMX_PT_VBASE(n) + GPIO_PUEN_OFFSET) -/* GPIO Register Bit Definitions ****************************************************/ +/* GPIO Register Bit Definitions ********************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMX1_IMX_GPIO_H */ #ifndef __ASSEMBLY__ -/* Handler circular include... This file includes arm_arch.h, but this file is - * included by arm_arch.h (via chip.h) BEFORE getreg32 is defined. +/* Handler circular include... This file includes arm_arch.h, but this file + * is included by arm_arch.h (via chip.h) BEFORE getreg32 is defined. */ #if !defined(__ARCH_ARM_IMX_GPIOHELPERS_H) && defined(getreg32) diff --git a/arch/arm/src/imx1/imx_i2c.h b/arch/arm/src/imx1/imx_i2c.h index 995d1fa0c96..c42cbf63cd6 100644 --- a/arch/arm/src/imx1/imx_i2c.h +++ b/arch/arm/src/imx1/imx_i2c.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_I2C_H #define __ARCH_ARM_IMX_I2C_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* I2C Register Offsets *************************************************************/ +/* I2C Register Offsets *****************************************************/ #define I2C_IADR_OFFSET 0x0000 #define I2C_IFDR_OFFSET 0x0004 @@ -37,7 +37,7 @@ #define I2C_I2SR_OFFSET 0x000c #define I2C_I2DR_OFFSET 0x0010 -/* I2C Register Addresses ***********************************************************/ +/* I2C Register Addresses ***************************************************/ #define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET) #define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET) @@ -45,10 +45,10 @@ #define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET) #define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET) -/* I2C Register Bit Definitions *****************************************************/ +/* I2C Register Bit Definitions *********************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_I2C_H */ diff --git a/arch/arm/src/imx1/imx_memorymap.h b/arch/arm/src/imx1/imx_memorymap.h index 48637087e57..5e07be26ccc 100644 --- a/arch/arm/src/imx1/imx_memorymap.h +++ b/arch/arm/src/imx1/imx_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_MEMORYMAP_H #define __ARCH_ARM_IMX_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include "arm.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Physical Memory Map **************************************************************/ +/* Physical Memory Map ******************************************************/ + +/* -0x000fffff + * Double Map Image 1Mb + * -0x001fffff + * Bootstrap ROM 1Mb + */ - /* -0x000fffff Double Map Image 1Mb */ - /* -0x001fffff Bootstrap ROM 1Mb */ #define IMX_PERIPHERALS_PSECTION 0x00200000 /* -0x002fffff Peripherals 1Mb */ #define IMX_ESRAM_PSECTION 0x00300000 /* -0x003fffff Embedded SRAM 128Kb */ #define IMX_SDRAM0_PSECTION 0x08000000 /* -0x0bffffff SDRAM0 (CSD0) 64Mb */ @@ -46,11 +50,11 @@ #define IMX_CS4_PSECTION 0x15000000 /* -0x15ffffff CS4 16Mb */ #define IMX_CS5_PSECTION 0x16000000 /* -0x16ffffff CS5 16Mb */ -/* Sizes of Address Sections ********************************************************/ +/* Sizes of Address Sections ************************************************/ /* Mapped sections */ #define IMX_PERIPHERALS_NSECTIONS 1 /* 1Mb 1 section */ -#define IMX_SDRAM0_NSECTIONS 16 /* 16Mb Based on CONFIG_RAM_SIZE */ +#define IMX_SDRAM0_NSECTIONS 16 /* 16Mb Based on CONFIG_RAM_SIZE */ #define IMX_SDRAM1_NSECTIONS 0 /* 64Mb (Not mapped) */ #define IMX_FLASH_NSECTIONS 32 /* 64Mb Based on CONFIG_FLASH_SIZE */ #define IMX_CS1_NSECTIONS 16 /* 16Mb */ @@ -59,14 +63,16 @@ #define IMX_CS4_NSECTIONS 16 /* 16Mb */ #define IMX_CS5_NSECTIONS 16 /* 16Mb */ -/* Virtual Memory Map ***************************************************************/ +/* Virtual Memory Map *******************************************************/ /* There are three operational memory configurations: * - * 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case: + * 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). + * In this case: * * - Our vectors must be located at the beginning of FLASH and will - * also be mapped to address zero (because of the i.MX's "double map image." + * also be mapped to address zero (because of the i.MX's "double map + * image." * - All vector addresses are FLASH absolute addresses, * - DRAM cannot reside at address zero, * - Vectors at address zero (CR_V is not set), @@ -80,30 +86,33 @@ * ourself to DRAM, * - DRAM will be mapped to address zero, * - The RESET vector is a FLASH absolute address, - * - All other vectors are absulte and reference functions in the final mapped SDRAM address + * - All other vectors are absulte and reference functions in the final + * mapped SDRAM address * - Vectors at address zero (CR_V is not set), and * - The boot logic must configure SDRAM. * - * 3. There is bootloader that copies us to DRAM, but probably not to the beginning - * of DRAM (say to 0x0900:0000) (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n). + * 3. There is bootloader that copies us to DRAM, but probably not to the + * beginning of DRAM (say to 0x0900:0000) + * (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n). * In this case: * * - DRAM will be mapped to address zero, * - Interrupt vectors will be copied to address zero, - * - Memory between the end of the vector area (say 0x0800:0400) and the beginning - * of the page table (0x0900:0000) will be given to the memory manager as a second - * memory region, - * - All vectors are absulte and reference functions in the final mapped SDRAM address + * - Memory between the end of the vector area (say 0x0800:0400) and the + * beginning of the page table (0x0900:0000) will be given to the memory + * manager as a second memory region, + * - All vectors are absulte and reference functions in the final mapped + * SDRAM address * - Vectors at address zero (CR_V is not set), and * - We must assume that the bootloader has configured SDRAM. */ #ifdef CONFIG_BOOT_RUNFROMFLASH - /* Use the identity mapping */ +/* Use the identity mapping */ # define IMX_SDRAM_VSECTION 0x08000000 /* -(+CONFIG_RAM_SIZE) */ #else - /* Map SDRAM to address zero */ +/* Map SDRAM to address zero */ # define IMX_SDRAM_VSECTION 0x00000000 /* -(+CONFIG_RAM_SIZE) */ #endif @@ -122,7 +131,7 @@ #define VECTOR_BASE 0x00000000 -/* Peripheral Register Offsets ******************************************************/ +/* Peripheral Register Offsets **********************************************/ #define IMX_AIPI1_OFFSET 0x00000000 /* -0x00000fff AIPI1 4Kb */ #define IMX_WDOG_OFFSET 0x00001000 /* -0x00001fff WatchDog 4Kb */ @@ -160,7 +169,7 @@ #define IMX_CSI_OFFSET 0x00024000 /* -0x00024fff CSI 4Kb */ /* -0x000fffff Reserved 876Kb */ -/* Peripheral Register Offsets ******************************************************/ +/* Peripheral Register Offsets **********************************************/ #define IMX_AIPI1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AIPI1_OFFSET) #define IMX_WDOG_VBASE (IMX_PERIPHERALS_VSECTION + IMX_WDOG_OFFSET) @@ -195,10 +204,10 @@ #define IMX_AITC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AITC_OFFSET) #define IMX_CSI_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CSI_OFFSET) -/* Memory Mapping Info **************************************************************/ +/* Memory Mapping Info ******************************************************/ -/* The NuttX entry point starts at an offset from the virtual beginning of DRAM. - * This offset reserves space for the MMU page cache. +/* The NuttX entry point starts at an offset from the virtual beginning of + * DRAM. This offset reserves space for the MMU page cache. */ #define NUTTX_START_VADDR ((CONFIG_RAM_NUTTXENTRY & 0xfff00000) | PGTABLE_SIZE) @@ -237,8 +246,8 @@ #define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_VEND-PGTABLE_COARSE_VBASE) #define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC) -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_MEMORYMAP_H */ diff --git a/arch/arm/src/imx1/imx_rtc.h b/arch/arm/src/imx1/imx_rtc.h index c393a2ee2c0..56f70352b3a 100644 --- a/arch/arm/src/imx1/imx_rtc.h +++ b/arch/arm/src/imx1/imx_rtc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_RTC_H #define __ARCH_ARM_IMX_RTC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* RTC Register Offsets *************************************************************/ +/* RTC Register Offsets *****************************************************/ #define RTC_HOURMIN_OFFSET 0x0000 #define RTC_SECOND_OFFSET 0x0004 @@ -45,7 +45,7 @@ #define RTC_TEST2_OFFSET 0x002c #define RTC_TEST3_OFFSET 0x0030 -/* RTC Register Addresses ***********************************************************/ +/* RTC Register Addresses ***************************************************/ #define IMX_RTC_HOURMIN (IMX_RTC_VBASE + RTC_HOURMIN_OFFSET) #define IMX_RTC_SECOND (IMX_RTC_VBASE + RTC_SECOND_OFFSET) @@ -61,10 +61,10 @@ #define IMX_RTC_TEST2 (IMX_RTC_VBASE + RTC_TEST2_OFFSET) #define IMX_RTC_TEST3 (IMX_RTC_VBASE + RTC_TEST3_OFFSET) -/* RTC Register Bit Definitions *****************************************************/ +/* RTC Register Bit Definitions *********************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_RTC_H */ diff --git a/arch/arm/src/imx1/imx_spi.c b/arch/arm/src/imx1/imx_spi.c index 3d29b751b3a..6719c619858 100644 --- a/arch/arm/src/imx1/imx_spi.c +++ b/arch/arm/src/imx1/imx_spi.c @@ -393,7 +393,9 @@ static int spi_performtx(struct imx_spidev_s *priv) } else { - /* Yes.. The transfer is complete, disable Tx FIFO empty interrupt */ + /* Yes.. + * The transfer is complete, disable Tx FIFO empty interrupt + */ regval = spi_getreg(priv, CSPI_INTCS_OFFSET); regval &= ~CSPI_INTCS_TEEN; @@ -1118,7 +1120,9 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port) #endif nxsem_init(&priv->exclsem, 0, 1); - /* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */ + /* Initialize control register: + * min frequency, ignore ready, master mode, mode=0, 8-bit + */ spi_putreg(priv, CSPI_CTRL_OFFSET, CSPI_CTRL_DIV512 | /* Lowest frequency */ diff --git a/arch/arm/src/imx1/imx_system.h b/arch/arm/src/imx1/imx_system.h index 24ea764f03c..4f1363b61bb 100644 --- a/arch/arm/src/imx1/imx_system.h +++ b/arch/arm/src/imx1/imx_system.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_system.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_SYSTEM_H #define __ARCH_ARM_IMX_SYSTEM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* AIPI Register Offsets ************************************************************/ +/* AIPI Register Offsets ****************************************************/ #define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */ #define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */ #define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */ -/* AIPI Register Addresses **********************************************************/ +/* AIPI Register Addresses **************************************************/ #define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET) #define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET) @@ -45,9 +45,9 @@ #define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET) #define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET) -/* AIPI Register Bit Definitions ****************************************************/ +/* AIPI Register Bit Definitions ********************************************/ -/* PLL Register Offsets *************************************************************/ +/* PLL Register Offsets *****************************************************/ #define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */ #define PLL_MPCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */ @@ -56,7 +56,7 @@ #define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */ #define PLL_PCDR_OFFSET 0x0020 /* Peripheral Clock Divider Register */ -/* PLL Register Addresses ***********************************************************/ +/* PLL Register Addresses ***************************************************/ #define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET) #define IMX_PLL_MPCTL0 (IMX_PLL_VBASE + PLL_MPCTL0_OFFSET) @@ -65,10 +65,10 @@ #define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET) #define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET) -/* PLL Register Bit Definitions *****************************************************/ +/* PLL Register Bit Definitions *********************************************/ -#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */ -#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */ +#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */ +#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */ #define PLL_CSCR_BCLKDIV_SHIFT 10 /* Bits 13–10: BClock Divider */ #define PLL_CSCR_BCLKDIV_MASK (15 << PLL_CSCR_BCLK_DIV_SHIFT) #define PLL_CSCR_PRESC (1 << 15) /* Bit 15: MPU PLL clock prescaler */ @@ -123,24 +123,23 @@ #define PLL_PCDR_PCLKDIV3_SHIFT 16 /* Bits 22–16: Peripheral Clock Divider 3 */ #define PLL_PCDR_PCLKDIV3_MASK (0x7f << PLL_PCDR_PCLKDIV3_SHIFT) -/* PLL Helper Macros ****************************************************************/ +/* PLL Helper Macros ********************************************************/ -/* SC Register Offsets **************************************************************/ +/* SC Register Offsets ******************************************************/ #define SC_RSR_OFFSET 0x0000 /* Reset Source Register */ #define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */ #define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */ #define SC_GPCR_OFFSET 0x000c /* Global Peripheral Control Register */ -/* SC Register Addresses ************************************************************/ +/* SC Register Addresses ****************************************************/ #define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET) #define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET) #define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET) #define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET) -/* SC Register Bit Definitions ******************************************************/ - +/* SC Register Bit Definitions **********************************************/ #define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */ #define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */ @@ -153,20 +152,20 @@ #define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin * (AOUT of Port D[9]) */ -/* SDRAMC Register Offsets **********************************************************/ +/* SDRAMC Register Offsets **************************************************/ #define SDRAMC_SDCTL0_OFFSET 0x0000 #define SDRAMC_SDCTL1_OFFSET 0x0004 -/* SDRAMC Register Addresses ********************************************************/ +/* SDRAMC Register Addresses ************************************************/ #define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET) #define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET)) -/* SDRAMC Register Bit Definitions **************************************************/ +/* SDRAMC Register Bit Definitions ******************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_SYSTEM_H */ diff --git a/arch/arm/src/imx1/imx_timer.h b/arch/arm/src/imx1/imx_timer.h index 7c832ff4bb5..1a5b0f3ac4c 100644 --- a/arch/arm/src/imx1/imx_timer.h +++ b/arch/arm/src/imx1/imx_timer.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_timer.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_TIMER_H #define __ARCH_ARM_IMX_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Timer Register Offsets ***********************************************************/ +/* Timer Register Offsets ***************************************************/ #define TIMER_TCTL_OFFSET 0x0000 /* Timer control register */ #define TIMER_TPRER_OFFSET 0x0004 /* Timer prescaler register */ @@ -38,7 +38,7 @@ #define TIMER_TCN_OFFSET 0x0010 /* Timer counter register */ #define TIMER_TSTAT_OFFSET 0x0014 /* Timer status register */ -/* Timer Register Addresses *********************************************************/ +/* Timer Register Addresses *************************************************/ #define IMX_TIMER1_TCTL (IMX_TIMER1_VBASE + TIMER_TCTL_OFFSET) #define IMX_TIMER1_TPRER (IMX_TIMER1_VBASE + TIMER_TPRER_OFFSET) @@ -54,7 +54,7 @@ #define IMX_TIMER2_TCN (IMX_TIMER2_VBASE + TIMER_TCN_OFFSET) #define IMX_TIMER2_TSTAT (IMX_TIMER2_VBASE + TIMER_TSTAT_OFFSET) -/* Timer Register Bit Definitions ***************************************************/ +/* Timer Register Bit Definitions *******************************************/ /* Timer Control Register */ @@ -82,8 +82,8 @@ #define TIMER_TSTAT_COMP (1 << 0) /* Bit 0: Compare Event */ #define TIMER_TSTAT_CAPT (1 << 1) /* Bit 1: Capture Event */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_TIMER_H */ diff --git a/arch/arm/src/imx1/imx_timerisr.c b/arch/arm/src/imx1/imx_timerisr.c index ad200a42764..74cff9e553d 100644 --- a/arch/arm/src/imx1/imx_timerisr.c +++ b/arch/arm/src/imx1/imx_timerisr.c @@ -118,7 +118,7 @@ void up_timer_initialize(void) * (defined in board.h) is the number of counts in millisecond, so: */ - putreg32(MSEC2TICK(IMX_PERCLK1_FREQ / 1000), IMX_TIMER1_TCMP); + putreg32(MSEC2TICK(IMX_PERCLK1_FREQ / 1000), IMX_TIMER1_TCMP); /* Configure to provide timer COMP interrupts when TCN increments * to TCMP. diff --git a/arch/arm/src/imx1/imx_uart.h b/arch/arm/src/imx1/imx_uart.h index 90db9ea5a40..b5851140cff 100644 --- a/arch/arm/src/imx1/imx_uart.h +++ b/arch/arm/src/imx1/imx_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMX1_CHIP_IMX_UART_H #define __ARCH_ARM_SRC_IMX1_CHIP_IMX_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* UART Register Offsets ************************************************************/ +/* UART Register Offsets ****************************************************/ #define UART_RXD0 0x0000 /* UART receiver register 0 */ #define UART_RXD1 0x0004 /* UART receiver register 1 */ @@ -61,7 +61,7 @@ #define UART_BMPR4 0x00cc /* UART BRM modulator preset register 4 */ #define UART_UTS 0x00d0 /* UART test register */ -/* UART Register Bit Definitions ****************************************************/ +/* UART Register Bit Definitions ********************************************/ /* UART Receiver Register */ @@ -205,8 +205,8 @@ #define UART_UTS_LOOP (1 << 12) /* Bit 12: Loop TX and RX for Test */ #define UART_UTS_FRCPERR (1 << 13) /* Bit 13: Force Parity Error */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMX1_CHIP_IMX_UART_H */ diff --git a/arch/arm/src/imx1/imx_usbd.h b/arch/arm/src/imx1/imx_usbd.h index dd8a100f2b8..7a30dd1a056 100644 --- a/arch/arm/src/imx1/imx_usbd.h +++ b/arch/arm/src/imx1/imx_usbd.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_usbd.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_USBD_H #define __ARCH_ARM_IMX_USBD_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* USBD Register Offsets ************************************************************/ +/* USBD Register Offsets ****************************************************/ #define USBD_FRAME_OFFSET 0x0000 #define USBD_SPEC_OFFSET 0x0004 @@ -61,7 +61,7 @@ #define USBD_EP_FRDP_OFFSET 0x0024 #define USBD_EP_FRWP_OFFSET 0x0028 -/* USBD Register Addresses **********************************************************/ +/* USBD Register Addresses **************************************************/ #define IMX_USBD_FRAME (IMX_USBD_VBASE + USBD_FRAME_OFFSET) #define IMX_USBD_SPEC (IMX_USBD_VBASE + USBD_SPEC_OFFSET) @@ -165,7 +165,7 @@ #define IMX_USBD_EP_FRDP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRDP_OFFSET) #define IMX_USBD_EP_FRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRWP_OFFSET) -/* USBD Register Bit Definitions ****************************************************/ +/* USBD Register Bit Definitions ********************************************/ /* USBD FRAME Register */ @@ -298,8 +298,8 @@ #define USBD_EPCTRL_FRAME (1 << 27) /* Bit 27: Frame Mode */ #define USBD_EPCTRL_WFR (1 << 28) /* Bit 29: Write Frame End */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_USBD_H */ diff --git a/arch/arm/src/imx1/imx_wdog.h b/arch/arm/src/imx1/imx_wdog.h index 0584637a2bd..03c8de80396 100644 --- a/arch/arm/src/imx1/imx_wdog.h +++ b/arch/arm/src/imx1/imx_wdog.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx1/imx_wdog.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,32 +16,32 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX_WDOG_H #define __ARCH_ARM_IMX_WDOG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* WDOG Register Offsets ************************************************************/ +/* WDOG Register Offsets ****************************************************/ #define WDOG_WCR_OFFSET 0x0000 /* Watchdog Control Register */ #define WDOG_WSR_OFFSET 0x0004 /* Watchdog Service Register */ #define WDOG_WSTR_OFFSET 0x0008 /* Watchdog Status Register */ -/* WDOG Register Addresses **********************************************************/ +/* WDOG Register Addresses **************************************************/ #define IMX_WDOG_WCR (IMX_WDOG_VBASE + WDOG_WCR_OFFSET) #define IMX_WDOG_WSR (IMX_WDOG_VBASE + WDOG_WSR_OFFSET) #define IMX_WDOG_WSTRT (IMX_WDOG_VBASE + WDOG_WSTR_OFFSET) -/* WDOG Register Bit Definitions ****************************************************/ +/* WDOG Register Bit Definitions ********************************************/ /* Watchdog Control Register */ @@ -50,6 +50,7 @@ #define WDOG_WCR_SWR (1 << 2) /* Bit 2: Software Reset Enable */ #define WDOG_WCR_TMD (1 << 3) /* Bit 3: Test Mode Enable */ #define WDOG_WCR_WIE (1 << 4) /* Bit 4: Watchdog Interrupt Enable */ + #define WDOG_WCR_WT_SHIFT 8 /* Bit 8-14: Watchdog Timeout */ #define WDOG_WCR_WT_MASK (0x7f << WDOG_WCR_WT_SHIFT) #define WDOG_WCR_WHALT (1 << 15) /* Bit 15: Watchdog Halt */ @@ -59,8 +60,8 @@ #define WDOG_WSR_SHIFT 0 /* Bit 0-15: Watchdog Service Register */ #define WDOG_WT_MASK (0xffff << WDOG_WSR_SHIFT) -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_IMX_WDOG_H */ diff --git a/arch/arm/src/imx6/hardware/imx_ccm.h b/arch/arm/src/imx6/hardware/imx_ccm.h index 8e9729bf979..a3630c51134 100644 --- a/arch/arm/src/imx6/hardware/imx_ccm.h +++ b/arch/arm/src/imx6/hardware/imx_ccm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_ccm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: - * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number - * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual", + * Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale. */ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_CCM_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_CCM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imx_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* CCM Register Offsets *************************************************************/ +/* CCM Register Offsets *****************************************************/ #define IMX_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ #define IMX_CCM_CCDR_OFFSET 0x0004 /* CCM Control Divider Register */ @@ -71,7 +71,7 @@ #define IMX_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ #define IMX_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Override Register */ -/* CCM Register Addresses ***********************************************************/ +/* CCM Register Addresses ***************************************************/ #define IMX_CCM_CCR (IMX_CCM_VBASE+IMX_CCM_CCR_OFFSET) #define IMX_CCM_CCDR (IMX_CCM_VBASE+IMX_CCM_CCDR_OFFSET) @@ -105,7 +105,7 @@ #define IMX_CCM_CCGR6 (IMX_CCM_VBASE+IMX_CCM_CCGR6_OFFSET) #define IMX_CCM_CMEOR (IMX_CCM_VBASE+IMX_CCM_CMEOR_OFFSET) -/* CCM Register Bit Definitions *****************************************************/ +/* CCM Register Bit Definitions *********************************************/ /* CCM Control Register */ @@ -188,12 +188,14 @@ # define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL3_SWCLK (1 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ # define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL2_PFD1 (2 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD1 */ # define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL2_PFD2 (3 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ + #define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT (8) /* Bits 8-9: Selector for gpu3d_shader clock multiplexer */ #define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (3 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) # define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MMDC_CH0 (0 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clk */ # define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_PLL3_SWCLK (1 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ # define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_PLL2_PFD1 (2 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD1 */ # define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_PLL3_PFD0 (3 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD0 */ + #define CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) /* Bit 10: Selector for pcie_axi clock multiplexer */ #define CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) /* Bit 11: Selector for vdoaxi clock multiplexer */ #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ @@ -201,23 +203,27 @@ # define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SWCLK (0 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ # define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK (1 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) /* Derive clock from osc_clk (pll1_ref_clk) */ # define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BYPASS (2 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) /* Derive clock from pll2_bypass_clk */ + #define CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for VPU axi clock multiplexer */ #define CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (3 << CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT) # define CCM_CBCMR_VPU_AXI_CLK_SEL_AXI (0 << CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT) /* Derive clock from AXI */ # define CCM_CBCMR_VPU_AXI_CLK_SEL_PLL2_PFD2 (1 << CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CBCMR_VPU_AXI_CLK_SEL_PLL2_PFD0 (2 << CCM_CBCMR_VPU_AXI_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ + #define CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT (16) /* Bits 16-17: Selector for open vg (GPU2D Core) clock multiplexer */ #define CCM_CBCMR_GPU2D_CORE_CLK_SEL_MASK (3 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) # define CCM_CBCMR_GPU2D_CORE_CLK_SEL_AXI (0 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) /* Derive clock from AXI */ # define CCM_CBCMR_GPU2D_CORE_CLK_SEL_PLL3_SWCLK (1 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ # define CCM_CBCMR_GPU2D_CORE_CLK_SEL_PLL2_PFD0 (2 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ # define CCM_CBCMR_GPU2D_CORE_CLK_SEL_PLL2_PFD2 (3 << CCM_CBCMR_GPU2D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ + #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) # define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2 (0 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) /* Derive clock from PLL2 */ # define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 (1 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 (2 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ # define CCM_CBCMR_PRE_PERIPH_CLK_SEL_DIV_PLL2_PFD2 (3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) /* Derive clock from divided (/2) PLL2 PFD2 */ + #define CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) /* Bit 20: Selector for periph2_clk2 clock multiplexer */ #define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT (21) /* Bits 21-22: Selector for pre_periph2 clock multiplexer */ #define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (3 << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT) @@ -225,6 +231,7 @@ # define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_PLL2_PFD2 (1 << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_PLL2_PFD0 (2 << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ # define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_DIV_PLL2_PFD2 (3 << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT) /* Derive clock from divided (/2) PLL2 PFD2 */ + #define CCM_CBCMR_GPU2D_CORE_CLK_PODF_SHIFT (23) /* Bits 23-25: Divider for gpu2d_core clock */ #define CCM_CBCMR_GPU2D_CORE_CLK_PODF_MASK (7 << CCM_CBCMR_GPU2D_CORE_CLK_PODF_SHIFT) # define CCM_CBCMR_GPU2D_CORE_CLK_PODF(n) ((uint32_t)(n) << CCM_CBCMR_GPU2D_CORE_CLK_PODF_SHIFT) @@ -240,21 +247,25 @@ #define CCM_CSCMR1_PERCLK_PODF_SHIFT (0) /* Bits 0-5: Divider for perclk podf */ #define CCM_CSCMR1_PERCLK_PODF_MASK (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT) # define CCM_CSCMR1_PERCLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCMR1_SSI1_CLK_SEL_SHIFT (10) /* Bits 10-11: Selector for ssi1 clock multiplexer */ #define CCM_CSCMR1_SSI1_CLK_SEL_MASK (3 << CCM_CSCMR1_SSI1_CLK_SEL_SHIFT) # define CCM_CSCMR1_SSI1_CLK_SEL_PLL3_PFD2 (0 << CCM_CSCMR1_SSI1_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */ # define CCM_CSCMR1_SSI1_CLK_SEL_PLL3_PFD3 (1 << CCM_CSCMR1_SSI1_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */ # define CCM_CSCMR1_SSI1_CLK_SEL_PLL4 (2 << CCM_CSCMR1_SSI1_CLK_SEL_SHIFT) /* Derive clock from PLL4 */ + #define CCM_CSCMR1_SSI2_CLK_SEL_SHIFT (12) /* Bits 12-13: Selector for ssi2 clock multiplexer */ #define CCM_CSCMR1_SSI2_CLK_SEL_MASK (3 << CCM_CSCMR1_SSI2_CLK_SEL_SHIFT) # define CCM_CSCMR1_SSI2_CLK_SEL_PLL3_PFD2 (0 << CCM_CSCMR1_SSI2_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */ # define CCM_CSCMR1_SSI2_CLK_SEL_PLL3_PFD3 (1 << CCM_CSCMR1_SSI2_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */ # define CCM_CSCMR1_SSI2_CLK_SEL_PLL4 (2 << CCM_CSCMR1_SSI2_CLK_SEL_SHIFT) /* Derive clock from PLL4 */ + #define CCM_CSCMR1_SSI3_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for ssi3 clock multiplexer */ #define CCM_CSCMR1_SSI3_CLK_SEL_MASK (3 << CCM_CSCMR1_SSI3_CLK_SEL_SHIFT) # define CCM_CSCMR1_SSI3_CLK_SEL_PLL3_PFD2 (0 << CCM_CSCMR1_SSI3_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */ # define CCM_CSCMR1_SSI3_CLK_SEL_PLL3_PFD3 (1 << CCM_CSCMR1_SSI3_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */ # define CCM_CSCMR1_SSI3_CLK_SEL_PLL4 (2 << CCM_CSCMR1_SSI3_CLK_SEL_SHIFT) /* Derive clock from PLL4 */ + #define CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) /* Bit 16: Selector for usdhc1 clock multiplexer */ #define CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) /* Bit 17: Selector for usdhc2 clock multiplexer */ #define CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) /* Bit 18: Selector for usdhc3 clock multiplexer */ @@ -280,12 +291,14 @@ #define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT (23) /* Bits 23-25: Divider for aclk_eim_slow clock root */ #define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK (7 << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT) # define CCM_CSCMR1_ACLK_EIM_SLOW_PODF(n) ((uint32_t)(n) << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCMR1_ACLK_SEL_SHIFT (27) /* Bits 27-28: Selector for aclk root clock multiplexer */ #define CCM_CSCMR1_ACLK_SEL_MASK (3 << CCM_CSCMR1_ACLK_SEL_SHIFT) # define CCM_CSCMR1_ACLK_SEL_PLL2_PFD2 (0 << CCM_CSCMR1_ACLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CSCMR1_ACLK_SEL_PLL3_SWCLK (1 << CCM_CSCMR1_ACLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ # define CCM_CSCMR1_ACLK_SEL_AXI (2 << CCM_CSCMR1_ACLK_SEL_SHIFT) /* Derive clock from AXI */ # define CCM_CSCMR1_ACLK_SEL_PLL2_PFD0 (3 << CCM_CSCMR1_ACLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ + #define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT (29) /* Bits 29-30: Selector for aclk_eim_slow root clock multiplexer */ #define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK (3 << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT) # define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_AXI (0 << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT) /* Derive clock from AXI */ @@ -298,6 +311,7 @@ #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ #define CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) # define CCM_CSCMR2_CAN_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) /* Bit 10: Control for divider of ldb clock for IPU di0 */ #define CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) /* Bit 11: Control for divider of ldb clock for IPU di1 */ #define CCM_CSCMR2_ESAI_CLK_SEL_SHIFT (19) /* Bits 19-20: Selector for esai clock multiplexer */ @@ -312,18 +326,23 @@ #define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for uart clock podf */ #define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT) # define CCM_CSCDR1_UART_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCDR1_USDHC1_PODF_SHIFT (11) /* Bits 11-13: Divider for usdhc1 clock podf */ #define CCM_CSCDR1_USDHC1_PODF_MASK (7 << CCM_CSCDR1_USDHC1_PODF_SHIFT) # define CCM_CSCDR1_USDHC1_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCDR1_USDHC2_PODF_SHIFT (16) /* Bits 16-18: Divider for usdhc2 clock */ #define CCM_CSCDR1_USDHC2_PODF_MASK (7 << CCM_CSCDR1_USDHC2_PODF_SHIFT) # define CCM_CSCDR1_USDHC2_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCDR1_USDHC3_PODF_SHIFT (19) /* Bits 19-21: Divider for usdhc3 clock podf */ #define CCM_CSCDR1_USDHC3_PODF_MASK (7 << CCM_CSCDR1_USDHC3_PODF_SHIFT) # define CCM_CSCDR1_USDHC3_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC3_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCDR1_USDHC4_PODF_SHIFT (22) /* Bits 22-24: Divider for usdhc4 clock pred */ #define CCM_CSCDR1_USDHC4_PODF_MASK (7 << CCM_CSCDR1_USDHC4_PODF_SHIFT) # define CCM_CSCDR1_USDHC4_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_USDHC4_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCDR1_VPU_AXI_PODF_SHIFT (25) /* Bits 25-27: Divider for vpu axi clock podf */ #define CCM_CSCDR1_VPU_AXI_PODF_MASK (7 << CCM_CSCDR1_VPU_AXI_PODF_SHIFT) # define CCM_CSCDR1_VPU_AXI_PODF(n) ((uint32_t)(n) << CCM_CSCDR1_VPU_AXI_PODF_SHIFT) /* n=(divisor-1) */ @@ -336,15 +355,18 @@ #define CCM_CS1CDR_SSI1_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for ssi1 clock pred */ #define CCM_CS1CDR_SSI1_CLK_PRED_MASK (7 << CCM_CS1CDR_SSI1_CLK_PRED_SHIFT) # define CCM_CS1CDR_SSI1_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SSI1_CLK_PRED_SHIFT) /* n=(divisor-1) */ + #define CCM_CS1CDR_ESAI_CLK_PRED_SHIFT (9) /* Bits 9-11: Divider for esai clock pred */ #define CCM_CS1CDR_ESAI_CLK_PRED_MASK (7 << CCM_CS1CDR_ESAI_CLK_PRED_SHIFT) # define CCM_CS1CDR_ESAI_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_ESAI_CLK_PRED_SHIFT) /* n=(divisor-1) */ + #define CCM_CS1CDR_SSI3_CLK_PODF_SHIFT (16) /* Bits 16-21: Divider for ssi3 clock podf */ #define CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3f << CCM_CS1CDR_SSI3_CLK_PODF_SHIFT) # define CCM_CS1CDR_SSI3_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_SSI3_CLK_PODF_SHIFT) #define CCM_CS1CDR_SSI3_CLK_PRED_SHIFT (22) /* Bits 22-24: Divider for ssi3 clock pred */ #define CCM_CS1CDR_SSI3_CLK_PRED_MASK (7 << CCM_CS1CDR_SSI3_CLK_PRED_SHIFT) # define CCM_CS1CDR_SSI3_CLK_PRED(n) ((uint32_t)(n) << CCM_CS1CDR_SSI3_CLK_PRED_SHIFT) /* n=(divisor-1) */ + #define CCM_CS1CDR_ESAI_CLK_PODF_SHIFT (25) /* Bits 25-27: Divider for esai clock podf */ #define CCM_CS1CDR_ESAI_CLK_PODF_MASK (7 << CCM_CS1CDR_ESAI_CLK_PODF_SHIFT) # define CCM_CS1CDR_ESAI_CLK_PODF(n) ((uint32_t)(n) << CCM_CS1CDR_ESAI_CLK_PODF_SHIFT) /* n=(divisor-1) */ @@ -354,9 +376,11 @@ #define CCM_CS2CDR_SSI2_CLK_PODF_SHIFT (0) /* Bits 0-5: Divider for ssi2 clock podf */ #define CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3f << CCM_CS2CDR_SSI2_CLK_PODF_SHIFT) # define CCM_CS2CDR_SSI2_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_SSI2_CLK_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CS2CDR_SSI2_CLK_PRED_SHIFT (6) /* Bits 6-8: Divider for ssi2 clock pred */ #define CCM_CS2CDR_SSI2_CLK_PRED_MASK (7 << CCM_CS2CDR_SSI2_CLK_PRED_SHIFT) # define CCM_CS2CDR_SSI2_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_SSI2_CLK_PRED_SHIFT) /* n=(divisor-1) */ + #define CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for ldb_di1 clock multiplexer */ #define CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (7 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) # define CCM_CS2CDR_LDB_DI0_CLK_SEL_PLL5 (0 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) /* Derive from PLL5 clock */ @@ -364,6 +388,7 @@ # define CCM_CS2CDR_LDB_DI0_CLK_SEL_PLL2_PFD2 (2 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CS2CDR_LDB_DI0_CLK_SEL_MMDC_CH1 (3 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch1 clock */ # define CCM_CS2CDR_LDB_DI0_CLK_SEL_PLL3_SWCLK (4 << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ + #define CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT (12) /* Bits 12-14: Selector for ldb_di1 clock multiplexer */ #define CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (7 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) # define CCM_CS2CDR_LDB_DI1_CLK_SEL_PLL5 (0 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) /* Derive PLL5 clock */ @@ -371,15 +396,18 @@ # define CCM_CS2CDR_LDB_DI1_CLK_SEL_PLL2_PFD2 (2 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CS2CDR_LDB_DI1_CLK_SEL_MMDC_CH1 (3 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch1 clock */ # define CCM_CS2CDR_LDB_DI1_CLK_SEL_PLL3_SWCLK (4 << CCM_CS2CDR_LDB_DI1_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ + #define CCM_CS2CDR_ENFC_CLK_SEL_SHIFT (16) /* Bits 16-17: Selector for enfc clock multiplexer */ #define CCM_CS2CDR_ENFC_CLK_SEL_MASK (3 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) # define CCM_CS2CDR_ENFC_CLK_SEL_PLL2_PFD0 (0 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ # define CCM_CS2CDR_ENFC_CLK_SEL_PLL2 (1 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) /* Derive clock from PLL2 */ # define CCM_CS2CDR_ENFC_CLK_SEL_PLL3_SWCLK (2 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ # define CCM_CS2CDR_ENFC_CLK_SEL_PLL2_PFD2 (3 << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ + #define CCM_CS2CDR_ENFC_CLK_PRED_SHIFT (18) /* Bits 18-20: Divider for enfc clock pred divider */ #define CCM_CS2CDR_ENFC_CLK_PRED_MASK (7 << CCM_CS2CDR_ENFC_CLK_PRED_SHIFT) # define CCM_CS2CDR_ENFC_CLK_PRED(n) ((uint32_t)(n) << CCM_CS2CDR_ENFC_CLK_PRED_SHIFT) /* n=(divisor-1) */ + #define CCM_CS2CDR_ENFC_CLK_PODF_SHIFT (21) /* Bits 21-26: Divider for enfc clock divider */ #define CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3f << CCM_CS2CDR_ENFC_CLK_PODF_SHIFT) # define CCM_CS2CDR_ENFC_CLK_PODF(n) ((uint32_t)(n) << CCM_CS2CDR_ENFC_CLK_PODF_SHIFT) @@ -392,24 +420,30 @@ # define CCM_CDCDR_SPDIF1_CLK_SEL_PLL3_PFD2 (1 << CCM_CDCDR_SPDIF1_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */ # define CCM_CDCDR_SPDIF1_CLK_SEL_PLL3_PFD3 (2 << CCM_CDCDR_SPDIF1_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */ # define CCM_CDCDR_SPDIF1_CLK_SEL_PLL3_SWCLK (3 << CCM_CDCDR_SPDIF1_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ + #define CCM_CDCDR_SPDIF1_CLK_PODF_SHIFT (9) /* Bits 9-11: Divider for spdif1 clock podf */ #define CCM_CDCDR_SPDIF1_CLK_PODF_MASK (7 << CCM_CDCDR_SPDIF1_CLK_PODF_SHIFT) # define CCM_CDCDR_SPDIF1_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF1_CLK_PODF_SHIFT) /* n=0,7 (divisor-1) */ + #define CCM_CDCDR_SPDIF1_CLK_PRED_SHIFT (12) /* Bits 12-14: Divider for spdif1 clock pred */ #define CCM_CDCDR_SPDIF1_CLK_PRED_MASK (7 << CCM_CDCDR_SPDIF1_CLK_PRED_SHIFT) # define CCM_CDCDR_SPDIF1_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF1_CLK_PRED_SHIFT) /* n=0,1,2,7 (divisor-1) */ + #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20) /* Bits 20-21: Selector for spdif0 clock multiplexer */ #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) # define CCM_CDCDR_SPDIF0_CLK_SEL_DIV_PLL4 (0 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL4 divided clock */ # define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2 (1 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */ # define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD3 (2 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */ # define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_SWCLK (3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */ + #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22) /* Bits 22-24: Divider for spdif0 clock podf */ #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) # define CCM_CDCDR_SPDIF0_CLK_PODF(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT) /* n=0,7 (divisor-1) */ + #define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25) /* Bits 25-27: Divider for spdif0 clock pred */ #define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) # define CCM_CDCDR_SPDIF0_CLK_PRED(n) ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT) /* n=0,1,2,7 (divisor-1) */ + #define CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) /* Bit 28: Selector for hsi_tx clock multiplexer */ #define CCM_CDCDR_HSI_TX_PODF_SHIFT (29) /* Bits 29-31: Divider for hsi_tx clock podf */ #define CCM_CDCDR_HSI_TX_PODF_MASK (7 << CCM_CDCDR_HSI_TX_PODF_SHIFT) @@ -424,9 +458,11 @@ # define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_IPP_DI1_CLK (2 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */ # define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI0_CLK (3 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */ # define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI1_CLK (4 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */ + #define CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT (3) /* Bits 3-5: Divider for ipu1_di0 clock divider */ #define CCM_CHSCCDR_IPU1_DI0_PODF_MASK (7 << CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT) # define CCM_CHSCCDR_IPU1_DI0_PODF(n) ((uint32_t)(n) << CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT (6) /* Bits 6-8: Selector for ipu1 di0 root clock pre-multiplexer */ #define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (7 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) # define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MMDC_CH0 (0 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */ @@ -435,6 +471,7 @@ # define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL2_PFD0 (3 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ # define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL2_PFD2 (4 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL3_PFD1 (5 << CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */ + #define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for ipu1 di1 root clock multiplexer */ #define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (7 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) # define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_DIV_IPU1 (0 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) /* Derive clock from divided pre-muxed ipu1 di1 clock */ @@ -442,9 +479,11 @@ # define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_IPP_DI1_CLK (2 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */ # define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_LDB_DI0_CLK (3 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */ # define CCM_CHSCCDR_IPU1_DI1_CLK_SEL_LDB_DI1_CLK (4 << CCM_CHSCCDR_IPU1_DI1_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */ + #define CCM_CHSCCDR_IPU1_DI1_PODF_SHIFT (12) /* Bits 12-14: Divider for ipu1_di clock divider */ #define CCM_CHSCCDR_IPU1_DI1_PODF_MASK (7 << CCM_CHSCCDR_IPU1_DI1_PODF_SHIFT) # define CCM_CHSCCDR_IPU1_DI1_PODF(n) ((uint32_t)(n) << CCM_CHSCCDR_IPU1_DI1_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for ipu1 di1 root clock pre-multiplexer */ #define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (7 << CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_SHIFT) # define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MMDC_CH0 (0 << CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */ @@ -463,9 +502,11 @@ # define CCM_CSCDR2_IPU2_DI0_CLK_SEL_IPP_DI1_CLK (2 << CCM_CSCDR2_IPU2_DI0_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */ # define CCM_CSCDR2_IPU2_DI0_CLK_SEL_LDB_DI0_CLK (3 << CCM_CSCDR2_IPU2_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */ # define CCM_CSCDR2_IPU2_DI0_CLK_SEL_LDB_DI1_CLK (4 << CCM_CSCDR2_IPU2_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */ + #define CCM_CSCDR2_IPU2_DI0_PODF_SHIFT (3) /* Bits 3-5: Divider for ipu2_di0 clock divider */ #define CCM_CSCDR2_IPU2_DI0_PODF_MASK (7 << CCM_CSCDR2_IPU2_DI0_PODF_SHIFT) # define CCM_CSCDR2_IPU2_DI0_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_IPU2_DI0_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT (6) /* Bits 6-8: Selector for ipu2 di0 root clock pre-multiplexer */ #define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (7 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) #define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MMDC_CH0 (0 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */ @@ -474,6 +515,7 @@ #define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_PLL2_PFD (3 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ #define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_PLL2_PFD2 (4 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ #define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_PLL3_PFD1 (5 << CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */ + #define CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for ipu1 di2 root clock multiplexer */ #define CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (7 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) # define CCM_CSCDR2_IPU2_DI1_CLK_SEL_DIV_IPU1 (0 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) /* Derive clock from divided pre-muxed ipu1 di1 clock */ @@ -481,9 +523,11 @@ # define CCM_CSCDR2_IPU2_DI1_CLK_SEL_IPP_DI1_CLK (2 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */ # define CCM_CSCDR2_IPU2_DI1_CLK_SEL_LDB_DI0_CLK (3 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */ # define CCM_CSCDR2_IPU2_DI1_CLK_SEL_LDB_DI1_CLK (4 << CCM_CSCDR2_IPU2_DI1_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */ + #define CCM_CSCDR2_IPU2_DI1_PODF_SHIFT (12) /* Bits 12-14: Divider for ipu2_di1 clock divider */ #define CCM_CSCDR2_IPU2_DI1_PODF_MASK (7 << CCM_CSCDR2_IPU2_DI1_PODF_SHIFT) # define CCM_CSCDR2_IPU2_DI1_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_IPU2_DI1_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT (15) /* Bits 15-17: Selector for ipu2 di1 root clock pre-multiplexer */ #define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (7 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) # define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MMDC_CH0 (0 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */ @@ -492,6 +536,7 @@ # define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_PLL2_PFD0 (3 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD0 */ # define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_PLL2_PFD2 (4 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_PLL3_PFD1 (5 << CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */ + #define CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT (19) /* Bits 19-24: Divider for ecspi clock podf */ #define CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3f << CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT) # define CCM_CSCDR2_ECSPI_CLK_PODF(n) ((uint32_t)(n) << CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT) /* n=(divisor-1) */ @@ -504,15 +549,18 @@ # define CCM_CSCDR3_IPU1_HSP_CLK_SEL_PLL2_PFD2 (1 << CCM_CSCDR3_IPU1_HSP_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CSCDR3_IPU1_HSP_CLK_SEL_PLL3_120M (2 << CCM_CSCDR3_IPU1_HSP_CLK_SEL_SHIFT) /* Derive clock from pll3_120M */ # define CCM_CSCDR3_IPU1_HSP_CLK_SEL_PLL3_PFD1 (3 << CCM_CSCDR3_IPU1_HSP_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */ + #define CCM_CSCDR3_IPU1_HSP_PODF_SHIFT (11) /* Bits 11-13: Divider for ipu1_hsp clock */ #define CCM_CSCDR3_IPU1_HSP_PODF_MASK (7 << CCM_CSCDR3_IPU1_HSP_PODF_SHIFT) # define CCM_CSCDR3_IPU1_HSP_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_IPU1_HSP_PODF_SHIFT) /* n=(divisor-1) */ + #define CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT (14) /* Bits 14-15: Selector for ipu2_hsp clock multiplexer */ #define CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (3 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) # define CCM_CSCDR3_IPU2_HSP_CLK_SEL_MMDC_CH0 (0 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 clock */ # define CCM_CSCDR3_IPU2_HSP_CLK_SEL_PLL2_PFD2 (1 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */ # define CCM_CSCDR3_IPU2_HSP_CLK_SEL_PLL3_120M (2 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) /* Derive clock from pll3_120M */ # define CCM_CSCDR3_IPU2_HSP_CLK_SEL_PLL3_PFD1 (3 << CCM_CSCDR3_IPU2_HSP_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD1 */ + #define CCM_CSCDR3_IPU2_HSP_PODF_SHIFT (16) /* Bits 16-18: Divider for ipu2_hsp clock */ #define CCM_CSCDR3_IPU2_HSP_PODF_MASK (7 << CCM_CSCDR3_IPU2_HSP_PODF_SHIFT) # define CCM_CSCDR3_IPU2_HSP_PODF(n) ((uint32_t)(n) << CCM_CSCDR3_IPU2_HSP_PODF_SHIFT) /* n=(divisor-1) */ @@ -536,6 +584,7 @@ # define CCM_CLPCR_LPM_RUNMODE (0 << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ # define CCM_CLPCR_LPM_WAITMODE (1 << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ # define CCM_CLPCR_LPM_STOPMODE (2 << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ + #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ #define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ #define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: Control closing of external reference oscillator clock */ @@ -546,6 +595,7 @@ # define CCM_CLPCR_STBY_COUNT_3 (1 << CCM_CLPCR_STBY_COUNT_SHIFT) /* Wait (3*pmic_delay_scaler)+1 ckil clocks */ # define CCM_CLPCR_STBY_COUNT_7 (2 << CCM_CLPCR_STBY_COUNT_SHIFT) /* Wait (7*pmic_delay_scaler)+1 ckil clocks */ # define CCM_CLPCR_STBY_COUNT_15 (3 << CCM_CLPCR_STBY_COUNT_SHIFT) /* Wait (15*pmic_delay_scaler)+1 ckil clocks */ + #define CCM_CLPCR_COSC_PWRDOWN (1 << 11) /* Bit 11: Control powering down of on chip oscillator */ #define CCM_CLPCR_WB_PER_AT_LPM (1 << 16) /* Bit 16: Enable periphery charge pump for well biasing at low power mode */ #define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS (1 << 19) /* Bit 19: Bypass handshake with mmdc_ch0 on next entrance to low power mode */ @@ -574,39 +624,41 @@ #define CCM_CCOSR_CLKO1_SEL_SHIFT (0) /* Bits 0-3: Selection of the clock to be generated on CCM_CLKO1 */ #define CCM_CCOSR_CLKO1_SEL_MASK (15 << CCM_CCOSR_CLKO1_SEL_SHIFT) -# define CCM_CCOSR_CLKO1_SEL_PLL3_SW_CLK (0 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll3_sw_clk (/2) */ -# define CCM_CCOSR_CLKO1_SEL_PLL2_MAIN_CLK (1 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll2_main_clk (/2) */ -# define CCM_CCOSR_CLKO1_SEL_PLL1_MAIN_CLK (2 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll1_main_clk (/2) */ -# define CCM_CCOSR_CLKO1_SEL_PLL5_MAIN_CLK (3 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll5_main_clk (/2) */ -# define CCM_CCOSR_CLKO1_SEL_VIDEO_27M_CLK_ROOT (4 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* video_27M_clk_root */ -# define CCM_CCOSR_CLKO1_SEL_AXI_CLK_ROOT (5 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* axi_clk_root */ -# define CCM_CCOSR_CLKO1_SEL_ENFC_CLK_ROOT (6 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* enfc_clk_root */ -# define CCM_CCOSR_CLKO1_SEL_IPU1_DI0_CLK_ROOT (7 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu1_di0_clk_root */ -# define CCM_CCOSR_CLKO1_SEL_IPU1_DI1_CLK_ROOT (8 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu1_di1_clk_root */ -# define CCM_CCOSR_CLKO1_SEL_IPU2_DI0_CLK_ROOT (9 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu2_di0_clk_root */ +# define CCM_CCOSR_CLKO1_SEL_PLL3_SW_CLK (0 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll3_sw_clk (/2) */ +# define CCM_CCOSR_CLKO1_SEL_PLL2_MAIN_CLK (1 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll2_main_clk (/2) */ +# define CCM_CCOSR_CLKO1_SEL_PLL1_MAIN_CLK (2 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll1_main_clk (/2) */ +# define CCM_CCOSR_CLKO1_SEL_PLL5_MAIN_CLK (3 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll5_main_clk (/2) */ +# define CCM_CCOSR_CLKO1_SEL_VIDEO_27M_CLK_ROOT (4 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* video_27M_clk_root */ +# define CCM_CCOSR_CLKO1_SEL_AXI_CLK_ROOT (5 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* axi_clk_root */ +# define CCM_CCOSR_CLKO1_SEL_ENFC_CLK_ROOT (6 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* enfc_clk_root */ +# define CCM_CCOSR_CLKO1_SEL_IPU1_DI0_CLK_ROOT (7 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu1_di0_clk_root */ +# define CCM_CCOSR_CLKO1_SEL_IPU1_DI1_CLK_ROOT (8 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu1_di1_clk_root */ +# define CCM_CCOSR_CLKO1_SEL_IPU2_DI0_CLK_ROOT (9 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu2_di0_clk_root */ # define CCM_CCOSR_CLKO1_SEL_IPU2_DI1_CLK_ROOT (10 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipu2_di1_clk_root */ # define CCM_CCOSR_CLKO1_SEL_AHB_CLK_ROOT (11 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ahb_clk_root */ # define CCM_CCOSR_CLKO1_SEL_IPG_CLK_ROOT (12 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ipg_clk_root */ # define CCM_CCOSR_CLKO1_SEL_PERCLK_ROOT (13 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* perclk_root */ # define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK_ROOT (14 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* ckil_sync_clk_root */ # define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK (15 << CCM_CCOSR_CLKO1_SEL_SHIFT) /* pll4_main_clk */ + #define CCM_CCOSR_CLKO1_DIV_SHIFT (4) /* Bits 4-6: Setting the divider of CCM_CLKO1 */ #define CCM_CCOSR_CLKO1_DIV_MASK (7 << CCM_CCOSR_CLKO1_DIV_SHIFT) # define CCM_CCOSR_CLKO1_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT) /* n=(divisor-1) */ + #define CCM_CCOSR_CLKO1_EN (1 << 7) /* Bit 7: Enable of CCM_CLKO1 clock */ #define CCM_CCOSR_CLK_OUT_SEL (1 << 8) /* Bit 8: CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */ -#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16) /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */ #define CCM_CCOSR_CLKO2_SEL_MASK (0x1f << CCM_CCOSR_CLKO2_SEL_SHIFT) -# define CCM_CCOSR_CLKO2_SEL_MMDC_CH0_CLK_ROOT (0 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* mmdc_ch0_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_MMDC_CH1_CLK_ROOT (1 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* mmdc_ch1_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_USDHC4_CLK_ROOT (2 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc4_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK_ROOT (3 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc1_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_GPU2D_AXI_CLK_ROOT (4 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* gpu2d_axi_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK_ROOT (5 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* wrck_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_ECSPI_CLK_ROOT (6 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* ecspi_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_GPU3D_AXI_CLK_ROOT (7 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* gpu3d_axi_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_USDHC3_CLK_ROOT (8 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc3_clk_root */ -# define CCM_CCOSR_CLKO2_SEL_125M_CLK_ROOT (9 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* 125M_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_MMDC_CH0_CLK_ROOT (0 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* mmdc_ch0_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_MMDC_CH1_CLK_ROOT (1 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* mmdc_ch1_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_USDHC4_CLK_ROOT (2 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc4_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK_ROOT (3 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc1_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_GPU2D_AXI_CLK_ROOT (4 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* gpu2d_axi_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_WRCK_CLK_ROOT (5 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* wrck_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_ECSPI_CLK_ROOT (6 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* ecspi_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_GPU3D_AXI_CLK_ROOT (7 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* gpu3d_axi_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_USDHC3_CLK_ROOT (8 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* usdhc3_clk_root */ +# define CCM_CCOSR_CLKO2_SEL_125M_CLK_ROOT (9 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* 125M_clk_root */ # define CCM_CCOSR_CLKO2_SEL_ARM_CLK_ROOT (10 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* arm_clk_root */ # define CCM_CCOSR_CLKO2_SEL_IPU1_HSP_CLK_ROOT (11 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* ipu1_hsp_clk_root */ # define CCM_CCOSR_CLKO2_SEL_IPU2_HSP_CLK_ROOT (12 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* ipu2_hsp_clk_root */ @@ -629,9 +681,11 @@ # define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK_ROOT (29 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* spdif0_clk_root */ # define CCM_CCOSR_CLKO2_SEL_SPDIF1_CLK_ROOT (30 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* spdif1_clk_root */ # define CCM_CCOSR_CLKO2_SEL_HSI_TX_CLK_ROOT (31 << CCM_CCOSR_CLKO2_SEL_SHIFT) /* hsi_tx_clk_root */ + #define CCM_CCOSR_CLKO2_DIV_SHIFT (21) /* Bits 21-23: Setting the divider of CCM_CLKO2 */ #define CCM_CCOSR_CLKO2_DIV_MASK (7 << CCM_CCOSR_CLKO2_DIV_SHIFT) # define CCM_CCOSR_CLKO2_DIV(n) ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT) /* n=(divisor-1) */ + #define CCM_CCOSR_CLKO2_EN (1 << 24) /* Bit 24: Enable of CCM_CLKO2 clock */ /* CCM General Purpose Register */ diff --git a/arch/arm/src/imx6/hardware/imx_ecspi.h b/arch/arm/src/imx6/hardware/imx_ecspi.h index d953c2a1483..2db5c78713a 100644 --- a/arch/arm/src/imx6/hardware/imx_ecspi.h +++ b/arch/arm/src/imx6/hardware/imx_ecspi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_ecspi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imx_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* ECSPI Register Offsets ***********************************************************/ +/* ECSPI Register Offsets ***************************************************/ #define ECSPI_RXDATA_OFFSET 0x0000 /* Receive Data Register */ #define ECSPI_TXDATA_OFFSET 0x0004 /* Transmit Data Register */ @@ -45,7 +45,7 @@ #define ECSPI_TESTREG_OFFSET 0x0020 /* Test Control Register */ #define ECSPI_MSGDATA_OFFSET 0x0040 /* Message Data Register */ -/* ECSPI Register Addresses *********************************************************/ +/* ECSPI Register Addresses *************************************************/ /* ECSPI1 */ @@ -112,7 +112,7 @@ #define IMX_ECSPI5_TESTREG (IMX_ECSPI5_VBASE + ECSPI_TESTREG_OFFSET) #define IMX_ECSPI5_MSGDATA (IMX_ECSPI5_VBASE + ECSPI_MSGDATA_OFFSET) -/* ECSPI Register Bit Definitions ***************************************************/ +/* ECSPI Register Bit Definitions *******************************************/ /* Control Register */ @@ -120,12 +120,13 @@ #define ECSPI_CONREG_HT (1 << 1) /* Bit 1: Hardware trigger enable */ #define ECSPI_CONREG_XCH (1 << 2) /* Bit 2: SPI Exchange bit */ #define ECSPI_CONREG_SMC (1 << 3) /* Bit 3: Start mode control */ -#define ECSPI_CONREG_CHMODE_SHIFT (4) /* Bits 4-7: SPI Channel mode */ +#define ECSPI_CONREG_CHMODE_SHIFT (4) /* Bits 4-7: SPI Channel mode */ #define ECSPI_CONREG_CHMODE_MASK (15 << ECSPI_CONREG_CHMODE_SHIFT) # define ECSPI_CONREG_CH0MASTER (1 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 0 master mode */ # define ECSPI_CONREG_CH1MASTER (2 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 1 master mode */ # define ECSPI_CONREG_CH2MASTER (4 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 2 master mode */ # define ECSPI_CONREG_CH3MASTER (8 << ECSPI_CONREG_CHMODE_SHIFT) /* Channel 3 master mode */ + #define ECSPI_CONREG_POSTDIV_SHIFT (8) /* Bits 8-11: SPI Post divider (exponent) */ #define ECSPI_CONREG_POSTDIV_MASK (15 << ECSPI_CONREG_POSTDIV_SHIFT) # define ECSPI_CONREG_POSTDIV_EXP(n) ((uint32_t)(n) << ECSPI_CONREG_POSTDIV_SHIFT) @@ -145,20 +146,24 @@ # define ECSPI_CONREG_POSTDIV_8192 (13 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*13 */ # define ECSPI_CONREG_POSTDIV_16384 (14 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*14 */ # define ECSPI_CONREG_POSTDIV_32768 (15 << ECSPI_CONREG_POSTDIV_SHIFT) /* Divide by 2*15 */ + #define ECSPI_CONREG_PREDIV_SHIFT (12) /* Bits 12-15: SPI Pre divider (minus 1) */ #define ECSPI_CONREG_PREDIV_MASK (15 << ECSPI_CONREG_PREDIV_SHIFT) # define ECSPI_CONREG_PREDIV(n) ((uint32_t)(n) << ECSPI_CONREG_PREDIV_SHIFT) + #define ECSPI_CONREG_DRCTL_SHIFT 16 /* Bits 16-17: SPI Data ready control */ #define ECSPI_CONREG_DRCTL_MASK (3 << ECSPI_CONREG_DRCTL_SHIFT) # define ECSPI_CONREG_DRCTL_IGNRDY (0 << ECSPI_CONREG_DRCTL_SHIFT) # define ECSPI_CONREG_DRCTL_FALLING (1 << ECSPI_CONREG_DRCTL_SHIFT) # define ECSPI_CONREG_DRCTL_ACTVLOW (2 << ECSPI_CONREG_DRCTL_SHIFT) + #define ECSPI_CONREG_CHSEL_SHIFT (18) /* Bits 18-19: SPI Channel select bits */ #define ECSPI_CONREG_CHSEL_MASK (3 << ECSPI_CONREG_CHSEL_SHIFT) # define ECSPI_CONREG_CHSEL_SS0 (0 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 0 select (SS0) */ # define ECSPI_CONREG_CHSEL_SS1 (1 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 1 select (SS1) */ # define ECSPI_CONREG_CHSEL_SS2 (2 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 2 select (SS2) */ # define ECSPI_CONREG_CHSEL_SS3 (3 << ECSPI_CONREG_CHSEL_SHIFT) /* Channel 3 select (SS3) */ + #define ECSPI_CONREG_BURSTLEN_SHIFT (20) /* Bits 20-31: Burst length */ #define ECSPI_CONREG_BURSTLEN_MASK (0xfff << ECSPI_CONREG_BURSTLEN_SHIFT) # define ECSPI_CONREG_BURSTLEN(n) ((uint32_t)(n) << ECSPI_CONREG_BURSTLEN_SHIFT) @@ -171,36 +176,42 @@ # define ECSPI_CONFIGREG_CH1PHA (2 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 1 SCLK Phase */ # define ECSPI_CONFIGREG_CH2PHA (4 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 2 SCLK Phase */ # define ECSPI_CONFIGREG_CH3PHA (8 << ECSPI_CONFIGREG_SCLKPHA_SHIFT) /* Channel 3 SCLK Phase */ + #define ECSPI_CONFIGREG_SCLKPOL_SHIFT (4) /* Bits 4-7: SPI Clock polarity control */ #define ECSPI_CONFIGREG_SCLKPOL_MASK (15 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) # define ECSPI_CONFIGREG_CH0POL (1 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 0 SCLK polarity */ # define ECSPI_CONFIGREG_CH1POL (2 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 1 SCLK polarity */ # define ECSPI_CONFIGREG_CH2POL (4 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 2 SCLK polarity */ # define ECSPI_CONFIGREG_CH3POL (8 << ECSPI_CONFIGREG_SCLKPOL_SHIFT) /* Channel 3 SCLK polarity */ + #define ECSPI_CONFIGREG_SSCTL_SHIFT (8) /* Bits 8-11: SPI SS Wave form select */ #define ECSPI_CONFIGREG_SSCTL_MASK (15 << ECSPI_CONFIGREG_SSCTL_SHIFT) # define ECSPI_CONFIGREG_CH0SSCTRL (1 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 0 SS control */ # define ECSPI_CONFIGREG_CH1SSCTRL (2 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 1 SS control */ # define ECSPI_CONFIGREG_CH2SSCTRL (4 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 2 SS control */ # define ECSPI_CONFIGREG_CH3SSCTRL (8 << ECSPI_CONFIGREG_SSCTL_SHIFT) /* Channel 3 SS control */ + #define ECSPI_CONFIGREG_SSPOL_SHIFT (12) /* Bits 12-15: SPI SS Polarity select */ #define ECSPI_CONFIGREG_SSPOL_MASK (15 << ECSPI_CONFIGREG_SSPOL_SHIFT) # define ECSPI_CONFIGREG_CH0SSPOL (1 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 0 SS polarity */ # define ECSPI_CONFIGREG_CH1SSPOL (2 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 1 SS polarity */ # define ECSPI_CONFIGREG_CH2SSPOL (4 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 2 SS polarity */ # define ECSPI_CONFIGREG_CH3SSPOL (8 << ECSPI_CONFIGREG_CHMODE_SHIFT) /* Channel 3 SS polarity */ + #define ECSPI_CONFIGREG_DATCTL_SHIFT (16) /* Bits 16-19: Data control */ #define ECSPI_CONFIGREG_DATCTL_MASK (15 << ECSPI_CONFIGREG_DATCTL_SHIFT) # define ECSPI_CONFIGREG_CH0DATLOW (1 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 0 SS low when inactive */ # define ECSPI_CONFIGREG_CH1DATLOW (2 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 1 SS low when inactive */ # define ECSPI_CONFIGREG_CH2DATLOW (4 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 2 SS low when inactive */ # define ECSPI_CONFIGREG_CH3DATLOW (8 << ECSPI_CONFIGREG_DATCTL_SHIFT) /* Channel 3 SS low when inactive */ + #define ECSPI_CONFIGREG_SCLKCTL_SHIFT (20) /* Bits 20-23: SCLK Control */ #define ECSPI_CONFIGREG_SCLKCTL_MASK (15 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) # define ECSPI_CONFIGREG_CH0SCLKLOW (1 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 0 SCLK low when inactive */ # define ECSPI_CONFIGREG_CH1SCLKLOW (2 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 1 SCLK low when inactive */ # define ECSPI_CONFIGREG_CH2SCLKLOW (4 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 2 SCLK low when inactive */ # define ECSPI_CONFIGREG_CH3SCLKLOW (8 << ECSPI_CONFIGREG_SCLKCTL_SHIFT) /* Channel 3 SCLK low when inactive */ + #define ECSPI_CONFIGREG_HTLEN_SHIFT (24) /* Bits 24-28: HT Length */ #define ECSPI_CONFIGREG_HTLEN_MASK (15 << ECSPI_CONFIGREG_HTLEN_SHIFT) # define ECSPI_CONFIGREG_HTLEN(n) ((uint32_t)(n) << ECSPI_CONFIGREG_HTLEN_SHIFT) @@ -264,12 +275,12 @@ /* Message Data Register (32-bit message data) */ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H */ diff --git a/arch/arm/src/imx6/hardware/imx_enet.h b/arch/arm/src/imx6/hardware/imx_enet.h index 34a649c71e4..18040dc9c8c 100644 --- a/arch/arm/src/imx6/hardware/imx_enet.h +++ b/arch/arm/src/imx6/hardware/imx_enet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_enet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_ENET_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_ENET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define IMX_ENET_HAS_DBSWAP 1 -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define IMX_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */ #define IMX_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */ @@ -96,7 +96,7 @@ #define IMX_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */ #define IMX_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define IMX_ENET_EIR (IMX_ENET_VBASE+IMX_ENET_EIR_OFFSET) #define IMX_ENET_EIMR (IMX_ENET_VBASE+IMX_ENET_EIMR_OFFSET) @@ -149,7 +149,7 @@ #define IMX_ENET_TCSR3 (IMX_ENET_VBASE+IMX_ENET_TCSR3_OFFSET) #define IMX_ENET_TCCR3 (IMX_ENET_VBASE+IMX_ENET_TCCR3_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Interrupt Event Register, Interrupt Mask Register */ @@ -490,7 +490,7 @@ /* Timer Compare Capture Register (32-bit compare value) */ -/* Buffer Descriptors ***************************************************************/ +/* Buffer Descriptors *******************************************************/ /* Endian-independent descriptor offsets */ @@ -637,11 +637,11 @@ # define RXDESC_BDU (1 << 7) #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/* Buffer Descriptors ***************************************************************/ +/* Buffer Descriptors *******************************************************/ /* Legacy Buffer Descriptor */ diff --git a/arch/arm/src/imx6/hardware/imx_gpio.h b/arch/arm/src/imx6/hardware/imx_gpio.h index a401f46ce47..6521094be95 100644 --- a/arch/arm/src/imx6/hardware/imx_gpio.h +++ b/arch/arm/src/imx6/hardware/imx_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: - * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number - * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual", + * Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale. */ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPIO_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imx_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define GPIO1 0 /* Port 1 index */ #define GPIO2 1 /* Port 2 index */ @@ -48,7 +48,7 @@ #define IMX_GPIO_NPORTS 7 /* Seven total ports */ #define IMX_GPIO_NPINS 32 /* Up to 32 pins per port */ -/* GPIO Register Offsets ************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define IMX_GPIO_DR_OFFSET 0x0000 /* Data Register */ #define IMX_GPIO_GDIR_OFFSET 0x0004 /* Data Direction Register */ @@ -59,7 +59,7 @@ #define IMX_GPIO_ISR_OFFSET 0x0018 /* Interrupt Status Register */ #define IMX_GPIO_EDGE_OFFSET 0x001c /* Interrupt Status Register */ -/* GPIO Register Addresses **********************************************************/ +/* GPIO Register Addresses **************************************************/ #define IMX_GPIO_DR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_DR_OFFSET) #define IMX_GPIO_GDIR(n) (IMX_GPIO_VBASE(n)+IMX_GPIO_GDIR_OFFSET) @@ -133,7 +133,7 @@ #define IMX_GPIO7_ISR (IMX_GPIO7_VBASE+IMX_GPIO_ISR_OFFSET) #define IMX_GPIO7_EDGE (IMX_GPIO7_VBASE+IMX_GPIO_EDGE_OFFSET) -/* GPIO Register Bit Definitions ****************************************************/ +/* GPIO Register Bit Definitions ********************************************/ /* Most registers are laid out simply with one bit per pin */ diff --git a/arch/arm/src/imx6/hardware/imx_gpt.h b/arch/arm/src/imx6/hardware/imx_gpt.h index 76d00ac3e1d..63c9672f050 100644 --- a/arch/arm/src/imx6/hardware/imx_gpt.h +++ b/arch/arm/src/imx6/hardware/imx_gpt.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_gpt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: - * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number - * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual", + * Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale. */ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imx_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPT Register Offsets ************************************************************/ +/* GPT Register Offsets *****************************************************/ #define IMX_GPT_CR_OFFSET 0x0000 /* GPT Control Register */ #define IMX_GPT_PR_OFFSET 0x0004 /* GPT Prescaler Register */ @@ -50,7 +50,7 @@ #define IMX_GPT_ICR2_OFFSET 0x0020 /* GPT Input Capture Register 2 */ #define IMX_GPT_CNT_OFFSET 0x0024 /* GPT Counter Register */ -/* GPT Register Addresses **********************************************************/ +/* GPT Register Addresses ***************************************************/ #define IMX_GPT_CR (IMX_GPT_VBASE+IMX_GPT_CR_OFFSET) #define IMX_GPT_PR (IMX_GPT_VBASE+IMX_GPT_PR_OFFSET) @@ -63,7 +63,7 @@ #define IMX_GPT_ICR2 (IMX_GPT_VBASE+IMX_GPT_ICR2_OFFSET) #define IMX_GPT_CNT (IMX_GPT_VBASE+IMX_GPT_CNT_OFFSET) -/* GPT Register Bit Definitions ****************************************************/ +/* GPT Register Bit Definitions *********************************************/ /* GPT Control Register */ @@ -82,6 +82,7 @@ # define GPT_CR_CLKSRC_LFREF (4 << GPT_CR_CLKSRC_SHIFT) /* Low Frequency Reference Clock */ # define GPT_CR_CLKSRC_OSCDIV8 (5 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator divided by 8 as Reference Clock */ # define GPT_CR_CLKSRC_OSC (7 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator as Reference Clock */ + #define GPT_CR_FFR (1 << 9) /* Bit 9: Free-Run or Restart mode */ #define GPT_CR_SWR (1 << 15) /* Bit 15: Software reset */ #define GPT_CR_IM1_SHIFT (16) /* Bits 16-17: Input Capture Channel 1 operating mode */ @@ -90,12 +91,14 @@ # define GPT_CR_IM1_RISING (1 << GPT_CR_IM1_SHIFT) /* Capture on rising edge only */ # define GPT_CR_IM1_FALLING (2 << GPT_CR_IM1_SHIFT) /* Capture on falling edge only */ # define GPT_CR_IM1_BOTH (3 << GPT_CR_IM1_SHIFT) /* Capture on both edges */ + #define GPT_CR_IM2_SHIFT (18) /* Bits 18-19: Input Capture Channel 2 operating mode */ #define GPT_CR_IM2_MASK (3 << GPT_CR_IM2_SHIFT) # define GPT_CR_IM2_DISABLED (0 << GPT_CR_IM2_SHIFT) /* Capture disabled */ # define GPT_CR_IM2_RISING (1 << GPT_CR_IM2_SHIFT) /* Capture on rising edge only */ # define GPT_CR_IM2_FALLING (2 << GPT_CR_IM2_SHIFT) /* Capture on falling edge only */ # define GPT_CR_IM2_BOTH (3 << GPT_CR_IM2_SHIFT) /* Capture on both edges */ + #define GPT_CR_OM1_SHIFT (22) /* Bits 20-22: Output Compare Channel 1 operating mode */ #define GPT_CR_OM1_MASK (7 << GPT_CR_OM1_SHIFT) # define GPT_CR_OM1_DISCON (0 << GPT_CR_OM1_SHIFT) /* Output disconnected */ @@ -103,6 +106,7 @@ # define GPT_CR_OM1_CLEAR (2 << GPT_CR_OM1_SHIFT) /* Clear output pin */ # define GPT_CR_OM1_SET (3 << GPT_CR_OM1_SHIFT) /* Set output pin */ # define GPT_CR_OM1_PULSE (4 << GPT_CR_OM1_SHIFT) /* Generate an active low pulse */ + #define GPT_CR_OM2_SHIFT (23) /* Bits 23-25: Output Compare Channel 2 operating mode */ #define GPT_CR_OM2_MASK (7 << GPT_CR_OM2_SHIFT) # define GPT_CR_OM2_DISCON (0 << GPT_CR_OM2_SHIFT) /* Output disconnected */ @@ -110,6 +114,7 @@ # define GPT_CR_OM2_CLEAR (2 << GPT_CR_OM2_SHIFT) /* Clear output pin */ # define GPT_CR_OM2_SET (3 << GPT_CR_OM2_SHIFT) /* Set output pin */ # define GPT_CR_OM2_PULSE (4 << GPT_CR_OM2_SHIFT) /* Generate an active low pulse */ + #define GPT_CR_OM3_SHIFT (26) /* Bits 26-28: Output Compare Channel 3 operating mode */ #define GPT_CR_OM3_MASK (7 << GPT_CR_OM3_SHIFT) # define GPT_CR_OM3_DISCON (0 << GPT_CR_OM3_SHIFT) /* Output disconnected */ @@ -117,6 +122,7 @@ # define GPT_CR_OM3_CLEAR (2 << GPT_CR_OM3_SHIFT) /* Clear output pin */ # define GPT_CR_OM3_SET (3 << GPT_CR_OM3_SHIFT) /* Set output pin */ # define GPT_CR_OM3_PULSE (4 << GPT_CR_OM3_SHIFT) /* Generate an active low pulse */ + #define GPT_CR_FO1 (1 << 29) /* FO1 Force Output Compare Channel 1 */ #define GPT_CR_FO2 (1 << 30) /* FO2 Force Output Compare Channel 2 */ #define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */ @@ -137,7 +143,9 @@ #define GPT_INT_ALL 0x0000003f /* GPT Output Compare Register 1,2,3 -- 32-bit compare registers */ + /* GPT Input Capture Register 1,2 -- 32-bit capture registers */ + /* GPT Counter Register -- 32-bit counter */ #endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H */ diff --git a/arch/arm/src/imx6/hardware/imx_iomuxc.h b/arch/arm/src/imx6/hardware/imx_iomuxc.h index 60c0d01a17c..f9023e4ee8e 100644 --- a/arch/arm/src/imx6/hardware/imx_iomuxc.h +++ b/arch/arm/src/imx6/hardware/imx_iomuxc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_iomuxc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,34 +16,35 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: - * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number - * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual", + * Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale. */ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_IOMUXC_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_IOMUXC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imx_memorymap.h" -/* These definitions derive from specifications for the i.MX 6Quad/6Dual and require - * review and modification in order to support other family members. +/* These definitions derive from specifications for the i.MX 6Quad/6Dual and + * require review and modification in order to support other family members. */ #if defined(CONFIG_ARCH_CHIP_IMX6_6QUAD) || defined(CONFIG_ARCH_CHIP_IMX6_6DUAL) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + +/* IOMUXC Register Offsets **************************************************/ -/* IOMUXC Register Offsets **********************************************************/ /* General Purpose Registers */ #define IMX_IOMUXC_GPR0_OFFSET 0x0000 @@ -62,6 +63,7 @@ #define IMX_IOMUXC_GPR13_OFFSET 0x0034 /* Pad Mux Registers */ + /* Pad Mux Register Indices (used by software for table lookups) */ #define IMX_PADMUX_SD2_DATA1_INDEX 0 @@ -467,6 +469,7 @@ #define IMX_PADMUX_SD2_DATA3_OFFSET 0x035c /* Pad Control Registers */ + /* Pad Mux Register Indices (used by software for table lookups) */ #define IMX_PADCTL_SD2_DATA1_INDEX 0 @@ -1112,7 +1115,8 @@ #define IMX_INPUT_USB_H1_OC_OFFSET 0x0948 #define IMX_INPUT_USDHC1_WP_ON_OFFSET 0x094c -/* IOMUXC Register Addresses ********************************************************/ +/* IOMUXC Register Addresses ************************************************/ + /* General Purpose Registers */ #define IMX_IOMUXC_GPR0 (IMX_IOMUXC_VBASE+IMX_IOMUXC_GPR0_OFFSET) @@ -1722,7 +1726,7 @@ #define IMX_INPUT_USB_H1_OC (IMX_IOMUXC_VBASE+IMX_INPUT_USB_H1_OC_OFFSET) #define IMX_INPUT_USDHC1_WP_ON (IMX_IOMUXC_VBASE+IMX_INPUT_USDHC1_WP_ON_OFFSET) -/* IOMUXC Register Bit Definitions **************************************************/ +/* IOMUXC Register Bit Definitions ******************************************/ /* General Purpose Register 0 (GPR0) */ @@ -2063,6 +2067,7 @@ #define GPR10_LOCK_DBG_EN (1 << 29) /* General Purpose Register 11 (GPR11) -- Contains no fields of interest. */ + /* General Purpose Register 12 (GPR12) */ #define GPR12_USDHC_DBG_MUX_SHIFT (2) @@ -2087,7 +2092,7 @@ # define GPR12_DIA_STATUS_BUS_SELECT(n) ((uint32_t)(n) << GPR12_DIA_STATUS_BUS_SELECT_SHIFT) #define GPR12_PCIE_CTL_7_SHIFT (21) #define GPR12_PCIE_CTL_7_MASK (7 << GPR12_PCIE_CTL_7_SHIFT) - #define GPR12_PCIE_CTL_7(n) ((uint32_t)(n) << GPR12_PCIE_CTL_7_SHIFT) +# define GPR12_PCIE_CTL_7(n) ((uint32_t)(n) << GPR12_PCIE_CTL_7_SHIFT) #define GPR12_ARMP_APB_CLK_EN (1 << 24) #define GPR12_ARMP_ATB_CLK_EN (1 << 25) #define GPR12_ARMP_AHB_CLK_EN (1 << 26) @@ -2227,6 +2232,7 @@ #define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */ #define PADCTL_DSE_MASK (7 << PADCTL_DSE_SHIFT) # define PADCTL_DSE(n) ((uint32_t)(n) << PADCTL_DSE_SHIFT) /* n=DRIVE_* */ + # define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */ # define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ # define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ @@ -2235,25 +2241,31 @@ # define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ # define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ # define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ + #define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */ #define PADCTL_SPEED_MASK (3 << PADCTL_SPEED_SHIFT) # define PADCTL_SPEED(n) ((uint32_t)(n) << PADCTL_SPEED_SHIFT) /* n=SPEED_* */ + # define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */ # define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ # define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ + #define PADCTL_ODE (1 << 11) /* Bit 11: Open Drain Enable Field */ #define PADCTL_PKE (1 << 12) /* Bit 12: Pull / Keep Enable Field */ #define PADCTL_PUE (1 << 13) /* Bit 13: Pull / Keep Select Field */ #define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */ #define PADCTL_PUS_MASK (3 << PADCTL_PUS_SHIFT) # define PADCTL_PUS(n) ((uint32_t)(n) << PADCTL_PUS_SHIFT) /* n=PULL_* */ + # define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */ # define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */ # define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */ # define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */ + #define PADCTL_HYS (1 << 16) /* Bit 16: Hysteresis Enable Field */ /* Pad Group Control Registers */ + /* Select Input Registers */ #endif /* CONFIG_ARCH_CHIP_IMX6_6QUAD || CONFIG_ARCH_CHIP_IMX6_6DUAL */ diff --git a/arch/arm/src/imx6/hardware/imx_memorymap.h b/arch/arm/src/imx6/hardware/imx_memorymap.h index 49bef956f1d..41fe426f5af 100644 --- a/arch/arm/src/imx6/hardware/imx_memorymap.h +++ b/arch/arm/src/imx6/hardware/imx_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,19 +16,19 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: - * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number - * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual", + * Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale. */ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_MEMORYMAP_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -36,24 +36,24 @@ /* i.MX6 Virtual (mapped) Memory Map * * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it depends - * on some the virtual address definitions provided above. + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. */ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Decimal configuration values may exceed 2Gb and, hence, overflow to negative - * values unless we force them to unsigned long: +/* Decimal configuration values may exceed 2Gb and, hence, overflow to + * negative values unless we force them to unsigned long: */ #define __CONCAT(a,b) a ## b #define MKULONG(a) __CONCAT(a,ul) -/* Overview ************************************************************************* +/* Overview ***************************************************************** * * i.MX6 Physical (unmapped) Memory Map * - i.MX6 System 1MB PSECTIONS @@ -90,9 +90,9 @@ * Page table start addresses * Base address of the interrupt vector table * - ************************************************************************************/ + ****************************************************************************/ -/* i.MX6 Physical (unmapped) Memory Map *********************************************/ +/* i.MX6 Physical (unmapped) Memory Map *************************************/ /* i.MX6 System PSECTIONS */ @@ -755,7 +755,12 @@ # define NUTTX_RAM_SIZE (NUTTX_RAM_PEND - NUTTX_RAM_PADDR) #else /* CONFIG_IMX6_BOOT_NOR */ - /* Must be CONFIG_IMX6_BOOT_OCRAM || CONFIG_IMX6_BOOT_SDRAM || CONFIG_IMX6_BOOT_SRAM */ + + /* Must be + * CONFIG_IMX6_BOOT_OCRAM || + * CONFIG_IMX6_BOOT_SDRAM || + * CONFIG_IMX6_BOOT_SRAM + */ /* Otherwise we are running from some kind of RAM (OCRAM, SRAM, or SDRAM). * Setup the RAM region as the NUTTX .txt, .bss, and .data region. @@ -894,11 +899,11 @@ * * (4GB address range / 4 KB per page ) * 4 bytes per entry = 4MB * - * 16KB of memory is reserved hold the page table for the virtual mappings. A - * portion of this table is not accessible in the virtual address space (for - * normal operation with a one-to-one address mapping). There is this large - * hole in the physcal address space for which there will never be level 1 - * mappings: + * 16KB of memory is reserved hold the page table for the virtual mappings. + * A portion of this table is not accessible in the virtual address space + * (for normal operation with a one-to-one address mapping). There is this + * large hole in the physcal address space for which there will never be + * level 1 mappings: * * 0x80000000-0xefffffff: Undefined (1.75 GB) * @@ -985,7 +990,8 @@ * * IMX_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM * IMX_VECTOR_VSRAM - Virtual address of vector table in SRAM - * IMX_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000) + * IMX_VECTOR_VADDR - Virtual address of vector table + * (0x00000000 or 0xffff0000) */ #define VECTOR_TABLE_SIZE 0x00010000 diff --git a/arch/arm/src/imx6/hardware/imx_pinmux.h b/arch/arm/src/imx6/hardware/imx_pinmux.h index 4f1d7a2880a..b825f6f9192 100644 --- a/arch/arm/src/imx6/hardware/imx_pinmux.h +++ b/arch/arm/src/imx6/hardware/imx_pinmux.h @@ -1,4 +1,4 @@ -/***************************************************************************************************** +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,35 +16,40 @@ * License for the specific language governing permissions and limitations * under the License. * - *****************************************************************************************************/ + ****************************************************************************/ /* Reference: - * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number - * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," + * Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale. */ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_PINMUX_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_PINMUX_H -/***************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************************************/ + ****************************************************************************/ + /* Alternate Pin Functions. * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however, - * will use the pin selection without the numeric suffix. Additional definitions are required in the - * board.h file. For example, if UART1 RXD connects via the SD3_DATA6 pin, then the following - * definition should appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. + * For example, if UART1 RXD connects via the SD3_DATA6 pin, then the + * following definition should appear in the board.h header file for that + * board: * * #define GPIO_UART1_RX_DATA GPIO_UART1_RX_DATA_1 * - * The driver will then automatically configere to use the SD3_DATA6 pin for UART RXD. + * The driver will then automatically configere to use the SD3_DATA6 pin for + * UART RXD. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific IOMUX options such as frequency, open-drain, - * push-pull, and pull-up/down! Just the basics are defined for most pins in this file. See the - * upper imx_gpio.h and imx_iomuxc.h header files for available definitions. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific IOMUX options such as + * frequency, open-drain, push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. See the upper imx_gpio.h and + * imx_iomuxc.h header files for available definitions. */ /* ARM */ @@ -661,7 +666,7 @@ #define GPIO_KEY_ROW7_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA09_INDEX)) #define GPIO_KEY_ROW7_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA0_INDEX)) -/* MediaLB (MLB)*/ +/* MediaLB (MLB) */ #define GPIO_MLB_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_ENET_TX_DATA1_INDEX)) #define GPIO_MLB_CLK_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO03_INDEX)) diff --git a/arch/arm/src/imx6/hardware/imx_src.h b/arch/arm/src/imx6/hardware/imx_src.h index ba33ca9c1f5..f3073e6cc04 100644 --- a/arch/arm/src/imx6/hardware/imx_src.h +++ b/arch/arm/src/imx6/hardware/imx_src.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_src.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ /* Reference: - * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number - * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," + * Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale. */ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_SRC_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_SRC_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imx_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* SRC Register Offsets *****************************************************************************/ +/* SRC Register Offsets *****************************************************/ #define IMX_SRC_SCR_OFFSET 0x0000 /* SRC Control Register */ #define IMX_SRC_SBMR1_OFFSET 0x0004 /* SRC Boot Mode Register 1 */ @@ -56,7 +56,7 @@ #define IMX_SRC_GPR9_OFFSET 0x0040 /* SRC General Purpose Register 9 */ #define IMX_SRC_GPR10_OFFSET 0x0044 /* SRC General Purpose Register 10 */ -/* SRC Register Addresses ***************************************************************************/ +/* SRC Register Addresses ***************************************************/ #define IMX_SRC_SCR (IMX_SRC_VBASE+IMX_SRC_SCR_OFFSET) #define IMX_SRC_SBMR1 (IMX_SRC_VBASE+IMX_SRC_SBMR1_OFFSET) @@ -75,41 +75,43 @@ #define IMX_SRC_GPR9 (IMX_SRC_VBASE+IMX_SRC_GPR9_OFFSET) #define IMX_SRC_GPR10 (IMX_SRC_VBASE+IMX_SRC_GPR10_OFFSET) -/* SRC Register Bit Definitions *********************************************************************/ +/* SRC Register Bit Definitions *********************************************/ /* SRC Control Register: Reset value 0x00000521 */ -#define SRC_SCR_WARM_RESET_ENABLE (1 << 0) /* Bit 0: WARM reset enable bit */ -#define SRC_SCR_SW_GPU_RST (1 << 1) /* Bit 1: Software reset for GPU */ -#define SRC_SCR_SW_VPU_RST (1 << 2) /* Bit 2: Software reset for VPU */ -#define SRC_SCR_SW_IPU1_RST (1 << 3) /* Bit 3: Software reset for IPU1 */ -#define SRC_SCR_SW_OPEN_VG_RST (1 << 4) /* Bit 4: Software reset for open_vg */ +#define SRC_SCR_WARM_RESET_ENABLE (1 << 0) /* Bit 0: WARM reset enable bit */ +#define SRC_SCR_SW_GPU_RST (1 << 1) /* Bit 1: Software reset for GPU */ +#define SRC_SCR_SW_VPU_RST (1 << 2) /* Bit 2: Software reset for VPU */ +#define SRC_SCR_SW_IPU1_RST (1 << 3) /* Bit 3: Software reset for IPU1 */ +#define SRC_SCR_SW_OPEN_VG_RST (1 << 4) /* Bit 4: Software reset for open_vg */ #define SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT (5) /* Bits 5-6: XTALI cycles before bypassing the MMDC ack */ #define SRC_SCR_WARM_RST_BYPASS_COUNT_MASK (3 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) # define SRC_SCR_WARM_RST_BYPASS_COUNT_NONE (0 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* Counter not used */ # define SRC_SCR_WARM_RST_BYPASS_COUNT_16 (1 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 16 XTALI cycles before WARM to COLD reset */ # define SRC_SCR_WARM_RST_BYPASS_COUNT_32 (2 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 32 XTALI cycles before WARM to COLD reset */ # define SRC_SCR_WARM_RST_BYPASS_COUNT_64 (3 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 64 XTALI cycles before WARM to COLD reset */ + #define SRC_SCR_MASK_WDOG_RST_SHIFT (7) /* Bits 7-10: Mask wdog_rst_b source */ #define SRC_SCR_MASK_WDOG_RST_MASK (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) # define SRC_SCR_MASK_WDOG_RST_MASKED (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) /* wdog_rst_b is masked */ # define SRC_SCR_MASK_WDOG_RST_UNMASKED (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) /* wdog_rst_b is not masked */ -#define SRC_SCR_EIM_RST (1 << 11) /* Bit 11: EIM reset is needed in order to reconfigure the eim chip select */ -#define SRC_SCR_SW_IPU2_RST (1 << 12) /* Bit 12: Software reset for ipu2 */ -#define SRC_SCR_CORE0_RST (1 << 13) /* Bit 13: Software reset for core0 */ -#define SRC_SCR_CORE1_RST (1 << 14) /* Bit 14: Software reset for core1 */ -#define SRC_SCR_CORE2_RST (1 << 15) /* Bit 15: Software reset for core2 */ -#define SRC_SCR_CORE3_RST (1 << 16) /* Bit 16: Software reset for core3 */ -#define SRC_SCR_CORE0_DBG_RST (1 << 17) /* Bit 17: Software reset for core0 debug */ -#define SRC_SCR_CORE1_DBG_RST (1 << 18) /* Bit 18: Software reset for core1 debug */ -#define SRC_SCR_CORE2_DBG_RST (1 << 19) /* Bit 19: Software reset for core2 debug */ -#define SRC_SCR_CORE3_DBG_RST (1 << 20) /* Bit 20: Software reset for core3 debug */ -#define SRC_SCR_CORES_DBG_RST (1 << 21) /* Bit 21: Software reset for debug of arm platform */ -#define SRC_SCR_CORE1_ENABLE (1 << 22) /* Bit 22: core1 enable */ -#define SRC_SCR_CORE2_ENABLE (1 << 23) /* Bit 23: core2 enable */ -#define SRC_SCR_CORE3_ENABLE (1 << 24) /* Bit 24: core3 enable */ -#define SRC_SCR_DBG_RST_MSK_PG (1 << 25) /* Bit 25: No debug resets after core power gating event */ - /* Bits 26-31: Reserved */ + +#define SRC_SCR_EIM_RST (1 << 11) /* Bit 11: EIM reset is needed in order to reconfigure the eim chip select */ +#define SRC_SCR_SW_IPU2_RST (1 << 12) /* Bit 12: Software reset for ipu2 */ +#define SRC_SCR_CORE0_RST (1 << 13) /* Bit 13: Software reset for core0 */ +#define SRC_SCR_CORE1_RST (1 << 14) /* Bit 14: Software reset for core1 */ +#define SRC_SCR_CORE2_RST (1 << 15) /* Bit 15: Software reset for core2 */ +#define SRC_SCR_CORE3_RST (1 << 16) /* Bit 16: Software reset for core3 */ +#define SRC_SCR_CORE0_DBG_RST (1 << 17) /* Bit 17: Software reset for core0 debug */ +#define SRC_SCR_CORE1_DBG_RST (1 << 18) /* Bit 18: Software reset for core1 debug */ +#define SRC_SCR_CORE2_DBG_RST (1 << 19) /* Bit 19: Software reset for core2 debug */ +#define SRC_SCR_CORE3_DBG_RST (1 << 20) /* Bit 20: Software reset for core3 debug */ +#define SRC_SCR_CORES_DBG_RST (1 << 21) /* Bit 21: Software reset for debug of arm platform */ +#define SRC_SCR_CORE1_ENABLE (1 << 22) /* Bit 22: core1 enable */ +#define SRC_SCR_CORE2_ENABLE (1 << 23) /* Bit 23: core2 enable */ +#define SRC_SCR_CORE3_ENABLE (1 << 24) /* Bit 24: core3 enable */ +#define SRC_SCR_DBG_RST_MSK_PG (1 << 25) /* Bit 25: No debug resets after core power gating event */ + /* Bits 26-31: Reserved */ /* SRC Boot Mode Register 1 */ @@ -173,15 +175,41 @@ #define SRC_SBMR2_BMOD_MASK (3 << SRC_SBMR2_BMOD_SHIFT) /* Bits 26-31: Reserved */ -/* SRC General Purpose Register 1: 32-bit PERSISTENT_ENTRY0: core0 entry function for waking-up from low power mode */ -/* SRC General Purpose Register 2: 32-bit PERSISTENT_ARG0: core0 entry function argument */ -/* SRC General Purpose Register 3: 32-bit PERSISTENT_ENTRY1: core1 entry function for waking-up from low power mode */ -/* SRC General Purpose Register 4: 32-bit PERSISTENT_ARG1: core1 entry function argument */ -/* SRC General Purpose Register 5: 32-bit PERSISTENT_ENTRY2: core2 entry function for waking-up from low power mode */ -/* SRC General Purpose Register 6: 32-bit PERSISTENT_ARG2: core1 entry function argument */ -/* SRC General Purpose Register 7: 32-bit PERSISTENT_ENTRY3: core3 entry function for waking-up from low power mode */ -/* SRC General Purpose Register 8: 32-bit PERSISTENT_ARG3: core3 entry function argument */ -/* SRC General Purpose Register 9: Reserved */ +/* SRC General Purpose Register 1: 32-bit PERSISTENT_ENTRY0: + * core0 entry function for waking-up from low power mode + */ + +/* SRC General Purpose Register 2: 32-bit PERSISTENT_ARG0: + * core0 entry function argument + */ + +/* SRC General Purpose Register 3: 32-bit PERSISTENT_ENTRY1: + * core1 entry function for waking-up from low power mode + */ + +/* SRC General Purpose Register 4: 32-bit PERSISTENT_ARG1: + * core1 entry function argument + */ + +/* SRC General Purpose Register 5: 32-bit PERSISTENT_ENTRY2: + * core2 entry function for waking-up from low power mode + */ + +/* SRC General Purpose Register 6: 32-bit PERSISTENT_ARG2: + * core1 entry function argument + */ + +/* SRC General Purpose Register 7: 32-bit PERSISTENT_ENTRY3: + * core3 entry function for waking-up from low power mode + */ + +/* SRC General Purpose Register 8: 32-bit PERSISTENT_ARG3: + * core3 entry function argument + */ + +/* SRC General Purpose Register 9: + * Reserved + */ /* SRC General Purpose Register 10 */ diff --git a/arch/arm/src/imx6/hardware/imx_uart.h b/arch/arm/src/imx6/hardware/imx_uart.h index 06aef52b1cb..078b7008082 100644 --- a/arch/arm/src/imx6/hardware/imx_uart.h +++ b/arch/arm/src/imx6/hardware/imx_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/hardware/imx_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: - * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number - * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual", + * Document Number IMX6DQRM, Rev. 3, 07/2015, FreeScale. */ #ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_UART_H #define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imx_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* UART Register Offsets ************************************************************/ +/* UART Register Offsets ****************************************************/ #define UART_RXD_OFFSET 0x0000 /* UART receiver register */ #define UART_TXD_OFFSET 0x0040 /* UART receiver register */ @@ -57,7 +57,7 @@ #define UART_UTS_OFFSET 0x00b4 /* UART test register */ #define UART_UMCR_OFFSET 0x00b8 /* UART RS-485 Mode Control Register */ -/* UART Register Addresses **********************************************************/ +/* UART Register Addresses **************************************************/ #define UART1_RXD (IMX_UART1_VBASE+UART_RXD_OFFSET) #define UART1_TXD (IMX_UART1_VBASE+UART_TXD_OFFSET) @@ -149,7 +149,7 @@ #define UART5_UTS (IMX_UART5_VBASE+UART_UTS_OFFSET) #define UART5_UMCR (IMX_UART5_VBASE+UART_UMCR_OFFSET) -/* UART Register Bit Definitions ****************************************************/ +/* UART Register Bit Definitions ********************************************/ /* UART Receiver Register */ @@ -185,6 +185,7 @@ # define UART_UCR1_ICD_8FRMS (1 << UART_UCR1_ICD_SHIFT) /* Idle for more than 8 frames */ # define UART_UCR1_ICD_16FRMS (2 << UART_UCR1_ICD_SHIFT) /* Idle for more than 16 frames */ # define UART_UCR1_ICD_32FRMS (3 << UART_UCR1_ICD_SHIFT) /* Idle for more than 32 frames */ + #define UART_UCR1_IDEN (1 << 12) /* Bit 12: Idle condition detected interrupt enable */ #define UART_UCR1_TRDYEN (1 << 13) /* Bit 13: Transmitter ready interrupt enable */ #define UART_UCR1_ADBR (1 << 14) /* Bit 14: Automatic detection of baud rate */ @@ -206,6 +207,7 @@ # define UART_UCR2_RTEC_RISE (0 << UART_UCR2_RTEC_SHIFT) /* Interrupt on rising edge */ # define UART_UCR2_RTEC_FALL (1 << UART_UCR2_RTEC_SHIFT) /* Interrupt on falling edge */ # define UART_UCR2_RTEC_BOTH (2 << UART_UCR2_RTEC_SHIFT) /* Interrupt on any edge */ + #define UART_UCR2_ESCEN (1 << 11) /* Bit 11: Escape enable */ #define UART_UCR2_CTS (1 << 12) /* Bit 12: Clear To Send pin */ #define UART_UCR2_CTSC (1 << 13) /* Bit 13: CTS Pin control */ @@ -264,6 +266,7 @@ # define UART_UFCR_RFDIV2 (4 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 2 */ # define UART_UFCR_RFDIV1 (5 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 1 */ # define UART_UFCR_RFDIV7 (6 << UART_UFCR_RFDIV_SHIFT) /* Divide input clock by 7 */ + #define UART_UFCR_TXTL_SHIFT 10 /* Bits 10-15: Transmitter Trigger Level */ #define UART_UFCR_TXTL_MASK (0x3f << UART_UFCR_TXTL_SHIFT) # define UART_UFCR_TXTL(n) ((uint32_t)(n) << UART_UFCR_TXTL_SHIFT) diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 1ee1fd2ed96..4dea7c9f2d1 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -212,8 +212,8 @@ static void imx_vectormapping(void) * Description: * Copy the interrupt block to its final destination. Vectors are already * positioned at the beginning of the text region and only need to be - * copied in the case where we are using high vectors or where the beginning - * of the text region cannot be remapped to address zero. + * copied in the case where we are using high vectors or where the + * beginning of the text region cannot be remapped to address zero. * ****************************************************************************/ @@ -232,8 +232,8 @@ static void imx_copyvectorblock(void) imx_vectorpermissions(MMU_L2_VECTRWFLAGS); #endif - /* Copy the vectors into OCRAM at the address that will be mapped to the vector - * address: + /* Copy the vectors into OCRAM at the address that will be mapped to the + * vector address: * * IMX_VECTOR_PADDR - Unmapped, physical address of vector table in OCRAM * IMX_VECTOR_VSRAM - Virtual address of vector table in OCRAM @@ -505,7 +505,8 @@ void arm_boot(void) /* Now we can enable all other CPUs. The enabled CPUs will start execution * at __cpuN_start and, after very low-level CPU initialization has been - * performed, will branch to arm_cpu_boot() (see arch/arm/src/armv7-a/smp.h) + * performed, will branch to arm_cpu_boot() + * (see arch/arm/src/armv7-a/smp.h) */ imx_cpu_enable(); diff --git a/arch/arm/src/imx6/imx_config.h b/arch/arm/src/imx6/imx_config.h index 4fbac68b8b0..ad7dad1c654 100644 --- a/arch/arm/src/imx6/imx_config.h +++ b/arch/arm/src/imx6/imx_config.h @@ -31,7 +31,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Configuration **********************************************************/ +/* Configuration ************************************************************/ /* Is there a UART enabled? */ diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c index 40578955536..cd294f3bc13 100644 --- a/arch/arm/src/imx6/imx_cpuboot.c +++ b/arch/arm/src/imx6/imx_cpuboot.c @@ -227,9 +227,9 @@ void imx_cpu_enable(void) * * Description: * Continues the C-level initialization started by the assembly language - * __cpu[n]_start function. At a minimum, this function needs to initialize - * interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to - * issue an SGI. + * __cpu[n]_start function. At a minimum, this function needs to + * initialize interrupt handling and, perhaps, wait on WFI for + * arm_cpu_start() to issue an SGI. * * This function must be provided by the each ARMv7-A MCU and implement * MCU-specific initialization logic. diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c index bd32a2eced1..2f77640328b 100644 --- a/arch/arm/src/imx6/imx_ecspi.c +++ b/arch/arm/src/imx6/imx_ecspi.c @@ -509,7 +509,9 @@ static int spi_performtx(struct imx_spidev_s *priv) } else { - /* Yes.. The transfer is complete, disable Tx FIFO empty interrupt */ + /* Yes.. + * The transfer is complete, disable Tx FIFO empty interrupt + */ regval = spi_getreg(priv, ECSPI_INTREG_OFFSET); regval &= ~ECSPI_INT_TE; @@ -1295,7 +1297,9 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port) #endif nxsem_init(&priv->exclsem, 0, 1); - /* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */ + /* Initialize control register: + * min frequency, ignore ready, master mode, mode=0, 8-bit + */ spi_putreg(priv, ECSPI_CONREG_OFFSET, ECSPI_CONREG_DIV512 | /* Lowest frequency */ diff --git a/arch/arm/src/imx6/imx_ecspi.h b/arch/arm/src/imx6/imx_ecspi.h index a4ea8124651..7a3ed76a6de 100644 --- a/arch/arm/src/imx6/imx_ecspi.h +++ b/arch/arm/src/imx6/imx_ecspi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/imx_ecspi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_IMX6_ECSPI_H #define __ARCH_ARM_IMX6_ECSPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,13 +33,13 @@ #include "hardware/imx_ecspi.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ #ifdef __cplusplus @@ -50,13 +50,13 @@ extern "C" #define EXTERN extern #endif /* __cplusplus */ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ struct spi_dev_s; /* Forward reference */ -/************************************************************************************ +/**************************************************************************** * Name: imx_spibus_initialize * * Description: @@ -65,7 +65,7 @@ struct spi_dev_s; /* Forward reference */ * prior to calling this function. Specifically: GPIOs should have * been configured for output, and all chip selects disabled. * - * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, + * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, * If multiple devices on on the bus, then multiple chip selects will be * required. Therefore, all GPIO chip management is deferred to board- * specific logic. @@ -76,33 +76,37 @@ struct spi_dev_s; /* Forward reference */ * Returned Value: * Valid SPI device structure reference on success; a NULL on failure * - ************************************************************************************/ + ****************************************************************************/ FAR struct spi_dev_s *imx_spibus_initialize(int port); -/************************************************************************************ - * The external functions, imx_spiselect, imx_spistatus, and imx_cmddata must be - * provided by board-specific logic. These are implementations of the select and - * status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including imx_spibus_initialize()) are - * provided by common logic. To use this common SPI logic on your board: +/**************************************************************************** + * The external functions, imx_spiselect, imx_spistatus, and imx_cmddata must + * be provided by board-specific logic. These are implementations of the + * select and status methods of the SPI interface defined by struct spi_ops_s + * (see include/nuttx/spi/spi.h). All other methods (including + * imx_spibus_initialize()) are provided by common logic. + * To use this common SPI logic on your board: * - * 1. Provide imx_spiselect() and imx_spistatus() functions in your board-specific - * logic. This function will perform chip selection and status operations using - * GPIOs in the way your board is configured. - * 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide the - * imx_spicmddata() function in your board-specific logic. This function will - * perform cmd/data selection operations using GPIOs in the way your board is - * configured. - * 3. Add a call to imx_spibus_initialize() in your low level initialization logic - * 4. The handle returned by imx_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), - * for example, will bind the SPI driver to the SPI MMC/SD driver). + * 1. Provide imx_spiselect() and imx_spistatus() functions in your + * board-specific logic. This function will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide + * the imx_spicmddata() function in your board-specific logic. This + * function will perform cmd/data selection operations using GPIOs in + * the way your board is configured. + * 3. Add a call to imx_spibus_initialize() in your low level + * initialization logic + * 4. The handle returned by imx_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMX6_ECSPI1 -void imx_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imx_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imx_spi1status(FAR struct spi_dev_s *dev, uint32_t devid); #ifdef CONFIG_SPI_CMDDATA int imx_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); @@ -110,7 +114,8 @@ int imx_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_IMX6_ECSPI2 -void imx_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imx_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imx_spi2status(FAR struct spi_dev_s *dev, uint32_t devid); #ifdef CONFIG_SPI_CMDDATA int imx_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); @@ -118,7 +123,8 @@ int imx_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_IMX6_ECSPI3 -void imx_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imx_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imx_spi3status(FAR struct spi_dev_s *dev, uint32_t devid); #ifdef CONFIG_SPI_CMDDATA int imx_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); @@ -126,7 +132,8 @@ int imx_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_IMX6_ECSPI4 -void imx_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imx_spi4select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imx_spi4status(FAR struct spi_dev_s *dev, uint32_t devid); #ifdef CONFIG_SPI_CMDDATA int imx_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); @@ -134,7 +141,8 @@ int imx_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_IMX6_ECSPI5 -void imx_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imx_spi5select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imx_spi5status(FAR struct spi_dev_s *dev, uint32_t devid); #ifdef CONFIG_SPI_CMDDATA int imx_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); diff --git a/arch/arm/src/imx6/imx_enet.h b/arch/arm/src/imx6/imx_enet.h index b8e59e01d3c..68d1f2f82c1 100644 --- a/arch/arm/src/imx6/imx_enet.h +++ b/arch/arm/src/imx6/imx_enet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/imx_enet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMX6_IMX_ENET_H #define __ARCH_ARM_SRC_IMX6_IMX_ENET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,17 +31,17 @@ #ifdef CONFIG_IMX_ENET -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Definitions for use with imx_phy_boardinitialize */ #define EMAC_INTF 0 -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -54,7 +54,7 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Function: up_netinitialize * * Description: @@ -72,19 +72,20 @@ extern "C" * Assumptions: * Called very early in the initialization sequence. * - ************************************************************************************/ + ****************************************************************************/ void up_netinitialize(void); -/************************************************************************************ +/**************************************************************************** * Function: imx_phy_boardinitialize * * Description: - * Some boards require specialized initialization of the PHY before it can be - * used. This may include such things as configuring GPIOs, resetting the PHY, - * etc. If CONFIG_IMX_ENET_PHYINIT is defined in the configuration then the - * board specific logic must provide imx_phyinitialize(); The i.MX RT Ethernet - * driver will call this function one time before it first uses the PHY. + * Some boards require specialized initialization of the PHY before it can + * be used. This may include such things as configuring GPIOs, resetting + * the PHY, etc. If CONFIG_IMX_ENET_PHYINIT is defined in the + * configuration then the board specific logic must provide + * imx_phyinitialize(); The i.MX RT Ethernet driver will call this + * function one time before it first uses the PHY. * * Input Parameters: * intf - Always zero for now. @@ -92,7 +93,7 @@ void up_netinitialize(void); * Returned Value: * OK on success; Negated errno on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMX_ENET_PHYINIT int imx_phy_boardinitialize(int intf); diff --git a/arch/arm/src/imx6/imx_gpio.c b/arch/arm/src/imx6/imx_gpio.c index fa4040f3112..be93d550474 100644 --- a/arch/arm/src/imx6/imx_gpio.c +++ b/arch/arm/src/imx6/imx_gpio.c @@ -318,7 +318,7 @@ static const uint8_t g_gpio7_padmux[IMX_GPIO_NPINS] = IMX_PADMUX_INVALID, /* GPIO6 Pin 31 */ }; -static FAR const uint8_t *g_gpio_padmux[IMX_GPIO_NPORTS+1] = +static FAR const uint8_t *g_gpio_padmux[IMX_GPIO_NPORTS + 1] = { g_gpio1_padmux, /* GPIO1 */ g_gpio2_padmux, /* GPIO2 */ @@ -559,13 +559,13 @@ int imx_config_gpio(gpio_pinset_t pinset) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: imx_gpio_write * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void imx_gpio_write(gpio_pinset_t pinset, bool value) { @@ -578,13 +578,13 @@ void imx_gpio_write(gpio_pinset_t pinset, bool value) leave_critical_section(flags); } -/************************************************************************************ +/**************************************************************************** * Name: imx_gpio_read * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool imx_gpio_read(gpio_pinset_t pinset) { diff --git a/arch/arm/src/imx6/imx_gpio.h b/arch/arm/src/imx6/imx_gpio.h index 39ae8522aca..3cba13ae0e0 100644 --- a/arch/arm/src/imx6/imx_gpio.h +++ b/arch/arm/src/imx6/imx_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/imx_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMX6_IMX_GPIO_H #define __ARCH_ARM_SRC_IMX6_IMX_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -32,9 +32,10 @@ #include "hardware/imx_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* 32-bit Encoding: * * ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM @@ -154,17 +155,17 @@ #define GPIO_IOMUX_SHIFT (0) /* Bits 0-15: IOMUX pin configuration */ #define GPIO_IOMUX_MASK (0xffff << GPIO_IOMUX_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* The smallest integer type that can hold the GPIO encoding */ typedef uint32_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -175,17 +176,18 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imx_gpioirq_initialize * * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMX6_GPIO_IRQ void imx_gpioirq_initialize(void); @@ -193,43 +195,43 @@ void imx_gpioirq_initialize(void); # define imx_gpio_irqinitialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: imx_config_gpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int imx_config_gpio(gpio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: imx_gpio_write * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void imx_gpio_write(gpio_pinset_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: imx_gpio_read * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool imx_gpio_read(gpio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: imx_gpioirq * * Description: * Configure an interrupt for the specified GPIO pin. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMX6_GPIO_IRQ void imx_gpioirq(gpio_pinset_t pinset); @@ -237,13 +239,13 @@ void imx_gpioirq(gpio_pinset_t pinset); # define imx_gpioirq(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: imx_gpioirq_enable * * Description: * Enable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMX6_GPIO_IRQ void imx_gpioirq_enable(int irq); @@ -251,13 +253,13 @@ void imx_gpioirq_enable(int irq); # define imx_gpioirq_enable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: imx_gpioirq_disable * * Description: * Disable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMX6_GPIO_IRQ void imx_gpioirq_disable(int irq); @@ -265,13 +267,14 @@ void imx_gpioirq_disable(int irq); # define imx_gpioirq_disable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Function: imx_dump_gpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int imx_dump_gpio(uint32_t pinset, const char *msg); diff --git a/arch/arm/src/imx6/imx_iomuxc.c b/arch/arm/src/imx6/imx_iomuxc.c index 0c45cfde1b7..a8f2802cb0c 100644 --- a/arch/arm/src/imx6/imx_iomuxc.c +++ b/arch/arm/src/imx6/imx_iomuxc.c @@ -35,6 +35,7 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* This table is indexed by the Pad Mux register index and provides the index * to the corresponding Pad Control register. * @@ -47,7 +48,9 @@ static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] = { - /* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */ + /* The first mappings are simple 1-to-1 mappings. + * This may be a little wasteful + */ IMX_PADCTL_SD2_DATA1_INDEX, /* IMX_PADMUX_SD2_DATA1_INDEX */ IMX_PADCTL_SD2_DATA2_INDEX, /* IMX_PADMUX_SD2_DATA2_INDEX */ @@ -139,7 +142,6 @@ static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] = IMX_PADCTL_DISP0_DATA14_INDEX, /* IMX_PADMUX_DISP0_DATA14_INDEX */ IMX_PADCTL_DISP0_DATA15_INDEX, /* IMX_PADMUX_DISP0_DATA15_INDEX */ - IMX_PADCTL_DISP0_DATA16_INDEX, /* IMX_PADMUX_DISP0_DATA16_INDEX */ IMX_PADCTL_DISP0_DATA17_INDEX, /* IMX_PADMUX_DISP0_DATA17_INDEX */ IMX_PADCTL_DISP0_DATA18_INDEX, /* IMX_PADMUX_DISP0_DATA18_INDEX */ @@ -159,55 +161,103 @@ static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] = IMX_PADCTL_ENET_TX_DATA0_INDEX, /* IMX_PADMUX_ENET_TX_DATA0_INDEX */ IMX_PADCTL_ENET_MDC_INDEX, /* IMX_PADMUX_ENET_MDC_INDEX */ - /* There is then a group of Pad Control registers with no Pad Mux register counterpart */ + /* There is then a group of Pad Control registers with no Pad Mux register + * counterpart + */ - /* IMX_PADCTL_DRAM_SDQS5_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_DQM5_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_DQM4_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDQS4_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDQS3_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_DQM3_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDQS2_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_DQM2_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR00_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR01_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR02_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR03_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR04_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR05_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR06_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR07_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR08_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR09_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR10_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR11_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR12_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR13_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR14_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ADDR15_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_CAS_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_CS0_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_CS1_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_RAS_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_RESET_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDBA0_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDBA1_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDCLK0_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDBA2_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDCKE0_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDCLK1_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDCKE1_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ODT0_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_ODT1_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDWE_B_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDQS0_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_DQM0_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDQS1_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_DQM1_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDQS6_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_DQM6_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_SDQS7_P_INDEX - No counterpart */ - /* IMX_PADCTL_DRAM_DQM7_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDQS5_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_DQM5_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_DQM4_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDQS4_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDQS3_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_DQM3_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDQS2_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_DQM2_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR00_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR01_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR02_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR03_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR04_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR05_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR06_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR07_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR08_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR09_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR10_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR11_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR12_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR13_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR14_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ADDR15_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_CAS_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_CS0_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_CS1_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_RAS_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_RESET_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDBA0_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDBA1_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDCLK0_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDBA2_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDCKE0_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDCLK1_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDCKE1_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ODT0_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_ODT1_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDWE_B_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDQS0_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_DQM0_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDQS1_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_DQM1_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDQS6_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_DQM6_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_SDQS7_P_INDEX - No counterpart */ + + /* IMX_PADCTL_DRAM_DQM7_INDEX - No counterpart */ /* The mapping is again 1-to-1 with an offset for the above registers that * have no Pad Mux register counterpart. @@ -258,14 +308,21 @@ static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] = IMX_PADCTL_CSI0_DATA18_INDEX, /* IMX_PADMUX_CSI0_DATA18_INDEX */ IMX_PADCTL_CSI0_DATA19_INDEX, /* IMX_PADMUX_CSI0_DATA19_INDEX */ - /* There is a second group of Pad Control registers with no Pad Mux register counterpart */ + /* There is a second group of Pad Control registers with no Pad Mux + * register counterpart + */ - /* IMX_PADCTL_JTAG_TMS_INDEX - No counterpart */ - /* IMX_PADCTL_JTAG_MOD_INDEX - No counterpart */ - /* IMX_PADCTL_JTAG_TRSTB_INDEX - No counterpart */ - /* IMX_PADCTL_JTAG_TDI_INDEX - No counterpart */ - /* IMX_PADCTL_JTAG_TCK_INDEX - No counterpart */ - /* IMX_PADCTL_JTAG_TDO_INDEX - No counterpart */ + /* IMX_PADCTL_JTAG_TMS_INDEX - No counterpart */ + + /* IMX_PADCTL_JTAG_MOD_INDEX - No counterpart */ + + /* IMX_PADCTL_JTAG_TRSTB_INDEX - No counterpart */ + + /* IMX_PADCTL_JTAG_TDI_INDEX - No counterpart */ + + /* IMX_PADCTL_JTAG_TCK_INDEX - No counterpart */ + + /* IMX_PADCTL_JTAG_TDO_INDEX - No counterpart */ /* The mapping is again 1-to-1 with an offset for the above registers that * have no Pad Mux register counterpart. diff --git a/arch/arm/src/imx6/imx_iomuxc.h b/arch/arm/src/imx6/imx_iomuxc.h index 4bed817d5f6..ba29ef59943 100644 --- a/arch/arm/src/imx6/imx_iomuxc.h +++ b/arch/arm/src/imx6/imx_iomuxc.h @@ -34,6 +34,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* 16-bit Encoding: * * .... RRRR ODDD LSST @@ -121,7 +122,7 @@ * Public Types ****************************************************************************/ - /* The smallest integer type that can hold the IOMUX encoding */ +/* The smallest integer type that can hold the IOMUX encoding */ typedef uint16_t iomux_pinset_t; diff --git a/arch/arm/src/imx6/imx_lowputc.c b/arch/arm/src/imx6/imx_lowputc.c index 3fe6420e868..ad39c39f2e1 100644 --- a/arch/arm/src/imx6/imx_lowputc.c +++ b/arch/arm/src/imx6/imx_lowputc.c @@ -46,6 +46,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifdef IMX_HAVE_UART_CONSOLE @@ -83,6 +84,7 @@ #endif /* Clocking *****************************************************************/ + /* the UART module receives two clocks, a peripheral_clock (ipg_clk) and the * module_clock (ipg_perclk). The peripheral_clock is used as write clock * of the TxFIFO, read clock of the RxFIFO and synchronization of the modem @@ -280,13 +282,13 @@ void imx_lowsetup(void) #endif /* CONFIG_SUPPRESS_UART_CONFIG */ } -/************************************************************************************ +/**************************************************************************** * Name: imx_uart_configure * * Description: * Configure a UART for non-interrupt driven operation * - ************************************************************************************/ + ****************************************************************************/ #ifdef IMX_HAVE_UART int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config) @@ -400,7 +402,7 @@ int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config) */ tmp = ((uint64_t)refclk << (16 - 4)) / config->baud; - DEBUGASSERT(tmp < 0x0000000100000000LL); + DEBUGASSERT(tmp < 0x0000000100000000ll); ratio = (b16_t)tmp; /* Pick a scale factor that gives us about 14 bits of accuracy. @@ -559,26 +561,29 @@ int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config) } #endif /* IMX_HAVE_UART */ -/************************************************************************************ +/**************************************************************************** * Name: imx_lowputc * * Description: - * Output a byte with as few system dependencies as possible. This will even work - * BEFORE the console is initialized if we are booting from U-Boot (and the same - * UART is used for the console, of course.) + * Output a byte with as few system dependencies as possible. This will + * even work BEFORE the console is initialized if we are booting from + * U-Boot (and the same UART is used for the console, of course.) * - ************************************************************************************/ + ****************************************************************************/ #if defined(IMX_HAVE_UART) && defined(CONFIG_DEBUG_FEATURES) void imx_lowputc(int ch) { - /* Poll the TX fifo trigger level bit of the UART status register. When the TXFE - * bit is non-zero, the TX Buffer FIFO is empty. + /* Poll the TX fifo trigger level bit of the UART status register. When the + * TXFE bit is non-zero, the TX Buffer FIFO is empty. */ - while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & UART_USR2_TXFE) == 0); + while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & + UART_USR2_TXFE) == 0); - /* If the character to output is a newline, then pre-pend a carriage return */ + /* If the character to output is a newline, then pre-pend a carriage + * return + */ if (ch == '\n') { @@ -586,21 +591,23 @@ void imx_lowputc(int ch) putreg32((uint32_t)'\r', IMX_CONSOLE_VBASE + UART_TXD_OFFSET); - /* Wait for the tranmsit register to be emptied. When the TXFE bit is non-zero, - * the TX Buffer FIFO is empty. + /* Wait for the tranmsit register to be emptied. When the TXFE bit is + * non-zero, the TX Buffer FIFO is empty. */ - while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & UART_USR2_TXFE) == 0); + while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & + UART_USR2_TXFE) == 0); } /* Send the character by writing it into the UART_TXD register. */ putreg32((uint32_t)ch, IMX_CONSOLE_VBASE + UART_TXD_OFFSET); - /* Wait for the tranmsit register to be emptied. When the TXFE bit is non-zero, - * the TX Buffer FIFO is empty. + /* Wait for the tranmsit register to be emptied. When the TXFE bit is + * non-zero, the TX Buffer FIFO is empty. */ - while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & UART_USR2_TXFE) == 0); + while ((getreg32(IMX_CONSOLE_VBASE + UART_USR2_OFFSET) & + UART_USR2_TXFE) == 0); } #endif diff --git a/arch/arm/src/imx6/imx_lowputc.h b/arch/arm/src/imx6/imx_lowputc.h index 6f390397483..265e1195cbb 100644 --- a/arch/arm/src/imx6/imx_lowputc.h +++ b/arch/arm/src/imx6/imx_lowputc.h @@ -68,27 +68,28 @@ struct uart_config_s void imx_lowsetup(void); -/************************************************************************************ +/**************************************************************************** * Name: imx_uart_configure * * Description: * Configure a UART for non-interrupt driven operation * - ************************************************************************************/ + ****************************************************************************/ #ifdef IMX_HAVE_UART -int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config); +int imx_uart_configure(uint32_t base, + FAR const struct uart_config_s *config); #endif -/************************************************************************************ +/**************************************************************************** * Name: imx_lowputc * * Description: - * Output a byte with as few system dependencies as possible. This will even work - * BEFORE the console is initialized if we are booting from U-Boot (and the same - * UART is used for the console, of course.) + * Output a byte with as few system dependencies as possible. + * This will even work BEFORE the console is initialized if we are booting + * from U-Boot (and the same UART is used for the console, of course.) * - ************************************************************************************/ + ****************************************************************************/ #if defined(IMX_HAVE_UART) && defined(CONFIG_DEBUG_FEATURES) void imx_lowputc(int ch); diff --git a/arch/arm/src/imx6/imx_memorymap.c b/arch/arm/src/imx6/imx_memorymap.c index 91a091fefce..e98f292f0f9 100644 --- a/arch/arm/src/imx6/imx_memorymap.c +++ b/arch/arm/src/imx6/imx_memorymap.c @@ -59,10 +59,10 @@ const struct section_mapping_s g_section_mapping[] = * reset, and until the Remap command is performed, the OCRAM is accessible * at address 0x0090 0000. * - * If we are executing from external SDRAM, then a secondary bootloader must - * have loaded us into SDRAM. In this case, simply set the VBAR register - * to the address of the vector table (not necessary at the beginning - * or SDRAM). + * If we are executing from external SDRAM, then a secondary bootloader + * must have loaded us into SDRAM. In this case, simply set the VBAR + * register to the address of the vector table (not necessary at the + * beginning or SDRAM). */ { IMX_ROMCP_PSECTION, IMX_ROMCP_VSECTION, /* Boot ROM (ROMCP) */ @@ -118,18 +118,19 @@ const struct section_mapping_s g_section_mapping[] = #endif /* i.MX6 External SDRAM Memory. The SDRAM is not usable until it has been - * initialized. If we are running out of SDRAM now, we can assume that some - * second level boot loader has properly configured SRAM for us. In that - * case, we set the MMU flags for the final, fully cache-able state. + * initialized. If we are running out of SDRAM now, we can assume that + * some second level boot loader has properly configured SRAM for us. + * In that case, we set the MMU flags for the final, fully cache-able + * state. * * Also, in this case, the mapping for the SDRAM was done in arm_head.S and * need not be repeated here. * - * If we are running from OCRAM or NOR flash, then we will need to configure - * the SDRAM ourselves. In this case, we set the MMU flags to the strongly - * ordered, non-cacheable state. We need this direct access to SDRAM in - * order to configure it. Once SDRAM has been initialized, it will be re- - * configured in its final state. + * If we are running from OCRAM or NOR flash, then we will need to + * configure the SDRAM ourselves. In this case, we set the MMU flags to + * the strongly ordered, non-cacheable state. We need this direct access + * to SDRAM in order to configure it. Once SDRAM has been initialized, it + * will be re- configured in its final state. */ #ifdef NEED_SDRAM_MAPPING @@ -145,9 +146,9 @@ const struct section_mapping_s g_section_mapping[] = /* LCDC Framebuffer. This entry reprograms a part of one of the above * regions, making it non-cacheable and non-buffereable. * - * If SDRAM will be reconfigured, then we will defer setup of the framebuffer - * until after the SDRAM remapping (since the framebuffer problem resides) in - * SDRAM. + * If SDRAM will be reconfigured, then we will defer setup of the + * framebuffer until after the SDRAM remapping (since the framebuffer + * problem resides) in SDRAM. */ #if defined(CONFIG_IMX6_LCDC) && !defined(NEED_SDRAM_REMAPPING) @@ -192,7 +193,6 @@ const struct section_mapping_s g_operational_mapping[] = MMU_IOFLAGS, IMX6_LCDC_FBNSECTIONS }, #endif - }; /* The number of entries in the operational mapping table */ @@ -203,3 +203,7 @@ const struct section_mapping_s g_operational_mapping[] = const size_t g_num_opmappings = NREMAPPINGS; #endif /* NEED_SDRAM_REMAPPING */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/imx6/imx_memorymap.h b/arch/arm/src/imx6/imx_memorymap.h index 0913b895b64..ea0f6580407 100644 --- a/arch/arm/src/imx6/imx_memorymap.h +++ b/arch/arm/src/imx6/imx_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imx6/imx_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMX6_IMX_MEMORYMAP_H #define __ARCH_ARM_SRC_IMX6_IMX_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "mmu.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* The vectors are, by default, positioned at the beginning of the text * section. Under what conditions do we have to remap these vectors? @@ -48,8 +48,8 @@ * is required because the vectors are position at the beginning of the * boot memory at link time and no additional MMU mapping required. * - * 2) We are not using a ROM page table. We cannot set any custom mappings in - * the case and the build must conform to the ROM page table properties + * 2) We are not using a ROM page table. We cannot set any custom mappings + * in the case and the build must conform to the ROM page table properties */ #if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_ARCH_ROMPGTABLE) @@ -74,11 +74,11 @@ # define NEED_SDRAM_REMAPPING 1 #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ - /* This table describes how to map a set of 1Mb pages to space the physical +/* This table describes how to map a set of 1Mb pages to space the physical * address space of the i.MX6. */ diff --git a/arch/arm/src/imx6/imx_timerisr.c b/arch/arm/src/imx6/imx_timerisr.c index 55216b58f30..c6cc333e99f 100644 --- a/arch/arm/src/imx6/imx_timerisr.c +++ b/arch/arm/src/imx6/imx_timerisr.c @@ -38,7 +38,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* The Peripheral Clock (ipg_clk) is selected as the GPT clock source. NOTE + +/* The Peripheral Clock (ipg_clk) is selected as the GPT clock source. + * NOTE * that the ipg_clk may be turned off in low power modes, stopping the timer * which is probably what you want. * diff --git a/arch/arm/src/imxrt/chip.h b/arch/arm/src/imxrt/chip.h index 009f4c9bf95..720c7ef5d3e 100644 --- a/arch/arm/src/imxrt/chip.h +++ b/arch/arm/src/imxrt/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_CHIP_H #define __ARCH_ARM_SRC_IMXRT_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the memory map and the chip definitions file. Other chip hardware files - * should then include this file for the proper setup. +/* Include the memory map and the chip definitions file. + * Other chip hardware files should then include this file for the proper + * setup. */ #include #include #include "hardware/imxrt_memorymap.h" -/* If the common ARMv7-M vector handling logic is used, then it expects the following - * definition in this file that provides the number of supported vectors external - * interrupts. +/* If the common ARMv7-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported + * vectors external interrupts. */ #define ARMV7M_PERIPHERAL_INTERRUPTS IMXRT_IRQ_NEXTINT @@ -47,20 +48,20 @@ #define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */ #define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMXRT_CHIP_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_adc.h b/arch/arm/src/imxrt/hardware/imxrt_adc.h index df307f385d5..f134bad0c4c 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_adc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_adc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_ADC_HC0_OFFSET 0x0000 /* Control register for hardware triggers */ #define IMXRT_ADC_HC1_OFFSET 0x0004 /* Control register for hardware triggers */ @@ -58,7 +58,7 @@ #define IMXRT_ADC_OFS_OFFSET 0x0054 /* Offset correction value register */ #define IMXRT_ADC_CAL_OFFSET 0x0058 /* Calibration value register */ -/* Register addresses ***************************************************************/ +/* Register addresses *******************************************************/ /* ADC1 Register Addresses */ @@ -112,7 +112,7 @@ #define IMXRT_ADC2_OFS (IMXRT_ADC2_BASE + IMXRT_ADC_OFS_OFFSET) /* ADC2 Offset correction value register */ #define IMXRT_ADC2_CAL (IMXRT_ADC2_BASE + IMXRT_ADC_CAL_OFFSET) /* ADC2 Calibration value register */ -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* Control register for hardware & SW triggers for n=0,1..7 */ @@ -139,7 +139,10 @@ # define ADC_HC_ADCH_VREFSH (25 << ADC_HC_ADCH_SHIFT) /* internal channel, for ADC self-test, hard connected to VRH internally */ # define ADC_HC_ADCH_DIS (31 << ADC_HC_ADCH_SHIFT) /* */ - /* Bits: 5-6 Reserved */ +/* Bits: 5-6 + * Reserved + */ + #define ADC_HC_AIEN (1 << 7) /* Bit: 7 Conversion Complete Interrupt Enable/Disable Control */ /* Bits: 8-31 Reserved */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_ccm.h b/arch/arm/src/imxrt/hardware/imxrt_ccm.h index 949e7b5737c..aa4fd281f3a 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_ccm.h +++ b/arch/arm/src/imxrt/hardware/imxrt_ccm.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_ccm.h * * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. @@ -33,14 +33,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_CCM_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_CCM_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" diff --git a/arch/arm/src/imxrt/hardware/imxrt_daisy.h b/arch/arm/src/imxrt/hardware/imxrt_daisy.h index c1938eadb85..174e05370af 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_daisy.h +++ b/arch/arm/src/imxrt/hardware/imxrt_daisy.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_daisy.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,29 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DAISY_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DAISY_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_daisy_select * * Description: * Initialize logic to support a daisy chain input selection for GPIO pins. * - ************************************************************************************/ + ****************************************************************************/ void imxrt_daisy_select(unsigned int index, unsigned int alt); diff --git a/arch/arm/src/imxrt/hardware/imxrt_dcdc.h b/arch/arm/src/imxrt/hardware/imxrt_dcdc.h index cfb73307949..4ec5fc48dff 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_dcdc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_dcdc.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_dcdc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,37 +31,37 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DCDC_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DCDC_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* Register offsets *********************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_DCDC_REG0_OFFSET 0x0000 /* DCDC Register 0 */ #define IMXRT_DCDC_REG1_OFFSET 0x0004 /* DCDC Register 1 */ #define IMXRT_DCDC_REG2_OFFSET 0x0008 /* DCDC Register 2 */ #define IMXRT_DCDC_REG3_OFFSET 0x000c /* DCDC Register 3 */ -/* Register addresses *******************************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_DCDC_REG0 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG0_OFFSET) #define IMXRT_DCDC_REG1 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG1_OFFSET) #define IMXRT_DCDC_REG2 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG2_OFFSET) #define IMXRT_DCDC_REG3 (IMXRT_DCDC_BASE + IMXRT_DCDC_REG3_OFFSET) -/* Register bit definitions *************************************************************************/ +/* Register bit definitions *************************************************/ /* Register 0 */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_edma.h b/arch/arm/src/imxrt/hardware/imxrt_edma.h index 9d11bc905ef..660521636ae 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_edma.h +++ b/arch/arm/src/imxrt/hardware/imxrt_edma.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_edma.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_EDMA_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_EDMA_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ #define IMXRT_EDMA_NCHANNELS 32 -/* eDMA Register Offsets ****************************************************************************/ +/* eDMA Register Offsets ****************************************************/ #define IMXRT_EDMA_CR_OFFSET 0x0000 /* Control */ #define IMXRT_EDMA_ES_OFFSET 0x0004 /* Error Status */ @@ -499,7 +499,7 @@ #define IMXRT_EDMA_TCD31_CSR_OFFSET 0x13fc /* TCD Control and Status */ #define IMXRT_EDMA_TCD31_BITER_ELINK_OFFSET 0x13fe /* TCD Beginning Minor Loop Link, Major Loop Count */ -/* eDMA Register Addresses **************************************************************************/ +/* eDMA Register Addresses **************************************************/ #define IMXRT_EDMA_CR (IMXRT_EDMA_BASE + IMXRT_EDMA_CR_OFFSET) #define IMXRT_EDMA_ES (IMXRT_EDMA_BASE + IMXRT_EDMA_ES_OFFSET) @@ -952,9 +952,10 @@ #define IMXRT_EDMA_TCD31_CSR (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_CSR_OFFSET) #define IMXRT_EDMA_TCD31_BITER_ELINK (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD31_BITER_ELINK_OFFSET) -/* eDMA Bit-Field Definitions ***********************************************************************/ +/* eDMA Bit-Field Definitions ***********************************************/ /* Control */ + /* Bit 0: Reserved */ #define EDMA_CR_EDBG (1 << 1) /* Bit 1: Enable Debug */ #define EDMA_CR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration */ @@ -1085,10 +1086,12 @@ #define EDMA_HRS(n) ((uint32_t)1 << (n)) /* Bit n: Hardware Request Status * Channel n */ + /* Enable Asynchronous Request in Stop */ #define EDMA_EARS(n) ((uint32_t)1 << (n)) /* Bit n: Enable asynchronous DMA * request in stop mode for channel n */ + /* Channel n Priority */ #define EDMA_DCHPRI_CHPRI_SHIFT (0) /* Bits 0-3: Channel n Arbitration Priority */ @@ -1101,6 +1104,7 @@ #define EDMA_DCHPRI_ECP (1 << 7) /* Bit 7: Enable Channel Preemption */ /* TCD Source Address (32-bit address) */ + /* TCD Signed Source Address Offset (16-bit offset) */ /* TCD Transfer Attributes */ @@ -1119,6 +1123,7 @@ # define EDMA_TCD_ATTR_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */ # define EDMA_TCD_ATTR_DSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 64-bit */ # define EDMA_TCD_ATTR_DSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-byte burst */ + #define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo */ #define EDMA_TCD_ATTR_DMOD_MASK (31 << EDMA_TCD_ATTR_DMOD_SHIFT) # define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT) @@ -1130,14 +1135,17 @@ # define EDMA_TCD_ATTR_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ # define EDMA_TCD_ATTR_SSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */ # define EDMA_TCD_ATTR_SSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte burst */ + #define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo */ #define EDMA_TCD_ATTR_SMOD_MASK (31 << EDMA_TCD_ATTR_SMOD_SHIFT) # define EDMA_TCD_ATTR_SMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SMOD_SHIFT) /* TCD Signed Minor Loop Offset / Byte Count */ + /* Minor Byte Count (Minor Loop Mapping Disabled -- 32-bit byte count) */ /* TCD Signed Minor Loop Offset / Byte Count */ + /* Minor Byte Count (Minor Loop Mapping Enabled, offset disabled) */ #define EDMA_TCD_NBYTES_ML_NBYTES_SHIFT (0) /* Bits 0-29: Minor Byte Transfer Count */ @@ -1147,6 +1155,7 @@ #define EDMA_TCD_NBYTES_ML_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */ /* TCD Signed Minor Loop Offset / Byte Count */ + /* Minor Byte Count (Minor Loop Mapping Enabled, offset enabled) */ #define EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT (0) /* Bits 0-9: Minor Byte Transfer Count */ @@ -1159,7 +1168,9 @@ #define EDMA_TCD_NBYTES_MLOFF_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */ /* TCD Last Source Address Adjustment (32-bit address adjustment) */ + /* TCD Destination Address (32-bit address) */ + /* TCD Signed Destination Address Offset (32-bit signed address offset) */ /* TCD Current Minor Loop Link, Major Loop Count (Channel linking disabled) */ @@ -1182,7 +1193,9 @@ #define EDMA_TCD_CITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking * on minor-loop complete */ -/* TCD Last Destination Address Adjustment/Scatter Gather Address (32-bit address) */ +/* TCD Last Destination Address Adjustment/Scatter Gather Address + * (32-bit address) + */ /* TCD Control and Status */ @@ -1209,7 +1222,9 @@ # define EDMA_TCD_CSR_BWC_8CYCLES (3 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 * cycles after each R/W */ -/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking disabled) */ +/* TCD Beginning Minor Loop Link, Major Loop Count + * (Channel linking disabled) + */ #define EDMA_TCD_BITER_BITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */ #define EDMA_TCD_BITER_BITER_MASK (0x7fff << EDMA_TCD_BITER_BITER_SHIFT) @@ -1217,7 +1232,9 @@ #define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking * on minor-loop complete */ -/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking enabled) */ +/* TCD Beginning Minor Loop Link, Major Loop Count + * (Channel linking enabled) + */ #define EDMA_TCD_BITER_ELINK_BITER_SHIFT (0) /* Bit 0-8: Current major iteration count */ #define EDMA_TCD_BITER_ELINK_BITER_MASK (0x1ff << EDMA_TCD_BITER_ELINK_BITER_SHIFT) @@ -1225,15 +1242,18 @@ #define EDMA_TCD_BITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-13: Link Channel Number */ #define EDMA_TCD_BITER_ELINK_LINKCH_MASK (31 << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT) # define EDMA_TCD_BITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT) + /* Bit 14: Reserved */ #define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking * on minor-loop complete */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/* In-memory representation of the 32-byte Transfer Control Descriptor (TCD) */ +/* In-memory representation of + * the 32-byte Transfer Control Descriptor (TCD) + */ struct imxrt_edmatcd_s { diff --git a/arch/arm/src/imxrt/hardware/imxrt_enc.h b/arch/arm/src/imxrt/hardware/imxrt_enc.h index 9a3cb77fd0f..5b2f0d201fb 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_enc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_enc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_enc.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -31,24 +31,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENC_H #define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *************************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_ENC_CTRL_OFFSET 0x0000 /* Control Register Offset */ #define IMXRT_ENC_FILT_OFFSET 0x0002 /* Input Filter Register Offset */ @@ -71,7 +71,7 @@ #define IMXRT_ENC_UCOMP_OFFSET 0x0024 /* Upper Compare Register Offset */ #define IMXRT_ENC_LCOMP_OFFSET 0x0026 /* Lower Compare Register Offset */ -/* Register Addresses ***********************************************************************/ +/* Register Addresses *******************************************************/ /* ENC1 Registers */ @@ -165,7 +165,7 @@ #define IMXRT_ENC4_UCOMP (IMXRT_ENC4_BASE + IMXRT_ENC_UCOMP_OFFSET) /* Upper Compare Register */ #define IMXRT_ENC4_LCOMP (IMXRT_ENC4_BASE + IMXRT_ENC_LCOMP_OFFSET) /* Lower Compare Register */ -/* Register Bit Definitions *****************************************************************/ +/* Register Bit Definitions *************************************************/ /* Control Register */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_enet.h b/arch/arm/src/imxrt/hardware/imxrt_enet.h index 3d1cae7fa19..5dbaf0934a2 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_enet.h +++ b/arch/arm/src/imxrt/hardware/imxrt_enet.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_enet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ENET_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ENET_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/* Register Offsets **********************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */ #define IMXRT_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */ @@ -88,7 +88,7 @@ #define IMXRT_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */ #define IMXRT_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */ -/* Register Addresses ********************************************************/ +/* Register Addresses *******************************************************/ #define IMXRT_ENET_EIR (IMXRT_ENET_BASE+IMXRT_ENET_EIR_OFFSET) #define IMXRT_ENET_EIMR (IMXRT_ENET_BASE+IMXRT_ENET_EIMR_OFFSET) @@ -141,9 +141,10 @@ #define IMXRT_ENET_TCSR3 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR3_OFFSET) #define IMXRT_ENET_TCCR3 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR3_OFFSET) -/* Register Bit Definitions **************************************************/ +/* Register Bit Definitions *************************************************/ /* Interrupt Event Register, Interrupt Mask Register */ + /* Bits 0-14: Reserved */ #define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */ #define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */ @@ -162,14 +163,19 @@ #define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */ #define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */ /* Bit 31: Reserved */ + /* Receive Descriptor Active Register */ + /* Bits 0-23: Reserved */ #define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */ /* Bits 25-31: Reserved */ + /* Transmit Descriptor Active Register */ + /* Bits 0-23: Reserved */ #define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */ /* Bits 25-31: Reserved */ + /* Ethernet Control Register */ #define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */ @@ -202,10 +208,12 @@ # define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */ # define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */ # define ENET_MMFR_OP_RdNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */ + #define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */ #define ENET_MMFR_ST_MASK (3 << ENET_MMFR_ST_SHIFT) /* MII Speed Control Register */ + /* Bit 0: Reserved */ #define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */ #define ENET_MSCR_MII_SPEED_MASK (63 << ENET_MSCR_MII_SPEED_SHIFT) @@ -216,8 +224,11 @@ # define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */ # define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */ # define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */ + /* Bits 11-31: Reserved */ + /* MIB Control Register */ + /* Bits 0-28: Reserved */ #define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */ #define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */ @@ -255,9 +266,12 @@ #define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */ #define ENET_TCR_ADDSEL_MASK (7 << ENET_TCR_ADDSEL_SHIFT) # define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT) /* Node MAC address programmed on PADDR1/2 registers */ + #define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */ /* Bits 10-31: Reserved */ + /* Physical Address Lower/Upper Register (32-bits of 48-address) */ + /* Physical Address Upper Register */ #define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */ @@ -272,8 +286,13 @@ #define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */ #define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT) -/* Descriptor Individual Upper/Lower Address Register (64-bit address in two 32-bit registers) */ -/* Descriptor Group Upper/Lower Address Register (64-bit address in two 32-bit registers) */ +/* Descriptor Individual Upper/Lower Address Register + * (64-bit address in two 32-bit registers) + */ + +/* Descriptor Group Upper/Lower Address Register + * (64-bit address in two 32-bit registers) + */ /* Transmit Interrupt Coalescing Register */ @@ -302,22 +321,28 @@ #define ENET_TFWR_TFWR_MASK (63 << ENET_TFWR_TFWR_SHIFT) #define ENET_TFWR_STRFWD (1 << 8) /* Bit 8: Store and forward enable */ /* Bits 9-31: Reserved */ + /* Receive Descriptor Ring Start Register */ + /* Bits 0-2: Reserved */ #define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */ #define ENET_RDSR_MASK (0xfffffff8) /* Transmit Buffer Descriptor Ring Start Register */ + /* Bits 0-2: Reserved */ #define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */ #define ENET_TDSR_MASK (0xfffffff8) /* Maximum Receive Buffer Size Register */ + /* Bits 14-31: Reserved */ #define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */ #define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT) /* Bits 0-3: Reserved */ + /* Receive FIFO Section Full Threshold */ + /* Bits 8-31: Reserved */ #define ENET_RSFL_SHIFT (0) /* Bits 0-7: Value of receive FIFO section full threshold */ #define ENET_RSFL_MASK (0xff << ENET_RSFL_SHIFT) @@ -327,41 +352,49 @@ #define ENET_RSEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO section empty threshold */ #define ENET_RSEM_MASK (0xff << ENET_RSEM_SHIFT) /* Bits 8-31: Reserved */ + /* Receive FIFO Almost Empty Threshold */ #define ENET_RAEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost empty threshold */ #define ENET_RAEM_MASK (0xff << ENET_RAEM_SHIFT) /* Bits 8-31: Reserved */ + /* Receive FIFO Almost Full Threshold */ #define ENET_RAFL_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost full threshold */ #define ENET_RAFL_MASK (0xff << ENET_RAFL_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit FIFO Section Empty Threshold */ #define ENET_TSEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ #define ENET_TSEM_MASK (0xff << ENET_TSEM_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit FIFO Almost Empty Threshold */ #define ENET_TAEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ #define ENET_TAEM_MASK (0xff << ENET_TAEM_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit FIFO Almost Full Threshold */ #define ENET_TAFL_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */ #define ENET_TAFL_MASK (0xff << ENET_TAFL_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit Inter-Packet Gap */ #define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */ #define ENET_TIPG_MASK (31 << ENET_TIPG_SHIFT) /* Bits 5-31: Reserved */ + /* Frame Truncation Length */ #define ENET_FTRL_SHIFT (0) /* Bits 0-13: Value of the transmit FIFO section empty threshold */ #define ENET_FTRL_MASK (0x3fff << ENET_FTRL_SHIFT) /* Bits 14-31: Reserved */ + /* Transmit Accelerator Function Configuration */ #define ENET_TACC_SHIFT16 (1 << 0) /* Bit 0: TX FIFO shift-16 */ @@ -369,6 +402,7 @@ #define ENET_TACC_IPCHK (1 << 3) /* Bit 3: Enables insertion of IP header checksum */ #define ENET_TACC_PROCHK (1 << 4) /* Bit 4: Enables insertion of protocol checksum */ /* Bits 5-31: Reserved */ + /* Receive Accelerator Function Configuration */ #define ENET_RACC_PADREM (1 << 0) /* Bit 0: Enable padding removal for short IP frames */ @@ -378,6 +412,7 @@ #define ENET_RACC_LINEDIS (1 << 6) /* Bit 6: Enable discard of frames with MAC layer errors */ #define ENET_RACC_SHIFT16 (1 << 7) /* Bit 7: RX FIFO shift-16 */ /* Bits 8-31: Reserved */ + /* Timer Control Register */ #define ENET_ATCR_EN (1 << 0) /* Bit 0: Enable timer */ @@ -394,14 +429,18 @@ /* Bit 12: Reserved */ #define ENET_ATCR_SLAVE (1 << 13) /* Bit 13: Enable timer slave mode */ /* Bits 14-31: Reserved */ + /* Timer Value Register (32-bit timer value) */ + /* Timer Offset Register (32-bit offset value) */ + /* Timer Period Register (32-bit timer period) */ /* Timer Correction Register */ #define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */ - /* Bit 31: Reserved */ + /* Bit 31: Reserved */ + /* Time-Stamping Clock Period Register */ #define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */ @@ -410,6 +449,7 @@ #define ENET_ATINC_INC_CORR_SHIFT (8) /* Bits 8-14: Correction increment value */ #define ENET_ATINC_INC_CORR_MASK (0x7f << ENET_ATINC_INC_CORR_SHIFT) /* Bits 15-31: Reserved */ + /* Timestamp of Last Transmitted Frame (32-bit timestamp) */ /* Timer Global Status Register */ @@ -419,6 +459,7 @@ #define ENET_TGSR_TF2 (1 << 2) /* Bit 2: Copy of Timer Flag for channel 2 */ #define ENET_TGSR_TF3 (1 << 3) /* Bit 3: Copy of Timer Flag for channel 3 */ /* Bits 14-31: Reserved */ + /* Timer Control Status Register n */ #define ENET_TCSR_TDRE (1 << 0) /* Bit 0: Timer DMA Request Enable */ @@ -437,12 +478,15 @@ # define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */ # define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */ # define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */ + #define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */ #define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */ /* Bits 8-31: Reserved */ + /* Timer Compare Capture Register (32-bit compare value) */ -/* Buffer Descriptors ********************************************************/ +/* Buffer Descriptors *******************************************************/ + /* Endian-independent descriptor offsets */ #define DESC_STATUS1_OFFSET (0) @@ -588,11 +632,11 @@ # define RXDESC_BDU (1 << 7) #endif -/***************************************************************************** +/**************************************************************************** * Public Types - *****************************************************************************/ + ****************************************************************************/ -/* Buffer Descriptors ********************************************************/ +/* Buffer Descriptors *******************************************************/ /* Legacy Buffer Descriptor */ @@ -649,12 +693,12 @@ struct enet_desc_s #endif /* IMXRT_USE_DBSWAP */ #endif /* CONFIG_ENET_ENHANCEDBD */ -/***************************************************************************** +/**************************************************************************** * Public Data - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** - * Public Functions - *****************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ENET_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_gpio.h b/arch/arm/src/imxrt/hardware/imxrt_gpio.h index efbfe95cf91..40df452b238 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_gpio.h +++ b/arch/arm/src/imxrt/hardware/imxrt_gpio.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPIO_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPIO_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include @@ -37,9 +37,9 @@ # error Unrecognized i.MX RT architecture #endif -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ #define GPIO1 0 /* Port 1 index */ #define GPIO2 1 /* Port 2 index */ @@ -54,7 +54,7 @@ #endif #define IMXRT_GPIO_NPINS 32 /* Up to 32 pins per port */ -/* Register bit definitions *****************************************************************/ +/* Register bit definitions *************************************************/ /* Most registers are laid out simply with one bit per pin */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h index 2e9f1d28ba7..26b18b2affc 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_iomuxc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_IOMUXC_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_IOMUXC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -37,9 +37,9 @@ # error Unrecognized i.MX RT architecture #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Pad Mux Registers */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_lcd.h b/arch/arm/src/imxrt/hardware/imxrt_lcd.h index c77685ff345..97e060ee259 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_lcd.h +++ b/arch/arm/src/imxrt/hardware/imxrt_lcd.h @@ -1,4 +1,4 @@ -/************************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_lcd.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -32,23 +32,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LCD_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LCD_H -/************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_LCDIF_CTRL_OFFSET 0x0000 /* General Control Register */ #define IMXRT_LCDIF_CTRL_SET_OFFSET 0x0004 /* General Control Register */ @@ -105,7 +105,7 @@ #define IMXRT_LCDIF_LUT1_ADDR_OFFSET 0x0b30 /* Lookup Table Control Register */ #define IMXRT_LCDIF_LUT1_DATA_OFFSET 0x0b40 /* Lookup Table Data Register */ -/* Register Addresses ***************************************************************************/ +/* Register Addresses *******************************************************/ #define IMXRT_LCDIF_CTRL (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_OFFSET) #define IMXRT_LCDIF_CTRL_SET (IMXRT_LCDIF_BASE + IMXRT_LCDIF_CTRL_SET_OFFSET) @@ -159,7 +159,7 @@ #define IMXRT_LCDIF_LUT1_DATA (IMXRT_LCDIF_BASE + IMXRT_LCDIF_LUT1_DATA_OFFSET) #define IMXRT_LCDIF_LUT_ENTRY_NUM (256) -/* Register Bitfield Definitions ****************************************************************/ +/* Register Bitfield Definitions ********************************************/ /* CTRL - LCDIF General Control Register */ @@ -168,16 +168,25 @@ #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) + /* DATA_FORMAT_24_BIT - * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. - * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 + * data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color + * per byte, hence the upper 2 bits in each byte do not contain + * any useful data, and should be dropped. */ #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) + /* DATA_FORMAT_18_BIT - * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. - * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 + * bits contain RGB 666 and upper 14 bits do not contain any + * useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 + * bits contain RGB 666 and lower 14 bits do not contain any + * useful data. */ #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) @@ -272,8 +281,11 @@ #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) /* DATA_FORMAT_24_BIT - * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. - * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 + * data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color + * per byte, hence the upper 2 bits in each byte do not contain + * any useful data, and should be dropped. */ #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) @@ -281,8 +293,12 @@ #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) /* DATA_FORMAT_18_BIT - * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. - * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 + * bits contain RGB 666 and upper 14 bits do not contain any + * useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 + * bits contain RGB 666 and lower 14 bits do not contain any + * useful data. */ #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) @@ -380,8 +396,11 @@ #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) /* DATA_FORMAT_24_BIT - * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. - * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 + * data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 + * color per byte, hence the upper 2 bits in each byte do not + * contain any useful data, and should be dropped. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) @@ -389,8 +408,12 @@ #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) /* DATA_FORMAT_18_BIT - * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. - * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 + * bits contain RGB 666 and upper 14 bits do not contain any + * useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 + * bits contain RGB 666 and lower 14 bits do not contain any + * useful data. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) @@ -488,8 +511,11 @@ #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) /* DATA_FORMAT_24_BIT - * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. - * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. + * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 + * data is contained in 24 bits. + * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 + * color per byte, hence the upper 2 bits in each byte do not + * contain any useful data, and should be dropped. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) @@ -497,8 +523,12 @@ #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) /* DATA_FORMAT_18_BIT - * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. - * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. + * 0b0..Data input to the block is in 18 bpp format, such that lower 18 + * bits contain RGB 666 and upper 14 bits do not contain any + * useful data. + * 0b1..Data input to the block is in 18 bpp format, such that upper 18 + * bits contain RGB 666 and lower 14 bits do not contain any + * useful data. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) diff --git a/arch/arm/src/imxrt/hardware/imxrt_lpi2c.h b/arch/arm/src/imxrt/hardware/imxrt_lpi2c.h index ff293f93677..c00964daccf 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_lpi2c.h +++ b/arch/arm/src/imxrt/hardware/imxrt_lpi2c.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_lpi2c.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,22 +31,22 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPI2C_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPI2C_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_LPI2C_VERID_OFFSET 0x0000 /* Version ID Register offset */ #define IMXRT_LPI2C_PARAM_OFFSET 0x0004 /* Parameter Register offset */ @@ -77,7 +77,7 @@ #define IMXRT_LPI2C_STDR_OFFSET 0x0160 /* Slave Transmit Data Register offset */ #define IMXRT_LPI2C_SRDR_OFFSET 0x0170 /* Slave Receive Data Register offset */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ /* LPI2C1 Registers */ @@ -203,7 +203,7 @@ #define IMXRT_LPI2C4_STDR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ #define IMXRT_LPI2C4_SRDR (IMXRT_LPI2C4_BASE + IMXRT_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ -/* Register bit definitions *****************************************************************/ +/* Register bit definitions *************************************************/ /* LPI2C Version ID Register */ @@ -328,7 +328,7 @@ #define LPI2C_MCFGR1_AUTOSTOP (1 << 8) /* Automatic STOP Generation Bit */ #define LPI2C_MCFGR1_IGNACK (1 << 9) /* Ignore NACK Bit */ #define LPI2C_MCFGR1_TIMECFG (1 << 10) /* Timeout Configuration Bit */ - /* Bits 15-11 Reserved */ + /* Bits 15-11 Reserved */ #define LPI2C_MCFGR1_MATCFG_SHIFT (16) #define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */ #define LPI2C_MCFGR1_MATCFG(n) ((n << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK) @@ -370,6 +370,7 @@ #define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT) #define LPI2C_MCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK) /* Bits 31-28 Reserved */ + /* LPI2C Master Config Register 3 */ /* Bits 7-0 Reserved */ @@ -421,30 +422,38 @@ #define LPI2C_MCCR1_SETHOLD_SHIFT (16) #define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT) /* Setup Hold Delay */ #define LPI2C_MCCR1_SETHOLD(n) ((n << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK) + /* Bits 23-22 Reserved */ #define LPI2C_MCCR1_DATAVD_SHIFT (24) #define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT) /* Setup Hold Delay */ #define LPI2C_MCCR1_DATAVD(n) ((n << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK) + /* Bits 31-30 Reserved */ /* LPI2C Master FIFO Control Register */ #define LPI2C_MFCR_TXWATER_SHIFT (0) #define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/ -#define LPI2C_MFCR_TXWATER(n) ((n << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark*/ + +#define LPI2C_MFCR_TXWATER(n) ((n << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark */ + /* Bits 15-2 Reserved */ #define LPI2C_MFCR_RXWATER_SHIFT (16) #define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */ -#define LPI2C_MFCR_RXWATER(n) ((n << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark*/ + +#define LPI2C_MFCR_RXWATER(n) ((n << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark */ + /* Bits 31-18 Reserved */ /* LPI2C Master FIFO Status Register */ #define LPI2C_MFSR_TXCOUNT_SHIFT (0) #define LPI2C_MFSR_TXCOUNT_MASK (3 << LPI2C_MFSR_TXCOUNT_SHIFT) /* Transmit FIFO Count */ + /* Bits 15-2 Reserved */ #define LPI2C_MFSR_RXCOUNT_SHIFT (16) #define LPI2C_MFSR_RXCOUNT_MASK (3 << LPI2C_MFSR_RXCOUNT_SHIFT) /* Receive FIFO Count */ + /* Bits 31-18 Reserved */ /* LPI2C Master Transmit Data Register */ @@ -463,15 +472,18 @@ # define LPI2C_MTDR_CMD_START_NACK (5 << LPI2C_MTDR_CMD_SHIFT) # define LPI2C_MTDR_CMD_START_HI (6 << LPI2C_MTDR_CMD_SHIFT) # define LPI2C_MTDR_CMD_START_HI_NACK (7 << LPI2C_MTDR_CMD_SHIFT) + /* Bits 31-11 Reserved */ /* LPI2C Master Receive Data Register */ #define LPI2C_MRDR_DATA_SHIFT (0) #define LPI2C_MRDR_DATA_MASK (0xff << LPI2C_MRDR_DATA_SHIFT) /* Receive Data */ + /* Bits 13-8 Reserved */ #define LPI2C_MRDR_RXEMPTY_SHIFT (14) #define LPI2C_MRDR_RXEMPTY_MASK (1 << LPI2C_MRDR_RXEMPTY_SHIFT) /* Rx Empty */ + /* Bits 31-15 Reserved */ /* LPI2C Slave Control Register */ @@ -592,7 +604,11 @@ /* LPI2C Slave Address Status Register */ #define LPI2C_SASR_RADDR_MASK (0x7ff << 0) /* Received Address */ - /* Bits 16-11 Reserved */ + +/* Bits 16-11 + * Reserved + */ + #define LPI2C_SASR_ANV (1 << 14) /* Address Not Valid */ /* Bits 31-15 Reserved */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_lpspi.h b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h index 3f8e69d41ef..7e648420147 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_lpspi.h +++ b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_lpspi.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,23 +31,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPSPI_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPSPI_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_LPSPI_VERID_OFFSET 0x0000 /* Version ID Register offset */ #define IMXRT_LPSPI_PARAM_OFFSET 0x0004 /* Parameter Register offset */ @@ -67,7 +67,7 @@ #define IMXRT_LPSPI_RSR_OFFSET 0x0070 /* Receive Status Register offset */ #define IMXRT_LPSPI_RDR_OFFSET 0x0074 /* Receive Data Register offset */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_LPSPI1_VERID (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_VERID_OFFSET) #define IMXRT_LPSPI1_PARAM (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_PARAM_OFFSET) @@ -141,7 +141,7 @@ #define IMXRT_LPSPI4_RSR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_RSR_OFFSET) #define IMXRT_LPSPI4_RDR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_RDR_OFFSET) -/* Register bit definitions *****************************************************************/ +/* Register bit definitions *************************************************/ /* Version ID Register */ @@ -238,6 +238,7 @@ #define LPSPI_CFGR1_PCSPOL_MASK (0xf << LPSPI_CFGR1_PCSPOL_SHIFT) # define LPSPI_CFGR1_PCSPOL_LOW (0 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active low */ # define LPSPI_CFGR1_PCSPOL_HIGH (1 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active high */ + /* Bits 12-15: Reserved */ #define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration */ #define LPSPI_CFGR1_MATCFG_MASK (7 << LPSPI_CFGR1_MATCFG_SHIFT) @@ -250,13 +251,14 @@ # define LPSPI_CFGR1_PINCFG_SOUT_SOUT (2 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */ # define LPSPI_CFGR1_PINCFG_SOUT_SIN (3 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */ # define LPSPI_CFGR1_PINCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_PINCFG_SHIFT) -#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config */ -# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */ + +#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config */ +# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */ # define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */ -#define LPSPI_CFGR1_PCSCFG (1 << 27) /* Bit 27: Peripheral Chip Select Configuration */ -# define LPSPI_CFGR1_PCSCFG_EN (0 << 27) /* PCS[3:2] are enabled */ -# define LPSPI_CFGR1_PCSCFG_DIS (1 << 27) /* PCS[3:2] are disabled */ - /* Bits 28-31: Reserved */ +#define LPSPI_CFGR1_PCSCFG (1 << 27) /* Bit 27: Peripheral Chip Select Configuration */ +# define LPSPI_CFGR1_PCSCFG_EN (0 << 27) /* PCS[3:2] are enabled */ +# define LPSPI_CFGR1_PCSCFG_DIS (1 << 27) /* PCS[3:2] are disabled */ + /* Bits 28-31: Reserved */ /* Data Match Register 0 */ @@ -320,6 +322,7 @@ # define LPSPI_TCR_WIDTH_1BIT (0 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */ # define LPSPI_TCR_WIDTH_2BIT (1 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */ # define LPSPI_TCR_WIDTH_4BIT (2 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */ + #define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask */ #define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask */ #define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command */ @@ -333,6 +336,7 @@ # define LPSPI_TCR_PCS_1 (1 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[1] */ # define LPSPI_TCR_PCS_2 (2 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[2] */ # define LPSPI_TCR_PCS_3 (3 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[3] */ + /* Bit 26: Reserved */ #define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value */ #define LPSPI_TCR_PRESCALE_MASK (7 << LPSPI_TCR_PRESCALE_SHIFT) @@ -345,6 +349,7 @@ # define LPSPI_TCR_PRESCALE_64 (6 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */ # define LPSPI_TCR_PRESCALE_128 (7 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */ # define LPSPI_TCR_PRESCALE(n) ((uint32_t)(n) << LPSPI_TCR_PRESCALE_SHIFT) + #define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase */ # define LPSPI_TCR_CPHA_CPT_LEAD (0 << 30) /* Data captured - leading edge of SCK and changed - following edge of SCK */ # define LPSPI_TCR_CPHA_CPT_FOLLOW (1 << 30) /* Data changed - leading edge of SCK and captured - following edge of SCK */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_lpuart.h b/arch/arm/src/imxrt/hardware/imxrt_lpuart.h index 1b0c2bc606c..e93b82bbb26 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_lpuart.h +++ b/arch/arm/src/imxrt/hardware/imxrt_lpuart.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_lpuart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPUART_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPUART_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_LPUART_VERID_OFFSET 0x0000 /* Version ID Register */ #define IMXRT_LPUART_PARAM_OFFSET 0x0004 /* Parameter Register */ @@ -47,7 +47,7 @@ #define IMXRT_LPUART_FIFO_OFFSET 0x0028 /* LPUART FIFO Register */ #define IMXRT_LPUART_WATER_OFFSET 0x002c /* LPUART Watermark Register */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_LPUART1_VERID (IMXRT_LPUART1_BASE + IMXRT_LPUART_VERID_OFFSET) #define IMXRT_LPUART1_PARAM (IMXRT_LPUART1_BASE + IMXRT_LPUART_PARAM_OFFSET) @@ -153,7 +153,7 @@ #define IMXRT_LPUART8_FIFO (IMXRT_LPUART8_BASE + IMXRT_LPUART_FIFO_OFFSET) #define IMXRT_LPUART8_WATER (IMXRT_LPUART8_BASE + IMXRT_LPUART_WATER_OFFSET) -/* Register bit definitions *****************************************************************/ +/* Register bit definitions *************************************************/ /* Version ID Register */ @@ -161,6 +161,7 @@ #define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT) # define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */ # define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */ + #define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */ #define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT) #define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */ @@ -188,6 +189,7 @@ # define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */ # define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */ # define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */ + /* Bits 2-31: Reserved */ /* LPUART Baud Rate Register */ @@ -207,6 +209,7 @@ # define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */ # define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match * On/Off for transmitter CTS input */ + /* Bit 20: Reserved */ #define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable */ /* Bit 22: Reserved */ @@ -262,6 +265,7 @@ # define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */ # define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */ # define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */ + #define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select */ /* Bits 12-13: Reserved */ #define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable */ @@ -332,6 +336,7 @@ #define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse */ #define LPUART_MODIR_TNP_MASK (3 << LPUART_MODIR_TNP_SHIFT) # define LPUART_MODIR_TNP(n) ((uint32_t)((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */ + #define LPUART_MODIR_IREN (1 << 18) /* Bit nn: Infrared enable */ /* Bits 19-31: Reserved */ @@ -347,6 +352,7 @@ # define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */ # define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */ # define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */ + #define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable */ #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO. Buffer Depth */ #define LPUART_FIFO_TXFIFOSIZE_MASK (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) diff --git a/arch/arm/src/imxrt/hardware/imxrt_memorymap.h b/arch/arm/src/imxrt/hardware/imxrt_memorymap.h index 02ebb46cfed..d646f76bb44 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_memorymap.h +++ b/arch/arm/src/imxrt/hardware/imxrt_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_MEMORYMAP_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/imxrt/hardware/imxrt_pinmux.h b/arch/arm/src/imxrt/hardware/imxrt_pinmux.h index 6d256a10f0f..7fb5081d460 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_pinmux.h +++ b/arch/arm/src/imxrt/hardware/imxrt_pinmux.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PINMUX_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PINMUX_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/imxrt/hardware/imxrt_pit.h b/arch/arm/src/imxrt/hardware/imxrt_pit.h index 36ba4d0ecc4..85c7c764b87 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_pit.h +++ b/arch/arm/src/imxrt/hardware/imxrt_pit.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_pit.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PIT_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PIT_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */ #define IMXRT_PIT_LTMR64H_OFFSET 0x00e0 /* PIT Upper Lifetime Timer Register */ @@ -54,7 +54,7 @@ #define IMXRT_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */ #define IMXRT_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define IMXRT_PIT_MCR (IMXRT_PIT_BASE+IMXRT_PIT_MCR_OFFSET) #define IMXRT_PIT_LTMR64H (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64H_OFFSET) @@ -76,7 +76,7 @@ #define IMXRT_PIT_TCTRL3 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL3_OFFSET) #define IMXRT_PIT_TFLG3 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG3_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* PIT Module Control Register */ @@ -101,16 +101,16 @@ #define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */ /* Bits 1-31: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Functions Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PIT_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_snvs.h b/arch/arm/src/imxrt/hardware/imxrt_snvs.h index eb2ad5f48b5..791148a3d8c 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_snvs.h +++ b/arch/arm/src/imxrt/hardware/imxrt_snvs.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_snvs.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SNVS_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SNVS_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ #define IMXRT_SNVS_LP_MAXTAMPER 10 -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_SNVS_HPLR_OFFSET 0x0000 /* SNVS_HP Lock Register */ #define IMXRT_SNVS_HPCOMR_OFFSET 0x0004 /* SNVS_HP Command Register */ @@ -67,7 +67,7 @@ #define IMXRT_SNVS_HPVIDR1_OFFSET 0x0bf8 /* SNVS_HP Version ID Register 1 */ #define IMXRT_SNVS_HPVIDR2_OFFSET 0x0bfc /* SNVS_HP Version ID Register 2 */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_SNVS_HPLR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPLR_OFFSET) #define IMXRT_SNVS_HPCOMR (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPCOMR_OFFSET) @@ -100,7 +100,7 @@ #define IMXRT_SNVS_HPVIDR1 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPVIDR1_OFFSET) #define IMXRT_SNVS_HPVIDR2 (IMXRT_SNVSHP_BASE + IMXRT_SNVS_HPVIDR2_OFFSET) -/* Register bit definitions *****************************************************************/ +/* Register bit definitions *************************************************/ /* SNVS_HP Lock Register */ @@ -142,6 +142,7 @@ # define SNVS_HPCR_HPCALBVAL_M15 (17 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -15 counts per 32768 ticks */ # define SNVS_HPCR_HPCALBVAL_M2 (30 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -2 counts per 32768 ticks */ # define SNVS_HPCR_HPCALBVAL_M1 (31 << SNVS_HPCR_HPCALBVAL_SHIFT) /* -1 counts per 32768 ticks */ + /* Bits 15: Reserved */ #define SNVS_HPCR_HPTS (1 << 16) /* Bit 16: LPSRTC time sychronization */ /* Bits 17-23: Reserved */ @@ -152,6 +153,7 @@ # define SNVS_HPCR_BTNCONFIG_RISING (2 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on rising edge */ # define SNVS_HPCR_BTNCONFIG_FALLING (3 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on falling edge */ # define SNVS_HPCR_BTNCONFIG_BOTH (4 << SNVS_HPCR_BTNCONFIG_SHIFT) /* Button signal active on any edge */ + #define SNVS_HPCR_BTNMASK (1 << 27) /* Bit 27: Button interrupt mask */ /* Bits 28-31: Reserved */ @@ -167,11 +169,13 @@ /* Bits 8-31: Reserved */ /* SNVS_HP Real Time Counter MSB Register (15-bit MSB of counter) */ + /* SNVS_HP Real Time Counter LSB Register (32-bit LSB of counter) */ #define SNVS_HPRTCMR_MASK 0x00007fff /* Bits 0-14: HP Real Time Counter */ /* SNVS_HP Time Alarm MSB Register (15-bit MSB of counter) */ + /* SNVS_HP Time Alarm LSB Register (32-bit LSB of counter) */ #define SNVS_HPTAMR_MASK 0x00007fff /* Bits 0-14: HP Time Alarm, most-significant 15 bits */ @@ -207,6 +211,7 @@ # define SNVS_LPCR_LPCALBVAL_M15 (17 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -15 counts per 32768 ticks */ # define SNVS_LPCR_LPCALBVAL_M2 (30 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -2 counts per 32768 ticks */ # define SNVS_LPCR_LPCALBVAL_M1 (31 << SNVS_LPCR_LPCALBVAL_SHIFT) /* -1 counts per 32768 ticks */ + /* Bit 15: Reserved */ #define SNVS_LPCR_BTNPRESSTIME_SHIFT (16) /* Bits 16-17: PMIC button press time out values */ #define SNVS_LPCR_BTNPRESSTIME_MASK (3 << SNVS_LPCR_BTNPRESSTIME_SHIFT) @@ -214,18 +219,21 @@ # define SNVS_LPCR_BTNPRESSTIME_10SEC (1 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 10 secs */ # define SNVS_LPCR_BTNPRESSTIME_15SEC (2 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* 15 secs */ # define SNVS_LPCR_BTNPRESSTIME_DESAB (3 << SNVS_LPCR_BTNPRESSTIME_SHIFT) /* Long press disabled */ + #define SNVS_LPCR_DEBOUNCE_SHIFT (18) /* Bits 18-19: Debounce time for BTN input signal */ #define SNVS_LPCR_DEBOUNCE_MASK (3 << SNVS_LPCR_DEBOUNCE_SHIFT) # define SNVS_LPCR_DEBOUNCE_50MS (0 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 50msec debounce */ # define SNVS_LPCR_DEBOUNCE_100MS (1 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 100msec debounce */ # define SNVS_LPCR_DEBOUNCE_500MS (2 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 500msec debounce */ # define SNVS_LPCR_DEBOUNCE_NONE (3 << SNVS_LPCR_DEBOUNCE_SHIFT) /* 0msec debounce */ + #define SNVS_LPCR_ONTIME_SHIFT (20) /* Bits 20-21: ON time configuration */ #define SNVS_LPCR_ONTIME_MASK (3 << SNVS_LPCR_ONTIME_SHIFT) # define SNVS_LPCR_ONTIME_500MS (0 << SNVS_LPCR_ONTIME_SHIFT) /* 500msec off->on transition time */ # define SNVS_LPCR_ONTIME_50MS (1 << SNVS_LPCR_ONTIME_SHIFT) /* 50msec off->on transition time */ # define SNVS_LPCR_ONTIME_100MS (2 << SNVS_LPCR_ONTIME_SHIFT) /* 100msec off->on transition time */ # define SNVS_LPCR_ONTIME_NONE (3 << SNVS_LPCR_ONTIME_SHIFT) /* 0msec off->on transition time */ + #define SNVS_LPCR_PKEN (1 << 22) /* Bit 22: PMIC On Request Enable */ #define SNVS_LPCR_PKOVERRIDE (1 << 23) /* Bit 23: PMIC On Request Override */ /* Bits 24-31: Reserved */ @@ -240,7 +248,10 @@ /* Bits 19-31: Reserved */ /* SNVS_LP Secure Monotonic Counter MSB Register */ -/* SNVS_LP Secure Monotonic Counter LSB Register (32-bit LSB counter value) */ + +/* SNVS_LP Secure Monotonic Counter LSB Register + * (32-bit LSB counter value) + */ #define SNVS_LPSMCMR_MONCOUNTER_SHIFT (0) /* Bits 0-15: Monotonic Counter most-significant 16 Bits */ #define SNVS_LPSMCMR_MONCOUNTER_MASK (0xffff << SNVS_LPSMCMR_MONCOUNTER_SHIFT) @@ -250,13 +261,21 @@ # define SNVS_LPSMCMR_MCERABITS(n) ((uint32_t)(n) << SNVS_LPSMCMR_MCERABITS_SHIFT) /* SNVS_LP General Purpose Register 0 (legacy alias) (32-bit value) */ + /* NVS_LP General Purpose Registers 0 LPGPR0_alias (32-bit value) */ + /* NVS_LP General Purpose Registers 1 LPGPR1_alias (32-bit value) */ + /* NVS_LP General Purpose Registers 2 LPGPR2_alias (32-bit value) */ + /* NVS_LP General Purpose Registers 3 LPGPR3_alias (32-bit value) */ + /* SNVS_LP General Purpose Registers 0 (32-bit value) */ + /* SNVS_LP General Purpose Registers 1 (32-bit value) */ + /* SNVS_LP General Purpose Registers 2 (32-bit value) */ + /* SNVS_LP General Purpose Registers 3 (32-bit value) */ /* SNVS_HP Version ID Register 1 */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_src.h b/arch/arm/src/imxrt/hardware/imxrt_src.h index e845e3fd1dc..45ade301d27 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_src.h +++ b/arch/arm/src/imxrt/hardware/imxrt_src.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_src.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SRC_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SRC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_SRC_SCR_OFFSET 0x0000 /* SRC Control Register */ #define IMXRT_SRC_SBMR1_OFFSET 0x0004 /* SRC Boot Mode Register 1 */ @@ -49,7 +49,7 @@ #define IMXRT_SRC_GPR9_OFFSET 0x0040 /* SRC General Purpose Register 9 */ #define IMXRT_SRC_GPR10_OFFSET 0x0044 /* SRC General Purpose Register 10 */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_SRC_SCR (IMXRT_SRC_BASE + IMXRT_SRC_SCR_OFFSET) #define IMXRT_SRC_SBMR1 (IMXRT_SRC_BASE + IMXRT_SRC_SBMR1_OFFSET) @@ -66,7 +66,7 @@ #define IMXRT_SRC_GPR9 (IMXRT_SRC_BASE + IMXRT_SRC_GPR9_OFFSET) #define IMXRT_SRC_GPR10 (IMXRT_SRC_BASE + IMXRT_SRC_GPR10_OFFSET) -/* Register bit definitions *****************************************************************/ +/* Register bit definitions *************************************************/ /* SRC Control Register */ @@ -131,11 +131,12 @@ /* Bits 5-23: Reserved */ #define SRC_SBMR2_BMOD_SHIFT (24) /* Bits 24-25: Latched state of the BOOT_MODE * and BOOT_MODE0 signals on POR. - /* Bits 26-31: Reserved */ + * Bits 26-31: Reserved */ /* SRC General Purpose Register 1 (32-bit values, some have reserved bits) - * NOTE: Ald GPR registers are used by the ROM code and should not be used by application - * software. + + * NOTE: Ald GPR registers are used by the ROM code and should not be used + * by application software. */ #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SRC_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_usbotg.h b/arch/arm/src/imxrt/hardware/imxrt_usbotg.h index 0cdda98e7c0..0c58f55445e 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_usbotg.h +++ b/arch/arm/src/imxrt/hardware/imxrt_usbotg.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_usbotg.h * * Copyright (C) 2009-2011, 2019 Gregory Nutt. All rights reserved. @@ -32,24 +32,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ #define IMXRT_EHCI_NRHPORT 1 /* There is only a single root hub port */ -/* USBOTG register offsets (with respect to IMXRT_USB_BASE) *********************************/ +/* USBOTG register offsets (with respect to IMXRT_USB_BASE) *****************/ /* 0x000 - 0x0ff: Reserved */ @@ -135,7 +135,7 @@ #define IMXRT_USBNC_USB_OTG1_CTRL_OFFSET 0x0800 /* OTG1 Control Register */ #define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET 0x0818 /* OTG1 Phy Control Register */ -/* USBOTG register (virtual) addresses ******************************************************/ +/* USBOTG register (virtual) addresses **************************************/ /* Device/host capability registers */ @@ -217,7 +217,7 @@ #define IMXRT_USBNC_USB_OTG1_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_CTRL_OFFSET) #define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET) -/* USBOTG register bit definitions **********************************************************/ +/* USBOTG register bit definitions ******************************************/ /* Device/host capability registers */ @@ -282,6 +282,7 @@ # define USBDEV_USBCMD_ITC16UF (16 << USBDEV_USBCMD_ITC_SHIFT) /* 16 micro frames */ # define USBDEV_USBCMD_ITC32UF (32 << USBDEV_USBCMD_ITC_SHIFT) /* 32 micro frames */ # define USBDEV_USBCMD_ITC64UF (64 << USBDEV_USBCMD_ITC_SHIFT) /* 64 micro frames */ + #define USBDEV_USBCMD_ATDTW (1 << 14) /* Bit 14: Add dTD trip wire */ #define USBDEV_USBCMD_SUTW (1 << 13) /* Bit 13: Setup trip wire */ #define USBDEV_USBCMD_RST (1 << 1) /* Bit 1: 1 Controller reset */ @@ -299,6 +300,7 @@ # define USBHOST_USBCMD_ITC16UF (16 << USBHOST_USBCMD_ITC_SHIFT) /* 16 micro frames */ # define USBHOST_USBCMD_ITC32UF (32 << USBHOST_USBCMD_ITC_SHIFT) /* 32 micro frames */ # define USBHOST_USBCMD_ITC64UF (64 << USBHOST_USBCMD_ITC_SHIFT) /* 64 micro frames */ + #define USBHOST_USBCMD_FS2 (1 << 15) /* Bit 15: Bit 2 of the Frame List Size bits */ #define USBHOST_USBCMD_ASPE (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */ #define USBHOST_USBCMD_ASP_SHIFT (8) /* Bits 8-9: Asynchronous schedule park mode */ @@ -447,6 +449,7 @@ # define USBDEV_PRTSC1_PSPD_FS (0 << USBDEV_PRTSC1_PSPD_SHIFT) /* Full-speed */ # define USBDEV_PRTSC1_PSPD_LS (1 << USBDEV_PRTSC1_PSPD_SHIFT) /* Low-speed */ # define USBDEV_PRTSC1_PSPD_HS (2 << USBDEV_PRTSC1_PSPD_SHIFT) /* High-speed */ + #define USBDEV_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */ #define USBDEV_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */ #define USBDEV_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: 19: Port test control */ @@ -458,11 +461,13 @@ # define USBDEV_PRTSC1_PTC_PACKET (4 << USBDEV_PRTSC1_PTC_SHIFT) /* Packet */ # define USBDEV_PRTSC1_PTC_HS (5 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_HS */ # define USBDEV_PRTSC1_PTC_FS (6 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_FS */ + #define USBDEV_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */ #define USBDEV_PRTSC1_PIC_MASK (3 << USBDEV_PRTSC1_PIC_SHIFT) # define USBDEV_PRTSC1_PIC_OFF (0 << USBDEV_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */ # define USBDEV_PRTSC1_PIC_AMBER (1 << USBDEV_PRTSC1_PIC_SHIFT) /* 01 amber */ # define USBDEV_PRTSC1_PIC_GREEN (2 << USBDEV_PRTSC1_PIC_SHIFT) /* 10 green */ + #define USBDEV_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */ #define USBDEV_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */ #define USBDEV_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */ @@ -478,6 +483,7 @@ # define USBHOST_PRTSC1_PSPD_FS (0 << USBHOST_PRTSC1_PSPD_SHIFT) /* Full-speed */ # define USBHOST_PRTSC1_PSPD_LS (1 << USBHOST_PRTSC1_PSPD_SHIFT) /* Low-speed */ # define USBHOST_PRTSC1_PSPD_HS (2 << USBHOST_PRTSC1_PSPD_SHIFT) /* High-speed */ + #define USBHOST_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */ #define USBHOST_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */ #define USBHOST_PRTSC1_WKOC (1 << 22) /* Bit 22: Wake on over-current enable (WKOC_E) */ @@ -493,17 +499,20 @@ # define USBHOST_PRTSC1_PTC_HS (5 << USBHOST_PRTSC1_PTC_SHIFT) /* 0101 FORCE_ENABLE_HS */ # define USBHOST_PRTSC1_PTC_FS (6 << USBHOST_PRTSC1_PTC_SHIFT) /* 0110 FORCE_ENABLE_FS */ # define USBHOST_PRTSC1_PTC_LS (7 << USBHOST_PRTSC1_PTC_SHIFT) /* 0111 FORCE_ENABLE_LS */ + #define USBHOST_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */ #define USBHOST_PRTSC1_PIC_MASK (3 << USBHOST_PRTSC1_PIC_SHIFT) # define USBHOST_PRTSC1_PIC_OFF (0 << USBHOST_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */ # define USBHOST_PRTSC1_PIC_AMBER (1 << USBHOST_PRTSC1_PIC_SHIFT) /* 01 Amber */ # define USBHOST_PRTSC1_PIC_GREEN (2 << USBHOST_PRTSC1_PIC_SHIFT) /* 10 Green */ + #define USBHOST_PRTSC1_PP (1 << 12) /* Bit 12: Port power control */ #define USBHOST_PRTSC1_LS_SHIFT (10) /* Bits 10-11: Line status */ #define USBHOST_PRTSC1_LS_MASK (3 << USBHOST_PRTSC1_LS_SHIFT) # define USBHOST_PRTSC1_LS_SE0 (0 << USBHOST_PRTSC1_LS_SHIFT) /* SE0 (USB_DP and USB_DM LOW) */ # define USBHOST_PRTSC1_LS_JSTATE (2 << USBHOST_PRTSC1_LS_SHIFT) /* J-state (USB_DP HIGH and USB_DM LOW) */ # define USBHOST_PRTSC1_LS_KSTATE (1 << USBHOST_PRTSC1_LS_SHIFT) /* K-state (USB_DP LOW and USB_DM HIGH) */ + #define USBHOST_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */ #define USBHOST_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */ #define USBHOST_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */ @@ -683,11 +692,13 @@ #define USBDEV_ENDPTCTRL0_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */ #define USBDEV_ENDPTCTRL0_TXT_MASK (3 << USBDEV_ENDPTCTRL0_TXT_SHIFT) # define USBDEV_ENDPTCTRL0_TXT_CTRL (0 << USBDEV_ENDPTCTRL0_TXT_SHIFT) /* Control */ + #define USBDEV_ENDPTCTRL0_TXS (1 << 16) /* Bit 16: Tx endpoint stall */ #define USBDEV_ENDPTCTRL0_RXE (1 << 7) /* Bit 7: Rx endpoint enable */ #define USBDEV_ENDPTCTRL0_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */ #define USBDEV_ENDPTCTR0L_RXT_MASK (3 << USBDEV_ENDPTCTRL0_RXT_SHIFT) # define USBDEV_ENDPTCTRL0_RXT_CTRL (0 << USBDEV_ENDPTCTRL0_RXT_SHIFT) /* Control */ + #define USBDEV_ENDPTCTRL0_RXS (1 << 0) /* Bit 0: Rx endpoint stall */ /* USB Endpoint 1-7 control registers ENDPTCTRL1-ENDPPTCTRL7 */ @@ -701,6 +712,7 @@ # define USBDEV_ENDPTCTRL_TXT_ISOC (1 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Isochronous */ # define USBDEV_ENDPTCTRL_TXT_BULK (2 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Bulk */ # define USBDEV_ENDPTCTRL_TXT_INTR (3 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Interrupt */ + #define USBDEV_ENDPTCTRL_TXS (1 << 16) /* Bit 16: Tx endpoint stall */ #define USBDEV_ENDPTCTRL_RXE (1 << 7) /* Bit 7: Rx endpoint enable */ #define USBDEV_ENDPTCTRL_RXR (1 << 6) /* Bit 6: Rx data toggle reset */ @@ -711,12 +723,16 @@ # define USBDEV_ENDPTCTRL_RXT_ISOC (1 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Isochronous */ # define USBDEV_ENDPTCTRL_RXT_BULK (2 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Bulk */ # define USBDEV_ENDPTCTRL_RXT_INTR (3 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Interrupt */ + #define USBDEV_ENDPTCTRL_RXS (1 << 0) /* Bit 0: Rx endpoint stall */ /* Device non-core registers */ /* USB OTG Control register */ - /* Bits 0-6: Reserved */ + +/* Bits 0-6: + * Reserved + */ #define USBNC_OVER_CUR_DIS (1 << 7) /* Bit 7: Disable Over current detection */ #define USBNC_OVER_CUR_POL (1 << 8) /* Bit 8: Polarity of over current */ #define USBNC_PWR_POL (1 << 9) /* Bit 9: Power polarity */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_usbphy.h b/arch/arm/src/imxrt/hardware/imxrt_usbphy.h index 34e9b766dca..1d4b7ff4cd0 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_usbphy.h +++ b/arch/arm/src/imxrt/hardware/imxrt_usbphy.h @@ -33,6 +33,7 @@ ****************************************************************************/ #define IMXRT_USBPHY_BASE_OFFSET 0x1000 /* USB PHY Base */ + #define IMXRT_USBPHY_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY_BASE_OFFSET) /* USB PHY Base */ /* Register Offsets *********************************************************/ @@ -44,10 +45,10 @@ /* Register addresses *******************************************************/ -#define IMXRT_USBPHY1_PWD (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_OFFSET) /* USBPHY1 USB PHY Power-Down Register */ +#define IMXRT_USBPHY1_PWD (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_OFFSET) /* USBPHY1 USB PHY Power-Down Register */ #define IMXRT_USBPHY1_PWD_CLR (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_CLR_OFFSET) /* USBPHY1 USB PHY Power-Down Register Clear */ -#define IMXRT_USBPHY1_CTRL (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_OFFSET) /* USBPHY1 USB PHY General Control Register */ -#define IMXRT_USBPHY1_CTRL_CLR (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY General Control Register Clear */ +#define IMXRT_USBPHY1_CTRL (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_OFFSET) /* USBPHY1 USB PHY General Control Register */ +#define IMXRT_USBPHY1_CTRL_CLR (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY General Control Register Clear */ /* Register Bit Definitions *************************************************/ diff --git a/arch/arm/src/imxrt/hardware/imxrt_usdhc.h b/arch/arm/src/imxrt/hardware/imxrt_usdhc.h index 34cbc46e46a..e1f370e7264 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_usdhc.h +++ b/arch/arm/src/imxrt/hardware/imxrt_usdhc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_usdhc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USDHC_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USDHC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define IMXRT_USDHC_DSADDR_OFFSET 0x0000 /* DMA System Address Register */ #define IMXRT_USDHC_BLKATTR_OFFSET 0x0004 /* Block Attributes Register */ @@ -65,7 +65,7 @@ #define IMXRT_USDHC_VENDOR2_OFFSET 0x00c8 /* Vendor 2 Register */ #define IMXRT_USDHC_TC_OFFSET 0x00cc /* Tuning Control Register */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ /* For USDHC1 ... */ @@ -130,7 +130,7 @@ #define IMXRT_USDHC2_VENDOR2 (IMXRT_USDHC2_BASE + IMXRT_USDHC_VENDOR2_OFFSET) #define IMXRT_USDHC2_TC (IMXRT_USDHC2_BASE + IMXRT_USDHC_TC_OFFSET) -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ /* DMA System Address Register */ @@ -151,13 +151,16 @@ /* Transfer Type Register */ - /* Bits 0-15: Reserved */ +/* Bits 0-15: + * Reserved + */ #define USDHC_XFERTYP_RSPTYP_SHIFT (16) /* Bits 16-17: Response Type Select */ #define USDHC_XFERTYP_RSPTYP_MASK (3 << USDHC_XFERTYP_RSPTYP_SHIFT) # define USDHC_XFERTYP_RSPTYP_NONE (0 << USDHC_XFERTYP_RSPTYP_SHIFT) /* No response */ # define USDHC_XFERTYP_RSPTYP_LEN136 (1 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */ # define USDHC_XFERTYP_RSPTYP_LEN48 (2 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */ # define USDHC_XFERTYP_RSPTYP_LEN48BSY (3 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */ + /* Bit 18: Reserved */ #define USDHC_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */ #define USDHC_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */ @@ -168,6 +171,7 @@ # define USDHC_XFERTYP_CMDTYP_SUSPEND (1 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */ # define USDHC_XFERTYP_CMDTYP_RESUME (2 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */ # define USDHC_XFERTYP_CMDTYP_ABORT (3 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */ + #define USDHC_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */ #define USDHC_XFERTYP_CMDINX_MASK (0x3f << USDHC_XFERTYP_CMDINX_SHIFT) /* Bits 30-31: Reserved */ @@ -218,12 +222,14 @@ # define USDHC_PROCTL_DTW_1BIT (0 << USDHC_PROCTL_DTW_SHIFT) /* 1-bit mode */ # define USDHC_PROCTL_DTW_4BIT (1 << USDHC_PROCTL_DTW_SHIFT) /* 4-bit mode */ # define USDHC_PROCTL_DTW_8BIT (2 << USDHC_PROCTL_DTW_SHIFT) /* 8-bit mode */ + #define USDHC_PROCTL_D3CD (1 << 3) /* Bit 3: DAT3 as Card Detection Pin */ #define USDHC_PROCTL_EMODE_SHIFT (4) /* Bits 4-5: Endian mode */ #define USDHC_PROCTL_EMODE_MASK (3 << USDHC_PROCTL_EMODE_SHIFT) # define USDHC_PROCTL_EMODE_BE (0 << USDHC_PROCTL_EMODE_SHIFT) /* Big endian mode */ # define USDHC_PROCTL_EMODE_HWBE (1 << USDHC_PROCTL_EMODE_SHIFT) /* Half word big endian mode */ # define USDHC_PROCTL_EMODE_LE (2 << USDHC_PROCTL_EMODE_SHIFT) /* Little endian mode */ + #define USDHC_PROCTL_CDTL (1 << 6) /* Bit 6: Card Detect Test Level */ #define USDHC_PROCTL_CDSS (1 << 7) /* Bit 7: Card Detect Signal Selection */ #define USDHC_PROCTL_DMAS_SHIFT (8) /* Bits 8-9: DMA Select */ @@ -231,7 +237,10 @@ # define USDHC_PROCTL_DMAS_NODMA (0 << USDHC_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */ # define USDHC_PROCTL_DMAS_ADMA1 (1 << USDHC_PROCTL_DMAS_SHIFT) /* ADMA1 is selected */ # define USDHC_PROCTL_DMAS_ADMA2 (2 << USDHC_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */ - /* Bits 10-15: Reserved */ + +/* Bits 10-15: + * Reserved + */ #define USDHC_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */ #define USDHC_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */ #define USDHC_PROCTL_RWCTL (1 << 18) /* Bit 18: Read Wait Control */ @@ -246,14 +255,17 @@ # define USDHC_PROCTL_BURST_INCR (1 << USDHC_PROCTL_BURST_SHIFT) /* Burst for Incr */ # define USDHC_PROCTL_BURST_4816 (2 << USDHC_PROCTL_BURST_SHIFT) /* Burst for 4/8/16 */ # define USDHC_PROCTL_BURST_4W8W16W (4 << USDHC_PROCTL_BURST_SHIFT) /* Burst for 4w/8w/16w */ + #define USDHC_PROTCTL_NEBLKRD (1 << 30) /* Bit 30: Non-exect block read */ /* Bit 31: Reserved */ + /* System Control Register */ #define USDHC_SYSCTL_RES0 (0x0F << 0) /* Bit 0-3: Reserved, set to 1 */ #define USDHC_SYSCTL_DVS_SHIFT (4) /* Bits 4-7: Divisor */ #define USDHC_SYSCTL_DVS_MASK (0x0f << USDHC_SYSCTL_DVS_SHIFT) # define USDHC_SYSCTL_DVS_DIV(n) (((n) - 1) << USDHC_SYSCTL_DVS_SHIFT) /* Divide by n, n=1..16 */ + #define USDHC_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */ #define USDHC_SYSCTL_SDCLKFS_MASK (0xff << USDHC_SYSCTL_SDCLKFS_SHIFT) # define USDHC_SYSCTL_SDCLKFS_BYPASS (0x00 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Bypass the prescaler */ @@ -265,10 +277,14 @@ # define USDHC_SYSCTL_SDCLKFS_DIV64 (0x20 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 64 */ # define USDHC_SYSCTL_SDCLKFS_DIV128 (0x40 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 128 */ # define USDHC_SYSCTL_SDCLKFS_DIV256 (0x80 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 256 */ + #define USDHC_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */ #define USDHC_SYSCTL_DTOCV_MASK (0x0f << USDHC_SYSCTL_DTOCV_SHIFT) # define USDHC_SYSCTL_DTOCV_MUL(n) (((n) - 213) << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */ - /* Bits 20-22: Reserved */ + +/* Bits 20-22: + * Reserved + */ #define USDHC_SYSCTL_IPPRSTN (1 << 23) /* Bit 23: Card /reset (default 1) */ #define USDHC_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */ #define USDHC_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */ @@ -277,7 +293,8 @@ #define USDHC_SYSCTL_RSTT (1 << 28) /* Bit 28: Reset tuning */ /* Bits 29-31: Reserved */ -/* Interrupt Status Register, Interrupt Status Enable Register and Interrupt Signal Enable Register +/* Interrupt Status Register, Interrupt Status Enable Register and + * Interrupt Signal Enable Register * Common interrupt bit definitions */ @@ -425,9 +442,11 @@ # define USDHC_ADMAES_FDS (1 << USDHC_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */ # define USDHC_ADMAES_CADR (2 << USDHC_ADMAES_ADMAES_SHIFT) /* Change address */ # define USDHC_ADMAES_TFR (3 << USDHC_ADMAES_ADMAES_SHIFT) /* Transfer data */ + #define USDHC_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */ #define USDHC_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */ /* Bits 4-31: Reserved */ + /* ADMA System Address Register */ #define USDHC_ADSADDR_SHIFT (0) /* Bits 1-31: ADMA System Address */ @@ -472,6 +491,7 @@ /* Clk tuning control and status */ /* Vendor Specific Register */ + /* Bit 0: Reserved */ #define SHDC_VENDOR_VSELECT18 (1 << 1) /* Bit 1: 1.8V signalling */ #define USDHC_VENDOR_CONFICTCHK_SHIFT (1 << 2) /* Bit 2: Conflict Check Enable .. not implemented */ @@ -488,6 +508,7 @@ #define USDHC_MMCBOOT_DTOCVACK_SHIFT (0) /* Bits 0-3: Boot ACK time out counter value */ #define USDHC_MMCBOOT_DTOCVACK_MASK (0x0f << USDHC_MMCBOOT_DTOCVACK_SHIFT) # define USDHC_MMCBOOT_DTOCVACK_MUL(n) ((n - 8) << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^n, n=8..22 */ + #define USDHC_MMCBOOT_BOOTACK (1 << 4) /* Bit 4: Boot ack mode select */ #define USDHC_MMCBOOT_BOOTMODE (1 << 5) /* Bit 5: Boot mode select */ #define USDHC_MMCBOOT_BOOTEN (1 << 6) /* Bit 6: Boot mode enable */ @@ -498,6 +519,7 @@ #define USDHC_MMCBOOT_BOOTBLKCNT_MASK (0xffff << USDHC_MMCBOOT_BOOTBLKCNT_SHIFT) /* Vendor specific register 2 */ + /* Bits 0-2: Reserved */ #define USDHC_VS2_CARDINTD3 (1 << 3) /* Bit 3: Card interrupt detection test */ #define USDHC_VS2_TUNING8BITEN (1 << 4) /* Bit 4: Tuning 8 bit enable */ @@ -525,16 +547,16 @@ #define USDHC_TC_TUNINGEN (1 << 24) /* Bit 24: Tuning enable */ /* Bits 25-31: Reserved */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USDHC_H */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_wdog.h b/arch/arm/src/imxrt/hardware/imxrt_wdog.h index 5420a09653f..482689bac3d 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_wdog.h +++ b/arch/arm/src/imxrt/hardware/imxrt_wdog.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_wdog.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,23 +31,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_WDOG_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_WDOG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_WDOG_WCR_OFFSET 0x0000 /* Watchdog control register */ #define IMXRT_WDOG_WSR_OFFSET 0x0002 /* Watchdog service register */ @@ -60,7 +60,7 @@ #define IMXRT_RTWDOG_TOVAL_OFFSET 0x0008 /* Watchdog timeout value register */ #define IMXRT_RTWDOG_WIN_OFFSET 0x000c /* Watchdog window register */ -/* Register addresses ***************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_WDOG1_WCR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WCR_OFFSET) #define IMXRT_WDOG1_WSR (IMXRT_WDOG1_BASE + IMXRT_WDOG_WSR_OFFSET) @@ -78,7 +78,7 @@ #define IMXRT_RTWDOG_TOVAL (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_TOVAL_OFFSET) #define IMXRT_RTWDOG_WIN (IMXRT_WDOG3_BASE + IMXRT_RTWDOG_WIN_OFFSET) -/* Register bit definitions *********************************************************/ +/* Register bit definitions *************************************************/ /* Watchdog control and status register */ @@ -102,7 +102,8 @@ /* Bits 2-3: reserved */ #define WDOG_WRSR_POR (1 << 4) /* Bit 4: Power on reset */ /* Bits 5-15: Reserved */ -/* Watchdog interrupt control */ + +/* Watchdog interrupt control */ #define WDOG_WICR_WICT_SHIFT (0) /* Bits 0-7: Watchdog Interrupt Count Time-out */ #define WDOG_WICR_WICT_MASK (0xff << WDOG_WCR_WT_SHIFT) @@ -115,6 +116,7 @@ #define WDOG_WMCR_PDE (1 << 0) /* Bit 0: Power Down Enable */ /* Bits 1-15: Reserved */ + /* RT Watchdog Control and Status Register */ #define RTWDOG_CS_STOP (1 << 0) /* Bit 0: Stop enable */ diff --git a/arch/arm/src/imxrt/hardware/imxrt_xbar.h b/arch/arm/src/imxrt/hardware/imxrt_xbar.h index 86ce4ad3fa0..eb7ebe5be07 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_xbar.h +++ b/arch/arm/src/imxrt/hardware/imxrt_xbar.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/imxrt_xbar.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_XBAR_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_XBAR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -39,9 +39,9 @@ # error Unrecognized i.MX RT architecture #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define IMXRT_SEL_PER_REG 2 diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h index b8150a1463a..ab9990d919a 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h * * Copyright (C) 2018-2019 Gregory Nutt. All rights reserved. @@ -33,25 +33,26 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_CCM_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_CCM_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/* Register offsets **********************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ + /* 0x0004 Reserved */ #define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ #define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ @@ -64,13 +65,18 @@ #define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ #define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ #define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ + /* 0x0034 Reserved */ #define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ #define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ + /* 0x0040 Reserved */ + /* 0x0044 Reserved */ #define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ + /* 0x004c Reserved */ + /* 0x0050 Reserved */ #define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ @@ -85,6 +91,7 @@ #define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ #define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ #define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ + /* 0x0084 Reserved */ #define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Override Register */ @@ -105,7 +112,7 @@ #define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ #define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ -/* Register addresses ********************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) #define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) @@ -152,12 +159,12 @@ #define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) #define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) -/* Helper Macros *************************************************************/ +/* Helper Macros ************************************************************/ #define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ #define CCM_PRED_FROM_DIVISOR(n) ((n)-1) /* PRED Values are divisor-1 */ -/* Register bit definitions **************************************************/ +/* Register bit definitions *************************************************/ /* Control Register */ @@ -172,6 +179,7 @@ # define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) #define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ /* Bits 28-31: Reserved */ + /* Status Register */ #define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ @@ -180,6 +188,7 @@ /* Bit 4: Reserved */ #define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ /* Bits 6-31: Reserved */ + /* Clock Switcher Register */ #define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ @@ -192,7 +201,9 @@ /* Bus Clock Divider Register */ - /* Bits 0-5: Reserved */ +/* Bits 0-5: + * Reserved + */ #define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ #define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ #define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ @@ -214,7 +225,9 @@ # define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) # define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) - /* Bit 26: Reserved */ +/* Bit 26: + * Reserved + */ #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) # define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) @@ -222,7 +235,9 @@ /* Bus Clock Multiplexer Register */ - /* Bits 0-3: Reserved */ +/* Bit 0-3: + * Reserved + */ #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) # define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) @@ -302,6 +317,7 @@ # define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) # define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT) /* Bit 31: Reserved */ + /* Serial Clock Multiplexer Register 2 */ #define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2) /* Bits 2-7: Divider for can clock podf */ @@ -395,7 +411,9 @@ /* Serial Clock Divider Register 2 */ - /* Bits 0-17: Reserved */ +/* Bits 0-17: + * Reserved + */ #define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ # define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ # define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ @@ -424,7 +442,10 @@ # define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ # define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ # define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ - /* Bits 2-4: Reserved */ + +/* Bits 2-4: + * Reserved + */ #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ #define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ #define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ @@ -623,15 +644,18 @@ #define CCM_CCGR_LPSPI3 IMXRT_CCM_CCGR1, 2 #define CCM_CCGR_LPSPI2 IMXRT_CCM_CCGR1, 1 #define CCM_CCGR_LPSPI1 IMXRT_CCM_CCGR1, 0 - /* 15 : Reserved */ + /* 14 : Reserved */ #define CCM_CCGR_GPIO3 IMXRT_CCM_CCGR2, 13 #define CCM_CCGR_XBAR2 IMXRT_CCM_CCGR2, 12 #define CCM_CCGR_XBAR1 IMXRT_CCM_CCGR2, 11 /* 10 : Reserved */ + /* 9 : Reserved */ + /* 8 : Reserved */ + /* 7 : Reserved */ #define CCM_CCGR_OCOTP_CTRL IMXRT_CCM_CCGR2, 6 #define CCM_CCGR_LPI2C3 IMXRT_CCM_CCGR2, 5 @@ -651,6 +675,7 @@ #define CCM_CCGR_WDOG1 IMXRT_CCM_CCGR3, 8 #define CCM_CCGR_EWM IMXRT_CCM_CCGR3, 7 /* 6 : Reserved */ + /* 5 : Reserved */ #define CCM_CCGR_AOI1 IMXRT_CCM_CCGR3, 4 #define CCM_CCGR_LPUART6 IMXRT_CCM_CCGR3, 3 @@ -659,10 +684,12 @@ /* 0 : Reserved */ /* 15 : Reserved */ + /* 14 : Reserved */ #define CCM_CCGR_ENC2 IMXRT_CCM_CCGR4, 13 #define CCM_CCGR_ENC1 IMXRT_CCM_CCGR4, 12 /* 11 : Reserved */ + /* 10 : Reserved */ #define CCM_CCGR_PWM2 IMXRT_CCM_CCGR4, 9 #define CCM_CCGR_PWM1 IMXRT_CCM_CCGR4, 8 @@ -711,7 +738,9 @@ /* Module Enable Override Register */ - /* Bits 0-4: Reserved */ +/* Bits 0-4: + * Reserved + */ #define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Override clock enable signal from GPT */ #define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Override clock enable signal from PIT */ #define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Override clock enable signal from USDHC */ @@ -721,7 +750,7 @@ #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Override clock enable signal from CAN1 */ /* Bit 31: Reserved */ -/* Analog System PLL (2) Control Register ***********************************/ +/* Analog System PLL (2) Control Register **********************************/ #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) /* Bits 0: This field controls the PLL loop divider 20 or 22 */ #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT) @@ -735,12 +764,16 @@ #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ + #define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bits 17-30 Reserved */ #define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ -/* Analog USB1 480MHz PLL (3) Control Register *******************************/ - /* Bit 0: Reserved */ +/* Analog USB1 480MHz PLL (3) Control Register ******************************/ + +/* Bit 0: + * Reserved + */ #define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1) /* Bit 1: This field controls the PLL loop divider 20 or 22 */ #define CCM_ANALOG_PLL_USB1_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT) #define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK CCM_ANALOG_PLL_USB1_DIV_SELECT(1) @@ -755,6 +788,7 @@ #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ + #define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bits 17-30 Reserved */ #define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ @@ -794,6 +828,7 @@ #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ + #define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bit 17-18: Reserved */ #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ @@ -817,6 +852,7 @@ #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) #define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) /* Bits 30-31: Reserved */ + /* Analog ENET PLL Control Register */ #define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */ @@ -826,12 +862,15 @@ # define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) # define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT) - /* Bits 2-11: Reserved */ +/* Bits 2-11: + * Reserved + */ #define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ + #define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bit 17-20: Reserved */ #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ @@ -914,7 +953,9 @@ /* Miscellaneous Register 1 */ - /* Bits 0-15: Reserved */ +/* Bits 0-15: + * Reserved + */ #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN (1 << 16) /* Bit 16: */ #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN (1 << 17) /* Bit 17: */ /* Bits 18-26: Reserved */ @@ -925,7 +966,10 @@ #define CCM_ANALOG_MISC1_IRQ_DIG_BO (1 << 31) /* Bit 31: digital regulator brownout interrupt */ /* Miscellaneous Register 2 */ - /* Bit 0-4: Reserved */ + +/* Bits 0-4: + * Reserved + */ #define CCM_ANALOG_MISC2_REG0_ENABLE_BO (1 << 5) /* Bit 5: Enables the brownout detection */ #define CCM_ANALOG_MISC2_REG0_OK (1 << 6) /* Bit 6: ARM supply */ #define CCM_ANALOG_MISC2_PLL3_DISABLE (1 << 7) /* Bit 7: PLL3 can be disabled when the SoC is not in any low power mode */ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h index b666d5846a8..7eadab88b8a 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,20 +32,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_DMAMUX_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_DMAMUX_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include -/***************************************************************************** +/**************************************************************************** * Preprocessor Definitions - *****************************************************************************/ + ****************************************************************************/ /* Peripheral DMA request channels */ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h index 520b3b21108..7cc56b8c440 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -33,23 +33,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_GPIO_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_GPIO_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/* Register offsets **********************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ #define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ @@ -63,7 +63,7 @@ #define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ #define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ -/* Register addresses ********************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) #define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h index def4a3a174b..e987ff7d4b4 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h @@ -32,23 +32,23 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_IOMUXC_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_IOMUXC_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/* Register offsets **********************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ #define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ @@ -615,7 +615,7 @@ #define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x04bc #define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x04c0 -/* Register addresses ********************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) #define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) @@ -966,7 +966,7 @@ #define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) #define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) -/* Register bit definitions **************************************************/ +/* Register bit definitions *************************************************/ /* General Purpose Register 0 (GPR0) - Reserved */ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h index c27907cecd4..859b6ba7d05 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h @@ -32,78 +32,109 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_MEMORYMAP_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_MEMORYMAP_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ /* System memory map */ #define IMXRT_ITCM_BASE 0x00000000 /* 256KB ITCM */ + /* 0x00040000 768KB ITCM Reserved */ + /* 0x00100000 1MB ITCM Reserved */ #define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */ + /* 0x00218000 416KB ROMCP Reserved */ + /* 0x00280000 1536KB Reserved */ + /* 0x00400000 124MB Reserved */ + /* 0x00800000 1527MB Reserved */ #define IMXRT_FLEXSPI_BASE 0x06000000 /* 128MB FlexSPI (Aliased) */ #define IMXRT_SEMCA_BASE 0x06800000 /* 639MB SEMC (Aliased) */ + /* 0x90000000 256MB SEMC (Aliased) */ #define IMXRT_DTCM_BASE 0x20000000 /* 256KB DTCM */ + /* 0x20040000 768KB DTCM Reserved */ + /* 0x20100000 1MB Reserved */ #define IMXRT_OCRAM_BASE 0x20200000 /* 256KB OCRAM */ + /* 0x20240000 1792KB OCRAM Reserved */ + /* 0x20400000 252MB Reserved */ + /* 0x30000000 256MB Reserved */ #define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ #define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ #define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ #define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ + /* 0x40400000 12MB Reserved */ + /* 0x41000000 1MB Reserved */ #define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ + /* 41200000 1MB Reserved for "per" GPV */ + /* 41300000 1MB Reserved for "ems" GPV */ #define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ + /* 0x41500000 1MB GPV Reserved */ + /* 0x41600000 1MB GPV Reserved */ + /* 0x41700000 1MB GPV Reserved */ + /* 0x41800000 8MB Reserved */ + /* 0x42000000 32MB Reserved */ + /* 0x44000000 64MB Reserved */ + /* 0x48000000 384MB Reserved */ #define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */ #define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */ #define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ #define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ #define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ + /* 0xe0100000 511MB Reserved */ /* AIPS-1 memory map */ /* 0x40000000 256KB Reserved */ + /* 0x40040000 240KB Reserved */ #define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 16KB AIPS-1 Configuration */ #define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ #define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ + /* 0x40088000 16KB Reserved */ + /* 0x4008c000 16KB Reserved */ + /* 0x40090000 16KB Reserved */ #define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ + /* 0x40098000 16KB Reserved */ + /* 0x4009c000 16KB Reserved */ + /* 0x400a0000 16KB Reserved */ #define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ #define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ @@ -120,10 +151,13 @@ #define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ #define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ #define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ + /* 0x400e0000 16KB Reserved */ + /* 0x400e4000 16KB Reserved */ #define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ #define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ + /* 400f0000 16KB Reserved */ #define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ #define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ @@ -132,6 +166,7 @@ /* AIPS-2 memory map */ /* 0x40100000 256KB Reserved */ + /* 0x40140000 240KB Reserved */ #define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ #define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ @@ -143,23 +178,33 @@ #define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ #define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ #define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ + /* 0x401a4000 16KB Reserved */ + /* 0x401a8000 16KB Reserved */ #define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ + /* 0x401b0000 16KB Reserved */ + /* 0x401b4000 16KB Reserved */ #define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ #define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ #define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ + /* 0x401c4000 16KB Reserved */ + /* 0x401c8000 16KB Reserved */ + /* 0x401cc000 16KB Reserved */ #define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ #define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ + /* 0x401d8000 16KB Reserved */ #define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */ #define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */ + /* 0x401e4000 16KB Reserved */ + /* 0x401e8000 16KB Reserved */ #define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */ #define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */ @@ -170,72 +215,110 @@ /* AIPS-3 memory map */ /* 0x40200000 256KB Reserved */ + /* 0x40240000 240KB Reserved */ #define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ + /* 0x40280000 16KB Reserved */ + /* 0x40284000 16KB Reserved */ + /* 0x40288000 16KB Reserved */ + /* 0x4028c000 16KB Reserved */ + /* 0x40290000 16KB Reserved */ + /* 0x40294000 16KB Reserved */ + /* 0x40298000 16KB Reserved */ + /* 0x4029c000 16KB Reserved */ + /* 0x402a0000 16KB Reserved */ + /* 0x402a4000 16KB Reserved */ #define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */ + /* 0x402ac000 16KB Reserved */ + /* 0x402b0000 16KB Reserved */ + /* 0x402b4000 16KB Reserved */ + /* 0x402b8000 16KB Reserved */ + /* 0x402bc000 16KB Reserved */ #define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ #define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ + /* 0x402c8000 16KB Reserved */ + /* 0x402cc000 16KB Reserved */ + /* 0x402d0000 16KB Reserved */ + /* 0x402d4000 16KB Reserved */ #define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ - /* 0x402dc000 16KB Reserved */ + + /* 0x402dc000 16KB Reserved */ #define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ + /* 0x402e4000 16KB Reserved */ + /* 0x402e8000 16KB Reserved */ + /* 0x402ec000 16KB Reserved */ #define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ + /* 0x402f4000 16KB Reserved */ + /* 0x402f8000 16KB Reserved */ #define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ /* AIPS-4 memory map */ /* 0x40300000 256KB Reserved */ + /* 0x40340000 240KB Reserved */ #define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ #define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ #define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ #define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ #define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ + /* 0x40390000 16KB Reserved */ #define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ #define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ #define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ #define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ + /* 0x403a4000 16KB Reserved */ + /* 0x403a8000 16KB Reserved */ + /* 0x403ac000 16KB Reserved */ #define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ #define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ + /* 0x403b8000 16KB Reserved */ #define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */ #define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */ + /* 0x403c4000 16KB Reserved */ #define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */ #define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ + /* 0x403d0000 16KB Reserved */ + /* 0x403d4000 16KB Reserved */ + /* 0x403d8000 16KB Reserved */ #define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ #define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ + /* 0x403e4000 16KB Reserved */ + /* 0x403e8000 16KB Reserved */ #define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */ #define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */ @@ -250,9 +333,12 @@ #define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ #define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ #define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ + /* 0xe0045000 236KB PPB Reserved */ #define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ + /* 0xe0081000 444KB PPB Reserved */ + /* 0xe00f0000 52KB PPB Reserved */ #define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ #define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h index 68c3d3825a4..9b1ba6f2798 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,21 +32,21 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_PINMUX_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_PINMUX_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "imxrt_iomuxc.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ /* Alternate Pin Functions. * @@ -120,7 +120,6 @@ #define GPIO_ENET_REF_CLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) #define GPIO_ENET_REF_CLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) - #define GPIO_ENET_RX_CLK_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC36_INDEX)) #define GPIO_ENET_RX_DATA00_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) #define GPIO_ENET_RX_DATA00_2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) @@ -251,7 +250,6 @@ #define GPIO_FLEXPWM2_PWMX02_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) #define GPIO_FLEXPWM2_PWMX03_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) - /* Flexible SPI (FlexSPI) */ #define GPIO_FLEXSPIA_DATA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) @@ -774,7 +772,6 @@ #define GPIO_USB_OTG_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) #define GPIO_USB_OTG_PWR_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) - #define GPIO_USBPHY1_TSTI_TX_DN_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) #define GPIO_USBPHY1_TSTI_TX_DP_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) #define GPIO_USBPHY1_TSTI_TX_EN_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_xbar.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_xbar.h index f8d6aefd1f1..8de712949e5 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_xbar.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_xbar.h @@ -1,39 +1,49 @@ /* XBAR Defines for IMXRT102x */ -/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ +/* XBARA1 Mux inputs (I values) *********************************************/ -#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ -#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 2) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 3) RESERVED */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ -#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 20) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 21) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 22) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 23) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 24) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 25) RESERVED */ -#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ -#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ -#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ -#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 30) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 31) RESERVED */ +#define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ +#define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 2) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 3) */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04 IMXRT_XBARA1(XBAR_INPUT, 4) /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05 IMXRT_XBARA1(XBAR_INPUT, 5) /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06 IMXRT_XBARA1(XBAR_INPUT, 6) /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07 IMXRT_XBARA1(XBAR_INPUT, 7) /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08 IMXRT_XBARA1(XBAR_INPUT, 8) /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09 IMXRT_XBARA1(XBAR_INPUT, 9) /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10 IMXRT_XBARA1(XBAR_INPUT, 10) /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11 IMXRT_XBARA1(XBAR_INPUT, 11) /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12 IMXRT_XBARA1(XBAR_INPUT, 12) /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13 IMXRT_XBARA1(XBAR_INPUT, 13) /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14 IMXRT_XBARA1(XBAR_INPUT, 14) /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15 IMXRT_XBARA1(XBAR_INPUT, 15) /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16 IMXRT_XBARA1(XBAR_INPUT, 16) /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17 IMXRT_XBARA1(XBAR_INPUT, 17) /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18 IMXRT_XBARA1(XBAR_INPUT, 18) /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ +#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19 IMXRT_XBARA1(XBAR_INPUT, 19) /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 20) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 21) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 22) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 23) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 24) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 25) */ +#define IMXRT_XBARA1_IN_ACMP1_OUT IMXRT_XBARA1(XBAR_INPUT, 26) /* ACMP1_OUT output assigned to XBARA1_IN26 input. */ +#define IMXRT_XBARA1_IN_ACMP2_OUT IMXRT_XBARA1(XBAR_INPUT, 27) /* ACMP2_OUT output assigned to XBARA1_IN27 input. */ +#define IMXRT_XBARA1_IN_ACMP3_OUT IMXRT_XBARA1(XBAR_INPUT, 28) /* ACMP3_OUT output assigned to XBARA1_IN28 input. */ +#define IMXRT_XBARA1_IN_ACMP4_OUT IMXRT_XBARA1(XBAR_INPUT, 29) /* ACMP4_OUT output assigned to XBARA1_IN29 input. */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 30) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 31) */ #define IMXRT_XBARA1_IN_QTIMER1_TMR0_OUT IMXRT_XBARA1(XBAR_INPUT, 32) /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ #define IMXRT_XBARA1_IN_QTIMER1_TMR1_OUT IMXRT_XBARA1(XBAR_INPUT, 33) /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ #define IMXRT_XBARA1_IN_QTIMER1_TMR2_OUT IMXRT_XBARA1(XBAR_INPUT, 34) /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ @@ -58,48 +68,62 @@ #define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 46) /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN46 input. */ #define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG0 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN47 input. */ #define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG1 IMXRT_XBARA1(XBAR_INPUT, 47) /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN47 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 48) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 49) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 50) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 51) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 52) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 53) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 54) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 55) RESERVED */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ -#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ -#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ -#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 62) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 63) RESERVED */ -#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ -#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ -#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 76) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 77) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 78) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 79) RESERVED */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ -#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ -/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 48) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 49) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 50) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 51) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 52) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 53) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 54) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 55) */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER0 IMXRT_XBARA1(XBAR_INPUT, 56) /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER1 IMXRT_XBARA1(XBAR_INPUT, 57) /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER2 IMXRT_XBARA1(XBAR_INPUT, 58) /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ +#define IMXRT_XBARA1_IN_PIT_TRIGGER3 IMXRT_XBARA1(XBAR_INPUT, 59) /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ +#define IMXRT_XBARA1_IN_ENC1_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 60) /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ +#define IMXRT_XBARA1_IN_ENC2_POS_MATCH IMXRT_XBARA1(XBAR_INPUT, 61) /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 62) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 63) */ +#define IMXRT_XBARA1_IN_DMA_DONE0 IMXRT_XBARA1(XBAR_INPUT, 64) /* DMA_DONE0 output assigned to XBARA1_IN64 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE1 IMXRT_XBARA1(XBAR_INPUT, 65) /* DMA_DONE1 output assigned to XBARA1_IN65 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE2 IMXRT_XBARA1(XBAR_INPUT, 66) /* DMA_DONE2 output assigned to XBARA1_IN66 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE3 IMXRT_XBARA1(XBAR_INPUT, 67) /* DMA_DONE3 output assigned to XBARA1_IN67 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE4 IMXRT_XBARA1(XBAR_INPUT, 68) /* DMA_DONE4 output assigned to XBARA1_IN68 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE5 IMXRT_XBARA1(XBAR_INPUT, 69) /* DMA_DONE5 output assigned to XBARA1_IN69 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE6 IMXRT_XBARA1(XBAR_INPUT, 70) /* DMA_DONE6 output assigned to XBARA1_IN70 input. */ +#define IMXRT_XBARA1_IN_DMA_DONE7 IMXRT_XBARA1(XBAR_INPUT, 71) /* DMA_DONE7 output assigned to XBARA1_IN71 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT0 IMXRT_XBARA1(XBAR_INPUT, 72) /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT1 IMXRT_XBARA1(XBAR_INPUT, 73) /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT2 IMXRT_XBARA1(XBAR_INPUT, 74) /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */ +#define IMXRT_XBARA1_IN_AOI1_OUT3 IMXRT_XBARA1(XBAR_INPUT, 75) /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 76) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 77) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 78) */ + +/* RESERVED IMXRT_XBARA1(XBAR_INPUT, 79) */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARA1(XBAR_INPUT, 80) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARA1(XBAR_INPUT, 81) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARA1(XBAR_INPUT, 82) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARA1(XBAR_INPUT, 83) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARA1(XBAR_INPUT, 84) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARA1(XBAR_INPUT, 85) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ +#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ + +/* XBARA1 Mux Output (M Muxes) *********************************************/ #define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ #define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ @@ -125,8 +149,10 @@ #define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 21) /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ #define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 22) /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ #define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 23) /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 24) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 25) RESERVED */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 24) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 25) */ #define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 26) /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ #define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 27) /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ #define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 28) /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ @@ -154,20 +180,34 @@ #define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 49) /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ #define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 50) /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ #define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 51) /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 52) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 53) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 54) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 55) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 56) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 57) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 58) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 59) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 60) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 61) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 62) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 63) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 64) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 65) RESERVED */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 52) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 53) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 54) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 55) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 56) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 57) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 58) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 59) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 60) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 61) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 62) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 63) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 64) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 65) */ #define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 66) /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN */ #define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 67) /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN */ #define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 68) /* XBARA1_OUT68 output assigned to ENC1_INDEX */ @@ -178,16 +218,26 @@ #define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 73) /* XBARA1_OUT73 output assigned to ENC2_INDEX */ #define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 74) /* XBARA1_OUT74 output assigned to ENC2_HOME */ #define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 75) /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 76) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 77) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 78) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 79) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 80) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 81) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 82) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 83) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 84) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 85) RESERVED */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 76) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 77) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 78) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 79) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 80) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 81) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 82) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 83) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 84) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 85) */ #define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 86) /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */ #define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 87) /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */ #define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 88) /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */ @@ -197,13 +247,20 @@ #define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 92) /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */ #define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 93) /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */ #define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 94) /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 95) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 96) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 97) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 98) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 99) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 100) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 101) RESERVED */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 95) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 96) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 97) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 98) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 99) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 100) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 101) */ #define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 102) /* XBARA1_OUT102 output assigned to EWM_EWM_IN */ #define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 103) /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ #define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 104) /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ @@ -231,24 +288,33 @@ #define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 126) /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN */ #define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 127) /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ #define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 128) /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 129) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 130) RESERVED */ -/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 131) RESERVED */ -/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 129) */ -#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ -#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 2) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 3) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 4) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 5) RESERVED */ -#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ -#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ -#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ -#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 10) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 11) RESERVED */ +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 130) */ + +/* RESERVED IMXRT_XBARA1(XBAR_OUTPUT, 131) */ + +/* XBARB2 Mux inputs (I values) *********************************************/ + +#define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ +#define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 2) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 3) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 4) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 5) */ +#define IMXRT_XBARB2_IN_ACMP1_OUT IMXRT_XBARB2(XBAR_INPUT, 6) /* ACMP1_OUT output assigned to XBARB2_IN6 input. */ +#define IMXRT_XBARB2_IN_ACMP2_OUT IMXRT_XBARB2(XBAR_INPUT, 7) /* ACMP2_OUT output assigned to XBARB2_IN7 input. */ +#define IMXRT_XBARB2_IN_ACMP3_OUT IMXRT_XBARB2(XBAR_INPUT, 8) /* ACMP3_OUT output assigned to XBARB2_IN8 input. */ +#define IMXRT_XBARB2_IN_ACMP4_OUT IMXRT_XBARB2(XBAR_INPUT, 9) /* ACMP4_OUT output assigned to XBARB2_IN9 input. */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 10) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 11) */ #define IMXRT_XBARB2_IN_QTIMER1_TMR0_OUT IMXRT_XBARB2(XBAR_INPUT, 12) /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ #define IMXRT_XBARB2_IN_QTIMER1_TMR1_OUT IMXRT_XBARB2(XBAR_INPUT, 13) /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ #define IMXRT_XBARB2_IN_QTIMER1_TMR2_OUT IMXRT_XBARB2(XBAR_INPUT, 14) /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ @@ -273,52 +339,62 @@ #define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 26) /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN26 input. */ #define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG0 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN27 input. */ #define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG1 IMXRT_XBARB2(XBAR_INPUT, 27) /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN27 input. */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 28) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 29) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 30) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 31) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 32) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 33) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 34) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 35) RESERVED */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ -#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ -#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ -#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ -#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 48) RESERVED */ -/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 49) RESERVED */ -#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ -#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ -/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 28) */ -#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ -#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ -#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ -#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ -#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ -#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ -#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ -#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ -#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ -#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ -#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ -#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ -#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ -#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ -#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ -#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 29) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 30) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 31) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 32) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 33) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 34) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 35) */ +#define IMXRT_XBARB2_IN_PIT_TRIGGER0 IMXRT_XBARB2(XBAR_INPUT, 36) /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ +#define IMXRT_XBARB2_IN_PIT_TRIGGER1 IMXRT_XBARB2(XBAR_INPUT, 37) /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0 IMXRT_XBARB2(XBAR_INPUT, 38) /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1 IMXRT_XBARB2(XBAR_INPUT, 39) /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2 IMXRT_XBARB2(XBAR_INPUT, 40) /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3 IMXRT_XBARB2(XBAR_INPUT, 41) /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0 IMXRT_XBARB2(XBAR_INPUT, 42) /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1 IMXRT_XBARB2(XBAR_INPUT, 43) /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARB2(XBAR_INPUT, 44) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ +#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARB2(XBAR_INPUT, 45) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ +#define IMXRT_XBARB2_IN_ENC1_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 46) /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ +#define IMXRT_XBARB2_IN_ENC2_POS_MATCH IMXRT_XBARB2(XBAR_INPUT, 47) /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 48) */ + +/* RESERVED IMXRT_XBARB2(XBAR_INPUT, 49) */ +#define IMXRT_XBARB2_IN_DMA_DONE0 IMXRT_XBARB2(XBAR_INPUT, 50) /* DMA_DONE0 output assigned to XBARB2_IN50 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE1 IMXRT_XBARB2(XBAR_INPUT, 51) /* DMA_DONE1 output assigned to XBARB2_IN51 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE2 IMXRT_XBARB2(XBAR_INPUT, 52) /* DMA_DONE2 output assigned to XBARB2_IN52 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE3 IMXRT_XBARB2(XBAR_INPUT, 53) /* DMA_DONE3 output assigned to XBARB2_IN53 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE4 IMXRT_XBARB2(XBAR_INPUT, 54) /* DMA_DONE4 output assigned to XBARB2_IN54 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE5 IMXRT_XBARB2(XBAR_INPUT, 55) /* DMA_DONE5 output assigned to XBARB2_IN55 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ +#define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ + +/* XBARB2 Mux Output (M Muxes) *********************************************/ + +#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ +#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ +#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 2) /* XBARB2_OUT2 output assigned to AOI1_IN02 */ +#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 3) /* XBARB2_OUT3 output assigned to AOI1_IN03 */ +#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 4) /* XBARB2_OUT4 output assigned to AOI1_IN04 */ +#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 5) /* XBARB2_OUT5 output assigned to AOI1_IN05 */ +#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 6) /* XBARB2_OUT6 output assigned to AOI1_IN06 */ +#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 7) /* XBARB2_OUT7 output assigned to AOI1_IN07 */ +#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 8) /* XBARB2_OUT8 output assigned to AOI1_IN08 */ +#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 9) /* XBARB2_OUT9 output assigned to AOI1_IN09 */ +#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 10) /* XBARB2_OUT10 output assigned to AOI1_IN10 */ +#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 11) /* XBARB2_OUT11 output assigned to AOI1_IN11 */ +#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 12) /* XBARB2_OUT12 output assigned to AOI1_IN12 */ +#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 13) /* XBARB2_OUT13 output assigned to AOI1_IN13 */ +#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ +#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h index a5fd8334df7..2135c002080 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,25 +32,26 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_CCM_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_CCM_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ + /* 0x0004 Reserved */ #define IMXRT_CCM_CSR_OFFSET 0x0008 /* CCM Status Register */ #define IMXRT_CCM_CCSR_OFFSET 0x000c /* CCM Clock Switcher Register */ @@ -63,13 +64,18 @@ #define IMXRT_CCM_CS1CDR_OFFSET 0x0028 /* CCM Clock Divider Register */ #define IMXRT_CCM_CS2CDR_OFFSET 0x002c /* CCM Clock Divider Register */ #define IMXRT_CCM_CDCDR_OFFSET 0x0030 /* CCM D1 Clock Divider Register */ + /* 0x0034 Reserved */ #define IMXRT_CCM_CSCDR2_OFFSET 0x0038 /* CCM Serial Clock Divider Register 2 */ #define IMXRT_CCM_CSCDR3_OFFSET 0x003c /* CCM Serial Clock Divider Register 3 */ + /* 0x0040 Reserved */ + /* 0x0044 Reserved */ #define IMXRT_CCM_CDHIPR_OFFSET 0x0048 /* CCM Divider Handshake In-Process Register */ + /* 0x004c Reserved */ + /* 0x0050 Reserved */ #define IMXRT_CCM_CLPCR_OFFSET 0x0054 /* CCM Low Power Control Register */ @@ -84,6 +90,7 @@ #define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */ #define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */ #define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */ + /* 0x0084 Reserved */ #define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Override Register */ @@ -109,7 +116,7 @@ #define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ #define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ -/* Register addresses ***************************************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) #define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) @@ -160,12 +167,12 @@ #define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) #define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) -/* Helper Macros ********************************************************************************************/ +/* Helper Macros ************************************************************/ #define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ #define CCM_PRED_FROM_DIVISOR(n) ((n)-1) /* PRED Values are divisor-1 */ -/* Register bit definitions *********************************************************************************/ +/* Register bit definitions *************************************************/ /* Control Register */ @@ -180,6 +187,7 @@ # define CCM_CCR_REG_BYPASS_COUNT(n) ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT) #define CCM_CCR_RBC_EN (1 << 27) /* Bit 27: Enable for REG_BYPASS_COUNTER */ /* Bits 28-31: Reserved */ + /* Status Register */ #define CCM_CSR_REF_EN_B (1 << 0) /* Bit 0: Status of the value of CCM_REF_EN_B */ @@ -188,6 +196,7 @@ /* Bit 4: Reserved */ #define CCM_CSR_COSC_READY (5 << 0) /* Bit 5: Status indication of on board oscillator */ /* Bits 6-31: Reserved */ + /* Clock Switcher Register */ #define CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Bit 0: Selects source to generate pll3_sw_clk */ @@ -200,7 +209,9 @@ /* Bus Clock Divider Register */ - /* Bits 0-5: Reserved */ +/* Bits 0-5: + * Reserved + */ #define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ #define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ #define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ @@ -222,15 +233,19 @@ # define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) # define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) - /* Bit 26: Reserved */ +/* Bits 26: + * Reserved + */ #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) # define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) - /* Bits 30-31: Reserved */ + /* Bits 30-31: Reserved */ /* Bus Clock Multiplexer Register */ - /* Bits 0-3: Reserved */ +/* Bits 0-3: + * Reserved + */ #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) # define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) @@ -424,7 +439,9 @@ /* Serial Clock Divider Register 2 */ - /* Bits 0-8: Reserved */ +/* Bits 0-8: + * Reserved + */ #define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for LCDIF root clock multiplexer */ #define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) # define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) @@ -445,6 +462,7 @@ # define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD0 ((uint32_t)(3) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) # define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD1 ((uint32_t)(4) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) # define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD1 ((uint32_t)(5) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT) + #define CCM_CSCDR2_LPI2C_CLK_SEL (1 << 18) /* Bit 18: Selector for the LPI2C clock multiplexer */ # define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M (0 << 18) /* derive clock from pll3_60m */ # define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK (1 << 18) /* derive clock from ock_clk */ @@ -455,7 +473,9 @@ /* Serial Clock Divider Register 3 */ - /* Bits 0-8: Reserved */ +/* Bits 0-8: + * Reserved + */ #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9) /* Bits 9-10: Selector for csi_mclk multiplexer */ #define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) # define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) @@ -487,7 +507,10 @@ # define CCM_CLPCR_LPM_RUN ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */ # define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ # define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ - /* Bits 2-4: Reserved */ + +/* Bits 2-4: + * Reserved + */ #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ #define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ #define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ @@ -766,7 +789,9 @@ /* Module Enable Override Register */ - /* Bits 0-4: Reserved */ +/* Bits 0-4: + * Reserved + */ #define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Override clock enable signal from GPT */ #define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Override clock enable signal from PIT */ #define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Override clock enable signal from USDHC */ @@ -788,6 +813,7 @@ #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ # define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ + #define CCM_ANALOG_PLL_ARM_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bits 17-18 Reserved */ #define CCM_ANALOG_PLL_ARM_PLL_SEL (1 << 39) /* Bit 19: ? */ @@ -809,6 +835,7 @@ # define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ # define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ # define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ + #define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bits 17-30 Reserved */ #define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ @@ -827,6 +854,7 @@ #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ # define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ + #define CCM_ANALOG_PLL_USB2_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bits 17-30 Reserved */ #define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ @@ -846,6 +874,7 @@ # define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ # define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ # define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ + #define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bit 17: Reserved */ #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ @@ -888,6 +917,7 @@ #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ # define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ + #define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bit 17: Reserved */ #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ @@ -912,6 +942,7 @@ #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) #define CCM_ANALOG_PLL_AUDIO_DENOM_B(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT) /* Bits 30-31: Reserved */ + /* Analog Video PLL control Register */ #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ @@ -924,6 +955,7 @@ #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ # define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ + #define CCM_ANALOG_PLL_VIDEO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ /* Bit 17: Reserved */ #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ @@ -966,19 +998,20 @@ /* Bits 4-11: Reserved */ #define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) # define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */ # define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ -#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ -#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ -#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ -#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */ -#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ +#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ + /* Bit 17: Reserved */ +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ +#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */ +#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */ + +#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ /* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_dmamux.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_dmamux.h index 674094e7583..99fce0cb2da 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_dmamux.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_dmamux.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_dmamux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_DMAMUX_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_DMAMUX_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Preprocessor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Peripheral DMA request channels */ diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h index b75d3c96126..5307b2df780 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_GPIO_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_GPIO_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ #define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ @@ -46,7 +46,7 @@ #define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ #define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) #define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h index e389cb1fbb0..e1b89a0ca7e 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_IOMUXC_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_IOMUXC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ #define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ @@ -766,7 +766,7 @@ #define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x0654 #define IMXRT_INPUT_XBAR1_IN21_OFFSET 0x0658 -/* Register addresses ***************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) #define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) @@ -1227,7 +1227,7 @@ #define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) #define IMXRT_INPUT_XBAR1_IN21 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN21_OFFSET) -/* Register bit definitions *********************************************************/ +/* Register bit definitions *************************************************/ /* General Purpose Register 0 (GPR0) - Reserved */ diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h index b89f3f2aaf2..f6afcb4a5be 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,76 +16,103 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* System memory map */ #define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */ + /* 0x00080000 512KB ITCM Reserved */ + /* 0x00100000 1MB ITCM Reserved */ #define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */ + /* 0x00218000 416KB ROMCP Reserved */ + /* 0x00280000 1536KB Reserved */ + /* 0x00400000 124MB Reserved */ #define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */ #define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */ #define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ + /* 0x20080000 512KB DTCM Reserved */ + /* 0x20100000 1MB Reserved */ #define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */ + /* 0x20280000 1536KB OCRAM Reserved */ + /* 0x20400000 252MB Reserved */ + /* 0x30000000 256MB Reserved */ #define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ #define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ #define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ #define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ + /* 40400000 12MB Reserved */ #define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */ #define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ + /* 41200000 1MB Reserved for "per" GPV */ + /* 41300000 1MB Reserved for "ems" GPV */ #define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ + /* 0x41500000 1MB GPV Reserved */ + /* 0x41600000 1MB GPV Reserved */ + /* 0x41700000 1MB GPV Reserved */ + /* 0x41800000 8MB Reserved */ + /* 0x42000000 32MB Reserved */ + /* 0x44000000 64MB Reserved */ + /* 0x48000000 384MB Reserved */ #define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */ #define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */ #define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ #define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ #define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ + /* 0xe0100000 511MB Reserved */ /* AIPS-1 memory map */ /* 0x40000000 256KB Reserved */ + /* 0x40040000 240KB Reserved */ #define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */ #define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ #define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ + /* 0x40088000 16KB Reserved */ + /* 0x4008c000 16KB Reserved */ #define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */ #define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ + /* 0x40098000 16KB Reserved */ + /* 0x4009c000 16KB Reserved */ + /* 0x400a0000 16KB Reserved */ #define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ #define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ @@ -102,10 +129,13 @@ #define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ #define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ #define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ + /* 0x400e0000 16KB Reserved */ + /* 0x400e4000 16KB Reserved */ #define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ #define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ + /* 400f0000 16KB Reserved */ #define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ #define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ @@ -114,6 +144,7 @@ /* AIPS-2 memory map */ /* 0x40100000 256KB Reserved */ + /* 0x40140000 240KB Reserved */ #define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ #define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ @@ -125,19 +156,25 @@ #define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ #define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ #define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ + /* 0x401a4000 16KB Reserved */ + /* 0x401a8000 16KB Reserved */ #define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ #define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */ + /* 0x401b4000 16KB Reserved */ #define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ #define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ #define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ #define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */ + /* 0x401c8000 16KB Reserved */ + /* 0x401cc000 16KB Reserved */ #define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ #define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ + /* 0x401d8000 16KB Reserved */ #define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */ #define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */ @@ -152,57 +189,84 @@ /* AIPS-3 memory map */ /* 0x40200000 256KB Reserved */ + /* 0x40240000 240KB Reserved */ #define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ + /* 0x40280000 16KB Reserved */ + /* 0x40284000 16KB Reserved */ + /* 0x40288000 16KB Reserved */ + /* 0x4028c000 16KB Reserved */ + /* 0x40290000 16KB Reserved */ + /* 0x40294000 16KB Reserved */ + /* 0x40298000 16KB Reserved */ + /* 0x4029c000 16KB Reserved */ + /* 0x402a0000 16KB Reserved */ + /* 0x402a4000 16KB Reserved */ #define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */ + /* 0x402ac000 16KB Reserved */ + /* 0x402b0000 16KB Reserved */ #define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */ #define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */ #define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */ #define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ #define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ + /* 0x402c8000 16KB Reserved */ + /* 0x402cc000 16KB Reserved */ + /* 0x402d0000 16KB Reserved */ + /* 0x402d4000 16KB Reserved */ #define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ #define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */ #define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ + /* 0x402e4000 16KB Reserved */ + /* 0x402e8000 16KB Reserved */ + /* 0x402ec000 16KB Reserved */ #define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ + /* 0x402f4000 16KB Reserved */ + /* 0x402f8000 16KB Reserved */ #define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ /* AIPS-4 memory map */ /* 0x40300000 256KB Reserved */ + /* 0x40340000 240KB Reserved */ #define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ #define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ #define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ #define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ #define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ + /* 0x40390000 16KB Reserved */ #define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ #define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ #define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ #define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ + /* 0x403a4000 16KB Reserved */ + /* 0x403a8000 16KB Reserved */ + /* 0x403ac000 16KB Reserved */ #define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ #define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ @@ -214,6 +278,7 @@ #define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ #define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */ #define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */ + /* 0x403d8000 16KB Reserved */ #define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ #define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ @@ -232,9 +297,12 @@ #define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ #define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ #define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ + /* 0xe0045000 236KB PPB Reserved */ #define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ + /* 0xe0081000 444KB PPB Reserved */ + /* 0xe00f0000 52KB PPB Reserved */ #define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ #define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h index 5271bf50607..63a9428bbdc 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_PINMUX_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_PINMUX_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "imxrt_iomuxc.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ /* Alternate Pin Functions. * diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_xbar.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_xbar.h index 697972163f6..56b35c1939f 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_xbar.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_xbar.h @@ -1,6 +1,6 @@ /* XBAR Defines for IMXRT1050 */ -/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ +/* XBARA1 Mux inputs (I values) *********************************************/ #define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ #define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ @@ -91,7 +91,7 @@ #define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ #define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ -/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ +/* XBARA1 Mux Output (M Muxes) *********************************************/ #define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ #define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ @@ -225,7 +225,7 @@ #define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ #define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ -/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ +/* XBARB2 Mux inputs (I values) *********************************************/ #define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ #define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ @@ -286,7 +286,7 @@ #define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ #define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ -/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ +/* XBARB2 Mux Output (M Muxes) *********************************************/ #define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ #define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ @@ -305,7 +305,7 @@ #define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ #define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ -/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/ +/* XBARB3 Mux inputs (I values) *********************************************/ #define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */ #define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */ @@ -366,7 +366,7 @@ #define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */ #define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */ -/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/ +/* XBARB3 Mux Output (M Muxes) *********************************************/ #define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */ #define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */ diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h index f8cc0290954..234431bd5af 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,23 +32,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_CCM_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_CCM_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_CCM_CCR_OFFSET 0x0000 /* CCM Control Register */ /* 0x0004 Reserved */ @@ -110,7 +110,7 @@ #define IMXRT_CCM_ANALOG_MISC1_OFFSET 0x0160 /* Miscellaneous Register 1 */ #define IMXRT_CCM_ANALOG_MISC2_OFFSET 0x0170 /* Miscellaneous Register 2 */ -/* Register addresses ***************************************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_CCM_CCR (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET) #define IMXRT_CCM_CSR (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET) @@ -162,12 +162,12 @@ #define IMXRT_CCM_ANALOG_MISC1 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET) #define IMXRT_CCM_ANALOG_MISC2 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET) -/* Helper Macros ********************************************************************************************/ +/* Helper Macros ************************************************************/ #define CCM_PODF_FROM_DIVISOR(n) ((n)-1) /* PODF Values are divisor-1 */ #define CCM_PRED_FROM_DIVISOR(n) ((n)-1) /* PRED Values are divisor-1 */ -/* Register bit definitions *********************************************************************************/ +/* Register bit definitions *************************************************/ /* Control Register */ @@ -204,7 +204,10 @@ /* Bus Clock Divider Register */ - /* Bits 0-5: Reserved */ +/* Bits 0-5: + * Reserved + */ + #define CCM_CBCDR_SEMC_CLK_SEL (1 << 6) /* Bit 6: SEMC clock source select */ #define CCM_CBCDR_SEMC_ALT_CLK_SEL (1 << 7) /* Bit 7: SEMC alternative clock select */ #define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2 (0 << 7) /* Bit 7: PLL2 PFD2 will be selected */ @@ -226,7 +229,10 @@ # define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH (0) # define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2 (1) - /* Bit 26: Reserved */ +/* Bit 26: + * Reserved + */ + #define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) /* Bits 27-29: Divider for periph_clk2_podf */ #define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) # define CCM_CBCDR_PERIPH_CLK2_PODF(n) ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) @@ -234,7 +240,10 @@ /* Bus Clock Multiplexer Register */ - /* Bits 0-3: Reserved */ +/* Bits 0-3: + * Reserved + */ + #define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4) /* Bits 4-5: Selector for lpspi clock multiplexer */ #define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) # define CCM_CBCMR_LPSPI_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) @@ -242,7 +251,11 @@ # define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0 ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) # define CCM_CBCMR_LPSPI_CLK_SEL_PLL2 ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) # define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2 ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT) - /* Bits 6-11: Reserved */ + +/* Bits 6-11: + * Reserved + */ + #define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */ #define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) # define CCM_CBCMR_PERIPH_CLK2_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT) @@ -256,7 +269,11 @@ # define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2 ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) # define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0 ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) # define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1 ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT) - /* Bits 16-17: Reserved */ + +/* Bits 16-17: + * Reserved + */ + #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) /* Bits 18-19: Selector for pre_periph clock multiplexer */ #define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) # define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n) ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT) @@ -428,7 +445,10 @@ /* Serial Clock Divider Register 2 */ - /* Bits 0-8: Reserved */ +/* Bits 0-8: + * Reserved + */ + #define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT (9) /* Bits 9-11: Selector for LCDIF root clock multiplexer */ #define CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) # define CCM_CSCDR2_LCDIF_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT) @@ -459,7 +479,10 @@ /* Serial Clock Divider Register 3 */ - /* Bits 0-8: Reserved */ +/* Bits 0-8: + * Reserved + */ + #define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9) /* Bits 9-10: Selector for csi_mclk multiplexer */ #define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) # define CCM_CSCDR3_CSI_CLK_SEL(n) ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT) @@ -492,7 +515,9 @@ # define CCM_CLPCR_LPM_WAIT ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */ # define CCM_CLPCR_LPM_STOP ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */ - /* Bits 2-4: Reserved */ +/* Bits 2-4: + * Reserved + */ #define CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) /* Bit 5: ARM clocks disabled on wait mode */ #define CCM_CLPCR_SBYOS (1 << 6) /* Bit 6: Standby clock oscillator bit */ #define CCM_CLPCR_DIS_REF_OSC (1 << 7) /* Bit 7: external high frequency oscillator disable */ @@ -779,7 +804,9 @@ /* Module Enable Override Register */ - /* Bits 0-4: Reserved */ +/* Bits 0-4: + * Reserved + */ #define CCM_CMEOR_MOD_EN_OV_GPT (1 << 5) /* Bit 5: Override clock enable signal from GPT */ #define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Override clock enable signal from PIT */ #define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Override clock enable signal from USDHC */ @@ -804,7 +831,9 @@ # define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ #define CCM_ANALOG_PLL_ARM_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-18 Reserved */ +/* Bits 17-18 + * Reserved + */ #define CCM_ANALOG_PLL_ARM_PLL_SEL (1 << 39) /* Bit 19: ? */ #define CCM_ANALOG_PLL_ARM_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ @@ -826,7 +855,9 @@ # define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* */ #define CCM_ANALOG_PLL_USB1_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ +/* Bits 17-30 + * Reserved + */ #define CCM_ANALOG_PLL_USB1_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ /* Analog USB2 480MHz PLL Control Register */ @@ -845,7 +876,10 @@ # define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ #define CCM_ANALOG_PLL_USB2_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bits 17-30 Reserved */ +/* Bits 17-30 + * Reserved + */ + #define CCM_ANALOG_PLL_USB2_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ /* Analog System PLL Control Register */ @@ -865,10 +899,15 @@ # define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* */ #define CCM_ANALOG_PLL_SYS_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ +/* Bit 17: + * Reserved + */ + #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ - /* Bits 19-30 Reserved */ +/* Bits 19-30 + * Reserved + */ #define CCM_ANALOG_PLL_SYS_LOCK (1 << 31) /* Bit 31: PLL is currently locked */ /* 528MHz System PLL Spread Spectrum Register */ @@ -900,7 +939,10 @@ #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0) /* Bits 0-6: This field controls the PLL loop divider: 27-54 */ #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) # define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n) ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT) - /* Bits 7-11: Reserved */ + +/* Bits 7-11: + * Reserved + */ #define CCM_ANALOG_PLL_AUDIO_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */ #define CCM_ANALOG_PLL_AUDIO_ENABLE (1 << 13) /* Bit 13: Enable PLL output */ #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */ @@ -909,7 +951,9 @@ # define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ #define CCM_ANALOG_PLL_AUDIO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ +/* Bit 17: + * Reserved + */ #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT) @@ -947,7 +991,9 @@ # define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ #define CCM_ANALOG_PLL_VIDEO_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ +/* Bit 17: + * Reserved + */ #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19) /* Bits 19-20: These bits implement a divider after the PLL */ #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x7f << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT) @@ -994,7 +1040,9 @@ # define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */ #define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */ - /* Bit 17: Reserved */ +/* Bit 17: + * Reserved + */ #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */ #define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */ #define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */ diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h index 923104359cb..1b9703b634e 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_DMAMUX_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_DMAMUX_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Preprocessor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Peripheral DMA request channels */ diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h index 6413e71a293..35cb35253be 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_GPIO_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_GPIO_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ #define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ @@ -46,7 +46,7 @@ #define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ #define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) #define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h index 08cd65169ac..f4b9ef47b79 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_IOMUXC_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_IOMUXC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/imxrt_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************/ +/* Register offsets *********************************************************/ #define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ #define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ @@ -911,7 +911,7 @@ #define IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET 0x0788 #define IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET 0x078C -/* Register addresses ***************************************************************/ +/* Register addresses *******************************************************/ #define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) #define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) @@ -1471,7 +1471,7 @@ #define IMXRT_INPUT_SEMC_I_IPP_IND_DQS4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET) #define IMXRT_INPUT_CANFD_IPP_IND_CANRX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET) -/* Register bit definitions *********************************************************/ +/* Register bit definitions *************************************************/ /* General Purpose Register 0 (GPR0) - Reserved */ diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h index 39f6a0ae737..5e828c29e08 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_PINMUX_H #define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_PINMUX_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "imxrt_iomuxc.h" #include "imxrt_gpio.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ /* Alternate Pin Functions. * diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_xbar.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_xbar.h index 3d697880494..b997fe05fb3 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_xbar.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_xbar.h @@ -1,6 +1,6 @@ /* XBAR Defines for IMXRT1060 */ -/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/ +/* XBARA1 Mux inputs (I values) *********************************************/ #define IMXRT_XBARA1_IN_LOGIC_LOW IMXRT_XBARA1(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARA1_IN0 input. */ #define IMXRT_XBARA1_IN_LOGIC_HIGH IMXRT_XBARA1(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */ @@ -91,7 +91,7 @@ #define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2 IMXRT_XBARA1(XBAR_INPUT, 86) /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ #define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3 IMXRT_XBARA1(XBAR_INPUT, 87) /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ -/* XBARA1 Mux Output (M Muxes) ***************************************************************************************************************/ +/* XBARA1 Mux Output (M Muxes) *********************************************/ #define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 0) /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ #define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 1) /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ @@ -225,7 +225,7 @@ #define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 129) /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ #define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 130) /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ -/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/ +/* XBARB2 Mux inputs (I values) *********************************************/ #define IMXRT_XBARB2_IN_LOGIC_LOW IMXRT_XBARB2(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB2_IN0 input. */ #define IMXRT_XBARB2_IN_LOGIC_HIGH IMXRT_XBARB2(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */ @@ -286,7 +286,7 @@ #define IMXRT_XBARB2_IN_DMA_DONE6 IMXRT_XBARB2(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB2_IN56 input. */ #define IMXRT_XBARB2_IN_DMA_DONE7 IMXRT_XBARB2(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB2_IN57 input. */ -/* XBARB2 Mux Output (M Muxes) ********************************************************************************************************************/ +/* XBARB2 Mux Output (M Muxes) *********************************************/ #define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 0) /* XBARB2_OUT0 output assigned to AOI1_IN00 */ #define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 1) /* XBARB2_OUT1 output assigned to AOI1_IN01 */ @@ -305,7 +305,7 @@ #define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 14) /* XBARB2_OUT14 output assigned to AOI1_IN14 */ #define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET IMXRT_XBARB2(XBAR_OUTPUT, 15) /* XBARB2_OUT15 output assigned to AOI1_IN15 */ -/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/ +/* XBARB3 Mux inputs (I values) *********************************************/ #define IMXRT_XBARB3_IN_LOGIC_LOW IMXRT_XBARB3(XBAR_INPUT, 0) /* LOGIC_LOW output assigned to XBARB3_IN0 input. */ #define IMXRT_XBARB3_IN_LOGIC_HIGH IMXRT_XBARB3(XBAR_INPUT, 1) /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */ @@ -366,7 +366,7 @@ #define IMXRT_XBARB3_IN_DMA_DONE6 IMXRT_XBARB3(XBAR_INPUT, 56) /* DMA_DONE6 output assigned to XBARB3_IN56 input. */ #define IMXRT_XBARB3_IN_DMA_DONE7 IMXRT_XBARB3(XBAR_INPUT, 57) /* DMA_DONE7 output assigned to XBARB3_IN57 input. */ -/* XBARB3 Mux Output (M Muxes) ********************************************************************************************************************/ +/* XBARB3 Mux Output (M Muxes) *********************************************/ #define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 0) /* XBARB3_OUT0 output assigned to AOI2_IN00 */ #define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET IMXRT_XBARB3(XBAR_OUTPUT, 1) /* XBARB3_OUT1 output assigned to AOI2_IN01 */ diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c index 3e30b664b40..a1d2f3b3acb 100644 --- a/arch/arm/src/imxrt/imxrt_allocateheap.c +++ b/arch/arm/src/imxrt/imxrt_allocateheap.c @@ -250,7 +250,8 @@ * aligned). */ -const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; +const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + + CONFIG_IDLETHREAD_STACKSIZE; /**************************************************************************** * Public Functions @@ -285,7 +286,8 @@ const uintptr_t g_idle_topstack = (uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZ * * Kernel .data region. Size determined at link time. * Kernel .bss region Size determined at link time. - * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Kernel IDLE thread stack. (size determined by + * CONFIG_IDLETHREAD_STACKSIZE). * Padding for alignment * User .data region. Size determined at link time. * User .bss region Size determined at link time. @@ -306,7 +308,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; size_t usize = PRIMARY_RAM_END - ubase; DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END); @@ -345,7 +348,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). */ - uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + + CONFIG_MM_KERNEL_HEAPSIZE; DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END); /* Return the kernel heap settings (i.e., the part of the heap region diff --git a/arch/arm/src/imxrt/imxrt_clrpend.c b/arch/arm/src/imxrt/imxrt_clrpend.c index e153006164f..9a9f26bdefc 100644 --- a/arch/arm/src/imxrt/imxrt_clrpend.c +++ b/arch/arm/src/imxrt/imxrt_clrpend.c @@ -39,7 +39,7 @@ * Name: imxrt_clrpend * * Description: - * Clear a pending interrupt at the NVIC. This does not seem to be required + * Clear a pending interrupt at the NVIC. This does not seem to be required * for most interrupts. Don't know why... but the LPC54xx Ethernet EMAC * interrupt definitely needs it! * @@ -57,30 +57,35 @@ void imxrt_clrpend(int irq) { if (irq < (IMXRT_IRQ_EXTINT + 32)) { - putreg32(1 << (irq - IMXRT_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND); + putreg32(1 << (irq - IMXRT_IRQ_EXTINT), + NVIC_IRQ0_31_CLRPEND); } #if IMXRT_IRQ_NEXTINT >= 64 else if (irq < (IMXRT_IRQ_EXTINT + 64)) { - putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND); + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 32), + NVIC_IRQ32_63_CLRPEND); } #endif #if IMXRT_IRQ_NEXTINT >= 96 else if (irq < (IMXRT_IRQ_EXTINT + 96)) { - putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 64), NVIC_IRQ64_95_CLRPEND); + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 64), + NVIC_IRQ64_95_CLRPEND); } #endif #if IMXRT_IRQ_NEXTINT >= 128 else if (irq < (IMXRT_IRQ_EXTINT + 128)) { - putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 96), NVIC_IRQ96_127_CLRPEND); + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 96), + NVIC_IRQ96_127_CLRPEND); } #endif #if IMXRT_IRQ_NEXTINT >= 160 else if (irq < (IMXRT_IRQ_EXTINT + 160)) { - putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 128), NVIC_IRQ128_159_CLRPEND); + putreg32(1 << (irq - IMXRT_IRQ_EXTINT - 128), + NVIC_IRQ128_159_CLRPEND); } #endif else diff --git a/arch/arm/src/imxrt/imxrt_config.h b/arch/arm/src/imxrt/imxrt_config.h index ba2ab74440c..8fb3d84b7d9 100644 --- a/arch/arm/src/imxrt/imxrt_config.h +++ b/arch/arm/src/imxrt/imxrt_config.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration *********************************************************************/ +/* Configuration ************************************************************/ #undef HAVE_LPUART1 #undef HAVE_LPUART2 @@ -81,8 +81,8 @@ # define HAVE_LPUART_DEVICE 1 #endif -/* Is there a serial console? There should be at most one defined. It could be on - * any LPUARTn, n=1,2,3,4,5,6,7,8 +/* Is there a serial console? There should be at most one defined. + * It could be on any LPUARTn, n=1,2,3,4,5,6,7,8 */ #undef HAVE_LPUART_CONSOLE @@ -200,8 +200,8 @@ #define IMXRT_ENET_HAS_DBSWAP 1 -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_CONFIG_H */ diff --git a/arch/arm/src/imxrt/imxrt_edma.h b/arch/arm/src/imxrt/imxrt_edma.h index f21c7a23693..4772593daac 100644 --- a/arch/arm/src/imxrt/imxrt_edma.h +++ b/arch/arm/src/imxrt/imxrt_edma.h @@ -1,11 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_edma.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Portions of the eDMA logic derive from NXP sample code which has a compatible - * BSD 3-clause license: + * Portions of the eDMA logic derive from NXP sample code which has a + * compatible BSD 3-clause license: * * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP @@ -38,7 +38,7 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_EDMAC_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_EDMAC_H @@ -65,46 +65,48 @@ * int ret; * ret = imxrt_dmach_xfrsetup(handle, &config); * - * 4. If you are setting up a scatter gather DMA (with CONFIG_IMXRT_EDMA_NTCD > 0), + * 4. If you are setting up a scatter gather DMA + * (with CONFIG_IMXRT_EDMA_NTCD > 0), * then repeat steps 2 and 3 for each segment of the transfer. * * 5. Start the DMA: * * ret = imxrt_dmach_start(handle, my_callback_func, priv); * - * Where my_callback_func() is called when the DMA completes or an error occurs. - * 'priv' represents some internal driver state that will be provided with the - * callback. + * Where my_callback_func() is called when the DMA completes or an error + * occurs. 'priv' represents some internal driver state that will be + * provided with the callback. * - * 6. If you need to stop the DMA and free resources (such as if a timeout occurs), - * then: + * 6. If you need to stop the DMA and free resources (such as if a timeout + * occurs), then: * * i mxrt_dmach_stop(handle); * - * 7. The callback will be received when the DMA completes (or an error occurs). - * After that, you may free the DMA channel, or re-use it on subsequent DMAs. + * 7. The callback will be received when the DMA completes (or an error + * occurs). After that, you may free the DMA channel, or re-use it on + * subsequent DMAs. * * imxrt_dmach_free(handle); * * Almost non-invasive debug instrumentation is available. You may call - * imxrt_dmasample() to save the current state of the eDMA registers at any given - * point in time. At some later, postmortem analysis, you can dump the content of - * the buffered registers with imxrt_dmadump(). imxrt_dmasample() is also available - * for monitoring DMA progress. + * imxrt_dmasample() to save the current state of the eDMA registers at any + * given point in time. At some later, postmortem analysis, you can dump the + * content of the buffered registers with imxrt_dmadump(). imxrt_dmasample() + * is also available for monitoring DMA progress. */ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/imxrt_edma.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Configuration flags. * @@ -119,9 +121,9 @@ # define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */ # define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ typedef FAR void *DMACH_HANDLE; typedef void (*edma_callback_t)(DMACH_HANDLE handle, @@ -136,7 +138,9 @@ enum imxrt_edma_xfrtype_e EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */ }; -/* This structure holds the source/destination transfer attribute configuration. */ +/* This structure holds the source/destination transfer attribute + * configuration. + */ struct imxrt_edma_xfrconfig_s { @@ -202,15 +206,15 @@ struct imxrt_dmaregs_s }; #endif /* CONFIG_DEBUG_DMA */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -221,11 +225,11 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmach_alloc * * Allocate a DMA channel. This function sets aside a DMA channel, @@ -234,7 +238,8 @@ extern "C" * * Input Parameters: * dmamux - DMAMUX configuration see DMAMUX channel configuration register - * bit-field definitions in hardware/imxrt_dmamux.h. Settings include: + * bit-field definitions in hardware/imxrt_dmamux.h. + * Settings include: * * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) * DMAMUX_CHCFG_AON DMA Channel Always Enable (optional) @@ -256,25 +261,26 @@ extern "C" * If a DMA channel is available, this function returns a non-NULL, void* * DMA channel handle. NULL is returned on any failure. * - ************************************************************************************/ + ****************************************************************************/ DMACH_HANDLE imxrt_dmach_alloc(uint32_t dmamux, uint8_t dchpri); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmach_free * * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must NEVER be - * used again until imxrt_dmach_alloc() is called again to re-gain a valid handle. + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again until + * imxrt_dmach_alloc() is called again to re-gain a valid handle. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void imxrt_dmach_free(DMACH_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmach_xfrsetup * * Description: @@ -283,7 +289,8 @@ void imxrt_dmach_free(DMACH_HANDLE handle); * structure. For "normal" DMA, imxrt_dmach_xfrsetup is called only once. * Scatter/gather DMA is accomplished by calling this function repeatedly, * once for each transfer in the sequence. Scatter/gather DMA processing - * is enabled automatically when the second transfer configuration is received. + * is enabled automatically when the second transfer configuration is + * received. * * This function may be called multiple times to handle multiple, * discontinuous transfers (scatter-gather) @@ -297,52 +304,55 @@ void imxrt_dmach_free(DMACH_HANDLE handle); * Zero (OK) is returned on success; a negated errno value is returned on * any failure. * - ************************************************************************************/ + ****************************************************************************/ int imxrt_dmach_xfrsetup(DMACH_HANDLE *handle, const struct imxrt_edma_xfrconfig_s *config); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmach_start * * Description: - * Start the DMA transfer by enabling the channel DMA request. This function - * should be called after the final call to imxrt_dmasetup() in order to avoid - * race conditions. + * Start the DMA transfer by enabling the channel DMA request. This + * function should be called after the final call to imxrt_dmasetup() in + * order to avoid race conditions. * - * At the conclusion of each major DMA loop, a callback to the user-provided - * function is made: |For "normal" DMAs, this will correspond to the DMA DONE - * interrupt; for scatter gather DMAs, multiple interrupts will be generated - * with the final being the DONE interrupt. + * At the conclusion of each major DMA loop, a callback to the + * user-provided function is made: |For "normal" DMAs, this will + * correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple + * interrupts will be generated with the final being the DONE interrupt. * - * At the conclusion of the DMA, the DMA channel is reset, all TCDs are freed, and - * the callback function is called with the the success/fail result of the DMA. + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. * - * NOTE: On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary - * to invalidate the destination memory. That is not done automatically by the - * DMA module. Invalidation of the destination memory regions is the - * responsibility of the caller. + * NOTE: On Rx DMAs (peripheral-to-memory or memory-to-memory), it is + * necessary to invalidate the destination memory. That is not done + * automatically by the DMA module. Invalidation of the destination memory + * regions is the responsibility of the caller. * * Input Parameters: * handle - DMA channel handle created by imxrt_dmach_alloc() - * callback - The callback to be invoked when the DMA is completes or is aborted. + * callback - The callback to be invoked when the DMA is completes or is + * aborted. * arg - An argument that accompanies the callback * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned on * any failure. * - ************************************************************************************/ + ****************************************************************************/ -int imxrt_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, void *arg); +int imxrt_dmach_start(DMACH_HANDLE handle, + edma_callback_t callback, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmach_stop * * Description: - * Cancel the DMA. After imxrt_dmach_stop() is called, the DMA channel is reset, - * all TCDs are freed, and imxrt_dmarx/txsetup() must be called before - * imxrt_dmach_start() can be called again + * Cancel the DMA. After imxrt_dmach_stop() is called, the DMA channel is + * reset, all TCDs are freed, and imxrt_dmarx/txsetup() must be called + * before imxrt_dmach_start() can be called again * * Input Parameters: * handle - DMA channel handle created by imxrt_dmach_alloc() @@ -350,11 +360,11 @@ int imxrt_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, void *arg); * Returned Value: * None. * - ************************************************************************************/ + ****************************************************************************/ void imxrt_dmach_stop(DMACH_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmach_getcount * * Description: @@ -377,7 +387,8 @@ void imxrt_dmach_stop(DMACH_HANDLE handle); * initial value of NBYTES (for example copied before enabling the channel) * is needed. The formula to calculate it is shown below: * - * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + * RemainingBytes = RemainingMajorLoopCount * NBYTES + * (initially configured) * * Input Parameters: * handle - DMA channel handle created by imxrt_dmach_alloc() @@ -385,17 +396,17 @@ void imxrt_dmach_stop(DMACH_HANDLE handle); * Returned Value: * Major loop count which has not been transferred yet for the current TCD. * - ************************************************************************************/ + ****************************************************************************/ unsigned int imxrt_dmach_getcount(DMACH_HANDLE *handle); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmasample * * Description: * Sample DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA void imxrt_dmasample(DMACH_HANDLE handle, struct imxrt_dmaregs_s *regs); @@ -403,13 +414,13 @@ void imxrt_dmasample(DMACH_HANDLE handle, struct imxrt_dmaregs_s *regs); # define imxrt_dmasample(handle,regs) #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_dmadump * * Description: * Dump previously sampled DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA void imxrt_dmadump(const struct imxrt_dmaregs_s *regs, const char *msg); diff --git a/arch/arm/src/imxrt/imxrt_ehci.c b/arch/arm/src/imxrt/imxrt_ehci.c index 1df6c700cae..4576de0ac2f 100644 --- a/arch/arm/src/imxrt/imxrt_ehci.c +++ b/arch/arm/src/imxrt/imxrt_ehci.c @@ -210,7 +210,9 @@ struct imxrt_qh_s uint8_t pad[8]; /* Padding to assure 32-byte alignment */ }; -/* Internal representation of the EHCI Queue Element Transfer Descriptor (qTD) */ +/* Internal representation of the EHCI Queue Element Transfer Descriptor + * (qTD) + */ struct imxrt_qtd_s { @@ -2368,7 +2370,9 @@ static int imxrt_async_setup(struct imxrt_rhport_s *rhport, tokenbits |= QTD_TOKEN_PID_IN; } - /* Allocate a new Queue Element Transfer Descriptor (qTD) for the status */ + /* Allocate a new Queue Element Transfer Descriptor (qTD) + * for the status + */ qtd = imxrt_qtd_statusphase(tokenbits); if (qtd == NULL) @@ -4163,7 +4167,9 @@ static int imxrt_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer) { DEBUGASSERT(drvr && buffer); - /* No special action is require to free the transfer/descriptor buffer memory */ + /* No special action is require to free the transfer/descriptor buffer + * memory + */ kmm_free(buffer); return OK; @@ -4309,7 +4315,9 @@ static int imxrt_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, req->index[1], req->index[0], len); #endif - /* We must have exclusive access to the EHCI hardware and data structures. */ + /* We must have exclusive access to the EHCI hardware and data + * structures. + */ ret = imxrt_takesem(&g_ehci.exclsem); if (ret < 0) @@ -4409,7 +4417,9 @@ static ssize_t imxrt_transfer(FAR struct usbhost_driver_s *drvr, DEBUGASSERT(rhport && epinfo && buffer && buflen > 0); - /* We must have exclusive access to the EHCI hardware and data structures. */ + /* We must have exclusive access to the EHCI hardware and data + * structures. + */ ret = imxrt_takesem(&g_ehci.exclsem); if (ret < 0) @@ -4417,7 +4427,9 @@ static ssize_t imxrt_transfer(FAR struct usbhost_driver_s *drvr, return (ssize_t)ret; } - /* Set the request for the IOC event well BEFORE initiating the transfer. */ + /* Set the request for the IOC event well BEFORE initiating the + * transfer. + */ ret = imxrt_ioc_setup(rhport, epinfo); if (ret != OK) @@ -4519,7 +4531,9 @@ static int imxrt_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, DEBUGASSERT(rhport && epinfo && buffer && buflen > 0); - /* We must have exclusive access to the EHCI hardware and data structures. */ + /* We must have exclusive access to the EHCI hardware and data + * structures. + */ ret = imxrt_takesem(&g_ehci.exclsem); if (ret < 0) @@ -4956,7 +4970,9 @@ static int imxrt_reset(void) return -ETIMEDOUT; } - /* Now we can set the HCReset bit in the USBCMD register to initiate the reset */ + /* Now we can set the HCReset bit in the USBCMD register to initiate the + * reset + */ regval = imxrt_getreg(&HCOR->usbcmd); regval |= EHCI_USBCMD_HCRESET; @@ -5339,7 +5355,9 @@ FAR struct usbhost_connection_s *imxrt_ehci_initialize(int controller) imxrt_putreg(regval, &HCOR->usbcmd); - /* Start the host controller by setting the RUN bit in the USBCMD register. */ + /* Start the host controller by setting the RUN bit in the USBCMD + * register. + */ regval = imxrt_getreg(&HCOR->usbcmd); regval |= EHCI_USBCMD_RUN; diff --git a/arch/arm/src/imxrt/imxrt_ehci.h b/arch/arm/src/imxrt/imxrt_ehci.h index 3adae182ec1..5a646999d77 100644 --- a/arch/arm/src/imxrt/imxrt_ehci.h +++ b/arch/arm/src/imxrt/imxrt_ehci.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/imxrt_ehci.h * * Copyright (C) 2012, 2015, 2019 Gregory Nutt. All rights reserved. @@ -32,31 +32,31 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_EHCI_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_EHCI_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Public Types - *****************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/***************************************************************************** +/**************************************************************************** * Public Data - *****************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -67,16 +67,17 @@ extern "C" #define EXTERN extern #endif -/***************************************************************************** +/**************************************************************************** * Public Function Prototypes - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: imxrt_usbhost_vbusdrive * * Description: - * Enable/disable driving of VBUS 5V output. This function must be provided - * by each platform that implements the OHCI or EHCI host interface + * Enable/disable driving of VBUS 5V output. This function must be + * provided by each platform that implements the OHCI or EHCI host + * interface * * Input Parameters: * rhport - Selects root hub port to be powered host interface. Since the @@ -87,16 +88,16 @@ extern "C" * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ extern void imxrt_usbhost_vbusdrive(int rhport, bool enable); -/***************************************************************************** +/**************************************************************************** * Name: imxrt_setup_overcurrent * * Description: - * Setup to receive an interrupt-level callback if an over-current condition - * is detected. + * Setup to receive an interrupt-level callback if an over-current + * condition is detected. * * Input Parameters: * handler - New over-current interrupt handler @@ -106,11 +107,11 @@ extern void imxrt_usbhost_vbusdrive(int rhport, bool enable); * Zero (OK) returned on success; a negated errno value is returned on * failure. * - *****************************************************************************/ + ****************************************************************************/ extern int imxrt_setup_overcurrent(xcpt_t handler, void *arg); -/***************************************************************************** +/**************************************************************************** * Name: imxrt_ehci_initialize * * Description: diff --git a/arch/arm/src/imxrt/imxrt_enc.c b/arch/arm/src/imxrt/imxrt_enc.c index a07d8397760..61ad1025315 100644 --- a/arch/arm/src/imxrt/imxrt_enc.c +++ b/arch/arm/src/imxrt/imxrt_enc.c @@ -1034,13 +1034,17 @@ static int imxrt_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, struct imxrt_enc_lowerhalf_s *priv = (struct imxrt_enc_lowerhalf_s *)lower; switch (cmd) { - /* QEIOC_POSDIFF: returns the content of the Position Difference register */ + /* QEIOC_POSDIFF: + * returns the content of the Position Difference register + */ case QEIOC_POSDIFF: *((uint16_t *)arg) = imxrt_enc_getreg16(priv, IMXRT_ENC_POSD_OFFSET); break; - /* QEIOC_REVOLUTION: returns the content of the Position Difference register */ + /* QEIOC_REVOLUTION: + * returns the content of the Position Difference register + */ case QEIOC_REVOLUTION: *((uint16_t *)arg) = imxrt_enc_getreg16(priv, IMXRT_ENC_REV_OFFSET); diff --git a/arch/arm/src/imxrt/imxrt_enc.h b/arch/arm/src/imxrt/imxrt_enc.h index a3cd71601ea..baadd244366 100644 --- a/arch/arm/src/imxrt/imxrt_enc.h +++ b/arch/arm/src/imxrt/imxrt_enc.h @@ -65,12 +65,13 @@ * Name: imxrt_qeinitialize * * Description: - * Initialize a quadrature encoder interface. This function must be called from - * board-specific logic.. + * Initialize a quadrature encoder interface. This function must be called + * from board-specific logic.. * * Input Parameters: * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * enc - The encoder peripheral to use. 'enc' must be an element of {1,2,3,4} + * enc - The encoder peripheral to use. + * 'enc' must be an element of {1,2,3,4} * * Returned Value: * Zero on success; A negated errno value is returned on failure. diff --git a/arch/arm/src/imxrt/imxrt_enet.h b/arch/arm/src/imxrt/imxrt_enet.h index e641894ae94..8d42e2b5869 100644 --- a/arch/arm/src/imxrt/imxrt_enet.h +++ b/arch/arm/src/imxrt/imxrt_enet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_enet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_ENET_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_ENET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,17 +31,17 @@ #ifdef CONFIG_IMXRT_ENET -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Definitions for use with imxrt_phy_boardinitialize */ #define EMAC_INTF 0 -/************************************************************************************ +/**************************************************************************** * Public Functions Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -54,7 +54,7 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Function: arm_netinitialize * * Description: @@ -72,41 +72,42 @@ extern "C" * Assumptions: * Called very early in the initialization sequence. * - ************************************************************************************/ + ****************************************************************************/ #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void); #else -/************************************************************************************ +/**************************************************************************** * Function: imxrt_netinitialize * * Description: * Initialize the Ethernet controller and driver * * Input Parameters: - * intf - In the case where there are multiple EMACs, this value identifies which - * EMAC is to be initialized. + * intf - In the case where there are multiple EMACs, this value identifies + * which EMAC is to be initialized. * * Returned Value: * OK on success; Negated errno on failure. * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ int imxrt_netinitialize(int intf); #endif -/************************************************************************************ +/**************************************************************************** * Function: imxrt_phy_boardinitialize * * Description: - * Some boards require specialized initialization of the PHY before it can be - * used. This may include such things as configuring GPIOs, resetting the PHY, - * etc. If CONFIG_IMXRT_ENET_PHYINIT is defined in the configuration then the - * board specific logic must provide imxrt_phyinitialize(); The i.MX RT Ethernet - * driver will call this function one time before it first uses the PHY. + * Some boards require specialized initialization of the PHY before it can + * be used. This may include such things as configuring GPIOs, resetting + * the PHY, etc. If CONFIG_IMXRT_ENET_PHYINIT is defined in the + * configuration then the board specific logic must provide + * imxrt_phyinitialize(); The i.MX RT Ethernet driver will call this + * function one time before it first uses the PHY. * * Input Parameters: * intf - Always zero for now. @@ -114,7 +115,7 @@ int imxrt_netinitialize(int intf); * Returned Value: * OK on success; Negated errno on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_ENET_PHYINIT int imxrt_phy_boardinitialize(int intf); diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c index c5cd1b7a4a3..b0bb6551179 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.c +++ b/arch/arm/src/imxrt/imxrt_gpio.c @@ -373,7 +373,9 @@ static const uint8_t * const g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = * Public Data ****************************************************************************/ -/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base addresses */ +/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base + * addresses + */ const uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = { @@ -422,13 +424,15 @@ static uintptr_t imxrt_padmux_address(unsigned int index) #if defined(IMXRT_PAD1MUX_OFFSET) if (index >= IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX) { - return (IMXRT_PAD1MUX_OFFSET(index - IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX)); + return (IMXRT_PAD1MUX_OFFSET(index - + IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX)); } #endif if (index >= IMXRT_PADMUX_WAKEUP_INDEX) { - return (IMXRT_PADMUX_ADDRESS_SNVS(index - IMXRT_PADMUX_WAKEUP_INDEX)); + return (IMXRT_PADMUX_ADDRESS_SNVS(index - + IMXRT_PADMUX_WAKEUP_INDEX)); } return (IMXRT_PADMUX_ADDRESS(index)); @@ -443,13 +447,15 @@ static uintptr_t imxrt_padctl_address(unsigned int index) #if defined(IMXRT_PAD1CTL_OFFSET) if (index >= IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX) { - return (IMXRT_PAD1CTL_OFFSET(index - IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX)); + return (IMXRT_PAD1CTL_OFFSET(index - + IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX)); } #endif if (index >= IMXRT_PADCTL_WAKEUP_INDEX) { - return (IMXRT_PADCTL_ADDRESS_SNVS(index - IMXRT_PADCTL_WAKEUP_INDEX)); + return (IMXRT_PADCTL_ADDRESS_SNVS(index - + IMXRT_PADCTL_WAKEUP_INDEX)); } return (IMXRT_PADCTL_ADDRESS(index)); @@ -678,7 +684,7 @@ static inline int imxrt_gpio_configperiph(gpio_pinset_t pinset) imxrt_daisy_select(index, alt); - /* Configure pin pad settings SW PAD Control Register*/ + /* Configure pin pad settings SW PAD Control Register */ index = imxrt_padmux_map(index); if (index >= IMXRT_PADCTL_NREGISTERS) diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h index dd4f66e0bf1..2cc957ef53c 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.h +++ b/arch/arm/src/imxrt/imxrt_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,9 +33,9 @@ #include "chip.h" #include "hardware/imxrt_gpio.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* 32-bit Encoding: * @@ -230,17 +230,17 @@ #define IMXRT_GPIO_CLEAR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_CLEAR_OFFSET) #define IMXRT_GPIO_TOGGLE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_TOGGLE_OFFSET) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* The smallest integer type that can hold the GPIO encoding */ typedef uint32_t gpio_pinset_t; -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -251,21 +251,24 @@ extern "C" #define EXTERN extern #endif -/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base addresses */ +/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base + * addresses + */ EXTERN const uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS]; -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_gpioirq_initialize * * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_GPIO_IRQ void imxrt_gpioirq_initialize(void); @@ -273,43 +276,43 @@ void imxrt_gpioirq_initialize(void); # define imxrt_gpioirq_initialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_config_gpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int imxrt_config_gpio(gpio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_gpio_write * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void imxrt_gpio_write(gpio_pinset_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_gpio_read * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool imxrt_gpio_read(gpio_pinset_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_gpioirq_configure * * Description: * Configure an interrupt for the specified GPIO pin. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_GPIO_IRQ int imxrt_gpioirq_configure(gpio_pinset_t pinset); @@ -317,13 +320,13 @@ int imxrt_gpioirq_configure(gpio_pinset_t pinset); # define imxrt_gpioirq_configure(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_gpioirq_enable * * Description: * Enable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_GPIO_IRQ int imxrt_gpioirq_enable(int irq); @@ -331,13 +334,13 @@ int imxrt_gpioirq_enable(int irq); # define imxrt_gpioirq_enable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_gpioirq_disable * * Description: * Disable the interrupt for specified GPIO IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_GPIO_IRQ int imxrt_gpioirq_disable(int irq); @@ -345,13 +348,14 @@ int imxrt_gpioirq_disable(int irq); # define imxrt_gpioirq_disable(irq) #endif -/************************************************************************************ +/**************************************************************************** * Function: imxrt_dump_gpio * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO int imxrt_dump_gpio(uint32_t pinset, const char *msg); diff --git a/arch/arm/src/imxrt/imxrt_hprtc.c b/arch/arm/src/imxrt/imxrt_hprtc.c index c35539e5ec4..0e0c4e5a0c4 100644 --- a/arch/arm/src/imxrt/imxrt_hprtc.c +++ b/arch/arm/src/imxrt/imxrt_hprtc.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_hprtc.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -46,9 +46,9 @@ #ifdef CONFIG_IMXRT_SNVS_HPRTC -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ /* Callback to use when the alarm expires */ @@ -56,9 +56,9 @@ static hprtc_alarm_callback_t g_hprtc_alarmcb; #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /* Variable determines the state of the RTC module. * @@ -73,11 +73,11 @@ volatile bool g_rtc_enabled; bool g_hprtc_timset; /* True: time has been set since power up */ #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_snvs_interrupt * * Description: @@ -90,7 +90,7 @@ bool g_hprtc_timset; /* True: time has been set since power up */ * Returned Value: * Zero (OK) on success; A negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) static int imxrt_snvs_interrupt(int irq, void *context, FAR void *arg) @@ -106,7 +106,9 @@ static int imxrt_snvs_interrupt(int irq, void *context, FAR void *arg) cb = g_hprtc_alarmcb; g_hprtc_alarmcb = NULL; - /* Disable the alarm, alarm interrupts, clear pending alarm interrupt status */ + /* Disable the alarm, alarm interrupts, clear pending alarm interrupt + * status + */ imxrt_hprtc_alarmdisable(); @@ -117,7 +119,7 @@ static int imxrt_snvs_interrupt(int irq, void *context, FAR void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_enable * * Description: @@ -129,7 +131,7 @@ static int imxrt_snvs_interrupt(int irq, void *context, FAR void *arg) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void imxrt_hprtc_enable(void) { @@ -146,12 +148,12 @@ static void imxrt_hprtc_enable(void) } } -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_alarmenable * * Description: - * Enable alarm interrupts. This is currently only used internally at the time - * that alarm interrupts are enabled. + * Enable alarm interrupts. This is currently only used internally at the + * time that alarm interrupts are enabled. * * Input Parameters: * None @@ -159,7 +161,7 @@ static void imxrt_hprtc_enable(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) static void imxrt_hprtc_alarmenable(void) @@ -178,25 +180,25 @@ static void imxrt_hprtc_alarmenable(void) } #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Functions used only for HPRTC - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_IMXRT_SNVS_LPSRTC -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_time * * Description: * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution RTC/counter - * hardware implementation selected. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC is set but neither - * CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC + * is set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. * * Input Parameters: * None @@ -204,7 +206,7 @@ static void imxrt_hprtc_alarmenable(void) * Returned Value: * The current time in seconds * - ************************************************************************************/ + ****************************************************************************/ time_t up_rtc_time(void) { @@ -213,12 +215,12 @@ time_t up_rtc_time(void) return imxrt_hprtc_time(); } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_settime * * Description: - * Set the RTC to the provided time. All RTC implementations must be able to - * set their time based on a standard timespec. + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. * * Input Parameters: * tp - the time to use @@ -226,7 +228,7 @@ time_t up_rtc_time(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_settime(FAR const struct timespec *ts) { @@ -268,16 +270,16 @@ int up_rtc_settime(FAR const struct timespec *ts) #endif /* !CONFIG_IMXRT_SNVS_LPSRTC */ -/************************************************************************************ +/**************************************************************************** * Logic Common to LPSRTC and HPRTC - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_initialize * * Description: - * Initialize the hardware RTC per the selected configuration. This function is - * called once during the OS initialization sequence + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence * * Input Parameters: * None @@ -285,7 +287,7 @@ int up_rtc_settime(FAR const struct timespec *ts) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_initialize(void) { @@ -331,12 +333,12 @@ int up_rtc_initialize(void) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_initialize * * Description: - * Initialize the LPSRTC per the selected configuration. This function is called - * via up_rtc_initialize (see imxrt_hprtc.c). + * Initialize the LPSRTC per the selected configuration. This function + * is called via up_rtc_initialize (see imxrt_hprtc.c). * * Input Parameters: * None @@ -344,7 +346,7 @@ int up_rtc_initialize(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int imxrt_hprtc_initialize(void) { @@ -379,7 +381,7 @@ int imxrt_hprtc_initialize(void) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_synchronize * * Description: @@ -391,7 +393,7 @@ int imxrt_hprtc_initialize(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_SNVS_LPSRTC void imxrt_hprtc_synchronize(void) @@ -399,8 +401,8 @@ void imxrt_hprtc_synchronize(void) uint32_t regval; uint32_t hpcr; - /* Make sure that the RTC is disabled (it should be at this point in the LPSRTC - * initialization sequence). + /* Make sure that the RTC is disabled (it should be at this point in the + * LPSRTC initialization sequence). */ hpcr = getreg32(IMXRT_SNVS_HPCR); @@ -424,13 +426,13 @@ void imxrt_hprtc_synchronize(void) } #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_time * * Description: - * Get the current time in seconds. This is the underlying implementation of the - * up_rtc_time() function that is used by the RTOS during initialization to set up - * the system time. + * Get the current time in seconds. This is the underlying implementation + * of the up_rtc_time() function that is used by the RTOS during + * initialization to set up the system time. * * Input Parameters: * None @@ -438,7 +440,7 @@ void imxrt_hprtc_synchronize(void) * Returned Value: * The current time in seconds * - ************************************************************************************/ + ****************************************************************************/ uint32_t imxrt_hprtc_time(void) { @@ -464,12 +466,12 @@ uint32_t imxrt_hprtc_time(void) return seconds; } -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_getalarm * * Description: - * Get the current alarm setting in seconds. This is only used by the lower half - * RTC driver. + * Get the current alarm setting in seconds. + * This is only used by the lower half RTC driver. * * Input Parameters: * None @@ -477,7 +479,7 @@ uint32_t imxrt_hprtc_time(void) * Returned Value: * The current alarm setting in seconds * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) uint32_t imxrt_hprtc_getalarm(void) @@ -493,12 +495,12 @@ uint32_t imxrt_hprtc_getalarm(void) } #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_setalarm * * Description: - * Set the alarm (in seconds) and enable alarm interrupts. This is only used by - * the lower half RTC driver. + * Set the alarm (in seconds) and enable alarm interrupts. + * This is only used by the lower half RTC driver. * * Input Parameters: * None @@ -506,7 +508,7 @@ uint32_t imxrt_hprtc_getalarm(void) * Returned Value: * The current alarm setting in seconds * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) int imxrt_hprtc_setalarm(FAR struct timespec *ts, hprtc_alarm_callback_t cb) @@ -568,13 +570,13 @@ int imxrt_hprtc_setalarm(FAR struct timespec *ts, hprtc_alarm_callback_t cb) } #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_alarmdisable * * Description: - * Disable alarm interrupts. Used internally after the receipt of the alarm - * interrupt. Also called by the lower-half RTC driver in order to cancel an - * alarm. + * Disable alarm interrupts. Used internally after the receipt of the + * alarm interrupt. Also called by the lower-half RTC driver in order to + * cancel an alarm. * * Input Parameters: * None @@ -582,7 +584,7 @@ int imxrt_hprtc_setalarm(FAR struct timespec *ts, hprtc_alarm_callback_t cb) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) void imxrt_hprtc_alarmdisable(void) diff --git a/arch/arm/src/imxrt/imxrt_hprtc.h b/arch/arm/src/imxrt/imxrt_hprtc.h index b92e5439c7d..3c6e21fa207 100644 --- a/arch/arm/src/imxrt/imxrt_hprtc.h +++ b/arch/arm/src/imxrt/imxrt_hprtc.h @@ -52,7 +52,7 @@ #endif /**************************************************************************** - * Private Types + * Public Types ****************************************************************************/ /* Callback type used by the HPRTC log to notify the RTC driver when the @@ -84,13 +84,13 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Functions used only for HPRTC - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Logic Common to LPSRTC and HPRTC - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: imxrt_rtc_lowerhalf @@ -119,12 +119,12 @@ struct rtc_lowerhalf_s; FAR struct rtc_lowerhalf_s *imxrt_rtc_lowerhalf(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_initialize * * Description: - * Initialize the LPSRTC per the selected configuration. This function is called - * via up_rtc_initialize (see imxrt_hprtc.c). + * Initialize the LPSRTC per the selected configuration. + * This function is called via up_rtc_initialize (see imxrt_hprtc.c). * * Input Parameters: * None @@ -132,11 +132,11 @@ FAR struct rtc_lowerhalf_s *imxrt_rtc_lowerhalf(void); * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int imxrt_hprtc_initialize(void); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_synchronize * * Description: @@ -148,19 +148,19 @@ int imxrt_hprtc_initialize(void); * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_SNVS_LPSRTC void imxrt_hprtc_synchronize(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_time * * Description: - * Get the current time in seconds. This is the underlying implementation of the - * up_rtc_tim() function that is used by the RTOS during initialization to set up - * the system time. + * Get the current time in seconds. + * This is the underlying implementation of the up_rtc_tim() function that + * is used by the RTOS during initialization to set up the system time. * * Input Parameters: * None @@ -168,16 +168,16 @@ void imxrt_hprtc_synchronize(void); * Returned Value: * The current time in seconds * - ************************************************************************************/ + ****************************************************************************/ uint32_t imxrt_hprtc_time(void); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_getalarm * * Description: - * Get the current alarm setting in seconds. This is only used by the lower half - * RTC driver. + * Get the current alarm setting in seconds. + * This is only used by the lower half RTC driver. * * Input Parameters: * None @@ -185,18 +185,18 @@ uint32_t imxrt_hprtc_time(void); * Returned Value: * The current alarm setting in seconds * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) uint32_t imxrt_hprtc_getalarm(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_setalarm * * Description: - * Set the alarm (in seconds) and enable alarm interrupts. This is only used by - * the lower half RTC driver. + * Set the alarm (in seconds) and enable alarm interrupts. + * This is only used by the lower half RTC driver. * * Input Parameters: * sec - The new alarm setting @@ -204,19 +204,20 @@ uint32_t imxrt_hprtc_getalarm(void); * Returned Value: * The current alarm setting in seconds * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) -int imxrt_hprtc_setalarm(FAR struct timespec *ts, hprtc_alarm_callback_t cb); +int imxrt_hprtc_setalarm(FAR struct timespec *ts, + hprtc_alarm_callback_t cb); #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_hprtc_alarmdisable * * Description: - * Disable alarm interrupts. Used internally after the receipt of the alarm - * interrupt. Also called by the lower-half RTC driver in order to cancel an - * alarm. + * Disable alarm interrupts. + * Used internally after the receipt of the alarm interrupt. + * Also called by the lower-half RTC driver in order to cancel an alarm. * * Input Parameters: * None @@ -224,7 +225,7 @@ int imxrt_hprtc_setalarm(FAR struct timespec *ts, hprtc_alarm_callback_t cb); * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) void imxrt_hprtc_alarmdisable(void); diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.c b/arch/arm/src/imxrt/imxrt_iomuxc.c index c679cf55c39..2cbc9df897e 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc.c +++ b/arch/arm/src/imxrt/imxrt_iomuxc.c @@ -54,7 +54,9 @@ #if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x)) static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] = { - /* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */ + /* The first mappings are simple 1-to-1 mappings. + * This may be a little wasteful + */ IMXRT_PADCTL_GPIO_EMC_00_INDEX, IMXRT_PADCTL_GPIO_EMC_01_INDEX, @@ -187,7 +189,9 @@ static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] = #elif defined(CONFIG_ARCH_FAMILY_IMXRT102x) static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] = { - /* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */ + /* The first mappings are simple 1-to-1 mappings. + * This may be a little wasteful + */ IMXRT_PADCTL_GPIO_EMC_00_INDEX, IMXRT_PADCTL_GPIO_EMC_01_INDEX, diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.h b/arch/arm/src/imxrt/imxrt_iomuxc.h index 6f6f4d92e10..be073d74a94 100644 --- a/arch/arm/src/imxrt/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/imxrt_iomuxc.h @@ -122,7 +122,7 @@ * Public Types ****************************************************************************/ - /* The smallest integer type that can hold the IOMUX encoding */ +/* The smallest integer type that can hold the IOMUX encoding */ typedef uint16_t iomux_pinset_t; diff --git a/arch/arm/src/imxrt/imxrt_irq.h b/arch/arm/src/imxrt/imxrt_irq.h index dd61f16d1db..b241ce17f94 100644 --- a/arch/arm/src/imxrt/imxrt_irq.h +++ b/arch/arm/src/imxrt/imxrt_irq.h @@ -28,7 +28,7 @@ #include /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/imxrt/imxrt_lcd.h b/arch/arm/src/imxrt/imxrt_lcd.h index 874be997910..d3f7aaecf4f 100644 --- a/arch/arm/src/imxrt/imxrt_lcd.h +++ b/arch/arm/src/imxrt/imxrt_lcd.h @@ -172,7 +172,7 @@ #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index 37ecd289da5..ea8039cb071 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/imxrt/imxrt_lpspi.c * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,9 +32,9 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * The external functions, imxrt_lpspi1/2/3/4select and * imxrt_lpspi1/2/3/4status must be provided by board-specific logic. * They are implementations of the select and status methods of the SPI @@ -43,24 +43,24 @@ * imxrt_lpspibus_initialize()) are provided by common IMXRT logic. * To use this common SPI logic on your board: * - * 1. Provide logic in imxrt_boardinitialize() to configure SPI chip select - * pins. + * 1. Provide logic in imxrt_boardinitialize() to configure SPI chip + * select pins. * 2. Provide imxrt_lpspi1/2/3/4select() and imxrt_lpspi1/2/3/4status() - * functions in your board-specific logic. These functions will perform - * chip selection and status operations using GPIOs in the way your board - * is configured. + * functions in your board-specific logic. These functions will + * perform chip selection and status operations using GPIOs in the way + * your board is configured. * 3. Add a calls to imxrt_lpspibus_initialize() in your low level * application initialization logic - * 4. The handle returned by imxrt_lpspibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_lpspislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). + * 4. The handle returned by imxrt_lpspibus_initialize() may then be + * used to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_lpspislotinitialize(), for example, will bind the SPI + * driver to the SPI MMC/SD driver). * - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include @@ -95,11 +95,11 @@ #if defined(CONFIG_IMXRT_LPSPI1) || defined(CONFIG_IMXRT_LPSPI2) || \ defined(CONFIG_IMXRT_LPSPI3) || defined(CONFIG_IMXRT_LPSPI4) -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/* Configuration *************************************************************/ +/* Configuration ************************************************************/ /* SPI interrupts */ @@ -117,9 +117,9 @@ # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif -/***************************************************************************** +/**************************************************************************** * Private Types - *****************************************************************************/ + ****************************************************************************/ struct imxrt_lpspidev_s { @@ -142,14 +142,15 @@ enum imxrt_delay_e LPSPI_BETWEEN_TRANSFER /* Delay between transfers. */ }; -/***************************************************************************** +/**************************************************************************** * Private Function Prototypes - *****************************************************************************/ + ****************************************************************************/ /* Helpers */ -static inline uint32_t imxrt_lpspi_getreg32(FAR struct imxrt_lpspidev_s *priv, - uint8_t offset); +static inline uint32_t +imxrt_lpspi_getreg32(FAR struct imxrt_lpspidev_s *priv, + uint8_t offset); static inline void imxrt_lpspi_putreg32(FAR struct imxrt_lpspidev_s *priv, uint8_t offset, uint32_t value); static inline uint32_t imxrt_lpspi_readword( @@ -180,7 +181,8 @@ static int imxrt_lpspi_hwfeatures(FAR struct spi_dev_s *dev, #endif static uint32_t imxrt_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd); static void imxrt_lpspi_exchange(FAR struct spi_dev_s *dev, - FAR const void *txbuffer, FAR void *rxbuffer, + FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords); #ifndef CONFIG_SPI_EXCHANGE static void imxrt_lpspi_sndblock(FAR struct spi_dev_s *dev, @@ -194,9 +196,9 @@ static void imxrt_lpspi_recvblock(FAR struct spi_dev_s *dev, static void imxrt_lpspi_bus_initialize(FAR struct imxrt_lpspidev_s *priv); -/***************************************************************************** +/**************************************************************************** * Private Data - *****************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_LPSPI1 static const struct spi_ops_s g_spi1ops = @@ -382,11 +384,11 @@ static struct imxrt_lpspidev_s g_lpspi4dev = }; #endif -/***************************************************************************** +/**************************************************************************** * Private Functions - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_getreg8 * * Description: @@ -399,7 +401,7 @@ static struct imxrt_lpspidev_s g_lpspi4dev = * Returned Value: * The contents of the 8-bit register * - *****************************************************************************/ + ****************************************************************************/ static inline uint8_t imxrt_lpspi_getreg8(FAR struct imxrt_lpspidev_s *priv, uint8_t offset) @@ -407,7 +409,7 @@ static inline uint8_t imxrt_lpspi_getreg8(FAR struct imxrt_lpspidev_s *priv, return getreg8(priv->spibase + offset); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_putreg8 * * Description: @@ -418,7 +420,7 @@ static inline uint8_t imxrt_lpspi_getreg8(FAR struct imxrt_lpspidev_s *priv, * offset - offset to the register of interest * value - the 8-bit value to be written * - *****************************************************************************/ + ****************************************************************************/ static inline void imxrt_lpspi_putreg8(FAR struct imxrt_lpspidev_s *priv, uint8_t offset, uint8_t value) @@ -426,7 +428,7 @@ static inline void imxrt_lpspi_putreg8(FAR struct imxrt_lpspidev_s *priv, putreg8(value, priv->spibase + offset); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_getreg * * Description: @@ -439,15 +441,16 @@ static inline void imxrt_lpspi_putreg8(FAR struct imxrt_lpspidev_s *priv, * Returned Value: * The contents of the 32-bit register * - *****************************************************************************/ + ****************************************************************************/ -static inline uint32_t imxrt_lpspi_getreg32(FAR struct imxrt_lpspidev_s *priv, - uint8_t offset) +static inline uint32_t +imxrt_lpspi_getreg32(FAR struct imxrt_lpspidev_s *priv, + uint8_t offset) { return getreg32(priv->spibase + offset); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_putreg * * Description: @@ -461,7 +464,7 @@ static inline uint32_t imxrt_lpspi_getreg32(FAR struct imxrt_lpspidev_s *priv, * Returned Value: * The contents of the 32-bit register * - *****************************************************************************/ + ****************************************************************************/ static inline void imxrt_lpspi_putreg32(FAR struct imxrt_lpspidev_s *priv, uint8_t offset, uint32_t value) @@ -469,7 +472,7 @@ static inline void imxrt_lpspi_putreg32(FAR struct imxrt_lpspidev_s *priv, putreg32(value, priv->spibase + offset); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_readword * * Description: @@ -481,9 +484,10 @@ static inline void imxrt_lpspi_putreg32(FAR struct imxrt_lpspidev_s *priv, * Returned Value: * word as read * - *****************************************************************************/ + ****************************************************************************/ -static inline uint32_t imxrt_lpspi_readword(FAR struct imxrt_lpspidev_s *priv) +static inline uint32_t +imxrt_lpspi_readword(FAR struct imxrt_lpspidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -495,7 +499,7 @@ static inline uint32_t imxrt_lpspi_readword(FAR struct imxrt_lpspidev_s *priv) return imxrt_lpspi_getreg32(priv, IMXRT_LPSPI_RDR_OFFSET); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_writeword * * Description: @@ -508,7 +512,7 @@ static inline uint32_t imxrt_lpspi_readword(FAR struct imxrt_lpspidev_s *priv) * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static inline void imxrt_lpspi_writeword(FAR struct imxrt_lpspidev_s *priv, uint16_t word) @@ -523,7 +527,7 @@ static inline void imxrt_lpspi_writeword(FAR struct imxrt_lpspidev_s *priv, imxrt_lpspi_putreg32(priv, IMXRT_LPSPI_TDR_OFFSET, word); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_readbyte * * Description: @@ -535,7 +539,7 @@ static inline void imxrt_lpspi_writeword(FAR struct imxrt_lpspidev_s *priv, * Returned Value: * Byte as read * - *****************************************************************************/ + ****************************************************************************/ static inline uint8_t imxrt_lpspi_readbyte(FAR struct imxrt_lpspidev_s *priv) { @@ -549,7 +553,7 @@ static inline uint8_t imxrt_lpspi_readbyte(FAR struct imxrt_lpspidev_s *priv) return imxrt_lpspi_getreg8(priv, IMXRT_LPSPI_RDR_OFFSET); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_writebyte * * Description: @@ -562,7 +566,7 @@ static inline uint8_t imxrt_lpspi_readbyte(FAR struct imxrt_lpspidev_s *priv) * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static inline void imxrt_lpspi_writebyte(FAR struct imxrt_lpspidev_s *priv, uint8_t byte) @@ -577,7 +581,7 @@ static inline void imxrt_lpspi_writebyte(FAR struct imxrt_lpspidev_s *priv, imxrt_lpspi_putreg8(priv, IMXRT_LPSPI_TDR_OFFSET, byte); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_9to16bitmode * * Description: @@ -589,9 +593,10 @@ static inline void imxrt_lpspi_writebyte(FAR struct imxrt_lpspidev_s *priv, * Returned Value: * true: >8 bit mode-bit mode, false: <= 8-bit mode * - *****************************************************************************/ + ****************************************************************************/ -static inline bool imxrt_lpspi_9to16bitmode(FAR struct imxrt_lpspidev_s *priv) +static inline bool +imxrt_lpspi_9to16bitmode(FAR struct imxrt_lpspidev_s *priv) { bool ret; @@ -608,7 +613,7 @@ static inline bool imxrt_lpspi_9to16bitmode(FAR struct imxrt_lpspidev_s *priv) return ret; } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_modifyreg * * Description: @@ -623,7 +628,7 @@ static inline bool imxrt_lpspi_9to16bitmode(FAR struct imxrt_lpspidev_s *priv) * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static void imxrt_lpspi_modifyreg32(FAR struct imxrt_lpspidev_s *priv, uint8_t offset, uint32_t clrbits, @@ -632,7 +637,7 @@ static void imxrt_lpspi_modifyreg32(FAR struct imxrt_lpspidev_s *priv, modifyreg32(priv->spibase + offset, clrbits, setbits); } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_master_set_delays * * Description: @@ -646,7 +651,7 @@ static void imxrt_lpspi_modifyreg32(FAR struct imxrt_lpspidev_s *priv, * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static inline void imxrt_lpspi_master_set_delay_scaler( FAR struct imxrt_lpspidev_s *priv, @@ -678,7 +683,7 @@ static inline void imxrt_lpspi_master_set_delay_scaler( } } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_master_set_delays * * Description: @@ -692,7 +697,7 @@ static inline void imxrt_lpspi_master_set_delay_scaler( * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static inline void imxrt_lpspi_master_set_delays( FAR struct imxrt_lpspidev_s *priv, @@ -749,10 +754,10 @@ static inline void imxrt_lpspi_master_set_delays( if (type == LPSPI_BETWEEN_TRANSFER) { - /* First calculate the initial, default delay, note min delay is 2 clock - * cycles. Due to large size of * calculated values (uint64_t), we need - * to break up the calculation into several steps to ensure * accurate - * calculated results + /* First calculate the initial, default delay, note min delay is 2 + * clock cycles. Due to large size of * calculated values (uint64_t), + * we need to break up the calculation into several steps to ensure + * accurate calculated results */ initial_delay_ns = 1000000000U; @@ -818,9 +823,9 @@ static inline void imxrt_lpspi_master_set_delays( real_delay *= (scaler + 1 + additional_scaler); real_delay /= clock_div_prescaler; - /* calculate the delay difference based on the conditional statement - * that states that the calculated delay must not be less then the - * desired delay + /* calculate the delay difference based on the conditional + * statement that states that the calculated delay must not be + * less then the desired delay */ if (real_delay >= delay_ns) @@ -841,7 +846,7 @@ static inline void imxrt_lpspi_master_set_delays( } } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_lock * * Description: @@ -860,7 +865,7 @@ static inline void imxrt_lpspi_master_set_delays( * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static int imxrt_lpspi_lock(FAR struct spi_dev_s *dev, bool lock) { @@ -879,7 +884,7 @@ static int imxrt_lpspi_lock(FAR struct spi_dev_s *dev, bool lock) return ret; } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_setfrequency * * Description: @@ -892,7 +897,7 @@ static int imxrt_lpspi_lock(FAR struct spi_dev_s *dev, bool lock) * Returned Value: * Returns the actual frequency selected * - *****************************************************************************/ + ****************************************************************************/ static uint32_t imxrt_lpspi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) @@ -938,8 +943,8 @@ static uint32_t imxrt_lpspi_setfrequency(FAR struct spi_dev_s *dev, pll_freq = BOARD_XTAL_FREQUENCY * pll3_div; /* Assumption this formula will work only if the LPSPI Clock Source is - * PLL3 PFD0 * so check if LPSPI clock source is set to 1 (PLL3 PFD0) in - * CCM_CBCMR register bits 4-5 + * PLL3 PFD0 * so check if LPSPI clock source is set to 1 (PLL3 PFD0) + * in CCM_CBCMR register bits 4-5 */ src_freq = pll_freq / @@ -1016,7 +1021,7 @@ static uint32_t imxrt_lpspi_setfrequency(FAR struct spi_dev_s *dev, return priv->actual; } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_setmode * * Description: @@ -1029,7 +1034,7 @@ static uint32_t imxrt_lpspi_setfrequency(FAR struct spi_dev_s *dev, * Returned Value: * Returns the actual frequency selected * - *****************************************************************************/ + ****************************************************************************/ static void imxrt_lpspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) @@ -1080,7 +1085,8 @@ static void imxrt_lpspi_setmode(FAR struct spi_dev_s *dev, return; } - imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET, clrbits, setbits); + imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET, + clrbits, setbits); while ((imxrt_lpspi_getreg32(priv, IMXRT_LPSPI_RSR_OFFSET) & LPSPI_RSR_RXEMPTY) != LPSPI_RSR_RXEMPTY) @@ -1104,7 +1110,7 @@ static void imxrt_lpspi_setmode(FAR struct spi_dev_s *dev, } } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_setbits * * Description: @@ -1117,7 +1123,7 @@ static void imxrt_lpspi_setmode(FAR struct spi_dev_s *dev, * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static void imxrt_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) { @@ -1164,7 +1170,7 @@ static void imxrt_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) } } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_hwfeatures * * Description: @@ -1178,7 +1184,7 @@ static void imxrt_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) * Zero (OK) if the selected H/W features are enabled; A negated errno * value if any H/W feature is not supportable. * - *****************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SPI_HWFEATURES static int imxrt_lpspi_hwfeatures(FAR struct spi_dev_s *dev, @@ -1215,7 +1221,7 @@ static int imxrt_lpspi_hwfeatures(FAR struct spi_dev_s *dev, } #endif -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_send * * Description: @@ -1229,7 +1235,7 @@ static int imxrt_lpspi_hwfeatures(FAR struct spi_dev_s *dev, * Returned Value: * response * - *****************************************************************************/ + ****************************************************************************/ static uint32_t imxrt_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) { @@ -1241,8 +1247,8 @@ static uint32_t imxrt_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) imxrt_lpspi_writeword(priv, wd); - while ((imxrt_lpspi_getreg32(priv, IMXRT_LPSPI_SR_OFFSET) & LPSPI_SR_RDF) != - LPSPI_SR_RDF); + while ((imxrt_lpspi_getreg32(priv, IMXRT_LPSPI_SR_OFFSET) & + LPSPI_SR_RDF) != LPSPI_SR_RDF); ret = imxrt_lpspi_readword(priv); @@ -1252,14 +1258,15 @@ static uint32_t imxrt_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) regval = imxrt_lpspi_getreg32(priv, IMXRT_LPSPI_SR_OFFSET); - spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 "\n", + spiinfo( + "Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 "\n", wd, ret, regval); UNUSED(regval); return ret; } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_exchange (no DMA). aka imxrt_lpspi_exchange_nodma * * Description: @@ -1278,12 +1285,13 @@ static uint32_t imxrt_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ #if !defined(CONFIG_IMXRT_LPSPI_DMA) || defined(CONFIG_IMXRT_DMACAPABLE) #if !defined(CONFIG_IMXRT_LPSPI_DMA) static void imxrt_lpspi_exchange(FAR struct spi_dev_s *dev, - FAR const void *txbuffer, FAR void *rxbuffer, + FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) #else static void imxrt_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, @@ -1367,7 +1375,7 @@ static void imxrt_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, } #endif /* !CONFIG_IMXRT_LPSPI_DMA || CONFIG_IMXRT_DMACAPABLE */ -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_sndblock * * Description: @@ -1376,16 +1384,16 @@ static void imxrt_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, * Input Parameters: * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's + * nwords - the length of data to send from the buffer in number of + * words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's * * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE static void imxrt_lpspi_sndblock(FAR struct spi_dev_s *dev, @@ -1396,7 +1404,7 @@ static void imxrt_lpspi_sndblock(FAR struct spi_dev_s *dev, } #endif -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_recvblock * * Description: @@ -1414,7 +1422,7 @@ static void imxrt_lpspi_sndblock(FAR struct spi_dev_s *dev, * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE static void imxrt_lpspi_recvblock(FAR struct spi_dev_s *dev, @@ -1425,13 +1433,13 @@ static void imxrt_lpspi_recvblock(FAR struct spi_dev_s *dev, } #endif -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_clock_enable * * Description: * Ungate LPSPI clock * - *****************************************************************************/ + ****************************************************************************/ void imxrt_lpspi_clock_enable(uint32_t base) { @@ -1453,13 +1461,13 @@ void imxrt_lpspi_clock_enable(uint32_t base) } } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_clock_disable * * Description: * Gate LPSPI clock * - *****************************************************************************/ + ****************************************************************************/ void imxrt_lpspi_clock_disable(uint32_t base) { @@ -1481,7 +1489,7 @@ void imxrt_lpspi_clock_disable(uint32_t base) } } -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspi_bus_initialize * * Description: @@ -1494,7 +1502,7 @@ void imxrt_lpspi_clock_disable(uint32_t base) * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static void imxrt_lpspi_bus_initialize(struct imxrt_lpspidev_s *priv) { @@ -1552,11 +1560,11 @@ static void imxrt_lpspi_bus_initialize(struct imxrt_lpspidev_s *priv) imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); } -/***************************************************************************** +/**************************************************************************** * Public Functions - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: imxrt_lpspibus_initialize * * Description: @@ -1568,7 +1576,7 @@ static void imxrt_lpspi_bus_initialize(struct imxrt_lpspidev_s *priv) * Returned Value: * Valid SPI device structure reference on success; a NULL on failure * - *****************************************************************************/ + ****************************************************************************/ FAR struct spi_dev_s *imxrt_lpspibus_initialize(int bus) { diff --git a/arch/arm/src/imxrt/imxrt_lpspi.h b/arch/arm/src/imxrt/imxrt_lpspi.h index 6b3d20ecb64..87b7ae787ac 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.h +++ b/arch/arm/src/imxrt/imxrt_lpspi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_lpspi.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_LPSPI_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_LPSPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -49,9 +49,9 @@ #include "chip.h" #include "hardware/imxrt_lpspi.h" -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -66,7 +66,7 @@ extern "C" struct spi_dev_s; /* Forward reference */ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_lpspibus_initialize * * Description: @@ -78,72 +78,82 @@ struct spi_dev_s; /* Forward reference */ * Returned Value: * Valid SPI device structure reference on success; a NULL on failure * - ************************************************************************************/ + ****************************************************************************/ FAR struct spi_dev_s *imxrt_lpspibus_initialize(int bus); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_lpspi1/2/...select and imxrt_lpspi1/2/...status * * Description: - * The external functions, imxrt_lpspi1/2/...select, imxrt_lpspi1/2/...status, and - * imxrt_lpspi1/2/...cmddata must be provided by board-specific logic. These are - * implementations of the select, status, and cmddata methods of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including imxrt_lpspibus_initialize()) are provided by common IMXRT logic. To use this - * common SPI logic on your board: + * The external functions, imxrt_lpspi1/2/...select, + * imxrt_lpspi1/2/...status, and imxrt_lpspi1/2/...cmddata must be + * provided by board-specific logic. These are implementations of the + * select, status, and cmddata methods of the SPI interface defined by + * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including imxrt_lpspibus_initialize()) are provided by common IMXRT + * logic. To use this common SPI logic on your board: * * 1. Provide logic in imxrt_boardinitialize() to configure SPI chip select * pins. - * 2. Provide imxrt_lpspi1/2/...select() and imxrt_lpspi1/2/...status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then - * provide imxrt_lpspi1/2/...cmddata() functions in your board-specific logic. - * These functions will perform cmd/data selection operations using GPIOs in the - * way your board is configured. - * 4. Add a calls to imxrt_lpspibus_initialize() in your low level application - * initialization logic - * 5. The handle returned by imxrt_lpspibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide imxrt_lpspi1/2/...select() and imxrt_lpspi1/2/...status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, + * then provide imxrt_lpspi1/2/...cmddata() functions in your + * board-specific logic. These functions will perform cmd/data selection + * operations using GPIOs in the way your board is configured. + * 4. Add a calls to imxrt_lpspibus_initialize() in your low level + * application initialization logic + * 5. The handle returned by imxrt_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_IMXRT_LPSPI1 -void imxrt_lpspi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imxrt_lpspi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imxrt_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid); -int imxrt_lpspi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int imxrt_lpspi1cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd); #endif #ifdef CONFIG_IMXRT_LPSPI2 -void imxrt_lpspi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imxrt_lpspi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imxrt_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid); -int imxrt_lpspi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int imxrt_lpspi2cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd); #endif #ifdef CONFIG_IMXRT_LPSPI3 -void imxrt_lpspi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imxrt_lpspi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imxrt_lpspi3status(FAR struct spi_dev_s *dev, uint32_t devid); -int imxrt_lpspi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int imxrt_lpspi3cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd); #endif #ifdef CONFIG_IMXRT_LPSPI4 -void imxrt_lpspi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void imxrt_lpspi4select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t imxrt_lpspi4status(FAR struct spi_dev_s *dev, uint32_t devid); -int imxrt_lpspi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int imxrt_lpspi4cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd); #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_lpspi1/2/...register * * Description: - * If the board supports a card detect callback to inform the SPI-based MMC/SD - * driver when an SD card is inserted or removed, then CONFIG_SPI_CALLBACK should - * be defined and the following function(s) must be implemented. These functions - * implements the registercallback method of the SPI interface (see - * include/nuttx/spi/spi.h for details) + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD driver when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function(s) + * must be implemented. These functions implements the registercallback + * method of the SPI interface (see include/nuttx/spi/spi.h for details) * * Input Parameters: * dev - Device-specific state data @@ -157,23 +167,27 @@ int imxrt_lpspi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_IMXRT_LPSPI1 -int imxrt_lpspi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); +int imxrt_lpspi1register(FAR struct spi_dev_s *dev, + spi_mediachange_t callback, + FAR void *arg); #endif #ifdef CONFIG_IMXRT_LPSPI2 -int imxrt_lpspi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); +int imxrt_lpspi2register(FAR struct spi_dev_s *dev, + spi_mediachange_t callback, + FAR void *arg); #endif #ifdef CONFIG_IMXRT_LPSPI3 -int imxrt_lpspi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); +int imxrt_lpspi3register(FAR struct spi_dev_s *dev, + spi_mediachange_t callback, + FAR void *arg); #endif #ifdef CONFIG_IMXRT_LPSPI4 -int imxrt_lpspi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); +int imxrt_lpspi4register(FAR struct spi_dev_s *dev, + spi_mediachange_t callback, + FAR void *arg); #endif #endif diff --git a/arch/arm/src/imxrt/imxrt_lpsrtc.c b/arch/arm/src/imxrt/imxrt_lpsrtc.c index 4970fc43e20..1253ee4704c 100644 --- a/arch/arm/src/imxrt/imxrt_lpsrtc.c +++ b/arch/arm/src/imxrt/imxrt_lpsrtc.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_lpsrtc.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -46,11 +46,11 @@ #ifdef CONFIG_IMXRT_SNVS_LPSRTC -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_lpsrtc_enable * * Description: @@ -62,7 +62,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void imxrt_lpsrtc_enable(void) { @@ -79,20 +79,20 @@ static void imxrt_lpsrtc_enable(void) } } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_lpsrtc_initialize * * Description: - * Initialize the LPSRTC per the selected configuration. This function is called - * via up_rtc_initialize (see imxrt_hprtc.c). + * Initialize the LPSRTC per the selected configuration. + * This function is called via up_rtc_initialize (see imxrt_hprtc.c). * - * NOTE that the LPSRTC is always configured synchronized with the HPRTC. This - * means that the time is set via the LPSRTC but read via the HPRTC. Also, only - * the alarms from the HPRTC are used. + * NOTE that the LPSRTC is always configured synchronized with the HPRTC. + * This means that the time is set via the LPSRTC but read via the HPRTC. + * Also, only the alarms from the HPRTC are used. * * Input Parameters: * None @@ -100,7 +100,7 @@ static void imxrt_lpsrtc_enable(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int imxrt_lpsrtc_initialize(void) { @@ -142,15 +142,15 @@ int imxrt_lpsrtc_initialize(void) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_time * * Description: * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution RTC/counter - * hardware implementation selected. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC is set but neither - * CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. * * Input Parameters: * None @@ -158,7 +158,7 @@ int imxrt_lpsrtc_initialize(void) * Returned Value: * The current time in seconds * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_RTC_HIRES time_t up_rtc_time(void) @@ -169,12 +169,12 @@ time_t up_rtc_time(void) } #endif -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_settime * * Description: - * Set the RTC to the provided time. All RTC implementations must be able to - * set their time based on a standard timespec. + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. * * Input Parameters: * tp - the time to use @@ -182,7 +182,7 @@ time_t up_rtc_time(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_settime(FAR const struct timespec *ts) { diff --git a/arch/arm/src/imxrt/imxrt_lpsrtc.h b/arch/arm/src/imxrt/imxrt_lpsrtc.h index 92483d1b81c..33afc6fe678 100644 --- a/arch/arm/src/imxrt/imxrt_lpsrtc.h +++ b/arch/arm/src/imxrt/imxrt_lpsrtc.h @@ -66,16 +66,16 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_lpsrtc_initialize * * Description: - * Initialize the LPSRTC per the selected configuration. This function is called - * via up_rtc_initialize (see imxrt_hprtc.c). + * Initialize the LPSRTC per the selected configuration. + * This function is called via up_rtc_initialize (see imxrt_hprtc.c). * - * NOTE that the LPSRTC is always configured synchronized with the HPRTC. This - * means that the time is set via the LPSRTC but read via the HPRTC. Also, only - * the alarms from the HPRTC are used. + * NOTE that the LPSRTC is always configured synchronized with the HPRTC. + * This means that the time is set via the LPSRTC but read via the HPRTC. + * Also, only the alarms from the HPRTC are used. * * Input Parameters: * None @@ -83,7 +83,7 @@ extern "C" * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int imxrt_lpsrtc_initialize(void); diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c index 84566978f3b..a0ed6155a4e 100644 --- a/arch/arm/src/imxrt/imxrt_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -102,84 +102,84 @@ void imxrt_mpu_initialize(void) mpu_user_intsram(datastart, dataend - datastart); #else mpu_configure_region(0xc0000000, 512 * 1024 * 1024, - MPU_RASR_TEX_DEV | /* Device */ - /* Not Cacheable */ - /* Not Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_TEX_DEV | /* Device + * Not Cacheable + * Not Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_configure_region(IMXRT_EXTMEM_BASE, 1024 * 1024 * 1024, - MPU_RASR_TEX_DEV | /* Device */ - /* Not Cacheable */ - /* Not Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_TEX_DEV | /* Device + * Not Cacheable + * Not Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_configure_region(IMXRT_FLEXCIPHER_BASE, 8 * 1024 * 1024, MPU_RASR_TEX_SO | /* Ordered */ MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RORO /* P:RO U:RO */ - /* Instruction access */); + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RORO); /* P:RO U:RO + * Instruction access */ mpu_configure_region(0x00000000, 1024 * 1024 * 1024, - MPU_RASR_TEX_DEV | /* Device */ - /* Not Cacheable */ - /* Not Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_TEX_DEV | /* Device + * Not Cacheable + * Not Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_configure_region(IMXRT_ITCM_BASE, 128 * 1024, MPU_RASR_TEX_SO | /* Ordered */ MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_configure_region(IMXRT_DTCM_BASE, 128 * 1024, MPU_RASR_TEX_SO | /* Ordered */ MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_configure_region(IMXRT_OCRAM2_BASE, 512 * 1024, MPU_RASR_TEX_SO | /* Ordered */ MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_configure_region(IMXRT_OCRAM_BASE, 512 * 1024, MPU_RASR_TEX_SO | /* Ordered */ MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_configure_region(IMXRT_EXTMEM_BASE, 32 * 1024 * 1024, MPU_RASR_TEX_SO | /* Ordered */ MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_configure_region(0x81e00000, 2 * 1024 * 1024, - MPU_RASR_TEX_NOR | /* Normal */ - /* Not Cacheable */ - /* Not Bufferable */ - /* Not Shareable */ - MPU_RASR_AP_RWRW /* P:RW U:RW */ - /* Instruction access */); + MPU_RASR_TEX_NOR | /* Normal + * Not Cacheable + * Not Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ mpu_control(true, true, true); return; diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.h b/arch/arm/src/imxrt/imxrt_mpuinit.h index 82155e50662..a1ba30d3f3d 100644 --- a/arch/arm/src/imxrt/imxrt_mpuinit.h +++ b/arch/arm/src/imxrt/imxrt_mpuinit.h @@ -57,8 +57,8 @@ extern "C" * Name: imxrt_mpu_initialize * * Description: - * Configure the MPU to permit user-space access to only unrestricted i.MXRT - * resources. + * Configure the MPU to permit user-space access to only unrestricted + * i.MXRT resources. * ****************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_periphclks.h b/arch/arm/src/imxrt/imxrt_periphclks.h index 133029a88f5..c0a7c7d151b 100644 --- a/arch/arm/src/imxrt/imxrt_periphclks.h +++ b/arch/arm/src/imxrt/imxrt_periphclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_periphclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,24 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_PERIPHCLKS_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_PERIPHCLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/imxrt_ccm.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Clock is off during all modes. Stop enter hardware handshake is disabled. */ +/* Clock is off during all modes. + * Stop enter hardware handshake is disabled. + */ #define imxrt_clockoff_acmp1() imxrt_periphclk_configure(CCM_CCGR_ACMP1, CCM_CG_OFF) #define imxrt_clockoff_acmp2() imxrt_periphclk_configure(CCM_CCGR_ACMP2, CCM_CG_OFF) @@ -375,7 +377,7 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Name: imxrt_periphclk_configure * * Description: @@ -390,7 +392,7 @@ extern "C" * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void imxrt_periphclk_configure(uintptr_t regaddr, unsigned int index, unsigned int value); diff --git a/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c b/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c index 8fe9f262d94..5e2a66b9bb2 100644 --- a/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c +++ b/arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c @@ -87,7 +87,7 @@ static bool imxrt_havesettime(FAR struct rtc_lowerhalf_s *lower); static int imxrt_setalarm(FAR struct rtc_lowerhalf_s *lower, FAR const struct lower_setalarm_s *alarminfo); static int imxrt_setrelative(FAR struct rtc_lowerhalf_s *lower, - FAR const struct lower_setrelative_s *alarminfo); + FAR const struct lower_setrelative_s *alarminfo); static int imxrt_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid); static int imxrt_rdalarm(FAR struct rtc_lowerhalf_s *lower, @@ -97,6 +97,7 @@ static int imxrt_rdalarm(FAR struct rtc_lowerhalf_s *lower, /**************************************************************************** * Private Data ****************************************************************************/ + /* i.MXRT RTC driver operations */ static const struct rtc_ops_s g_rtc_ops = @@ -374,6 +375,7 @@ static int imxrt_setrelative(FAR struct rtc_lowerhalf_s *lower, if (alarminfo->id == 0 && alarminfo->reltime > 0) { /* Get the current time in seconds */ + /* The resolution of time is only 1 second */ ts.tv_sec = up_rtc_time(); diff --git a/arch/arm/src/imxrt/imxrt_start.h b/arch/arm/src/imxrt/imxrt_start.h index 0d9967c8641..0882a0acc7f 100644 --- a/arch/arm/src/imxrt/imxrt_start.h +++ b/arch/arm/src/imxrt/imxrt_start.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_START_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_START_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,23 +35,23 @@ #include "arm_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -62,43 +62,44 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: imxrt_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. * - ************************************************************************************/ + ****************************************************************************/ void imxrt_lowsetup(void); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_boardinitialize * * Description: - * All i.MXRT architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * All i.MXRT architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. * - ************************************************************************************/ + ****************************************************************************/ void imxrt_boardinitialize(void); -/************************************************************************************ +/**************************************************************************** * Name: imxrt_ocram_initialize * * Description: * Called off reset vector to reconfigure the flexRAM * and finish the FLASH to RAM Copy. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_BOOT_RUNFROMISRAM void imxrt_ocram_initialize(void); diff --git a/arch/arm/src/imxrt/imxrt_timerisr.c b/arch/arm/src/imxrt/imxrt_timerisr.c index c3e9d30932a..7ea757dc4c4 100644 --- a/arch/arm/src/imxrt/imxrt_timerisr.c +++ b/arch/arm/src/imxrt/imxrt_timerisr.c @@ -49,7 +49,8 @@ /* Select MCU-specific settings * - * The SysTick timer is driven by the output of the Main Clock (main_clk). */ + * The SysTick timer is driven by the output of the Main Clock (main_clk). + */ #define IMXRT_SYSTICK_CLOCK BOARD_CPU_FREQUENCY @@ -146,33 +147,31 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, case(PM_NORMAL): { /* Logic for PM_NORMAL goes here */ - } break; case(PM_IDLE): { /* Logic for PM_IDLE goes here */ - } break; case(PM_STANDBY): { /* Logic for PM_STANDBY goes here */ - } break; case(PM_SLEEP): { /* Logic for PM_SLEEP goes here */ - } break; default: + /* Should not get here */ + break; } } diff --git a/arch/arm/src/imxrt/imxrt_usdhc.h b/arch/arm/src/imxrt/imxrt_usdhc.h index dff7fed217f..ea1d9ec159b 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.h +++ b/arch/arm/src/imxrt/imxrt_usdhc.h @@ -87,4 +87,4 @@ void imxrt_usdhc_set_sdio_card_isr(FAR struct sdio_dev_s *dev, FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno); -#endif /*__ARCH_ARM_SRC_IMXRT_IMX_USDHC_H */ +#endif /* __ARCH_ARM_SRC_IMXRT_IMX_USDHC_H */ diff --git a/arch/arm/src/imxrt/imxrt_userspace.h b/arch/arm/src/imxrt/imxrt_userspace.h index 6f39ffc54e9..1acd038e245 100644 --- a/arch/arm/src/imxrt/imxrt_userspace.h +++ b/arch/arm/src/imxrt/imxrt_userspace.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/imxrt/imxrt_userspace.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_USERSPACE_H #define __ARCH_ARM_SRC_IMXRT_IMXRT_USERSPACE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,9 +35,9 @@ #include "arm_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -50,9 +50,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: imxrt_userspace