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Merge remote-tracking branch 'origin/patch'

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This commit is contained in:
Ryan Kurtz
2026-02-25 04:51:08 -05:00
parent fc73f70b9c 0079da9835
commit 1988690096
5 changed files with 656 additions and 658 deletions
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Ghidra/Processors/Xtensa/data/languages/flix.sinc
+2 -1
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@@ -4,6 +4,7 @@
# 16 bytes. Customizable, if found they should be flagged.
define pcodeop flix;
:FLIX u_4_23 is op0=0xe & u_4_23 {
# Care probably needs to be taken here with BE support if any FLIX instructions are ever defined
:FLIX flix_i20 is op0=0xe & flix_i20 {
flix();
}
Ghidra/Processors/Xtensa/data/languages/xtensaArch.sinc
+84 -88
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@@ -108,6 +108,8 @@ define token insn(24)
ar = (8,11)
fr = (8,11)
br = (8,11)
mw = (8,9)
mx = (10,10)
as = (12,15)
fs = (12,15)
bs = (12,15)
@@ -115,45 +117,42 @@ define token insn(24)
at = (16,19)
ft = (16,19)
bt = (16,19)
my = (18,18)
op0 = (20,23)
# Signed and unsigned immediates. Named [us]N_L.M, where u and s denote signedness, L and M the
# least and most significant bit of the immediate in the instruction word, and N the length
# (i.e. M-L+1).
u3_21_23 = (1,3)
u4_20_23 = (0,3)
s8_16_23 = (0,7) signed
u8_16_23 = (0,7)
u12_12_23 = (0,11)
s12_12_23 = (0,11) signed
u16_8_23 = (0,15)
s8_6_23 = (0,17) signed
u1_20 = (0,0)
u2_18_19 = (4,5)
u3_17_19 = (5,7)
u2_16_17 = (6,7)
u1_16 = (4,4)
u1_15_15 = (11,11)
u2_14_15 = (10,11)
u3_13_15 = (9,11)
u4_12_15 = (8,11)
m0m1_14_14 = (10,10)
u2_12_13 = (8,9)
mw_12_13 = (8,9)
u1_12 = (8,8)
u4_8_11 = (12,15)
u8_4_11 = (12,19)
s4_8_11 = (12,15) signed
u1_7_7 = (19,19)
u2_6_7 = (16,17)
u3_5_7 = (17,19)
u4_4_7 = (16,19)
s4_4_7 = (16,19)
m2m3_6_6 = (18,18)
u_4_23 = (0,19)
t2_4_5 = (16,17)
u2_4_5 = (18,19)
u1_4 = (16,16)
op2_1_3 = (1,3)
op2_0 = (0,0)
ri8_i8 = (0,7)
ri8_si8 = (0,7) signed
bri12_i12 = (0,11)
bri12_si12 = (0,11) signed
ri16_i16 = (0,15)
call_o18 = (0,17) signed
op1_1_3 = (5,7)
op1_0 = (4,4)
op_r_3 = (11,11)
op_r_2_2 = (10,11)
op_r_1_3 = (9,11)
op_r_0_2 = (8,9)
op_r_0 = (8,8)
op_r = (8,11)
op_s = (12,15)
op_st = (12,19)
op_st_i8 = (12,15) signed
op_t_3 = (19,19)
op_t_1_3 = (17,19)
op_t_0_2 = (16,17)
op_t = (16,19)
op_t_0 = (16,16)
op_t_si4 = (16,19) signed
# If flix instructions are defined for a BE processor
# this will possibly need to be split for the operands
flix_i20 = (0,19)
# Care needs to be taken with these for BE
bri8_n = (18,19)
bri8_m = (16,17)
;
# little-endian -> big-endian 16-bit conversion chart
@@ -167,14 +166,14 @@ define token narrowinsn(16)
n_at = (8,11)
n_op0 = (12,15)
n_u4_12_15 = (0,3)
n_s4_12_15 = (0,3) signed
n_u4_8_11 = (4,7)
n_u1_7 = (11,11)
n_u2_6_7 = (10,11)
n_u4_4_7 = (8,11)
n_s3_4_6 = (8,10)
n_u2_4_5 = (8,9)
ri6_i6_0_4 = (0,3)
ri6_si6_0_4 = (0,3) signed
n_op_t = (4,7)
n_op_s_3 = (11,11)
n_op_s_2_2 = (10,11)
n_op_s = (8,11)
n_op_s_0_3 = (8,10)
ri6_i6_4_2 = (8,9)
;
@else
@@ -182,9 +181,12 @@ define token narrowinsn(16)
define token insn(24)
# Named opcode/register fields.
op2 = (20,23)
op1 = (16,19)
ar = (12,15)
fr = (12,15)
br = (12,15)
mw = (12,13)
mx = (14,14)
as = (8,11)
fs = (8,11)
bs = (8,11)
@@ -192,46 +194,40 @@ define token insn(24)
at = (4,7)
ft = (4,7)
bt = (4,7)
op1 = (16,19)
my = (6,6)
op0 = (0,3)
# Signed and unsigned immediates. Named [us]N_L_M, where u and s denote signedness, L and M the
# least and most significant bit of the immediate in the instruction word, and N the length
# (i.e. M-L+1).
u3_21_23 = (21,23)
u4_20_23 = (20,23)
s8_16_23 = (16,23) signed
u8_16_23 = (16,23)
u12_12_23 = (12,23)
s12_12_23 = (12,23) signed
u16_8_23 = (8,23)
s8_6_23 = (6,23) signed
u1_20 = (20,20)
u2_18_19 = (18,19)
u3_17_19 = (17,19)
u2_16_17 = (16,17)
u1_16 = (16,16)
u1_15_15 = (15,15)
u2_14_15 = (14,15)
u3_13_15 = (13,15)
u4_12_15 = (12,15)
m0m1_14_14 = (14,14)
u2_12_13 = (12,13)
mw_12_13 = (12,13)
u1_12 = (12,12)
u4_8_11 = (8,11)
u8_4_11 = (4,11)
s4_8_11 = (8,11) signed
u1_7_7 = (7,7)
u2_6_7 = (6,7)
u3_5_7 = (5,7)
u4_4_7 = (4,7)
s4_4_7 = (4,7)
m2m3_6_6 = (6,6)
u_4_23 = (4,23)
t2_4_5 = (4,5)
u2_4_5 = (4,5)
u1_4 = (4,4)
op2_1_3 = (21,23)
op2_0 = (20,20)
ri8_i8 = (16,23)
ri8_si8 = (16,23) signed
bri12_i12 = (12,23)
bri12_si12 = (12,23) signed
ri16_i16 = (8,23)
call_o18 = (6,23) signed
op1_1_3 = (17,19)
op1_0 = (16,16)
op_r_3 = (15,15)
op_r_2_2 = (14,15)
op_r_1_3 = (13,15)
op_r_0_2 = (12,13)
op_r_0 = (12,12)
op_r = (12,15)
op_s = (8,11)
op_st = (4,11)
op_st_i8 = (8,11) signed
op_t_3 = (7,7)
op_t_1_3 = (5,7)
op_t_0_2 = (4,5)
op_t_0 = (4,4)
op_t = (4,7)
op_t_si4 = (4,7) signed
flix_i20 = (4,23)
bri8_n = (4,5)
bri8_m = (6,7)
;
# Narrow 16-bit instructions; fields are always prefixed with n_.
@@ -241,14 +237,14 @@ define token narrowinsn(16)
n_at = (4,7)
n_op0 = (0, 3)
n_u4_12_15 = (12,15)
n_s4_12_15 = (12,15) signed
n_u4_8_11 = (8,11)
n_u1_7 = (7,7)
n_u2_6_7 = (6,7)
n_u4_4_7 = (4,7)
n_s3_4_6 = (4,6)
n_u2_4_5 = (4,5)
ri6_i6_0_4 = (12,15)
ri6_si6_0_4 = (12,15) signed
n_op_t = (8,11)
n_op_s_3 = (7,7)
n_op_s_2_2 = (6,7)
n_op_s = (4,7)
n_op_s_0_3 = (4,6)
ri6_i6_4_2 = (4,5)
;
@endif
Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc
+533 -532
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File diff suppressed because it is too large Load Diff
Ghidra/Processors/Xtensa/data/languages/xtensaMain.sinc
+34 -34
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@@ -87,15 +87,15 @@ attach variables [ br bs bt ] [
# bits are named foo_LL.LM_ML.MM, where LL is the least significant bits of the least
# singificant operand half, LM the most significant bits of the least significant operand half, etc.
attach variables [ mw_12_13 ] [
attach variables [ mw ] [
M0 M1 M2 M3
];
attach variables [ m2m3_6_6 ] [
attach variables [ my ] [
M2 M3
];
attach variables [ m0m1_14_14 ] [
attach variables [ mx ] [
M0 M1
];
@@ -184,62 +184,62 @@ define pcodeop xsr;
# bits are named foo_LL_LM_ML_MM, where LL is the least significant bits of the least
# singificant operand half, LM the most significant bits of the least significant operand half, etc.
srel_16_23: rel is s8_16_23 [ rel = inst_start + s8_16_23 + 4; ] { export *:4 rel; }
ri8_srel: rel is ri8_si8 [ rel = inst_start + ri8_si8 + 4; ] { export *:4 rel; }
srel_12_23: rel is s12_12_23 [ rel = inst_start + s12_12_23 + 4; ] { export *:4 rel; }
bri12_srel: rel is bri12_si12 [ rel = inst_start + bri12_si12 + 4; ] { export *:4 rel; }
srel_6_23: rel is s8_6_23 [ rel = inst_start + s8_6_23 + 4; ] { export *:4 rel; }
urel_12_15_4_5: rel is n_u2_4_5 & n_u4_12_15 [
rel = inst_start + ((n_u2_4_5 << 4) | n_u4_12_15) + 4;
ri6_rel: rel is ri6_i6_4_2 & ri6_i6_0_4 [
rel = inst_start + ((ri6_i6_4_2 << 4) | ri6_i6_0_4) + 4;
] { export *:4 rel; }
srel_6_23_sb2: rel is s8_6_23 [
rel = (inst_start & ~3) + ( s8_6_23 << 2 ) + 4;
call_srel: rel is call_o18 [ rel = inst_start + call_o18 + 4; ] { export *:4 rel; }
call_srel_sh2: rel is call_o18 [
rel = (inst_start & ~3) + ( call_o18 << 2 ) + 4;
] { export *:4 rel; }
srel_8_23_oex_sb2: rel is u16_8_23 [
rel = ((inst_start + 3) & ~3) + ((u16_8_23 | 0xffff0000) << 2);
srel_oex_sh2: rel is ri16_i16 [
rel = ((inst_start + 3) & ~3) + ((ri16_i16 | 0xffff0000) << 2);
] { export *:4 rel; }
# Immediates split across the instruction.
u5_8_11_20: tmp is u1_20 & u4_8_11 [ tmp = (u1_20 << 4) | u4_8_11; ] { export *[const]:4 tmp; }
u5_4_7_20: tmp is u1_20 & u4_4_7 [ tmp = 32 - ((u1_20 << 4) | u4_4_7); ] { export *[const]:4 tmp; }
u5_8_11_16: tmp is u1_16 & u4_8_11 [ tmp = (u1_16 << 4) | u4_8_11; ] { export *[const]:4 tmp; }
u5_4_7_12: tmp is u1_12 & u4_4_7 [ tmp = (u1_12 << 4) | u4_4_7; ] { export *[const]:4 tmp; }
u5_8_11_4: tmp is u1_4 & u4_8_11 [ tmp = (u1_4 << 4) | u4_8_11; ] { export *[const]:4 tmp; }
u5_8_11_20: tmp is op2_0 & op_s [ tmp = (op2_0 << 4) | op_s; ] { export *[const]:4 tmp; }
u5_4_7_20: tmp is op2_0 & op_t [ tmp = 32 - ((op2_0 << 4) | op_t); ] { export *[const]:4 tmp; }
u5_8_11_16: tmp is op1_0 & op_s [ tmp = (op1_0 << 4) | op_s; ] { export *[const]:4 tmp; }
u5_4_7_12: tmp is op_r_0 & op_t [ tmp = (op_r_0 << 4) | op_t; ] { export *[const]:4 tmp; }
u5_8_11_4: tmp is op_t_0 & op_s [ tmp = (op_t_0 << 4) | op_s; ] { export *[const]:4 tmp; }
# Signed 12-bit (extended to 16) immediate, used by MOVI.
s16_16_23_8_11: tmp is s4_8_11 & u8_16_23 [
tmp = (s4_8_11 << 8) | u8_16_23;
movi_si16: tmp is op_st_i8 & ri8_i8 [
tmp = (op_st_i8 << 8) | ri8_i8;
] { export *[const]:2 tmp; }
# An “asymmetric” immediate from -32..95, used by MOVI.N.
n_s8_12_15_4_6_asymm: tmp is n_s3_4_6 & n_s4_12_15 [
tmp = ((((n_s3_4_6 & 7) << 4) | (n_s4_12_15 & 15)) |
((((n_s3_4_6 >> 2) & 1) & ((n_s3_4_6 >> 1) & 1)) << 7));
movin_si8: tmp is n_op_s_0_3 & ri6_si6_0_4 [
tmp = ((((n_op_s_0_3 & 7) << 4) | (ri6_si6_0_4 & 15)) |
((((n_op_s_0_3 >> 2) & 1) & ((n_op_s_0_3 >> 1) & 1)) << 7));
] { export *[const]:1 tmp; }
# Immediates shifted or with offset.
s16_16_23_sb8: tmp is s8_16_23 [ tmp = s8_16_23 << 8; ] { export *[const]:4 tmp; }
u15_12_23_sb3: tmp is u12_12_23 [ tmp = u12_12_23 << 3; ] { export *[const]:4 tmp; }
u10_16_23_sb2: tmp is u8_16_23 [ tmp = u8_16_23 << 2; ] { export *[const]:4 tmp; }
u9_16_23_sb1: tmp is u8_16_23 [ tmp = u8_16_23 << 1; ] { export *[const]:4 tmp; }
u5_20_23_plus1: tmp is u4_20_23 [ tmp = u4_20_23 + 1; ] { export *[const]:4 tmp; }
u8_20_23_sb4: tmp is u4_20_23 [ tmp = u4_20_23 << 4; ] { export *[const]:4 tmp; }
u5_4_7_plus7: tmp is u4_4_7 [ tmp = u4_4_7 + 7; ] { export *[const]:4 tmp; }
ri8_si8_sh8: tmp is ri8_si8 [ tmp = ri8_si8 << 8; ] { export *[const]:4 tmp; }
bri12_i12_sh3: tmp is bri12_i12 [ tmp = bri12_i12 << 3; ] { export *[const]:4 tmp; }
ri8_i8_sh2: tmp is ri8_i8 [ tmp = ri8_i8 << 2; ] { export *[const]:4 tmp; }
u9_16_23_sb1: tmp is ri8_i8 [ tmp = ri8_i8 << 1; ] { export *[const]:4 tmp; }
u5_20_23_plus1: tmp is op2 [ tmp = op2 + 1; ] { export *[const]:4 tmp; }
u8_20_23_sb4: tmp is op2 [ tmp = op2 << 4; ] { export *[const]:4 tmp; }
u5_4_7_plus7: tmp is op_t [ tmp = op_t + 7; ] { export *[const]:4 tmp; }
n_u6_12_15_sb2: tmp is n_u4_12_15 [ tmp = n_u4_12_15 << 2; ] { export *[const]:4 tmp; }
n_u6_12_15_sb2: tmp is ri6_i6_0_4 [ tmp = ri6_i6_0_4 << 2; ] { export *[const]:4 tmp; }
# One-extended. FIXME: Verify this. Only used by [LS]32E (window extension), which aren’t yet
# implemented.
s5_12_15_oex: tmp is u4_12_15 [ tmp = (u4_12_15 << 2) - 64; ] { export *[const]:2 tmp; }
s5_12_15_oex: tmp is op_r [ tmp = (op_r << 2) - 64; ] { export *[const]:2 tmp; }
# Some 4-bit immediates with mappings that can’t be (easily) expressed in a single disassembly action.
# n_u4_4_7 with 0 being -1, used by ADDI.N.
n_s4_4_7_nozero: tmp is n_u4_4_7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; }
n_s4_4_7_nozero: tmp is n_u4_4_7 [ tmp = n_u4_4_7+0; ] { export *[const]:4 tmp; }
n_s4_4_7_nozero: tmp is n_op_s = 0 [ tmp = -1; ] { export *[const]:4 tmp; }
n_s4_4_7_nozero: tmp is n_op_s [ tmp = n_op_s+0; ] { export *[const]:4 tmp; }
# B4CONST(ar) (Branch Immediate) encodings, pg. 41 f.
r_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; }
Ghidra/Processors/Xtensa/data/languages/xtensa_depbits.sinc
+3 -3
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@@ -2,9 +2,9 @@
# This is broken out because it collides with the floating point instructions. It is not included by default
# DEPBITS - Add (RRR), pg. 394.
shiftimm: simm is u4_20_23 & u1_16 [ simm = u1_16 << 4 + u4_20_23; ] { export *[const]:4 simm; }
:depbits as, at, shiftimm, u4_12_15 is u3_17_19=0x5 & u4_12_15 & as & at & op0 = 0 & shiftimm {
mask:4 = (1 << u4_12_15) - 1;
shiftimm: simm is op2 & op1_0 [ simm = op1_0 << 4 + op2; ] { export *[const]:4 simm; }
:depbits as, at, shiftimm, u4_12_15 is op1_1_3=0x5 & op_r & as & at & op0 = 0 & shiftimm {
mask:4 = (1 << op_r) - 1;
bits:4 = (as & mask) << shiftimm;
mask = mask << shiftimm;
at = (~mask & at) | bits;