diff --git a/Ghidra/Processors/Xtensa/data/languages/flix.sinc b/Ghidra/Processors/Xtensa/data/languages/flix.sinc index f012f83992..c03e07bc9c 100644 --- a/Ghidra/Processors/Xtensa/data/languages/flix.sinc +++ b/Ghidra/Processors/Xtensa/data/languages/flix.sinc @@ -4,6 +4,7 @@ # 16 bytes. Customizable, if found they should be flagged. define pcodeop flix; -:FLIX u_4_23 is op0=0xe & u_4_23 { +# Care probably needs to be taken here with BE support if any FLIX instructions are ever defined +:FLIX flix_i20 is op0=0xe & flix_i20 { flix(); } \ No newline at end of file diff --git a/Ghidra/Processors/Xtensa/data/languages/xtensaArch.sinc b/Ghidra/Processors/Xtensa/data/languages/xtensaArch.sinc index a8d8d82cfb..fa03ef3983 100644 --- a/Ghidra/Processors/Xtensa/data/languages/xtensaArch.sinc +++ b/Ghidra/Processors/Xtensa/data/languages/xtensaArch.sinc @@ -108,6 +108,8 @@ define token insn(24) ar = (8,11) fr = (8,11) br = (8,11) + mw = (8,9) + mx = (10,10) as = (12,15) fs = (12,15) bs = (12,15) @@ -115,45 +117,42 @@ define token insn(24) at = (16,19) ft = (16,19) bt = (16,19) + my = (18,18) op0 = (20,23) - # Signed and unsigned immediates. Named [us]N_L.M, where u and s denote signedness, L and M the - # least and most significant bit of the immediate in the instruction word, and N the length - # (i.e. M-L+1). - u3_21_23 = (1,3) - u4_20_23 = (0,3) - s8_16_23 = (0,7) signed - u8_16_23 = (0,7) - u12_12_23 = (0,11) - s12_12_23 = (0,11) signed - u16_8_23 = (0,15) - s8_6_23 = (0,17) signed - u1_20 = (0,0) - u2_18_19 = (4,5) - u3_17_19 = (5,7) - u2_16_17 = (6,7) - u1_16 = (4,4) - u1_15_15 = (11,11) - u2_14_15 = (10,11) - u3_13_15 = (9,11) - u4_12_15 = (8,11) - m0m1_14_14 = (10,10) - u2_12_13 = (8,9) - mw_12_13 = (8,9) - u1_12 = (8,8) - u4_8_11 = (12,15) - u8_4_11 = (12,19) - s4_8_11 = (12,15) signed - u1_7_7 = (19,19) - u2_6_7 = (16,17) - u3_5_7 = (17,19) - u4_4_7 = (16,19) - s4_4_7 = (16,19) - m2m3_6_6 = (18,18) - u_4_23 = (0,19) - t2_4_5 = (16,17) - u2_4_5 = (18,19) - u1_4 = (16,16) + op2_1_3 = (1,3) + op2_0 = (0,0) + ri8_i8 = (0,7) + ri8_si8 = (0,7) signed + bri12_i12 = (0,11) + bri12_si12 = (0,11) signed + ri16_i16 = (0,15) + call_o18 = (0,17) signed + op1_1_3 = (5,7) + op1_0 = (4,4) + op_r_3 = (11,11) + op_r_2_2 = (10,11) + op_r_1_3 = (9,11) + op_r_0_2 = (8,9) + op_r_0 = (8,8) + op_r = (8,11) + op_s = (12,15) + op_st = (12,19) + op_st_i8 = (12,15) signed + op_t_3 = (19,19) + op_t_1_3 = (17,19) + op_t_0_2 = (16,17) + op_t = (16,19) + op_t_0 = (16,16) + op_t_si4 = (16,19) signed + + # If flix instructions are defined for a BE processor + # this will possibly need to be split for the operands + flix_i20 = (0,19) + + # Care needs to be taken with these for BE + bri8_n = (18,19) + bri8_m = (16,17) ; # little-endian -> big-endian 16-bit conversion chart @@ -167,14 +166,14 @@ define token narrowinsn(16) n_at = (8,11) n_op0 = (12,15) - n_u4_12_15 = (0,3) - n_s4_12_15 = (0,3) signed - n_u4_8_11 = (4,7) - n_u1_7 = (11,11) - n_u2_6_7 = (10,11) - n_u4_4_7 = (8,11) - n_s3_4_6 = (8,10) - n_u2_4_5 = (8,9) + ri6_i6_0_4 = (0,3) + ri6_si6_0_4 = (0,3) signed + n_op_t = (4,7) + n_op_s_3 = (11,11) + n_op_s_2_2 = (10,11) + n_op_s = (8,11) + n_op_s_0_3 = (8,10) + ri6_i6_4_2 = (8,9) ; @else @@ -182,9 +181,12 @@ define token narrowinsn(16) define token insn(24) # Named opcode/register fields. op2 = (20,23) + op1 = (16,19) ar = (12,15) fr = (12,15) br = (12,15) + mw = (12,13) + mx = (14,14) as = (8,11) fs = (8,11) bs = (8,11) @@ -192,46 +194,40 @@ define token insn(24) at = (4,7) ft = (4,7) bt = (4,7) - op1 = (16,19) + my = (6,6) op0 = (0,3) # Signed and unsigned immediates. Named [us]N_L_M, where u and s denote signedness, L and M the # least and most significant bit of the immediate in the instruction word, and N the length # (i.e. M-L+1). - u3_21_23 = (21,23) - u4_20_23 = (20,23) - s8_16_23 = (16,23) signed - u8_16_23 = (16,23) - u12_12_23 = (12,23) - s12_12_23 = (12,23) signed - u16_8_23 = (8,23) - s8_6_23 = (6,23) signed - u1_20 = (20,20) - u2_18_19 = (18,19) - u3_17_19 = (17,19) - u2_16_17 = (16,17) - u1_16 = (16,16) - u1_15_15 = (15,15) - u2_14_15 = (14,15) - u3_13_15 = (13,15) - u4_12_15 = (12,15) - m0m1_14_14 = (14,14) - u2_12_13 = (12,13) - mw_12_13 = (12,13) - u1_12 = (12,12) - u4_8_11 = (8,11) - u8_4_11 = (4,11) - s4_8_11 = (8,11) signed - u1_7_7 = (7,7) - u2_6_7 = (6,7) - u3_5_7 = (5,7) - u4_4_7 = (4,7) - s4_4_7 = (4,7) - m2m3_6_6 = (6,6) - u_4_23 = (4,23) - t2_4_5 = (4,5) - u2_4_5 = (4,5) - u1_4 = (4,4) + op2_1_3 = (21,23) + op2_0 = (20,20) + ri8_i8 = (16,23) + ri8_si8 = (16,23) signed + bri12_i12 = (12,23) + bri12_si12 = (12,23) signed + ri16_i16 = (8,23) + call_o18 = (6,23) signed + op1_1_3 = (17,19) + op1_0 = (16,16) + op_r_3 = (15,15) + op_r_2_2 = (14,15) + op_r_1_3 = (13,15) + op_r_0_2 = (12,13) + op_r_0 = (12,12) + op_r = (12,15) + op_s = (8,11) + op_st = (4,11) + op_st_i8 = (8,11) signed + op_t_3 = (7,7) + op_t_1_3 = (5,7) + op_t_0_2 = (4,5) + op_t_0 = (4,4) + op_t = (4,7) + op_t_si4 = (4,7) signed + flix_i20 = (4,23) + bri8_n = (4,5) + bri8_m = (6,7) ; # Narrow 16-bit instructions; fields are always prefixed with n_. @@ -241,14 +237,14 @@ define token narrowinsn(16) n_at = (4,7) n_op0 = (0, 3) - n_u4_12_15 = (12,15) - n_s4_12_15 = (12,15) signed - n_u4_8_11 = (8,11) - n_u1_7 = (7,7) - n_u2_6_7 = (6,7) - n_u4_4_7 = (4,7) - n_s3_4_6 = (4,6) - n_u2_4_5 = (4,5) + ri6_i6_0_4 = (12,15) + ri6_si6_0_4 = (12,15) signed + n_op_t = (8,11) + n_op_s_3 = (7,7) + n_op_s_2_2 = (6,7) + n_op_s = (4,7) + n_op_s_0_3 = (4,6) + ri6_i6_4_2 = (4,5) ; @endif diff --git a/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc b/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc index f7e2d391c6..f06e61937a 100644 --- a/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc +++ b/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc @@ -29,8 +29,8 @@ } # ADDI - Add Immediate (RRI8), pg. 251. -:addi at, as, s8_16_23 is s8_16_23 & ar = 0b1100 & as & at & op0 = 0b0010 { - at = as + s8_16_23; +:addi at, as, ri8_si8 is ri8_si8 & ar = 0b1100 & as & at & op0 = 0b0010 { + at = as + ri8_si8; } # ADDI.N - Narrow Add Immediate (RRRN), pg. 252. @@ -38,27 +38,27 @@ n_ar = n_as + n_s4_4_7_nozero; } -# ADDMI - Add Immediate with Shift by 8, pg. 253. -:addmi at, as, s16_16_23_sb8 is s16_16_23_sb8 & ar = 0b1101 & as & at & op0 = 0b0010 { - at = as + s16_16_23_sb8; +# ADDMI - Add Immediate with Shift by 8 (RRI8), pg. 253. +:addmi at, as, ri8_si8_sh8 is ri8_si8_sh8 & ar = 0b1101 & as & at & op0 = 0b0010 { + at = as + ri8_si8_sh8; } -# ADDX2 - Add with Shift by 1, pg. 254. +# ADDX2 - Add with Shift by 1 (RRR), pg. 254. :addx2 ar, as, at is op2 = 0b1001 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 1) + at; } -# ADDX4 - Add with Shift by 2, pg. 255. +# ADDX4 - Add with Shift by 2 (RRR), pg. 255. :addx4 ar, as, at is op2 = 0b1010 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 2) + at; } -# ADDX8 - Add with Shift by 4, pg. 256. +# ADDX8 - Add with Shift by 4 (RRR), pg. 256. :addx8 ar, as, at is op2 = 0b1011 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 3) + at; } -# ALL4 - All 4 Booleans True, pg. 257. +# ALL4 - All 4 Booleans True (RRR), pg. 257. :all4 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1001 & bs & bt & op0 = 0 { local b = *[register]:1 &:4 bs+1; local c = *[register]:1 &:4 bs+2; @@ -66,7 +66,7 @@ bt = bs && b && c && d; } -# ALL8 - All 8 Booleans True, pg. 258. +# ALL8 - All 8 Booleans True (RRR), pg. 258. :all8 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1011 & bs & bt & op0 = 0 { local b = *[register]:1 &:4 bs+1; local c = *[register]:1 &:4 bs+2; @@ -78,22 +78,22 @@ bt = bs && b && c && d && e && f && g && h; } -# AND - Bitwise Logical And, pg. 259. +# AND - Bitwise Logical And (RRR), pg. 259. :and ar, as, at is op2 = 0b0001 & op1 = 0 & ar & as & at & op0 = 0 { ar = as & at; } -# ANDB - Boolean And, pg. 260. +# ANDB - Boolean And (RRR), pg. 260. :andb br, bs, bt is op2 = 0 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs && bt; } -# ANDBC - Boolean And with Complement, pg. 261. +# ANDBC - Boolean And with Complement (RRR), pg. 261. :andbc br, bs, bt is op2 = 0b0001 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs && !bt; } -# ANY4 - Any 4 Booleans True, pg. 262. +# ANY4 - Any 4 Booleans True (RRR), pg. 262. :any4 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1000 & bs & bt & op0 = 0 { local b = *[register]:1 &:4 bs+1; local c = *[register]:1 &:4 bs+2; @@ -101,7 +101,7 @@ bt = bs || b || c || d; } -# ANY8 - Any 8 Booleans True, pg. 263. +# ANY8 - Any 8 Booleans True (RRR), pg. 263. :any8 bt, bs is op2 = 0 & op1 = 0 & ar = 0b1010 & bs & bt & op0 = 0 { local b = *[register]:1 &:4 bs+1; local c = *[register]:1 &:4 bs+2; @@ -113,16 +113,16 @@ bt = bs || b || c || d || e || f || g || h; } -# BALL - Branch if All Bits Set, pg. 264. -:ball srel_16_23, as, at is srel_16_23 & ar = 0b0100 & as & at & op0 = 0b0111 { +# BALL - Branch if All Bits Set (RRI8), pg. 264. +:ball ri8_srel, as, at is ri8_srel & ar = 0b0100 & as & at & op0 = 0b0111 { local test:4 = ~as & at; - if (test == 0) goto srel_16_23; + if (test == 0) goto ri8_srel; } -# BANY - Branch if Any Bit Set, pg. 265. -:bany srel_16_23, as, at, is srel_16_23 & ar = 0b1000 & as & at & op0 = 0b0111 { +# BANY - Branch if Any Bit Set (RRI8), pg. 265. +:bany ri8_srel, as, at, is ri8_srel & ar = 0b1000 & as & at & op0 = 0b0111 { local test:4 = as & at; - if (test != 0) goto srel_16_23; + if (test != 0) goto ri8_srel; } macro extract_bit(bit, result) { @@ -133,230 +133,230 @@ macro extract_bit(bit, result) { @endif } -# BBC - Branch if Bit Clear, pg. 266. -:bbc as, at, srel_16_23 is srel_16_23 & ar = 0b0101 & as & at & op0 = 0b0111 { +# BBC - Branch if Bit Clear (RRR), pg. 266. +:bbc as, at, ri8_srel is ri8_srel & ar = 0b0101 & as & at & op0 = 0b0111 { local bval:4 = 0; extract_bit(at[0,5], bval); bval = as & bval; if (bval == 0) - goto srel_16_23; + goto ri8_srel; } -# BBCI - Branch if Bit Clear immediate, pg. 267 -:bbci as, u5_4_7_12, srel_16_23 is srel_16_23 & u3_13_15 = 0b011 & as & u5_4_7_12 & op0 = 0b0111 { +# BBCI - Branch if Bit Clear immediate (RRI8), pg. 267 +:bbci as, u5_4_7_12, ri8_srel is ri8_srel & op_r_1_3 = 0b011 & as & u5_4_7_12 & op0 = 0b0111 { local bval; extract_bit(u5_4_7_12, bval); bval = as & bval; if (bval == 0) - goto srel_16_23; + goto ri8_srel; } -# BBS - Branch if Bit Set, pg. 269. -:bbs as, at, srel_16_23 is srel_16_23 & ar = 0b1101 & as & at & op0 = 0b0111 { +# BBS - Branch if Bit Set (RRI8), pg. 269. +:bbs as, at, ri8_srel is ri8_srel & ar = 0b1101 & as & at & op0 = 0b0111 { local bval; extract_bit(at[0,5], bval); bval = as & bval; if (bval != 0) - goto srel_16_23; + goto ri8_srel; } -# BBSI - Branch if Bit Set immediate, pg. 270. -:bbsi as, u5_4_7_12, srel_16_23 is srel_16_23 & u3_13_15 = 0b111 & as & u5_4_7_12 & op0 = 0b0111 { +# BBSI - Branch if Bit Set immediate (RRI8), pg. 270. +:bbsi as, u5_4_7_12, ri8_srel is ri8_srel & op_r_1_3 = 0b111 & as & u5_4_7_12 & op0 = 0b0111 { local bval; extract_bit(u5_4_7_12, bval); bval = as & bval; if (bval != 0) - goto srel_16_23; + goto ri8_srel; } -# BEQ - Branch if Equal, pg. 272. -:beq as, at, srel_16_23 is srel_16_23 & ar = 0b0001 & as & at & op0 = 0b0111 { +# BEQ - Branch if Equal (RRI8), pg. 272. +:beq as, at, ri8_srel is ri8_srel & ar = 0b0001 & as & at & op0 = 0b0111 { if (as == at) - goto srel_16_23; + goto ri8_srel; } -# BEQI - Branch if Equal Immediate, pg. 273. -:beqi as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0 & u2_4_5 = 0b10 & op0 = 0b0110 { +# BEQI - Branch if Equal Immediate (BRI8), pg. 273. +:beqi as, r_b4const, ri8_srel is ri8_srel & r_b4const & as & bri8_m = 0 & bri8_n = 0b10 & op0 = 0b0110 { if (as == r_b4const) - goto srel_16_23; + goto ri8_srel; } -# BEQZ - Branch if Equal Zero, pg. 274. -:beqz as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0 & u2_4_5 = 0b01 & op0 = 0b0110 { +# BEQZ - Branch if Equal Zero (BRI12), pg. 274. +:beqz as, bri12_srel is bri12_srel & as & bri8_m = 0 & bri8_n = 0b01 & op0 = 0b0110 { if (as == 0) - goto srel_12_23; + goto bri12_srel; } -# BEQZ.N - Narrow Branch if Equal Zero, pg. 275. -:beqz.n n_as, urel_12_15_4_5 is urel_12_15_4_5 & n_as & n_u2_6_7 = 0b10 & n_op0 = 0b1100 { +# BEQZ.N - Narrow Branch if Equal Zero (RI6), pg. 275. +:beqz.n n_as, ri6_rel is ri6_rel & n_as & n_op_s_2_2 = 0b10 & n_op0 = 0b1100 { if (n_as == 0) - goto urel_12_15_4_5; + goto ri6_rel; } -# BF - Branch if False, pg. 276. -:bf bs, srel_16_23 is srel_16_23 & ar = 0 & bs & at = 0b0111 & op0 = 0b0110 { +# BF - Branch if False (RRI8), pg. 276. +:bf bs, ri8_srel is ri8_srel & ar = 0 & bs & at = 0b0111 & op0 = 0b0110 { if (!bs) - goto srel_16_23; + goto ri8_srel; } -# BGE - Branch if Greater Than or Equal, pg. 277. -:bge as, at, srel_16_23 is srel_16_23 & ar = 0b1010 & as & at & op0 = 0b0111 { +# BGE - Branch if Greater Than or Equal (RRI8), pg. 277. +:bge as, at, ri8_srel is ri8_srel & ar = 0b1010 & as & at & op0 = 0b0111 { if (as s>= at) - goto srel_16_23; + goto ri8_srel; } -# BGEI - Branch if Greater Than or Equal Immediate, pg. 278. -:bgei as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b11 & u2_4_5 = 0b10 & op0 = 0b0110 { +# BGEI - Branch if Greater Than or Equal Immediate (BRI8), pg. 278. +:bgei as, r_b4const, ri8_srel is ri8_srel & r_b4const & as & bri8_m = 0b11 & bri8_n = 0b10 & op0 = 0b0110 { if (as s>= r_b4const) - goto srel_16_23; + goto ri8_srel; } -# BGEU - Branch if Greater Than or Equal Unsigned, pg. 279. -:bgeu as, at, srel_16_23 is srel_16_23 & ar = 0b1011 & as & at & op0 = 0b0111 { +# BGEU - Branch if Greater Than or Equal Unsigned (RRI8), pg. 279. +:bgeu as, at, ri8_srel is ri8_srel & ar = 0b1011 & as & at & op0 = 0b0111 { if (as >= at) - goto srel_16_23; + goto ri8_srel; } -# BGEUI - Branch if Greater Than or Equal Unsigned Immediate, pg. 280. -:bgeui as, r_b4constu, srel_16_23 is srel_16_23 & r_b4constu & as & u2_6_7 = 0b11 & u2_4_5 = 0b11 & op0 = 0b0110 { +# BGEUI - Branch if Greater Than or Equal Unsigned Immediate (BRI8), pg. 280. +:bgeui as, r_b4constu, ri8_srel is ri8_srel & r_b4constu & as & bri8_m = 0b11 & bri8_n = 0b11 & op0 = 0b0110 { if (as >= r_b4constu) - goto srel_16_23; + goto ri8_srel; } -# BGEZ - Branch if Greater Than or Equal Zero, pg. 281. -:bgez as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b11 & u2_4_5 = 0b01 & op0 = 0b0110 { +# BGEZ - Branch if Greater Than or Equal Zero (BRI12), pg. 281. +:bgez as, bri12_srel is bri12_srel & as & bri8_m = 0b11 & bri8_n = 0b01 & op0 = 0b0110 { if (as s>= 0) - goto srel_12_23; + goto bri12_srel; } -# BLT - Branch if Less Than, pg. 282. -:blt as, at, srel_16_23 is srel_16_23 & ar = 0b0010 & as & at & op0 = 0b0111 { +# BLT - Branch if Less Than (RRI8), pg. 282. +:blt as, at, ri8_srel is ri8_srel & ar = 0b0010 & as & at & op0 = 0b0111 { if (as s< at) - goto srel_16_23; + goto ri8_srel; } -# BLTI - Branch if Less Than Immediate, pg. 283. -:blti as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0b0110 { +# BLTI - Branch if Less Than Immediate (BRI8), pg. 283. +:blti as, r_b4const, ri8_srel is ri8_srel & r_b4const & as & bri8_m = 0b10 & bri8_n = 0b10 & op0 = 0b0110 { if (as s< r_b4const) - goto srel_16_23; + goto ri8_srel; } -# BLTU - Branch if Less Than Unsigned, pg. 284. -:bltu as, at, srel_16_23 is srel_16_23 & ar = 0b0011 & as & at & op0 = 0b0111 { +# BLTU - Branch if Less Than Unsigned (RRI8), pg. 284. +:bltu as, at, ri8_srel is ri8_srel & ar = 0b0011 & as & at & op0 = 0b0111 { if (as < at) - goto srel_16_23; + goto ri8_srel; } -# BLTUI - Branch if Less Than Unsigned Immediate, pg. 285. -:bltui as, r_b4constu, srel_16_23 is srel_16_23 & r_b4constu & as & u2_6_7 = 0b10 & u2_4_5 = 0b11 & op0 = 0b0110 { +# BLTUI - Branch if Less Than Unsigned Immediate (BRI8), pg. 285. +:bltui as, r_b4constu, ri8_srel is ri8_srel & r_b4constu & as & bri8_m = 0b10 & bri8_n = 0b11 & op0 = 0b0110 { if (as < r_b4constu) - goto srel_16_23; + goto ri8_srel; } -# BLTZ - Branch if Less Than Zero, pg. 286. -:bltz as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b10 & u2_4_5 = 0b01 & op0 = 0b0110 { +# BLTZ - Branch if Less Than Zero (BRI12), pg. 286. +:bltz as, bri12_srel is bri12_srel & as & bri8_m = 0b10 & bri8_n = 0b01 & op0 = 0b0110 { if (as s< 0) - goto srel_12_23; + goto bri12_srel; } -# BNALL - Branch if Not-All Bits Set, pg. 287. -:bnall srel_16_23, as, at is srel_16_23 & ar = 0b1100 & as & at & op0 = 0b0111 { +# BNALL - Branch if Not-All Bits Set (RRI8), pg. 287. +:bnall ri8_srel, as, at is ri8_srel & ar = 0b1100 & as & at & op0 = 0b0111 { if ((~as & at) != 0) - goto srel_16_23; + goto ri8_srel; } -# BNE - Branch if Not Equal, pg. 288. -:bne as, at, srel_16_23 is srel_16_23 & ar = 0b1001 & as & at & op0 = 0b0111 { +# BNE - Branch if Not Equal (RRI8), pg. 288. +:bne as, at, ri8_srel is ri8_srel & ar = 0b1001 & as & at & op0 = 0b0111 { if (as != at) - goto srel_16_23; + goto ri8_srel; } -# BNEI - Branch if Not EquaL Immediate, pg. 289. -:bnei as, r_b4const, srel_16_23 is srel_16_23 & r_b4const & as & u2_6_7 = 0b01 & u2_4_5 = 0b10 & op0 = 0b0110 { +# BNEI - Branch if Not EquaL Immediate (BRI8), pg. 289. +:bnei as, r_b4const, ri8_srel is ri8_srel & r_b4const & as & bri8_m = 0b01 & bri8_n = 0b10 & op0 = 0b0110 { if (as != r_b4const) - goto srel_16_23; + goto ri8_srel; } -# BNEZ - Branch if Not Equal Zero, pg. 290. -:bnez as, srel_12_23 is srel_12_23 & as & u2_6_7 = 0b01 & u2_4_5 = 0b01 & op0 = 0b0110 { +# BNEZ - Branch if Not Equal Zero (BRI12), pg. 290. +:bnez as, bri12_srel is bri12_srel & as & bri8_m = 0b01 & bri8_n = 0b01 & op0 = 0b0110 { if (as != 0) - goto srel_12_23; + goto bri12_srel; } -# BNEZ.N - Narrow Branch if Not Equal Zero, pg. 291. -:bnez.n n_as, urel_12_15_4_5 is urel_12_15_4_5 & n_as & n_u2_6_7 = 0b11 & n_op0 = 0b1100 { +# BNEZ.N - Narrow Branch if Not Equal Zero (RI6), pg. 291. +:bnez.n n_as, ri6_rel is ri6_rel & n_as & n_op_s_2_2 = 0b11 & n_op0 = 0b1100 { if (n_as != 0) - goto urel_12_15_4_5; + goto ri6_rel; } -# BNONE - Branch if No Bit Set, pg. 292. -:bnone srel_16_23, as, at, is srel_16_23 & ar = 0 & as & at & op0 = 0b0111 { +# BNONE - Branch if No Bit Set (RRI8), pg. 292. +:bnone ri8_srel, as, at, is ri8_srel & ar = 0 & as & at & op0 = 0b0111 { if ((as & at) == 0) - goto srel_16_23; + goto ri8_srel; } -# BREAK - Breakpoint, pg. 293. -:break u4_8_11, u4_4_7 is op2 = 0 & op1 = 0 & ar = 0b0100 & u4_8_11 & u4_4_7 & op0 = 0 { +# BREAK - Breakpoint (RRR), pg. 293. +:break op_s, op_t is op2 = 0 & op1 = 0 & ar = 0b0100 & op_s & op_t & op0 = 0 { break_inst:4 = inst_start; - breakpoint(0x001000:4, break_inst, u4_8_11:1, u4_4_7:1); + breakpoint(0x001000:4, break_inst, op_s:1, op_t:1); } -# BREAK.N - Narrow Breakpoint, pg. 295. -:break.n n_u4_8_11 is n_ar = 0b1111 & n_u4_8_11 & n_at = 0b0010 & n_op0 = 0b1101 { +# BREAK.N - Narrow Breakpoint (RRRN), pg. 295. +:break.n n_op_t is n_ar = 0b1111 & n_op_t & n_at = 0b0010 & n_op0 = 0b1101 { break_inst:4 = inst_start; - breakpoint(0x010000:4, break_inst, n_u4_8_11:1, 0:1); + breakpoint(0x010000:4, break_inst, n_op_t:1, 0:1); } -# BT - Branch if True, pg. 296. -:bt bs, srel_16_23 is srel_16_23 & ar = 0b0001 & bs & at = 0b0111 & op0 = 0b0110 { +# BT - Branch if True (RRI8), pg. 296. +:bt bs, ri8_srel is ri8_srel & ar = 0b0001 & bs & at = 0b0111 & op0 = 0b0110 { if (bs) - goto srel_16_23; + goto ri8_srel; } -# CALL0 - Non-windowed Call, pg. 297. -:call0 srel_6_23_sb2 is srel_6_23_sb2 & u2_4_5 = 0 & op0 = 0b0101 { +# CALL0 - Non-windowed Call (CALL), pg. 297. +:call0 call_srel_sh2 is call_srel_sh2 & bri8_n = 0 & op0 = 0b0101 { $(PS_CALLINC) = 0; a0 = inst_next; - call srel_6_23_sb2; + call call_srel_sh2; } -# CALL4 - Call PC-relative, Rotate Window by 4, pg. 298. -:call4 srel_6_23_sb2 is srel_6_23_sb2 & Ret4 & u2_4_5 = 0b01 & op0 = 0b0101 { +# CALL4 - Call PC-relative, Rotate Window by 4 (CALL), pg. 298. +:call4 call_srel_sh2 is call_srel_sh2 & Ret4 & bri8_n = 0b01 & op0 = 0b0101 { $(PS_CALLINC) = 1; a4 = Ret4; swap4(); - call srel_6_23_sb2; + call call_srel_sh2; restore4(); } -# CALL8 - Call PC-relative, Rotate Window by 8, pg. 300. -:call8 srel_6_23_sb2 is srel_6_23_sb2 & Ret8 & u2_4_5 = 0b10 & op0 = 0b0101 { +# CALL8 - Call PC-relative, Rotate Window by 8 (CALL), pg. 300. +:call8 call_srel_sh2 is call_srel_sh2 & Ret8 & bri8_n = 0b10 & op0 = 0b0101 { $(PS_CALLINC) = 2; a8 = Ret8; swap8(); - call srel_6_23_sb2; + call call_srel_sh2; restore8(); } -# CALL12 - Call PC-relative, Rotate Window by 12, pg. 302. -:call12 srel_6_23_sb2 is srel_6_23_sb2 & Ret12 & u2_4_5 = 0b11 & op0 = 0b0101 { +# CALL12 - Call PC-relative, Rotate Window by 12 (CALL), pg. 302. +:call12 call_srel_sh2 is call_srel_sh2 & Ret12 & bri8_n = 0b11 & op0 = 0b0101 { $(PS_CALLINC) = 3; a12 = Ret12; swap12(); - call srel_6_23_sb2; + call call_srel_sh2; restore12(); } -# CALLX0 - Non-windowed Call Register, pg. 304. -:callx0 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6_7 = 0b11 & u2_4_5 = 0 & op0 = 0 { +# CALLX0 - Non-windowed Call Register (CALLX), pg. 304. +:callx0 as is op2 = 0 & op1 = 0 & ar = 0 & as & bri8_m = 0b11 & bri8_n = 0 & op0 = 0 { $(PS_CALLINC) = 0; local dst = as; a0 = inst_next; call [dst]; } -# CALLX4 - Call Register, Rotate Window by 4, pg. 305. -:callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret4 & u2_6_7 = 0b11 & u2_4_5 = 0b01 & op0 = 0 { +# CALLX4 - Call Register, Rotate Window by 4 (CALLX), pg. 305. +:callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret4 & bri8_m = 0b11 & bri8_n = 0b01 & op0 = 0 { $(PS_CALLINC) = 1; dest:4 = as; a4 = Ret4; @@ -365,8 +365,8 @@ macro extract_bit(bit, result) { restore4(); } -# CALLX8 - Call Register, Rotate Window by 8, pg. 307. -:callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret8 & u2_6_7 = 0b11 & u2_4_5 = 0b10 & op0 = 0 { +# CALLX8 - Call Register, Rotate Window by 8 (CALLX), pg. 307. +:callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret8 & bri8_m = 0b11 & bri8_n = 0b10 & op0 = 0 { $(PS_CALLINC) = 2; dest:4 = as; a8 = Ret8; @@ -375,8 +375,8 @@ macro extract_bit(bit, result) { restore8(); } -# CALLX12 - Call Register, Rotate Window by 12, pg. 308. -:callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret12 & u2_6_7 = 0b11 & u2_4_5 = 0b11 & op0 = 0 { +# CALLX12 - Call Register, Rotate Window by 12 (CALLX), pg. 308. +:callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & Ret12 & bri8_m = 0b11 & bri8_n = 0b11 & op0 = 0 { $(PS_CALLINC) = 3; dest:4 = as; a12 = Ret12; @@ -385,13 +385,13 @@ macro extract_bit(bit, result) { restore12(); } -# CEIL.S - Ceiling Single to Fixed, pg. 311. -:ceil.s ar, fs, u4_4_7 is op2 = 0b1011 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# CEIL.S - Ceiling Single to Fixed (RRR), pg. 311. +:ceil.s ar, fs, op_t is op2 = 0b1011 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = 1 << op_t; ar = ceil(fs f* int2float(scale)); } -# CLAMPS - Signed Clamp, pg. 312. +# CLAMPS - Signed Clamp (RRR), pg. 312. :clamps ar, as, u5_4_7_plus7 is op2 = 0b0011 & op1 = 0b0011 & ar & as & u5_4_7_plus7 & op0 = 0 { # ar min(max(as, -2^{u5_4_7_plus7}), 2^{u5_4_7_plus7}-1) local x:4 = as; @@ -402,457 +402,457 @@ macro extract_bit(bit, result) { ar = (zext(mt) * max) + (zext(!mt) * (clamp-1)); } -# DHI - Data Cache Hit Invalidate, pg. 313. -:dhi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0110 & op0 = 0b0010 { - dhi(as + u10_16_23_sb2); +# DHI - Data Cache Hit Invalidate (RRI8), pg. 313. +:dhi as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0110 & op0 = 0b0010 { + dhi(as + ri8_i8_sh2); } -# DHU - Data Cache Hit Unlock, pg. 315. +# DHU - Data Cache Hit Unlock (RRI4), pg. 315. :dhu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0010 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { dhu(as + u8_20_23_sb4); } -# DHWB - Data Cache Hit Writeback, pg. 317. -:dhwb as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0100 & op0 = 0b0010 { - dhwb(as + u10_16_23_sb2); +# DHWB - Data Cache Hit Writeback (RRI8), pg. 317. +:dhwb as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0100 & op0 = 0b0010 { + dhwb(as + ri8_i8_sh2); } -# DHWBI - Data Cache Hit Writeback Invalidate, pg. 319. -:dhwbi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0101 & op0 = 0b0010 { - dhwbi(as + u10_16_23_sb2); +# DHWBI - Data Cache Hit Writeback Invalidate (RRI8), pg. 319. +:dhwbi as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0101 & op0 = 0b0010 { + dhwbi(as + ri8_i8_sh2); } -# DII - Data Cache Index Invalidate, pg. 321. -:dii as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0111 & op0 = 0b0010 { - dii(as + u10_16_23_sb2); +# DII - Data Cache Index Invalidate (RRI8), pg. 321. +:dii as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0111 & op0 = 0b0010 { + dii(as + ri8_i8_sh2); } -# DIU - Data Cache Index Unlock, pg. 323. +# DIU - Data Cache Index Unlock (RRI4), pg. 323. :diu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0011 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { diu(as + u8_20_23_sb4); } -# DIWB - Data Cache Index Write Back, pg. 325. +# DIWB - Data Cache Index Write Back (RRI4), pg. 325. :diwb as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0100 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { diwb(as + u8_20_23_sb4); } -# DIWBI - Data Cache Index Write Back Invalidate, pg. 327. +# DIWBI - Data Cache Index Write Back Invalidate (RRI4), pg. 327. :diwbi as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0101 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { diwbi(as + u8_20_23_sb4); } -# DPFL - Data Cache Prefetch and Lock, pg. 329. +# DPFL - Data Cache Prefetch and Lock (RRI4), pg. 329. :dpfl as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0 & ar = 0b0111 & as & at = 0b1000 & op0 = 0b0010 { dpfl(as + u8_20_23_sb4); } -# DPFR - Data Cache Prefetch for Read, pg. 331. -:dpfr as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0 & op0 = 0b0010 { - dpfr(as + u10_16_23_sb2); +# DPFR - Data Cache Prefetch for Read (RRI8), pg. 331. +:dpfr as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0 & op0 = 0b0010 { + dpfr(as + ri8_i8_sh2); } -# DPFRO - Data Cache Prefetch for Read Once, pg. 333. -:dpfro as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0010 & op0 = 0b0010 { - dpfro(as + u10_16_23_sb2); +# DPFRO - Data Cache Prefetch for Read Once (RRI8), pg. 333. +:dpfro as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0010 & op0 = 0b0010 { + dpfro(as + ri8_i8_sh2); } -# DPFW - Data Cache Prefetch for Write, pg. 335. -:dpfw as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0001 & op0 = 0b0010 { - dpfw(as + u10_16_23_sb2); +# DPFW - Data Cache Prefetch for Write (RRI8), pg. 335. +:dpfw as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0001 & op0 = 0b0010 { + dpfw(as + ri8_i8_sh2); } -# DPFWO - Data Cache Prefetch for Write Once, pg. 337. -:dpfwo as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b0011 & op0 = 0b0010 { - dpfwo(as + u10_16_23_sb2); +# DPFWO - Data Cache Prefetch for Write Once (RRI8), pg. 337. +:dpfwo as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b0011 & op0 = 0b0010 { + dpfwo(as + ri8_i8_sh2); } -# DSYNC - Load/Store Synchronize, pg. 339. +# DSYNC - Load/Store Synchronize (RRR), pg. 339. :dsync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0011 & op0 = 0 { dsync(); } -# ENTRY - Subroutine Entry, pg. 340. -:entry as, u15_12_23_sb3 is u15_12_23_sb3 & as & u2_6_7 = 0b00 & u2_4_5 = 0b11 & op0 = 0b0110 { +# ENTRY - Subroutine Entry (BRI12), pg. 340. +:entry as, bri12_i12_sh3 is bri12_i12_sh3 & as & bri8_m = 0b00 & bri8_n = 0b11 & op0 = 0b0110 { local callSP = a1; callinc:1 = $(PS_CALLINC); rotateRegWindow(callinc); - as = callSP - zext(u15_12_23_sb3); + as = callSP - zext(bri12_i12_sh3); } -# ESYNC - Execute Synchronize, pg. 342. +# ESYNC - Execute Synchronize (RRR), pg. 342. :esync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0010 & op0 = 0 { esync(); } -# EXCW - Exception Wait, pg. 343. +# EXCW - Exception Wait (RRR), pg. 343. :excw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1000 & op0 = 0 { excw(); } -# EXTUI - Extract Unsigned Immediate, pg. 344. -:extui ar, at, u5_8_11_16, u5_20_23_plus1 is u5_20_23_plus1 & u3_17_19 = 0b010 & u5_8_11_16 & ar & at & op0 = 0 { +# EXTUI - Extract Unsigned Immediate (RRR), pg. 344. +:extui ar, at, u5_8_11_16, u5_20_23_plus1 is u5_20_23_plus1 & op1_1_3 = 0b010 & u5_8_11_16 & ar & at & op0 = 0 { local shifted:4 = at >> u5_8_11_16; local mask:4 = (1:4 << (u5_20_23_plus1))-1; ar = shifted & mask; } -# EXTW - External Wait, pg. 345. +# EXTW - External Wait (RRR), pg. 345. :extw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1101 & op0 = 0 { extw(); } -# FLOAT.S - Convert Fixed to Single, pg. 346. -:float.s fr, as, u4_4_7 is op2 = 0b1100 & op1 = 0b1010 & fr & as & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# FLOAT.S - Convert Fixed to Single (RRR), pg. 346. +:float.s fr, as, op_t is op2 = 0b1100 & op1 = 0b1010 & fr & as & op_t & op0 = 0 { + local scale:4 = 1 << op_t; fr = int2float(as) f/ int2float(scale); } -# FLOOR.S - Floor Single to Fixed, pg. 347. -:floor.s ar, fs, u4_4_7 is op2 = 0b1010 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# FLOOR.S - Floor Single to Fixed (RRR), pg. 347. +:floor.s ar, fs, op_t is op2 = 0b1010 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = 1 << op_t; ar = floor(fs f* int2float(scale)); } -# IDTLB - Invalidate Data TLB Entry, pg. 348. +# IDTLB - Invalidate Data TLB Entry (RRR), pg. 348. :idtlb as is op2 = 0b0101 & op1 = 0 & ar = 0b1100 & as & at = 0 & op0 = 0 { idtlb(); } -# IHI - Instruction Cache Hit Invalidate, pg. 349. -:ihi as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1110 & op0 = 0b0010 { - ihi(as + u10_16_23_sb2); +# IHI - Instruction Cache Hit Invalidate (RRI8), pg. 349. +:ihi as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b1110 & op0 = 0b0010 { + ihi(as + ri8_i8_sh2); } -# IHU - Instruction Cache Hit Unlock, pg. 351. +# IHU - Instruction Cache Hit Unlock (RRI4), pg. 351. :ihu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0010 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 { ihu(as + u8_20_23_sb4); } -# III - Instruction Cache Index Invalidate, pg. 353. -:iii as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1111 & op0 = 0b0010 { - iii(as + u10_16_23_sb2); +# III - Instruction Cache Index Invalidate (RRI8), pg. 353. +:iii as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b1111 & op0 = 0b0010 { + iii(as + ri8_i8_sh2); } -# IITLB - Invalidate Instruction TLB Entry, pg. 355. +# IITLB - Invalidate Instruction TLB Entry (RRR), pg. 355. :iitlb as is op2 = 0b0101 & op1 = 0 & ar = 0b0100 & as & at = 0 & op0 = 0 { iitlb(as); } -# IIU - Instruction Cache Index Unlock, pg. 356. +# IIU - Instruction Cache Index Unlock (RRI4), pg. 356. :iiu as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0b0011 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 { iiu(as + u8_20_23_sb4); } -# ILL - Illegal Instruction, pg. 358. +# ILL - Illegal Instruction (CALLX), pg. 358. :ill is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & at = 0 & op0 = 0 { ill(); goto inst_start; } -# ILL.N - Narrow Illegal Instruction, pg. 359. +# ILL.N - Narrow Illegal Instruction (RRRN), pg. 359. :ill.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0110 & n_op0 = 0b1101 { ill(); goto inst_start; } -# IPF - Instruction Cache Prefetch, pg. 360. -:ipf as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0111 & as & at = 0b1100 & op0 = 0b0010 { - ipf(as + u10_16_23_sb2); +# IPF - Instruction Cache Prefetch (RRI8), pg. 360. +:ipf as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0111 & as & at = 0b1100 & op0 = 0b0010 { + ipf(as + ri8_i8_sh2); } -# IPFL - Instruction Cache Prefetch and Lock, pg. 362. +# IPFL - Instruction Cache Prefetch and Lock (RRI4), pg. 362. :ipfl as, u8_20_23_sb4 is u8_20_23_sb4 & op1 = 0 & ar = 0b0111 & as & at = 0b1101 & op0 = 0b0010 { ipfl(as + u8_20_23_sb4); } -# ISYNC - Instruction Fetch Synchronize, pg. 364. +# ISYNC - Instruction Fetch Synchronize (RRR), pg. 364. :isync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0 & op0 = 0 { isync(); } -# J - Unconditional Jump, pg. 366. -:j srel_6_23 is srel_6_23 & u2_4_5 = 0 & op0 = 0b0110 { - goto srel_6_23; +# J - Unconditional Jump (CALL), pg. 366. +:j call_srel is call_srel & bri8_n = 0 & op0 = 0b0110 { + goto call_srel; } # J.L is a macro. -# RET (JX A0) - Non-Windowed Return, pg. 478. -:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0 { +# RET (JX A0) - Non-Windowed Return (CALLX), pg. 478. +:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & bri8_m = 0b10 & bri8_n = 0b10 & op0 = 0 { return [a0]; } # The manual suggests that RET is equivalent to JX A0, yet RET has bit 5 unset, JX doesn’t. -:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b00 & op0 = 0 { +:ret is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & bri8_m = 0b10 & bri8_n = 0b00 & op0 = 0 { return [a0]; } -# JX - Uncoditional Jump Register, pg. 368. -:jx as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6_7 = 0b10 & u2_4_5 = 0b10 & op0 = 0 { +# JX - Uncoditional Jump Register (CALLX), pg. 368. +:jx as is op2 = 0 & op1 = 0 & ar = 0 & as & bri8_m = 0b10 & bri8_n = 0b10 & op0 = 0 { goto [as]; } -# L8UI - Load 8-bit Unsigned, pg. 369. -:l8ui at, as, u8_16_23 is u8_16_23 & ar = 0 & as & at & op0 = 0b0010 { - local addr:4 = as + zext(u8_16_23:1); +# L8UI - Load 8-bit Unsigned (RRI8), pg. 369. +:l8ui at, as, ri8_i8 is ri8_i8 & ar = 0 & as & at & op0 = 0b0010 { + local addr:4 = as + zext(ri8_i8:1); at = zext(*:1 addr); } -# L16SI - Load 16-bit Signed, pg. 370. +# L16SI - Load 16-bit Signed (RRI8), pg. 370. :l16si at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b1001 & as & at & op0 = 0b0010 { local addr:4 = as + u9_16_23_sb1; at = sext(*:2 addr); } -# L16UI - Load 16-bit Unsigned, pg. 372. +# L16UI - Load 16-bit Unsigned (RRI8), pg. 372. :l16ui at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b001 & as & at & op0 = 0b0010 { local addr:4 = as + u9_16_23_sb1; at = zext(*:2 addr); } -# L32AI - Load 32-bit Acquire, pg. 374. -:l32ai at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1011 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; +# L32AI - Load 32-bit Acquire (RRI8), pg. 374. +:l32ai at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1011 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; at = *:4 addr; acquire(addr); } -# L32E - Load 32-bit for Window Exceptions, pg. 376. +# L32E - Load 32-bit for Window Exceptions (RRI4), pg. 376. :l32e at, as, s5_12_15_oex is op2 = 0 & op1 = 0b1001 & s5_12_15_oex & as & at & op0 = 0 { ptr:4 = as + sext(s5_12_15_oex); at = *:4 ptr; } -# L32I - Load 32-bit, pg. 378. -:l32i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0010 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; +# L32I - Load 32-bit (RRI8), pg. 378. +:l32i at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0010 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; at = *:4 addr; } -# L32I.N - Narrow Load 32-bit, pg. 380. +# L32I.N - Narrow Load 32-bit (RRRN), pg. 380. :l32i.n n_at, n_as, n_u6_12_15_sb2 is n_u6_12_15_sb2 & n_as & n_at & n_op0 = 0b1000 { local addr:4 = n_as + n_u6_12_15_sb2; n_at = *:4 addr; } -# L32R - Load 32-bit PC-relative, pg. 382. -:l32r at, srel_8_23_oex_sb2 is srel_8_23_oex_sb2 & at & op0 = 0b0001 { - at = srel_8_23_oex_sb2; +# L32R - Load 32-bit PC-relative (RI6), pg. 382. +:l32r at, srel_oex_sh2 is srel_oex_sh2 & at & op0 = 0b0001 { + at = srel_oex_sh2; } -# LDCT - Load Data Cache Tag, pg. 384. +# LDCT - Load Data Cache Tag (RRR), pg. 384. :ldct at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1000 & as & at & op0 = 0 { at = ldct(as); } -# LICT - Load Instruction Cache Tag, pg. 388. +# LICT - Load Instruction Cache Tag (RRR), pg. 388. :lict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0 & as & at & op0 = 0 { at = lict(as); } -# LICW - Load Instruction Cache Word, pg. 390. +# LICW - Load Instruction Cache Word (RRR), pg. 390. :licw at, as is op2 = 0b1111 & op1 = 0b0010 & ar = 0 & as & at & op0 = 0 { at = licw(as); } -# LSI - Load Single Immediate, pg. 398. -:lsi ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0 & as & ft & op0 = 0b0011 { - local addr:4 = as + u10_16_23_sb2; +# LSI - Load Single Immediate, (RRI8) pg. 398. +:lsi ft, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0 & as & ft & op0 = 0b0011 { + local addr:4 = as + ri8_i8_sh2; ft = *:4 addr; } -# LSIU - Load Single Immediate with Update, pg. 400. -:lsiu ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1000 & as & ft & op0 = 0b0011 { - local addr:4 = as + u10_16_23_sb2; +# LSIU - Load Single Immediate with Update (RRI8), pg. 400. +:lsiu ft, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1000 & as & ft & op0 = 0b0011 { + local addr:4 = as + ri8_i8_sh2; ft = *:4 addr; as = addr; } -# LSX - Load Single Indexed, pg. 402. +# LSX - Load Single Indexed (RRR), pg. 402. :lsx fr, as, at is op2 = 0 & op1 = 0b1000 & fr & as & at & op0 = 0 { local addr:4 = as+at; fr = *:4 addr; } -# LSXU - Load Single Indexed with Update, pg. 404. +# LSXU - Load Single Indexed with Update (RRR), pg. 404. :lsxu fr, as, at is op2 = 0b0001 & op1 = 0b1000 & fr & as & at & op0 = 0 { local addr:4 = as+at; fr = *:4 addr; as = addr; } -# MADD.S - Multiply and Add Single, pg. 406. +# MADD.S - Multiply and Add Single (RRR), pg. 406. :madd.s fr, fs, ft is op2 = 0b0100 & op1 = 0b1010 & fr & fs & ft & op0 = 0 { fr = fr f+ (fs f* ft); } -# MAX - Maximum Value, pg. 407. +# MAX - Maximum Value (RRR), pg. 407. :max ar, as, at is op2 = 0b0101 & op1 = 0b0011 & ar & as & at & op0 = 0 { test:1 = as s< at; ar = (zext(test) * at) + (zext(!test) * as); } -# MAXU - Maximum Value Unsigned, pg. 408. +# MAXU - Maximum Value Unsigned (RRR), pg. 408. :maxu ar, as, at is op2 = 0b0111 & op1 = 0b0011 & ar & as & at & op0 = 0 { test:1 = as < at; ar = (zext(test) * at) + (zext(!test) * as); } -# MEMW - Memory Wait, pg. 409. +# MEMW - Memory Wait (RRR), pg. 409. :memw is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1100 & op0 = 0 { memw(); } -# MIN - Minimum Value, pg. 410. +# MIN - Minimum Value (RRR), pg. 410. :min ar, as, at is op2 = 0b0100 & op1 = 0b0011 & ar & as & at & op0 = 0 { test:1 = as s< at; ar = (zext(test) * as) + (zext(!test) * at); } -# MINU - Minimum Value Unsigned, pg. 411. +# MINU - Minimum Value Unsigned (RRR), pg. 411. :minu ar, as, at is op2 = 0b0110 & op1 = 0b0011 & ar & as & at & op0 = 0 { test:1 = as < at; ar = (zext(test) * as) + (zext(!test) * at); } -# MOV.N - Narrow Move, pg. 413. +# MOV.N - Narrow Move (RRRN), pg. 413. :mov.n n_at, n_as is n_ar = 0 & n_as & n_at & n_op0 = 0b1101 { n_at = n_as; } -# MOV.S - Move Single, pg. 414. +# MOV.S - Move Single (RRR), pg. 414. :mov.s fr, fs is op2 = 0b1111 & op1 = 0b1010 & fr & fs & at = 0 & op0 = 0 { fr = fs; } -# MOVEQZ - Move if Equal to Zero, pg. 415. +# MOVEQZ - Move if Equal to Zero (RRR), pg. 415. :moveqz ar, as, at is op2 = 0b1000 & op1 = 0b0011 & ar & as & at & op0 = 0 { if (at != 0) goto ; ar = as; } -# MOVEQZ.S - Move Single if Equal to Zero, pg. 416. +# MOVEQZ.S - Move Single if Equal to Zero (RRR), pg. 416. :moveqz.s fr, fs, at is op2 = 0b1000 & op1 = 0b1011 & fr & fs & at & op0 = 0 { if (at != 0) goto ; fr = fs; } -# MOVF - Move if False, pg. 417. +# MOVF - Move if False (RRR), pg. 417. :movf ar, as, bt is op2 = 0b1100 & op1 = 0b0011 & ar & as & bt & op0 = 0 { if (bt) goto ; ar = as; } -# MOVF.S - Move Single if False, pg. 418. +# MOVF.S - Move Single if False (RRR), pg. 418. :movf.s fr, fs, bt is op2 = 0b1100 & op1 = 0b1011 & fr & fs & bt & op0 = 0 { if (bt)goto ; fr = fs; } -# MOVGEZ - Move if Greater Than or Equal to Zero, pg. 419. +# MOVGEZ - Move if Greater Than or Equal to Zero (RRR), pg. 419. :movgez ar, as, at is op2 = 0b1011 & op1 = 0b0011 & ar & as & at & op0 = 0 { if (at s< 0) goto ; ar = as; } -# MOVGEZ.S - Move Single if Greater Than or Equal to Zero, pg. 420. +# MOVGEZ.S - Move Single if Greater Than or Equal to Zero (RRR), pg. 420. :movgez.s fr, fs, at is op2 = 0b1011 & op1 = 0b1011 & fr & fs & at & op0 = 0 { if (at s< 0) goto ; fr = fs; } -# MOVI - Move Immediate, pg. 421. -:movi at, s16_16_23_8_11 is s16_16_23_8_11 & ar = 0b1010 & at & op0 = 0b0010 { - local val:4 = sext(s16_16_23_8_11); +# MOVI - Move Immediate (RRI8), pg. 421. +:movi at, movi_si16 is movi_si16 & ar = 0b1010 & at & op0 = 0b0010 { + local val:4 = sext(movi_si16); at = val; } -# MOVI.N - Narrow Move Immediate, pg. 422. -:movi.n n_as, n_s8_12_15_4_6_asymm is n_s8_12_15_4_6_asymm & n_as & n_u1_7 = 0 & n_op0 = 0b1100 { - local val:4 = sext(n_s8_12_15_4_6_asymm); +# MOVI.N - Narrow Move Immediate (RI7), pg. 422. +:movi.n n_as, movin_si8 is movin_si8 & n_as & n_op_s_3 = 0 & n_op0 = 0b1100 { + local val:4 = sext(movin_si8); n_as = val; } -# MOVLTZ - Move if Less Than Zero, pg. 423. +# MOVLTZ - Move if Less Than Zero (RRR), pg. 423. :movltz ar, as, at is op2 = 0b1010 & op1 = 0b0011 & ar & as & at & op0 = 0 { if (at s>= 0) goto ; ar = as; } -# MOVLTZ.S - Move Single if Less Than Zero, pg. 424. +# MOVLTZ.S - Move Single if Less Than Zero (RRR), pg. 424. :movltz.s fr, fs, at is op2 = 0b1010 & op1 = 0b1011 & fr & fs & at & op0 = 0 { if (at s>= 0) goto ; fr = fs; } -# MOVNEZ - Move if Not Equal to Zero, pg. 425. +# MOVNEZ - Move if Not Equal to Zero (RRR), pg. 425. :movnez ar, as, at is op2 = 0b1001 & op1 = 0b0011 & ar & as & at & op0 = 0 { if (at == 0) goto ; ar = as; } -# MOVNEZ.S - Move Single if Not Equal to Zero, pg. 426. +# MOVNEZ.S - Move Single if Not Equal to Zero (RRR), pg. 426. :movnez.s fr, fs, at is op2 = 0b1001 & op1 = 0b1011 & fr & fs & at & op0 = 0 { if (at == 0) goto ; fr = fs; } -# MOVSP - Move to Stack Pointer, pg. 427. +# MOVSP - Move to Stack Pointer (RRR), pg. 427. :movsp at, as is op2 = 0 & op1 = 0 & ar = 0b0001 & as & at & op0 = 0 { at = (zext(WindowStart == 0) * at) + (zext(WindowStart != 0) * as); } -# MOVT - Move if True, pg. 428. +# MOVT - Move if True (RRR), pg. 428. :movt ar, as, bt is op2 = 0b1101 & op1 = 0b0011 & ar & as & bt & op0 = 0 { if (!bt) goto ; ar = as; } -# MOVT.S - Move Single if True, pg. 429. +# MOVT.S - Move Single if True (RRR), pg. 429. :movt.s fr, fs, bt is op2 = 0b1101 & op1 = 0b1011 & fr & fs & bt & op0 = 0 { if (!bt) goto ; fr = fs; } -# MSUB.S - Multiply and Subtract Single, pg. 430. +# MSUB.S - Multiply and Subtract Single (RRR), pg. 430. :msub.s fr, fs, ft is op2 = 0b0101 & op1 = 0b1010 & fr & fs & ft & op0 = 0 { fr = fr f- (fs f* ft); } -# MUL.S - Multiply Single, pg. 435. +# MUL.S - Multiply Single (RRR), pg. 435. :mul.s fr, fs, ft is op2 = 0b0010 & op1 = 0b1010 & fr & fs & ft & op0 = 0 { fr = fs f* ft; } -# MUL16S - Multiply 16-bit Signed, pg. 436. +# MUL16S - Multiply 16-bit Signed (RRR), pg. 436. :mul16s ar, as, at is op2 = 0b1101 & op1 = 0b0001 & ar & as & at & op0 = 0 { ar = sext(as:2) * sext(at:2); } -# MUL16U - Multiply 16-bit Unsigned, pg. 437. +# MUL16U - Multiply 16-bit Unsigned (RRR), pg. 437. :mul16u ar, as, at is op2 = 0b1100 & op1 = 0b0001 & ar & as & at & op0 = 0 { ar = zext(as:2) * zext(at:2); } -# MULL - Multiply Low, pg. 450. +# MULL - Multiply Low (RRR), pg. 450. :mull ar, as, at is op2 = 0b1000 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as * at; } -# MULSH - Multiply Signed High, pg. 455. +# MULSH - Multiply Signed High (RRR), pg. 455. :mulsh ar, as, at is op2 = 0b1011 & op1 = 0b0010 & ar & as & at & op0 = 0 { local s64:8 = sext(as); local t64:8 = sext(at); @@ -860,7 +860,7 @@ macro extract_bit(bit, result) { ar = p(4); } -# MULUH - Multiply Unsigned High, pg. 456. +# MULUH - Multiply Unsigned High (RRR), pg. 456. :muluh ar, as, at is op2 = 0b1010 & op1 = 0b0010 & ar & as & at & op0 = 0 { local s64:8 = zext(as); local t64:8 = zext(at); @@ -868,214 +868,214 @@ macro extract_bit(bit, result) { ar = p(4); } -# NEG - Negate, pg. 457. +# NEG - Negate (RRR), pg. 457. :neg ar, at is op2 = 0b0110 & op1 = 0 & ar & as = 0 & at & op0 = 0 { ar = -at; } -# NEG.S - Negate Single, pg. 458. +# NEG.S - Negate Single (RRR), pg. 458. :neg.s fr, fs is op2 = 0b1111 & op1 = 0b1010 & fr & fs & at = 0b0110 & op0 = 0 { fr = 0 f- fs; } -# NOP - No Operation, pg. 459. +# NOP - No Operation (RRR), pg. 459. :nop is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b1111 & op0 = 0 { } -# NOP.N - Narrow No Operation, pg. 460. +# NOP.N - Narrow No Operation (RRRN), pg. 460. :nop.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0011 & n_op0 = 0b1101 { } -# NSA - Normalization Shift Amount, pg. 461. +# NSA - Normalization Shift Amount (RRR), pg. 461. :nsa at, as is op2 = 0b0100 & op1 = 0 & ar = 0b1110 & as & at & op0 = 0 { at = lzcount(~as); } -# NSAU - Normalization Shift Amount Unsigned, pg. 462. (Count leading zeros) +# NSAU - Normalization Shift Amount Unsigned (RRR), pg. 462. (Count leading zeros) :nsau at, as is op2 = 0b0100 & op1 = 0 & ar = 0b1111 & as & at & op0 = 0 { at = lzcount(as); } -# OEQ.S - Compare Single Equal, pg. 463. +# OEQ.S - Compare Single Equal (RRR), pg. 463. :oeq.s br, fs, ft is op2 = 0b0010 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = !nan(fs) && !nan(ft) && fs f== ft; } -# OLE.S - Compare Single Ordered and Less Than or Equal, pg. 464 +# OLE.S - Compare Single Ordered and Less Than or Equal (RRR), pg. 464 :ole.s br, fs, ft is op2 = 0b0110 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = !nan(fs) && !nan(ft) && fs f<= ft; } -# OLT.S - Compare Single Ordered and Less Than, pg. 465. +# OLT.S - Compare Single Ordered and Less Than (RRR), pg. 465. :olt.s br, fs, ft is op2 = 0b0100 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = !nan(fs) && !nan(ft) && fs f< ft; } -# MOV - Move, pg. 412. Special case of OR as, at, at. +# MOV - Move (RRR), pg. 412. Special case of OR as, at, at. :mov ar, as is op2 = 0b0010 & op1 = 0 & ar & as & as = at & op0 = 0 { ar = as; } -# OR - Bitwise Logical Or, pg. 466. +# OR - Bitwise Logical Or (RRR), pg. 466. :or ar, as, at is op2 = 0b0010 & op1 = 0 & ar & as & at & op0 = 0 { ar = as | at; } -# ORB - Boolean Or, pg. 467. +# ORB - Boolean Or (RRR), pg. 467. :orb br, bs, bt is op2 = 0b0010 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs || bt; } -# ORBC - Boolean Or with Complement, pg. 468. +# ORBC - Boolean Or with Complement (RRR), pg. 468. :orbc br, bs, bt is op2 = 0b0011 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs || !bt; } -# PDTLB - Probe Data TLB, pg. 469. +# PDTLB - Probe Data TLB (RRR), pg. 469. :pdtlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1101 & as & at & op0 = 0 { at = pdtlb(as); } -# PITLB - Probe Instruction TLB, pg. 470. +# PITLB - Probe Instruction TLB (RRR), pg. 470. :pitlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0101 & as & at & op0 = 0 { at = pitlb(as); } -# QUOS - Quotient Signed, pg. 471. +# QUOS - Quotient Signed (RRR), pg. 471. :quos ar, as, at is op2 = 0b1101 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as s/ at; } -# QUOU - Quotient Unsigned, pg. 472. +# QUOU - Quotient Unsigned (RRR), pg. 472. :quou ar, as, at is op2 = 0b1100 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as / at; } -# RDTLB0 - Read Data TLB Virtual Entry, pg. 473. +# RDTLB0 - Read Data TLB Virtual Entry (RRR), pg. 473. :rdtlb0 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1011 & as & at & op0 = 0 { at = rdtlb0(as); } -# RDTLB1 - Read Data TLB Entry Translation, pg. 474. +# RDTLB1 - Read Data TLB Entry Translation (RRR), pg. 474. :rdtlb1 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1111 & as & at & op0 = 0 { at = rdtlb1(as); } -# REMS - Remainder Signed, pg. 475. +# REMS - Remainder Signed (RRR), pg. 475. :rems ar, as, at, is op2 = 0b1111 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as s% at; } -# REMU - Remainder Unsigned, pg. 476. +# REMU - Remainder Unsigned (RRR), pg. 476. :remu ar, as, at, is op2 = 0b1110 & op1 = 0b0010 & ar & as & at & op0 = 0 { ar = as % at; } -# RER - Read External Register, pg. 477. +# RER - Read External Register (RRR), pg. 477. :rer as, at is op2 = 0b0100 & op1 = 0 & ar = 0b0110 & as & at & op0 = 0 { as = rer(at); } -# RET.N - Narrow Non-Windowed Return, pg. 479. +# RET.N - Narrow Non-Windowed Return (RRRN), pg. 479. :ret.n is n_ar = 0b1111 & n_as = 0 & n_at = 0 & n_op0 = 0b1101 { return [a0]; } -# RETW - Windowed Return, pg. 480. -:retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6_7 = 0b10 & u2_4_5 = 0b01 & op0 = 0 { +# RETW - Windowed Return (CALLX), pg. 480. +:retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & bri8_m = 0b10 & bri8_n = 0b01 & op0 = 0 { local addr:4 = (a0 & 0x3fffffff) | (inst_start & 0xc0000000); restoreRegWindow(); return [addr]; } -# RETW.N - Narrow Windowed Return, pg. 482. +# RETW.N - Narrow Windowed Return (RRRN), pg. 482. :retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 { local addr:4 = (a0 & 0x3fffffff) | (inst_start & 0xc0000000); restoreRegWindow(); return [addr]; } -# RFDD - Return from Debug and Dispatch, pg. 484. +# RFDD - Return from Debug and Dispatch (RRR), pg. 484. :rfdd is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1110 & (as = 0b0000 | as = 0b0001) & at = 0b0001 & op0 = 0 { local tmp:4 = rfdd(); return [tmp]; } -# RFDE _ Return From Double Exception, pg. 485. +# RFDE _ Return From Double Exception (RRR), pg. 485. :rfde is op2 = 0 & op1 = 0 & ar = 0b0011 & as =0b0010 & at = 0 & op0 = 0 { local tmp:4 = rfde(); return [tmp]; } -# RFDO - Return from Debug Operation, pg. 486. +# RFDO - Return from Debug Operation (RRR), pg. 486. :rfdo is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1110 & as = 0 & at = 0 & op0 = 0 { local tmp:4 = rfdo(); return [tmp]; } -# RFE - Return From Exception, pg. 487. +# RFE - Return From Exception (RRR), pg. 487. :rfe is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0 & at = 0 & op0 = 0 { local tmp:4 = rfe(); return [tmp]; } -rfi_epc: ptr is u4_8_11 [ ptr = $(EPC_BASE) + (4 * u4_8_11); ] { export *[register]:4 ptr; } -rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[register]:4 ptr; } +rfi_epc: ptr is op_s [ ptr = $(EPC_BASE) + (4 * op_s); ] { export *[register]:4 ptr; } +rfi_eps: ptr is op_s [ ptr = $(EPS_BASE) + (4 * op_s); ] { export *[register]:4 ptr; } -# RFI - Return from High-Priority Interrupt, pg. 488. -:rfi u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0011 & u4_8_11 & at = 0b0001 & op0 = 0 & rfi_epc & rfi_eps { +# RFI - Return from High-Priority Interrupt (RRR), pg. 488. +:rfi op_s is op2 = 0 & op1 = 0 & ar = 0b0011 & op_s & at = 0b0001 & op0 = 0 & rfi_epc & rfi_eps { PS = rfi_eps; return [rfi_epc]; } -# RFME - Return from Memory Error, pg. 489. +# RFME - Return from Memory Error (RRR), pg. 489. :rfme is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0 & at = 0b0010 & op0 = 0 { PS = MEPS; MESR[0,1] = 0; return [MEPC]; } -# RFR - Move FR to AR, pg. 490. +# RFR - Move FR to AR (RRR), pg. 490. :rfr ar, fs is op2 = 0b1111 & op1 = 0b1010 & ar & fs & at = 0b0100 & op0 = 0 { ar = fs; } -# RFUE - Return from User-Mode Exception, pg. 491. +# RFUE - Return from User-Mode Exception (RRR), pg. 491. :rfue is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0001 & at = 0 & op0 = 0 { local tmp:4 = rfue(); return [tmp]; } -# RFWO - Return from Window Overflow, pg. 492. +# RFWO - Return from Window Overflow (RRR), pg. 492. :rfwo is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0100 & at = 0 & op0 = 0 { $(PS_EXCM) = 0; rfwo(); return [EPC1]; } -# RFWU - Return from Window Underflow, pg. 493. +# RFWU - Return from Window Underflow (RRR), pg. 493. :rfwu is op2 = 0 & op1 = 0 & ar = 0b0011 & as = 0b0101 & at = 0 & op0 = 0 { $(PS_EXCM) = 0; rfwu(); return [EPC1]; } -# RITLB0 - Read Instruction TLB Virtual Entry, pg. 494. +# RITLB0 - Read Instruction TLB Virtual Entry (RRR), pg. 494. :ritlb0 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0011 & as & at & op0 = 0 { at = ritlb0(as); } -# RITLB1 - Read Instruction TLB Entry Translation, pg. 495. +# RITLB1 - Read Instruction TLB Entry Translation (RRR), pg. 495. :ritlb1 at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0111 & as & at & op0 = 0 { at = ritlb1(as); } -# ROTW - Rotate Window, pg. 496. -:rotw s4_4_7 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & s4_4_7 & op0 = 0 { - WindowBase = WindowBase + s4_4_7; +# ROTW - Rotate Window (RRR), pg. 496. +:rotw op_t_si4 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & op_t_si4 & op0 = 0 { + WindowBase = WindowBase + op_t_si4; } -# ROUND.S - Round Single to Fixed, pg. 497. -:round.s ar, fs, u4_4_7 is op2 = 0b1000 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# ROUND.S - Round Single to Fixed (RRR), pg. 497. +:round.s ar, fs, op_t is op2 = 0b1000 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = 1 << op_t; local result = fs f* int2float(scale); isNan:1 = nan(result); if (isNan) goto ; @@ -1088,41 +1088,41 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist } -# RSIL - Read and Set Interrupt Level, pg. 498. -:rsil at, u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0110 & u4_8_11 & at & op0 = 0 { - at = rsil(u4_8_11:1); +# RSIL - Read and Set Interrupt Level (RRR), pg. 498. +:rsil at, op_s is op2 = 0 & op1 = 0 & ar = 0b0110 & op_s & at & op0 = 0 { + at = rsil(op_s:1); } -# RSR - Read Special Register, pg. 500. +# RSR - Read Special Register (RSR), pg. 500. :rsr at, sr is op0 = 0 & op1 = 0b0011 & sr & at & op0 = 0 { at = rsr(sr:1); } -# RSYNC - Register Read Synchronize, pg. 502. +# RSYNC - Register Read Synchronize (RRR), pg. 502. :rsync is op2 = 0 & op1 = 0 & ar = 0b0010 & as = 0 & at = 0b0001 & op0 = 0 { rsync(); } -# RUR - Read User Register, pg. 503. -:rur ar, u8_4_11 is op2 = 0b1110 & op1 = 0b0011 & ar & u8_4_11 & op0 = 0 { - ar = rur(u8_4_11:1); +# RUR - Read User Register (RRR), pg. 503. +:rur ar, op_st is op2 = 0b1110 & op1 = 0b0011 & ar & op_st & op0 = 0 { + ar = rur(op_st:1); } -# S8I - Store 8-bit, pg. 504. -:s8i at, as, u8_16_23 is u8_16_23 & ar = 0b0100 & as & at & op0 = 0b0010 { - local addr:4 = as + zext(u8_16_23:1); - *:1 addr = at:1; +# S8I - Store 8-bit (RRI8), pg. 504. +:s8i at, as, ri8_i8 is ri8_i8 & ar = 0b0100 & as & at & op0 = 0b0010 { + local addr:4 = as + zext(ri8_i8:1); + *:1 addr = at:1; } -# S16I - Store 16-bit, pg. 505. +# S16I - Store 16-bit (RRI8), pg. 505. :s16i at, as, u9_16_23_sb1 is u9_16_23_sb1 & ar = 0b0101 & as & at & op0 = 0b0010 { - local addr:4 = as + u9_16_23_sb1; - *:2 addr = at:2; + local addr:4 = as + u9_16_23_sb1; + *:2 addr = at:2; } -# S32C1I - Store 32-bit Compare Conditional, pg. 506 -:s32c1i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1110 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; +# S32C1I - Store 32-bit Compare Conditional (RRI8), pg. 506 +:s32c1i at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1110 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; old:4 = *:4 addr; if (old != SCOMPARE1) goto ; *:4 addr = at; @@ -1130,86 +1130,87 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist at = old; } -# S32E - Store 32-bit for Window Exceptions, pg. 508. +# S32E - Store 32-bit for Window Exceptions (RRI4), pg. 508. :s32e at, as, s5_12_15_oex is op2 = 0b0100 & op1 = 0b1001 & s5_12_15_oex & as & at & op0 = 0 { ptr:4 = as + sext(s5_12_15_oex); *:4 ptr = at; } -# S32I - Store 32-bit, pg. 510. -:s32i at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0110 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; - *:4 addr = at; +# S32I - Store 32-bit (RRR), pg. 510. +:s32i at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0110 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; + *:4 addr = at; } -# S32I.N - Narrow Store 32-bit, pg. 512. +# S32I.N - Narrow Store 32-bit (RRRN), pg. 512. :s32i.n n_at, n_as, n_u6_12_15_sb2 is n_u6_12_15_sb2 & n_as & n_at & n_op0 = 0b1001 { - local addr:4 = n_as + n_u6_12_15_sb2; - *:4 addr = n_at; + local addr:4 = n_as + n_u6_12_15_sb2; + *:4 addr = n_at; } -# S32RI - Store 32-bit Release, pg. 514. -:s32ri at, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1111 & as & at & op0 = 0b0010 { - local addr:4 = as + u10_16_23_sb2; +# S32RI - Store 32-bit Release (RRI8), pg. 514. +:s32ri at, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1111 & as & at & op0 = 0b0010 { + local addr:4 = as + ri8_i8_sh2; release(addr); *:4 addr = at; } -# SDCT - Store Data Cache Tag, pg. 516. +# SDCT - Store Data Cache Tag (RRR), pg. 516. :sdct at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b1001 & as & at & op0 = 0 { sdct(as, at); } -# SEXT - Sign Extend, pg. 518. -:sext ar, as, u5_4_7_plus7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u5_4_7_plus7 & op0 = 0 { +# SEXT - Sign Extend (RRR), pg. 518. +# quoting mnemonic to prevent it showing up as an error in the sleigh editor +:^"sext" ar, as, u5_4_7_plus7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u5_4_7_plus7 & op0 = 0 { local shift:4 = 31 - u5_4_7_plus7; local tmp:4 = as << shift; ar = tmp s>> shift; } -:sext ar, as, 7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 0 & op0 = 0 { +:^"sext" ar, as, 7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & op_t = 0 & op0 = 0 { ar = sext(as:1); } -:sext ar, as, 15 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 8 & op0 = 0 { +:^"sext" ar, as, 15 is op2 = 0b0010 & op1 = 0b0011 & ar & as & op_t = 8 & op0 = 0 { ar = sext(as:2); } -# SICT - Store Instruction Cache Tag, pg. 519. +# SICT - Store Instruction Cache Tag (RRR), pg. 519. :sict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0001 & as & at & op0 = 0 { sict(as, at); } -# SICW - Store Instruction Cache word, pg. 521. +# SICW - Store Instruction Cache word (RRR), pg. 521. :sicw at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0011 & as & at & op0 = 0 { sicw(as, at); } -# SIMCALL - Simulator Call, pg. 523. +# SIMCALL - Simulator Call (RRR), pg. 523. :simcall is op2 = 0 & op1 = 0 & ar = 0b0101 & as = 0b0001 & at = 0 & op0 = 0 { simcall(); } -# SLL - Shift Left Logical, pg. 524. +# SLL - Shift Left Logical (RRR), pg. 524. :sll ar, as is op2 = 0b1010 & op1 = 0b0001 & ar & as & at = 0 & op0 = 0 { local sa:4 = 32 - SAR; ar = as << sa; } -# SLLI - Shift Left Logical Immediate, pg. 525. -:slli ar, as, u5_4_7_20 is u3_21_23 = 0 & u5_4_7_20 & op1 = 0b0001 & ar & as & op0 = 0 { +# SLLI - Shift Left Logical Immediate (RRR), pg. 525. +:slli ar, as, u5_4_7_20 is op2_1_3 = 0 & u5_4_7_20 & op1 = 0b0001 & ar & as & op0 = 0 { ar = as << u5_4_7_20; } -# SRA - Shift Right Arithmetic, pg. 526. +# SRA - Shift Right Arithmetic (RRR), pg. 526. :sra ar, at is op2 = 0b1011 & op1 = 0b0001 & ar & as = 0 & at & op0 = 0 { - ar = at s>> SAR; + ar = at s>> SAR; } -# SRAI - Shift Right Arithmetic Immediate, pg. 527. -:srai ar, at, u5_8_11_20 is u3_21_23 = 0b001 & u5_8_11_20 & op1 = 0b0001 & ar & at & op0 = 0 { +# SRAI - Shift Right Arithmetic Immediate (RRR), pg. 527. +:srai ar, at, u5_8_11_20 is op2_1_3 = 0b001 & u5_8_11_20 & op1 = 0b0001 & ar & at & op0 = 0 { ar = at s>> u5_8_11_20; } -# SRC - Shift Right Combined, pg. 528. +# SRC - Shift Right Combined (RRR), pg. 528. :src ar, as, at is op2 = 0b1000 & op1 = 0b0001 & ar & as & at & op0 = 0 { local s64:8 = zext(as); local t64:8 = zext(at); @@ -1218,102 +1219,102 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ar = shifted:4; } -# SRL - Shift Right Logical, pg. 529. +# SRL - Shift Right Logical (RRR), pg. 529. :srl ar, at is op2 = 0b1001 & op1 = 0b0001 & ar & as = 0 & at & op0 = 0 { ar = at >> SAR; } -# SRLI - Shift Right Logical Immediate, pg. 530. -:srli ar, at, u4_8_11 is op2 = 0b0100 & op1 = 0b0001 & ar & u4_8_11 & at & op0 = 0 { - ar = at >> u4_8_11; +# SRLI - Shift Right Logical Immediate (RRR), pg. 530. +:srli ar, at, op_s is op2 = 0b0100 & op1 = 0b0001 & ar & op_s & at & op0 = 0 { + ar = at >> op_s; } -# SSA8B - Set Shift Amount for BE Byte Shift, pg. 531. +# SSA8B - Set Shift Amount for BE Byte Shift (RRR), pg. 531. :ssa8b as is op2 = 0b0100 & op1 = 0 & ar = 0b0011 & as & at = 0 & op0 = 0 { local lsa:4 = (as&3)*8; SAR = 32 - lsa; } -# SSA8L - Set Shift Amount for LE Byte Shift, pg. 532. +# SSA8L - Set Shift Amount for LE Byte Shift (RRR), pg. 532. :ssa8l as is op2 = 0b0100 & op1 = 0 & ar = 0b0010 & as & at = 0 & op0 = 0 { local rsa:4 = (as & 3)*8; SAR = rsa; } -# SSAI - Set Shift Amount Immediate, pg. 533. -:ssai u5_8_11_4 is op2 = 0b0100 & op1 = 0 & ar = 0b0100 & u5_8_11_4 & u3_5_7 = 0 & op0 = 0 { +# SSAI - Set Shift Amount Immediate (RRR), pg. 533. +:ssai u5_8_11_4 is op2 = 0b0100 & op1 = 0 & ar = 0b0100 & u5_8_11_4 & op_t_1_3 = 0 & op0 = 0 { SAR = u5_8_11_4; } -# SSI - Store Single Immediate, pg. 534. -:ssi ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b0100 & as & ft & op0 = 0b0011 { - local addr:4 = as + u10_16_23_sb2; +# SSI - Store Single Immediate (RRI8), pg. 534. +:ssi ft, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b0100 & as & ft & op0 = 0b0011 { + local addr:4 = as + ri8_i8_sh2; *:4 addr = ft; } -# SSIU - Store Single Immediate with Update, pg. 536. -:ssiu ft, as, u10_16_23_sb2 is u10_16_23_sb2 & ar = 0b1100 & as & ft & op0 = 0b0011 { - local addr:4 = as + u10_16_23_sb2; +# SSIU - Store Single Immediate with Update (RRI8), pg. 536. +:ssiu ft, as, ri8_i8_sh2 is ri8_i8_sh2 & ar = 0b1100 & as & ft & op0 = 0b0011 { + local addr:4 = as + ri8_i8_sh2; *:4 addr = ft; as = addr; } -# SSL - Set Shift Amount for Left Shift, pg. 538. +# SSL - Set Shift Amount for Left Shift (RRR), pg. 538. :ssl as is op2 = 0b0100 & op1 = 0 & ar = 0b0001 & as & at = 0 & op0 = 0 { SAR = 32 - (as & 0x1f); } -# SSR - Set Shift Amount for Right Shift, pg. 539. +# SSR - Set Shift Amount for Right Shift (RRR), pg. 539. :ssr as is op2 = 0b0100 & op1 = 0 & ar = 0 & as & at = 0 & op0 = 0 { SAR = (as & 0x1f); } -# SSX - Store Single Indexed, pg. 540. +# SSX - Store Single Indexed (RRR), pg. 540. :ssx fr, as, at is op2 = 0b0100 & op1 = 0b1000 & fr & as & at & op0 = 0 { local addr:4 = as+at; *:4 addr = fr; } -# SSXU - Store Single Indexed with Update, pg. 541. +# SSXU - Store Single Indexed with Update (RRR), pg. 541. :ssxu fr, as, at is op2 = 0b0101 & op1 = 0b1000 & fr & as & at & op0 = 0 { local addr:4 = as+at; *:4 addr = fr; as = addr; } -# SUB - Subtract, pg. 542. +# SUB - Subtract (RRR), pg. 542. :sub ar, as, at is op2 = 0b1100 & op1 = 0 & ar & as & at & op0 = 0 { ar = as - at; } -# SUB.S - Subtract Single, pg. 543. +# SUB.S - Subtract Single (RRR), pg. 543. :sub.s fr, fs, ft is op2 = 0b0001 & op1 = 0b1010 & fr & fs & ft & op0 = 0 { fr = fs f- ft; } -# SUBX2 - Subtract with Shift by 1, pg. 544. +# SUBX2 - Subtract with Shift by 1 (RRR), pg. 544. :subx2 ar, as, at is op2 = 0b1101 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 1) - at; } -# SUBX4 - Subtract with Shift by 2, pg. 545. +# SUBX4 - Subtract with Shift by 2 (RRR), pg. 545. :subx4 ar, as, at is op2 = 0b1110 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 2) - at; } -# SUBX8 - Subtract with Shift by 3, pg. 546. +# SUBX8 - Subtract with Shift by 3 (RRR), pg. 546. :subx8 ar, as, at is op2 = 0b1111 & op1 = 0 & ar & as & at & op0 = 0 { ar = (as << 3) - at; } -# SYSCALL - System Call, pg. 547. +# SYSCALL - System Call (RRR), pg. 547. :syscall is op2 = 0 & op1 = 0 & ar = 0b0101 & as = 0 & at = 0 & op0 = 0 { syscall(); } -# TRUNC.S - Truncate Single to Fixed, pg. 548 -:trunc.s ar, fs, u4_4_7 is op2 = 0b1001 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = 1 << u4_4_7; +# TRUNC.S - Truncate Single to Fixed (RRR), pg. 548 +:trunc.s ar, fs, op_t is op2 = 0b1001 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = 1 << op_t; local result = fs f* int2float(scale); isNan:1 = nan(result); if (isNan) goto ; @@ -1326,36 +1327,36 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist } -# UEQ.S - Compare Single Unordered or Equal, pg. 549. +# UEQ.S - Compare Single Unordered or Equal (RRR), pg. 549. :ueq.s br, fs, ft is op2 = 0b0011 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = nan(fs) || nan(ft) || fs f== ft; } -# UFLOAT.S - Convert Unsigned Fixed to Single, pg. 550. -:ufloat.s fr, as, u4_4_7 is op2 = 0b1101 & op1 = 0b1010 & fr & as & u4_4_7 & op0 = 0 { +# UFLOAT.S - Convert Unsigned Fixed to Single (RRR), pg. 550. +:ufloat.s fr, as, op_t is op2 = 0b1101 & op1 = 0b1010 & fr & as & op_t & op0 = 0 { local tmp:8 = zext(as); - local scale:4 = 1 << u4_4_7; + local scale:4 = 1 << op_t; fr = int2float(tmp) f/ int2float(scale); } -# ULE.S - Compare Single Unordered or Less Than or Equal, pg. 551. +# ULE.S - Compare Single Unordered or Less Than or Equal (RRR), pg. 551. :ule.s br, fs, ft is op2 = 0b0111 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = nan(fs) || nan(ft) || fs f<= ft; } -# ULT.S - Compare Single Unordered or Less Than, pg. 552. +# ULT.S - Compare Single Unordered or Less Than (RRR), pg. 552. :ult.s br, fs, ft is op2 = 0b0101 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = nan(fs) || nan(ft) || fs f< ft; } -# UN.S - Compare Single Unordered, pg. 554. +# UN.S - Compare Single Unordered (RRR), pg. 554. :un.s br, fs, ft is op2 = 0b0001 & op1 = 0b1011 & br & fs & ft & op0 = 0 { br = nan(fs) || nan(ft); } -# UTRUNC.S - Truncate Single to Fixed Unsigned, pg. 555. -:utrunc.s ar, fs, u4_4_7 is op2 = 0b1110 & op1 = 0b1010 & ar & fs & u4_4_7 & op0 = 0 { - local scale:4 = int2float(1:2 << u4_4_7:2); +# UTRUNC.S - Truncate Single to Fixed Unsigned (RRR), pg. 555. +:utrunc.s ar, fs, op_t is op2 = 0b1110 & op1 = 0b1010 & ar & fs & op_t & op0 = 0 { + local scale:4 = int2float(1:2 << op_t:2); local tmp:8 = trunc(fs f* scale); local posof = nan(fs) || (tmp >> 16) != 0; local negof = tmp s< 0; @@ -1363,73 +1364,73 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ar = zext(posof)*0xffffffff + zext(negof)*0x80000000 + zext(noof)*tmp:4; } -# WAITI - Wait Interrupt, pg. 556. -:waiti u4_8_11 is op2 = 0 & op1 = 0 & ar = 0b0111 & u4_8_11 & at = 0 & op0 = 0 { - waiti(u4_8_11:4); +# WAITI - Wait Interrupt (RRR), pg. 556. +:waiti op_s is op2 = 0 & op1 = 0 & ar = 0b0111 & op_s & at = 0 & op0 = 0 { + waiti(op_s:4); } -# WDTLB - Write Data TLB Entry, pg. 557. +# WDTLB - Write Data TLB Entry (RRR), pg. 557. :wdtlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b1110 & as & at & op0 = 0 { wdtlb(as, at); } -# WER - Write External Register, pg. 558. +# WER - Write External Register (RRR), pg. 558. :wer as, at is op2 = 0b0100 & op1 = 0 & ar = 0b0111 & as & at & op0 = 0 { wer(as, at); } -# WFR - Move AR to FR, pg. 559. +# WFR - Move AR to FR (RRR), pg. 559. :wfr fr, as is op2 = 0b1111 & op1 = 0b1010 & fr & as & at = 0b0101 & op0 = 0 { fr = as; } -# WITLB - Write Instruction TLB Entry, pg. 560. +# WITLB - Write Instruction TLB Entry (RRR), pg. 560. :witlb at, as is op2 = 0b0101 & op1 = 0 & ar = 0b0110 & as & at & op0 = 0 { witlb(as, at); } -# WSR - Write Special Register, pg. 561. +# WSR - Write Special Register (RRR), pg. 561. :wsr at, sr is op2 = 0b0001 & op1 = 0b0011 & sr & at & op0 = 0 { wsr(sr:1, at); } -# WUR - Write User Register, pg. 563. +# WUR - Write User Register (RSR), pg. 563. :wur at, sr is op2 = 0b1111 & op1 = 0b0011 & sr & at & op0 = 0 { wur(sr:1, at); } -# XOR - Bitwise Exclusive Or, pg. 564. +# XOR - Bitwise Exclusive Or (RRR), pg. 564. :xor ar, as, at is op2 = 0b0011 & op1 = 0 & ar & as & at & op0 = 0 { ar = as ^ at; } -# XORB - Boolean Exclusive Or, pg. 565. +# XORB - Boolean Exclusive Or (RRR), pg. 565. :xorb br, bs, bt is op2 = 0b0100 & op1 = 0b0010 & br & bs & bt & op0 = 0 { br = bs ^^ bt; } -# XSR - Exchange Special Register, pg. 566. +# XSR - Exchange Special Register (RSR), pg. 566. :xsr at, sr is op2 = 0b0110 & op1 = 0b0001 & sr & at & op0 = 0 { at = xsr(sr:1, at); } ## MAC16 option ## -# LDDEC - Load with Autodecrement, pg. 386. -:lddec "MAC16_REGS[" mw_12_13 "]", as is op2 = 0b1001 & op1 = 0 & u2_14_15 = 0 & mw_12_13 & as & at = 0 & op0 = 0b0100 { +# LDDEC - Load with Autodecrement (RRR), pg. 386. +:lddec "MAC16_REGS[" mw "]", as is op2 = 0b1001 & op1 = 0 & op_r_2_2 = 0 & mw & as & at = 0 & op0 = 0b0100 { local ptr:4 = as - 4; - mw_12_13 = *:4 ptr; + mw = *:4 ptr; as = ptr; } -# LDINC - Load with Autoincrement, pg. 387. -:ldinc "MAC16_REGS[" mw_12_13 "]", as is op2 = 0b1000 & op1 = 0 & u2_14_15 = 0 & mw_12_13 & as & at = 0 & op0 = 0b0100 { +# LDINC - Load with Autoincrement (RRR), pg. 387. +:ldinc "MAC16_REGS[" mw "]", as is op2 = 0b1000 & op1 = 0 & op_r_2_2 = 0 & mw & as & at = 0 & op0 = 0b0100 { local ptr:4 = as + 4; - mw_12_13 = *:4 ptr; + mw = *:4 ptr; as = ptr; } -# MUL.AA.* - Signed Multiply, pg. 431. +# MUL.AA.* - Signed Multiply (RRR), pg. 431. :mul.aa.ll as, at is op2 = 0x7 & op1 = 0x4 & ar = 0 & as & at & op0 = 0x4 { tm1:2 = as:2; tm2:2 = at:2; @@ -1461,104 +1462,104 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = sext(M1:2) * sext(M2:2); } -# MUL.AD.* - Signed Multiply, pg. 432. -:mul.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +# MUL.AD.* - Signed Multiply (RRR), pg. 432. +:mul.ad.ll as, my is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as:2; - tm2:2 = m2m3_6_6:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.hl as, my is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as(2); - tm2:2 = m2m3_6_6:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.lh as, my is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as:2; - tm2:2 = m2m3_6_6(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.hh as, my is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as(2); - tm2:2 = m2m3_6_6(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -# MUL.AD.* - Signed Multiply, pg. 433. -:mul.da.ll m0m1_14_14, at is op2 = 0x6 & at & op1 = 0x4 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; +# MUL.AD.* - Signed Multiply (RRR), pg. 433. +:mul.da.ll mx, at is op2 = 0x6 & at & op1 = 0x4 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op0 = 0x4 { + tm1:2 = mx:2; tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.da.hl m0m1_14_14, at is op2 = 0x6 & op1 = 0x5 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; +:mul.da.hl mx, at is op2 = 0x6 & op1 = 0x5 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx:2; tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.da.lh m0m1_14_14, at is op2 = 0x6 & op1 = 0x6 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); +:mul.da.lh mx, at is op2 = 0x6 & op1 = 0x6 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx(2); tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.da.hh m0m1_14_14, at is op2 = 0x6 & op1 = 0x7 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); +:mul.da.hh mx, at is op2 = 0x6 & op1 = 0x7 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx(2); tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -# MUL.AD.* - Signed Multiply, pg. 434. -:mul.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x4 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6:2; +# MUL.AD.* - Signed Multiply (RRR), pg. 434. +:mul.dd.ll mx, my is op2 = 0x2 & op1 = 0x4 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x5 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6:2; +:mul.dd.hl mx, my is op2 = 0x2 & op1 = 0x5 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx(2); + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x6 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6(2); +:mul.dd.lh mx, my is op2 = 0x2 & op1 = 0x6 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx:2; + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x7 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6(2); +:mul.dd.hh mx, my is op2 = 0x2 & op1 = 0x7 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -# MULA.AA.* - Signed Multiply, pg. 431. +# MULA.AA.* - Signed Multiply (RRR), pg. 431. :mula.aa.ll as, at is op2 = 0x7 & op1 = 0x8 & ar = 0 & as & at & op0 = 0x4 { tm1:2 = as:2; tm2:2 = at:2; @@ -1590,281 +1591,281 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.ll as, my is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as:2; - tm2:2 = m2m3_6_6:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.hl as, my is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as(2); - tm2:2 = m2m3_6_6:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xa & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.lh as, my is op2 = 0x3 & op1 = 0xa & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as:2; - tm2:2 = m2m3_6_6(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xb & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.hh as, my is op2 = 0x3 & op1 = 0xb & ar = 0 & as & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { tm1:2 = as(2); - tm2:2 = m2m3_6_6(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.da.ll m0m1_14_14, at is op2 = 0x6 & at & op1 = 0x8 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; +:mula.da.ll mx, at is op2 = 0x6 & at & op1 = 0x8 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op0 = 0x4 { + tm1:2 = mx:2; tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.da.hl m0m1_14_14, at is op2 = 0x6 & op1 = 0x9 & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; +:mula.da.hl mx, at is op2 = 0x6 & op1 = 0x9 & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx:2; tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.da.lh m0m1_14_14, at is op2 = 0x6 & op1 = 0xa & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); +:mula.da.lh mx, at is op2 = 0x6 & op1 = 0xa & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx(2); tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.da.hh m0m1_14_14, at is op2 = 0x6 & op1 = 0xb & as = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & at & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); +:mula.da.hh mx, at is op2 = 0x6 & op1 = 0xb & as = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & at & op0 = 0x4 { + tm1:2 = mx(2); tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x8 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6:2; +:mula.dd.ll mx, my is op2 = 0x2 & op1 = 0x8 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x9 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6:2; +:mula.dd.hl mx, my is op2 = 0x2 & op1 = 0x9 & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx(2); + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xa & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6(2); +:mula.dd.lh mx, my is op2 = 0x2 & op1 = 0xa & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx:2; + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xb & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6(2); +:mula.dd.hh mx, my is op2 = 0x2 & op1 = 0xb & ar = 0 & op_r_3 = 0 & op_r_0_2 = 0 & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { + tm1:2 = mx(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -# Signed Mult/Accum, Ld/Autodec MULA.DA.*.LDDEC, pg. 441. -:mula.da.ll.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & at & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 { +# Signed Mult/Accum, Ld/Autodec MULA.DA.*.LDDEC (RRR), pg. 441. +:mula.da.ll.lddec mw, as, mx, at is op2 = 0x5 & at & op1 = 0x8 & as & op_r_3 = 0 & mw & mx & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14:2; + tm1:2 = mx:2; tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hl.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.hl.lddec mw, as, mx, at is op2 = 0x5 & op1 = 0x9 & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14:2; + tm1:2 = mx:2; tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.lh.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.lh.lddec mw, as, mx, at is op2 = 0x5 & op1 = 0xa & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14(2); + tm1:2 = mx(2); tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hh.lddec mw_12_13, as, m0m1_14_14, at is op2 = 0x5 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.hh.lddec mw, as, mx, at is op2 = 0x5 & op1 = 0xb & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14(2); + tm1:2 = mx(2); tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -# Signed Mult/Accum, Ld/Autoinc MULA.DA.*.LDINC, pg. 443. -:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & at & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 { +# Signed Mult/Accum, Ld/Autoinc MULA.DA.*.LDINC (RRR), pg. 443. +:mula.da.ll.ldinc mw, as, mx, at is op2 = 0x4 & at & op1 = 0x8 & as & op_r_3 = 0 & mw & mx & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14:2; + tm1:2 = mx:2; tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.hl.ldinc mw, as, mx, at is op2 = 0x4 & op1 = 0x9 & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14:2; + tm1:2 = mx:2; tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.lh.ldinc mw, as, mx, at is op2 = 0x4 & op1 = 0xa & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14(2); + tm1:2 = mx(2); tm2:2 = at:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, at is op2 = 0x4 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & at & op0 = 0x4 { +:mula.da.hh.ldinc mw, as, mx, at is op2 = 0x4 & op1 = 0xb & as & op_r_3 = 0 & mw & mx & at & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14(2); + tm1:2 = mx(2); tm2:2 = at(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -# Signed Mult/Accum, Ld/Autodec MULA.DD.*.LDDEC, pg. 446. -:mula.dd.ll.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 { +# Signed Mult/Accum, Ld/Autodec MULA.DD.*.LDDEC (RRR), pg. 446. +:mula.dd.ll.lddec mw, as, mx, my is op2 = 0x1 & op1 = 0x8 & as & op_r_3 = 0 & op_t_3 = 0 & op_t_0_2 = 0 & my & mw & mx & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6:2; + tm1:2 = mx:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.dd.hl.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.hl.lddec mw, as, mx, my is op2 = 0x1 & op1 = 0x9 & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6(2); + tm1:2 = mx:2; + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.dd.lh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.lh.lddec mw, as, mx, my is op2 = 0x1 & op1 = 0xa & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6:2; + tm1:2 = mx(2); + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.dd.hh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.hh.lddec mw, as, mx, my is op2 = 0x1 & op1 = 0xb & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as - 4; - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6(2); + tm1:2 = mx(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -# Signed Mult/Accum, Ld/Autoinc MULA.DD.*.LDINC, pg. 448. -:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +# Signed Mult/Accum, Ld/Autoinc MULA.DD.*.LDINC (RRR), pg. 448. +:mula.da.ll.ldinc mw, as, mx, my is op2 = 0x0 & op1 = 0x8 & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6:2; + tm1:2 = mx:2; + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.hl.ldinc mw, as, mx, my is op2 = 0x0 & op1 = 0x9 & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14:2; - tm2:2 = m2m3_6_6(2); + tm1:2 = mx:2; + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.lh.ldinc mw, as, mx, my is op2 = 0x0 & op1 = 0xa & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6:2; + tm1:2 = mx(2); + tm2:2 = my:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.hh.ldinc mw, as, mx, my is op2 = 0x0 & op1 = 0xb & as & op_r_3 = 0 & mw & mx & op_t_3 = 0 & op_t_0_2 = 0 & my & op0 = 0x4 { local vaddr:4 = as + 4; - tm1:2 = m0m1_14_14(2); - tm2:2 = m2m3_6_6(2); + tm1:2 = mx(2); + tm2:2 = my(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); as = vaddr; - mw_12_13 = *:4 vaddr; + mw = *:4 vaddr; } -# UMUL.AA.* - Unsigned Multiply, pg. 553. +# UMUL.AA.* - Unsigned Multiply (RRR), pg. 553. :umul.aa.ll as, at is op2 = 0x7 & op1 = 0x0 & ar = 0 & as & at & op0 = 0x4 { tm1:2 = as:2; tm2:2 = at:2; @@ -1898,9 +1899,9 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ## Loop Option ## -LoopOffset8: loc is u8_16_23 [ loc = inst_start + u8_16_23 + 4; ] { export *:4 loc; } +LoopOffset8: loc is ri8_i8 [ loc = inst_start + ri8_i8 + 4; ] { export *:4 loc; } -# LOOP - Loop, pg. 392. +# LOOP - Loop (BRI8), pg. 392. :loop as, LoopOffset8 is LoopOffset8 & ar = 8 & as & at = 0b0111 & op0 = 6 [ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] { LCOUNT = as - 1; @@ -1908,7 +1909,7 @@ LoopOffset8: loc is u8_16_23 [ loc = inst_start + u8_16_23 + 4; ] { export *:4 l LEND = &LoopOffset8; } -# LOOPGTZ - Loop if Greater Than Zero, pg. 394. +# LOOPGTZ - Loop if Greater Than Zero (BRI8), pg. 394. :loopgtz as, LoopOffset8 is LoopOffset8 & ar = 0b1010 & as & at = 0b0111 & op0 = 0b0110 [ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] { LCOUNT = as - 1; @@ -1917,7 +1918,7 @@ LoopOffset8: loc is u8_16_23 [ loc = inst_start + u8_16_23 + 4; ] { export *:4 l if (as s<= 0) goto LoopOffset8; } -# LOOPNEZ - Loop if Not Equal Zero, pg. 396. +# LOOPNEZ - Loop if Not Equal Zero (BRI8), pg. 396. :loopnez as, LoopOffset8 is LoopOffset8 & ar = 0b1001 & as & at = 0b0111 & op0 = 0b0110 [ loopMode=1; loopEnd = 1; globalset(LoopOffset8, loopEnd); ] { LCOUNT = as - 1; diff --git a/Ghidra/Processors/Xtensa/data/languages/xtensaMain.sinc b/Ghidra/Processors/Xtensa/data/languages/xtensaMain.sinc index 55a1e2e25d..6aee9c3ae7 100644 --- a/Ghidra/Processors/Xtensa/data/languages/xtensaMain.sinc +++ b/Ghidra/Processors/Xtensa/data/languages/xtensaMain.sinc @@ -87,15 +87,15 @@ attach variables [ br bs bt ] [ # bits are named foo_LL.LM_ML.MM, where LL is the least significant bits of the least # singificant operand half, LM the most significant bits of the least significant operand half, etc. -attach variables [ mw_12_13 ] [ +attach variables [ mw ] [ M0 M1 M2 M3 ]; -attach variables [ m2m3_6_6 ] [ +attach variables [ my ] [ M2 M3 ]; -attach variables [ m0m1_14_14 ] [ +attach variables [ mx ] [ M0 M1 ]; @@ -184,62 +184,62 @@ define pcodeop xsr; # bits are named foo_LL_LM_ML_MM, where LL is the least significant bits of the least # singificant operand half, LM the most significant bits of the least significant operand half, etc. -srel_16_23: rel is s8_16_23 [ rel = inst_start + s8_16_23 + 4; ] { export *:4 rel; } +ri8_srel: rel is ri8_si8 [ rel = inst_start + ri8_si8 + 4; ] { export *:4 rel; } -srel_12_23: rel is s12_12_23 [ rel = inst_start + s12_12_23 + 4; ] { export *:4 rel; } +bri12_srel: rel is bri12_si12 [ rel = inst_start + bri12_si12 + 4; ] { export *:4 rel; } -srel_6_23: rel is s8_6_23 [ rel = inst_start + s8_6_23 + 4; ] { export *:4 rel; } - -urel_12_15_4_5: rel is n_u2_4_5 & n_u4_12_15 [ - rel = inst_start + ((n_u2_4_5 << 4) | n_u4_12_15) + 4; +ri6_rel: rel is ri6_i6_4_2 & ri6_i6_0_4 [ + rel = inst_start + ((ri6_i6_4_2 << 4) | ri6_i6_0_4) + 4; ] { export *:4 rel; } -srel_6_23_sb2: rel is s8_6_23 [ - rel = (inst_start & ~3) + ( s8_6_23 << 2 ) + 4; +call_srel: rel is call_o18 [ rel = inst_start + call_o18 + 4; ] { export *:4 rel; } + +call_srel_sh2: rel is call_o18 [ + rel = (inst_start & ~3) + ( call_o18 << 2 ) + 4; ] { export *:4 rel; } -srel_8_23_oex_sb2: rel is u16_8_23 [ - rel = ((inst_start + 3) & ~3) + ((u16_8_23 | 0xffff0000) << 2); +srel_oex_sh2: rel is ri16_i16 [ + rel = ((inst_start + 3) & ~3) + ((ri16_i16 | 0xffff0000) << 2); ] { export *:4 rel; } # Immediates split across the instruction. -u5_8_11_20: tmp is u1_20 & u4_8_11 [ tmp = (u1_20 << 4) | u4_8_11; ] { export *[const]:4 tmp; } -u5_4_7_20: tmp is u1_20 & u4_4_7 [ tmp = 32 - ((u1_20 << 4) | u4_4_7); ] { export *[const]:4 tmp; } -u5_8_11_16: tmp is u1_16 & u4_8_11 [ tmp = (u1_16 << 4) | u4_8_11; ] { export *[const]:4 tmp; } -u5_4_7_12: tmp is u1_12 & u4_4_7 [ tmp = (u1_12 << 4) | u4_4_7; ] { export *[const]:4 tmp; } -u5_8_11_4: tmp is u1_4 & u4_8_11 [ tmp = (u1_4 << 4) | u4_8_11; ] { export *[const]:4 tmp; } +u5_8_11_20: tmp is op2_0 & op_s [ tmp = (op2_0 << 4) | op_s; ] { export *[const]:4 tmp; } +u5_4_7_20: tmp is op2_0 & op_t [ tmp = 32 - ((op2_0 << 4) | op_t); ] { export *[const]:4 tmp; } +u5_8_11_16: tmp is op1_0 & op_s [ tmp = (op1_0 << 4) | op_s; ] { export *[const]:4 tmp; } +u5_4_7_12: tmp is op_r_0 & op_t [ tmp = (op_r_0 << 4) | op_t; ] { export *[const]:4 tmp; } +u5_8_11_4: tmp is op_t_0 & op_s [ tmp = (op_t_0 << 4) | op_s; ] { export *[const]:4 tmp; } # Signed 12-bit (extended to 16) immediate, used by MOVI. -s16_16_23_8_11: tmp is s4_8_11 & u8_16_23 [ - tmp = (s4_8_11 << 8) | u8_16_23; +movi_si16: tmp is op_st_i8 & ri8_i8 [ + tmp = (op_st_i8 << 8) | ri8_i8; ] { export *[const]:2 tmp; } # An “asymmetric” immediate from -32..95, used by MOVI.N. -n_s8_12_15_4_6_asymm: tmp is n_s3_4_6 & n_s4_12_15 [ - tmp = ((((n_s3_4_6 & 7) << 4) | (n_s4_12_15 & 15)) | - ((((n_s3_4_6 >> 2) & 1) & ((n_s3_4_6 >> 1) & 1)) << 7)); +movin_si8: tmp is n_op_s_0_3 & ri6_si6_0_4 [ + tmp = ((((n_op_s_0_3 & 7) << 4) | (ri6_si6_0_4 & 15)) | + ((((n_op_s_0_3 >> 2) & 1) & ((n_op_s_0_3 >> 1) & 1)) << 7)); ] { export *[const]:1 tmp; } # Immediates shifted or with offset. -s16_16_23_sb8: tmp is s8_16_23 [ tmp = s8_16_23 << 8; ] { export *[const]:4 tmp; } -u15_12_23_sb3: tmp is u12_12_23 [ tmp = u12_12_23 << 3; ] { export *[const]:4 tmp; } -u10_16_23_sb2: tmp is u8_16_23 [ tmp = u8_16_23 << 2; ] { export *[const]:4 tmp; } -u9_16_23_sb1: tmp is u8_16_23 [ tmp = u8_16_23 << 1; ] { export *[const]:4 tmp; } -u5_20_23_plus1: tmp is u4_20_23 [ tmp = u4_20_23 + 1; ] { export *[const]:4 tmp; } -u8_20_23_sb4: tmp is u4_20_23 [ tmp = u4_20_23 << 4; ] { export *[const]:4 tmp; } -u5_4_7_plus7: tmp is u4_4_7 [ tmp = u4_4_7 + 7; ] { export *[const]:4 tmp; } +ri8_si8_sh8: tmp is ri8_si8 [ tmp = ri8_si8 << 8; ] { export *[const]:4 tmp; } +bri12_i12_sh3: tmp is bri12_i12 [ tmp = bri12_i12 << 3; ] { export *[const]:4 tmp; } +ri8_i8_sh2: tmp is ri8_i8 [ tmp = ri8_i8 << 2; ] { export *[const]:4 tmp; } +u9_16_23_sb1: tmp is ri8_i8 [ tmp = ri8_i8 << 1; ] { export *[const]:4 tmp; } +u5_20_23_plus1: tmp is op2 [ tmp = op2 + 1; ] { export *[const]:4 tmp; } +u8_20_23_sb4: tmp is op2 [ tmp = op2 << 4; ] { export *[const]:4 tmp; } +u5_4_7_plus7: tmp is op_t [ tmp = op_t + 7; ] { export *[const]:4 tmp; } -n_u6_12_15_sb2: tmp is n_u4_12_15 [ tmp = n_u4_12_15 << 2; ] { export *[const]:4 tmp; } +n_u6_12_15_sb2: tmp is ri6_i6_0_4 [ tmp = ri6_i6_0_4 << 2; ] { export *[const]:4 tmp; } # One-extended. FIXME: Verify this. Only used by [LS]32E (window extension), which aren’t yet # implemented. -s5_12_15_oex: tmp is u4_12_15 [ tmp = (u4_12_15 << 2) - 64; ] { export *[const]:2 tmp; } +s5_12_15_oex: tmp is op_r [ tmp = (op_r << 2) - 64; ] { export *[const]:2 tmp; } # Some 4-bit immediates with mappings that can’t be (easily) expressed in a single disassembly action. # n_u4_4_7 with 0 being -1, used by ADDI.N. -n_s4_4_7_nozero: tmp is n_u4_4_7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; } -n_s4_4_7_nozero: tmp is n_u4_4_7 [ tmp = n_u4_4_7+0; ] { export *[const]:4 tmp; } +n_s4_4_7_nozero: tmp is n_op_s = 0 [ tmp = -1; ] { export *[const]:4 tmp; } +n_s4_4_7_nozero: tmp is n_op_s [ tmp = n_op_s+0; ] { export *[const]:4 tmp; } # B4CONST(ar) (Branch Immediate) encodings, pg. 41 f. r_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; } diff --git a/Ghidra/Processors/Xtensa/data/languages/xtensa_depbits.sinc b/Ghidra/Processors/Xtensa/data/languages/xtensa_depbits.sinc index ccf799116e..6cf3037e86 100644 --- a/Ghidra/Processors/Xtensa/data/languages/xtensa_depbits.sinc +++ b/Ghidra/Processors/Xtensa/data/languages/xtensa_depbits.sinc @@ -2,9 +2,9 @@ # This is broken out because it collides with the floating point instructions. It is not included by default # DEPBITS - Add (RRR), pg. 394. -shiftimm: simm is u4_20_23 & u1_16 [ simm = u1_16 << 4 + u4_20_23; ] { export *[const]:4 simm; } -:depbits as, at, shiftimm, u4_12_15 is u3_17_19=0x5 & u4_12_15 & as & at & op0 = 0 & shiftimm { - mask:4 = (1 << u4_12_15) - 1; +shiftimm: simm is op2 & op1_0 [ simm = op1_0 << 4 + op2; ] { export *[const]:4 simm; } +:depbits as, at, shiftimm, u4_12_15 is op1_1_3=0x5 & op_r & as & at & op0 = 0 & shiftimm { + mask:4 = (1 << op_r) - 1; bits:4 = (as & mask) << shiftimm; mask = mask << shiftimm; at = (~mask & at) | bits;