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nxphlite-v1 Changes to provides USB clocking

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Support the PX4 contrib to upstream Nuttx for SIM. MCG and PMC
  clocking. Now sets the USB clock correctly.

  Refit in FLASH
This commit is contained in:
David Sidrane
2017-02-28 15:54:42 -10:00
committed by Daniel Agar
parent 73944daf75
commit fe3398300b
2 changed files with 27 additions and 1 deletions
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cmake/configs/nuttx_nxphlite-v1_default.cmake
+1 -1
View File
@@ -95,7 +95,7 @@ set(config_module_list
modules/mavlink
modules/gpio_led
##NO CAN YET modules/uavcan
modules/land_detector
##SPACE modules/land_detector
#
# Estimation modules (EKF/ SO3 / other filters)
nuttx-configs/nxphlite-v1/include/board.h
+26
View File
@@ -84,6 +84,11 @@
#define BOARD_PRDIV 4 /* PLL External Reference Divider */
#define BOARD_VDIV 30 /* PLL VCO Divider (frequency multiplier) */
/* Define additional MCG_C2 Setting */
#define BOARD_MCG_C2_FCFTRIM 0 /* Do not enable FCFTRIM */
#define BOARD_MCG_C2_LOCRE0 MCG_C2_LOCRE0 /* Enable reset on loss of clock */
#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV)
#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV)
#define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ
@@ -100,6 +105,27 @@
#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3)
#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4)
/* Use BOARD_MCG_FREQ as the output SIM_SOPT2 MUX selected by
* SIM_SOPT2[PLLFLLSEL]
*/
#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK
#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ
/* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
* SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ]
* 48Mhz = 120Mhz X [(1 + 1) / (4 + 1)]
* 48Mhz = 120Mhz / (4 + 1) * (1 + 1)
*/
#define BOARD_SIM_CLKDIV2_USBFRAC 2
#define BOARD_SIM_CLKDIV2_USBDIV 5
#define BOARD_SIM_CLKDIV2_FREQ (BOARD_SOPT2_FREQ / \
BOARD_SIM_CLKDIV2_USBDIV * \
BOARD_SIM_CLKDIV2_USBFRAC)
#define BOARD_USB_CLKSRC SIM_SOPT2_USBSRC
#define BOARD_USB_FREQ BOARD_SIM_CLKDIV2_FREQ
/* SDHC clocking ********************************************************************/
/* SDCLK configurations corresponding to various modes of operation. Formula is: