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Consolidate the flash patches to fix build (#6850)

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nuttx-patches/workarround_for_flash_data_cache_corruption.patch was
   patching a file patched in nuttx-patches/wip_inflight_to_upstream.patch

   The changes in workarround_for_flash_data_cache_corruption.patch
   will be submitted upstream once refactored (upstream coding style
   compliant and moved to correct location)
This commit is contained in:
David Sidrane
2017-03-20 06:18:23 -10:00
committed by GitHub
parent c9643cb075
commit f2164b135d
2 changed files with 111 additions and 119 deletions
Download Patch File Download Diff File Expand all files Collapse all files
nuttx-patches/wip_inflight_to_upstream.patch
+111 -38
View File
@@ -62,44 +62,6 @@ index 5e2ba73..adda863 100644
/* Wait until the HSI is ready (or until a timeout elapsed) */
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
index 73f1419..9ac38a1 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
@@ -231,12 +231,14 @@ ssize_t up_progmem_erasepage(size_t page)
return -EFAULT;
}
- /* Get flash ready and begin erasing single page */
-
+#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
return -EPERM;
}
+#endif
+
+ /* Get flash ready and begin erasing single page */
stm32_flash_unlock();
@@ -318,12 +320,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
return -EFAULT;
}
- /* Get flash ready and begin flashing */
-
+#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
return -EPERM;
}
+#endif
+
+ /* Get flash ready and begin flashing */
stm32_flash_unlock();
diff --git NuttX/nuttx/drivers/mtd/ramtron.c NuttX/nuttx/drivers/mtd/ramtron.c
index ad448c8..236084f 100644
--- NuttX/nuttx/drivers/mtd/ramtron.c
@@ -681,3 +643,114 @@ index bd42b83..5445c01 100644
if (ret != OK && nretry > 0)
{
diff --git NuttX/nuttx/arch/arm/src/stm32/Kconfig NuttX/nuttx/arch/arm/src/stm32/Kconfig
index b6c0458..d9fb0ae 100644
--- NuttX/nuttx/arch/arm/src/stm32/Kconfig
+++ NuttX/nuttx/arch/arm/src/stm32/Kconfig
@@ -2514,6 +2514,12 @@ config STM32_FLASH_PREFETCH
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
properly and enabling this option may interfere with ADC accuracy.
+config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
+ bool "Enable the workaround to fix flash data cache corruption when reading from one flash bank while writing on other flash bank"
+ default n
+ ---help---
+ See your STM32 errata to check if your STM32 is affected by this problem.
+
choice
prompt "JTAG Configuration"
default STM32_JTAG_DISABLE
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
index 73f1419..9a2e50a 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
@@ -231,12 +231,14 @@ ssize_t up_progmem_erasepage(size_t page)
return -EFAULT;
}
- /* Get flash ready and begin erasing single page */
-
+#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
return -EPERM;
}
+#endif
+
+ /* Get flash ready and begin erasing single page */
stm32_flash_unlock();
@@ -294,6 +296,37 @@ ssize_t up_progmem_ispageerased(size_t page)
return bwritten;
}
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+static void data_cache_disable(void)
+{
+ uint32_t value = getreg32(STM32_FLASH_ACR);
+
+ if (value & FLASH_ACR_DCEN)
+ {
+ value &= ~FLASH_ACR_DCEN;
+ putreg32(value, STM32_FLASH_ACR);
+ }
+}
+
+static void data_cache_enable(void)
+{
+ uint32_t value = getreg32(STM32_FLASH_ACR);
+ if (value & FLASH_ACR_DCEN)
+ {
+ return;
+ }
+
+ /* reset data cache */
+ value |= FLASH_ACR_DCRST;
+ putreg32(value, STM32_FLASH_ACR);
+
+ /* enable data cache */
+ value = getreg32(STM32_FLASH_ACR);
+ value |= FLASH_ACR_DCEN;
+ putreg32(value, STM32_FLASH_ACR);
+}
+#endif
+
ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
{
uint16_t *hword = (uint16_t *)buf;
@@ -318,15 +351,21 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
return -EFAULT;
}
- /* Get flash ready and begin flashing */
-
+#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
return -EPERM;
}
+#endif
+
+ /* Get flash ready and begin flashing */
stm32_flash_unlock();
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+ data_cache_disable();
+#endif
+
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
#if defined(CONFIG_STM32_STM32F40XX)
@@ -358,6 +397,10 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
}
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
+
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+ data_cache_enable();
+#endif
return written;
}
nuttx-patches/workarround_for_flash_data_cache_corruption.patch
-81
View File
@@ -1,81 +0,0 @@
diff --git NuttX/nuttx/arch/arm/src/stm32/Kconfig NuttX/nuttx/arch/arm/src/stm32/Kconfig
index b6c0458649..d9fb0aeaa2 100644
--- NuttX/nuttx/arch/arm/src/stm32/Kconfig
+++ NuttX/nuttx/arch/arm/src/stm32/Kconfig
@@ -2514,6 +2514,12 @@ config STM32_FLASH_PREFETCH
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
properly and enabling this option may interfere with ADC accuracy.
+config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
+ bool "Enable the workaround to fix flash data cache corruption when reading from one flash bank while writing on other flash bank"
+ default n
+ ---help---
+ See your STM32 errata to check if your STM32 is affected by this problem.
+
choice
prompt "JTAG Configuration"
default STM32_JTAG_DISABLE
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
index 73f1419506..fd0b05d624 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
@@ -294,6 +294,37 @@ ssize_t up_progmem_ispageerased(size_t page)
return bwritten;
}
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+static void data_cache_disable(void)
+{
+ uint32_t value = getreg32(STM32_FLASH_ACR);
+
+ if (value & FLASH_ACR_DCEN)
+ {
+ value &= ~FLASH_ACR_DCEN;
+ putreg32(value, STM32_FLASH_ACR);
+ }
+}
+
+static void data_cache_enable(void)
+{
+ uint32_t value = getreg32(STM32_FLASH_ACR);
+ if (value & FLASH_ACR_DCEN)
+ {
+ return;
+ }
+
+ /* reset data cache */
+ value |= FLASH_ACR_DCRST;
+ putreg32(value, STM32_FLASH_ACR);
+
+ /* enable data cache */
+ value = getreg32(STM32_FLASH_ACR);
+ value |= FLASH_ACR_DCEN;
+ putreg32(value, STM32_FLASH_ACR);
+}
+#endif
+
ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
{
uint16_t *hword = (uint16_t *)buf;
@@ -327,6 +358,10 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
stm32_flash_unlock();
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+ data_cache_disable();
+#endif
+
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
#if defined(CONFIG_STM32_STM32F40XX)
@@ -358,6 +393,10 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
}
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
+
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+ data_cache_enable();
+#endif
return written;
}