mirror of
https://github.com/PX4/PX4-Autopilot.git
synced 2026-05-25 16:56:25 +08:00
icm20602: accumulated minor improvements and cleanup
- perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc) - track consecutive errors and trigger full reset if necessary - remove interrupt perf counter and instead only count misses - minor style changes to stay in sync with the other Invensense drivers - read FIFO count along with full transfer as a sanity check
This commit is contained in:
Daniel Agar
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2019 PX4 Development Team. All rights reserved.
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* Copyright (c) 2019-2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -73,21 +73,23 @@ private:
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void exit_and_cleanup() override;
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// Sensor Configuration
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static constexpr float FIFO_SAMPLE_DT{125.f};
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static constexpr uint32_t SAMPLES_PER_TRANSFER{2}; // ensure at least 1 new accel sample per transfer
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static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 8 kHz gyro
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static constexpr float ACCEL_RATE{GYRO_RATE / 2.f}; // 4 kHz accel
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static constexpr float FIFO_SAMPLE_DT{1e6f / 8000.f};
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static constexpr uint32_t SAMPLES_PER_TRANSFER{2}; // ensure at least 1 new accel sample per transfer
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static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 8000 Hz gyro
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static constexpr float ACCEL_RATE{GYRO_RATE / SAMPLES_PER_TRANSFER}; // 4000 Hz accel
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// maximum FIFO samples per transfer is limited to the size of sensor_accel_fifo/sensor_gyro_fifo
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static constexpr uint32_t FIFO_MAX_SAMPLES{math::min(math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(sensor_gyro_fifo_s::x) / sizeof(sensor_gyro_fifo_s::x[0])), sizeof(sensor_accel_fifo_s::x) / sizeof(sensor_accel_fifo_s::x[0]) * (int)(GYRO_RATE / ACCEL_RATE))};
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// Transfer data
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struct FIFOTransferBuffer {
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uint8_t cmd{static_cast<uint8_t>(Register::FIFO_R_W) | DIR_READ};
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uint8_t cmd{static_cast<uint8_t>(Register::FIFO_COUNTH) | DIR_READ};
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uint8_t FIFO_COUNTH{0};
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uint8_t FIFO_COUNTL{0};
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FIFO::DATA f[FIFO_MAX_SAMPLES] {};
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};
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// ensure no struct padding
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static_assert(sizeof(FIFOTransferBuffer) == (1 + FIFO_MAX_SAMPLES *sizeof(FIFO::DATA)));
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static_assert(sizeof(FIFOTransferBuffer) == (3 + FIFO_MAX_SAMPLES *sizeof(FIFO::DATA)));
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struct register_config_t {
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Register reg;
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@@ -110,21 +112,19 @@ private:
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bool DataReadyInterruptConfigure();
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bool DataReadyInterruptDisable();
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bool RegisterCheck(const register_config_t ®_cfg, bool notify = false);
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bool RegisterCheck(const register_config_t ®_cfg);
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uint8_t RegisterRead(Register reg);
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void RegisterWrite(Register reg, uint8_t value);
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void RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits);
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void RegisterSetBits(Register reg, uint8_t setbits) { RegisterSetAndClearBits(reg, setbits, 0); }
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void RegisterClearBits(Register reg, uint8_t clearbits) { RegisterSetAndClearBits(reg, 0, clearbits); }
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uint16_t FIFOReadCount();
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bool FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples);
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bool FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples);
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void FIFOReset();
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bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
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void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
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bool ProcessTemperature(const FIFOTransferBuffer &buffer, const uint8_t samples);
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bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples);
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void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples);
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bool ProcessTemperature(const FIFO::DATA fifo[], const uint8_t samples);
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const spi_drdy_gpio_t _drdy_gpio;
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@@ -136,14 +136,13 @@ private:
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perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO empty")};
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perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO overflow")};
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perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO reset")};
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perf_counter_t _drdy_interval_perf{perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval")};
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perf_counter_t _drdy_missed_perf{nullptr};
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hrt_abstime _reset_timestamp{0};
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hrt_abstime _last_config_check_timestamp{0};
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hrt_abstime _fifo_watermark_interrupt_timestamp{0};
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hrt_abstime _temperature_update_timestamp{0};
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int _failure_count{0};
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px4::atomic<uint8_t> _fifo_read_samples{0};
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px4::atomic<uint32_t> _drdy_fifo_read_samples{0};
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bool _data_ready_interrupt_enabled{false};
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enum class STATE : uint8_t {
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@@ -156,24 +155,23 @@ private:
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STATE _state{STATE::RESET};
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uint16_t _fifo_empty_interval_us{1250}; // default 1250 us / 800 Hz transfer interval
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uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
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uint8_t _fifo_accel_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))};
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uint32_t _fifo_gyro_samples{static_cast<uint32_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
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uint8_t _checked_register{0};
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static constexpr uint8_t size_register_cfg{12};
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register_config_t _register_cfg[size_register_cfg] {
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// Register | Set bits, Clear bits
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{ Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::DEVICE_RESET | PWR_MGMT_1_BIT::SLEEP },
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{ Register::I2C_IF, I2C_IF_BIT::I2C_IF_DIS, 0 },
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{ Register::CONFIG, CONFIG_BIT::FIFO_MODE | CONFIG_BIT::DLPF_CFG_BYPASS_DLPF_8KHZ, 0 },
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{ Register::GYRO_CONFIG, GYRO_CONFIG_BIT::FS_SEL_2000_DPS, GYRO_CONFIG_BIT::FCHOICE_B_8KHZ_BYPASS_DLPF },
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{ Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::ACCEL_FS_SEL_16G, 0 },
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{ Register::ACCEL_CONFIG2, ACCEL_CONFIG2_BIT::ACCEL_FCHOICE_B_BYPASS_DLPF, 0 },
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{ Register::GYRO_CONFIG, GYRO_CONFIG_BIT::FS_SEL_2000_DPS, GYRO_CONFIG_BIT::FCHOICE_B_8KHZ_BYPASS_DLPF },
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{ Register::CONFIG, CONFIG_BIT::FIFO_MODE | CONFIG_BIT::DLPF_CFG_BYPASS_DLPF_8KHZ, Bit7 },
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{ Register::FIFO_WM_TH1, 0, 0 }, // FIFO_WM_TH[9:8]
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{ Register::FIFO_WM_TH2, 0, 0 }, // FIFO_WM_TH[7:0]
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{ Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN, USER_CTRL_BIT::FIFO_RST | USER_CTRL_BIT::SIG_COND_RST },
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{ Register::FIFO_EN, FIFO_EN_BIT::GYRO_FIFO_EN | FIFO_EN_BIT::ACCEL_FIFO_EN, 0 },
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{ Register::INT_PIN_CFG, INT_PIN_CFG_BIT::INT_LEVEL | INT_PIN_CFG_BIT::LATCH_INT_EN | INT_PIN_CFG_BIT::INT_RD_CLEAR, 0 },
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{ Register::INT_ENABLE, 0, INT_ENABLE_BIT::DATA_RDY_INT_EN }
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{ Register::INT_ENABLE, 0, INT_ENABLE_BIT::DATA_RDY_INT_EN },
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{ Register::FIFO_WM_TH1, 0, 0 }, // FIFO_WM_TH[9:8]
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{ Register::FIFO_WM_TH2, 0, 0 }, // FIFO_WM_TH[7:0]
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{ Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN, 0 },
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{ Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::SLEEP },
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{ Register::I2C_IF, I2C_IF_BIT::I2C_IF_DIS, 0 },
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};
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};
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2019 PX4 Development Team. All rights reserved.
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* Copyright (c) 2019-2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -59,39 +59,44 @@ static constexpr uint8_t DIR_READ = 0x80;
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static constexpr uint8_t WHOAMI = 0x12;
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static constexpr float TEMPERATURE_SENSITIVITY = 326.8f; // LSB/C
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static constexpr float TEMPERATURE_OFFSET = 25.f; // C
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static constexpr float TEMPERATURE_SENSITIVITY = 326.8f; // LSB/°C
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static constexpr float TEMPERATURE_OFFSET = 25.f; // °C
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static constexpr float TEMPERATURE_SENSOR_MIN = -40.f; // °C
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static constexpr float TEMPERATURE_SENSOR_MAX = 85.f; // °C
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enum class Register : uint8_t {
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CONFIG = 0x1A,
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GYRO_CONFIG = 0x1B,
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ACCEL_CONFIG = 0x1C,
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ACCEL_CONFIG2 = 0x1D,
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CONFIG = 0x1A,
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GYRO_CONFIG = 0x1B,
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ACCEL_CONFIG = 0x1C,
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ACCEL_CONFIG2 = 0x1D,
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FIFO_EN = 0x23,
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FIFO_EN = 0x23,
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INT_PIN_CFG = 0x37,
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INT_ENABLE = 0x38,
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INT_PIN_CFG = 0x37,
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INT_ENABLE = 0x38,
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TEMP_OUT_H = 0x41,
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TEMP_OUT_L = 0x42,
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TEMP_OUT_H = 0x41,
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TEMP_OUT_L = 0x42,
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FIFO_WM_TH1 = 0x60,
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FIFO_WM_TH2 = 0x61,
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FIFO_WM_TH1 = 0x60,
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FIFO_WM_TH2 = 0x61,
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USER_CTRL = 0x6A,
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PWR_MGMT_1 = 0x6B,
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SIGNAL_PATH_RESET = 0x68,
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I2C_IF = 0x70,
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USER_CTRL = 0x6A,
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PWR_MGMT_1 = 0x6B,
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FIFO_COUNTH = 0x72,
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FIFO_COUNTL = 0x73,
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FIFO_R_W = 0x74,
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WHO_AM_I = 0x75,
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I2C_IF = 0x70,
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FIFO_COUNTH = 0x72,
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FIFO_COUNTL = 0x73,
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FIFO_R_W = 0x74,
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WHO_AM_I = 0x75,
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};
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// CONFIG
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enum CONFIG_BIT : uint8_t {
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// Bit7 - FIFO_WM_TH[9:0] User should ensure that bit 7 of register 0x1A is set to 0 before using this feature
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FIFO_MODE = Bit6, // when the FIFO is full, additional writes will not be written to FIFO
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DLPF_CFG_BYPASS_DLPF_8KHZ = 7, // Rate 8 kHz [2:0]
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@@ -139,8 +144,13 @@ enum INT_PIN_CFG_BIT : uint8_t {
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// INT_ENABLE
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enum INT_ENABLE_BIT : uint8_t {
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FIFO_OFLOW_EN = Bit4,
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DATA_RDY_INT_EN = Bit0
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DATA_RDY_INT_EN = Bit0,
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};
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// SIGNAL_PATH_RESET
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enum SIGNAL_PATH_RESET_BIT : uint8_t {
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ACCEL_RST = Bit1,
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TEMP_RST = Bit0,
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};
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// USER_CTRL
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@@ -155,9 +165,8 @@ enum PWR_MGMT_1_BIT : uint8_t {
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DEVICE_RESET = Bit7,
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SLEEP = Bit6,
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CLKSEL_2 = Bit2,
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CLKSEL_1 = Bit1,
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CLKSEL_0 = Bit0,
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// CLKSEL[2:0]
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CLKSEL_0 = Bit0, // It is required that CLKSEL[2:0] be set to 001 to achieve full gyroscope performance.
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};
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// I2C_IF
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