boards: add NAND flash logging support to KakuteH7v2

- Initialize W25N01GV NAND flash on SPI1 with littlefs. - Enable BOARD_SMALL_FLASH_LOGGING for small flash handling. - Increase logger buffer size for flash write performance.
2026-03-27 01:12:18 +08:00 · 2025-12-19 09:55:11 +13:00
parent 0294d4a794
commit e0af9f4ef4
7 changed files with 79 additions and 22 deletions
--- a/boards/holybro/kakuteh7v2/init/rc.board_defaults
+++ b/boards/holybro/kakuteh7v2/init/rc.board_defaults
@@ -38,5 +38,6 @@ param set-default SYS_DM_BACKEND 1
 # Ignore that there is no SD card
 param set-default COM_ARM_SDCARD 0

-# Disable logging
-param set-default SDLOG_BACKEND 0
+# W25N NAND flash with littlefs (128 MB): larger buffer, auto-rotate
+set LOGGER_BUF 32
+param set-default SDLOG_DIRS_MAX 3
--- a/boards/holybro/kakuteh7v2/nuttx-config/include/board.h
+++ b/boards/holybro/kakuteh7v2/nuttx-config/include/board.h
@@ -99,7 +99,7 @@
 *   PLL1_VCO = (8,000,000 / 1) * 120 = 960 MHz
 *
 *   PLL1P = PLL1_VCO/2  = 960 MHz / 2   = 480 MHz
- *   PLL1Q = PLL1_VCO/4  = 960 MHz / 4   = 240 MHz
+ *   PLL1Q = PLL1_VCO/5  = 960 MHz / 5   = 192 MHz (SPI123 clock, max 200 MHz)
 *   PLL1R = PLL1_VCO/8  = 960 MHz / 8   = 120 MHz
 */

@@ -111,12 +111,12 @@
 #define STM32_PLLCFG_PLL1M       RCC_PLLCKSELR_DIVM1(1)
 #define STM32_PLLCFG_PLL1N       RCC_PLL1DIVR_N1(120)
 #define STM32_PLLCFG_PLL1P       RCC_PLL1DIVR_P1(2)
-#define STM32_PLLCFG_PLL1Q       RCC_PLL1DIVR_Q1(4)
+#define STM32_PLLCFG_PLL1Q       RCC_PLL1DIVR_Q1(5)
 #define STM32_PLLCFG_PLL1R       RCC_PLL1DIVR_R1(8)

 #define STM32_VCO1_FREQUENCY     ((STM32_HSE_FREQUENCY / 1) * 120)
 #define STM32_PLL1P_FREQUENCY    (STM32_VCO1_FREQUENCY / 2)
-#define STM32_PLL1Q_FREQUENCY    (STM32_VCO1_FREQUENCY / 4)
+#define STM32_PLL1Q_FREQUENCY    (STM32_VCO1_FREQUENCY / 5)
 #define STM32_PLL1R_FREQUENCY    (STM32_VCO1_FREQUENCY / 8)

 /* PLL2 */
@@ -227,9 +227,9 @@

 #define STM32_RCC_D3CCIPR_I2C4SRC    RCC_D3CCIPR_I2C4SEL_HSI

-/* SPI123 clock source */
+/* SPI123 clock source - PLL1Q = 192 MHz for W25N NAND flash (max 104 MHz) */

-#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL2
+#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1

 /* SPI45 clock source */

@@ -281,17 +281,17 @@

 #define STM32_SDMMC_INIT_CLKDIV     (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)

-/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div =  PLL1Q/(2*freq)
- * div = 4.8 = 240 / 50, So round up to 5 for default speed 24 MB/s
+/* 25 MHz Max for now, 25 mHz = PLL1Q/(2*div), div = PLL1Q/(2*freq)
+ * PLL1Q = 192 MHz, div = 192 / 50 = 3.84, round up to 4 for 24 MHz
 */

 #if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA)
-#  define STM32_SDMMC_MMCXFR_CLKDIV   (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#  define STM32_SDMMC_MMCXFR_CLKDIV   (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #else
 #  define STM32_SDMMC_MMCXFR_CLKDIV   (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #endif
 #if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA)
-#  define STM32_SDMMC_SDXFR_CLKDIV    (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#  define STM32_SDMMC_SDXFR_CLKDIV    (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #else
 #  define STM32_SDMMC_SDXFR_CLKDIV    (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #endif
--- a/boards/holybro/kakuteh7v2/nuttx-config/include/board_dma_map.h
+++ b/boards/holybro/kakuteh7v2/nuttx-config/include/board_dma_map.h
@@ -33,6 +33,10 @@

 #pragma once

+/* SPI1 DMA for W25N NAND Flash */
+#define DMAMAP_SPI1_RX    DMAMAP_DMA12_SPI1RX_0 /* DMA1 */
+#define DMAMAP_SPI1_TX    DMAMAP_DMA12_SPI1TX_0 /* DMA1 */
+
 #define DMAMAP_SPI4_RX    DMAMAP_DMA12_SPI4RX_1 /* DMA2 */
 #define DMAMAP_SPI4_TX    DMAMAP_DMA12_SPI4TX_1 /* DMA2 */

--- a/boards/holybro/kakuteh7v2/nuttx-config/nsh/defconfig
+++ b/boards/holybro/kakuteh7v2/nuttx-config/nsh/defconfig
@@ -104,6 +104,10 @@ CONFIG_FS_PROCFS_INCLUDE_PROGMEM=y
 CONFIG_FS_PROCFS_MAX_TASKS=64
 CONFIG_FS_PROCFS_REGISTER=y
 CONFIG_FS_ROMFS=y
+CONFIG_FS_LITTLEFS=y
+CONFIG_FS_LITTLEFS_PROGRAM_SIZE_FACTOR=1
+CONFIG_FS_LITTLEFS_READ_SIZE_FACTOR=1
+CONFIG_FS_LITTLEFS_CACHE_SIZE_FACTOR=1
 CONFIG_GRAN=y
 CONFIG_GRAN_INTR=y
 CONFIG_HAVE_CXX=y
@@ -126,7 +130,9 @@ CONFIG_MTD=y
 CONFIG_MTD_BYTE_WRITE=y
 CONFIG_MTD_PARTITION=y
 CONFIG_MTD_PROGMEM=y
-CONFIG_MTD_RAMTRON=y
+# CONFIG_MTD_RAMTRON is not set
+CONFIG_MTD_W25N=y
+CONFIG_W25N_SPIFREQUENCY=104000000
 CONFIG_NAME_MAX=40
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_ARGCAT=y
@@ -135,7 +141,7 @@ CONFIG_NSH_CMDPARMS=y
 CONFIG_NSH_CROMFSETC=y
 CONFIG_NSH_LINELEN=128
 CONFIG_NSH_MAXARGUMENTS=15
-CONFIG_NSH_MMCSDSPIPORTNO=1
+# CONFIG_NSH_MMCSDSPIPORTNO is not set
 CONFIG_NSH_NESTDEPTH=8
 CONFIG_NSH_QUOTE=y
 CONFIG_NSH_ROMFSETC=y
@@ -148,9 +154,6 @@ CONFIG_PREALLOC_TIMERS=50
 CONFIG_PRIORITY_INHERITANCE=y
 CONFIG_PTHREAD_MUTEX_ROBUST=y
 CONFIG_PTHREAD_STACK_MIN=512
-CONFIG_RAMTRON_EMULATE_PAGE_SHIFT=5
-CONFIG_RAMTRON_EMULATE_SECTOR_SHIFT=5
-CONFIG_RAMTRON_SETSPEED=y
 CONFIG_RAM_SIZE=245760
 CONFIG_RAM_START=0x20010000
 CONFIG_RAW_BINARY=y
@@ -188,6 +191,7 @@ CONFIG_STM32H7_BKPSRAM=y
 CONFIG_STM32H7_DMA1=y
 CONFIG_STM32H7_DMA2=y
 CONFIG_STM32H7_DMACAPABLE=y
+CONFIG_STM32H7_DMAMUX1=y
 CONFIG_STM32H7_FLOWCONTROL_BROKEN=y
 CONFIG_STM32H7_I2C1=y
 CONFIG_STM32H7_I2C_DYNTIMEO=y
@@ -202,6 +206,8 @@ CONFIG_STM32H7_SDMMC1=y
 CONFIG_STM32H7_SERIALBRK_BSDCOMPAT=y
 CONFIG_STM32H7_SERIAL_DISABLE_REORDERING=y
 CONFIG_STM32H7_SPI1=y
+CONFIG_STM32H7_SPI1_DMA=y
+CONFIG_STM32H7_SPI1_DMA_BUFFER=4096
 CONFIG_STM32H7_SPI2=y
 CONFIG_STM32H7_SPI4=y
 CONFIG_STM32H7_SPI4_DMA=y
--- a/boards/holybro/kakuteh7v2/src/board_config.h
+++ b/boards/holybro/kakuteh7v2/src/board_config.h
@@ -59,6 +59,11 @@
 #  define BOARD_HAS_NBAT_V              1
 #  define BOARD_HAS_NBAT_I              1

+/* Enable small flash logging support (for W25N NAND flash) */
+#ifdef CONFIG_MTD_W25N
+#  define BOARD_SMALL_FLASH_LOGGING 1
+#endif
+
 /* Holybro KakuteH7 GPIOs ************************************************************************/

 /* LEDs are driven with push open drain to support Anode to 5V or 3.3V */
--- a/boards/holybro/kakuteh7v2/src/init.c
+++ b/boards/holybro/kakuteh7v2/src/init.c
@@ -59,6 +59,8 @@
 #include <nuttx/spi/spi.h>
 #include <nuttx/analog/adc.h>
 #include <nuttx/mm/gran.h>
+#include <nuttx/mtd/mtd.h>
+#include <nuttx/fs/fs.h>
 #include <chip.h>
 #include <stm32_uart.h>
 #include <arch/board/board.h>
@@ -79,6 +81,10 @@
 #  include <parameters/flashparams/flashfs.h>
 #endif

+#ifdef CONFIG_MTD_W25N
+extern FAR struct mtd_dev_s *w25n_initialize(FAR struct spi_dev_s *dev, uint32_t spi_devid);
+#endif
+

 /****************************************************************************
 * Pre-Processor Definitions
@@ -231,14 +237,49 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 		led_on(LED_RED);
 	}

-	/* Get the SPI port for the microSD slot */
-	struct spi_dev_s *spi_dev = stm32_spibus_initialize(CONFIG_NSH_MMCSDSPIPORTNO);
+#ifdef CONFIG_MTD_W25N
+	/* Initialize W25N01GV NAND Flash on SPI1 */
+	struct spi_dev_s *spi1 = stm32_spibus_initialize(1);

-	if (!spi_dev) {
-		syslog(LOG_ERR, "[boot] FAILED to initialize SPI port %d\n", CONFIG_NSH_MMCSDSPIPORTNO);
-		led_on(LED_BLUE);
+	if (!spi1) {
+		syslog(LOG_ERR, "[boot] FAILED to initialize SPI1 for W25N\n");
+		led_on(LED_RED);
+
+	} else {
+		struct mtd_dev_s *mtd = w25n_initialize(spi1, 0);
+
+		if (!mtd) {
+			syslog(LOG_ERR, "[boot] FAILED to initialize W25N MTD driver\n");
+			led_on(LED_RED);
+
+		} else {
+			int ret = register_mtddriver("/dev/mtd0", mtd, 0755, NULL);
+
+			if (ret < 0) {
+				syslog(LOG_ERR, "[boot] FAILED to register MTD driver: %d\n", ret);
+				led_on(LED_RED);
+
+			} else {
+				syslog(LOG_INFO, "[boot] W25N MTD registered at /dev/mtd0\n");
+
+#ifdef CONFIG_FS_LITTLEFS
+				ret = nx_mount("/dev/mtd0", "/fs/microsd", "littlefs", 0, "autoformat");
+
+				if (ret < 0) {
+					syslog(LOG_ERR, "[boot] FAILED to mount littlefs: %d\n", ret);
+					led_on(LED_RED);
+
+				} else {
+					syslog(LOG_INFO, "[boot] LittleFS mounted at /fs/microsd\n");
+				}
+
+#endif
+			}
+		}
 	}

+#endif
+
 	up_udelay(20);


--- a/boards/holybro/kakuteh7v2/src/spi.cpp
+++ b/boards/holybro/kakuteh7v2/src/spi.cpp
@@ -37,7 +37,7 @@

 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
 	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(SPIDEV_MMCSD(0), SPI::CS{GPIO::PortA, GPIO::Pin4})
+		initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortA, GPIO::Pin4})  // W25N01GV NAND Flash
 	}),
 	initSPIBus(SPI::Bus::SPI2, {
 		initSPIDevice(DRV_OSD_DEVTYPE_ATXXXX, SPI::CS{GPIO::PortB, GPIO::Pin12}),