Finish STM32 IWDG and WWDG watchdog timer drivers

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4613 7fd9a85b-ad96-42d3-883c-3090e2eb8679

nuttx/arch/arm/src/stm32/chip/stm32_wdg.h

@@ -116,6 +116,8 @@
 
 #define WWDG_CFR_W_SHIFT        (0)       /* Bits 6:0 W[6:0] 7-bit window value */
 #define WWDG_CFR_W_MASK         (0x7f << WWDG_CFR_W_SHIFT)
+#  define WWDG_CFR_W_MAX        (0x3f << WWDG_CFR_W_SHIFT)
+#  define WWDG_CFR_W_RESET      (0x40 << WWDG_CFR_W_SHIFT)
 #define WWDG_CFR_WDGTB_SHIFT    (7)       /* Bits 8:7 [1:0]: Timer Base */
 #define WWDG_CFR_WDGTB_MASK     (3 << WWDG_CFR_WDGTB_SHIFT)
 #  define WWDG_CFR_PCLK1        (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */

nuttx/arch/arm/src/stm32/stm32_gpio.c

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/stm32/stm32_gpio.c
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2011 Uros Platise. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *           Uros Platise <uros.platise@isotel.eu>
@@ -127,7 +127,7 @@ static inline void stm32_gpioremap(void)
 #ifdef CONFIG_STM32_JTAG_FULL_ENABLE
   /* The reset default */
 #elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
-  val |= AFIO_MAPR_SWJ;    /* enabled but without JNTRST */
+  val |= AFIO_MAPR_SWJ;       /* enabled but without JNTRST */
 #elif CONFIG_STM32_JTAG_SW_ENABLE
   val |= AFIO_MAPR_SWDP;      /* set JTAG-DP disabled and SW-DP enabled */
 #else

nuttx/arch/arm/src/stm32/stm32_iwdg.c

@@ -47,6 +47,7 @@
 
 #include "up_arch.h"
 #include "stm32_rcc.h"
+#include "chip/stm32_dbgmcu.h"
 #include "stm32_wdg.h"
 
 #if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG)
@@ -315,12 +316,16 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
 
   DEBUGASSERT(priv);
 
+  /* Return the status bit */
+
   status->flags = WDFLAGS_RESET;
   if (priv->started)
     {
       status->flags |= WDFLAGS_ACTIVE;
     }
 
+  /* Return the actual timeout is milliseconds */
+
   status->timeout = priv->timeout;
 
   /* I am not sure what will be returned when reading from the reload register.
@@ -374,11 +379,12 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
        * PR = 4 -> Divider = 64  = 1 << 6
        * PR = 5 -> Divider = 128 = 1 << 7
        * PR = 6 -> Divider = 256 = 1 << 8
+       * PR = n -> Divider       = 1 << (n+2)
        */
 
       shift = pr + 2;
 
-      /* Is the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock,
+      /* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock,
        * this is value in the range of 7500 and 125.
        */
 
@@ -471,6 +477,10 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
 {
   FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
 
+  /* NOTE we assume that clocking to the IWDG has already been provided by
+   * the RCC initialization logic.
+   */
+
   /* Initialize the driver state structure. */
 
   priv->ops = &g_wdgops;
@@ -496,6 +506,21 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
   /* Register the watchdog driver as /dev/watchdog0 */
 
   (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
+
+  /* When the microcontroller enters debug mode (Cortex™-M4F core halted),
+   * the IWDG counter either continues to work normally or stops, depending
+   * on DBG_WIDG_STOP configuration bit in DBG module.
+   */
+
+#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \
+    defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \
+    defined(CONFIG_STM32_JTAG_SW_ENABLE)
+    {
+      uint32_t cr = getreg32(STM32_DBGMCU_CR);
+      cr |= DBGMCU_CR_IWDGSTOP;
+      putreg32(cr, STM32_DBGMCU_CR);
+    }
+#endif
 }
 
 #endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */

nuttx/include/nuttx/watchdog.h

@@ -54,6 +54,8 @@
  * transfer interface, the majority of the functionality is implemented in
  * driver ioctl calls.  The watchdog ioctl commands are lised below:
  *
+ * These are detected and handled by the "upper half" watchdog timer driver.
+ *
  * WDIOC_START      - Start the watchdog timer
  *                    Argument: Ignored
  * WDIOC_STOP       - Stop the watchdog timer
@@ -66,6 +68,14 @@
  *                    Argument: A pointer to struct watchdog_capture_s.
  * WDIOC_KEEPALIVE  - Reset the watchdog timer ("ping", "pet the dog");
  *                    Argument: Ignored
+ *
+ * These may be supported by certain "lower half" drivers
+ *
+ * WDIOC_MINTIME    - Set the minimum ping time.  If two keepalive ioctls
+ *                    are received within this time, a reset event will
+ *                    be generated.  This feature should assume to be 
+ *                    disabled after WDIOC_SETTIMEOUT.
+ *                    Argument: A 32-bit time value in milliseconds.
  */
 
 #define WDIOC_START      _WDIOC(0x001)
@@ -75,6 +85,8 @@
 #define WDIOC_CAPTURE    _WDIOC(0x005)
 #define WDIOC_KEEPALIVE  _WDIOC(0x006)
 
+#define WDIOC_MINTIME    _WDIOC(0x080)
+
 /* Bit Settings *************************************************************/
 /* Bit settings for the struct watchdog_status_s flags field */