mirror of
https://github.com/PX4/PX4-Autopilot.git
synced 2026-05-31 02:16:53 +08:00
rddrone-uavcan146: HRT & RTC timer support
This commit is contained in:
Peter van der Perk
committed by
GitHub
GitHub
parent
3d44077f2c
commit
a4e6f96365
@@ -67,7 +67,7 @@ px4_add_board(
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#reflect
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#sd_bench
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shutdown
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#top
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top
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#topic_listener
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#tune_control
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ver
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@@ -57,6 +57,8 @@
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#define BOARD_XTAL_FREQUENCY 8000000
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#define BOARD_FTM_FREQ 8000000
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/* The S32K146 will run at 112MHz */
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/* LED definitions **********************************************************/
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@@ -5,7 +5,6 @@
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_ARCH_FPU is not set
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# CONFIG_NSH_ARGCAT is not set
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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# CONFIG_NSH_CMDPARMS is not set
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@@ -19,6 +18,8 @@ CONFIG_ARCH_CHIP_S32K146=y
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CONFIG_ARCH_CHIP_S32K14X=y
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CONFIG_ARCH_CHIP_S32K1XX=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_MEMCPY=y
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CONFIG_ARMV7M_USEBASEPRI=y
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CONFIG_BOARDCTL_RESET=y
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CONFIG_BOARD_LOOPSPERMSEC=3997
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CONFIG_BUILTIN=y
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@@ -33,6 +34,7 @@ CONFIG_I2CTOOL_MAXADDR=0x7f
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CONFIG_I2CTOOL_MAXBUS=0
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CONFIG_I2CTOOL_MINADDR=0x00
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LIBC_FLOATINGPOINT=y
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CONFIG_LPUART0_RXBUFSIZE=64
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CONFIG_LPUART0_TXBUFSIZE=64
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CONFIG_LPUART1_RXBUFSIZE=64
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@@ -54,15 +56,19 @@ CONFIG_RAM_SIZE=126976
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CONFIG_RAM_START=0x1fff0000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_RTC=y
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CONFIG_S32K1XX_LPI2C0=y
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CONFIG_S32K1XX_LPSPI0=y
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CONFIG_S32K1XX_LPUART0=y
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CONFIG_S32K1XX_LPUART1=y
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CONFIG_S32K1XX_RTC=y
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CONFIG_SCHED_INSTRUMENTATION=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_SDCLONE_DISABLE=y
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CONFIG_SPITOOL_DEFFREQ=400000
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CONFIG_SPITOOL_MAXBUS=0
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CONFIG_SPITOOL_PROGNAME="spi"
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CONFIG_STACK_COLORATION=y
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CONFIG_START_DAY=18
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CONFIG_START_MONTH=8
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CONFIG_START_YEAR=2019
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@@ -71,4 +77,5 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y
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CONFIG_SYSTEM_I2CTOOL=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_SYSTEM_SPITOOL=y
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CONFIG_USER_ENTRYPOINT="nsh_main"
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CONFIG_USER_ENTRYPOINT="nsh_main"
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CONFIG_WATCHDOG=y
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@@ -92,9 +92,14 @@ __BEGIN_DECLS
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/* Count of peripheral clock user configurations */
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#define NUM_OF_PERIPHERAL_CLOCKS_0 15
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#define NUM_OF_PERIPHERAL_CLOCKS_0 14
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/* High-resolution timer */
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#define HRT_TIMER 1 /* FTM timer for the HRT */
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#define HRT_TIMER_CHANNEL 0 /* Use capture/compare channel 0 */
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#define HRT_PPM_CHANNEL 1 /* Use TPM1 capture/compare channel 1 */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@@ -76,151 +76,137 @@
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const struct clock_configuration_s g_initial_clkconfig = {
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.scg =
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{
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.sirc =
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.sirc =
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{
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.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = true, /* SIRCSTEN */
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.lowpower = true, /* SIRCLPEN */
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.locked = false, /* LK */
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.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = false, /* SIRCSTEN */
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.lowpower = true, /* SIRCLPEN */
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.locked = false, /* LK */
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},
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.firc =
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.firc =
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{
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.range = SCG_FIRC_RANGE_48M, /* RANGE */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = false, /* */
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.lowpower = false, /* */
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.regulator = true, /* FIRCREGOFF */
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.locked = false, /* LK */
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.range = SCG_FIRC_RANGE_48M, /* RANGE */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
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.initialize = true, /* Initialize */
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.regulator = true, /* FIRCREGOFF */
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.locked = false, /* LK */
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},
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.sosc =
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.sosc =
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{
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.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
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.gain = SCG_SOSC_GAIN_LOW, /* HGO */
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.range = SCG_SOSC_RANGE_MID, /* RANGE */
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.extref = SCG_SOSC_REF_OSC, /* EREFS */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
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.initialize = true, /* Initialize */
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.stopmode = false, /* */
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.lowpower = false, /* */
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.locked = false, /* LK */
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.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
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.gain = SCG_SOSC_GAIN_LOW, /* HGO */
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.range = SCG_SOSC_RANGE_HIGH, /* RANGE */
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.extref = SCG_SOSC_REF_OSC, /* EREFS */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
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.initialize = true, /* Initialize */
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.locked = false, /* LK */
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},
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.spll =
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.spll =
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{
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.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
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.prediv = 1, /* PREDIV */
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.mult = 40, /* MULT */
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.src = 0, /* SOURCE */
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.initialize = true, /* Initialize */
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.stopmode = false, /* */
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.locked = false, /* LK */
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.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
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.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
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.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
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.prediv = 1, /* PREDIV */
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.mult = 40, /* MULT */
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.src = 0, /* SOURCE */
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.initialize = true, /* Initialize */
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.locked = false, /* LK */
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},
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.rtc =
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.rtc =
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{
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.initialize = true, /* Initialize */
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.clkin = 0 /* RTC_CLKIN */
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.initialize = true, /* Initialize */
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.clkin = 0, /* RTC_CLKIN */
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},
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.clockout =
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.clockout =
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{
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.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
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.initialize = true, /* Initialize */
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.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
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.initialize = true, /* Initialize */
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},
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.clockmode =
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.clockmode =
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{
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.rccr = /* RCCR - Run Clock Control Register */
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.rccr = /* RCCR - Run Clock Control Register */
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2 /* DIVCORE, range 1..16 */
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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.vccr = /* VCCR - VLPR Clock Control Register */
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.vccr = /* VCCR - VLPR Clock Control Register */
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
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.divslow = 4, /* DIVSLOW, range 1..16 */
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.divbus = 1, /* DIVBUS, range 1..16 */
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.divcore = 2 /* DIVCORE, range 1..16 */
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.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
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.divslow = 4, /* DIVSLOW, range 1..16 */
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.divbus = 1, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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.hccr =
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.hccr =
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{
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2 /* DIVCORE, range 1..16 */
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.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
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.divslow = 3, /* DIVSLOW, range 1..16 */
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.divbus = 2, /* DIVBUS, range 1..16 */
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.divcore = 2, /* DIVCORE, range 1..16 */
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},
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/* .altclk */
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.initialize = true, /* Initialize */
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.initialize = true, /* Initialize */
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},
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},
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.sim =
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.sim =
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{
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.clockout = /* Clock Out configuration. */
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.clockout = /* Clock Out configuration. */
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{
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.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
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.divider = 1, /* CLKOUTDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = false, /* CLKOUTEN */
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.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
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.divider = 1, /* CLKOUTDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = false, /* CLKOUTEN */
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},
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.lpoclk = /* Low Power Clock configuration. */
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.lpoclk = /* Low Power Clock configuration. */
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{
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.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
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.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
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.initialize = true, /* Initialize */
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.lpo32k = true, /* LPO32KCLKEN */
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.lpo1k = true, /* LPO1KCLKEN */
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.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
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.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
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.initialize = true, /* Initialize */
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.lpo32k = true, /* LPO32KCLKEN */
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.lpo1k = true, /* LPO1KCLKEN */
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},
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.tclk = /* TCLK CLOCK configuration. */
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.tclk = /* TCLK CLOCK configuration. */
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{
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.tclkfreq[0] = 0, /* TCLK0 */
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.tclkfreq[1] = 0, /* TCLK1 */
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.tclkfreq[2] = 0, /* TCLK2 */
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.initialize = true, /* Initialize */
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.tclkfreq[0] = 0, /* TCLK0 */
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.tclkfreq[1] = 0, /* TCLK1 */
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.tclkfreq[2] = 0, /* TCLK2 */
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.initialize = true, /* Initialize */
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},
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.platgate = /* Platform Gate Clock configuration. */
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.platgate = /* Platform Gate Clock configuration. */
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{
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.initialize = true, /* Initialize */
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.mscm = true, /* CGCMSCM */
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.mpu = true, /* CGCMPU */
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.dma = true, /* CGCDMA */
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.erm = true, /* CGCERM */
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.eim = true, /* CGCEIM */
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.initialize = true, /* Initialize */
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.mscm = true, /* CGCMSCM */
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.mpu = true, /* CGCMPU */
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.dma = true, /* CGCDMA */
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.erm = true, /* CGCERM */
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.eim = true, /* CGCEIM */
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},
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.traceclk = /* Debug trace Clock Configuration. */
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.traceclk = /* Debug trace Clock Configuration. */
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{
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.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
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.divider = 1, /* TRACEDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = true, /* TRACEDIVEN */
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.fraction = false, /* TRACEFRAC */
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.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
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.divider = 1, /* TRACEDIV, range 1..8 */
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.initialize = true, /* Initialize */
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.enable = true, /* TRACEDIVEN */
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.fraction = false, /* TRACEFRAC */
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},
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#ifdef CONFIG_S32K1XX_HAVE_QSPI
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.qspirefclk = /* Quad Spi Internal Reference Clock Gating. */
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{
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.refclk = false, /* Qspi reference clock gating */
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},
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#endif
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},
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.pcc =
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.pcc =
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{
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.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
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.pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */
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.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
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.pclks = g_peripheral_clockconfig0, /* Peripheral clock configurations */
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},
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.pmc =
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.pmc =
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{
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.lpoclk = /* Low Power Clock configuration. */
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.lpoclk = /* Low Power Clock configuration. */
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{
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.trim = 0, /* Trimming value for LPO */
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.initialize = true, /* Initialize */
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.enable = true, /* Enable/disable LPO */
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.trim = 0, /* Trimming value for LPO */
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.initialize = true, /* Initialize */
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.enable = true, /* Enable/disable LPO */
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},
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}
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},
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};
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@@ -43,6 +43,8 @@
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#include "board_config.h"
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#include <px4_platform_common/init.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@@ -87,6 +89,9 @@ int board_app_initialize(uintptr_t arg)
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return OK;
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#else
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px4_platform_init();
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/* Perform board-specific initialization */
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return s32k1xx_bringup();
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@@ -79,108 +79,96 @@
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const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = {
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{
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.clkname = ADC0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_FIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = FLEXCAN0_CLK,
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#ifdef CONFIG_S32K1XX_FLEXCAN0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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},
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{
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.clkname = ADC1_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_FIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = FLEXCAN1_CLK,
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#ifdef CONFIG_S32K1XX_FLEXCAN1
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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},
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{
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.clkname = LPI2C0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = LPI2C0_CLK,
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#ifdef CONFIG_S32K1XX_LPI2C0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPSPI0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = LPSPI0_CLK,
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#ifdef CONFIG_S32K1XX_LPSPI0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPSPI1_CLK,
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.clkgate = false,
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.clksrc = CLK_SRC_FIRC,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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.clkname = LPUART0_CLK,
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#ifdef CONFIG_S32K1XX_LPUART0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
|
||||
.clkname = LPSPI2_CLK,
|
||||
.clkgate = false,
|
||||
.clksrc = CLK_SRC_FIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = LPUART1_CLK,
|
||||
#ifdef CONFIG_S32K1XX_LPUART1
|
||||
.clkgate = true,
|
||||
#else
|
||||
.clkgate = false,
|
||||
#endif
|
||||
.clksrc = CLK_SRC_SIRC_DIV2,
|
||||
},
|
||||
{
|
||||
.clkname = LPTMR0_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
},
|
||||
{
|
||||
.clkname = LPUART0_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
},
|
||||
{
|
||||
.clkname = LPUART1_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
},
|
||||
{
|
||||
.clkname = LPUART2_CLK,
|
||||
.clkgate = false,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
},
|
||||
{
|
||||
.clkname = PORTA_CLK,
|
||||
.clkgate = true,
|
||||
.clkname = RTC0_CLK,
|
||||
#ifdef CONFIG_S32K1XX_RTC
|
||||
.clkgate = true,
|
||||
#else
|
||||
.clkgate = false,
|
||||
#endif
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
},
|
||||
{
|
||||
.clkname = PORTB_CLK,
|
||||
.clkname = FTM0_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
},
|
||||
{
|
||||
.clkname = PORTC_CLK,
|
||||
.clkname = FTM1_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clksrc = CLK_SRC_SIRC,
|
||||
},
|
||||
{
|
||||
.clkname = PORTD_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
.clkname = PORTA_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = PORTE_CLK,
|
||||
.clkgate = true,
|
||||
.clksrc = CLK_SRC_OFF,
|
||||
.frac = MULTIPLY_BY_ONE,
|
||||
.divider = 1,
|
||||
}
|
||||
.clkname = PORTB_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = PORTC_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = PORTD_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
{
|
||||
.clkname = PORTE_CLK,
|
||||
.clkgate = true,
|
||||
},
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user