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STM32F7 disable d-cache as a precaution (#11374)
- see 1259864 Data corruption in a sequence of Write-Through stores and loads - if we can be certain this sequence won't occur in PX4 then the d-cache will be re-enabled
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@@ -162,8 +162,7 @@ CONFIG_ARMV7M_HAVE_DCACHE=y
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CONFIG_ARMV7M_USEBASEPRI=y
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CONFIG_ARMV7M_BASEPRI_WAR=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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# CONFIG_ARMV7M_DCACHE is not set
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CONFIG_ARMV7M_HAVE_ITCM=y
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CONFIG_ARMV7M_HAVE_DTCM=y
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# CONFIG_ARMV7M_ITCM is not set
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