mirror of
https://github.com/PX4/PX4-Autopilot.git
synced 2026-05-10 14:51:15 +08:00
new TDK ICM42670p IMU driver support (#18141)
Co-authored-by: zhaoxiaowei <zhaoxiaowei@efy-tech.com>
This commit is contained in:
ShiauweiZhao
GitHub
@@ -78,6 +78,7 @@
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#define DRV_IMU_DEVTYPE_ICM40609D 0x27
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#define DRV_IMU_DEVTYPE_ICM20948 0x28
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#define DRV_IMU_DEVTYPE_ICM42605 0x29
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#define DRV_IMU_DEVTYPE_ICM42670P 0x2A
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#define DRV_RNG_DEVTYPE_MB12XX 0x31
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#define DRV_RNG_DEVTYPE_LL40LS 0x32
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@@ -38,6 +38,7 @@ add_subdirectory(icm20689)
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add_subdirectory(icm40609d)
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add_subdirectory(icm42605)
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add_subdirectory(icm42688p)
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add_subdirectory(icm42670p)
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add_subdirectory(mpu6000)
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add_subdirectory(mpu6500)
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add_subdirectory(mpu9250)
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@@ -0,0 +1,46 @@
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############################################################################
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#
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# Copyright (c) 2021 PX4 Development Team. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
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||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name PX4 nor the names of its contributors may be
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||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
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||||
#
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||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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############################################################################
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px4_add_module(
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MODULE drivers__imu__invensense__icm42670p
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MAIN icm42670p
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COMPILE_FLAGS
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SRCS
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icm42670p_main.cpp
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ICM42670P.cpp
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ICM42670P.hpp
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InvenSense_ICM42670P_registers.hpp
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DEPENDS
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px4_work_queue
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drivers_accelerometer
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drivers_gyroscope
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)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,184 @@
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/****************************************************************************
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*
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* Copyright (c) 2021 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
|
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/**
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* @file ICM42688P.hpp
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*
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* Driver for the Invensense ICM42688P connected via SPI.
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*
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*/
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#pragma once
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#include "InvenSense_ICM42670P_registers.hpp"
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#include <drivers/drv_hrt.h>
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#include <lib/drivers/accelerometer/PX4Accelerometer.hpp>
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#include <lib/drivers/device/spi.h>
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#include <lib/drivers/gyroscope/PX4Gyroscope.hpp>
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#include <lib/perf/perf_counter.h>
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#include <px4_platform_common/atomic.h>
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#include <px4_platform_common/i2c_spi_buses.h>
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using namespace InvenSense_ICM42670P;
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class ICM42670P : public device::SPI, public I2CSPIDriver<ICM42670P>
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{
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public:
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ICM42670P(const I2CSPIDriverConfig &config);
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~ICM42670P() override;
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static void print_usage();
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void RunImpl();
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int init() override;
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void print_status() override;
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private:
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void exit_and_cleanup() override;
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// Sensor Configuration
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static constexpr float FIFO_SAMPLE_DT{1e6f / 800.f}; // 8000 Hz accel & gyro ODR configured
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static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT};
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static constexpr float ACCEL_RATE{1e6f / FIFO_SAMPLE_DT};
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// maximum FIFO samples per transfer is limited to the size of sensor_accel_fifo/sensor_gyro_fifo
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static constexpr uint32_t FIFO_MAX_SAMPLES{math::min(math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(sensor_gyro_fifo_s::x) / sizeof(sensor_gyro_fifo_s::x[0])), sizeof(sensor_accel_fifo_s::x) / sizeof(sensor_accel_fifo_s::x[0]) * (int)(GYRO_RATE / ACCEL_RATE))};
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// Transfer data
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struct FIFOTransferBuffer {
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uint8_t cmd{static_cast<uint8_t>(Register::BANK_0::INT_STATUS) | DIR_READ};
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uint8_t INT_STATUS{0};
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uint8_t INT_STATUS2{0};
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uint8_t INT_STATUS3{0};
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uint8_t FIFO_COUNTH{0};
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uint8_t FIFO_COUNTL{0};
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FIFO::DATA f[FIFO_MAX_SAMPLES] {};
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};
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// ensure no struct padding
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static_assert(sizeof(FIFOTransferBuffer) == (4 + 2 + FIFO_MAX_SAMPLES *sizeof(FIFO::DATA)));
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struct register_bank0_config_t {
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Register::BANK_0 reg;
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uint8_t set_bits{0};
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uint8_t clear_bits{0};
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};
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int probe() override;
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bool Reset();
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bool Configure();
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void ConfigureAccel();
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void ConfigureGyro();
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void ConfigureSampleRate(int sample_rate);
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void ConfigureFIFOWatermark(uint8_t samples);
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static int DataReadyInterruptCallback(int irq, void *context, void *arg);
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void DataReady();
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bool DataReadyInterruptConfigure();
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bool DataReadyInterruptDisable();
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template <typename T> bool RegisterCheck(const T ®_cfg);
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template <typename T> uint8_t RegisterRead(T reg);
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template <typename T> void RegisterWrite(T reg, uint8_t value);
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template <typename T> void RegisterSetAndClearBits(T reg, uint8_t setbits, uint8_t clearbits);
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template <typename T> void RegisterSetBits(T reg, uint8_t setbits) { RegisterSetAndClearBits(reg, setbits, 0); }
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template <typename T> void RegisterClearBits(T reg, uint8_t clearbits) { RegisterSetAndClearBits(reg, 0, clearbits); }
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uint16_t FIFOReadCount();
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bool FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples);
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void FIFOReset();
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void ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples);
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void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples);
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void UpdateTemperature();
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uint8_t RegisterReadBank1(uint8_t reg);
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void RegisterWriteBank1(uint8_t reg, uint8_t value);
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void Mreg1Config();
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bool Mreg1Check();
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const spi_drdy_gpio_t _drdy_gpio;
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PX4Accelerometer _px4_accel;
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PX4Gyroscope _px4_gyro;
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perf_counter_t _bad_register_perf{perf_alloc(PC_COUNT, MODULE_NAME": bad register")};
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perf_counter_t _bad_transfer_perf{perf_alloc(PC_COUNT, MODULE_NAME": bad transfer")};
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perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO empty")};
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perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO overflow")};
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perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO reset")};
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perf_counter_t _drdy_missed_perf{nullptr};
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hrt_abstime _reset_timestamp{0};
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hrt_abstime _last_config_check_timestamp{0};
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hrt_abstime _temperature_update_timestamp{0};
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int _failure_count{0};
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enum REG_BANK_SEL_BIT _last_register_bank {REG_BANK_SEL_BIT::USER_BANK_0};
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px4::atomic<uint32_t> _drdy_fifo_read_samples{0};
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bool _data_ready_interrupt_enabled{false};
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enum class STATE : uint8_t {
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RESET,
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WAIT_FOR_RESET,
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CONFIGURE,
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FIFO_READ,
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};
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STATE _state{STATE::RESET};
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uint16_t _fifo_empty_interval_us{1250}; // default 1250 us / 800 Hz transfer interval
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uint32_t _fifo_gyro_samples{static_cast<uint32_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
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uint8_t _checked_register_bank0{0};
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static constexpr uint8_t size_register_bank0_cfg{10};
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register_bank0_config_t _register_bank0_cfg[size_register_bank0_cfg] {
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// Register | Set bits, Clear bits
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{ Register::BANK_0::INT_CONFIG, INT_CONFIG_BIT::INT1_MODE | INT_CONFIG_BIT::INT1_DRIVE_CIRCUIT, INT_CONFIG_BIT::INT1_POLARITY },
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{ Register::BANK_0::FIFO_CONFIG1, FIFO_CONFIG1_BIT::FIFO_MODE_STOP_ON_FULL, Bit0 },
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{ Register::BANK_0::PWR_MGMT0, PWR_MGMT0_BIT::GYRO_MODE_LOW_NOISE | PWR_MGMT0_BIT::ACCEL_MODE_LOW_NOISE, 0 },
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{ Register::BANK_0::GYRO_CONFIG0, GYRO_CONFIG0_BIT::GYRO_ODR_1600Hz | GYRO_CONFIG0_BIT::GYRO_FS_SEL_2000_DPS, Bit7 | Bit3 | Bit0 },
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{ Register::BANK_0::ACCEL_CONFIG0, ACCEL_CONFIG0_BIT::ACCEL_ODR_1600Hz | ACCEL_CONFIG0_BIT::ACCEL_FS_SEL_16G, Bit6 | Bit5 | Bit3 | Bit0 },
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{ Register::BANK_0::GYRO_CONFIG1, GYRO_CONFIG1_BIT::GYRO_UI_FILT_BW_34Hz, Bit1 },
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{ Register::BANK_0::ACCEL_CONFIG1, ACCEL_CONFIG1_BIT::ACCEL_UI_FILT_BW_34Hz, Bit1 },
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{ Register::BANK_0::FIFO_CONFIG2, 0, 0 }, // FIFO_WM[7:0] set at runtime
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{ Register::BANK_0::FIFO_CONFIG3, 0, 0 }, // FIFO_WM[11:8] set at runtime
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{ Register::BANK_0::INT_SOURCE0, INT_SOURCE0_BIT::FIFO_THS_INT1_EN, 0 },
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};
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};
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@@ -0,0 +1,293 @@
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/****************************************************************************
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*
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* Copyright (c) 2021 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name PX4 nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
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*
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****************************************************************************/
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/**
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* @file InvenSense_ICM42670P_registers.hpp
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*
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* Invensense ICM-42670-P registers.
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*
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*/
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#pragma once
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#include <cstdint>
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namespace InvenSense_ICM42670P
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{
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// TODO: move to a central header
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static constexpr uint8_t Bit0 = (1 << 0);
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static constexpr uint8_t Bit1 = (1 << 1);
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static constexpr uint8_t Bit2 = (1 << 2);
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static constexpr uint8_t Bit3 = (1 << 3);
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static constexpr uint8_t Bit4 = (1 << 4);
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static constexpr uint8_t Bit5 = (1 << 5);
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static constexpr uint8_t Bit6 = (1 << 6);
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static constexpr uint8_t Bit7 = (1 << 7);
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static constexpr uint32_t SPI_SPEED = 12 * 1000 * 1000; // 24 MHz SPI
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static constexpr uint8_t DIR_READ = 0x80;
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static constexpr uint8_t WHOAMI = 0x67;
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static constexpr float TEMPERATURE_SENSITIVITY = 128.0f; // LSB/C
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static constexpr float TEMPERATURE_OFFSET = 25.f; // C
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namespace Register
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{
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enum class BANK_0 : uint8_t {
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DEVICE_CONFIG = 0x01,
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INT_CONFIG = 0x06,
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TEMP_DATA1 = 0x09,
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TEMP_DATA0 = 0x0A,
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INT_STATUS = 0x3A,
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FIFO_COUNTH = 0x3D,
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FIFO_COUNTL = 0x3E,
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FIFO_DATA = 0x3F,
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SIGNAL_PATH_RESET = 0x02,
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PWR_MGMT0 = 0x1F,
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GYRO_CONFIG0 = 0x20,
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ACCEL_CONFIG0 = 0x21,
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GYRO_CONFIG1 = 0x23,
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ACCEL_CONFIG1 = 0x24,
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FIFO_CONFIG1 = 0x28,
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FIFO_CONFIG2 = 0x29,
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FIFO_CONFIG3 = 0x2A,
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INT_SOURCE0 = 0x2B,
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WHO_AM_I = 0x75,
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// REG_BANK_SEL = 0x76,
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BLK_SEL_W = 0x79,
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MADDR_W = 0x7A,
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M_W = 0x7B,
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BLK_SEL_R = 0x7C,
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MADDR_R = 0x7D,
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M_R = 0x7E,
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};
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enum class MREG_1 : uint8_t {
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FIFO_CONFIG5_MREG1 = 0x01,
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INT_CONFIG0_MREG1 = 0x04,
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};
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enum class MREG_2 : uint8_t {
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OTP_CTRL7_MREG2 = 0x06,
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};
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enum class MREG_3 : uint8_t {
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XA_ST_DATA_MREG3 = 0x00,
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YA_ST_DATA_MREG3 = 0x01,
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ZA_ST_DATA_MREG3 = 0x02,
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XG_ST_DATA_MREG3 = 0x03,
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YG_ST_DATA_MREG3 = 0x04,
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ZG_ST_DATA_MREG3 = 0x05,
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};
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||||
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||||
|
||||
};
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//---------------- BANK0 Register bits
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// SIGNAL_PATH_RESET
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enum SIGNAL_PATH_RESET_BIT : uint8_t {
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SOFT_RESET_DEVICE_CONFIG = Bit4, //
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FIFO_FLUSH = Bit2,
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};
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// INT_CONFIG
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enum INT_CONFIG_BIT : uint8_t {
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INT1_MODE = Bit2,
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INT1_DRIVE_CIRCUIT = Bit1,
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INT1_POLARITY = Bit0,
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};
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// GYRO_CONFIG1
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enum GYRO_CONFIG1_BIT : uint8_t {
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// 2:0 GYRO_ODR
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GYRO_UI_FILT_BW_16Hz = Bit2 | Bit1 | Bit0, // 111: 16Hz
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GYRO_UI_FILT_BW_25Hz = Bit2 | Bit1, // 110: 25Hz
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GYRO_UI_FILT_BW_34Hz = Bit2 | Bit0, // 101: 34Hz
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GYRO_UI_FILT_BW_53Hz = Bit2, // 100: 53Hz
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GYRO_UI_FILT_BW_73Hz = Bit1 | Bit0, // 011: 73Hz
|
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GYRO_UI_FILT_BW_121Hz = Bit1, // 010: 121Hz
|
||||
GYRO_UI_FILT_BW_180Hz = Bit0, // 001: 180Hz
|
||||
};
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||||
|
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// ACCEL_CONFIG1
|
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enum ACCEL_CONFIG1_BIT : uint8_t {
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||||
|
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// 2:0 ACCEL_ODR
|
||||
ACCEL_UI_FILT_BW_16Hz = Bit2 | Bit1 | Bit0, // 111: 16Hz
|
||||
ACCEL_UI_FILT_BW_25Hz = Bit2 | Bit1, // 110: 25Hz
|
||||
ACCEL_UI_FILT_BW_34Hz = Bit2 | Bit0, // 101: 34Hz
|
||||
ACCEL_UI_FILT_BW_53Hz = Bit2, // 100: 53Hz
|
||||
ACCEL_UI_FILT_BW_73Hz = Bit1 | Bit0, // 011: 73Hz
|
||||
ACCEL_UI_FILT_BW_121Hz = Bit1, // 010: 121Hz
|
||||
ACCEL_UI_FILT_BW_180Hz = Bit0, // 001: 180Hz
|
||||
};
|
||||
// FIFO_CONFIG1
|
||||
enum FIFO_CONFIG1_BIT : uint8_t {
|
||||
// 1 FIFO_MODE
|
||||
FIFO_MODE_STOP_ON_FULL = Bit1, // 11: STOP-on-FULL Mode
|
||||
};
|
||||
|
||||
// INT_STATUS
|
||||
enum INT_STATUS_BIT : uint8_t {
|
||||
RESET_DONE_INT = Bit4,
|
||||
FIFO_THS_INT = Bit2,
|
||||
FIFO_FULL_INT = Bit1,
|
||||
};
|
||||
|
||||
// PWR_MGMT0
|
||||
enum PWR_MGMT0_BIT : uint8_t {
|
||||
GYRO_MODE_LOW_NOISE = Bit3 | Bit2, // 11: Places gyroscope in Low Noise (LN) Mode
|
||||
ACCEL_MODE_LOW_NOISE = Bit1 | Bit0, // 11: Places accelerometer in Low Noise (LN) Mode
|
||||
};
|
||||
|
||||
// GYRO_CONFIG0
|
||||
enum GYRO_CONFIG0_BIT : uint8_t {
|
||||
// 6:5 GYRO_FS_SEL
|
||||
GYRO_FS_SEL_2000_DPS = 0, // 0b000 = ±2000dps
|
||||
GYRO_FS_SEL_1000_DPS = Bit5, // 0b001 = ±1000 dps
|
||||
GYRO_FS_SEL_500_DPS = Bit6, // 0b010 = ±500 dps
|
||||
GYRO_FS_SEL_250_DPS = Bit6 | Bit5, // 0b011 = ±250 dps
|
||||
|
||||
// 3:0 GYRO_ODR
|
||||
GYRO_ODR_1600Hz = Bit2 | Bit0, // 0101: 1600Hz
|
||||
GYRO_ODR_800Hz = Bit2 | Bit1, // 0110: 800Hz
|
||||
GYRO_ODR_400Hz = Bit2 | Bit1 | Bit0, // 0111: 400Hz
|
||||
GYRO_ODR_200Hz = Bit3, // 1000: 200Hz
|
||||
};
|
||||
|
||||
// ACCEL_CONFIG0
|
||||
enum ACCEL_CONFIG0_BIT : uint8_t {
|
||||
// 6:5 ACCEL_FS_SEL
|
||||
ACCEL_FS_SEL_16G = 0, // 000: ±16g
|
||||
ACCEL_FS_SEL_8G = Bit5, // 001: ±8g
|
||||
ACCEL_FS_SEL_4G = Bit6, // 010: ±4g
|
||||
ACCEL_FS_SEL_2G = Bit6 | Bit5, // 011: ±2g
|
||||
|
||||
// 3:0 ACCEL_ODR
|
||||
ACCEL_ODR_1600Hz = Bit2 | Bit0, // 0101: 1600Hz
|
||||
ACCEL_ODR_800Hz = Bit2 | Bit1, // 0110: 800Hz
|
||||
ACCEL_ODR_400Hz = Bit2 | Bit1 | Bit0, // 0111: 400Hz
|
||||
ACCEL_ODR_200Hz = Bit3, // 1000: 200Hz
|
||||
};
|
||||
|
||||
// FIFO_CONFIG5
|
||||
enum FIFO_CONFIG5_BIT : uint8_t {
|
||||
FIFO_RESUME_PARTIAL_RD = Bit4,
|
||||
FIFO_WM_GT_TH = Bit5,
|
||||
FIFO_HIRES_EN = Bit3,
|
||||
FIFO_TMST_FSYNC_EN = Bit2,
|
||||
FIFO_GYRO_EN = Bit1,
|
||||
FIFO_ACCEL_EN = Bit0,
|
||||
};
|
||||
|
||||
// INT_CONFIG0
|
||||
enum INT_CONFIG0_BIT : uint8_t {
|
||||
// 3:2 FIFO_THS_INT_CLEAR
|
||||
CLEAR_ON_FIFO_READ = Bit3,
|
||||
};
|
||||
|
||||
// INT_SOURCE0
|
||||
enum INT_SOURCE0_BIT : uint8_t {
|
||||
ST_INT1_END = Bit7,
|
||||
FSYNC_INT1_EN = Bit6,
|
||||
PLL_RDY_INT1_EN = Bit5,
|
||||
RESET_DONE_INT1_EN = Bit4,
|
||||
DRDY_INT1_EN = Bit3,
|
||||
FIFO_THS_INT1_EN = Bit2, // FIFO threshold interrupt routed to INT1
|
||||
FIFO_FULL_INT1_EN = Bit1,
|
||||
AGC_RDY_INT1_EN = Bit0,
|
||||
};
|
||||
|
||||
// REG_BANK_SEL
|
||||
enum REG_BANK_SEL_BIT : uint8_t {
|
||||
USER_BANK_0 = 0, // 0: Select USER BANK 0.
|
||||
USER_BANK_1 = Bit4, // 1: Select USER BANK 1.
|
||||
USER_BANK_2 = Bit5, // 2: Select USER BANK 2.
|
||||
USER_BANK_3 = Bit5 | Bit4, // 3: Select USER BANK 3.
|
||||
};
|
||||
|
||||
namespace FIFO
|
||||
{
|
||||
static constexpr size_t SIZE = 2048;
|
||||
|
||||
// FIFO_DATA layout when FIFO_CONFIG1 has FIFO_GYRO_EN and FIFO_ACCEL_EN set
|
||||
|
||||
// Packet 3
|
||||
struct DATA {
|
||||
uint8_t FIFO_Header;
|
||||
uint8_t ACCEL_DATA_X1;
|
||||
uint8_t ACCEL_DATA_X0;
|
||||
uint8_t ACCEL_DATA_Y1;
|
||||
uint8_t ACCEL_DATA_Y0;
|
||||
uint8_t ACCEL_DATA_Z1;
|
||||
uint8_t ACCEL_DATA_Z0;
|
||||
uint8_t GYRO_DATA_X1;
|
||||
uint8_t GYRO_DATA_X0;
|
||||
uint8_t GYRO_DATA_Y1;
|
||||
uint8_t GYRO_DATA_Y0;
|
||||
uint8_t GYRO_DATA_Z1;
|
||||
uint8_t GYRO_DATA_Z0;
|
||||
uint8_t temperature; // Temperature[7:0]
|
||||
uint8_t timestamp_l;
|
||||
uint8_t timestamp_h;
|
||||
};
|
||||
|
||||
// With FIFO_ACCEL_EN and FIFO_GYRO_EN header should be 8’b_0110_10xx
|
||||
enum FIFO_HEADER_BIT : uint8_t {
|
||||
HEADER_MSG = Bit7, // 1: FIFO is empty
|
||||
HEADER_ACCEL = Bit6,
|
||||
HEADER_GYRO = Bit5,
|
||||
HEADER_20 = Bit4,
|
||||
HEADER_TIMESTAMP_FSYNC = Bit3 | Bit2,
|
||||
HEADER_ODR_ACCEL = Bit1,
|
||||
HEADER_ODR_GYRO = Bit0,
|
||||
};
|
||||
|
||||
}
|
||||
} // namespace InvenSense_ICM42670P
|
||||
@@ -0,0 +1,89 @@
|
||||
/****************************************************************************
|
||||
*
|
||||
* Copyright (c) 2021 PX4 Development Team. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name PX4 nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "ICM42670P.hpp"
|
||||
|
||||
#include <px4_platform_common/getopt.h>
|
||||
#include <px4_platform_common/module.h>
|
||||
|
||||
void ICM42670P::print_usage()
|
||||
{
|
||||
PRINT_MODULE_USAGE_NAME("icm42670p", "driver");
|
||||
PRINT_MODULE_USAGE_SUBCATEGORY("imu");
|
||||
PRINT_MODULE_USAGE_COMMAND("start");
|
||||
PRINT_MODULE_USAGE_PARAMS_I2C_SPI_DRIVER(false, true);
|
||||
PRINT_MODULE_USAGE_PARAM_INT('R', 0, 0, 35, "Rotation", true);
|
||||
PRINT_MODULE_USAGE_DEFAULT_COMMANDS();
|
||||
}
|
||||
|
||||
|
||||
extern "C" int icm42670p_main(int argc, char *argv[])
|
||||
{
|
||||
int ch;
|
||||
using ThisDriver = ICM42670P;
|
||||
BusCLIArguments cli{false, true};
|
||||
cli.default_spi_frequency = SPI_SPEED;
|
||||
|
||||
while ((ch = cli.getOpt(argc, argv, "R:")) != EOF) {
|
||||
switch (ch) {
|
||||
case 'R':
|
||||
cli.rotation = (enum Rotation)atoi(cli.optArg());
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
const char *verb = cli.optArg();
|
||||
|
||||
if (!verb) {
|
||||
ThisDriver::print_usage();
|
||||
return -1;
|
||||
}
|
||||
|
||||
BusInstanceIterator iterator(MODULE_NAME, cli, DRV_IMU_DEVTYPE_ICM42670P);
|
||||
|
||||
if (!strcmp(verb, "start")) {
|
||||
return ThisDriver::module_start(cli, iterator);
|
||||
}
|
||||
|
||||
if (!strcmp(verb, "stop")) {
|
||||
return ThisDriver::module_stop(iterator);
|
||||
}
|
||||
|
||||
if (!strcmp(verb, "status")) {
|
||||
return ThisDriver::module_status(iterator);
|
||||
}
|
||||
|
||||
ThisDriver::print_usage();
|
||||
return -1;
|
||||
}
|
||||
Reference in New Issue
Block a user