mirror of
https://github.com/PX4/PX4-Autopilot.git
synced 2026-05-29 03:36:07 +08:00
InvenSense ICM-42688-P IMU driver
This is a new InvenSense sensor with max output data rate of 32 kHz (both accel & gyro), on board anti-aliasing filter, optional higher resolution output (18 bit accel, 19 bit gyro), and clock sync.
This commit is contained in:
Daniel Agar
GitHub
@@ -25,7 +25,8 @@ px4_add_board(
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dshot
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dshot
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gps
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gps
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imu/bmi088
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imu/bmi088
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# TODO imu/icm42688
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imu/invensense/icm20602
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imu/invensense/icm42688p
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imu/mpu6000
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imu/mpu6000
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irlock
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irlock
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lights/blinkm
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lights/blinkm
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@@ -13,7 +13,7 @@ voxlpm -X -b 3 -T P5VDC start
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mpu6000 -R 6 -s -T 20602 start
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mpu6000 -R 6 -s -T 20602 start
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# Internal SPI bus ICM-42688
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# Internal SPI bus ICM-42688
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# TODO
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icm42688p -R 12 start
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# Internal SPI bus BMI088 accel
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# Internal SPI bus BMI088 accel
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bmi088 -A -R 4 start
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bmi088 -A -R 4 start
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@@ -135,8 +135,8 @@
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#define GPIO_SPI2_nCS1_ICM_42688 /* PH5 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTH|GPIO_PIN5)
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#define GPIO_SPI2_nCS1_ICM_42688 /* PH5 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTH|GPIO_PIN5)
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/* Define the SPI2 Data Ready interrupts */
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/* Define the SPI2 Data Ready interrupts */
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#define GPIO_SPI2_DRDY1_ICM_42688 /* PH12 */ (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTH|GPIO_PIN12) // IMU_2_INT -> PH12
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#define GPIO_SPI2_DRDY1_ICM_42688 /* PH12 */ (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTH|GPIO_PIN12)
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#define GPIO_SPI2_DRDY2_ICM_42688 /* PA0 */ (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0) // IMU_2_FSYNC <- PA0/TIM5_CH1
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/* SPI2 off */
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/* SPI2 off */
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@@ -144,8 +144,6 @@
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#define GPIO_SPI2_MISO_OFF _PIN_OFF(GPIO_SPI2_MISO)
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#define GPIO_SPI2_MISO_OFF _PIN_OFF(GPIO_SPI2_MISO)
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#define GPIO_SPI2_MOSI_OFF _PIN_OFF(GPIO_SPI2_MOSI)
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#define GPIO_SPI2_MOSI_OFF _PIN_OFF(GPIO_SPI2_MOSI)
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#define GPIO_DRDY_OFF_SPI2_DRDY1_ICM_42688 _PIN_OFF(GPIO_SPI2_DRDY1_ICM_42688)
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/* SPI 5 CS */
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/* SPI 5 CS */
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#define GPIO_SPI5_nCS1_FRAM /* PG7 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN7)
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#define GPIO_SPI5_nCS1_FRAM /* PG7 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN7)
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@@ -162,7 +160,8 @@
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/* Define the SPI6 Data Ready interrupts */
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/* Define the SPI6 Data Ready interrupts */
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#define GPIO_DRDY_OFF_SPI6_DRDY1_BMI088 _PIN_OFF(GPIO_SPI6_DRDY1_BMI088_INT1_ACCEL)#define GPIO_DRDY_OFF_SPI6_DRDY2_BMI088 _PIN_OFF(GPIO_SPI6_DRDY2_BMI088_INT3_GYRO)
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#define GPIO_DRDY_OFF_SPI6_DRDY1_BMI088 _PIN_OFF(GPIO_SPI6_DRDY1_BMI088_INT1_ACCEL)
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#define GPIO_DRDY_OFF_SPI6_DRDY2_BMI088 _PIN_OFF(GPIO_SPI6_DRDY2_BMI088_INT3_GYRO)
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/* SPI6 off */
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/* SPI6 off */
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@@ -186,7 +185,7 @@
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#define PX4_SPIDEV_ICM_20602 PX4_MK_SPI_SEL(0,DRV_IMU_DEVTYPE_ICM20602)
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#define PX4_SPIDEV_ICM_20602 PX4_MK_SPI_SEL(0,DRV_IMU_DEVTYPE_ICM20602)
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#define PX4_SENSORS1_BUS_CS_GPIO {GPIO_SPI1_nCS1_ICM20602}
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#define PX4_SENSORS1_BUS_CS_GPIO {GPIO_SPI1_nCS1_ICM20602}
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#define PX4_SPIDEV_ICM_42688 PX4_MK_SPI_SEL(0,DRV_DEVTYPE_UNUSED)
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#define PX4_SPIDEV_ICM_42688 PX4_MK_SPI_SEL(0,DRV_IMU_DEVTYPE_ICM42688P)
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#define PX4_SENSORS2_BUS_CS_GPIO {GPIO_SPI2_nCS1_ICM_42688}
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#define PX4_SENSORS2_BUS_CS_GPIO {GPIO_SPI2_nCS1_ICM_42688}
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#define PX4_SPIDEV_MEMORY SPIDEV_FLASH(0)
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#define PX4_SPIDEV_MEMORY SPIDEV_FLASH(0)
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@@ -40,8 +40,7 @@ constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
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initSPIDevice(DRV_IMU_DEVTYPE_ICM20602, SPI::CS{GPIO::PortI, GPIO::Pin9}, SPI::DRDY{GPIO::PortF, GPIO::Pin2}),
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initSPIDevice(DRV_IMU_DEVTYPE_ICM20602, SPI::CS{GPIO::PortI, GPIO::Pin9}, SPI::DRDY{GPIO::PortF, GPIO::Pin2}),
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}),
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}),
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initSPIBus(SPI::Bus::SPI2, {
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initSPIBus(SPI::Bus::SPI2, {
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// ICM-42688
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initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortH, GPIO::Pin5}, SPI::DRDY{GPIO::PortH, GPIO::Pin12}),
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initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortH, GPIO::Pin5}, SPI::DRDY{GPIO::PortH, GPIO::Pin12}),
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}),
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}),
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initSPIBus(SPI::Bus::SPI5, {
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initSPIBus(SPI::Bus::SPI5, {
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initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortG, GPIO::Pin7})
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initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortG, GPIO::Pin7})
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@@ -76,6 +76,7 @@
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#define DRV_GYR_DEVTYPE_GYROSIM 0x23
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#define DRV_GYR_DEVTYPE_GYROSIM 0x23
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#define DRV_IMU_DEVTYPE_MPU9250 0x24
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#define DRV_IMU_DEVTYPE_MPU9250 0x24
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#define DRV_GYR_DEVTYPE_BMI160 0x25
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#define DRV_GYR_DEVTYPE_BMI160 0x25
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#define DRV_IMU_DEVTYPE_ICM42688P 0x26
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#define DRV_RNG_DEVTYPE_MB12XX 0x31
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#define DRV_RNG_DEVTYPE_MB12XX 0x31
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#define DRV_RNG_DEVTYPE_LL40LS 0x32
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#define DRV_RNG_DEVTYPE_LL40LS 0x32
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@@ -0,0 +1,46 @@
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############################################################################
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#
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# Copyright (c) 2020 PX4 Development Team. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# 3. Neither the name PX4 nor the names of its contributors may be
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# used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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############################################################################
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px4_add_module(
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MODULE drivers__imu__invensense__icm42688p
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MAIN icm42688p
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COMPILE_FLAGS
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SRCS
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icm42688p_main.cpp
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ICM42688P.cpp
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ICM42688P.hpp
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InvenSense_ICM42688P_registers.hpp
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DEPENDS
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px4_work_queue
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drivers_accelerometer
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drivers_gyroscope
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)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,174 @@
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/****************************************************************************
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*
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* Copyright (c) 2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/**
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* @file ICM42688P.hpp
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*
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* Driver for the Invensense ICM42688P connected via SPI.
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*
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*/
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#pragma once
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#include "InvenSense_ICM42688P_registers.hpp"
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#include <drivers/drv_hrt.h>
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#include <lib/drivers/accelerometer/PX4Accelerometer.hpp>
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#include <lib/drivers/device/spi.h>
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#include <lib/drivers/gyroscope/PX4Gyroscope.hpp>
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#include <lib/ecl/geo/geo.h>
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#include <lib/perf/perf_counter.h>
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#include <px4_platform_common/atomic.h>
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#include <px4_platform_common/px4_work_queue/ScheduledWorkItem.hpp>
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using namespace InvenSense_ICM42688P;
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class ICM42688P : public device::SPI, public px4::ScheduledWorkItem
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{
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public:
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ICM42688P(int bus, uint32_t device, enum Rotation rotation = ROTATION_NONE);
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~ICM42688P() override;
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bool Init();
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void Start();
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void Stop();
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bool Reset();
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void PrintInfo();
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private:
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static constexpr uint32_t GYRO_RATE{8000}; // 8 kHz gyro
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static constexpr uint32_t ACCEL_RATE{8000}; // 8 kHz accel
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static constexpr uint32_t FIFO_MAX_SAMPLES{ math::min(FIFO::SIZE / sizeof(FIFO::DATA) + 1, sizeof(PX4Gyroscope::FIFOSample::x) / sizeof(PX4Gyroscope::FIFOSample::x[0]))};
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// Transfer data
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struct TransferBuffer {
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uint8_t cmd;
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uint8_t INT_STATUS;
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uint8_t FIFO_COUNTH;
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uint8_t FIFO_COUNTL;
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FIFO::DATA f[FIFO_MAX_SAMPLES];
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};
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// ensure no struct padding
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static_assert(sizeof(TransferBuffer) == (4 * sizeof(uint8_t) + FIFO_MAX_SAMPLES *sizeof(FIFO::DATA)));
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struct register_bank0_config_t {
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Register::BANK_0 reg;
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uint8_t set_bits{0};
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uint8_t clear_bits{0};
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};
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int probe() override;
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void Run() override;
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bool Configure();
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void ConfigureAccel();
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void ConfigureGyro();
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void ConfigureSampleRate(int sample_rate);
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static int DataReadyInterruptCallback(int irq, void *context, void *arg);
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void DataReady();
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bool DataReadyInterruptConfigure();
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bool DataReadyInterruptDisable();
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bool RegisterCheck(const register_bank0_config_t ®_cfg, bool notify = false);
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uint8_t RegisterRead(Register::BANK_0 reg);
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void RegisterWrite(Register::BANK_0 reg, uint8_t value);
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void RegisterSetAndClearBits(Register::BANK_0 reg, uint8_t setbits, uint8_t clearbits);
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void RegisterSetBits(Register::BANK_0 reg, uint8_t setbits);
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void RegisterClearBits(Register::BANK_0 reg, uint8_t clearbits);
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uint16_t FIFOReadCount();
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bool FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples);
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void FIFOReset();
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void ProcessAccel(const hrt_abstime ×tamp_sample, const TransferBuffer *const buffer, uint8_t samples);
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void ProcessGyro(const hrt_abstime ×tamp_sample, const TransferBuffer *const buffer, uint8_t samples);
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void UpdateTemperature();
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uint8_t *_dma_data_buffer{nullptr};
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PX4Accelerometer _px4_accel;
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PX4Gyroscope _px4_gyro;
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perf_counter_t _transfer_perf{perf_alloc(PC_ELAPSED, MODULE_NAME": transfer")};
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perf_counter_t _bad_register_perf{perf_alloc(PC_COUNT, MODULE_NAME": bad register")};
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perf_counter_t _bad_transfer_perf{perf_alloc(PC_COUNT, MODULE_NAME": bad transfer")};
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perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO empty")};
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perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO overflow")};
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perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO reset")};
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perf_counter_t _drdy_interval_perf{perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval")};
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hrt_abstime _reset_timestamp{0};
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hrt_abstime _last_config_check_timestamp{0};
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hrt_abstime _fifo_watermark_interrupt_timestamp{0};
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hrt_abstime _temperature_update_timestamp{0};
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px4::atomic<uint8_t> _data_ready_count{0};
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px4::atomic<uint8_t> _fifo_read_samples{0};
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bool _data_ready_interrupt_enabled{false};
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enum class STATE : uint8_t {
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RESET,
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WAIT_FOR_RESET,
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CONFIGURE,
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FIFO_READ,
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REQUEST_STOP,
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STOPPED,
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};
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px4::atomic<STATE> _state{STATE::RESET};
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uint16_t _fifo_empty_interval_us{500}; // default 500 us / 2000 Hz transfer interval
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uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
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uint8_t _fifo_accel_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))};
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uint8_t _checked_register_bank0{0};
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static constexpr uint8_t size_register_bank0_cfg{11};
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register_bank0_config_t _register_bank0_cfg[size_register_bank0_cfg] {
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// Register | Set bits, Clear bits
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{ Register::BANK_0::INT_CONFIG, INT_CONFIG_BIT::INT1_MODE | INT_CONFIG_BIT::INT1_DRIVE_CIRCUIT, INT_CONFIG_BIT::INT1_POLARITY },
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{ Register::BANK_0::FIFO_CONFIG, FIFO_CONFIG_BIT::FIFO_MODE_STOP_ON_FULL, 0 },
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{ Register::BANK_0::PWR_MGMT0, PWR_MGMT0_BIT::GYRO_MODE_LOW_NOISE | PWR_MGMT0_BIT::ACCEL_MODE_LOW_NOISE, 0 },
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{ Register::BANK_0::GYRO_CONFIG0, GYRO_CONFIG0_BIT::GYRO_ODR_8kHz, Bit7 | Bit6 | Bit5 | Bit3 | Bit2 },
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{ Register::BANK_0::ACCEL_CONFIG0, ACCEL_CONFIG0_BIT::ACCEL_ODR_8kHz, Bit7 | Bit6 | Bit5 | Bit3 | Bit2 },
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{ Register::BANK_0::FIFO_CONFIG1, FIFO_CONFIG1_BIT::FIFO_WM_GT_TH | FIFO_CONFIG1_BIT::FIFO_GYRO_EN | FIFO_CONFIG1_BIT::FIFO_ACCEL_EN, 0 },
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||||||
|
{ Register::BANK_0::FIFO_CONFIG2, 0, 0 }, // FIFO_WM[7:0] set at runtime
|
||||||
|
{ Register::BANK_0::FIFO_CONFIG3, 0, 0 }, // FIFO_WM[11:8] set at runtime
|
||||||
|
{ Register::BANK_0::INT_CONFIG0, INT_CONFIG0_BIT::CLEAR_ON_FIFO_READ, 0 },
|
||||||
|
{ Register::BANK_0::INT_CONFIG1, INT_CONFIG1_BIT::INT_TPULSE_DURATION, 0 },
|
||||||
|
{ Register::BANK_0::INT_SOURCE0, INT_SOURCE0_BIT::FIFO_THS_INT1_EN, 0 },
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
@@ -0,0 +1,248 @@
|
|||||||
|
/****************************************************************************
|
||||||
|
*
|
||||||
|
* Copyright (c) 2020 PX4 Development Team. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name PX4 nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file InvenSense_ICM42688P_registers.hpp
|
||||||
|
*
|
||||||
|
* Invensense ICM-42688-P registers.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#include <cstdint>
|
||||||
|
|
||||||
|
// TODO: move to a central header
|
||||||
|
static constexpr uint8_t Bit0 = (1 << 0);
|
||||||
|
static constexpr uint8_t Bit1 = (1 << 1);
|
||||||
|
static constexpr uint8_t Bit2 = (1 << 2);
|
||||||
|
static constexpr uint8_t Bit3 = (1 << 3);
|
||||||
|
static constexpr uint8_t Bit4 = (1 << 4);
|
||||||
|
static constexpr uint8_t Bit5 = (1 << 5);
|
||||||
|
static constexpr uint8_t Bit6 = (1 << 6);
|
||||||
|
static constexpr uint8_t Bit7 = (1 << 7);
|
||||||
|
|
||||||
|
namespace InvenSense_ICM42688P
|
||||||
|
{
|
||||||
|
static constexpr uint32_t SPI_SPEED = 24 * 1000 * 1000; // 24 MHz SPI
|
||||||
|
static constexpr uint8_t DIR_READ = 0x80;
|
||||||
|
|
||||||
|
static constexpr uint8_t WHOAMI = 0x47;
|
||||||
|
|
||||||
|
static constexpr float TEMPERATURE_SENSITIVITY = 132.48f; // LSB/C
|
||||||
|
static constexpr float ROOM_TEMPERATURE_OFFSET = 25.f; // C
|
||||||
|
|
||||||
|
namespace Register
|
||||||
|
{
|
||||||
|
|
||||||
|
enum class BANK_0 : uint8_t {
|
||||||
|
DEVICE_CONFIG = 0x11,
|
||||||
|
|
||||||
|
INT_CONFIG = 0x14,
|
||||||
|
|
||||||
|
FIFO_CONFIG = 0x16,
|
||||||
|
|
||||||
|
TEMP_DATA1 = 0x1D,
|
||||||
|
TEMP_DATA0 = 0x1E,
|
||||||
|
|
||||||
|
INT_STATUS = 0x2D,
|
||||||
|
FIFO_COUNTH = 0x2E,
|
||||||
|
FIFO_COUNTL = 0x2F,
|
||||||
|
FIFO_DATA = 0x30,
|
||||||
|
|
||||||
|
SIGNAL_PATH_RESET = 0x4B,
|
||||||
|
|
||||||
|
PWR_MGMT0 = 0x4E,
|
||||||
|
GYRO_CONFIG0 = 0x4F,
|
||||||
|
ACCEL_CONFIG0 = 0x50,
|
||||||
|
|
||||||
|
FIFO_CONFIG1 = 0x5F,
|
||||||
|
FIFO_CONFIG2 = 0x60,
|
||||||
|
FIFO_CONFIG3 = 0x61,
|
||||||
|
|
||||||
|
INT_CONFIG0 = 0x63,
|
||||||
|
INT_CONFIG1 = 0x64,
|
||||||
|
INT_SOURCE0 = 0x65,
|
||||||
|
|
||||||
|
WHO_AM_I = 0x75,
|
||||||
|
REG_BANK_SEL = 0x76,
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
//---------------- BANK0 Register bits
|
||||||
|
|
||||||
|
// DEVICE_CONFIG
|
||||||
|
enum DEVICE_CONFIG_BIT : uint8_t {
|
||||||
|
SOFT_RESET_CONFIG = Bit0, //
|
||||||
|
};
|
||||||
|
|
||||||
|
// INT_CONFIG
|
||||||
|
enum INT_CONFIG_BIT : uint8_t {
|
||||||
|
INT1_MODE = Bit2,
|
||||||
|
INT1_DRIVE_CIRCUIT = Bit1,
|
||||||
|
INT1_POLARITY = Bit0,
|
||||||
|
};
|
||||||
|
|
||||||
|
// FIFO_CONFIG
|
||||||
|
enum FIFO_CONFIG_BIT : uint8_t {
|
||||||
|
// 7:6 FIFO_MODE
|
||||||
|
FIFO_MODE_STOP_ON_FULL = Bit7 | Bit6, // 11: STOP-on-FULL Mode
|
||||||
|
};
|
||||||
|
|
||||||
|
// INT_STATUS
|
||||||
|
enum INT_STATUS_BIT : uint8_t {
|
||||||
|
RESET_DONE_INT = Bit4,
|
||||||
|
DATA_RDY_INT = Bit3,
|
||||||
|
FIFO_THS_INT = Bit2,
|
||||||
|
FIFO_FULL_INT = Bit1,
|
||||||
|
};
|
||||||
|
|
||||||
|
// SIGNAL_PATH_RESET
|
||||||
|
enum SIGNAL_PATH_RESET_BIT : uint8_t {
|
||||||
|
ABORT_AND_RESET = Bit3,
|
||||||
|
FIFO_FLUSH = Bit1,
|
||||||
|
};
|
||||||
|
|
||||||
|
// PWR_MGMT0
|
||||||
|
enum PWR_MGMT0_BIT : uint8_t {
|
||||||
|
GYRO_MODE_LOW_NOISE = Bit3 | Bit2, // 11: Places gyroscope in Low Noise (LN) Mode
|
||||||
|
ACCEL_MODE_LOW_NOISE = Bit1 | Bit0, // 11: Places accelerometer in Low Noise (LN) Mode
|
||||||
|
};
|
||||||
|
|
||||||
|
// GYRO_CONFIG0
|
||||||
|
enum GYRO_CONFIG0_BIT : uint8_t {
|
||||||
|
// 7:5 GYRO_FS_SEL
|
||||||
|
GYRO_FS_SEL_2000_DPS = 0, // 0b000 = ±2000 dps
|
||||||
|
GYRO_FS_SEL_1000_DPS = Bit5, // 0b001 = ±1000 dps
|
||||||
|
GYRO_FS_SEL_500_DPS = Bit6, // 0b010 = ±500 dps
|
||||||
|
GYRO_FS_SEL_250_DPS = Bit6 | Bit5, // 0b011 = ±250 dps
|
||||||
|
GYRO_FS_SEL_125_DPS = Bit7, // 0b100 = ±125 dps
|
||||||
|
|
||||||
|
// 3:0 GYRO_ODR
|
||||||
|
GYRO_ODR_32kHz = Bit0, // 0001: 32kHz
|
||||||
|
GYRO_ODR_16kHz = Bit1, // 0010: 16kHz
|
||||||
|
GYRO_ODR_8kHz = Bit1 | Bit0, // 0011: 8kHz
|
||||||
|
GYRO_ODR_4kHz = Bit2, // 0100: 4kHz
|
||||||
|
GYRO_ODR_2kHz = Bit2 | Bit0, // 0101: 2kHz
|
||||||
|
GYRO_ODR_1kHz = Bit2 | Bit1, // 0110: 1kHz (default)
|
||||||
|
};
|
||||||
|
|
||||||
|
// ACCEL_CONFIG0
|
||||||
|
enum ACCEL_CONFIG0_BIT : uint8_t {
|
||||||
|
// 7:5 ACCEL_FS_SEL
|
||||||
|
ACCEL_FS_SEL_16G = 0, // 000: ±16g (default)
|
||||||
|
ACCEL_FS_SEL_8G = Bit5, // 001: ±8g
|
||||||
|
ACCEL_FS_SEL_4G = Bit6, // 010: ±4g
|
||||||
|
ACCEL_FS_SEL_2G = Bit6 | Bit5, // 011: ±2g
|
||||||
|
|
||||||
|
// 3:0 ACCEL_ODR
|
||||||
|
ACCEL_ODR_32kHz = Bit0, // 0001: 32kHz
|
||||||
|
ACCEL_ODR_16kHz = Bit1, // 0010: 16kHz
|
||||||
|
ACCEL_ODR_8kHz = Bit1 | Bit0, // 0011: 8kHz
|
||||||
|
ACCEL_ODR_4kHz = Bit2, // 0100: 4kHz
|
||||||
|
ACCEL_ODR_2kHz = Bit2 | Bit0, // 0101: 2kHz
|
||||||
|
ACCEL_ODR_1kHz = Bit2 | Bit1, // 0110: 1kHz (default)
|
||||||
|
};
|
||||||
|
|
||||||
|
// FIFO_CONFIG1
|
||||||
|
enum FIFO_CONFIG1_BIT : uint8_t {
|
||||||
|
FIFO_RESUME_PARTIAL_RD = Bit6,
|
||||||
|
FIFO_WM_GT_TH = Bit5,
|
||||||
|
|
||||||
|
FIFO_TEMP_EN = Bit2,
|
||||||
|
FIFO_GYRO_EN = Bit1,
|
||||||
|
FIFO_ACCEL_EN = Bit0,
|
||||||
|
};
|
||||||
|
|
||||||
|
// INT_CONFIG0
|
||||||
|
enum INT_CONFIG0_BIT : uint8_t {
|
||||||
|
// 3:2 FIFO_THS_INT_CLEAR
|
||||||
|
CLEAR_ON_FIFO_READ = Bit3,
|
||||||
|
};
|
||||||
|
|
||||||
|
// INT_CONFIG1
|
||||||
|
enum INT_CONFIG1_BIT : uint8_t {
|
||||||
|
INT_TPULSE_DURATION = Bit6, // 0: Interrupt pulse duration is 100μs
|
||||||
|
};
|
||||||
|
|
||||||
|
// INT_SOURCE0
|
||||||
|
enum INT_SOURCE0_BIT : uint8_t {
|
||||||
|
UI_FSYNC_INT1_EN = Bit6,
|
||||||
|
PLL_RDY_INT1_EN = Bit5,
|
||||||
|
RESET_DONE_INT1_EN = Bit4,
|
||||||
|
UI_DRDY_INT1_EN = Bit3,
|
||||||
|
FIFO_THS_INT1_EN = Bit2, // FIFO threshold interrupt routed to INT1
|
||||||
|
FIFO_FULL_INT1_EN = Bit1,
|
||||||
|
UI_AGC_RDY_INT1_EN = Bit0,
|
||||||
|
};
|
||||||
|
|
||||||
|
namespace FIFO
|
||||||
|
{
|
||||||
|
static constexpr size_t SIZE = 2048;
|
||||||
|
|
||||||
|
// FIFO_DATA layout when FIFO_CONFIG1 has FIFO_GYRO_EN and FIFO_ACCEL_EN set
|
||||||
|
|
||||||
|
// Packet 3
|
||||||
|
struct DATA {
|
||||||
|
uint8_t FIFO_Header;
|
||||||
|
uint8_t ACCEL_DATA_X1;
|
||||||
|
uint8_t ACCEL_DATA_X0;
|
||||||
|
uint8_t ACCEL_DATA_Y1;
|
||||||
|
uint8_t ACCEL_DATA_Y0;
|
||||||
|
uint8_t ACCEL_DATA_Z1;
|
||||||
|
uint8_t ACCEL_DATA_Z0;
|
||||||
|
uint8_t GYRO_DATA_X1;
|
||||||
|
uint8_t GYRO_DATA_X0;
|
||||||
|
uint8_t GYRO_DATA_Y1;
|
||||||
|
uint8_t GYRO_DATA_Y0;
|
||||||
|
uint8_t GYRO_DATA_Z1;
|
||||||
|
uint8_t GYRO_DATA_Z0;
|
||||||
|
uint8_t temperature; // Temperature[7:0]
|
||||||
|
uint8_t timestamp_l;
|
||||||
|
uint8_t timestamp_h;
|
||||||
|
};
|
||||||
|
|
||||||
|
// With FIFO_ACCEL_EN and FIFO_GYRO_EN header should be 8’b_0110_10xx
|
||||||
|
enum FIFO_HEADER_BIT : uint8_t {
|
||||||
|
HEADER_MSG = Bit7, // 1: FIFO is empty
|
||||||
|
HEADER_ACCEL = Bit6,
|
||||||
|
HEADER_GYRO = Bit5,
|
||||||
|
HEADER_20 = Bit4,
|
||||||
|
HEADER_TIMESTAMP_FSYNC = Bit3 | Bit2,
|
||||||
|
HEADER_ODR_ACCEL = Bit1,
|
||||||
|
HEADER_ODR_GYRO = Bit0,
|
||||||
|
};
|
||||||
|
|
||||||
|
}
|
||||||
|
} // namespace InvenSense_ICM42688P
|
||||||
@@ -0,0 +1,151 @@
|
|||||||
|
/****************************************************************************
|
||||||
|
*
|
||||||
|
* Copyright (c) 2020 PX4 Development Team. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name PX4 nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#include "ICM42688P.hpp"
|
||||||
|
|
||||||
|
#include <px4_platform_common/getopt.h>
|
||||||
|
|
||||||
|
namespace icm42688p
|
||||||
|
{
|
||||||
|
ICM42688P *g_dev{nullptr};
|
||||||
|
|
||||||
|
static int start(enum Rotation rotation)
|
||||||
|
{
|
||||||
|
if (g_dev != nullptr) {
|
||||||
|
PX4_WARN("already started");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
// create the driver
|
||||||
|
#if defined(PX4_SPI_BUS_SENSORS2) && defined(PX4_SPIDEV_ICM_42688)
|
||||||
|
g_dev = new ICM42688P(PX4_SPI_BUS_SENSORS2, PX4_SPIDEV_ICM_42688, rotation);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (g_dev == nullptr) {
|
||||||
|
PX4_ERR("driver start failed");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!g_dev->Init()) {
|
||||||
|
PX4_ERR("driver init failed");
|
||||||
|
delete g_dev;
|
||||||
|
g_dev = nullptr;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stop()
|
||||||
|
{
|
||||||
|
if (g_dev == nullptr) {
|
||||||
|
PX4_WARN("driver not running");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
g_dev->Stop();
|
||||||
|
delete g_dev;
|
||||||
|
g_dev = nullptr;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int reset()
|
||||||
|
{
|
||||||
|
if (g_dev == nullptr) {
|
||||||
|
PX4_WARN("driver not running");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
return g_dev->Reset();
|
||||||
|
}
|
||||||
|
|
||||||
|
static int status()
|
||||||
|
{
|
||||||
|
if (g_dev == nullptr) {
|
||||||
|
PX4_INFO("driver not running");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
g_dev->PrintInfo();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int usage()
|
||||||
|
{
|
||||||
|
PX4_INFO("missing command: try 'start', 'stop', 'reset', 'status'");
|
||||||
|
PX4_INFO("options:");
|
||||||
|
PX4_INFO(" -R rotation");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace icm42688p
|
||||||
|
|
||||||
|
extern "C" int icm42688p_main(int argc, char *argv[])
|
||||||
|
{
|
||||||
|
enum Rotation rotation = ROTATION_NONE;
|
||||||
|
int myoptind = 1;
|
||||||
|
int ch = 0;
|
||||||
|
const char *myoptarg = nullptr;
|
||||||
|
|
||||||
|
// start options
|
||||||
|
while ((ch = px4_getopt(argc, argv, "R:", &myoptind, &myoptarg)) != EOF) {
|
||||||
|
switch (ch) {
|
||||||
|
case 'R':
|
||||||
|
rotation = (enum Rotation)atoi(myoptarg);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
return icm42688p::usage();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
const char *verb = argv[myoptind];
|
||||||
|
|
||||||
|
if (!strcmp(verb, "start")) {
|
||||||
|
return icm42688p::start(rotation);
|
||||||
|
|
||||||
|
} else if (!strcmp(verb, "stop")) {
|
||||||
|
return icm42688p::stop();
|
||||||
|
|
||||||
|
} else if (!strcmp(verb, "status")) {
|
||||||
|
return icm42688p::status();
|
||||||
|
|
||||||
|
} else if (!strcmp(verb, "reset")) {
|
||||||
|
return icm42688p::reset();
|
||||||
|
}
|
||||||
|
|
||||||
|
return icm42688p::usage();
|
||||||
|
}
|
||||||
Reference in New Issue
Block a user