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stm32/drv_io_timer:GTIM_CCER_CC1NP not on all STM32 HW

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The F1 series GTIMs to not have GTIM_CCER_CC1NP.
   This bug fix tracks the upstream change that
   made GTIM_CCER_CC1NP conditional on the chip.
This commit is contained in:
David Sidrane
2018-11-29 12:42:16 -08:00
parent 7ba81fac4b
commit 1f54214224
1 changed files with 7 additions and 1 deletions
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src/drivers/stm32/drv_io_timer.c
+7 -1
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@@ -63,6 +63,12 @@
#include <stm32_gpio.h>
#include <stm32_tim.h>
#if defined(HAVE_GTIM_CCXNP)
#define HW_GTIM_CCER_CC1NP GTIM_CCER_CC1NP
#else
# define HW_GTIM_CCER_CC1NP 0
#endif
#define arraySize(a) (sizeof((a))/sizeof(((a)[0])))
/* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
@@ -729,7 +735,7 @@ int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode,
/* on PWM Out ccer_setbits is 0 */
clearbits = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP) << (shifts * CCER_C1_NUM_BITS);
clearbits = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | HW_GTIM_CCER_CC1NP) << (shifts * CCER_C1_NUM_BITS);
setbits = ccer_setbits << (shifts * CCER_C1_NUM_BITS);
rvalue = rCCER(timer);
rvalue &= ~clearbits;