mirror of
https://github.com/lvgl/lvgl.git
synced 2026-09-21 02:04:52 +08:00
fix(gpu): fix STM GPU drivers for some variants (#4004)
This commit is contained in:
Morgan Diepart
+1
-1
@@ -183,7 +183,7 @@
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#define LV_USE_GPU_STM32_DMA2D 0
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#if LV_USE_GPU_STM32_DMA2D
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/*Must be defined to include path of CMSIS header of target processor
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e.g. "stm32f769xx.h" or "stm32f429xx.h"*/
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e.g. "stm32f7xx.h" or "stm32f4xx.h"*/
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#define LV_GPU_DMA2D_CMSIS_INCLUDE
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#endif
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@@ -343,7 +343,9 @@ LV_STM32_DMA2D_STATIC void _lv_draw_stm32_dma2d_blend_fill(const lv_color_t * de
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DMA2D->CR = 0x3UL << DMA2D_CR_MODE_Pos; // Register-to-memory (no FG nor BG, only output stage active)
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DMA2D->OPFCCR = LvglColorFormat;
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#if defined(DMA2D_OPFCCR_RBS_Pos)
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DMA2D->OPFCCR |= (RBS_BIT << DMA2D_OPFCCR_RBS_Pos);
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#endif
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DMA2D->OMAR = (uint32_t)(dest_buf + (dest_stride * draw_area->y1) + draw_area->x1);
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DMA2D->OOR = dest_stride - draw_width; // out buffer offset
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// Note: unlike FGCOLR and BGCOLR, OCOLR bits must match DMA2D_OUTPUT_COLOR, alpha can be specified
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@@ -370,14 +372,18 @@ LV_STM32_DMA2D_STATIC void _lv_draw_stm32_dma2d_blend_fill(const lv_color_t * de
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DMA2D->FGCOLR = lv_color_to32(color) & 0x00ffffff; // swap FGCOLR R/B bits if FGPFCCR.RBS (RBS_BIT) bit is set
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DMA2D->BGPFCCR = LvglColorFormat;
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#if defined(DMA2D_BGPFCCR_RBS_Pos)
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DMA2D->BGPFCCR |= (RBS_BIT << DMA2D_BGPFCCR_RBS_Pos);
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#endif
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DMA2D->BGMAR = (uint32_t)(dest_buf + (dest_stride * draw_area->y1) + draw_area->x1);
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DMA2D->BGOR = dest_stride - draw_width;
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DMA2D->BGCOLR = 0; // used in A4 and A8 modes only
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_lv_gpu_stm32_dma2d_clean_cache(DMA2D->BGMAR, DMA2D->BGOR, draw_width, draw_height, sizeof(lv_color_t));
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DMA2D->OPFCCR = LvglColorFormat;
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#if defined(DMA2D_OPFCCR_RBS_Pos)
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DMA2D->OPFCCR |= (RBS_BIT << DMA2D_OPFCCR_RBS_Pos);
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#endif
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DMA2D->OMAR = DMA2D->BGMAR;
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DMA2D->OOR = DMA2D->BGOR;
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DMA2D->OCOLR = 0;
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@@ -454,15 +460,18 @@ LV_STM32_DMA2D_STATIC void _lv_draw_stm32_dma2d_blend_map(const lv_color_t * des
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DMA2D->FGPFCCR |= (0x1UL << DMA2D_FGPFCCR_AM_Pos);
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}
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}
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#if defined(DMA2D_FGPFCCR_RBS_Pos)
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DMA2D->FGPFCCR |= (RBS_BIT << DMA2D_FGPFCCR_RBS_Pos);
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#endif
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DMA2D->FGMAR = ((uint32_t)src_buf) + srcBpp * ((src_stride * src_offset->y) + src_offset->x);
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DMA2D->FGOR = src_stride - draw_width;
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DMA2D->FGCOLR = 0; // used in A4 and A8 modes only
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_lv_gpu_stm32_dma2d_clean_cache(DMA2D->FGMAR, DMA2D->FGOR, draw_width, draw_height, srcBpp);
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DMA2D->OPFCCR = LvglColorFormat;
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#if defined(DMA2D_OPFCCR_RBS_Pos)
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DMA2D->OPFCCR |= (RBS_BIT << DMA2D_OPFCCR_RBS_Pos);
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#endif
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DMA2D->OMAR = (uint32_t)(dest_buf + (dest_stride * draw_area->y1) + draw_area->x1);
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DMA2D->OOR = dest_stride - draw_width;
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DMA2D->OCOLR = 0;
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@@ -470,7 +479,9 @@ LV_STM32_DMA2D_STATIC void _lv_draw_stm32_dma2d_blend_map(const lv_color_t * des
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if(opa != 0xff || bitmapHasOpacity) {
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// use background (BG*) registers
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DMA2D->BGPFCCR = LvglColorFormat;
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#if defined(DMA2D_BGPFCCR_RBS_Pos)
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DMA2D->BGPFCCR |= (RBS_BIT << DMA2D_BGPFCCR_RBS_Pos);
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#endif
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DMA2D->BGMAR = DMA2D->OMAR;
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DMA2D->BGOR = DMA2D->OOR;
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DMA2D->BGCOLR = 0; // used in A4 and A8 modes only
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@@ -514,14 +525,18 @@ LV_STM32_DMA2D_STATIC void _lv_draw_stm32_dma2d_blend_paint(const lv_color_t * d
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_lv_gpu_stm32_dma2d_clean_cache(DMA2D->FGMAR, DMA2D->FGOR, draw_width, draw_height, sizeof(lv_opa_t));
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DMA2D->BGPFCCR = LvglColorFormat;
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#if defined(DMA2D_BGPFCCR_RBS_Pos)
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DMA2D->BGPFCCR |= (RBS_BIT << DMA2D_BGPFCCR_RBS_Pos);
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#endif
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DMA2D->BGMAR = (uint32_t)(dest_buf + (dest_stride * draw_area->y1) + draw_area->x1);
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DMA2D->BGOR = dest_stride - draw_width;
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DMA2D->BGCOLR = 0; // used in A4 and A8 modes only
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_lv_gpu_stm32_dma2d_clean_cache(DMA2D->BGMAR, DMA2D->BGOR, draw_width, draw_height, sizeof(lv_color_t));
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DMA2D->OPFCCR = LvglColorFormat;
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#if defined(DMA2D_OPFCCR_RBS_Pos)
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DMA2D->OPFCCR |= (RBS_BIT << DMA2D_OPFCCR_RBS_Pos);
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#endif
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DMA2D->OMAR = DMA2D->BGMAR;
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DMA2D->OOR = DMA2D->BGOR;
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DMA2D->OCOLR = 0;
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@@ -547,7 +562,9 @@ LV_STM32_DMA2D_STATIC void _lv_draw_stm32_dma2d_copy_buffer(const lv_color_t * d
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DMA2D->CR = 0x0UL; // Memory-to-memory (FG fetch only)
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DMA2D->FGPFCCR = LvglColorFormat;
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#if defined(DMA2D_FGPFCCR_RBS_Pos)
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DMA2D->FGPFCCR |= (RBS_BIT << DMA2D_FGPFCCR_RBS_Pos);
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#endif
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DMA2D->FGMAR = (uint32_t)(src_buf + (src_stride * src_offset->y) + src_offset->x);
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DMA2D->FGOR = src_stride - draw_width;
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DMA2D->FGCOLR = 0; // used in A4 and A8 modes only
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@@ -556,7 +573,9 @@ LV_STM32_DMA2D_STATIC void _lv_draw_stm32_dma2d_copy_buffer(const lv_color_t * d
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// Note BG* registers do not need to be set up since BG is not used
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DMA2D->OPFCCR = LvglColorFormat;
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#if defined(DMA2D_OPFCCR_RBS_Pos)
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DMA2D->OPFCCR |= (RBS_BIT << DMA2D_OPFCCR_RBS_Pos);
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#endif
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DMA2D->OMAR = (uint32_t)(dest_buf + (dest_stride * draw_area->y1) + draw_area->x1);
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DMA2D->OOR = dest_stride - draw_width;
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DMA2D->OCOLR = 0;
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@@ -615,6 +634,7 @@ LV_STM32_DMA2D_STATIC void _lv_gpu_stm32_dma2d_await_dma_transfer_finish(lv_disp
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LV_STM32_DMA2D_STATIC void _lv_gpu_stm32_dma2d_invalidate_cache(uint32_t address, lv_coord_t offset, lv_coord_t width,
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lv_coord_t height, uint8_t pixel_size)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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if(((SCB->CCR) & SCB_CCR_DC_Msk) == 0) return; // L1 data cache is disabled
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uint16_t stride = pixel_size * (width + offset); // in bytes
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uint16_t ll = pixel_size * width; // line length in bytes
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@@ -640,11 +660,13 @@ LV_STM32_DMA2D_STATIC void _lv_gpu_stm32_dma2d_invalidate_cache(uint32_t address
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__DSB();
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__ISB();
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#endif
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}
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LV_STM32_DMA2D_STATIC void _lv_gpu_stm32_dma2d_clean_cache(uint32_t address, lv_coord_t offset, lv_coord_t width,
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lv_coord_t height, uint8_t pixel_size)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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if(((SCB->CCR) & SCB_CCR_DC_Msk) == 0) return; // L1 data cache is disabled
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uint16_t stride = pixel_size * (width + offset); // in bytes
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uint16_t ll = pixel_size * width; // line length in bytes
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@@ -669,6 +691,7 @@ LV_STM32_DMA2D_STATIC void _lv_gpu_stm32_dma2d_clean_cache(uint32_t address, lv_
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__DSB();
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__ISB();
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#endif
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}
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// initialize µs timer
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@@ -679,8 +702,9 @@ LV_STM32_DMA2D_STATIC bool _lv_gpu_stm32_dwt_init(void)
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// enable TRC
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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#if defined(__CORTEX_M) && (__CORTEX_M == 7U)
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DWT->LAR = 0xC5ACCE55;
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#endif
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// disable clock cycle counter
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DWT->CTRL &= ~DWT_CTRL_CYCCNTENA_Msk;
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// enable clock cycle counter
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@@ -435,7 +435,7 @@
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#endif
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#if LV_USE_GPU_STM32_DMA2D
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/*Must be defined to include path of CMSIS header of target processor
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e.g. "stm32f769xx.h" or "stm32f429xx.h"*/
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e.g. "stm32f7xx.h" or "stm32f4xx.h"*/
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#ifndef LV_GPU_DMA2D_CMSIS_INCLUDE
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#ifdef CONFIG_LV_GPU_DMA2D_CMSIS_INCLUDE
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#define LV_GPU_DMA2D_CMSIS_INCLUDE CONFIG_LV_GPU_DMA2D_CMSIS_INCLUDE
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