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Release 6.1.7

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This commit is contained in:
Bo Chen
2021-06-02 06:45:05 +00:00
parent d759e6bb9e
commit f5056f4923
1269 changed files with 57325 additions and 55178 deletions
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common/inc/tx_api.h
+16 -2
View File
@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE C */
/* 6.1.6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -69,6 +69,9 @@
/* 04-02-2021 Scott Larson Modified comment(s), and */
/* update patch number, */
/* resulting in version 6.1.6 */
/* 06-02-2021 Yuxin Zhou Modified comment(s), added */
/* Execution Profile support, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
@@ -101,7 +104,7 @@ extern "C" {
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 1
#define THREADX_PATCH_VERSION 6
#define THREADX_PATCH_VERSION 7
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX
@@ -498,6 +501,17 @@ typedef struct TX_THREAD_STRUCT
is typically defined to whitespace in tx_port.h. */
TX_THREAD_EXTENSION_3
/* Define variables for supporting execution profile. */
/* Note that in ThreadX 5.x, user would define TX_ENABLE_EXECUTION_CHANGE_NOTIFY and use TX_THREAD_EXTENSION_3
to define the following two variables.
For Azure RTOS 6, user shall use TX_EXECUTION_PROFILE_ENABLE instead of TX_ENABLE_EXECUTION_CHANGE_NOTIFY,
and SHALL NOT add variables to TX_THREAD_EXTENSION_3. */
#if (defined(TX_EXECUTION_PROFILE_ENABLE) && !defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY))
unsigned long long tx_thread_execution_time_total;
unsigned long long tx_thread_execution_time_last_start;
#endif
/* Define suspension sequence number. This is used to ensure suspension is still valid when
cleanup routine executes. */
ULONG tx_thread_suspension_sequence;
common/src/tx_byte_pool_search.c
+13 -11
View File
@@ -35,7 +35,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_byte_pool_search PORTABLE C */
/* 6.1 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -76,9 +76,12 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 Yuxin Zhou Modified comment(s), */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 Yuxin Zhou Modified comment(s), */
/* resulting in version 6.1 */
/* 06-02-2021 Scott Larson Improve possible free bytes */
/* calculation, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size)
@@ -96,13 +99,16 @@ UINT first_free_block_found = TX_FALSE;
TX_THREAD *thread_ptr;
ALIGN_TYPE *free_ptr;
UCHAR *work_ptr;
ULONG total_theoretical_available;
/* Disable interrupts. */
TX_DISABLE
/* First, determine if there are enough bytes in the pool. */
if (memory_size >= pool_ptr -> tx_byte_pool_available)
/* Theoretical bytes available = free bytes + ((fragments-2) * overhead of each block) */
total_theoretical_available = pool_ptr -> tx_byte_pool_available + ((pool_ptr -> tx_byte_pool_fragments - 2) * ((sizeof(UCHAR *)) + (sizeof(ALIGN_TYPE))));
if (memory_size >= total_theoretical_available)
{
/* Restore interrupts. */
@@ -146,10 +152,9 @@ UCHAR *work_ptr;
/* Determine if this is the first free block. */
if (first_free_block_found == TX_FALSE)
{
/* This is the first free block. */
pool_ptr->tx_byte_pool_search = current_ptr;
/* Set the flag to indicate we have found the first free
block. */
first_free_block_found = TX_TRUE;
@@ -178,7 +183,7 @@ UCHAR *work_ptr;
/* Clear the available bytes variable. */
available_bytes = ((ULONG) 0);
/* Not enough memory, check to see if the neighbor is
/* Not enough memory, check to see if the neighbor is
free and can be merged. */
work_ptr = TX_UCHAR_POINTER_ADD(next_ptr, (sizeof(UCHAR *)));
free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(work_ptr);
@@ -207,14 +212,12 @@ UCHAR *work_ptr;
/* See if the search pointer is affected. */
if (pool_ptr -> tx_byte_pool_search == next_ptr)
{
/* Yes, update the search pointer. */
pool_ptr -> tx_byte_pool_search = current_ptr;
}
}
else
{
/* Neighbor is not free so we can skip over it! */
next_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(next_ptr);
current_ptr = *next_block_link_ptr;
@@ -222,7 +225,6 @@ UCHAR *work_ptr;
/* Decrement the examined block count to account for this one. */
if (examine_blocks != ((UINT) 0))
{
examine_blocks--;
#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
@@ -297,7 +299,7 @@ UCHAR *work_ptr;
/* Update the current pointer to point at the newly created block. */
*this_block_link_ptr = next_ptr;
/* Set available equal to memory size for subsequent calculation. */
available_bytes = memory_size;
common/src/tx_thread_create.c
+12 -1
View File
@@ -36,7 +36,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_create PORTABLE C */
/* 6.1 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -84,6 +84,9 @@
/* changed stack calculations */
/* to use ALIGN_TYPE integers, */
/* resulting in version 6.1 */
/* 06-02-2021 William E. Lamie Modified comment(s), and */
/* supported TX_MISRA_ENABLE, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input,
@@ -120,7 +123,11 @@ ALIGN_TYPE updated_stack_start;
stack_size = ((stack_size/(sizeof(ULONG))) * (sizeof(ULONG))) - (sizeof(ULONG));
/* Ensure the starting stack address is evenly aligned. */
#ifdef TX_MISRA_ENABLE
new_stack_start = TX_POINTER_TO_ULONG_CONVERT(stack_start);
#else
new_stack_start = TX_POINTER_TO_ALIGN_TYPE_CONVERT(stack_start);
#endif /* TX_MISRA_ENABLE */
updated_stack_start = ((((ULONG) new_stack_start) + ((sizeof(ULONG)) - ((ULONG) 1)) ) & (~((sizeof(ULONG)) - ((ULONG) 1))));
/* Determine if the starting stack address is different. */
@@ -132,7 +139,11 @@ ALIGN_TYPE updated_stack_start;
}
/* Update the starting stack pointer. */
#ifdef TX_MISRA_ENABLE
stack_start = TX_ULONG_TO_POINTER_CONVERT(updated_stack_start);
#else
stack_start = TX_ALIGN_TYPE_TO_POINTER_CONVERT(updated_stack_start);
#endif /* TX_MISRA_ENABLE */
#endif
/* Prepare the thread control block prior to placing it on the created
common/src/tx_thread_initialize.c
+4 -1
View File
@@ -310,6 +310,9 @@ const CHAR _tx_thread_special_string[] =
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 Yuxin Zhou Modified comment(s), */
/* resulting in version 6.1 */
/* 06-02-2021 Yuxin Zhou Modified comment(s), added */
/* Execution Profile support, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
VOID _tx_thread_initialize(VOID)
@@ -439,7 +442,7 @@ VOID _tx_thread_initialize(VOID)
#ifdef TX_ENABLE_EVENT_TRACE
| (((ULONG) 1) << 8)
#endif
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)
| (((ULONG) 1) << 7)
#endif
#if TX_PORT_SPECIFIC_BUILD_OPTIONS != 0
common/src/tx_thread_stack_error_handler.c
+8 -1
View File
@@ -26,6 +26,7 @@
/* Include necessary system files. */
#include "tx_api.h"
#ifndef TX_PORT_THREAD_STACK_ERROR_HANDLER
#if defined(TX_MISRA_ENABLE) || defined(TX_ENABLE_STACK_CHECKING)
#include "tx_thread.h"
@@ -35,7 +36,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_error_handler PORTABLE C */
/* 6.1.1 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -72,6 +73,11 @@
/* 10-16-2020 William E. Lamie Modified comment(s), */
/* fixed link issue, */
/* resulting in version 6.1.1 */
/* 06-02-2021 William E. Lamie Modified comment(s), */
/* fixed link issue, added */
/* conditional compilation */
/* for ARMv8-M (Cortex M23/33) */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr)
@@ -111,3 +117,4 @@ TX_INTERRUPT_SAVE_AREA
}
#endif /* TX_MISRA_ENABLE */
#endif /* TX_PORT_THREAD_STACK_ERROR_HANDLER */
common/src/tx_thread_stack_error_notify.c
+7 -1
View File
@@ -26,6 +26,7 @@
/* Include necessary system files. */
#include "tx_api.h"
#ifndef TX_PORT_THREAD_STACK_ERROR_NOTIFY
#include "tx_thread.h"
#ifdef TX_ENABLE_STACK_CHECKING
#include "tx_trace.h"
@@ -37,7 +38,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_error_notify PORTABLE C */
/* 6.1 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -74,6 +75,10 @@
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 Yuxin Zhou Modified comment(s), */
/* resulting in version 6.1 */
/* 06-02-2021 Yuxin Zhou Modified comment(s), added */
/* conditional compilation */
/* for ARMv8-M (Cortex M23/33) */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr))
@@ -125,3 +130,4 @@ TX_INTERRUPT_SAVE_AREA
#endif
}
#endif /* TX_PORT_THREAD_STACK_ERROR_NOTIFY */
common_modules/module_manager/src/txm_module_manager_thread_create.c
+16 -18
View File
@@ -108,10 +108,8 @@ UINT core_index;
#endif
TX_THREAD *next_thread;
TX_THREAD *previous_thread;
#ifndef TX_DISABLE_PREEMPTION_THRESHOLD
TX_THREAD *saved_thread_ptr;
UINT saved_threshold = ((UINT) 0);
#endif
UCHAR *temp_ptr;
#ifdef TX_ENABLE_STACK_CHECKING
ALIGN_TYPE new_stack_start;
@@ -155,7 +153,7 @@ ULONG i;
/* Determine if this thread matches the thread in the list. */
if (thread_ptr == next_thread)
{
break;
}
@@ -177,7 +175,7 @@ ULONG i;
/* Decrement the preempt disable flag. */
_tx_thread_preempt_disable--;
/* Restore interrupts. */
TX_RESTORE
@@ -260,11 +258,11 @@ ULONG i;
/* Check for interrupt call. */
if (TX_THREAD_GET_SYSTEM_STATE() != 0)
{
/* Now, make sure the call is from an interrupt and not initialization. */
if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
{
/* Invalid caller of this function, return appropriate error code. */
return(TX_CALLER_ERROR);
}
@@ -280,7 +278,7 @@ ULONG i;
#ifdef TX_ENABLE_STACK_CHECKING
/* Ensure that there are two ULONG of 0xEF patterns at the top and
/* Ensure that there are two ULONG of 0xEF patterns at the top and
bottom of the thread's stack. This will be used to check for stack
overflow conditions during run-time. */
stack_size = ((stack_size/(sizeof(ULONG))) * (sizeof(ULONG))) - (sizeof(ULONG));
@@ -292,7 +290,7 @@ ULONG i;
/* Determine if the starting stack address is different. */
if (new_stack_start != updated_stack_start)
{
/* Yes, subtract another ULONG from the size to avoid going past the stack area. */
stack_size = stack_size - (sizeof(ULONG));
}
@@ -301,7 +299,7 @@ ULONG i;
stack_start = TX_ALIGN_TYPE_TO_POINTER_CONVERT(updated_stack_start);
#endif
/* Allocate the thread entry information at the top of thread's stack - Leaving one
/* Allocate the thread entry information at the top of thread's stack - Leaving one
ULONG worth of 0xEF pattern between the actual stack and the entry info structure. */
stack_size = stack_size - (sizeof(TXM_MODULE_THREAD_ENTRY_INFO) + (3*sizeof(ULONG)));
@@ -368,7 +366,7 @@ ULONG i;
/* Default thread creation such that core0 is the only allowed core for execution, i.e., bit 1 is set to exclude core1. */
thread_ptr -> tx_thread_smp_cores_excluded = (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE);
thread_ptr -> tx_thread_smp_cores_allowed = 1;
/* Default the timers to run on core 0 as well. */
thread_ptr -> tx_thread_timer.tx_timer_internal_smp_cores_excluded = (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE);
@@ -420,11 +418,11 @@ ULONG i;
TX_THREAD_CREATE_INTERNAL_EXTENSION(thread_ptr)
/* Setup pointer to the thread entry information structure, which will live at the top of each
module thread's stack. This will allow the module thread entry function to avoid direct
module thread's stack. This will allow the module thread entry function to avoid direct
access to the actual thread control block. */
thread_entry_info = (TXM_MODULE_THREAD_ENTRY_INFO *) (((UCHAR *) thread_ptr -> tx_thread_stack_end) + (2*sizeof(ULONG)) + 1);
thread_entry_info = (TXM_MODULE_THREAD_ENTRY_INFO *) (((ALIGN_TYPE)(thread_entry_info)) & (~0x3));
/* Build the thread entry information structure. */
thread_entry_info -> txm_module_thread_entry_info_thread = thread_ptr;
thread_entry_info -> txm_module_thread_entry_info_module = module_instance;
@@ -458,7 +456,7 @@ ULONG i;
with the actual stack pointer at the end of stack build. */
thread_ptr -> tx_thread_stack_ptr = (VOID *) thread_entry_info;
/* Call the target specific stack frame building routine to build the
/* Call the target specific stack frame building routine to build the
thread's initial stack and to setup the actual stack pointer in the
control block. */
_txm_module_manager_thread_stack_build(thread_ptr, shell_function);
@@ -648,22 +646,22 @@ ULONG i;
/* Yes, this create call was made from initialization. */
/* Pickup the current thread execute pointer, which corresponds to the
highest priority thread ready to execute. Interrupt lockout is
not required, since interrupts are assumed to be disabled during
highest priority thread ready to execute. Interrupt lockout is
not required, since interrupts are assumed to be disabled during
initialization. */
saved_thread_ptr = _tx_thread_execute_ptr;
/* Determine if there is thread ready for execution. */
if (saved_thread_ptr != TX_NULL)
{
/* Yes, a thread is ready for execution when initialization completes. */
/* Save the current preemption-threshold. */
saved_threshold = saved_thread_ptr -> tx_thread_preempt_threshold;
/* For initialization, temporarily set the preemption-threshold to the
priority level to make sure the highest-priority thread runs once
/* For initialization, temporarily set the preemption-threshold to the
priority level to make sure the highest-priority thread runs once
initialization is complete. */
saved_thread_ptr -> tx_thread_preempt_threshold = saved_thread_ptr -> tx_thread_priority;
}
common_smp/inc/tx_api.h
+14 -2
View File
@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE SMP */
/* 6.1.6 */
/* 6.1.7 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,6 +58,9 @@
/* 04-02-2021 Scott Larson Modified comment(s), and */
/* update patch number, */
/* resulting in version 6.1.6 */
/* 06-02-2021 Scott Larson Added options for multiple */
/* block pool search & delay, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
@@ -88,6 +91,15 @@ extern "C" {
#endif
/* Define default block pool search and delay values. */
#ifndef TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH
#define TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH 20
#endif
#ifndef TX_BTYE_POOL_DELAY_VALUE
#define TX_BYTE_POOL_DELAY_VALUE 3
#endif
/* Define basic constants for the ThreadX kernel. */
@@ -97,7 +109,7 @@ extern "C" {
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 1
#define THREADX_PATCH_VERSION 6
#define THREADX_PATCH_VERSION 7
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX
common_smp/inc/tx_user_sample.h
+15
View File
@@ -49,6 +49,9 @@
/* added option to remove */
/* FileX pointer, */
/* resulting in version 6.1.5 */
/* 06-02-2021 Scott Larson Added options for multiple */
/* block pool search & delay, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
@@ -268,5 +271,17 @@
#define TX_TIMER_ENABLE_PERFORMANCE_INFO
*/
/* Override options for byte pool searches of multiple blocks. */
/*
#define TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH 20
*/
/* Override options for byte pool search delay to avoid thrashing. */
/*
#define TX_BYTE_POOL_DELAY_VALUE 3
*/
#endif
common_smp/src/tx_byte_pool_search.c
+76 -62
View File
@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Byte Pool */
/** */
@@ -30,53 +30,57 @@
#include "tx_byte_pool.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_byte_pool_search PORTABLE SMP */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_byte_pool_search PORTABLE SMP */
/* 6.1.7 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function searches a byte pool for a memory block to satisfy */
/* the requested number of bytes. Merging of adjacent free blocks */
/* takes place during the search and a split of the block that */
/* satisfies the request may occur before this function returns. */
/* */
/* It is assumed that this function is called with interrupts enabled */
/* and with the tx_pool_owner field set to the thread performing the */
/* search. Also note that the search can occur during allocation and */
/* release of a memory block. */
/* */
/* INPUT */
/* */
/* pool_ptr Pointer to pool control block */
/* memory_size Number of bytes required */
/* */
/* OUTPUT */
/* */
/* UCHAR * Pointer to the allocated memory, */
/* if successful. Otherwise, a */
/* NULL is returned */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_byte_allocate Allocate bytes of memory */
/* _tx_byte_release Release bytes of memory */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function searches a byte pool for a memory block to satisfy */
/* the requested number of bytes. Merging of adjacent free blocks */
/* takes place during the search and a split of the block that */
/* satisfies the request may occur before this function returns. */
/* */
/* It is assumed that this function is called with interrupts enabled */
/* and with the tx_pool_owner field set to the thread performing the */
/* search. Also note that the search can occur during allocation and */
/* release of a memory block. */
/* */
/* INPUT */
/* */
/* pool_ptr Pointer to pool control block */
/* memory_size Number of bytes required */
/* */
/* OUTPUT */
/* */
/* UCHAR * Pointer to the allocated memory, */
/* if successful. Otherwise, a */
/* NULL is returned */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_byte_allocate Allocate bytes of memory */
/* _tx_byte_release Release bytes of memory */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 06-02-2021 Scott Larson Improve possible free bytes */
/* calculation, and reduced */
/* number of search resets, */
/* resulting in version 6.1.7 */
/* */
/**************************************************************************/
UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size)
@@ -84,17 +88,18 @@ UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size)
TX_INTERRUPT_SAVE_AREA
UCHAR *current_ptr;
UCHAR *next_ptr;
UCHAR *current_ptr;
UCHAR *next_ptr;
UCHAR **this_block_link_ptr;
UCHAR **next_block_link_ptr;
ULONG available_bytes;
UINT examine_blocks;
ULONG available_bytes;
UINT examine_blocks;
UINT first_free_block_found = TX_FALSE;
TX_THREAD *thread_ptr;
ALIGN_TYPE *free_ptr;
UCHAR *work_ptr;
volatile ULONG delay_count;
ULONG total_theoretical_available;
#ifdef TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH
UINT blocks_searched = ((UINT) 0);
#endif
@@ -104,7 +109,9 @@ UINT blocks_searched = ((UINT) 0);
TX_DISABLE
/* First, determine if there are enough bytes in the pool. */
if (memory_size >= pool_ptr -> tx_byte_pool_available)
/* Theoretical bytes available = free bytes + ((fragments-2) * overhead of each block) */
total_theoretical_available = pool_ptr -> tx_byte_pool_available + ((pool_ptr -> tx_byte_pool_fragments - 2) * ((sizeof(UCHAR *)) + (sizeof(ALIGN_TYPE))));
if (memory_size >= total_theoretical_available)
{
/* Restore interrupts. */
@@ -121,7 +128,7 @@ UINT blocks_searched = ((UINT) 0);
/* Setup ownership of the byte pool. */
pool_ptr -> tx_byte_pool_owner = thread_ptr;
/* Walk through the memory pool in search for a large enough block. */
current_ptr = pool_ptr -> tx_byte_pool_search;
examine_blocks = pool_ptr -> tx_byte_pool_fragments + ((UINT) 1);
@@ -148,7 +155,6 @@ UINT blocks_searched = ((UINT) 0);
/* Determine if this is the first free block. */
if (first_free_block_found == TX_FALSE)
{
/* This is the first free block. */
pool_ptr->tx_byte_pool_search = current_ptr;
@@ -171,7 +177,6 @@ UINT blocks_searched = ((UINT) 0);
has been satisfied! */
if (available_bytes >= memory_size)
{
/* Get out of the search loop! */
break;
}
@@ -181,7 +186,7 @@ UINT blocks_searched = ((UINT) 0);
/* Clear the available bytes variable. */
available_bytes = ((ULONG) 0);
/* Not enough memory, check to see if the neighbor is
/* Not enough memory, check to see if the neighbor is
free and can be merged. */
work_ptr = TX_UCHAR_POINTER_ADD(next_ptr, (sizeof(UCHAR *)));
free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(work_ptr);
@@ -210,17 +215,15 @@ UINT blocks_searched = ((UINT) 0);
/* See if the search pointer is affected. */
if (pool_ptr -> tx_byte_pool_search == next_ptr)
{
/* Yes, update the search pointer. */
pool_ptr -> tx_byte_pool_search = current_ptr;
}
}
else
{
/* Neighbor is not free so we can skip over it! */
next_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(next_ptr);
current_ptr = *next_block_link_ptr;
current_ptr = *next_block_link_ptr;
/* Decrement the examined block count to account for this one. */
if (examine_blocks != ((UINT) 0))
@@ -243,9 +246,9 @@ UINT blocks_searched = ((UINT) 0);
{
/* Block is not free, move to next block. */
this_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(current_ptr);
this_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(current_ptr);
current_ptr = *this_block_link_ptr;
}
}
/* Another block has been searched... decrement counter. */
if (examine_blocks != ((UINT) 0))
@@ -282,12 +285,23 @@ UINT blocks_searched = ((UINT) 0);
/* Disable interrupts. */
TX_DISABLE
#endif
#endif
/* Determine if anything has changed in terms of pool ownership. */
if (pool_ptr -> tx_byte_pool_owner != thread_ptr)
{
/* Loop to delay changing the ownership back to avoid thrashing. */
delay_count = 0;
do
{
/* Restore interrupts temporarily. */
TX_RESTORE
/* Increment the delay counter. */
delay_count++;
/* Disable interrupts. */
TX_DISABLE
} while (delay_count < ((ULONG) TX_BYTE_POOL_DELAY_VALUE));
/* Pool changed ownership in the brief period interrupts were
enabled. Reset the search. */
current_ptr = pool_ptr -> tx_byte_pool_search;
@@ -317,7 +331,7 @@ UINT blocks_searched = ((UINT) 0);
work_ptr = TX_UCHAR_POINTER_ADD(next_ptr, (sizeof(UCHAR *)));
free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(work_ptr);
*free_ptr = TX_BYTE_BLOCK_FREE;
/* Increase the total fragment counter. */
pool_ptr -> tx_byte_pool_fragments++;
@@ -371,7 +385,7 @@ UINT blocks_searched = ((UINT) 0);
current_ptr = TX_NULL;
}
}
/* Return the search pointer. */
return(current_ptr);
}
ports/cortex_m0/ac5/src/tx_thread_context_restore.s
+4 -4
View File
@@ -21,9 +21,9 @@
;/**************************************************************************/
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
IMPORT _tx_execution_isr_exit
ENDIF
#endif
;
AREA ||.text||, CODE, READONLY
PRESERVE8
@@ -74,12 +74,12 @@
EXPORT _tx_thread_context_restore
_tx_thread_context_restore
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;
BL _tx_execution_isr_exit ; Call the ISR exit function
ENDIF
#endif
;
; /* Preemption has already been addressed - just return! */
;
ports/cortex_m0/ac5/src/tx_thread_context_save.s
+4 -4
View File
@@ -21,9 +21,9 @@
;/**************************************************************************/
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
IMPORT _tx_execution_isr_enter
ENDIF
#endif
;
;
AREA ||.text||, CODE, READONLY
@@ -73,7 +73,7 @@
;{
EXPORT _tx_thread_context_save
_tx_thread_context_save
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
@@ -81,7 +81,7 @@ _tx_thread_context_save
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, r1} ; Recover ISR lr
MOV lr, r1
ENDIF
#endif
;
; /* Return to interrupt processing. */
;
ports/cortex_m0/ac5/src/tx_thread_schedule.s
+6 -6
View File
@@ -26,10 +26,10 @@
IMPORT _tx_timer_time_slice
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
#endif
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
@@ -127,7 +127,7 @@ __tx_PendSVHandler
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the thread exit function to indicate the thread is no longer executing. */
;
@@ -137,7 +137,7 @@ __tx_ts_handler
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
CPSIE i ; Enable interrupts
ENDIF
#endif
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address
MOVS r3, #0 ; Build NULL value
@@ -210,14 +210,14 @@ __tx_ts_restore
;
STR r5, [r4] ; Setup global time-slice
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the thread entry function to indicate the thread is executing. */
;
PUSH {r0, r1} ; Save r0/r1
BL _tx_execution_thread_enter ; Call the thread execution enter function
POP {r0, r1} ; Recover r0/r1
ENDIF
#endif
;
; /* Restore the thread context and PSP. */
;
ports/cortex_m0/ac6/src/tx_thread_context_restore.S
+10 -1
View File
@@ -21,6 +21,9 @@
@/**************************************************************************/
@
@
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
.global _tx_thread_system_state
.global _tx_thread_current_ptr
.global _tx_thread_system_stack_ptr
@@ -81,6 +84,12 @@
.thumb_func
_tx_thread_context_restore:
@
@ /* Not needed for this port - just return! */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_exit // Call the ISR exit function
POP {r0, lr} // Recover return address
#endif
BX lr
@}
ports/cortex_m0/ac6/src/tx_thread_context_save.S
+10 -1
View File
@@ -21,6 +21,9 @@
@/**************************************************************************/
@
@
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_enter
#endif
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@
@@ -75,6 +78,12 @@
.thumb_func
_tx_thread_context_save:
@
@ /* Not needed for this port - just return! */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is starting. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_enter // Call the ISR enter function
POP {r0, lr} // Recover return address
#endif
BX lr
@}
ports/cortex_m0/ac6/src/tx_thread_schedule.S
+6 -2
View File
@@ -25,6 +25,10 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#endif
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
@@ -131,7 +135,7 @@ __tx_SVCallHandler:
.thumb_func
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
@
@ /* Call the thread exit function to indicate the thread is no longer executing. */
@
@@ -214,7 +218,7 @@ __tx_ts_restore:
@
STR r5, [r4] @ Setup global time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
@
@ /* Call the thread entry function to indicate the thread is executing. */
@
ports/cortex_m0/gnu/src/tx_thread_context_restore.S
+9 -1
View File
@@ -29,6 +29,9 @@
.global _tx_thread_schedule
.global _tx_thread_preempt_disable
.global _tx_execution_isr_exit
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
.global _tx_execution_isr_exit
#endif
@
@
.text 32
@@ -85,6 +88,11 @@
.thumb_func
_tx_thread_context_restore:
@
@ /* Not needed for this port - just return! */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_exit // Call the ISR exit function
POP {r0, lr} // Recover return address
#endif
BX lr
@}
ports/cortex_m0/gnu/src/tx_thread_context_save.S
+9 -1
View File
@@ -79,6 +79,14 @@
.thumb_func
_tx_thread_context_save:
@
@ /* Not needed for this port - just return! */
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is starting. */
PUSH {r0, lr} // Save return address
BL _tx_execution_isr_enter // Call the ISR enter function
POP {r0, lr} // Recover return address
#endif
/* Context is already saved - just return. */
BX lr
@}
ports/cortex_m0/gnu/src/tx_thread_schedule.S
+2 -2
View File
@@ -135,7 +135,7 @@ __tx_SVCallHandler:
.thumb_func
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
@
@ /* Call the thread exit function to indicate the thread is no longer executing. */
@
@@ -218,7 +218,7 @@ __tx_ts_restore:
@
STR r5, [r4] @ Setup global time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
@
@ /* Call the thread entry function to indicate the thread is executing. */
@
ports/cortex_m0/iar/inc/tx_port.h
-5
View File
@@ -190,12 +190,7 @@ ULONG _tx_misra_time_stamp_get(VOID);
#else
#define TX_THREAD_EXTENSION_2
#endif
#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#define TX_THREAD_EXTENSION_3
#else
#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \
unsigned long long tx_thread_execution_time_last_start;
#endif
/* Define the port extensions of the remaining ThreadX objects. */
ports/cortex_m0/iar/src/tx_thread_context_restore.s
+1 -1
View File
@@ -80,7 +80,7 @@
PUBLIC _tx_thread_context_restore
_tx_thread_context_restore:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;
ports/cortex_m0/iar/src/tx_thread_context_save.s
+1 -1
View File
@@ -73,7 +73,7 @@
;{
PUBLIC _tx_thread_context_save
_tx_thread_context_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is starting. */
;
ports/cortex_m0/iar/src/tx_thread_schedule.s
+2 -2
View File
@@ -124,7 +124,7 @@ __tx_PendSVHandler:
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the thread exit function to indicate the thread is no longer executing. */
;
@@ -208,7 +208,7 @@ __tx_ts_restore:
;
STR r5, [r4] ; Setup global time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the thread entry function to indicate the thread is executing. */
;
ports/cortex_m0/keil/src/tx_thread_context_restore.s
+5 -4
View File
@@ -21,9 +21,10 @@
;/**************************************************************************/
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
IMPORT _tx_execution_isr_exit
ENDIF
#endif
;
AREA ||.text||, CODE, READONLY
PRESERVE8
@@ -74,12 +75,12 @@
EXPORT _tx_thread_context_restore
_tx_thread_context_restore
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;
BL _tx_execution_isr_exit ; Call the ISR exit function
ENDIF
#endif
;
; /* Preemption has already been addressed - just return! */
;
ports/cortex_m0/keil/src/tx_thread_context_save.s
+4 -4
View File
@@ -21,9 +21,9 @@
;/**************************************************************************/
;
;
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
IMPORT _tx_execution_isr_enter
ENDIF
#endif
;
;
AREA ||.text||, CODE, READONLY
@@ -73,7 +73,7 @@
;{
EXPORT _tx_thread_context_save
_tx_thread_context_save
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
@@ -81,7 +81,7 @@ _tx_thread_context_save
BL _tx_execution_isr_enter ; Call the ISR enter function
POP {r0, r1} ; Recover ISR lr
MOV lr, r1
ENDIF
#endif
;
; /* Return to interrupt processing. */
;
ports/cortex_m0/keil/src/tx_thread_schedule.s
+6 -6
View File
@@ -26,10 +26,10 @@
IMPORT _tx_timer_time_slice
IMPORT _tx_thread_system_stack_ptr
IMPORT _tx_thread_preempt_disable
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
#endif
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
@@ -127,7 +127,7 @@ __tx_PendSVHandler
;
__tx_ts_handler
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the thread exit function to indicate the thread is no longer executing. */
;
@@ -137,7 +137,7 @@ __tx_ts_handler
POP {r0, r1} ; Recover LR
MOV lr, r1 ;
CPSIE i ; Enable interrupts
ENDIF
#endif
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address
MOVS r3, #0 ; Build NULL value
@@ -211,14 +211,14 @@ __tx_ts_restore
;
STR r5, [r4] ; Setup global time-slice
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
;
; /* Call the thread entry function to indicate the thread is executing. */
;
PUSH {r0, r1} ; Save r0/r1
BL _tx_execution_thread_enter ; Call the thread execution enter function
POP {r0, r1} ; Recover r0/r1
ENDIF
#endif
;
; /* Restore the thread context and PSP. */
;
ports/cortex_m23/ac5/example_build/ARMCM23_TZ_config.txt
-9
View File
@@ -1,9 +0,0 @@
# Parameters:
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
#----------------------------------------------------------------------------------------------
cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' :
cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included
fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2]
fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic
#----------------------------------------------------------------------------------------------
ports/cortex_m23/ac5/example_build/AzureRTOS.uvmpw
-26
View File
@@ -1,26 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<WorkspaceName>WorkSpace</WorkspaceName>
<project>
<PathAndName>.\demo_secure_zone\demo_secure_zone.uvprojx</PathAndName>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
<project>
<PathAndName>.\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx</PathAndName>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
<project>
<PathAndName>.\ThreadX_Library.uvprojx</PathAndName>
<NodeIsActive>1</NodeIsActive>
<NodeIsExpanded>1</NodeIsExpanded>
</project>
</ProjectWorkspace>
ports/cortex_m23/ac5/example_build/Debug.ini
-4
View File
@@ -1,4 +0,0 @@
LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental
LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental
RESET
g, \\demo_secure_zone\main_s\main
ports/cortex_m23/ac5/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h
-21
View File
@@ -1,21 +0,0 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'ThreadX_Library'
* Target: 'ThreadX_Library_Project'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM23_TZ.h"
#endif /* RTE_COMPONENTS_H */
ports/cortex_m23/ac5/example_build/ThreadX_Library.uvoptx
-2564
View File
File diff suppressed because it is too large Load Diff
ports/cortex_m23/ac5/example_build/ThreadX_Library.uvprojx
-1423
View File
File diff suppressed because it is too large Load Diff
ports/cortex_m23/ac5/example_build/demo_secure_zone/Abstract.txt
-19
View File
@@ -1,19 +0,0 @@
This ARM Cortex-M33 secure/non-secure example project that
shows the setup of the CMSIS-RTOS2 RTX for TrustZone for
ARMv8-M applications.
The application uses CMSIS and can be executed on a Fixed
Virtual Platform (FVP) simulation model. The application
demonstrates three RTOS threads.
Secure application:
- Setup code and start non-secure application.
Non-secure application:
- Calls a secure function from non-secure state.
- Calls a secure function that call back to a non-secure function.
Output:
Variables used in this application can be viewed in the Debugger
Watch window.
ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct
-78
View File
@@ -1,78 +0,0 @@
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00000000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*----------------------------------------------------------------------------
User Stack & Heap boundery definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE (__RAM_BASE )
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
; *(Veneer$$CMSE) ; uncomment for secure applications
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
SEAL +0
{
*.o(.seal+FIRST)
}
}
ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h
-832
View File
File diff suppressed because it is too large Load Diff
ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c
-140
View File
@@ -1,140 +0,0 @@
/******************************************************************************
* @file startup_ARMCM23.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device
* @version V2.0.0
* @date 04. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM23)
#include "ARMCM23.h"
#elif defined (ARMCM23_TZ)
#include "ARMCM23_TZ.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const pFunc __VECTOR_TABLE[240];
const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/* The linker will place this value at the bottom of the stack to seal the secure main stack. */
const int stack_seal __attribute__((section (".seal"))) = 0xFEF5EDA5;
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}
ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c
-98
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@@ -1,98 +0,0 @@
/**************************************************************************//**
* @file system_ARMCM23.c
* @brief CMSIS Device System Source File for
* ARMCM23 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM23)
#include "ARMCM23.h"
#elif defined (ARMCM23_TZ)
#include "ARMCM23_TZ.h"
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_ARMCM23.h"
#endif
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL) /* Oscillator frequency */
#define SYSTEM_CLOCK (XTAL / 2U)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __VECTOR_TABLE;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__VECTOR_TABLE;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
#endif
SystemCoreClock = SYSTEM_CLOCK;
*(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */
*(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */
}
#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)
void HardFault_Handler(void)
{
while(1);
}
void UsageFault_Handler(void)
{
while(1);
}
#endif
ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h
-21
View File
@@ -1,21 +0,0 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'demo_secure_zone'
* Target: 'FVP Simulation Model'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM23_TZ.h"
#endif /* RTE_COMPONENTS_H */
ports/cortex_m23/ac5/example_build/demo_secure_zone/demo_secure_zone.uvoptx
-328
View File
@@ -1,328 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>FVP Simulation Model</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>0</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>15</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>..\Debug.ini</tIfile>
<pMon>BIN\DbgFMv8M.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2V8M</Key>
<Name>UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DbgFMv8M</Key>
<Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_TZ_config.txt" -PF -MA</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(6010=3649,-370,4126,226,0)(6018=2033,530,2222,894,0)(6019=-1,-1,-1,-1,0)(6008=1847,-259,2141,-74,0)(6009=2148,-261,2442,-76,0)(6014=1836,-490,2094,241,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=75,104,528,436,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>_tx_thread_current_ptr</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>thread_0_counter</ItemText>
</Ww>
<Ww>
<count>2</count>
<WinNumber>1</WinNumber>
<ItemText>thread_1_counter</ItemText>
</Ww>
<Ww>
<count>3</count>
<WinNumber>1</WinNumber>
<ItemText>thread_2_counter</ItemText>
</Ww>
<Ww>
<count>4</count>
<WinNumber>1</WinNumber>
<ItemText>thread_3_counter</ItemText>
</Ww>
<Ww>
<count>5</count>
<WinNumber>1</WinNumber>
<ItemText>thread_4_counter</ItemText>
</Ww>
<Ww>
<count>6</count>
<WinNumber>1</WinNumber>
<ItemText>thread_5_counter</ItemText>
</Ww>
<Ww>
<count>7</count>
<WinNumber>1</WinNumber>
<ItemText>thread_6_counter</ItemText>
</Ww>
<Ww>
<count>8</count>
<WinNumber>1</WinNumber>
<ItemText>thread_7_counter</ItemText>
</Ww>
<Ww>
<count>9</count>
<WinNumber>1</WinNumber>
<ItemText>_tx_timer_system_clock</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>2</SubType>
<ItemText>0x2003ffd8</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<MemoryWindow2>
<Mm>
<WinNumber>2</WinNumber>
<SubType>2</SubType>
<ItemText>0xE000ED28</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow2>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Secure Code</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\src\tx_thread_secure_stack.c</PathWithFileName>
<FilenameWithoutPath>tx_thread_secure_stack.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main_s.c</PathWithFileName>
<FilenameWithoutPath>main_s.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Interface</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\interface.c</PathWithFileName>
<FilenameWithoutPath>interface.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>
ports/cortex_m23/ac5/example_build/demo_secure_zone/demo_secure_zone.uvprojx
-521
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File diff suppressed because it is too large Load Diff
ports/cortex_m23/ac5/example_build/demo_secure_zone/interface.c
-49
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@@ -1,49 +0,0 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* interface.c Secure/non-secure callable application code
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
#include <arm_cmse.h> // CMSE definitions
#include "interface.h" // Header file with secure interface API
/* typedef for non-secure callback functions */
typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));
/* Non-secure callable (entry) function */
int func1(int x) __attribute__((cmse_nonsecure_entry)) {
return x+3;
}
/* Non-secure callable (entry) function, calling a non-secure callback function */
int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) {
funcptr_NS callback_NS; // non-secure callback function pointer
int y;
/* return function pointer with cleared LSB */
callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);
y = callback_NS (x+1);
return (y+2);
}
ports/cortex_m23/ac5/example_build/demo_secure_zone/interface.h
-31
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@@ -1,31 +0,0 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* interface.h API definition for the non-secure state
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
/* Function pointer declaration */
typedef int (*funcptr)(int);
/* Non-secure callable functions */
extern int func1(int x);
extern int func2(funcptr callback, int x);
ports/cortex_m23/ac5/example_build/demo_secure_zone/main_ns.c
-108
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@@ -1,108 +0,0 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* main_ns.c Non-secure main function - RTOS demo
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
#include "interface.h" // Interface API
//#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
//static osStatus_t Status;
//static osThreadId_t ThreadA_Id;
//static osThreadId_t ThreadB_Id;
//static osThreadId_t ThreadC_Id;
void ThreadA (void *argument);
void ThreadB (void *argument);
void ThreadC (void *argument);
extern volatile int counterA;
extern volatile int counterB;
extern volatile int counterC;
volatile int counterA;
volatile int counterB;
volatile int counterC;
/*
static int callbackA (int val) {
return (val);
}
__attribute__((noreturn))
void ThreadA (void *argument) {
(void)argument;
for (;;) {
counterA = func1 (counterA);
counterA = func2 (callbackA, counterA);
osDelay(2U);
}
}
static int callbackB (int val) {
uint32_t flags;
flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever);
if (flags == 1U) {
return (val+1);
} else {
return (0);
}
}
__attribute__((noreturn))
void ThreadB (void *argument) {
(void)argument;
for (;;) {
counterB = func1 (counterB);
counterB = func2 (callbackB, counterB);
}
}
__attribute__((noreturn))
void ThreadC (void *argument) {
(void)argument;
for (;;) {
counterC = counterC + 1;
if ((counterC % 0x10) == 0) {
osThreadFlagsSet (ThreadB_Id, 1);
}
osDelay(1U);
}
}
static const osThreadAttr_t ThreadAttr = {
.tz_module = 1U, // indicate calls to secure mode
};
*/
#if 1
int main (void) {
for (;;);
}
#endif
ports/cortex_m23/ac5/example_build/demo_secure_zone/main_s.c
-61
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@@ -1,61 +0,0 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Code template for secure main function
*
*---------------------------------------------------------------------------*/
/* Use CMSE intrinsics */
#include <arm_cmse.h>
#include <stdlib.h>
#include "RTE_Components.h"
#include CMSIS_device_header
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (0x200000U)
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}
ports/cortex_m23/ac5/example_build/demo_secure_zone/tz_context.c
-203
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@@ -1,203 +0,0 @@
/*
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------------
*
* $Date: 15. October 2016
* $Revision: 1.1.0
*
* Project: TrustZone for ARMv8-M
* Title: Context Management for ARMv8-M TrustZone - Sample implementation
*
*---------------------------------------------------------------------------*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "tz_context.h"
/// Number of process slots (threads may call secure library code)
#ifndef TZ_PROCESS_STACK_SLOTS
#define TZ_PROCESS_STACK_SLOTS 8U
#endif
/// Stack size of the secure library code
#ifndef TZ_PROCESS_STACK_SIZE
#define TZ_PROCESS_STACK_SIZE 256U
#endif
typedef struct {
uint32_t sp_top; // stack space top
uint32_t sp_limit; // stack space limit
uint32_t sp; // current stack pointer
} stack_info_t;
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_InitContextSystem_S (void) {
uint32_t n;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
ProcessStackInfo[n].sp = 0U;
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
}
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
ProcessStackFreeSlot = 0U;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
// Privileged Thread Mode using PSP
__set_CONTROL(0x02U);
return 1U; // Success
}
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
__attribute__((cmse_nonsecure_entry))
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
uint32_t slot;
(void)module; // Ignore (fixed Stack size)
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
return 0U; // No slot available
}
slot = ProcessStackFreeSlot;
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
return (slot + 1U);
}
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
ProcessStackInfo[slot].sp = 0U;
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
ProcessStackFreeSlot = slot;
return 1U; // Success
}
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
// Setup process stack pointer and stack limit
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
__set_PSP (ProcessStackInfo[slot].sp);
return 1U; // Success
}
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
uint32_t slot;
uint32_t sp;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
sp = __get_PSP();
if ((sp < ProcessStackInfo[slot].sp_limit) ||
(sp > ProcessStackInfo[slot].sp_top)) {
return 0U; // SP out of range
}
ProcessStackInfo[slot].sp = sp;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
return 1U; // Success
}
ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c
-64
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@@ -1,64 +0,0 @@
/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
for (;;) {}
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
}
ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h
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ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct
-74
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@@ -1,74 +0,0 @@
#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc
; command above MUST be in first line (no comment above!)
/*
;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
*/
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00200000
#define __ROM_SIZE 0x00080000
/*--------------------- Embedded RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __RAM_BASE 0x20200000
#define __RAM_SIZE 0x00040000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00000200
#define __HEAP_SIZE 0x00000C00
/*----------------------------------------------------------------------------
User Stack & Heap boundery definition
*----------------------------------------------------------------------------*/
#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
/*----------------------------------------------------------------------------
Scatter File Definitions definition
*----------------------------------------------------------------------------*/
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW_BASE (__RAM_BASE )
#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
; *(Veneer$$CMSE) ; uncomment for secure applications
.ANY (+RO)
.ANY (+XO)
}
RW_RAM __RW_BASE __RW_SIZE { ; RW data
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}
ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h
-832
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ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c
-137
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@@ -1,137 +0,0 @@
/******************************************************************************
* @file startup_ARMCM23.c
* @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device
* @version V2.0.0
* @date 04. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM23)
#include "ARMCM23.h"
#elif defined (ARMCM23_TZ)
#include "ARMCM23_TZ.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Exception / Interrupt Handler Function Prototype
*----------------------------------------------------------------------------*/
typedef void( *pFunc )( void );
/*----------------------------------------------------------------------------
External References
*----------------------------------------------------------------------------*/
extern uint32_t __INITIAL_SP;
extern uint32_t __STACK_LIMIT;
extern __NO_RETURN void __PROGRAM_START(void);
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void __NO_RETURN Default_Handler(void);
void __NO_RETURN Reset_Handler (void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
/* Exceptions */
void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector table
*----------------------------------------------------------------------------*/
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
extern const pFunc __VECTOR_TABLE[240];
const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
(pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* -14 NMI Handler */
HardFault_Handler, /* -13 Hard Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* -5 SVCall Handler */
0, /* Reserved */
0, /* Reserved */
PendSV_Handler, /* -2 PendSV Handler */
SysTick_Handler, /* -1 SysTick Handler */
/* Interrupts */
Interrupt0_Handler, /* 0 Interrupt 0 */
Interrupt1_Handler, /* 1 Interrupt 1 */
Interrupt2_Handler, /* 2 Interrupt 2 */
Interrupt3_Handler, /* 3 Interrupt 3 */
Interrupt4_Handler, /* 4 Interrupt 4 */
Interrupt5_Handler, /* 5 Interrupt 5 */
Interrupt6_Handler, /* 6 Interrupt 6 */
Interrupt7_Handler, /* 7 Interrupt 7 */
Interrupt8_Handler, /* 8 Interrupt 8 */
Interrupt9_Handler /* 9 Interrupt 9 */
/* Interrupts 10 .. 223 are left out */
};
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
SystemInit(); /* CMSIS System Initialization */
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}

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