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Restored ports_arch as the source of truth for the Cortex-M ports (#590)

Browse Source 
The Cortex-M ports under ports/ are generated. scripts/copy_armv7_m.sh copies
one tx_port.h and the per tool sources to fifteen M3, M4 and M7 targets, and
scripts/copy_armv8_m.sh does the same for nine M33, M55 and M85 targets. The
ports_arch_check workflow runs both scripts and fails if the tree is not
reproducible, so those copies are meant never to be edited directly.

They were. Every Cortex-M fix since #523 was applied to the generated copies
and not to the source, so the source fell behind and the check went red:
running the three scripts on dev changes 35 files. The check triggers only on
pull requests targeting master, which is why nothing caught it while the fixes
were merged into dev.

Left alone, the next run of these scripts would have reverted three separate
pieces of work: the memory barriers and clobbers from #523, the correction of
the IAR assembly header to use the assembler's own comment syntax, and the move
of tx_initialize_low_level.S into example_build for the M33, M55 and M85 GNU
ports from #514.

Bring the sources up to what the ports carry today, and regenerate. Two
behavioural changes come with that, both deliberate. The barriers from #523
reach the ac5 and keil variants of M3, M4 and M7, which were outside the scope
of that fix and never received it. The barrier that follows restoring the
interrupt posture, which #523 gave only to the GNU ports because GNU was the
only toolchain that could be tested, now applies to every tool; the identical
asm statement already shipped in the AC6 and IAR ports, so this adds a pipeline
flush rather than any new compiler exposure.

Regenerating also drops a stray #endif at the end of the Cortex-M85 IAR
tx_port.h, added by #523, which left that header with one more #endif than #if
and unable to compile. Every other ARMv8-M port was balanced.

Verified that the scripts are idempotent afterwards, that ports_arch_check
would pass, that no port loses a barrier or a clobber, that every regenerated
header is preprocessor balanced, and that every Cortex-M port covered by the
two scripts now carries the entry barrier.

Assisted-by: Claude Code (Opus 5) <noreply@anthropic.com>
This commit is contained in:
Frédéric Desbiens
2026-08-09 10:42:54 -04:00
committed by GitHub
parent cbdf924d6b
commit eb4ec4e3b5
54 changed files with 313 additions and 362 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ports/cortex_m3/ac5/inc/tx_port.h
+9 -2
View File
@@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m3/ac6/inc/tx_port.h
+4 -1
View File
@@ -11,6 +11,7 @@
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
ports/cortex_m3/ac6/src/tx_thread_system_return.S
+2
View File
@@ -85,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m3/gnu/inc/tx_port.h
+4
View File
@@ -10,6 +10,8 @@
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -543,6 +545,7 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
ports/cortex_m3/iar/inc/tx_port.h
+4 -1
View File
@@ -11,6 +11,7 @@
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
ports/cortex_m3/iar/src/tx_thread_system_return.s
+2
View File
@@ -83,10 +83,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m3/keil/inc/tx_port.h
+9 -2
View File
@@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m33/ac6/inc/tx_port.h
+2
View File
@@ -10,6 +10,7 @@
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -592,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m33/ac6/src/tx_thread_system_return.S
+2
View File
@@ -86,10 +86,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m33/gnu/inc/tx_port.h
+2
View File
@@ -10,6 +10,7 @@
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -556,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
ports/cortex_m33/iar/inc/tx_port.h
+2
View File
@@ -10,6 +10,7 @@
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -592,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m33/iar/src/tx_thread_system_return.s
+2
View File
@@ -82,10 +82,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m4/ac5/inc/tx_port.h
+9 -2
View File
@@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m4/ac6/inc/tx_port.h
+2 -1
View File
@@ -545,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
@@ -593,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m4/ac6/src/tx_thread_system_return.S
+2
View File
@@ -85,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m4/gnu/inc/tx_port.h
+2 -1
View File
@@ -11,6 +11,7 @@
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
ports/cortex_m4/iar/inc/tx_port.h
+4 -1
View File
@@ -11,6 +11,7 @@
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
ports/cortex_m4/iar/src/tx_thread_system_return.s
+2
View File
@@ -83,10 +83,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m4/keil/inc/tx_port.h
+9 -2
View File
@@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m55/ac6/inc/tx_port.h
+7 -1
View File
@@ -9,6 +9,9 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -541,7 +544,7 @@ UINT posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -579,6 +583,7 @@ UINT interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (_tx_ipsr_get() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -588,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m55/ac6/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m55/gnu/inc/tx_port.h
+1
View File
@@ -10,6 +10,7 @@
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
ports/cortex_m55/iar/inc/tx_port.h
+6 -1
View File
@@ -9,6 +9,9 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -541,7 +544,7 @@ UINT posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -589,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m55/iar/src/tx_thread_system_return.s
+2
View File
@@ -82,10 +82,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m7/ac5/inc/tx_port.h
+9 -2
View File
@@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m7/ac6/inc/tx_port.h
+4 -1
View File
@@ -11,6 +11,7 @@
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
ports/cortex_m7/ac6/src/tx_thread_system_return.S
+2
View File
@@ -85,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m7/gnu/inc/tx_port.h
+2 -2
View File
@@ -11,6 +11,7 @@
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
@@ -562,7 +563,6 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
#endif
}
__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void)
{
unsigned int int_posture;
ports/cortex_m7/iar/inc/tx_port.h
+4 -1
View File
@@ -11,6 +11,7 @@
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
@@ -544,8 +545,8 @@ __attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsign
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile ("CPSIE i": : : "memory");
@@ -592,8 +593,10 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupt(interrupt_save);
ports/cortex_m7/iar/src/tx_thread_system_return.s
+2
View File
@@ -83,10 +83,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m85/ac6/inc/tx_port.h
+7 -1
View File
@@ -9,6 +9,9 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -541,7 +544,7 @@ UINT posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -579,6 +583,7 @@ UINT interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (_tx_ipsr_get() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -588,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports/cortex_m85/ac6/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports/cortex_m85/gnu/inc/tx_port.h
+1
View File
@@ -10,6 +10,7 @@
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
ports/cortex_m85/iar/inc/tx_port.h
+5 -2
View File
@@ -9,6 +9,9 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -580,6 +583,7 @@ UINT interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (_tx_ipsr_get() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -589,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
@@ -624,5 +629,3 @@ extern CHAR _tx_version_id[];
#endif
#endif
#endif
ports/cortex_m85/iar/src/tx_thread_system_return.s
+2
View File
@@ -82,10 +82,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s
+18 -11
View File
@@ -1,16 +1,19 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
;***************************************************************************
;* Copyright (c) 2024 Microsoft Corporation
;* Copyright (c) 2026-present Eclipse ThreadX contributors
;*
;* This program and the accompanying materials are made available under the
;* terms of the MIT License which is available at
;* https://opensource.org/licenses/MIT.
;*
;* SPDX-License-Identifier: MIT
;**************************************************************************
; Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
;**************************************************************************
/**************************************************************************/
/** */
/** ThreadX Component */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB SY // Ensure memory access is complete
ISB SY // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_arch/ARMv7-M/threadx/inc/tx_port.h
+9 -2
View File
@@ -9,6 +9,10 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Copilot (Claude Sonnet 4.6).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -539,8 +543,9 @@ unsigned int posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(unsigned int basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
@@ -552,7 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsign
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
//__asm__ volatile ("MSR BASEPRI,%0": : "r" (int_posture): "memory");
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -578,6 +583,7 @@ unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (__get_ipsr_value() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -587,6 +593,7 @@ unsigned int interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_arch/ARMv8-M/threadx/gnu/CMakeLists.txt
+7 -4
View File
@@ -1,7 +1,8 @@
target_sources(${PROJECT_NAME} PRIVATE
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME} PUBLIC
inc
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S
-276
View File
File diff suppressed because it is too large Load Diff
ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -74,6 +76,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -82,10 +86,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s
+18 -11
View File
@@ -1,16 +1,19 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
;***************************************************************************
;* Copyright (c) 2024 Microsoft Corporation
;* Copyright (c) 2026-present Eclipse ThreadX contributors
;*
;* This program and the accompanying materials are made available under the
;* terms of the MIT License which is available at
;* https://opensource.org/licenses/MIT.
;*
;* SPDX-License-Identifier: MIT
;**************************************************************************
; Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
;**************************************************************************
/**************************************************************************/
/** */
/** ThreadX Component */
@@ -69,6 +72,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB SY // Ensure memory access is complete
ISB SY // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -77,10 +82,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_arch/ARMv8-M/threadx/inc/tx_port.h
+7 -1
View File
@@ -9,6 +9,9 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
// Some portions generated by Claude Code (Opus 5).
/**************************************************************************/
/**************************************************************************/
@@ -541,7 +544,7 @@ UINT posture;
#ifdef TX_PORT_USE_BASEPRI
__attribute__( ( always_inline ) ) static inline void __set_basepri_value(UINT basepri_value)
{
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value));
__asm__ volatile ("MSR BASEPRI,%0 ": : "r" (basepri_value) : "memory");
}
#else
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
@@ -554,6 +557,7 @@ __attribute__( ( always_inline ) ) static inline void __restore_interrupt(UINT i
{
#ifdef TX_PORT_USE_BASEPRI
__set_basepri_value(int_posture);
__asm__ volatile ("" : : : "memory");
#else
__asm__ volatile ("MSR PRIMASK,%0": : "r" (int_posture): "memory");
#endif
@@ -579,6 +583,7 @@ UINT interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
__asm__ volatile ("dsb 0xF \n isb 0xF " : : : "memory");
if (_tx_ipsr_get() == 0)
{
interrupt_save = __get_interrupt_posture();
@@ -588,6 +593,7 @@ UINT interrupt_save;
__enable_interrupts();
#endif
__restore_interrupt(interrupt_save);
__asm__ volatile ("isb 0xF " : : : "memory");
}
}
ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s
+18 -11
View File
@@ -1,16 +1,19 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
;***************************************************************************
;* Copyright (c) 2024 Microsoft Corporation
;* Copyright (c) 2026-present Eclipse ThreadX contributors
;*
;* This program and the accompanying materials are made available under the
;* terms of the MIT License which is available at
;* https://opensource.org/licenses/MIT.
;*
;* SPDX-License-Identifier: MIT
;**************************************************************************
; Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
;**************************************************************************
/**************************************************************************/
/** */
/** ThreadX Component */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB SY // Ensure memory access is complete
ISB SY // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s
+18 -11
View File
@@ -1,16 +1,19 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
;***************************************************************************
;* Copyright (c) 2024 Microsoft Corporation
;* Copyright (c) 2026-present Eclipse ThreadX contributors
;*
;* This program and the accompanying materials are made available under the
;* terms of the MIT License which is available at
;* https://opensource.org/licenses/MIT.
;*
;* SPDX-License-Identifier: MIT
;**************************************************************************
; Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
;**************************************************************************
/**************************************************************************/
/** */
/** ThreadX Component */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB SY // Ensure memory access is complete
ISB SY // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S
+6
View File
@@ -9,6 +9,8 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
/**************************************************************************/
@@ -73,6 +75,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB #0xF // Ensure memory access is complete
ISB #0xF // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -81,10 +85,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB #0xF // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller
ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s
+18 -11
View File
@@ -1,16 +1,19 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
;***************************************************************************
;* Copyright (c) 2024 Microsoft Corporation
;* Copyright (c) 2026-present Eclipse ThreadX contributors
;*
;* This program and the accompanying materials are made available under the
;* terms of the MIT License which is available at
;* https://opensource.org/licenses/MIT.
;*
;* SPDX-License-Identifier: MIT
;**************************************************************************
; Some portions generated by Gemini (Gemini 2.0 Flash).
/**************************************************************************/
;**************************************************************************
/**************************************************************************/
/** */
/** ThreadX Component */
@@ -70,6 +73,8 @@ _tx_thread_system_return:
MOV r0, #0x10000000 // Load PENDSVSET bit
MOV r1, #0xE000E000 // Load NVIC base
STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR
DSB SY // Ensure memory access is complete
ISB SY // Flush pipeline
MRS r0, IPSR // Pickup IPSR
CMP r0, #0 // Is it a thread returning?
BNE _isr_context // If ISR, skip interrupt enable
@@ -78,10 +83,12 @@ _tx_thread_system_return:
MOV r0, #0
MSR BASEPRI, r0 // Enable interrupts
MSR BASEPRI, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#else
MRS r1, PRIMASK // Thread context returning, pickup PRIMASK
CPSIE i // Enable interrupts
MSR PRIMASK, r1 // Restore original interrupt posture
ISB SY // Flush pipeline
#endif
_isr_context:
BX lr // Return to caller