mirror of
https://github.com/eclipse-threadx/threadx.git
synced 2026-08-18 11:49:38 +08:00
Fix VFP build failure in Cortex-A tx_thread_schedule.S
When TX_ENABLE_VFP_SUPPORT is defined, the build fails due to missing IRQ_MASK and FIQ_MASK symbols in the restore logic. This adds the local definitions (0x80 and 0x40) to tx_thread_schedule.S to match tx_thread_interrupt_restore.S, enabling successful compilation on GNU and AC6 Cortex-A ports.
This commit is contained in:
@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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@@ -39,6 +39,14 @@
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#define IRQ_MODE 0x12 // IRQ mode
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#define SVC_MODE 0x13 // SVC mode
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#ifdef TX_ENABLE_VFP_SUPPORT
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IRQ_MASK = 0x080
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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FIQ_MASK = 0x040
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#endif
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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