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Added thumb mode support under GNU for module manager on Cortex-A7 pl… (#287)

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* Added thumb mode support under GNU for module manager on Cortex-A7 platform.

* update code for comment.
This commit is contained in:
yajunxiaMS
2023-07-21 09:26:22 +08:00
committed by GitHub
parent 1ffd7c2cde
commit 7fa087d061
26 changed files with 1101 additions and 598 deletions
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ports_module/cortex_a7/gnu/example_build/build_threadx_module_library.bat
+18 -18
View File
@@ -98,21 +98,21 @@ arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -m
arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c
arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c
armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o
armar -r txm.a txm_block_pool_prioritize.o txm_block_release.o
armar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o
armar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o
armar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o
armar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o
armar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o
armar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o
armar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o
armar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o
armar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o
armar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o
armar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o
armar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o
armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o
armar -r txm.a txm_time_get.o txm_time_set.o
armar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o
armar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o
arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o
arm-none-eabi-ar -r txm.a txm_block_pool_prioritize.o txm_block_release.o
arm-none-eabi-ar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o
arm-none-eabi-ar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o
arm-none-eabi-ar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o
arm-none-eabi-ar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o
arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o
arm-none-eabi-ar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o
arm-none-eabi-ar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o
arm-none-eabi-ar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o
arm-none-eabi-ar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o
arm-none-eabi-ar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o
arm-none-eabi-ar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o
arm-none-eabi-ar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o
arm-none-eabi-ar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o
arm-none-eabi-ar -r txm.a txm_time_get.o txm_time_set.o
arm-none-eabi-ar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o
arm-none-eabi-ar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o
ports_module/cortex_a7/gnu/example_build/crt0.S
+20 -13
View File
@@ -1,15 +1,30 @@
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
/* .text is used instead of .section .text so it works with arm-aout too. */
.text
.code 32
.align 0
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _mainCRTStartup
_mainCRTStartup:
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _start
_start:
#if defined(THUMB_MODE)
.thumb_func
#endif
.global start
start:
_start:
_mainCRTStartup:
/* Start by setting up a stack */
/* Set up the stack pointer to a fixed value */
@@ -68,17 +83,9 @@ _mainCRTStartup:
.Lfini:
.word _fini
#endif */
/* Return ... */
#ifdef __APCS_26__
movs pc, lr
#else
#ifdef __THUMB_INTERWORK
bx lr
#else
mov pc, lr
#endif
#endif
/* Return ... */
bx lr
/* Workspace for Angel calls. */
.data
ports_module/cortex_a7/gnu/example_build/gcc_setup.S
+10 -4
View File
@@ -1,10 +1,18 @@
.syntax unified
#if !defined(THUMB_MODE)
.arm
#else
.thumb
#endif
.text
.align 4
.syntax unified
.global _gcc_setup
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _gcc_setup
_gcc_setup:
STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers
@@ -93,7 +101,6 @@ got_setup_done:
/* Startup helper functions. */
.thumb_func
crt0_memory_copy:
cmp r0, r1
@@ -112,7 +119,6 @@ memory_copy_loop:
memory_copy_done:
bx lr
.thumb_func
crt0_memory_set:
cmp r0, r1
beq memory_set_done
ports_module/cortex_a7/gnu/example_build/module_code.c
+449
View File
File diff suppressed because it is too large Load Diff
ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s
+52 -27
View File
@@ -20,7 +20,12 @@
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
SVC_MODE = 0xD3 // Disable IRQ/FIQ SVC mode
IRQ_MODE = 0xD2 // Disable IRQ/FIQ IRQ mode
@@ -39,24 +44,14 @@ THUMB_MASK = 0x20 // THUMB mode bit
.global _end
.global _sp
.global _stack_bottom
/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for
applications calling this function from to 16-bit Thumb mode. */
.text
.align 2
.thumb
.global $_tx_initialize_low_level
.type $_tx_initialize_low_level,function
$_tx_initialize_low_level:
BX pc // Switch to 32-bit mode
NOP //
.arm
STMFD sp!, {lr} // Save return address
BL _tx_initialize_low_level // Call _tx_initialize_low_level function
LDMFD sp!, {lr} // Recover saved return address
BX lr // Return to 16-bit caller
#ifdef TX_ENABLE_FIQ_SUPPORT
.global _tx_thread_fiq_context_save
.global _tx_thread_fiq_context_restore
#ifdef TX_ENABLE_FIQ_NESTING
.global _tx_thread_fiq_nesting_start
.global _tx_thread_fiq_nesting_end
#endif
#endif
.text
.align 2
@@ -65,7 +60,7 @@ $_tx_initialize_low_level:
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -101,8 +96,14 @@ $_tx_initialize_low_level:
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_initialize_low_level
.type _tx_initialize_low_level,function
_tx_initialize_low_level:
@@ -155,28 +156,37 @@ _stack_error_loop:
ADD r1, r1, #8 // Increment to next free word
STR r1, [r2] // Save first free memory address
#ifdef __THUMB_INTERWORK
BX lr // Return to caller
#else
MOV pc, lr // Return to caller
#endif
/* Define shells for each of the interrupt vectors. */
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_undefined
__tx_undefined:
B __tx_undefined // Undefined handler
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_reserved_handler
__tx_reserved_handler:
B __tx_reserved_handler // Reserved exception handler
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_irq_handler
.global __tx_irq_processing_return
__tx_irq_handler:
/* Jump to context save to save system context. */
B _tx_thread_context_save
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_irq_processing_return
__tx_irq_processing_return:
//
/* At this point execution is still in the IRQ mode. The CPSR, point of
@@ -245,12 +255,18 @@ __tx_irq_processing_return:
#ifdef TX_ENABLE_FIQ_SUPPORT
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_fiq_handler
.global __tx_fiq_processing_return
__tx_fiq_handler:
asdf
/* Jump to fiq context save to save system context. */
B _tx_thread_fiq_context_save
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_fiq_processing_return
__tx_fiq_processing_return:
/* At this point execution is still in the FIQ mode. The CPSR, point of
@@ -279,6 +295,9 @@ __tx_fiq_processing_return:
#else
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_fiq_handler
__tx_fiq_handler:
B __tx_fiq_handler // FIQ interrupt handler
@@ -336,9 +355,15 @@ __tx_fiq_handler:
// EXTERN _tx_execution_thread_exit
// EXTERN _tx_thread_schedule
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_prefetch_handler
.global __tx_abort_handler
__tx_prefetch_handler:
#if defined(THUMB_MODE)
.thumb_func
#endif
.global __tx_abort_handler
__tx_abort_handler:
STMDB sp!, {r0-r3} // Save some working registers
LDR r3, =_tx_thread_system_state // Pickup address of system state var
ports_module/cortex_a7/gnu/inc/tx_port.h
+30 -31
View File
@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h ARMv7-A */
/* 6.1.12 */
/* 6.x */
/* */
/* AUTHOR */
/* */
@@ -56,6 +56,9 @@
/* 07-29-2022 Scott Larson Updated comments, removed */
/* unneeded temp variable, */
/* resulting in version 6.1.12 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
@@ -269,21 +272,10 @@ typedef unsigned short USHORT;
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* Determine if the ARM architecture has the CLZ instruction. This is available on
architectures v5 and above. If available, redefine the macro for calculating the
lowest bit set. */
#if __TARGET_ARCH_ARM > 4
#ifndef __thumb__
/* Redefine the macro for calculating the lowest bit set. */
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \
asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \
b = 31 - b;
#endif
#endif
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
@@ -292,32 +284,39 @@ typedef unsigned short USHORT;
is used to define a local function save area for the disable and restore
macros. */
#ifdef __thumb__
unsigned int _tx_thread_interrupt_disable(void);
unsigned int _tx_thread_interrupt_restore(UINT old_posture);
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
#else
#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save;
#ifdef TX_ENABLE_FIQ_SUPPORT
#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) );
#define TX_DISABLE \
{ \
asm volatile (" MRS %0,CPSR": "=r" (interrupt_save)); \
asm volatile (" CPSID if"); \
}
#define TX_RESTORE \
{ \
if ((interrupt_save & 0x40) == 0) \
asm volatile (" CPSIE f"); \
if ((interrupt_save & 0x80) == 0) \
asm volatile (" CPSIE i"); \
}
#else
#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) );
#endif
#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) );
#define TX_DISABLE \
{ \
asm volatile (" MRS %0,CPSR": "=r" (interrupt_save)); \
asm volatile (" CPSID i"); \
}
#define TX_RESTORE \
{ \
if ((interrupt_save & 0x80) == 0) \
asm volatile (" CPSIE i"); \
}
#endif
/* Define VFP extension for the ARMv7-A. Each is assumed to be called in the context of the executing
thread. */
ports_module/cortex_a7/gnu/inc/txm_module_port.h
+6 -3
View File
@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module_port.h Cortex-A7/MMU/GNU */
/* 6.2.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -41,6 +41,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 03-08-2023 Scott Larson Initial Version 6.2.1 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
@@ -106,7 +109,7 @@ The following extensions must also be defined in tx_port.h:
/* Define the properties for this particular module port. */
#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED
#define TXM_MODULE_MEMORY_PROTECTION 0x00000001
#define TXM_MODULE_MEMORY_PROTECTION 0x00000002
#else
#define TXM_MODULE_MEMORY_PROTECTION 0x00000000
#endif
@@ -115,7 +118,7 @@ The following extensions must also be defined in tx_port.h:
/* Define the supported options for this module. */
#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_MEMORY_PROTECTION)
#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION)
#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s
+76 -115
View File
File diff suppressed because it is too large Load Diff
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s
+22 -72
View File
@@ -20,6 +20,13 @@
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
.global _tx_thread_system_state
.global _tx_thread_current_ptr
.global __tx_irq_processing_return
@@ -28,7 +35,6 @@
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save
since it will never be called 16-bit mode. */
.arm
.text
.align 2
/**************************************************************************/
@@ -36,7 +42,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -73,8 +79,14 @@
/* resulting in version 6.1.9 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_context_save
.type _tx_thread_context_save,function
_tx_thread_context_save:
@@ -82,91 +94,29 @@ _tx_thread_context_save:
/* Upon entry to this routine, it is assumed that IRQ interrupts are locked
out, we are in IRQ mode, and all registers are intact. */
/* Check for a nested interrupt condition. */
STMDB sp!, {r0-r3} // Save some working registers
#ifdef TX_ENABLE_FIQ_SUPPORT
CPSID if // Disable FIQ interrupts
#endif
LDR r3, =_tx_thread_system_state // Pickup address of system state variable
LDR r2, [r3] // Pickup system state
CMP r2, #0 // Is this the first interrupt?
BEQ __tx_thread_not_nested_save // Yes, not a nested context save
/* Nested interrupt condition. */
ADD r2, r2, #1 // Increment the interrupt counter
STR r2, [r3] // Store it back in the variable
/* Save the rest of the scratch registers on the stack and return to the
calling ISR. */
MRS r0, SPSR // Pickup saved SPSR
SUB lr, lr, #4 // Adjust point of interrupt
STMDB sp!, {r0, r10, r12, lr} // Store other registers
/* Return to the ISR. */
MOV r10, #0 // Clear stack limit
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is executing. */
PUSH {lr} // Save ISR lr
BL _tx_execution_isr_enter // Call the ISR enter function
POP {lr} // Recover ISR lr
#endif
B __tx_irq_processing_return // Continue IRQ processing
__tx_thread_not_nested_save:
/* Otherwise, not nested, check to see if a thread was running. */
ADD r2, r2, #1 // Increment the interrupt counter
STR r2, [r3] // Store it back in the variable
LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr
LDR r0, [r1] // Pickup current thread pointer
CMP r0, #0 // Is it NULL?
BEQ __tx_thread_idle_system_save // If so, interrupt occurred in
// scheduling loop - nothing needs saving!
PUSH {r0-r3} // Save some working registers
/* Save minimal context of interrupted thread. */
MRS r2, SPSR // Pickup saved SPSR
MRS r0, SPSR // Pickup saved SPSR
SUB lr, lr, #4 // Adjust point of interrupt
STMDB sp!, {r2, r10, r12, lr} // Store other registers
PUSH {r0, r10, r12, lr} // Store other registers
LDR r1, =_tx_thread_system_state // Pickup address of system state variable
LDR r0, [r1] // Pickup system state
ADD r0, #1 // Increment the interrupt counter
STR r0, [r1] // Store it back in the variable
MOV r10, #0 // Clear stack limit
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is executing. */
PUSH {lr} // Save ISR lr
BL _tx_execution_isr_enter // Call the ISR enter function
POP {lr} // Recover ISR lr
#endif
B __tx_irq_processing_return // Continue IRQ processing
__tx_thread_idle_system_save:
/* Interrupt occurred in the scheduling loop. */
/* Not much to do here, just adjust the stack pointer, and return to IRQ
processing. */
MOV r10, #0 // Clear stack limit
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is executing. */
PUSH {lr} // Save ISR lr
BL _tx_execution_isr_enter // Call the ISR enter function
POP {lr} // Recover ISR lr
#endif
ADD sp, sp, #16 // Recover saved registers
B __tx_irq_processing_return // Continue IRQ processing
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s
+22 -16
View File
@@ -19,11 +19,16 @@
/** */
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
SVC_MODE = 0xD3 // SVC mode
FIQ_MODE = 0xD1 // FIQ mode
MODE_MASK = 0x1F // Mode mask
THUMB_MASK = 0x20 // Thumb bit mask
IRQ_MODE_BITS = 0x12 // IRQ mode bits
@@ -36,11 +41,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits
.global _tx_thread_preempt_disable
.global _tx_execution_isr_exit
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore
since it will never be called 16-bit mode. */
.arm
.text
.align 2
/**************************************************************************/
@@ -48,7 +48,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fiq_context_restore ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -86,8 +86,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits
/* resulting in version 6.1.9 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_fiq_context_restore
.type _tx_thread_fiq_context_restore,function
_tx_thread_fiq_context_restore:
@@ -116,9 +122,9 @@ _tx_thread_fiq_context_restore:
/* Just recover the saved registers and return to the point of
interrupt. */
LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
POP {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs
MSR SPSR_cxsf, r0 // Put SPSR back
LDMIA sp!, {r0-r3} // Recover r0-r3
POP {r0-r3} // Recover r0-r3
MOVS pc, lr // Return to point of interrupt
__tx_thread_fiq_not_nested_restore:
@@ -153,26 +159,26 @@ __tx_thread_fiq_no_preempt_restore:
/* Restore interrupted thread or ISR. */
/* Recover the saved context and return to the point of interrupt. */
LDMIA sp!, {r0, lr} // Recover SPSR, POI, and scratch regs
POP {r0, lr} // Recover SPSR, POI, and scratch regs
MSR SPSR_cxsf, r0 // Put SPSR back
LDMIA sp!, {r0-r3} // Recover r0-r3
POP {r0-r3} // Recover r0-r3
MOVS pc, lr // Return to point of interrupt
__tx_thread_fiq_preempt_restore:
LDMIA sp!, {r3, lr} // Recover temporarily saved registers
POP {r3, lr} // Recover temporarily saved registers
MOV r1, lr // Save lr (point of interrupt)
MOV r2, #SVC_MODE // Build SVC mode CPSR
MSR CPSR_c, r2 // Enter SVC mode
STR r1, [sp, #-4]! // Save point of interrupt
STMDB sp!, {r4-r12, lr} // Save upper half of registers
PUSH {r4-r12, lr} // Save upper half of registers
MOV r4, r3 // Save SPSR in r4
MOV r2, #FIQ_MODE // Build FIQ mode CPSR
MSR CPSR_c, r2 // Reenter FIQ mode
LDMIA sp!, {r0-r3} // Recover r0-r3
POP {r0-r3} // Recover r0-r3
MOV r5, #SVC_MODE // Build SVC mode CPSR
MSR CPSR_c, r5 // Enter SVC mode
STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack
PUSH {r0-r3} // Save r0-r3 on thread's stack
LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr
LDR r0, [r1] // Pickup current thread pointer
@@ -189,7 +195,7 @@ _tx_skip_fiq_vfp_save:
#endif
MOV r3, #1 // Build interrupt stack type
STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR
PUSH {r3, r4} // Save interrupt stack type and SPSR
STR sp, [r0, #8] // Save stack pointer in thread control
// block */
LDR r3, =_tx_timer_time_slice // Pickup time-slice variable address
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s
+17 -6
View File
@@ -19,6 +19,12 @@
/** */
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
.global _tx_thread_system_state
.global _tx_thread_current_ptr
@@ -29,7 +35,6 @@
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save
since it will never be called 16-bit mode. */
.arm
.text
.align 2
/**************************************************************************/
@@ -37,7 +42,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fiq_context_save ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -74,8 +79,14 @@
/* resulting in version 6.1.9 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_fiq_context_save
.type _tx_thread_fiq_context_save,function
_tx_thread_fiq_context_save:
@@ -85,7 +96,7 @@ _tx_thread_fiq_context_save:
/* Check for a nested interrupt condition. */
STMDB sp!, {r0-r3} // Save some working registers
PUSH {r0-r3} // Save some working registers
LDR r3, =_tx_thread_system_state // Pickup address of system state variable
LDR r2, [r3] // Pickup system state
CMP r2, #0 // Is this the first interrupt?
@@ -101,7 +112,7 @@ _tx_thread_fiq_context_save:
MRS r0, SPSR // Pickup saved SPSR
SUB lr, lr, #4 // Adjust point of interrupt
STMDB sp!, {r0, r10, r12, lr} // Store other registers
PUSH {r0, r10, r12, lr} // Store other registers
/* Return to the ISR. */
@@ -134,7 +145,7 @@ __tx_thread_fiq_not_nested_save:
MRS r2, SPSR // Pickup saved SPSR
SUB lr, lr, #4 // Adjust point of interrupt
STMDB sp!, {r2, lr} // Store other registers, Note that we don't
PUSH {r2, lr} // Store other registers, Note that we don't
// need to save sl and ip since FIQ has
// copies of these registers. Nested
// interrupt processing does need to save
@@ -172,7 +183,7 @@ __tx_thread_fiq_idle_system_save:
MRS r0, SPSR // Pickup saved SPSR
SUB lr, lr, #4 // Adjust point of interrupt
STMDB sp!, {r0, lr} // Store other registers that will get used
PUSH {r0, lr} // Store other registers that will get used
// or stripped off the stack in context
// restore
B __tx_fiq_processing_return // Continue FIQ processing
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s
+14 -10
View File
@@ -20,6 +20,13 @@
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
#ifdef TX_ENABLE_FIQ_SUPPORT
DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts
#else
@@ -28,11 +35,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts
MODE_MASK = 0x1F // Mode mask
FIQ_MODE_BITS = 0x11 // FIQ mode bits
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end
since it will never be called 16-bit mode. */
.arm
.text
.align 2
/**************************************************************************/
@@ -40,7 +42,7 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fiq_nesting_end ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -82,8 +84,14 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_fiq_nesting_end
.type _tx_thread_fiq_nesting_end,function
_tx_thread_fiq_nesting_end:
@@ -97,8 +105,4 @@ _tx_thread_fiq_nesting_end:
ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
MSR CPSR_c, r0 // Reenter IRQ mode
#ifdef __THUMB_INTERWORK
BX r3 // Return to caller
#else
MOV pc, r3 // Return to caller
#endif
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s
+13 -9
View File
@@ -24,11 +24,13 @@ FIQ_DISABLE = 0x40 // FIQ disable bit
MODE_MASK = 0x1F // Mode mask
SYS_MODE_BITS = 0x1F // System mode bits
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start
since it will never be called 16-bit mode. */
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
.text
.align 2
/**************************************************************************/
@@ -36,7 +38,7 @@ SYS_MODE_BITS = 0x1F // System mode bits
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fiq_nesting_start ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -75,8 +77,14 @@ SYS_MODE_BITS = 0x1F // System mode bits
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_fiq_nesting_start
.type _tx_thread_fiq_nesting_start,function
_tx_thread_fiq_nesting_start:
@@ -89,8 +97,4 @@ _tx_thread_fiq_nesting_start:
// and push r1 just to keep 8-byte alignment
BIC r0, r0, #FIQ_DISABLE // Build enable FIQ CPSR
MSR CPSR_c, r0 // Enter system mode
#ifdef __THUMB_INTERWORK
BX r3 // Return to caller
#else
MOV pc, r3 // Return to caller
#endif
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s
+35 -32
View File
@@ -20,25 +20,18 @@
/**************************************************************************/
/**************************************************************************/
INT_MASK = 0x03F
/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for
applications calling this function from to 16-bit Thumb mode. */
.text
.align 2
.global $_tx_thread_interrupt_control
$_tx_thread_interrupt_control:
.thumb
BX pc // Switch to 32-bit mode
NOP //
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
STMFD sp!, {lr} // Save return address
BL _tx_thread_interrupt_control // Call _tx_thread_interrupt_control function
LDMFD sp!, {lr} // Recover saved return address
BX lr // Return to 16-bit caller
#endif
INT_MASK = 0x0C0
IRQ_MASK = 0x080
#ifdef TX_ENABLE_FIQ_SUPPORT
FIQ_MASK = 0x040
#endif
.text
.align 2
@@ -47,7 +40,7 @@ $_tx_thread_interrupt_control:
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -80,25 +73,35 @@ $_tx_thread_interrupt_control:
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_interrupt_control
.type _tx_thread_interrupt_control,function
_tx_thread_interrupt_control:
MRS r1, CPSR // Pickup current CPSR
/* Pickup current interrupt lockout posture. */
MRS r3, CPSR // Pickup current CPSR
MOV r2, #INT_MASK // Build interrupt mask
AND r1, r3, r2 // Clear interrupt lockout bits
ORR r1, r1, r0 // Or-in new interrupt lockout bits
/* Apply the new interrupt posture. */
MSR CPSR_c, r1 // Setup new CPSR
BIC r0, r3, r2 // Return previous interrupt mask
#ifdef __THUMB_INTERWORK
BX lr // Return to caller
#ifdef TX_ENABLE_FIQ_SUPPORT
CPSID if // Disable IRQ and FIQ
#else
MOV pc, lr // Return to caller
CPSID i // Disable IRQ
#endif
TST r0, #IRQ_MASK
BNE no_irq
CPSIE i
no_irq:
#ifdef TX_ENABLE_FIQ_SUPPORT
TST r0, #FIQ_MASK
BNE no_fiq
CPSIE f
no_fiq:
#endif
AND r0, r1, #INT_MASK
BX lr
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s
+12 -20
View File
@@ -20,22 +20,12 @@
/**************************************************************************/
/**************************************************************************/
/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for
applications calling this function from to 16-bit Thumb mode. */
.text
.align 2
.global $_tx_thread_interrupt_disable
$_tx_thread_interrupt_disable:
.thumb
BX pc // Switch to 32-bit mode
NOP //
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
STMFD sp!, {lr} // Save return address
BL _tx_thread_interrupt_disable // Call _tx_thread_interrupt_disable function
LDMFD sp!, {lr} // Recover saved return address
BX lr // Return to 16-bit caller
#endif
.text
.align 2
@@ -44,7 +34,7 @@ $_tx_thread_interrupt_disable:
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -76,8 +66,14 @@ $_tx_thread_interrupt_disable:
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_interrupt_disable
.type _tx_thread_interrupt_disable,function
_tx_thread_interrupt_disable:
@@ -94,8 +90,4 @@ _tx_thread_interrupt_disable:
CPSID i // Disable IRQ
#endif
#ifdef __THUMB_INTERWORK
BX lr // Return to caller
#else
MOV pc, lr // Return to caller
#endif
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s
+28 -20
View File
@@ -20,22 +20,18 @@
/**************************************************************************/
/**************************************************************************/
/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for
applications calling this function from to 16-bit Thumb mode. */
.text
.align 2
.global $_tx_thread_interrupt_restore
$_tx_thread_interrupt_restore:
.thumb
BX pc // Switch to 32-bit mode
NOP //
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
STMFD sp!, {lr} // Save return address
BL _tx_thread_interrupt_restore // Call _tx_thread_interrupt_restore function
LDMFD sp!, {lr} // Recover saved return address
BX lr // Return to 16-bit caller
#endif
INT_MASK = 0x0C0
IRQ_MASK = 0x080
#ifdef TX_ENABLE_FIQ_SUPPORT
FIQ_MASK = 0x040
#endif
.text
.align 2
@@ -44,7 +40,7 @@ $_tx_thread_interrupt_restore:
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -77,17 +73,29 @@ $_tx_thread_interrupt_restore:
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_interrupt_restore
.type _tx_thread_interrupt_restore,function
_tx_thread_interrupt_restore:
/* Apply the new interrupt posture. */
MSR CPSR_c, r0 // Setup new CPSR
#ifdef __THUMB_INTERWORK
BX lr // Return to caller
#else
MOV pc, lr // Return to caller
TST r0, #IRQ_MASK
BNE no_irq
CPSIE i
no_irq:
#ifdef TX_ENABLE_FIQ_SUPPORT
TST r0, #FIQ_MASK
BNE no_fiq
CPSIE f
no_fiq:
#endif
BX lr // Return to caller
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s
+14 -10
View File
@@ -20,6 +20,13 @@
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
#ifdef TX_ENABLE_FIQ_SUPPORT
DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts
#else
@@ -28,11 +35,6 @@ DISABLE_INTS = 0x80 // Disable IRQ interrupts
MODE_MASK = 0x1F // Mode mask
IRQ_MODE_BITS = 0x12 // IRQ mode bits
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end
since it will never be called 16-bit mode. */
.arm
.text
.align 2
/**************************************************************************/
@@ -40,7 +42,7 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits
/* FUNCTION RELEASE */
/* */
/* _tx_thread_irq_nesting_end ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -82,8 +84,14 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_irq_nesting_end
.type _tx_thread_irq_nesting_end,function
_tx_thread_irq_nesting_end:
@@ -96,8 +104,4 @@ _tx_thread_irq_nesting_end:
BIC r0, r0, #MODE_MASK // Clear mode bits
ORR r0, r0, #IRQ_MODE_BITS // Build IRQ mode CPSR
MSR CPSR_c, r0 // Reenter IRQ mode
#ifdef __THUMB_INTERWORK
BX r3 // Return to caller
#else
MOV pc, r3 // Return to caller
#endif
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s
+14 -10
View File
@@ -20,15 +20,17 @@
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
IRQ_DISABLE = 0x80 // IRQ disable bit
MODE_MASK = 0x1F // Mode mask
SYS_MODE_BITS = 0x1F // System mode bits
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start
since it will never be called 16-bit mode. */
.arm
.text
.align 2
/**************************************************************************/
@@ -36,7 +38,7 @@ SYS_MODE_BITS = 0x1F // System mode bits
/* FUNCTION RELEASE */
/* */
/* _tx_thread_irq_nesting_start ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -75,8 +77,14 @@ SYS_MODE_BITS = 0x1F // System mode bits
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_irq_nesting_start
.type _tx_thread_irq_nesting_start,function
_tx_thread_irq_nesting_start:
@@ -89,8 +97,4 @@ _tx_thread_irq_nesting_start:
// and push r1 just to keep 8-byte alignment
BIC r0, r0, #IRQ_DISABLE // Build enable IRQ CPSR
MSR CPSR_c, r0 // Enter system mode
#ifdef __THUMB_INTERWORK
BX r3 // Return to caller
#else
MOV pc, r3 // Return to caller
#endif
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s
+115 -71
View File
File diff suppressed because it is too large Load Diff
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s
+37 -37
View File
@@ -19,33 +19,24 @@
/** */
/**************************************************************************/
/**************************************************************************/
.arm
SVC_MODE = 0x13 // SVC mode
#ifdef TX_ENABLE_FIQ_SUPPORT
CPSR_MASK = 0xDF // Mask initial CPSR, IRQ & FIQ interrupts enabled
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
CPSR_MASK = 0x9F // Mask initial CPSR, IRQ interrupts enabled
.arm
#endif
USR_MODE = 0x10 // USR mode
SVC_MODE = 0x13 // SVC mode
SYS_MODE = 0x1F // SYS mode
THUMB_MASK = 0x20
/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for
applications calling this function from to 16-bit Thumb mode. */
.text
.align 2
.thumb
.global $_tx_thread_stack_build
.type $_tx_thread_stack_build,function
$_tx_thread_stack_build:
BX pc // Switch to 32-bit mode
NOP //
.arm
STMFD sp!, {lr} // Save return address
BL _tx_thread_stack_build // Call _tx_thread_stack_build function
LDMFD sp!, {lr} // Recover saved return address
BX lr // Return to 16-bit caller
#ifdef TX_ENABLE_FIQ_SUPPORT
CPSR_MASK = 0xFF // Mask initial CPSR, T, IRQ & FIQ interrupts enabled
#else
CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ interrupts enabled
#endif
.text
.align 2
@@ -54,7 +45,7 @@ $_tx_thread_stack_build:
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -89,8 +80,14 @@ $_tx_thread_stack_build:
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_stack_build
.type _tx_thread_stack_build,function
_tx_thread_stack_build:
@@ -128,6 +125,15 @@ _tx_thread_stack_build:
MOV r3, #1 // Build interrupt stack type
STR r3, [r2, #0] // Store stack type
MRS r3, CPSR // Pickup CPSR
BIC r3, #CPSR_MASK // Mask mode bits of CPSR
ORR r3, #SYS_MODE // Build CPSR, SYS mode, interrupts enabled
TST r1, #1 // Check if the initial PC is a Thumb function
IT NE
ORRNE r3, #THUMB_MASK // If the initial PC is a thumb function, CPSR must reflect this
STR r3, [r2, #4] // Store initial CPSR
MOV r3, #0 // Build initial register value
STR r3, [r2, #8] // Store initial r0
STR r3, [r2, #12] // Store initial r1
@@ -139,26 +145,20 @@ _tx_thread_stack_build:
STR r3, [r2, #36] // Store initial r7
STR r3, [r2, #40] // Store initial r8
STR r3, [r2, #44] // Store initial r9
LDR r3, [r0, #12] // Pickup stack starting address
STR r3, [r2, #48] // Store initial r10 (sl)
LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace
STR r3, [r2, #60] // Store initial r14 (lr)
MOV r3, #0 // Build initial register value
STR r3, [r2, #52] // Store initial r11
STR r3, [r2, #56] // Store initial r12
STR r1, [r2, #64] // Store initial pc
STR r3, [r2, #68] // 0 for back-trace
MRS r1, CPSR // Pickup CPSR
BIC r1, r1, #CPSR_MASK // Mask mode bits of CPSR
ORR r3, r1, #SVC_MODE // Build CPSR, SVC mode, interrupts enabled
STR r3, [r2, #4] // Store initial CPSR
LDR r3, [r0, #12] // Pickup stack starting address
STR r3, [r2, #48] // Store initial r10 (sl)
LDR r3,=_tx_thread_schedule // Pickup address of _tx_thread_schedule for GDB backtrace
STR r3, [r2, #60] // Store initial r14 (lr)
STR r1, [r2, #64] // Store initial pc
/* Setup stack pointer. */
STR r2, [r0, #8] // Save stack pointer in thread's
// control block
#ifdef __THUMB_INTERWORK
BX lr // Return to caller
#else
MOV pc, lr // Return to caller
#endif
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s
+21 -28
View File
@@ -20,32 +20,18 @@
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
.global _tx_thread_current_ptr
.global _tx_timer_time_slice
.global _tx_thread_schedule
/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for
applications calling this function from to 16-bit Thumb mode. */
.text
.align 2
.global $_tx_thread_system_return
.type $_tx_thread_system_return,function
$_tx_thread_system_return:
.thumb
BX pc // Switch to 32-bit mode
NOP //
.arm
STMFD sp!, {lr} // Save return address
BL _tx_thread_system_return // Call _tx_thread_system_return function
LDMFD sp!, {lr} // Recover saved return address
BX lr // Return to 16-bit caller
SYS_MODE = 0x1F // SYS mode
.text
.align 2
@@ -54,7 +40,7 @@ $_tx_thread_system_return:
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -92,15 +78,21 @@ $_tx_thread_system_return:
/* resulting in version 6.1.9 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_system_return
.type _tx_thread_system_return,function
_tx_thread_system_return:
/* Save minimal context on the stack. */
STMDB sp!, {r4-r11, lr} // Save minimal context
PUSH {r4-r11, lr} // Save minimal context
LDR r4, =_tx_thread_current_ptr // Pickup address of current ptr
LDR r5, [r4] // Pickup current thread pointer
@@ -117,15 +109,16 @@ _tx_skip_solicited_vfp_save:
#endif
MOV r0, #0 // Build a solicited stack type
MRS r1, CPSR // Pickup the CPSR
STMDB sp!, {r0-r1} // Save type and CPSR
/* Lockout interrupts. */
MRS r1, CPSR // Pickup the CPSR, T bit is always cleared by hardware
TST lr, #1 // Check if calling function is in Thumb mode
IT NE
ORRNE r1, #0x20 // Set the T bit so that the correct mode is set on return
PUSH {r0-r1} // Save type and CPSR
#ifdef TX_ENABLE_FIQ_SUPPORT
CPSID if // Disable IRQ and FIQ interrupts
CPSID if // Disable IRQ and FIQ
#else
CPSID i // Disable IRQ interrupts
CPSID i // Disable IRQ
#endif
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s
+13 -3
View File
@@ -19,17 +19,21 @@
/** */
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
.global _tx_thread_system_state
.global _tx_thread_current_ptr
.global _tx_execution_isr_enter
/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save
since it will never be called 16-bit mode. */
.arm
.text
.align 2
/**************************************************************************/
@@ -37,7 +41,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_vectored_context_save ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -74,8 +78,14 @@
/* resulting in version 6.1.9 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_thread_vectored_context_save
.type _tx_thread_vectored_context_save,function
_tx_thread_vectored_context_save:
ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s
+14 -29
View File
@@ -20,8 +20,12 @@
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
/* Define Assembly language external references... */
@@ -34,26 +38,6 @@
.global _tx_timer_expired
.global _tx_thread_time_slice
/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for
applications calling this function from to 16-bit Thumb mode. */
.text
.align 2
.thumb
.global $_tx_timer_interrupt
.type $_tx_timer_interrupt,function
$_tx_timer_interrupt:
BX pc // Switch to 32-bit mode
NOP //
.arm
STMFD sp!, {lr} // Save return address
BL _tx_timer_interrupt // Call _tx_timer_interrupt function
LDMFD sp!, {lr} // Recover saved return address
BX lr // Return to 16-bit caller
.text
.align 2
/**************************************************************************/
@@ -61,7 +45,7 @@ $_tx_timer_interrupt:
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt ARMv7-A */
/* 6.1.11 */
/* 6.x */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -98,8 +82,14 @@ $_tx_timer_interrupt:
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-25-2022 Zhen Kong Updated comments, */
/* resulting in version 6.1.11 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _tx_timer_interrupt
.type _tx_timer_interrupt,function
_tx_timer_interrupt:
@@ -191,7 +181,7 @@ __tx_timer_done:
__tx_something_expired:
STMDB sp!, {r0, lr} // Save the lr register on the stack
PUSH {r0, lr} // Save the lr register on the stack
// and save r0 just to keep 8-byte alignment
/* Did a timer expire? */
@@ -219,13 +209,8 @@ __tx_timer_dont_activate:
__tx_timer_not_ts_expiration:
LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for
// the 8-byte stack alignment
POP {r0, lr} // Recover lr register (r0 is just there for the 8-byte stack alignment
__tx_timer_nothing_expired:
#ifdef __THUMB_INTERWORK
BX lr // Return to caller
#else
MOV pc, lr // Return to caller
#endif
ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s
+20 -5
View File
@@ -20,6 +20,12 @@
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
#define THUMB_MASK 0x20 // THUMB bit
#define USR_MODE 0x10 // USR mode
@@ -35,7 +41,7 @@
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/GNU */
/* 6.2.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -68,11 +74,18 @@
/* DATE NAME DESCRIPTION */
/* */
/* 03-08-2023 Scott Larson Initial Version 6.2.1 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
// {
.text
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _txm_module_manager_thread_stack_build
.type _txm_module_manager_thread_stack_build, "function"
_txm_module_manager_thread_stack_build:
@@ -132,13 +145,15 @@ _txm_module_manager_thread_stack_build:
STR r1, [r2, #64] // Store initial pc
STR r3, [r2, #68] // 0 for back-trace
MRS r3, CPSR // Pickup CPSR
BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR
BIC r3, #CPSR_MASK // Mask mode bits of CPSR
TST r1, #1 // Test if THUMB bit set in initial PC
ORRNE r3, r3, #THUMB_MASK // Set T bit if set
IT NE
ORRNE r3, #THUMB_MASK // Set T bit if set
LDR r1, [r0, #156] // Load tx_thread_module_current_user_mode
TST r1, #1 // Test if the flag is set
ORREQ r3, r3, #SYS_MODE // Flag not set: Build CPSR, SYS mode, IRQ enabled
ORRNE r3, r3, #USR_MODE // Flag set: Build CPSR, USR mode, IRQ enabled
ITE EQ
ORREQ r3, #SYS_MODE // Flag not set: Build CPSR, SYS mode, IRQ enabled
ORRNE r3, #USR_MODE // Flag set: Build CPSR, USR mode, IRQ enabled
STR r3, [r2, #4] // Store initial CPSR
/* Setup stack pointer. */
ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s
+24 -4
View File
@@ -19,16 +19,21 @@
/** */
/**************************************************************************/
/**************************************************************************/
.syntax unified
#if defined(THUMB_MODE)
.thumb
#else
.arm
#endif
.global _txm_module_manager_kernel_dispatch
.global _txm_system_mode_enter
.global _txm_system_mode_exit
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_user_mode_entry Cortex-A7/MMU/GNU */
/* 6.2.1 */
/* 6.x */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -59,23 +64,38 @@
/* DATE NAME DESCRIPTION */
/* */
/* 03-08-2023 Scott Larson Initial Version 6.2.1 */
/* xx-xx-xxxx Yajun Xia Updated comments, */
/* Added thumb mode support, */
/* resulting in version 6.x */
/* */
/**************************************************************************/
.text
.align 12
.eabi_attribute Tag_ABI_align_preserved, 1
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _txm_module_manager_user_mode_entry
.type _txm_module_manager_user_mode_entry, "function"
_txm_module_manager_user_mode_entry:
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _txm_system_mode_enter
_txm_system_mode_enter:
SVC 1 // Get out of user mode
_txm_module_priv:
// At this point, we are in system mode.
// Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function.
PUSH {r3, lr}
BL _txm_module_manager_kernel_dispatch
POP {r3, lr}
#if defined(THUMB_MODE)
.thumb_func
#endif
.global _txm_system_mode_exit
_txm_system_mode_exit:
// Trap to restore user mode while inside of ThreadX
test/ports/azrtos_cicd.csv
+5 -5
View File
@@ -133,11 +133,11 @@
"ThreadX Modules for Cortex M33 using the ARM compiler v6", "TXM ThreadX Modules ARM Cortex M33 ARM compiler v6 KEIL MDK v5", "ports_module\cortex_m33\ac6\example_build", "Win32NT", "azrtos_setenv_mdk5.bat", "azrtos_clean_txm_tz_mdk5.bat", "azrtos_setenv_mdk5.bat", "azrtos_build_txm_tz_mdk5.bat", "", ""
"ThreadX Modules for Cortex A35 using the ARM compiler v6", "TXM ThreadX Modules ARM Cortex A35 ARMv8-A ARM compiler v6", "ports_module\cortex_a35\ac6\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_setenv_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
### GCC
"ThreadX Modules for Cortex M0+ using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex M0+ GNU GCC", "ports_module\cortex_m0+\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex M3 using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex M3 GNU GCC", "ports_module\cortex_m3\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex M4 using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex M4 GNU GCC", "ports_module\cortex_m4\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex M7 using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex M7 GNU GCC", "ports_module\cortex_m7\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex A35 using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex A35 ARMv8-A GNU GCC", "ports_module\cortex_a35\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex M0+ using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex M0+ GNU GCC", "ports_module\cortex_m0+\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_setenv_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex M3 using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex M3 GNU GCC", "ports_module\cortex_m3\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_setenv_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex M4 using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex M4 GNU GCC", "ports_module\cortex_m4\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_setenv_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex M7 using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex M7 GNU GCC", "ports_module\cortex_m7\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_setenv_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
"ThreadX Modules for Cortex A35 using the GNU Compiler Collection", "TXM ThreadX Modules ARM Cortex A35 ARMv8-A GNU GCC", "ports_module\cortex_a35\gnu\example_build", "Win32NT", "azrtos_setenv_arm_ds.bat", "azrtos_clean_txm_arm_ds.bat", "azrtos_setenv_arm_ds.bat", "azrtos_build_txm_arm_ds.bat", "", ""
##############################################################################
# ThreadX SMP
##############################################################################
1 Name Keywords Path HostPlatform CleanEnvScript CleanScript BuildEnvScript BuildScript TestEnvScript TestScript
133 ThreadX Modules for Cortex A35 using the ARM compiler v6 TXM ThreadX Modules ARM Cortex A35 ARMv8-A ARM compiler v6 ports_module\cortex_a35\ac6\example_build Win32NT azrtos_setenv_arm_ds.bat azrtos_clean_txm_arm_ds.bat azrtos_setenv_arm_ds.bat azrtos_build_txm_arm_ds.bat
134 ### GCC
135 ThreadX Modules for Cortex M0+ using the GNU Compiler Collection TXM ThreadX Modules ARM Cortex M0+ GNU GCC ports_module\cortex_m0+\gnu\example_build Win32NT azrtos_setenv_arm_ds.bat azrtos_clean_txm_arm_ds.bat azrtos_build_txm_arm_ds.bat azrtos_setenv_arm_ds.bat azrtos_build_txm_arm_ds.bat
136 ThreadX Modules for Cortex M3 using the GNU Compiler Collection TXM ThreadX Modules ARM Cortex M3 GNU GCC ports_module\cortex_m3\gnu\example_build Win32NT azrtos_setenv_arm_ds.bat azrtos_clean_txm_arm_ds.bat azrtos_build_txm_arm_ds.bat azrtos_setenv_arm_ds.bat azrtos_build_txm_arm_ds.bat
137 ThreadX Modules for Cortex M4 using the GNU Compiler Collection TXM ThreadX Modules ARM Cortex M4 GNU GCC ports_module\cortex_m4\gnu\example_build Win32NT azrtos_setenv_arm_ds.bat azrtos_clean_txm_arm_ds.bat azrtos_build_txm_arm_ds.bat azrtos_setenv_arm_ds.bat azrtos_build_txm_arm_ds.bat
138 ThreadX Modules for Cortex M7 using the GNU Compiler Collection TXM ThreadX Modules ARM Cortex M7 GNU GCC ports_module\cortex_m7\gnu\example_build Win32NT azrtos_setenv_arm_ds.bat azrtos_clean_txm_arm_ds.bat azrtos_build_txm_arm_ds.bat azrtos_setenv_arm_ds.bat azrtos_build_txm_arm_ds.bat
139 ThreadX Modules for Cortex A35 using the GNU Compiler Collection TXM ThreadX Modules ARM Cortex A35 ARMv8-A GNU GCC ports_module\cortex_a35\gnu\example_build Win32NT azrtos_setenv_arm_ds.bat azrtos_clean_txm_arm_ds.bat azrtos_build_txm_arm_ds.bat azrtos_setenv_arm_ds.bat azrtos_build_txm_arm_ds.bat
140 ##############################################################################
141 # ThreadX SMP
142 ##############################################################################
143 ### ARM compiler v6 - ARMv8-A-SMP legacy