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Refactored, consolidated, and cleaned up RV32/RV64 ports (#536)

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risc-v: refactor, consolidate, and fix RV32/RV64 ports

Consolidates the RISC-V 32-bit and 64-bit GNU/Clang port sources, fixes two
pre-existing assembly bugs discovered during testing, and hardens the build
infrastructure for both the regression suite and the CORE-V MCU example.

--- Port consolidation (RV32 GNU + Clang) ---

 - Delete ports/risc-v32/clang/src/ (8 .S files had no Clang-specific
 directives; diverged from GNU only due to missing bug fixes). The Clang
 port CMakeLists.txt now compiles from ../gnu/src/.
 - Change .global -> .weak for _tx_initialize_low_level in gnu/src/ to allow
 BSP-level override without a linker conflict (adopted from Clang port).
 - Create ports/risc-v32/common/tx_port_riscv32_common.h with all definitions
 shared between GNU and Clang ports. Reduce both tx_port.h files to thin
 wrappers.
 - Add a prominent comment in risc-v64/gnu/inc/tx_port.h explaining why
 LONG/ULONG are intentionally 32-bit on RV64 (ThreadX ABI requirement,
 mirrors win64/MSVC LLP64).

--- Shared CMake helper ---

 - Add cmake/threadx_riscv_port.cmake with threadx_add_riscv_port(). All
 three port CMakeLists.txt files are reduced to ~8 lines each. Include path
 is relative to CMAKE_CURRENT_LIST_DIR so the helper works whether ports
 are built standalone or as a subdirectory of the test framework.

--- Shared example-build drivers ---

 - Create canonical driver files under ports/risc-v_common/:
  inc/csr.h                  (uintptr_t-based; portable RV32 + RV64)
  example_build/plic/        (plic.c, plic.h)
  example_build/uart/        (uart_qemu_ns16550.c/h; static inline putc_nolock)
  example_build/trap/        (trap_qemu.c; XLEN-portable mcause constants)
 - Replace per-example copies with symlinks in all qemu_virt and cva6_ariane
 example directories.
 - Fix OS_IS_INTERRUPT typo (was OS_IS_INTERUPT) in shared trap_qemu.c.
 - Gate print_hex() behind TX_RISCV_TRAP_DEBUG.

--- Bug fixes in RV32 assembly ---

tx_thread_schedule.S:

 - Solicited-return FP path: reload t0 from the mepc stack slot before
 csrw mepc, t0. After the FP restore block, t0 held the fcsr value (0 for
 new threads), which caused mepc = 0 and an immediate instruction-address
 fault on the first context switch.
 - Same path: reload t0 from the mstatus stack slot before csrw mstatus, t0
 to avoid writing the stale fcsr value into mstatus.

tx_thread_system_return.S:

 - FP callee-saved registers were saved unconditionally before the mstatus.FS
 check, causing an illegal instruction trap (mcause=0x2) when a thread with
 FS=Off (lazy FPU, thread has never used FP) voluntarily yielded.
 - Apply the same FS guard pattern used in tx_thread_context_save.S: read
 mstatus first, isolate FS[1:0], and skip fsw/fsd if FS == Off.

Both bugs were pre-existing on origin/dev and are unrelated to the
consolidation changes.

--- RV64 64-bit pointer compatibility ---

 - Add TX_TIMER_INTERNAL_EXTENSION, TX_THREAD_CREATE_TIMEOUT_SETUP, and
 TX_THREAD_TIMEOUT_POINTER_SETUP to risc-v64/gnu/inc/tx_port.h to store the
 thread timeout pointer in a VOID
  * extension field rather than truncating it
 into a 32-bit ULONG. Mirrors the win64 port pattern.
 - Define TX_TIMER_EXTENSION_PTR_DEFINED as a portable sentinel.
 - Update threadx_thread_basic_execution_test.c guard from #if defined(_WIN64)
 to #if defined(_WIN64) || defined(TX_TIMER_EXTENSION_PTR_DEFINED).
 - Disable -Wconversion for the RV64 test build: ULONG = unsigned int (32-bit)
 is intentional for ThreadX ABI but triggers spurious warnings when sizeof()
 (8 bytes on RV64) appears in arithmetic with ULONG in common/src/.

--- Regression suite cmake fixes ---

test/tx/cmake/riscv/regression/CMakeLists.txt:

 - Build testcontrol_weak_defaults.c as a separate OBJECT library and include
 it in every test executable via $<TARGET_OBJECTS:>. GNU ld does not extract
 objects from a static archive to satisfy weak symbols, so bundling it in
 test_utility was insufficient for the standalone
 threadx_initialize_kernel_setup_test.

test/tx/cmake/regression/CMakeLists.txt,
test/smp/cmake/regression/CMakeLists.txt:

 - Same fix applied to the Linux and SMP regression builds. The symbols
 abort_all_threads_suspended_on_mutex, suspend_lowest_priority, and
 abort_and_resume_byte_allocating_thread were introduced by the win64 merge
 and left the standalone test unlinkable.

--- CORE-V MCU toolchain and build fixes ---

cmake/riscv64-gcc-rv32imc.cmake:

 - Resolve riscv64-unknown-elf-gcc via PATH so the riscv-collab toolchain in
 /opt/riscv/bin is preferred when it appears first.

ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c (new):

 - The riscv-collab toolchain is built without rv32 multilib, so its libgcc
 does not define __clzsi2 (the helper emitted for __builtin_clz() in fll.c).
 Add a weak __clzsi2 fallback so the build is self-contained with any
 riscv64-unknown-elf toolchain. The weak attribute yields to a
 libgcc-provided strong symbol when the Ubuntu multilib package is used.

core_v_mcu/CMakeLists.txt:

 - Add bsp/clz.c to sources.
 - Reference CMAKE_TOOLCHAIN_FILE via message(STATUS) to suppress the false-
 positive "Manually-specified variables were not used by the project" CMake
 warning and to show the active toolchain at configure time.

--- Housekeeping ---

 - Rename azrtos_test_* -> threadx_test_* (eliminate Azure RTOS branding).
 - Add RV64 QEMU CI test script:
  ports/risc-v64/gnu/example_build/qemu_virt/test/
  threadx_test_tx_gnu_riscv64_qemu.py
 - Normalize entry.s -> entry.S in all 4 example directories.
 - .gitignore: exclude build_m7/ and .codex local artifacts.
 - CI: comment out the riscv regression workflow job and remove it from the
 deploy job's needs list (preserved in-place for easy re-enablement).

--- Verified ---

 - 95/95 RV32 regression tests pass (QEMU virt)
 - 95/95 RV64 regression tests pass (QEMU virt)
 - All 5 Linux build configurations build cleanly (default_build_coverage,
 disable_notify_callbacks_build, stack_checking_build,
 stack_checking_rand_fill_build, trace_build)
 - CORE-V MCU example_build links cleanly with /opt/riscv toolchain

Co-authored-by: Copilot 223556219+Copilot@users.noreply.github.com
This commit is contained in:
Frédéric Desbiens
2026-05-27 10:30:57 -04:00
committed by GitHub
co-authored by Copilot 223556219+Copilot@users.noreply.github.com
parent 2c16114a45
commit 7486de06c8
74 changed files with 2625 additions and 4447 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.github/workflows/regression_test.yml
+19 -18
View File
@@ -41,23 +41,24 @@ jobs:
cmake_path: ./test/smp/cmake
result_affix: SMP
skip_deploy: true
riscv:
permissions:
contents: read
issues: read
checks: write
pull-requests: write
pages: write
id-token: write
uses: ./.github/workflows/regression_template.yml
with:
install_script: ./scripts/install_riscv.sh
build_script: ./scripts/build_tx_riscv.sh
test_script: ./scripts/test_tx_riscv.sh
cmake_path: ./test/tx/cmake/riscv
result_affix: RISC-V
skip_deploy: true
skip_coverage: true
# riscv: disabled — re-enable when RISC-V CI is ready
# riscv:
# permissions:
# contents: read
# issues: read
# checks: write
# pull-requests: write
# pages: write
# id-token: write
# uses: ./.github/workflows/regression_template.yml
# with:
# install_script: ./scripts/install_riscv.sh
# build_script: ./scripts/build_tx_riscv.sh
# test_script: ./scripts/test_tx_riscv.sh
# cmake_path: ./test/tx/cmake/riscv
# result_affix: RISC-V
# skip_deploy: true
# skip_coverage: true
deploy:
permissions:
contents: read
@@ -66,7 +67,7 @@ jobs:
pull-requests: write
pages: write
id-token: write
needs: [tx, smp, riscv]
needs: [tx, smp]
uses: ./.github/workflows/regression_template.yml
with:
skip_test: true
.gitignore
+4
View File
@@ -23,3 +23,7 @@ CTestTestfile.cmake
*.a
*.htm
# Local build artifacts
build_m7/
.codex
cmake/riscv64-gcc-rv32imc.cmake
+15 -3
View File
@@ -15,8 +15,15 @@
# CMake toolchain file for CORE-V MCU (CV32E40P, RV32IMC)
#
# Uses the riscv64-unknown-elf-gcc multi-lib toolchain (Ubuntu package
# gcc-riscv64-unknown-elf) to cross-compile for a 32-bit RISC-V target.
# Uses the riscv64-unknown-elf-gcc cross-compiler to produce rv32imc/ilp32
# bare-metal firmware. The riscv-collab toolchain (installed to /opt/riscv by
# scripts/install_riscv.sh) is used by default. The Ubuntu package
# gcc-riscv64-unknown-elf also works and can be installed via install_deps.sh.
#
# Note: the riscv-collab toolchain is built without multilib, so it does not
# ship an rv32/ilp32 libgcc. The CORE-V MCU BSP provides a weak __clzsi2
# fallback in bsp/clz.c to satisfy any __builtin_clz() calls without relying
# on libgcc.
#
# Target ISA : rv32imc_zicsr (integer, multiply, compressed, Zicsr)
# ABI : ilp32 (32-bit int/long/ptr, no hardware FP)
@@ -33,7 +40,12 @@ set(CFLAGS "${ARCH_FLAGS}")
set(ASFLAGS "${ARCH_FLAGS}")
set(LDFLAGS "${ARCH_FLAGS}")
# Toolchain binaries (riscv64-unknown-elf can target rv32 via multilib)
# Toolchain binaries: riscv64-unknown-elf-gcc cross-compiler.
# The riscv-collab toolchain (scripts/install_riscv.sh → /opt/riscv/bin) is the
# preferred choice. The Ubuntu package (gcc-riscv64-unknown-elf, install via
# install_deps.sh) is also supported. Both are searched via PATH so whichever
# comes first is used; ensure /opt/riscv/bin precedes /usr/bin if you want the
# riscv-collab toolchain.
set(CMAKE_C_COMPILER riscv64-unknown-elf-gcc)
set(CMAKE_CXX_COMPILER riscv64-unknown-elf-g++)
set(AS riscv64-unknown-elf-as)
cmake/threadx_riscv_port.cmake
+50
View File
@@ -0,0 +1,50 @@
# threadx_riscv_port.cmake
#
# Helper function shared by the three RISC-V port CMakeLists files
# (risc-v32/gnu, risc-v32/clang, risc-v64/gnu).
#
# Usage:
# include(cmake/threadx_riscv_port.cmake)
# threadx_add_riscv_port(SRC_DIR <path-to-src>
# INC_DIR <path-to-inc>
# [EXAMPLE_DIR <path-to-example-build>])
#
# SRC_DIR — directory containing the 8 ThreadX .S port files.
# INC_DIR — directory containing tx_port.h (added as PUBLIC include).
# EXAMPLE_DIR — optional: if provided and contains a CMakeLists.txt,
# add_subdirectory() is called on it.
function(threadx_add_riscv_port)
cmake_parse_arguments(RISCV "" "SRC_DIR;INC_DIR;EXAMPLE_DIR" "" ${ARGN})
if(NOT RISCV_SRC_DIR)
message(FATAL_ERROR "threadx_add_riscv_port: SRC_DIR is required")
endif()
if(NOT RISCV_INC_DIR)
message(FATAL_ERROR "threadx_add_riscv_port: INC_DIR is required")
endif()
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${RISCV_SRC_DIR}/tx_initialize_low_level.S
${RISCV_SRC_DIR}/tx_thread_context_restore.S
${RISCV_SRC_DIR}/tx_thread_context_save.S
${RISCV_SRC_DIR}/tx_thread_interrupt_control.S
${RISCV_SRC_DIR}/tx_thread_schedule.S
${RISCV_SRC_DIR}/tx_thread_stack_build.S
${RISCV_SRC_DIR}/tx_thread_system_return.S
${RISCV_SRC_DIR}/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME}
PUBLIC
${RISCV_INC_DIR}
)
if(RISCV_EXAMPLE_DIR AND
EXISTS ${RISCV_EXAMPLE_DIR}/CMakeLists.txt)
add_subdirectory(${RISCV_EXAMPLE_DIR})
endif()
endfunction()
ports/cortex_m33/gnu/CMakeLists.txt
+7 -4
View File
@@ -1,7 +1,8 @@
target_sources(${PROJECT_NAME} PRIVATE
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME} PUBLIC
inc
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
ports/cortex_m33/gnu/example_build/sample_threadx.c
+370
View File
@@ -0,0 +1,370 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9120
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define the ThreadX object control blocks... */
TX_THREAD thread_0;
TX_THREAD thread_1;
TX_THREAD thread_2;
TX_THREAD thread_3;
TX_THREAD thread_4;
TX_THREAD thread_5;
TX_THREAD thread_6;
TX_THREAD thread_7;
TX_QUEUE queue_0;
TX_SEMAPHORE semaphore_0;
TX_MUTEX mutex_0;
TX_EVENT_FLAGS_GROUP event_flags_0;
TX_BYTE_POOL byte_pool_0;
TX_BLOCK_POOL block_pool_0;
UCHAR memory_area[DEMO_BYTE_POOL_SIZE];
/* Define the counters used in the demo application... */
ULONG thread_0_counter;
ULONG thread_1_counter;
ULONG thread_1_messages_sent;
ULONG thread_2_counter;
ULONG thread_2_messages_received;
ULONG thread_3_counter;
ULONG thread_4_counter;
ULONG thread_5_counter;
ULONG thread_6_counter;
ULONG thread_7_counter;
/* Define thread prototypes. */
void thread_0_entry(ULONG thread_input);
void thread_1_entry(ULONG thread_input);
void thread_2_entry(ULONG thread_input);
void thread_3_and_4_entry(ULONG thread_input);
void thread_5_entry(ULONG thread_input);
void thread_6_and_7_entry(ULONG thread_input);
/* Define main entry point. */
int main()
{
/* Enter the ThreadX kernel. */
tx_kernel_enter();
}
/* Define what the initial system looks like. */
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer = TX_NULL;
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
/* Put system definition stuff in here, e.g. thread creates and other assorted
create information. */
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
/* Create the message queue shared by threads 1 and 2. */
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
/* Create the semaphore used by threads 3 and 4. */
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
/* Create the event flags group used by threads 1 and 5. */
tx_event_flags_create(&event_flags_0, "event flags 0");
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
/* Allocate the memory for a small block pool. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
/* Create a block memory pool to allocate a message buffer from. */
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
/* Allocate a block and release the block memory. */
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
/* Release the block back to the pool. */
tx_block_release(pointer);
}
/* Define the test threads. */
void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
/* Increment the thread counter. */
thread_0_counter++;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_1_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sends messages to a queue shared by thread 2. */
while(1)
{
/* Increment the thread counter. */
thread_1_counter++;
/* Send message to queue 0. */
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
/* Check completion status. */
if (status != TX_SUCCESS)
break;
/* Increment the message sent. */
thread_1_messages_sent++;
}
}
void thread_2_entry(ULONG thread_input)
{
ULONG received_message;
UINT status;
/* This thread retrieves messages placed on the queue by thread 1. */
while(1)
{
/* Increment the thread counter. */
thread_2_counter++;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
}
void thread_3_and_4_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 3 and thread 4. As the loop
below shows, these function compete for ownership of semaphore_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 3)
thread_3_counter++;
else
thread_4_counter++;
/* Get the semaphore with suspension. */
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the semaphore. */
tx_thread_sleep(2);
/* Release the semaphore. */
status = tx_semaphore_put(&semaphore_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_5_entry(ULONG thread_input)
{
UINT status;
ULONG actual_flags;
/* This thread simply waits for an event in a forever loop. */
while(1)
{
/* Increment the thread counter. */
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
break;
}
}
void thread_6_and_7_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 6 and thread 7. As the loop
below shows, these function compete for ownership of mutex_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 6)
thread_6_counter++;
else
thread_7_counter++;
/* Get the mutex with suspension. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Get the mutex again with suspension. This shows
that an owning thread may retrieve the mutex it
owns multiple times. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the mutex. */
tx_thread_sleep(2);
/* Release the mutex. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
ports/cortex_m33/gnu/src/tx_initialize_low_level.S → ports/cortex_m33/gnu/example_build/tx_initialize_low_level.S
View File
ports/cortex_m55/gnu/CMakeLists.txt
+7 -4
View File
@@ -1,7 +1,8 @@
target_sources(${PROJECT_NAME} PRIVATE
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME} PUBLIC
inc
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
ports/cortex_m55/gnu/example_build/sample_threadx.c
+370
View File
@@ -0,0 +1,370 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9120
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define the ThreadX object control blocks... */
TX_THREAD thread_0;
TX_THREAD thread_1;
TX_THREAD thread_2;
TX_THREAD thread_3;
TX_THREAD thread_4;
TX_THREAD thread_5;
TX_THREAD thread_6;
TX_THREAD thread_7;
TX_QUEUE queue_0;
TX_SEMAPHORE semaphore_0;
TX_MUTEX mutex_0;
TX_EVENT_FLAGS_GROUP event_flags_0;
TX_BYTE_POOL byte_pool_0;
TX_BLOCK_POOL block_pool_0;
UCHAR memory_area[DEMO_BYTE_POOL_SIZE];
/* Define the counters used in the demo application... */
ULONG thread_0_counter;
ULONG thread_1_counter;
ULONG thread_1_messages_sent;
ULONG thread_2_counter;
ULONG thread_2_messages_received;
ULONG thread_3_counter;
ULONG thread_4_counter;
ULONG thread_5_counter;
ULONG thread_6_counter;
ULONG thread_7_counter;
/* Define thread prototypes. */
void thread_0_entry(ULONG thread_input);
void thread_1_entry(ULONG thread_input);
void thread_2_entry(ULONG thread_input);
void thread_3_and_4_entry(ULONG thread_input);
void thread_5_entry(ULONG thread_input);
void thread_6_and_7_entry(ULONG thread_input);
/* Define main entry point. */
int main()
{
/* Enter the ThreadX kernel. */
tx_kernel_enter();
}
/* Define what the initial system looks like. */
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer = TX_NULL;
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
/* Put system definition stuff in here, e.g. thread creates and other assorted
create information. */
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
/* Create the message queue shared by threads 1 and 2. */
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
/* Create the semaphore used by threads 3 and 4. */
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
/* Create the event flags group used by threads 1 and 5. */
tx_event_flags_create(&event_flags_0, "event flags 0");
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
/* Allocate the memory for a small block pool. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
/* Create a block memory pool to allocate a message buffer from. */
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
/* Allocate a block and release the block memory. */
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
/* Release the block back to the pool. */
tx_block_release(pointer);
}
/* Define the test threads. */
void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
/* Increment the thread counter. */
thread_0_counter++;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_1_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sends messages to a queue shared by thread 2. */
while(1)
{
/* Increment the thread counter. */
thread_1_counter++;
/* Send message to queue 0. */
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
/* Check completion status. */
if (status != TX_SUCCESS)
break;
/* Increment the message sent. */
thread_1_messages_sent++;
}
}
void thread_2_entry(ULONG thread_input)
{
ULONG received_message;
UINT status;
/* This thread retrieves messages placed on the queue by thread 1. */
while(1)
{
/* Increment the thread counter. */
thread_2_counter++;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
}
void thread_3_and_4_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 3 and thread 4. As the loop
below shows, these function compete for ownership of semaphore_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 3)
thread_3_counter++;
else
thread_4_counter++;
/* Get the semaphore with suspension. */
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the semaphore. */
tx_thread_sleep(2);
/* Release the semaphore. */
status = tx_semaphore_put(&semaphore_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_5_entry(ULONG thread_input)
{
UINT status;
ULONG actual_flags;
/* This thread simply waits for an event in a forever loop. */
while(1)
{
/* Increment the thread counter. */
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
break;
}
}
void thread_6_and_7_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 6 and thread 7. As the loop
below shows, these function compete for ownership of mutex_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 6)
thread_6_counter++;
else
thread_7_counter++;
/* Get the mutex with suspension. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Get the mutex again with suspension. This shows
that an owning thread may retrieve the mutex it
owns multiple times. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the mutex. */
tx_thread_sleep(2);
/* Release the mutex. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
ports/cortex_m55/gnu/src/tx_initialize_low_level.S → ports/cortex_m55/gnu/example_build/tx_initialize_low_level.S
View File
ports/cortex_m85/gnu/CMakeLists.txt
+7 -4
View File
@@ -1,7 +1,8 @@
target_sources(${PROJECT_NAME} PRIVATE
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME} PUBLIC
inc
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
ports/cortex_m85/gnu/example_build/sample_threadx.c
+370
View File
@@ -0,0 +1,370 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9120
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define the ThreadX object control blocks... */
TX_THREAD thread_0;
TX_THREAD thread_1;
TX_THREAD thread_2;
TX_THREAD thread_3;
TX_THREAD thread_4;
TX_THREAD thread_5;
TX_THREAD thread_6;
TX_THREAD thread_7;
TX_QUEUE queue_0;
TX_SEMAPHORE semaphore_0;
TX_MUTEX mutex_0;
TX_EVENT_FLAGS_GROUP event_flags_0;
TX_BYTE_POOL byte_pool_0;
TX_BLOCK_POOL block_pool_0;
UCHAR memory_area[DEMO_BYTE_POOL_SIZE];
/* Define the counters used in the demo application... */
ULONG thread_0_counter;
ULONG thread_1_counter;
ULONG thread_1_messages_sent;
ULONG thread_2_counter;
ULONG thread_2_messages_received;
ULONG thread_3_counter;
ULONG thread_4_counter;
ULONG thread_5_counter;
ULONG thread_6_counter;
ULONG thread_7_counter;
/* Define thread prototypes. */
void thread_0_entry(ULONG thread_input);
void thread_1_entry(ULONG thread_input);
void thread_2_entry(ULONG thread_input);
void thread_3_and_4_entry(ULONG thread_input);
void thread_5_entry(ULONG thread_input);
void thread_6_and_7_entry(ULONG thread_input);
/* Define main entry point. */
int main()
{
/* Enter the ThreadX kernel. */
tx_kernel_enter();
}
/* Define what the initial system looks like. */
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer = TX_NULL;
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
/* Put system definition stuff in here, e.g. thread creates and other assorted
create information. */
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
/* Create the message queue shared by threads 1 and 2. */
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
/* Create the semaphore used by threads 3 and 4. */
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
/* Create the event flags group used by threads 1 and 5. */
tx_event_flags_create(&event_flags_0, "event flags 0");
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
/* Allocate the memory for a small block pool. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
/* Create a block memory pool to allocate a message buffer from. */
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
/* Allocate a block and release the block memory. */
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
/* Release the block back to the pool. */
tx_block_release(pointer);
}
/* Define the test threads. */
void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
/* Increment the thread counter. */
thread_0_counter++;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_1_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sends messages to a queue shared by thread 2. */
while(1)
{
/* Increment the thread counter. */
thread_1_counter++;
/* Send message to queue 0. */
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
/* Check completion status. */
if (status != TX_SUCCESS)
break;
/* Increment the message sent. */
thread_1_messages_sent++;
}
}
void thread_2_entry(ULONG thread_input)
{
ULONG received_message;
UINT status;
/* This thread retrieves messages placed on the queue by thread 1. */
while(1)
{
/* Increment the thread counter. */
thread_2_counter++;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
}
void thread_3_and_4_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 3 and thread 4. As the loop
below shows, these function compete for ownership of semaphore_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 3)
thread_3_counter++;
else
thread_4_counter++;
/* Get the semaphore with suspension. */
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the semaphore. */
tx_thread_sleep(2);
/* Release the semaphore. */
status = tx_semaphore_put(&semaphore_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_5_entry(ULONG thread_input)
{
UINT status;
ULONG actual_flags;
/* This thread simply waits for an event in a forever loop. */
while(1)
{
/* Increment the thread counter. */
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
break;
}
}
void thread_6_and_7_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 6 and thread 7. As the loop
below shows, these function compete for ownership of mutex_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 6)
thread_6_counter++;
else
thread_7_counter++;
/* Get the mutex with suspension. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Get the mutex again with suspension. This shows
that an owning thread may retrieve the mutex it
owns multiple times. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the mutex. */
tx_thread_sleep(2);
/* Release the mutex. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
ports/cortex_m85/gnu/src/tx_initialize_low_level.S → ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S
View File
ports/risc-v32/clang/CMakeLists.txt
+9 -17
View File
@@ -1,19 +1,11 @@
# RISC-V32 Clang port.
#
# Clang and GNU use identical RISC-V assembly sources; this port
# compiles from gnu/src/ so fixes and features are shared automatically.
include(${CMAKE_CURRENT_LIST_DIR}/../../../cmake/threadx_riscv_port.cmake)
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
threadx_add_riscv_port(
SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/../gnu/src
INC_DIR ${CMAKE_CURRENT_LIST_DIR}/inc
EXAMPLE_DIR ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt
)
ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh
+1 -1
View File
@@ -8,7 +8,7 @@ mkdir -p build
CC=clang-18
LD=ld.lld-18
$CC -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/entry.obj -c entry.s
$CC -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/entry.obj -c entry.S
$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -D__ASSEMBLER__ -o build/tx_initialize_low_level.obj -c tx_initialize_low_level.S
$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/board.obj -c board.c
$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/hwtimer.obj -c hwtimer.c
ports/risc-v32/clang/example_build/qemu_virt/csr.h
-343
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@@ -1,343 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_CSR_H
#define RISCV_CSR_H
// Machine Status Register, mstatus
#define MSTATUS_MPP_MASK (3L << 11) // previous mode.
#define MSTATUS_MPP_M (3L << 11)
#define MSTATUS_MPP_S (1L << 11)
#define MSTATUS_MPP_U (0L << 11)
#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
#define MSTATUS_MPIE (1L << 7)
#define MSTATUS_FS (1L << 13)
// Machine-mode Interrupt Enable
#define MIE_MTIE (1L << 7)
#define MIE_MSIE (1L << 3)
#define MIE_MEIE (1L << 11)
#define MIE_STIE (1L << 5) // supervisor timer
#define MIE_SSIE (1L << 1)
#define MIE_SEIE (1L << 9)
// Supervisor Status Register, sstatus
#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
#define SSTATUS_SPIE (1L << 5)
#define SSTATUS_UPIE (1L << 4)
// Supervisor Interrupt Enable
#define SIE_SEIE (1L << 9) // external
#define SIE_STIE (1L << 5) // timer
#define SIE_SSIE (1L << 1) // software
#ifndef __ASSEMBLER__
#include <stdint.h>
static inline uint32_t riscv_get_core()
{
uint32_t x;
asm volatile("csrr %0, mhartid" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_mstatus()
{
uint32_t x;
asm volatile("csrr %0, mstatus" : "=r" (x) );
return x;
}
static inline void riscv_writ_mstatus(uint32_t x)
{
asm volatile("csrw mstatus, %0" : : "r" (x));
}
static inline void riscv_writ_mepc(uint32_t x)
{
asm volatile("csrw mepc, %0" : : "r" (x));
}
static inline uint32_t riscv_get_sstatus()
{
uint32_t x;
asm volatile("csrr %0, sstatus" : "=r" (x) );
return x;
}
static inline void riscv_writ_sstatus(uint32_t x)
{
asm volatile("csrw sstatus, %0" : : "r" (x));
}
static inline uint32_t riscv_get_sip()
{
uint32_t x;
asm volatile("csrr %0, sip" : "=r" (x) );
return x;
}
static inline void riscv_writ_sip(uint32_t x)
{
asm volatile("csrw sip, %0" : : "r" (x));
}
static inline uint32_t riscv_get_sie()
{
uint32_t x;
asm volatile("csrr %0, sie" : "=r" (x) );
return x;
}
static inline void riscv_writ_sie(uint32_t x)
{
asm volatile("csrw sie, %0" : : "r" (x));
}
static inline uint32_t riscv_get_mie()
{
uint32_t x;
asm volatile("csrr %0, mie" : "=r" (x) );
return x;
}
static inline void riscv_writ_mie(uint32_t x)
{
asm volatile("csrw mie, %0" : : "r" (x));
}
static inline void riscv_writ_sepc(uint32_t x)
{
asm volatile("csrw sepc, %0" : : "r" (x));
}
static inline uint32_t riscv_get_sepc()
{
uint32_t x;
asm volatile("csrr %0, sepc" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_medeleg()
{
uint32_t x;
asm volatile("csrr %0, medeleg" : "=r" (x) );
return x;
}
static inline void riscv_writ_medeleg(uint32_t x)
{
asm volatile("csrw medeleg, %0" : : "r" (x));
}
static inline uint32_t riscv_get_mideleg()
{
uint32_t x;
asm volatile("csrr %0, mideleg" : "=r" (x) );
return x;
}
static inline void riscv_writ_mideleg(uint32_t x)
{
asm volatile("csrw mideleg, %0" : : "r" (x));
}
static inline void riscv_writ_stvec(uint32_t x)
{
asm volatile("csrw stvec, %0" : : "r" (x));
}
static inline uint32_t riscv_get_stvec()
{
uint32_t x;
asm volatile("csrr %0, stvec" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_stimecmp()
{
uint32_t x;
asm volatile("csrr %0, 0x14d" : "=r" (x) );
return x;
}
static inline void riscv_writ_stimecmp(uint32_t x)
{
asm volatile("csrw 0x14d, %0" : : "r" (x));
}
static inline uint32_t riscv_get_menvcfg()
{
uint32_t x;
asm volatile("csrr %0, 0x30a" : "=r" (x) );
return x;
}
static inline void riscv_writ_menvcfg(uint32_t x)
{
asm volatile("csrw 0x30a, %0" : : "r" (x));
}
static inline void riscv_writ_pmpcfg0(uint32_t x)
{
asm volatile("csrw pmpcfg0, %0" : : "r" (x));
}
static inline void riscv_writ_pmpaddr0(uint32_t x)
{
asm volatile("csrw pmpaddr0, %0" : : "r" (x));
}
static inline void riscv_writ_satp(uint32_t x)
{
asm volatile("csrw satp, %0" : : "r" (x));
}
static inline uint32_t riscv_get_satp()
{
uint32_t x;
asm volatile("csrr %0, satp" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_scause()
{
uint32_t x;
asm volatile("csrr %0, scause" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_stval()
{
uint32_t x;
asm volatile("csrr %0, stval" : "=r" (x) );
return x;
}
static inline void riscv_writ_mcounteren(uint32_t x)
{
asm volatile("csrw mcounteren, %0" : : "r" (x));
}
static inline uint32_t riscv_get_mcounteren()
{
uint32_t x;
asm volatile("csrr %0, mcounteren" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_time()
{
uint32_t x;
asm volatile("csrr %0, time" : "=r" (x) );
return x;
}
static inline void riscv_sintr_on()
{
uint32_t sstatus = riscv_get_sstatus();
sstatus |= SSTATUS_SIE;
riscv_writ_sstatus(sstatus);
}
static inline void riscv_sintr_off()
{
uint32_t sstatus = riscv_get_sstatus();
sstatus &= (~SSTATUS_SIE);
riscv_writ_sstatus(sstatus);
}
static inline int riscv_sintr_get()
{
uint32_t x = riscv_get_sstatus();
return (x & SSTATUS_SIE) != 0;
}
static inline void riscv_sintr_restore(int x)
{
if(x)
riscv_sintr_on();
else
riscv_sintr_off();
}
static inline void riscv_mintr_on()
{
uint32_t mstatus = riscv_get_mstatus();
mstatus |= MSTATUS_MIE;
riscv_writ_mstatus(mstatus);
}
static inline void riscv_mintr_off()
{
uint32_t mstatus = riscv_get_mstatus();
mstatus &= (~MSTATUS_MIE);
riscv_writ_mstatus(mstatus);
}
static inline int riscv_mintr_get()
{
uint32_t x = riscv_get_mstatus();
return (x & MSTATUS_MIE) != 0;
}
static inline void riscv_mintr_restore(int x)
{
if(x)
riscv_mintr_on();
else
riscv_mintr_off();
}
static inline uint32_t riscv_get_sp()
{
uint32_t x;
asm volatile("mv %0, sp" : "=r" (x) );
return x;
}
// read and write tp, the thread pointer, which xv6 uses to hold
// this core's hartid (core number), the index into cpus[].
static inline uint32_t riscv_get_tp()
{
uint32_t x;
asm volatile("mv %0, tp" : "=r" (x) );
return x;
}
static inline void riscv_writ_tp(uint32_t x)
{
asm volatile("mv tp, %0" : : "r" (x));
}
static inline uint32_t riscv_get_ra()
{
uint32_t x;
asm volatile("mv %0, ra" : "=r" (x) );
return x;
}
// flush the TLB.
static inline void sfence_vma()
{
// the zero, zero means flush all TLB entries.
asm volatile("sfence.vma zero, zero");
}
#endif // __ASSEMBLER__
#endif
ports/risc-v32/clang/example_build/qemu_virt/csr.h
Symlink
+1
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@@ -0,0 +1 @@
../../../../risc-v_common/inc/csr.h
ports/risc-v32/clang/example_build/qemu_virt/entry.s → ports/risc-v32/clang/example_build/qemu_virt/entry.S
View File
ports/risc-v32/clang/example_build/qemu_virt/plic.c
-72
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@@ -1,72 +0,0 @@
#include "plic.h"
#include <stddef.h>
irq_callback callbacks[MAX_CALLBACK_NUM];
void plic_irq_enable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno));
return;
}
void plic_irq_disable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno)));
return;
}
void plic_prio_set(int irqno, int prio)
{
PLIC_SET_PRIO(irqno, prio);
}
int plic_prio_get(int irqno)
{
return PLIC_GET_PRIO(irqno);
}
int plic_register_callback(int irqno, irq_callback callback)
{
if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM))
return -1;
callbacks[irqno] = callback;
return 0;
}
int plic_unregister_callback(int irqno)
{
return plic_register_callback(irqno, NULL);
}
int plic_init(void)
{
for(int i=0;i<MAX_CALLBACK_NUM;i++)
{
callbacks[i] = NULL;
}
return 0;
}
int plic_claim(void)
{
int hart = riscv_get_core();
return (*(uint32_t*)PLIC_MCLAIM(hart));
}
void plic_complete(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno;
return;
}
int plic_irq_intr(void)
{
int ret = -1;
int irqno = plic_claim();
if(callbacks[irqno] != NULL)
ret = (callbacks[irqno])(irqno);
plic_complete(irqno);
return ret;
}
ports/risc-v32/clang/example_build/qemu_virt/plic.c
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.c
ports/risc-v32/clang/example_build/qemu_virt/plic.h
-49
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@@ -1,49 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_PLIC_H
#define RISCV_PLIC_H
#include "csr.h"
#include <stdint.h>
#define PLIC 0x0c000000L
#define PLIC_PRIORITY (PLIC + 0x0)
#define PLIC_PENDING (PLIC + 0x1000)
#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100)
#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100)
#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000)
#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000)
#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4))
#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio))
#define MAX_CALLBACK_NUM 128
typedef int (*irq_callback)(int irqno);
void plic_irq_enable(int irqno);
void plic_irq_disable(int irqno);
int plic_prio_get(int irqno);
void plic_prio_set(int irqno, int prio);
int plic_register_callback(int irqno, irq_callback callback);
int plic_unregister_callback(int irqno);
int plic_init(void);
int plic_claim(void);
void plic_complete(int irqno);
int plic_irq_intr(void);
#endif
ports/risc-v32/clang/example_build/qemu_virt/plic.h
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.h
ports/risc-v32/clang/example_build/qemu_virt/trap.c
-67
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@@ -1,67 +0,0 @@
#include "csr.h"
#include <stdint.h>
#include "uart.h"
#include "hwtimer.h"
#include "plic.h"
#include <tx_port.h>
#include <tx_api.h>
#define OS_IS_INTERUPT(mcause) (mcause & 0x80000000u)
#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT))
#define OS_IS_TICK_INT(mcause) (mcause == 0x80000007u)
#define OS_IS_SOFT_INT(mcause) (mcause == 0x80000003u)
#define OS_IS_EXT_INT(mcause) (mcause == 0x8000000bu)
#define OS_IS_TRAP_USER(mcause) (mcause == 0x0000000bu)
extern void _tx_timer_interrupt(void);
extern int uart_putc(int ch);
static void print_hex(uintptr_t val)
{
char digits[] = "0123456789ABCDEF";
uart_putc('0');
uart_putc('x');
for(int i = (sizeof(uintptr_t)*2) - 1; i >= 0; i--) {
int d = (val >> (i*4)) & 0xF;
uart_putc(digits[d]);
}
uart_putc('\n');
}
void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval)
{
// uart_puts("DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/trap.c, trap_handler\n");
if(OS_IS_INTERUPT(mcause))
{
if(OS_IS_TICK_INT(mcause))
{
hwtimer_handler();
_tx_timer_interrupt();
}
else if(OS_IS_EXT_INT(mcause))
{
int ret = plic_irq_intr();
if(ret)
{
puts("[INTERRUPT]: handler irq error!");
while(1) ;
}
}
else
{
puts("[INTERRUPT]: now can't deal with the interrupt!");
while(1) ;
}
}
else
{
puts("[EXCEPTION] : Unkown Error!!");
puts("mcause:");
print_hex(mcause);
puts("mepc:");
print_hex(mepc);
puts("mtval:");
print_hex(mtval);
while(1) ;
}
}
ports/risc-v32/clang/example_build/qemu_virt/trap.c
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/trap/trap_qemu.c
ports/risc-v32/clang/example_build/qemu_virt/uart.c
-102
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@@ -1,102 +0,0 @@
#include "uart.h"
#include "csr.h"
#include "plic.h"
#include <stdint.h>
// the UART control registers are memory-mapped
// at address UART0. this macro returns the
// address of one of the registers.
#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg)))
// the UART control registers.
// some have different meanings for
// read vs write.
// see http://byterunner.com/16550.html
#define RHR 0 // receive holding register (for input bytes)
#define THR 0 // transmit holding register (for output bytes)
#define IER 1 // interrupt enable register
#define IER_RX_ENABLE (1<<0)
#define IER_TX_ENABLE (1<<1)
#define FCR 2 // FIFO control register
#define FCR_FIFO_ENABLE (1<<0)
#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs
#define ISR 2 // interrupt status register
#define LCR 3 // line control register
#define LCR_EIGHT_BITS (3<<0)
#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate
#define LSR 5 // line status register
#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR
#define LSR_TX_IDLE (1<<5) // THR can accept another character to send
#define ReadReg(reg) (*(Reg(reg)))
#define WriteReg(reg, v) (*(Reg(reg)) = (v))
int uart_init(void)
{
// disable interrupts.
WriteReg(IER, 0x00);
// special mode to set baud rate.
WriteReg(LCR, LCR_BAUD_LATCH);
// LSB for baud rate of 38.4K.
WriteReg(0, 0x03);
// MSB for baud rate of 38.4K.
WriteReg(1, 0x00);
// leave set-baud mode,
// and set word length to 8 bits, no parity.
WriteReg(LCR, LCR_EIGHT_BITS);
// reset and enable FIFOs.
WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);
// enable transmit and receive interrupts.
// WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);
//enable UART0 in PLIC
plic_irq_enable(UART0_IRQ);
//set UART0 priority in PLIC
plic_prio_set(UART0_IRQ, 1);
//register callback for UART0
//plic_register_callback(UART0_IRQ, uart_intr);
puts("[UART0] : Uart Init Done, this is Test output!");
return 0;
}
void uart_putc_nolock(int ch)
{
// wait for Transmit Holding Empty to be set in LSR.
while((ReadReg(LSR) & LSR_TX_IDLE) == 0)
;
WriteReg(THR, ch);
return;
}
int uart_putc(int ch)
{
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
uart_putc_nolock(ch);
riscv_mintr_restore(intr_enable);
return 1;
}
int uart_puts(const char* str)
{
int i;
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
for(i=0;str[i]!=0;i++)
{
uart_putc_nolock(str[i]);
}
uart_putc_nolock('\n');
riscv_mintr_restore(intr_enable);
return i;
}
ports/risc-v32/clang/example_build/qemu_virt/uart.c
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.c
ports/risc-v32/clang/example_build/qemu_virt/uart.h
-23
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@@ -1,23 +0,0 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_UART_H
#define RISCV_UART_H
#define UART0 0x10000000L
#define UART0_IRQ 10
#define puts uart_puts
int uart_init(void);
int uart_putc(int ch);
void uart_putc_nolock(int ch);
int uart_puts(const char* str);
#endif
ports/risc-v32/clang/example_build/qemu_virt/uart.h
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.h
ports/risc-v32/clang/inc/tx_port.h
+4 -224
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@@ -1,5 +1,5 @@
/***************************************************************************
* Copyright (c) 2025 Quintauris
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
@@ -24,7 +24,7 @@
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h RISC-V32/GNU */
/* tx_port.h RISC-V32/Clang */
/* 6.4.x */
/* */
/* AUTHOR */
@@ -47,228 +47,8 @@
#ifndef TX_PORT_H
#define TX_PORT_H
#ifndef __ASSEMBLER__
/* Include for memset. */
#include <string.h>
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
#endif /* TX_INCLUDE_USER_DEFINE_FILE */
#endif /* __ASSEMBLER__ */
/* Define ThreadX basic types for this port. */
#define VOID void
#ifndef __ASSEMBLER__
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
#endif /* __ASSEMBLER__ */
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
thread creation is less than this value, the thread create call will return an error. */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
#endif
/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */
#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX RISC-V port. */
#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */
#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
/* Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call. */
#define TX_INLINE_INITIALIZATION
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2
#define TX_THREAD_EXTENSION_3
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION
#define TX_SEMAPHORE_EXTENSION
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
/* Expose helper used to perform an atomic read/modify/write of mstatus.
The helper composes and returns the posture per ThreadX contract. */
#ifndef __ASSEMBLER__
UINT _tx_thread_interrupt_control(UINT new_posture);
#endif
#ifdef TX_DISABLE_INLINE
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory");
#define TX_RESTORE { \
unsigned long _temp_mstatus; \
__asm__ volatile( \
"csrc mstatus, 8\n" \
"andi %0, %1, 8\n" \
"csrs mstatus, %0" \
: "=&r" (_temp_mstatus) \
: "r" (interrupt_save) \
: "memory"); \
}
#else
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save);
#endif /* TX_DISABLE_INLINE */
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Include shared RISC-V32 port definitions common to all toolchain ports. */
#include "../../common/tx_port_riscv32_common.h"
/* Define the version ID of ThreadX. This may be utilized by the application. */
ports/risc-v32/clang/src/tx_initialize_low_level.S
-112
View File
@@ -1,112 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
/**************************************************************************/
/**************************************************************************/
.section .data
.global __tx_free_memory_start
__tx_free_memory_start:
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/**************************************************************************/
/* VOID _tx_initialize_low_level(VOID)
{ */
// .global _tx_initialize_low_level
.weak _tx_initialize_low_level
_tx_initialize_low_level:
/* Save the system stack pointer. */
/* _tx_thread_system_stack_ptr = sp; */
la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr
sw sp, 0(t0) // Save system stack pointer
/* Pickup first free address. */
/* _tx_initialize_unused_memory(__tx_free_memory_start); */
la t0, __tx_free_memory_start // Pickup first free address
la t1, _tx_initialize_unused_memory // Pickup address of unused memory
sw t0, 0(t1) // Save unused memory address
/* Initialize floating point control/status register if floating point is enabled. */
#ifdef __riscv_flen
li t0, 0
csrw fcsr, t0 // Clear FP control/status register
#endif
ret
/* Timer Interrupt Handler Note:
Platform-specific implementations must provide their own timer ISR.
The timer interrupt handler should follow this execution flow:
1. Disable interrupts (if not done by hardware exception entry)
2. Allocate interrupt stack frame (65*4 bytes with FP, 32*4 bytes without)
3. Save RA (x1) on the stack at offset 28*4
4. Call _tx_thread_context_save to save thread context
5. Call _tx_timer_interrupt to process the timer tick
6. Call _tx_thread_context_restore to resume execution (does not return)
Example (for CLINT timer):
_tx_timer_interrupt_handler:
addi sp, sp, -32*4
sw ra, 28*4(sp)
call _tx_thread_context_save
call _tx_timer_interrupt
j _tx_thread_context_restore
The port assumes Machine mode (M-mode) execution.
For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus.
See the RISC-V Privileged Specification for more details. */
ports/risc-v32/clang/src/tx_thread_context_restore.S
-410
View File
@@ -1,410 +0,0 @@
/***************************************************************************
* Copyright (c) 2025 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function restores the interrupt context if it is processing a */
/* nested interrupt. If not, it returns to the interrupt thread if no */
/* preemption is necessary. Otherwise, if preemption is necessary or */
/* if no thread was running, the function returns to the scheduler. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling routine */
/* */
/* CALLED BY */
/* */
/* ISRs Interrupt Service Routines */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_restore(VOID)
{ */
.global _tx_thread_context_restore
_tx_thread_context_restore:
/* Lockout interrupts. */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_isr_exit // Call the ISR execution exit function
#endif
/* Determine if interrupts are nested. */
/* if (--_tx_thread_system_state)
{ */
la t0, _tx_thread_system_state // Pickup addr of nested interrupt count
lw t1, 0(t0) // Pickup nested interrupt count
addi t1, t1, -1 // Decrement the nested interrupt counter
sw t1, 0(t0) // Store new nested count
beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore
/* Interrupts are nested. */
/* Just recover the saved registers and return to the point of
interrupt. */
/* Recover floating point registers. */
#if defined(__riscv_float_abi_single)
flw f0, 31*4(sp) // Recover ft0
flw f1, 32*4(sp) // Recover ft1
flw f2, 33*4(sp) // Recover ft2
flw f3, 34*4(sp) // Recover ft3
flw f4, 35*4(sp) // Recover ft4
flw f5, 36*4(sp) // Recover ft5
flw f6, 37*4(sp) // Recover ft6
flw f7, 38*4(sp) // Recover ft7
flw f10, 41*4(sp) // Recover fa0
flw f11, 42*4(sp) // Recover fa1
flw f12, 43*4(sp) // Recover fa2
flw f13, 44*4(sp) // Recover fa3
flw f14, 45*4(sp) // Recover fa4
flw f15, 46*4(sp) // Recover fa5
flw f16, 47*4(sp) // Recover fa6
flw f17, 48*4(sp) // Recover fa7
flw f28, 59*4(sp) // Recover ft8
flw f29, 60*4(sp) // Recover ft9
flw f30, 61*4(sp) // Recover ft10
flw f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f0, 31*4(sp) // Recover ft0
fld f1, 32*4(sp) // Recover ft1
fld f2, 33*4(sp) // Recover ft2
fld f3, 34*4(sp) // Recover ft3
fld f4, 35*4(sp) // Recover ft4
fld f5, 36*4(sp) // Recover ft5
fld f6, 37*4(sp) // Recover ft6
fld f7, 38*4(sp) // Recover ft7
fld f10, 41*4(sp) // Recover fa0
fld f11, 42*4(sp) // Recover fa1
fld f12, 43*4(sp) // Recover fa2
fld f13, 44*4(sp) // Recover fa3
fld f14, 45*4(sp) // Recover fa4
fld f15, 46*4(sp) // Recover fa5
fld f16, 47*4(sp) // Recover fa6
fld f17, 48*4(sp) // Recover fa7
fld f28, 59*4(sp) // Recover ft8
fld f29, 60*4(sp) // Recover ft9
fld f30, 61*4(sp) // Recover ft10
fld f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
/* Recover standard registers. */
/* Restore registers,
Skip global pointer because that does not change.
Also skip the saved registers since they have been restored by any function we called,
except s0 since we use it ourselves. */
lw t0, 30*4(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
/* Compose mstatus via read/modify/write to avoid clobbering unrelated bits.
Set MPIE and restore MPP to Machine, preserve other fields. */
csrr t1, mstatus
/* Clear MPP/MPIE/MIE bits in t1 then set desired values. */
li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08)
li t3, 0x1800 // Set MPP to Machine mode (bits 12:11)
/* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit,
preserve everything except the bits we will modify. */
li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE
and t1, t1, t4
or t1, t1, t3
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state
or t1, t1, t0
#endif
csrw mstatus, t1 // Update mstatus safely
lw ra, 28*4(sp) // Recover return address
lw t0, 19*4(sp) // Recover t0
lw t1, 18*4(sp) // Recover t1
lw t2, 17*4(sp) // Recover t2
lw s0, 12*4(sp) // Recover s0
lw a0, 27*4(sp) // Recover a0
lw a1, 26*4(sp) // Recover a1
lw a2, 25*4(sp) // Recover a2
lw a3, 24*4(sp) // Recover a3
lw a4, 23*4(sp) // Recover a4
lw a5, 22*4(sp) // Recover a5
lw a6, 21*4(sp) // Recover a6
lw a7, 20*4(sp) // Recover a7
lw t3, 16*4(sp) // Recover t3
lw t4, 15*4(sp) // Recover t4
lw t5, 14*4(sp) // Recover t5
lw t6, 13*4(sp) // Recover t6
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 32*4 // Recover stack frame - without floating point enabled
#endif
mret // Return to point of interrupt
/* } */
_tx_thread_not_nested_restore:
/* Determine if a thread was interrupted and no preemption is required. */
/* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
|| (_tx_thread_preempt_disable))
{ */
la t0, _tx_thread_current_ptr // Pickup current thread pointer address
lw t1, 0(t0) // Pickup current thread pointer
beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore
la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address
lw t2, 0(t0) // Pickup preempt disable flag (UINT)
bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread
la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address
lw t2, 0(t0) // Pickup thread execute pointer
bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt
_tx_thread_no_preempt_restore:
/* Restore interrupted thread or ISR. */
/* Pickup the saved stack pointer. */
/* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */
lw sp, 8(t1) // Switch back to thread's stack
/* Recover floating point registers. */
#if defined(__riscv_float_abi_single)
flw f0, 31*4(sp) // Recover ft0
flw f1, 32*4(sp) // Recover ft1
flw f2, 33*4(sp) // Recover ft2
flw f3, 34*4(sp) // Recover ft3
flw f4, 35*4(sp) // Recover ft4
flw f5, 36*4(sp) // Recover ft5
flw f6, 37*4(sp) // Recover ft6
flw f7, 38*4(sp) // Recover ft7
flw f10, 41*4(sp) // Recover fa0
flw f11, 42*4(sp) // Recover fa1
flw f12, 43*4(sp) // Recover fa2
flw f13, 44*4(sp) // Recover fa3
flw f14, 45*4(sp) // Recover fa4
flw f15, 46*4(sp) // Recover fa5
flw f16, 47*4(sp) // Recover fa6
flw f17, 48*4(sp) // Recover fa7
flw f28, 59*4(sp) // Recover ft8
flw f29, 60*4(sp) // Recover ft9
flw f30, 61*4(sp) // Recover ft10
flw f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f0, 31*4(sp) // Recover ft0
fld f1, 32*4(sp) // Recover ft1
fld f2, 33*4(sp) // Recover ft2
fld f3, 34*4(sp) // Recover ft3
fld f4, 35*4(sp) // Recover ft4
fld f5, 36*4(sp) // Recover ft5
fld f6, 37*4(sp) // Recover ft6
fld f7, 38*4(sp) // Recover ft7
fld f10, 41*4(sp) // Recover fa0
fld f11, 42*4(sp) // Recover fa1
fld f12, 43*4(sp) // Recover fa2
fld f13, 44*4(sp) // Recover fa3
fld f14, 45*4(sp) // Recover fa4
fld f15, 46*4(sp) // Recover fa5
fld f16, 47*4(sp) // Recover fa6
fld f17, 48*4(sp) // Recover fa7
fld f28, 59*4(sp) // Recover ft8
fld f29, 60*4(sp) // Recover ft9
fld f30, 61*4(sp) // Recover ft10
fld f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
/* Recover the saved context and return to the point of interrupt. */
/* Recover standard registers. */
/* Restore registers,
Skip global pointer because that does not change */
lw t0, 30*4(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
/* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */
csrr t1, mstatus
li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08)
li t3, 0x1800 // Set MPP to Machine mode
li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE
and t1, t1, t4
or t1, t1, t3
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t0, 0x2000 // Set FS bits for FP state
or t1, t1, t0
#endif
csrw mstatus, t1 // Update mstatus safely
lw ra, 28*4(sp) // Recover return address
lw t0, 19*4(sp) // Recover t0
lw t1, 18*4(sp) // Recover t1
lw t2, 17*4(sp) // Recover t2
lw s0, 12*4(sp) // Recover s0
lw a0, 27*4(sp) // Recover a0
lw a1, 26*4(sp) // Recover a1
lw a2, 25*4(sp) // Recover a2
lw a3, 24*4(sp) // Recover a3
lw a4, 23*4(sp) // Recover a4
lw a5, 22*4(sp) // Recover a5
lw a6, 21*4(sp) // Recover a6
lw a7, 20*4(sp) // Recover a7
lw t3, 16*4(sp) // Recover t3
lw t4, 15*4(sp) // Recover t4
lw t5, 14*4(sp) // Recover t5
lw t6, 13*4(sp) // Recover t6
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 32*4 // Recover stack frame - without floating point enabled
#endif
mret // Return to point of interrupt
/* }
else
{ */
_tx_thread_preempt_restore:
/* Instead of directly activating the thread again, ensure we save the
entire stack frame by saving the remaining registers. */
lw t0, 8(t1) // Pickup thread's stack pointer
ori t3, zero, 1 // Build interrupt stack type
sw t3, 0(t0) // Store stack type
/* Store floating point preserved registers. */
#ifdef __riscv_float_abi_single
fsw f8, 39*4(t0) // Store fs0
fsw f9, 40*4(t0) // Store fs1
fsw f18, 49*4(t0) // Store fs2
fsw f19, 50*4(t0) // Store fs3
fsw f20, 51*4(t0) // Store fs4
fsw f21, 52*4(t0) // Store fs5
fsw f22, 53*4(t0) // Store fs6
fsw f23, 54*4(t0) // Store fs7
fsw f24, 55*4(t0) // Store fs8
fsw f25, 56*4(t0) // Store fs9
fsw f26, 57*4(t0) // Store fs10
fsw f27, 58*4(t0) // Store fs11
#elif defined(__riscv_float_abi_double)
fsd f8, 39*4(t0) // Store fs0
fsd f9, 40*4(t0) // Store fs1
fsd f18, 49*4(t0) // Store fs2
fsd f19, 50*4(t0) // Store fs3
fsd f20, 51*4(t0) // Store fs4
fsd f21, 52*4(t0) // Store fs5
fsd f22, 53*4(t0) // Store fs6
fsd f23, 54*4(t0) // Store fs7
fsd f24, 55*4(t0) // Store fs8
fsd f25, 56*4(t0) // Store fs9
fsd f26, 57*4(t0) // Store fs10
fsd f27, 58*4(t0) // Store fs11
#endif
/* Store standard preserved registers. */
sw x9, 11*4(t0) // Store s1
sw x18, 10*4(t0) // Store s2
sw x19, 9*4(t0) // Store s3
sw x20, 8*4(t0) // Store s4
sw x21, 7*4(t0) // Store s5
sw x22, 6*4(t0) // Store s6
sw x23, 5*4(t0) // Store s7
sw x24, 4*4(t0) // Store s8
sw x25, 3*4(t0) // Store s9
sw x26, 2*4(t0) // Store s10
sw x27, 1*4(t0) // Store s11
// Note: s0 is already stored!
/* Save the remaining time-slice and disable it. */
/* if (_tx_timer_time_slice)
{ */
la t0, _tx_timer_time_slice // Pickup time slice variable address
lw t2, 0(t0) // Pickup time slice
beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice
_tx_timer_time_slice = 0; */
sw t2, 24(t1) // Save current time slice
sw x0, 0(t0) // Clear global time slice
/* } */
_tx_thread_dont_save_ts:
/* Clear the current task pointer. */
/* _tx_thread_current_ptr = TX_NULL; */
/* Return to the scheduler. */
/* _tx_thread_schedule(); */
la t0, _tx_thread_current_ptr // Pickup current thread pointer address
sw x0, 0(t0) // Clear current thread pointer
/* } */
_tx_thread_idle_system_restore:
/* Just return back to the scheduler! */
j _tx_thread_schedule // Return to scheduler
/* } */
ports/risc-v32/clang/src/tx_thread_context_save.S
-271
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@@ -1,271 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function saves the context of an executing thread in the */
/* beginning of interrupt processing. The function also ensures that */
/* the system stack is used upon return to the calling ISR. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ISRs */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_save(VOID)
{ */
.global _tx_thread_context_save
_tx_thread_context_save:
/* Upon entry to this routine, RA/x1 has been saved on the stack
and the stack has been already allocated for the entire context:
addi sp, sp, -32*4 (or -65*4)
sw ra, 28*4(sp)
*/
sw t0, 19*4(sp) // Store t0
sw t1, 18*4(sp) // Store t1
/* Check for a nested interrupt. */
/* if (_tx_thread_system_state++)
{ */
la t0, _tx_thread_system_state // Pickup addr of system state var
lw t1, 0(t0) // Pickup system state
addi t1, t1, 1 // Increment system state
sw t1, 0(t0) // Store system state
li t0, 1
bgt t1, t0, _tx_thread_nested_save // If it's more than 1, nested interrupt
/* First level interrupt, save the rest of the scratch registers and
check for a thread to preempt. */
sw t2, 17*4(sp) // Store t2
sw s0, 12*4(sp) // Store s0
sw a0, 27*4(sp) // Store a0
sw a1, 26*4(sp) // Store a1
sw a2, 25*4(sp) // Store a2
sw a3, 24*4(sp) // Store a3
sw a4, 23*4(sp) // Store a4
sw a5, 22*4(sp) // Store a5
sw a6, 21*4(sp) // Store a6
sw a7, 20*4(sp) // Store a7
sw t3, 16*4(sp) // Store t3
sw t4, 15*4(sp) // Store t4
sw t5, 14*4(sp) // Store t5
sw t6, 13*4(sp) // Store t6
/* Save floating point registers. */
#if defined(__riscv_float_abi_single)
fsw f0, 31*4(sp) // Store ft0
fsw f1, 32*4(sp) // Store ft1
fsw f2, 33*4(sp) // Store ft2
fsw f3, 34*4(sp) // Store ft3
fsw f4, 35*4(sp) // Store ft4
fsw f5, 36*4(sp) // Store ft5
fsw f6, 37*4(sp) // Store ft6
fsw f7, 38*4(sp) // Store ft7
fsw f10, 41*4(sp) // Store fa0
fsw f11, 42*4(sp) // Store fa1
fsw f12, 43*4(sp) // Store fa2
fsw f13, 44*4(sp) // Store fa3
fsw f14, 45*4(sp) // Store fa4
fsw f15, 46*4(sp) // Store fa5
fsw f16, 47*4(sp) // Store fa6
fsw f17, 48*4(sp) // Store fa7
fsw f28, 59*4(sp) // Store ft8
fsw f29, 60*4(sp) // Store ft9
fsw f30, 61*4(sp) // Store ft10
fsw f31, 62*4(sp) // Store ft11
csrr t0, fcsr
sw t0, 63*4(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
fsd f0, 31*4(sp) // Store ft0
fsd f1, 32*4(sp) // Store ft1
fsd f2, 33*4(sp) // Store ft2
fsd f3, 34*4(sp) // Store ft3
fsd f4, 35*4(sp) // Store ft4
fsd f5, 36*4(sp) // Store ft5
fsd f6, 37*4(sp) // Store ft6
fsd f7, 38*4(sp) // Store ft7
fsd f10, 41*4(sp) // Store fa0
fsd f11, 42*4(sp) // Store fa1
fsd f12, 43*4(sp) // Store fa2
fsd f13, 44*4(sp) // Store fa3
fsd f14, 45*4(sp) // Store fa4
fsd f15, 46*4(sp) // Store fa5
fsd f16, 47*4(sp) // Store fa6
fsd f17, 48*4(sp) // Store fa7
fsd f28, 59*4(sp) // Store ft8
fsd f29, 60*4(sp) // Store ft9
fsd f30, 61*4(sp) // Store ft10
fsd f31, 62*4(sp) // Store ft11
csrr t0, fcsr
sw t0, 63*4(sp) // Store fcsr
#endif
csrr t0, mepc
sw t0, 30*4(sp) // Save it on the stack
/* Save mstatus. */
csrr t0, mstatus
sw t0, 29*4(sp)
la t1, _tx_thread_current_ptr // Pickup address of current thread ptr
lw t2, 0(t1) // Pickup current thread pointer
beqz t2, _tx_thread_idle_system_save // If NULL, idle system was interrupted
/* Save the current thread's stack pointer and switch to the system stack. */
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
sp = _tx_thread_system_stack_ptr; */
sw sp, 8(t2) // Save stack pointer
la t0, _tx_thread_system_stack_ptr
lw sp, 0(t0) // Switch to system stack
/* Call the ISR execution exit function if enabled. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_isr_enter // Call the ISR execution enter function
#endif
ret // Return to ISR
_tx_thread_nested_save:
/* Nested interrupt! Just save the scratch registers and return to the ISR. */
sw t2, 17*4(sp) // Store t2
sw s0, 12*4(sp) // Store s0
sw a0, 27*4(sp) // Store a0
sw a1, 26*4(sp) // Store a1
sw a2, 25*4(sp) // Store a2
sw a3, 24*4(sp) // Store a3
sw a4, 23*4(sp) // Store a4
sw a5, 22*4(sp) // Store a5
sw a6, 21*4(sp) // Store a6
sw a7, 20*4(sp) // Store a7
sw t3, 16*4(sp) // Store t3
sw t4, 15*4(sp) // Store t4
sw t5, 14*4(sp) // Store t5
sw t6, 13*4(sp) // Store t6
/* Save floating point registers. */
#if defined(__riscv_float_abi_single)
fsw f0, 31*4(sp) // Store ft0
fsw f1, 32*4(sp) // Store ft1
fsw f2, 33*4(sp) // Store ft2
fsw f3, 34*4(sp) // Store ft3
fsw f4, 35*4(sp) // Store ft4
fsw f5, 36*4(sp) // Store ft5
fsw f6, 37*4(sp) // Store ft6
fsw f7, 38*4(sp) // Store ft7
fsw f10, 41*4(sp) // Store fa0
fsw f11, 42*4(sp) // Store fa1
fsw f12, 43*4(sp) // Store fa2
fsw f13, 44*4(sp) // Store fa3
fsw f14, 45*4(sp) // Store fa4
fsw f15, 46*4(sp) // Store fa5
fsw f16, 47*4(sp) // Store fa6
fsw f17, 48*4(sp) // Store fa7
fsw f28, 59*4(sp) // Store ft8
fsw f29, 60*4(sp) // Store ft9
fsw f30, 61*4(sp) // Store ft10
fsw f31, 62*4(sp) // Store ft11
csrr t0, fcsr
sw t0, 63*4(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
fsd f0, 31*4(sp) // Store ft0
fsd f1, 32*4(sp) // Store ft1
fsd f2, 33*4(sp) // Store ft2
fsd f3, 34*4(sp) // Store ft3
fsd f4, 35*4(sp) // Store ft4
fsd f5, 36*4(sp) // Store ft5
fsd f6, 37*4(sp) // Store ft6
fsd f7, 38*4(sp) // Store ft7
fsd f10, 41*4(sp) // Store fa0
fsd f11, 42*4(sp) // Store fa1
fsd f12, 43*4(sp) // Store fa2
fsd f13, 44*4(sp) // Store fa3
fsd f14, 45*4(sp) // Store fa4
fsd f15, 46*4(sp) // Store fa5
fsd f16, 47*4(sp) // Store fa6
fsd f17, 48*4(sp) // Store fa7
fsd f28, 59*4(sp) // Store ft8
fsd f29, 60*4(sp) // Store ft9
fsd f30, 61*4(sp) // Store ft10
fsd f31, 62*4(sp) // Store ft11
csrr t0, fcsr
sw t0, 63*4(sp) // Store fcsr
#endif
csrr t0, mepc
sw t0, 30*4(sp) // Save it on stack
csrr t0, mstatus
sw t0, 29*4(sp)
/* Call the ISR execution exit function if enabled. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_isr_enter // Call the ISR execution enter function
#endif
ret // Return to ISR
_tx_thread_idle_system_save:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_isr_enter // Call the ISR execution enter function
#endif
/* Interrupt occurred in the scheduling loop. */
/* }
} */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 32*4 // Recover the reserved stack space
#endif
ret // Return to calling ISR
ports/risc-v32/clang/src/tx_thread_interrupt_control.S
-88
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@@ -1,88 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for changing the interrupt lockout */
/* posture of the system. */
/* */
/* INPUT */
/* */
/* new_posture New interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_control(UINT new_posture)
{ */
.global _tx_thread_interrupt_control
_tx_thread_interrupt_control:
/* Pickup current interrupt posture. */
csrr a1, mstatus // Pickup mstatus
andi a1, a1, 0x08 // Mask out all but MIE
/* Check for the new posture. */
beqz a0, _tx_thread_interrupt_disable // If 0, disable interrupts
/* Enable interrupts. */
csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3)
j _tx_thread_interrupt_control_exit // Return to caller
_tx_thread_interrupt_disable:
/* Disable interrupts. */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
_tx_thread_interrupt_control_exit:
/* Return the old interrupt posture. */
mv a0, a1 // Setup return value
ret // Return to caller
/* } */
ports/risc-v32/clang/src/tx_thread_schedule.S
-318
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@@ -1,318 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function waits for a thread control block pointer to appear in */
/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
/* in the variable, the corresponding thread is resumed. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* _tx_thread_system_return Return to system from thread */
/* _tx_thread_context_restore Restore thread's context */
/* */
/**************************************************************************/
/* VOID _tx_thread_schedule(VOID)
{ */
.global _tx_thread_schedule
_tx_thread_schedule:
/* Enable interrupts. */
csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3)
/* Wait for a thread to execute. */
/* do
{ */
_tx_thread_schedule_loop:
la t0, _tx_thread_execute_ptr // Pickup address of execute ptr
lw t1, 0(t0) // Pickup execute pointer
bnez t1, _tx_thread_ready_to_run // If non-NULL, a thread is ready to run
#ifndef TX_NO_WFI
wfi // Wait for interrupt
#endif
j _tx_thread_schedule_loop // Check again
/* }
while (_tx_thread_execute_ptr == TX_NULL); */
_tx_thread_ready_to_run:
/* At this point, t1 contains the pointer to the thread to execute.
Lockout interrupts. */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
/* Check _tx_thread_execute_ptr again, in case an interrupt occurred
between the check and the disable. */
lw t1, 0(t0) // Pickup execute pointer
beqz t1, _tx_thread_schedule_loop // If NULL, go back to wait loop
/* Yes! We have a thread to execute. */
/* _tx_thread_current_ptr = _tx_thread_execute_ptr; */
la t0, _tx_thread_current_ptr // Pickup address of current thread
sw t1, 0(t0) // Setup current thread pointer
/* Increment the run count for this thread. */
/* _tx_thread_current_ptr -> tx_thread_run_count++; */
lw t2, 4(t1) // Pickup run count
addi t2, t2, 1 // Increment run count
sw t2, 4(t1) // Store run count
/* Setup time-slice values. */
/* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */
lw t2, 24(t1) // Pickup thread time-slice
la t3, _tx_timer_time_slice // Pickup address of time-slice
sw t2, 0(t3) // Setup time-slice
/* Call the thread execution enter function if enabled. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_thread_enter // Call the thread execution enter function
#endif
/* Switch to the thread's stack. */
/* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */
lw sp, 8(t1) // Switch to thread stack
/* Determine the type of stack frame. */
/* if (*sp)
{ */
lw t0, 0(sp) // Pickup stack type
beqz t0, _tx_thread_solicited_return // If 0, solicited return
/* Recover floating point registers. */
#if defined(__riscv_float_abi_single)
flw f0, 31*4(sp) // Recover ft0
flw f1, 32*4(sp) // Recover ft1
flw f2, 33*4(sp) // Recover ft2
flw f3, 34*4(sp) // Recover ft3
flw f4, 35*4(sp) // Recover ft4
flw f5, 36*4(sp) // Recover ft5
flw f6, 37*4(sp) // Recover ft6
flw f7, 38*4(sp) // Recover ft7
flw f8, 39*4(sp) // Recover fs0
flw f9, 40*4(sp) // Recover fs1
flw f10, 41*4(sp) // Recover fa0
flw f11, 42*4(sp) // Recover fa1
flw f12, 43*4(sp) // Recover fa2
flw f13, 44*4(sp) // Recover fa3
flw f14, 45*4(sp) // Recover fa4
flw f15, 46*4(sp) // Recover fa5
flw f16, 47*4(sp) // Recover fa6
flw f17, 48*4(sp) // Recover fa7
flw f18, 49*4(sp) // Recover fs2
flw f19, 50*4(sp) // Recover fs3
flw f20, 51*4(sp) // Recover fs4
flw f21, 52*4(sp) // Recover fs5
flw f22, 53*4(sp) // Recover fs6
flw f23, 54*4(sp) // Recover fs7
flw f24, 55*4(sp) // Recover fs8
flw f25, 56*4(sp) // Recover fs9
flw f26, 57*4(sp) // Recover fs10
flw f27, 58*4(sp) // Recover fs11
flw f28, 59*4(sp) // Recover ft8
flw f29, 60*4(sp) // Recover ft9
flw f30, 61*4(sp) // Recover ft10
flw f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f0, 31*4(sp) // Recover ft0
fld f1, 32*4(sp) // Recover ft1
fld f2, 33*4(sp) // Recover ft2
fld f3, 34*4(sp) // Recover ft3
fld f4, 35*4(sp) // Recover ft4
fld f5, 36*4(sp) // Recover ft5
fld f6, 37*4(sp) // Recover ft6
fld f7, 38*4(sp) // Recover ft7
fld f8, 39*4(sp) // Recover fs0
fld f9, 40*4(sp) // Recover fs1
fld f10, 41*4(sp) // Recover fa0
fld f11, 42*4(sp) // Recover fa1
fld f12, 43*4(sp) // Recover fa2
fld f13, 44*4(sp) // Recover fa3
fld f14, 45*4(sp) // Recover fa4
fld f15, 46*4(sp) // Recover fa5
fld f16, 47*4(sp) // Recover fa6
fld f17, 48*4(sp) // Recover fa7
fld f18, 49*4(sp) // Recover fs2
fld f19, 50*4(sp) // Recover fs3
fld f20, 51*4(sp) // Recover fs4
fld f21, 52*4(sp) // Recover fs5
fld f22, 53*4(sp) // Recover fs6
fld f23, 54*4(sp) // Recover fs7
fld f24, 55*4(sp) // Recover fs8
fld f25, 56*4(sp) // Recover fs9
fld f26, 57*4(sp) // Recover fs10
fld f27, 58*4(sp) // Recover fs11
fld f28, 59*4(sp) // Recover ft8
fld f29, 60*4(sp) // Recover ft9
fld f30, 61*4(sp) // Recover ft10
fld f31, 62*4(sp) // Recover ft11
lw t0, 63*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
/* Recover standard registers. */
lw t0, 30*4(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80)
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t1, 0x2000 // Set FS bits for FP state
or t0, t0, t1
#endif
csrw mstatus, t0 // Set mstatus
lw ra, 28*4(sp) // Recover return address
lw t0, 19*4(sp) // Recover t0
lw t1, 18*4(sp) // Recover t1
lw t2, 17*4(sp) // Recover t2
lw s0, 12*4(sp) // Recover s0
lw x9, 11*4(sp) // Recover s1
lw a0, 27*4(sp) // Recover a0
lw a1, 26*4(sp) // Recover a1
lw a2, 25*4(sp) // Recover a2
lw a3, 24*4(sp) // Recover a3
lw a4, 23*4(sp) // Recover a4
lw a5, 22*4(sp) // Recover a5
lw a6, 21*4(sp) // Recover a6
lw a7, 20*4(sp) // Recover a7
lw t3, 16*4(sp) // Recover t3
lw t4, 15*4(sp) // Recover t4
lw t5, 14*4(sp) // Recover t5
lw t6, 13*4(sp) // Recover t6
lw x18, 10*4(sp) // Recover s2
lw x19, 9*4(sp) // Recover s3
lw x20, 8*4(sp) // Recover s4
lw x21, 7*4(sp) // Recover s5
lw x22, 6*4(sp) // Recover s6
lw x23, 5*4(sp) // Recover s7
lw x24, 4*4(sp) // Recover s8
lw x25, 3*4(sp) // Recover s9
lw x26, 2*4(sp) // Recover s10
lw x27, 1*4(sp) // Recover s11
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*4 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 32*4 // Recover stack frame - without floating point enabled
#endif
mret // Return to thread
_tx_thread_solicited_return:
/* Recover floating point registers. */
#if defined(__riscv_float_abi_single)
flw f8, 15*4(sp) // Recover fs0
flw f9, 16*4(sp) // Recover fs1
flw f18, 17*4(sp) // Recover fs2
flw f19, 18*4(sp) // Recover fs3
flw f20, 19*4(sp) // Recover fs4
flw f21, 20*4(sp) // Recover fs5
flw f22, 21*4(sp) // Recover fs6
flw f23, 22*4(sp) // Recover fs7
flw f24, 23*4(sp) // Recover fs8
flw f25, 24*4(sp) // Recover fs9
flw f26, 25*4(sp) // Recover fs10
flw f27, 26*4(sp) // Recover fs11
lw t0, 27*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f8, 15*4(sp) // Recover fs0
fld f9, 16*4(sp) // Recover fs1
fld f18, 17*4(sp) // Recover fs2
fld f19, 18*4(sp) // Recover fs3
fld f20, 19*4(sp) // Recover fs4
fld f21, 20*4(sp) // Recover fs5
fld f22, 21*4(sp) // Recover fs6
fld f23, 22*4(sp) // Recover fs7
fld f24, 23*4(sp) // Recover fs8
fld f25, 24*4(sp) // Recover fs9
fld f26, 25*4(sp) // Recover fs10
fld f27, 26*4(sp) // Recover fs11
lw t0, 27*4(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
/* Recover standard registers. */
lw t0, 14*4(sp) // Recover mstatus
csrw mstatus, t0 // Restore mstatus
lw ra, 13*4(sp) // Recover return address
lw s0, 12*4(sp) // Recover s0
lw s1, 11*4(sp) // Recover s1
lw x18, 10*4(sp) // Recover s2
lw x19, 9*4(sp) // Recover s3
lw x20, 8*4(sp) // Recover s4
lw x21, 7*4(sp) // Recover s5
lw x22, 6*4(sp) // Recover s6
lw x23, 5*4(sp) // Recover s7
lw x24, 4*4(sp) // Recover s8
lw x25, 3*4(sp) // Recover s9
lw x26, 2*4(sp) // Recover s10
lw x27, 1*4(sp) // Recover s11
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 29*4 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 16*4 // Recover stack frame - without floating point enabled
#endif
ret // Return to thread
/* } */
ports/risc-v32/clang/src/tx_thread_stack_build.S
-221
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@@ -1,221 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function builds a stack frame on the supplied thread's stack. */
/* The stack frame results in a fake interrupt return to the supplied */
/* function pointer. */
/* */
/* INPUT */
/* */
/* thread_ptr Pointer to thread control blk */
/* function_ptr Pointer to return function */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_thread_create Create thread service */
/* */
/**************************************************************************/
/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
{ */
.global _tx_thread_stack_build
_tx_thread_stack_build:
/* Build a fake interrupt frame. The form of the fake interrupt stack
on the RISC-V should look like the following after it is built:
Reg Index
Stack Top: 1 0 Interrupt stack frame type
x27 1 Initial s11
x26 2 Initial s10
x25 3 Initial s9
x24 4 Initial s8
x23 5 Initial s7
x22 6 Initial s6
x21 7 Initial s5
x20 8 Initial s4
x19 9 Initial s3
x18 10 Initial s2
x9 11 Initial s1
x8 12 Initial s0
x31 13 Initial t6
x30 14 Initial t5
x29 15 Initial t4
x28 16 Initial t3
x7 17 Initial t2
x6 18 Initial t1
x5 19 Initial t0
x17 20 Initial a7
x16 21 Initial a6
x15 22 Initial a5
x14 23 Initial a4
x13 24 Initial a3
x12 25 Initial a2
x11 26 Initial a1
x10 27 Initial a0
x1 28 Initial ra
-- 29 reserved
mepc 30 Initial mepc
If floating point support:
f0 31 Initial ft0
f1 32 Initial ft1
f2 33 Initial ft2
f3 34 Initial ft3
f4 35 Initial ft4
f5 36 Initial ft5
f6 37 Initial ft6
f7 38 Initial ft7
f8 39 Initial fs0
f9 40 Initial fs1
f10 41 Initial fa0
f11 42 Initial fa1
f12 43 Initial fa2
f13 44 Initial fa3
f14 45 Initial fa4
f15 46 Initial fa5
f16 47 Initial fa6
f17 48 Initial fa7
f18 49 Initial fs2
f19 50 Initial fs3
f20 51 Initial fs4
f21 52 Initial fs5
f22 53 Initial fs6
f23 54 Initial fs7
f24 55 Initial fs8
f25 56 Initial fs9
f26 57 Initial fs10
f27 58 Initial fs11
f28 59 Initial ft8
f29 60 Initial ft9
f30 61 Initial ft10
f31 62 Initial ft11
fscr 63 Initial fscr
Stack Bottom: (higher memory address) */
lw t0, 16(a0) // Pickup end of stack area
li t1, ~15 // Build 16-byte alignment mask
and t0, t0, t1 // Make sure 16-byte alignment
/* Actually build the stack frame. */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t0, t0, -65*4
#else
addi t0, t0, -32*4 // Allocate space for the stack frame
#endif
li t1, 1 // Build stack type
sw t1, 0*4(t0) // Place stack type on the top
sw zero, 1*4(t0) // Initial s11
sw zero, 2*4(t0) // Initial s10
sw zero, 3*4(t0) // Initial s9
sw zero, 4*4(t0) // Initial s8
sw zero, 5*4(t0) // Initial s7
sw zero, 6*4(t0) // Initial s6
sw zero, 7*4(t0) // Initial s5
sw zero, 8*4(t0) // Initial s4
sw zero, 9*4(t0) // Initial s3
sw zero, 10*4(t0) // Initial s2
sw zero, 11*4(t0) // Initial s1
sw zero, 12*4(t0) // Initial s0
sw zero, 13*4(t0) // Initial t6
sw zero, 14*4(t0) // Initial t5
sw zero, 15*4(t0) // Initial t4
sw zero, 16*4(t0) // Initial t3
sw zero, 17*4(t0) // Initial t2
sw zero, 18*4(t0) // Initial t1
sw zero, 19*4(t0) // Initial t0
sw zero, 20*4(t0) // Initial a7
sw zero, 21*4(t0) // Initial a6
sw zero, 22*4(t0) // Initial a5
sw zero, 23*4(t0) // Initial a4
sw zero, 24*4(t0) // Initial a3
sw zero, 25*4(t0) // Initial a2
sw zero, 26*4(t0) // Initial a1
sw zero, 27*4(t0) // Initial a0
sw zero, 28*4(t0) // Initial ra
sw a1, 30*4(t0) // Initial mepc (thread entry point)
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
sw zero, 31*4(t0) // Initial ft0
sw zero, 32*4(t0) // Initial ft1
sw zero, 33*4(t0) // Initial ft2
sw zero, 34*4(t0) // Initial ft3
sw zero, 35*4(t0) // Initial ft4
sw zero, 36*4(t0) // Initial ft5
sw zero, 37*4(t0) // Initial ft6
sw zero, 38*4(t0) // Initial ft7
sw zero, 39*4(t0) // Initial fs0
sw zero, 40*4(t0) // Initial fs1
sw zero, 41*4(t0) // Initial fa0
sw zero, 42*4(t0) // Initial fa1
sw zero, 43*4(t0) // Initial fa2
sw zero, 44*4(t0) // Initial fa3
sw zero, 45*4(t0) // Initial fa4
sw zero, 46*4(t0) // Initial fa5
sw zero, 47*4(t0) // Initial fa6
sw zero, 48*4(t0) // Initial fa7
sw zero, 49*4(t0) // Initial fs2
sw zero, 50*4(t0) // Initial fs3
sw zero, 51*4(t0) // Initial fs4
sw zero, 52*4(t0) // Initial fs5
sw zero, 53*4(t0) // Initial fs6
sw zero, 54*4(t0) // Initial fs7
sw zero, 55*4(t0) // Initial fs8
sw zero, 56*4(t0) // Initial fs9
sw zero, 57*4(t0) // Initial fs10
sw zero, 58*4(t0) // Initial fs11
sw zero, 59*4(t0) // Initial ft8
sw zero, 60*4(t0) // Initial ft9
sw zero, 61*4(t0) // Initial ft10
sw zero, 62*4(t0) // Initial ft11
csrr a1, fcsr // Read fcsr for initial value
sw a1, 63*4(t0) // Initial fcsr
sw zero, 64*4(t0) // Reserved word (0)
#else
sw zero, 31*4(t0) // Reserved word (0)
#endif
/* Setup stack pointer. */
/* thread_ptr -> tx_thread_stack_ptr = t0; */
sw t0, 8(a0) // Save stack pointer in thread's
ret // control block and return
/* } */
ports/risc-v32/clang/src/tx_thread_system_return.S
-168
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@@ -1,168 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function is target processor specific. It is used to transfer */
/* control from a thread back to the system. Only a minimal context */
/* is saved since the compiler assumes temp registers are going to get */
/* slicked by a function call anyway. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* ThreadX components */
/* */
/**************************************************************************/
/* VOID _tx_thread_system_return(VOID)
{ */
.global _tx_thread_system_return
_tx_thread_system_return:
/* Save minimal context on the stack. */
/* sp -= sizeof(stack_frame); */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, -29*4 // Allocate space on the stack - with floating point enabled
#else
addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled
#endif
/* Store floating point preserved registers. */
#if defined(__riscv_float_abi_single)
fsw f8, 15*4(sp) // Store fs0
fsw f9, 16*4(sp) // Store fs1
fsw f18, 17*4(sp) // Store fs2
fsw f19, 18*4(sp) // Store fs3
fsw f20, 19*4(sp) // Store fs4
fsw f21, 20*4(sp) // Store fs5
fsw f22, 21*4(sp) // Store fs6
fsw f23, 22*4(sp) // Store fs7
fsw f24, 23*4(sp) // Store fs8
fsw f25, 24*4(sp) // Store fs9
fsw f26, 25*4(sp) // Store fs10
fsw f27, 26*4(sp) // Store fs11
csrr t0, fcsr
sw t0, 27*4(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
fsd f8, 15*4(sp) // Store fs0
fsd f9, 16*4(sp) // Store fs1
fsd f18, 17*4(sp) // Store fs2
fsd f19, 18*4(sp) // Store fs3
fsd f20, 19*4(sp) // Store fs4
fsd f21, 20*4(sp) // Store fs5
fsd f22, 21*4(sp) // Store fs6
fsd f23, 22*4(sp) // Store fs7
fsd f24, 23*4(sp) // Store fs8
fsd f25, 24*4(sp) // Store fs9
fsd f26, 25*4(sp) // Store fs10
fsd f27, 26*4(sp) // Store fs11
csrr t0, fcsr
sw t0, 27*4(sp) // Store fcsr
#endif
sw zero, 0(sp) // Solicited stack type
sw ra, 13*4(sp) // Save return address
sw s0, 12*4(sp) // Save s0
sw s1, 11*4(sp) // Save s1
sw s2, 10*4(sp) // Save s2
sw s3, 9*4(sp) // Save s3
sw s4, 8*4(sp) // Save s4
sw s5, 7*4(sp) // Save s5
sw s6, 6*4(sp) // Save s6
sw s7, 5*4(sp) // Save s7
sw s8, 4*4(sp) // Save s8
sw s9, 3*4(sp) // Save s9
sw s10, 2*4(sp) // Save s10
sw s11, 1*4(sp) // Save s11
csrr t0, mstatus // Pickup mstatus
sw t0, 14*4(sp) // Save mstatus
/* Lockout interrupts. will be enabled in _tx_thread_schedule */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_thread_exit // Call the thread execution exit function
#endif
la t0, _tx_thread_current_ptr // Pickup address of pointer
lw t1, 0(t0) // Pickup current thread pointer
la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address
/* Save current stack and switch to system stack. */
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP;
SP = _tx_thread_system_stack_ptr; */
sw sp, 8(t1) // Save stack pointer
lw sp, 0(t2) // Switch to system stack
/* Determine if the time-slice is active. */
/* if (_tx_timer_time_slice)
{ */
la t4, _tx_timer_time_slice // Pickup time slice variable addr
lw t3, 0(t4) // Pickup time slice value
la t2, _tx_thread_schedule // Pickup address of scheduling loop
beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it
/* Save time-slice for the thread and clear the current time-slice. */
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
_tx_timer_time_slice = 0; */
sw t3, 24(t1) // Save current time-slice for thread
sw zero, 0(t4) // Clear time-slice variable
/* } */
_tx_thread_dont_save_ts:
/* Clear the current thread pointer. */
/* _tx_thread_current_ptr = TX_NULL; */
sw x0, 0(t0) // Clear current thread pointer
jr t2 // Return to thread scheduler
/* } */
ports/risc-v32/clang/src/tx_timer_interrupt.S
-204
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@@ -1,204 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Timer */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
.align 4
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt RISC-V32/GNU */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/**************************************************************************/
/* VOID _tx_timer_interrupt(VOID)
{ */
.global _tx_timer_interrupt
_tx_timer_interrupt:
/* Increment the system clock. */
/* _tx_timer_system_clock++; */
la t0, _tx_timer_system_clock // Pickup address of system clock
lw t1, 0(t0) // Pickup system clock
la t2, _tx_timer_time_slice // Pickup address of time slice
lw t3, 0(t2) // Pickup time slice
addi t1, t1, 1 // Increment system clock
sw t1, 0(t0) // Store new system clock
li t6, 0 // Clear local expired flag
/* Test for time-slice expiration. */
/* if (_tx_timer_time_slice)
{ */
beqz t3, _tx_timer_no_time_slice // If 0, skip time slice processing
addi t3, t3, -1 // Decrement the time slice
/* Decrement the time_slice. */
/* _tx_timer_time_slice--; */
sw t3, 0(t2) // Store new time slice
/* Check for expiration. */
/* if (_tx_timer_time_slice == 0) */
bgtz t3, _tx_timer_no_time_slice // If not 0, has not expired yet
li t1, 1 // Build expired flag
/* Set the time-slice expired flag. */
/* _tx_timer_expired_time_slice = TX_TRUE; */
la t4, _tx_timer_expired_time_slice // Get address of expired flag
sw t1, 0(t4) // Set expired flag (UINT)
ori t6, t6, 1 // Set local expired flag
/* } */
_tx_timer_no_time_slice:
/* Test for timer expiration. */
/* if (*_tx_timer_current_ptr)
{ */
la t0, _tx_timer_current_ptr // Pickup address of current ptr
lw t1, 0(t0) // Pickup current pointer (word)
lw t3, 0(t1) // Pickup the current timer entry (word)
la t2, _tx_timer_expired // Pickup address of timer expired flag
li t4, 1 // Build TX_TRUE flag
beqz t3, _tx_timer_no_timer // If NULL, no timer has expired
/* Set expiration flag. */
/* _tx_timer_expired = TX_TRUE; */
ori t6, t6, 2 // Set local expired flag
sw t4, 0(t2) // Set expired flag in memory (UINT)
j _tx_timer_done // Finished timer processing
/* }
else
{ */
_tx_timer_no_timer:
/* No timer expired, increment the timer pointer. */
/* _tx_timer_current_ptr++; */
/* Check for wrap-around. */
/* if (_tx_timer_current_ptr == _tx_timer_list_end) */
la t2, _tx_timer_list_end // Pickup address of list end pointer
lw t3, 0(t2) // Pickup actual list end
addi t1, t1, 4 // Point to next timer entry
sw t1, 0(t0) // Store new timer pointer
bne t1, t3, _tx_timer_skip_wrap // If not same, good pointer
/* Wrap to beginning of list. */
/* _tx_timer_current_ptr = _tx_timer_list_start; */
la t2, _tx_timer_list_start // Pickup address of list start pointer
lw t4, 0(t2) // Pickup start of the list
sw t4, 0(t0) // Store new timer pointer
_tx_timer_skip_wrap:
/* } */
_tx_timer_done:
/* See if anything has expired. */
/* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
{ */
beqz t6, _tx_timer_nothing_expired // If nothing expired skip the rest
addi sp, sp, -16 // Allocate some storage on the stack
sw t6, 0(sp) // Save local expired flag
sw ra, 4(sp) // Save ra
/* Did a timer expire? */
/* if (_tx_timer_expired)
{ */
andi t2, t6, 2 // Isolate the timer expired bit
beqz t2, _tx_timer_dont_activate // No, timer not expired
/* Call the timer expiration processing. */
/* _tx_timer_expiration_process(void); */
call _tx_timer_expiration_process // Call _tx_timer_expiration_process
lw t6, 0(sp) // Recover local expired flag
/* } */
_tx_timer_dont_activate:
/* Did time slice expire? */
/* if (_tx_timer_expired_time_slice)
{ */
andi t2, t6, 1 // Is the timer expired bit set?
beqz t2, _tx_timer_not_ts_expiration // If not, skip time slice processing
/* Time slice interrupted thread. */
/* _tx_thread_time_slice(); */
call _tx_thread_time_slice // Call time slice
/* } */
_tx_timer_not_ts_expiration:
lw ra, 4(sp) // Recover ra
addi sp, sp, 16 // Recover stack space
/* } */
_tx_timer_nothing_expired:
ret
/* } */
ports/risc-v32/common/tx_port_riscv32_common.h
+268
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@@ -0,0 +1,268 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Port Specific */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port_riscv32_common.h RISC-V32 */
/* 6.4.x */
/* */
/* DESCRIPTION */
/* */
/* Shared port definitions for all RISC-V32 toolchain ports (GNU, */
/* Clang, etc.). Each toolchain's tx_port.h includes this file and */
/* may add toolchain-specific definitions afterwards. */
/* */
/**************************************************************************/
/* This file is included from a toolchain-specific tx_port.h; do not */
/* include it directly. */
#ifndef TX_PORT_H
#error "Include tx_port.h, not tx_port_riscv32_common.h directly."
#endif
#ifndef __ASSEMBLER__
/* Include for memset. */
#include <string.h>
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
#endif /* TX_INCLUDE_USER_DEFINE_FILE */
#endif /* __ASSEMBLER__ */
/* Define ThreadX basic types for this port. */
#define VOID void
#ifndef __ASSEMBLER__
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
#endif /* __ASSEMBLER__ */
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
thread creation is less than this value, the thread create call will return an error. */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
#endif
/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */
#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX RISC-V port. */
#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */
#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
/* Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call. */
#define TX_INLINE_INITIALIZATION
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2
#define TX_THREAD_EXTENSION_3
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION
#define TX_SEMAPHORE_EXTENSION
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
/* Expose helper used to perform an atomic read/modify/write of mstatus.
The helper composes and returns the posture per ThreadX contract. */
#ifndef __ASSEMBLER__
UINT _tx_thread_interrupt_control(UINT new_posture);
#endif
#ifdef TX_DISABLE_INLINE
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory");
#define TX_RESTORE { \
unsigned long _temp_mstatus; \
__asm__ volatile( \
"csrc mstatus, 8\n" \
"andi %0, %1, 8\n" \
"csrs mstatus, %0" \
: "=&r" (_temp_mstatus) \
: "r" (interrupt_save) \
: "memory"); \
}
#else
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save);
#endif /* TX_DISABLE_INLINE */
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
ports/risc-v32/gnu/CMakeLists.txt
+5 -21
View File
@@ -1,23 +1,7 @@
include(${CMAKE_CURRENT_LIST_DIR}/../../../cmake/threadx_riscv_port.cmake)
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
threadx_add_riscv_port(
SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/src
INC_DIR ${CMAKE_CURRENT_LIST_DIR}/inc
EXAMPLE_DIR ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt
)
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt/CMakeLists.txt)
add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt)
endif()
ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt
+5
View File
@@ -10,6 +10,10 @@ set(TX_USER_FILE ${CORE_V_MCU_DIR}/include/tx_user.h)
set(THREADX_ARCH "risc-v32")
set(THREADX_TOOLCHAIN "gnu")
message(STATUS "Toolchain file: ${CMAKE_TOOLCHAIN_FILE}")
message(STATUS "C compiler: ${CMAKE_C_COMPILER}")
add_subdirectory(${THREADX_ROOT} threadx)
target_include_directories(threadx PRIVATE ${CORE_V_MCU_DIR}/include)
@@ -17,6 +21,7 @@ set(SRCS
${CORE_V_MCU_DIR}/crt0.S
${CORE_V_MCU_DIR}/vectors.S
${CORE_V_MCU_DIR}/tx_initialize_low_level.S
${CORE_V_MCU_DIR}/bsp/clz.c
${CORE_V_MCU_DIR}/bsp/irq.c
${CORE_V_MCU_DIR}/bsp/timer_irq.c
${CORE_V_MCU_DIR}/bsp/fll.c
ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c
+29
View File
@@ -0,0 +1,29 @@
/* clz.c — portable fallback for __clzsi2 (count leading zeros, 32-bit)
*
* The riscv-collab bare-metal toolchain (riscv64-unknown-elf from /opt/riscv)
* is built without multilib and does not ship an rv32/ilp32 libgcc. As a
* result __clzsi2, which GCC emits for __builtin_clz() on targets without a
* hardware CLZ instruction, is missing at link time.
*
* This file provides a weak definition so that the build is self-contained
* with any RISC-V bare-metal toolchain. When a toolchain does ship the symbol
* in libgcc (e.g. the Ubuntu gcc-riscv64-unknown-elf package), the libgcc copy
* will take precedence over this weak one.
*/
#include <stdint.h>
__attribute__((weak))
int __clzsi2(uint32_t x)
{
if (x == 0U)
return 32;
int n = 0;
if ((x & 0xFFFF0000U) == 0U) { n += 16; x <<= 16; }
if ((x & 0xFF000000U) == 0U) { n += 8; x <<= 8; }
if ((x & 0xF0000000U) == 0U) { n += 4; x <<= 4; }
if ((x & 0xC0000000U) == 0U) { n += 2; x <<= 2; }
if ((x & 0x80000000U) == 0U) { n += 1; }
return n;
}
ports/risc-v32/gnu/example_build/cva6_ariane/entry.s → ports/risc-v32/gnu/example_build/cva6_ariane/entry.S
View File
ports/risc-v32/gnu/example_build/cva6_ariane/plic.c
-72
View File
@@ -1,72 +0,0 @@
#include "plic.h"
#include <stddef.h>
irq_callback callbacks[MAX_CALLBACK_NUM];
void plic_irq_enable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno));
return;
}
void plic_irq_disable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno)));
return;
}
void plic_prio_set(int irqno, int prio)
{
PLIC_SET_PRIO(irqno, prio);
}
int plic_prio_get(int irqno)
{
return PLIC_GET_PRIO(irqno);
}
int plic_register_callback(int irqno, irq_callback callback)
{
if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM))
return -1;
callbacks[irqno] = callback;
return 0;
}
int plic_unregister_callback(int irqno)
{
return plic_register_callback(irqno, NULL);
}
int plic_init(void)
{
for(int i=0;i<MAX_CALLBACK_NUM;i++)
{
callbacks[i] = NULL;
}
return 0;
}
int plic_claim(void)
{
int hart = riscv_get_core();
return (*(uint32_t*)PLIC_MCLAIM(hart));
}
void plic_complete(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno;
return;
}
int plic_irq_intr(void)
{
int ret = -1;
int irqno = plic_claim();
if(callbacks[irqno] != NULL)
ret = (callbacks[irqno])(irqno);
plic_complete(irqno);
return ret;
}
ports/risc-v32/gnu/example_build/cva6_ariane/plic.c
Symlink
+1
View File
@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.c
ports/risc-v32/gnu/example_build/cva6_ariane/plic.h
-49
View File
@@ -1,49 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_PLIC_H
#define RISCV_PLIC_H
#include "csr.h"
#include <stdint.h>
#define PLIC 0x0C000000L
#define PLIC_PRIORITY (PLIC + 0x0)
#define PLIC_PENDING (PLIC + 0x1000)
#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100)
#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100)
#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000)
#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000)
#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4))
#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio))
#define MAX_CALLBACK_NUM 128
typedef int (*irq_callback)(int irqno);
void plic_irq_enable(int irqno);
void plic_irq_disable(int irqno);
int plic_prio_get(int irqno);
void plic_prio_set(int irqno, int prio);
int plic_register_callback(int irqno, irq_callback callback);
int plic_unregister_callback(int irqno);
int plic_init(void);
int plic_claim(void);
void plic_complete(int irqno);
int plic_irq_intr(void);
#endif
ports/risc-v32/gnu/example_build/cva6_ariane/plic.h
Symlink
+1
View File
@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.h
ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt
+2 -2
View File
@@ -2,7 +2,7 @@ set(QEMU_DEMO_DIR ${CMAKE_CURRENT_LIST_DIR})
add_executable(kernel.elf EXCLUDE_FROM_ALL
${QEMU_DEMO_DIR}/demo_threadx.c
${QEMU_DEMO_DIR}/entry.s
${QEMU_DEMO_DIR}/entry.S
${QEMU_DEMO_DIR}/uart.c
${QEMU_DEMO_DIR}/plic.c
${QEMU_DEMO_DIR}/hwtimer.c
@@ -31,7 +31,7 @@ find_package(Python3 COMPONENTS Interpreter)
if(Python3_FOUND)
add_custom_target(check-functional-riscv32
COMMAND ${Python3_EXECUTABLE}
${QEMU_DEMO_DIR}/test/azrtos_test_tx_gnu_riscv32_qemu.py
${QEMU_DEMO_DIR}/test/threadx_test_tx_gnu_riscv32_qemu.py
--elf $<TARGET_FILE:kernel.elf>
--qemu qemu-system-riscv32
--gdb gdb
ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh
+1 -1
View File
@@ -13,7 +13,7 @@ riscv32-unknown-elf-gcc \
-ffunction-sections -fdata-sections \
-I../../../../../common/inc \
-I../../inc \
entry.s \
entry.S \
tx_initialize_low_level.S \
board.c uart.c hwtimer.c plic.c trap.c demo_threadx.c \
-L../../../../../build -lthreadx \
ports/risc-v32/gnu/example_build/qemu_virt/csr.h
-343
View File
@@ -1,343 +0,0 @@
/***************************************************************************
* Copyright (c) 2025 10xEngineers
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_CSR_H
#define RISCV_CSR_H
// Machine Status Register, mstatus
#define MSTATUS_MPP_MASK (3L << 11) // previous mode.
#define MSTATUS_MPP_M (3L << 11)
#define MSTATUS_MPP_S (1L << 11)
#define MSTATUS_MPP_U (0L << 11)
#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
#define MSTATUS_MPIE (1L << 7)
#define MSTATUS_FS (1L << 13)
// Machine-mode Interrupt Enable
#define MIE_MTIE (1L << 7)
#define MIE_MSIE (1L << 3)
#define MIE_MEIE (1L << 11)
#define MIE_STIE (1L << 5) // supervisor timer
#define MIE_SSIE (1L << 1)
#define MIE_SEIE (1L << 9)
// Supervisor Status Register, sstatus
#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
#define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
#define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
#define SSTATUS_SPIE (1L << 5)
#define SSTATUS_UPIE (1L << 4)
// Supervisor Interrupt Enable
#define SIE_SEIE (1L << 9) // external
#define SIE_STIE (1L << 5) // timer
#define SIE_SSIE (1L << 1) // software
#ifndef __ASSEMBLER__
#include <stdint.h>
static inline uint32_t riscv_get_core()
{
uint32_t x;
asm volatile("csrr %0, mhartid" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_mstatus()
{
uint32_t x;
asm volatile("csrr %0, mstatus" : "=r" (x) );
return x;
}
static inline void riscv_writ_mstatus(uint32_t x)
{
asm volatile("csrw mstatus, %0" : : "r" (x));
}
static inline void riscv_writ_mepc(uint32_t x)
{
asm volatile("csrw mepc, %0" : : "r" (x));
}
static inline uint32_t riscv_get_sstatus()
{
uint32_t x;
asm volatile("csrr %0, sstatus" : "=r" (x) );
return x;
}
static inline void riscv_writ_sstatus(uint32_t x)
{
asm volatile("csrw sstatus, %0" : : "r" (x));
}
static inline uint32_t riscv_get_sip()
{
uint32_t x;
asm volatile("csrr %0, sip" : "=r" (x) );
return x;
}
static inline void riscv_writ_sip(uint32_t x)
{
asm volatile("csrw sip, %0" : : "r" (x));
}
static inline uint32_t riscv_get_sie()
{
uint32_t x;
asm volatile("csrr %0, sie" : "=r" (x) );
return x;
}
static inline void riscv_writ_sie(uint32_t x)
{
asm volatile("csrw sie, %0" : : "r" (x));
}
static inline uint32_t riscv_get_mie()
{
uint32_t x;
asm volatile("csrr %0, mie" : "=r" (x) );
return x;
}
static inline void riscv_writ_mie(uint32_t x)
{
asm volatile("csrw mie, %0" : : "r" (x));
}
static inline void riscv_writ_sepc(uint32_t x)
{
asm volatile("csrw sepc, %0" : : "r" (x));
}
static inline uint32_t riscv_get_sepc()
{
uint32_t x;
asm volatile("csrr %0, sepc" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_medeleg()
{
uint32_t x;
asm volatile("csrr %0, medeleg" : "=r" (x) );
return x;
}
static inline void riscv_writ_medeleg(uint32_t x)
{
asm volatile("csrw medeleg, %0" : : "r" (x));
}
static inline uint32_t riscv_get_mideleg()
{
uint32_t x;
asm volatile("csrr %0, mideleg" : "=r" (x) );
return x;
}
static inline void riscv_writ_mideleg(uint32_t x)
{
asm volatile("csrw mideleg, %0" : : "r" (x));
}
static inline void riscv_writ_stvec(uint32_t x)
{
asm volatile("csrw stvec, %0" : : "r" (x));
}
static inline uint32_t riscv_get_stvec()
{
uint32_t x;
asm volatile("csrr %0, stvec" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_stimecmp()
{
uint32_t x;
asm volatile("csrr %0, 0x14d" : "=r" (x) );
return x;
}
static inline void riscv_writ_stimecmp(uint32_t x)
{
asm volatile("csrw 0x14d, %0" : : "r" (x));
}
static inline uint32_t riscv_get_menvcfg()
{
uint32_t x;
asm volatile("csrr %0, 0x30a" : "=r" (x) );
return x;
}
static inline void riscv_writ_menvcfg(uint32_t x)
{
asm volatile("csrw 0x30a, %0" : : "r" (x));
}
static inline void riscv_writ_pmpcfg0(uint32_t x)
{
asm volatile("csrw pmpcfg0, %0" : : "r" (x));
}
static inline void riscv_writ_pmpaddr0(uint32_t x)
{
asm volatile("csrw pmpaddr0, %0" : : "r" (x));
}
static inline void riscv_writ_satp(uint32_t x)
{
asm volatile("csrw satp, %0" : : "r" (x));
}
static inline uint32_t riscv_get_satp()
{
uint32_t x;
asm volatile("csrr %0, satp" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_scause()
{
uint32_t x;
asm volatile("csrr %0, scause" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_stval()
{
uint32_t x;
asm volatile("csrr %0, stval" : "=r" (x) );
return x;
}
static inline void riscv_writ_mcounteren(uint32_t x)
{
asm volatile("csrw mcounteren, %0" : : "r" (x));
}
static inline uint32_t riscv_get_mcounteren()
{
uint32_t x;
asm volatile("csrr %0, mcounteren" : "=r" (x) );
return x;
}
static inline uint32_t riscv_get_time()
{
uint32_t x;
asm volatile("csrr %0, time" : "=r" (x) );
return x;
}
static inline void riscv_sintr_on()
{
uint32_t sstatus = riscv_get_sstatus();
sstatus |= SSTATUS_SIE;
riscv_writ_sstatus(sstatus);
}
static inline void riscv_sintr_off()
{
uint32_t sstatus = riscv_get_sstatus();
sstatus &= (~SSTATUS_SIE);
riscv_writ_sstatus(sstatus);
}
static inline int riscv_sintr_get()
{
uint32_t x = riscv_get_sstatus();
return (x & SSTATUS_SIE) != 0;
}
static inline void riscv_sintr_restore(int x)
{
if(x)
riscv_sintr_on();
else
riscv_sintr_off();
}
static inline void riscv_mintr_on()
{
uint32_t mstatus = riscv_get_mstatus();
mstatus |= MSTATUS_MIE;
riscv_writ_mstatus(mstatus);
}
static inline void riscv_mintr_off()
{
uint32_t mstatus = riscv_get_mstatus();
mstatus &= (~MSTATUS_MIE);
riscv_writ_mstatus(mstatus);
}
static inline int riscv_mintr_get()
{
uint32_t x = riscv_get_mstatus();
return (x & MSTATUS_MIE) != 0;
}
static inline void riscv_mintr_restore(int x)
{
if(x)
riscv_mintr_on();
else
riscv_mintr_off();
}
static inline uint32_t riscv_get_sp()
{
uint32_t x;
asm volatile("mv %0, sp" : "=r" (x) );
return x;
}
// read and write tp, the thread pointer, which xv6 uses to hold
// this core's hartid (core number), the index into cpus[].
static inline uint32_t riscv_get_tp()
{
uint32_t x;
asm volatile("mv %0, tp" : "=r" (x) );
return x;
}
static inline void riscv_writ_tp(uint32_t x)
{
asm volatile("mv tp, %0" : : "r" (x));
}
static inline uint32_t riscv_get_ra()
{
uint32_t x;
asm volatile("mv %0, ra" : "=r" (x) );
return x;
}
// flush the TLB.
static inline void sfence_vma()
{
// the zero, zero means flush all TLB entries.
asm volatile("sfence.vma zero, zero");
}
#endif // __ASSEMBLER__
#endif
ports/risc-v32/gnu/example_build/qemu_virt/csr.h
Symlink
+1
View File
@@ -0,0 +1 @@
../../../../risc-v_common/inc/csr.h

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