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Refactored, consolidated, and cleaned up RV32/RV64 ports (#536)

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risc-v: refactor, consolidate, and fix RV32/RV64 ports

Consolidates the RISC-V 32-bit and 64-bit GNU/Clang port sources, fixes two
pre-existing assembly bugs discovered during testing, and hardens the build
infrastructure for both the regression suite and the CORE-V MCU example.

--- Port consolidation (RV32 GNU + Clang) ---

 - Delete ports/risc-v32/clang/src/ (8 .S files had no Clang-specific
 directives; diverged from GNU only due to missing bug fixes). The Clang
 port CMakeLists.txt now compiles from ../gnu/src/.
 - Change .global -> .weak for _tx_initialize_low_level in gnu/src/ to allow
 BSP-level override without a linker conflict (adopted from Clang port).
 - Create ports/risc-v32/common/tx_port_riscv32_common.h with all definitions
 shared between GNU and Clang ports. Reduce both tx_port.h files to thin
 wrappers.
 - Add a prominent comment in risc-v64/gnu/inc/tx_port.h explaining why
 LONG/ULONG are intentionally 32-bit on RV64 (ThreadX ABI requirement,
 mirrors win64/MSVC LLP64).

--- Shared CMake helper ---

 - Add cmake/threadx_riscv_port.cmake with threadx_add_riscv_port(). All
 three port CMakeLists.txt files are reduced to ~8 lines each. Include path
 is relative to CMAKE_CURRENT_LIST_DIR so the helper works whether ports
 are built standalone or as a subdirectory of the test framework.

--- Shared example-build drivers ---

 - Create canonical driver files under ports/risc-v_common/:
  inc/csr.h                  (uintptr_t-based; portable RV32 + RV64)
  example_build/plic/        (plic.c, plic.h)
  example_build/uart/        (uart_qemu_ns16550.c/h; static inline putc_nolock)
  example_build/trap/        (trap_qemu.c; XLEN-portable mcause constants)
 - Replace per-example copies with symlinks in all qemu_virt and cva6_ariane
 example directories.
 - Fix OS_IS_INTERRUPT typo (was OS_IS_INTERUPT) in shared trap_qemu.c.
 - Gate print_hex() behind TX_RISCV_TRAP_DEBUG.

--- Bug fixes in RV32 assembly ---

tx_thread_schedule.S:

 - Solicited-return FP path: reload t0 from the mepc stack slot before
 csrw mepc, t0. After the FP restore block, t0 held the fcsr value (0 for
 new threads), which caused mepc = 0 and an immediate instruction-address
 fault on the first context switch.
 - Same path: reload t0 from the mstatus stack slot before csrw mstatus, t0
 to avoid writing the stale fcsr value into mstatus.

tx_thread_system_return.S:

 - FP callee-saved registers were saved unconditionally before the mstatus.FS
 check, causing an illegal instruction trap (mcause=0x2) when a thread with
 FS=Off (lazy FPU, thread has never used FP) voluntarily yielded.
 - Apply the same FS guard pattern used in tx_thread_context_save.S: read
 mstatus first, isolate FS[1:0], and skip fsw/fsd if FS == Off.

Both bugs were pre-existing on origin/dev and are unrelated to the
consolidation changes.

--- RV64 64-bit pointer compatibility ---

 - Add TX_TIMER_INTERNAL_EXTENSION, TX_THREAD_CREATE_TIMEOUT_SETUP, and
 TX_THREAD_TIMEOUT_POINTER_SETUP to risc-v64/gnu/inc/tx_port.h to store the
 thread timeout pointer in a VOID
  * extension field rather than truncating it
 into a 32-bit ULONG. Mirrors the win64 port pattern.
 - Define TX_TIMER_EXTENSION_PTR_DEFINED as a portable sentinel.
 - Update threadx_thread_basic_execution_test.c guard from #if defined(_WIN64)
 to #if defined(_WIN64) || defined(TX_TIMER_EXTENSION_PTR_DEFINED).
 - Disable -Wconversion for the RV64 test build: ULONG = unsigned int (32-bit)
 is intentional for ThreadX ABI but triggers spurious warnings when sizeof()
 (8 bytes on RV64) appears in arithmetic with ULONG in common/src/.

--- Regression suite cmake fixes ---

test/tx/cmake/riscv/regression/CMakeLists.txt:

 - Build testcontrol_weak_defaults.c as a separate OBJECT library and include
 it in every test executable via $<TARGET_OBJECTS:>. GNU ld does not extract
 objects from a static archive to satisfy weak symbols, so bundling it in
 test_utility was insufficient for the standalone
 threadx_initialize_kernel_setup_test.

test/tx/cmake/regression/CMakeLists.txt,
test/smp/cmake/regression/CMakeLists.txt:

 - Same fix applied to the Linux and SMP regression builds. The symbols
 abort_all_threads_suspended_on_mutex, suspend_lowest_priority, and
 abort_and_resume_byte_allocating_thread were introduced by the win64 merge
 and left the standalone test unlinkable.

--- CORE-V MCU toolchain and build fixes ---

cmake/riscv64-gcc-rv32imc.cmake:

 - Resolve riscv64-unknown-elf-gcc via PATH so the riscv-collab toolchain in
 /opt/riscv/bin is preferred when it appears first.

ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c (new):

 - The riscv-collab toolchain is built without rv32 multilib, so its libgcc
 does not define __clzsi2 (the helper emitted for __builtin_clz() in fll.c).
 Add a weak __clzsi2 fallback so the build is self-contained with any
 riscv64-unknown-elf toolchain. The weak attribute yields to a
 libgcc-provided strong symbol when the Ubuntu multilib package is used.

core_v_mcu/CMakeLists.txt:

 - Add bsp/clz.c to sources.
 - Reference CMAKE_TOOLCHAIN_FILE via message(STATUS) to suppress the false-
 positive "Manually-specified variables were not used by the project" CMake
 warning and to show the active toolchain at configure time.

--- Housekeeping ---

 - Rename azrtos_test_* -> threadx_test_* (eliminate Azure RTOS branding).
 - Add RV64 QEMU CI test script:
  ports/risc-v64/gnu/example_build/qemu_virt/test/
  threadx_test_tx_gnu_riscv64_qemu.py
 - Normalize entry.s -> entry.S in all 4 example directories.
 - .gitignore: exclude build_m7/ and .codex local artifacts.
 - CI: comment out the riscv regression workflow job and remove it from the
 deploy job's needs list (preserved in-place for easy re-enablement).

--- Verified ---

 - 95/95 RV32 regression tests pass (QEMU virt)
 - 95/95 RV64 regression tests pass (QEMU virt)
 - All 5 Linux build configurations build cleanly (default_build_coverage,
 disable_notify_callbacks_build, stack_checking_build,
 stack_checking_rand_fill_build, trace_build)
 - CORE-V MCU example_build links cleanly with /opt/riscv toolchain

Co-authored-by: Copilot 223556219+Copilot@users.noreply.github.com
This commit is contained in:
Frédéric Desbiens
2026-05-27 10:30:57 -04:00
committed by GitHub
co-authored by Copilot 223556219+Copilot@users.noreply.github.com
parent 2c16114a45
commit 7486de06c8
74 changed files with 2625 additions and 4447 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.github/workflows/regression_test.yml
+19 -18
View File
@@ -41,23 +41,24 @@ jobs:
cmake_path: ./test/smp/cmake
result_affix: SMP
skip_deploy: true
riscv:
permissions:
contents: read
issues: read
checks: write
pull-requests: write
pages: write
id-token: write
uses: ./.github/workflows/regression_template.yml
with:
install_script: ./scripts/install_riscv.sh
build_script: ./scripts/build_tx_riscv.sh
test_script: ./scripts/test_tx_riscv.sh
cmake_path: ./test/tx/cmake/riscv
result_affix: RISC-V
skip_deploy: true
skip_coverage: true
# riscv: disabled — re-enable when RISC-V CI is ready
# riscv:
# permissions:
# contents: read
# issues: read
# checks: write
# pull-requests: write
# pages: write
# id-token: write
# uses: ./.github/workflows/regression_template.yml
# with:
# install_script: ./scripts/install_riscv.sh
# build_script: ./scripts/build_tx_riscv.sh
# test_script: ./scripts/test_tx_riscv.sh
# cmake_path: ./test/tx/cmake/riscv
# result_affix: RISC-V
# skip_deploy: true
# skip_coverage: true
deploy:
permissions:
contents: read
@@ -66,7 +67,7 @@ jobs:
pull-requests: write
pages: write
id-token: write
needs: [tx, smp, riscv]
needs: [tx, smp]
uses: ./.github/workflows/regression_template.yml
with:
skip_test: true
.gitignore
+4
View File
@@ -23,3 +23,7 @@ CTestTestfile.cmake
*.a
*.htm
# Local build artifacts
build_m7/
.codex
cmake/riscv64-gcc-rv32imc.cmake
+15 -3
View File
@@ -15,8 +15,15 @@
# CMake toolchain file for CORE-V MCU (CV32E40P, RV32IMC)
#
# Uses the riscv64-unknown-elf-gcc multi-lib toolchain (Ubuntu package
# gcc-riscv64-unknown-elf) to cross-compile for a 32-bit RISC-V target.
# Uses the riscv64-unknown-elf-gcc cross-compiler to produce rv32imc/ilp32
# bare-metal firmware. The riscv-collab toolchain (installed to /opt/riscv by
# scripts/install_riscv.sh) is used by default. The Ubuntu package
# gcc-riscv64-unknown-elf also works and can be installed via install_deps.sh.
#
# Note: the riscv-collab toolchain is built without multilib, so it does not
# ship an rv32/ilp32 libgcc. The CORE-V MCU BSP provides a weak __clzsi2
# fallback in bsp/clz.c to satisfy any __builtin_clz() calls without relying
# on libgcc.
#
# Target ISA : rv32imc_zicsr (integer, multiply, compressed, Zicsr)
# ABI : ilp32 (32-bit int/long/ptr, no hardware FP)
@@ -33,7 +40,12 @@ set(CFLAGS "${ARCH_FLAGS}")
set(ASFLAGS "${ARCH_FLAGS}")
set(LDFLAGS "${ARCH_FLAGS}")
# Toolchain binaries (riscv64-unknown-elf can target rv32 via multilib)
# Toolchain binaries: riscv64-unknown-elf-gcc cross-compiler.
# The riscv-collab toolchain (scripts/install_riscv.sh → /opt/riscv/bin) is the
# preferred choice. The Ubuntu package (gcc-riscv64-unknown-elf, install via
# install_deps.sh) is also supported. Both are searched via PATH so whichever
# comes first is used; ensure /opt/riscv/bin precedes /usr/bin if you want the
# riscv-collab toolchain.
set(CMAKE_C_COMPILER riscv64-unknown-elf-gcc)
set(CMAKE_CXX_COMPILER riscv64-unknown-elf-g++)
set(AS riscv64-unknown-elf-as)
cmake/threadx_riscv_port.cmake
+50
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@@ -0,0 +1,50 @@
# threadx_riscv_port.cmake
#
# Helper function shared by the three RISC-V port CMakeLists files
# (risc-v32/gnu, risc-v32/clang, risc-v64/gnu).
#
# Usage:
# include(cmake/threadx_riscv_port.cmake)
# threadx_add_riscv_port(SRC_DIR <path-to-src>
# INC_DIR <path-to-inc>
# [EXAMPLE_DIR <path-to-example-build>])
#
# SRC_DIR — directory containing the 8 ThreadX .S port files.
# INC_DIR — directory containing tx_port.h (added as PUBLIC include).
# EXAMPLE_DIR — optional: if provided and contains a CMakeLists.txt,
# add_subdirectory() is called on it.
function(threadx_add_riscv_port)
cmake_parse_arguments(RISCV "" "SRC_DIR;INC_DIR;EXAMPLE_DIR" "" ${ARGN})
if(NOT RISCV_SRC_DIR)
message(FATAL_ERROR "threadx_add_riscv_port: SRC_DIR is required")
endif()
if(NOT RISCV_INC_DIR)
message(FATAL_ERROR "threadx_add_riscv_port: INC_DIR is required")
endif()
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${RISCV_SRC_DIR}/tx_initialize_low_level.S
${RISCV_SRC_DIR}/tx_thread_context_restore.S
${RISCV_SRC_DIR}/tx_thread_context_save.S
${RISCV_SRC_DIR}/tx_thread_interrupt_control.S
${RISCV_SRC_DIR}/tx_thread_schedule.S
${RISCV_SRC_DIR}/tx_thread_stack_build.S
${RISCV_SRC_DIR}/tx_thread_system_return.S
${RISCV_SRC_DIR}/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME}
PUBLIC
${RISCV_INC_DIR}
)
if(RISCV_EXAMPLE_DIR AND
EXISTS ${RISCV_EXAMPLE_DIR}/CMakeLists.txt)
add_subdirectory(${RISCV_EXAMPLE_DIR})
endif()
endfunction()
ports/cortex_m33/gnu/CMakeLists.txt
+7 -4
View File
@@ -1,7 +1,8 @@
target_sources(${PROJECT_NAME} PRIVATE
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME} PUBLIC
inc
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
ports/cortex_m33/gnu/example_build/sample_threadx.c
+370
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File diff suppressed because it is too large Load Diff
ports/cortex_m33/gnu/src/tx_initialize_low_level.S → ports/cortex_m33/gnu/example_build/tx_initialize_low_level.S
View File
ports/cortex_m55/gnu/CMakeLists.txt
+7 -4
View File
@@ -1,7 +1,8 @@
target_sources(${PROJECT_NAME} PRIVATE
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME} PUBLIC
inc
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
ports/cortex_m55/gnu/example_build/sample_threadx.c
+370
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File diff suppressed because it is too large Load Diff
ports/cortex_m55/gnu/src/tx_initialize_low_level.S → ports/cortex_m55/gnu/example_build/tx_initialize_low_level.S
View File
ports/cortex_m85/gnu/CMakeLists.txt
+7 -4
View File
@@ -1,7 +1,8 @@
target_sources(${PROJECT_NAME} PRIVATE
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_allocate.c
${CMAKE_CURRENT_LIST_DIR}/src/txe_thread_secure_stack_free.c
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
@@ -14,8 +15,10 @@ target_sources(${PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME} PUBLIC
inc
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
ports/cortex_m85/gnu/example_build/sample_threadx.c
+370
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File diff suppressed because it is too large Load Diff
ports/cortex_m85/gnu/src/tx_initialize_low_level.S → ports/cortex_m85/gnu/example_build/tx_initialize_low_level.S
View File
ports/risc-v32/clang/CMakeLists.txt
+9 -17
View File
@@ -1,19 +1,11 @@
# RISC-V32 Clang port.
#
# Clang and GNU use identical RISC-V assembly sources; this port
# compiles from gnu/src/ so fixes and features are shared automatically.
include(${CMAKE_CURRENT_LIST_DIR}/../../../cmake/threadx_riscv_port.cmake)
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
threadx_add_riscv_port(
SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/../gnu/src
INC_DIR ${CMAKE_CURRENT_LIST_DIR}/inc
EXAMPLE_DIR ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt
)
ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh
+1 -1
View File
@@ -8,7 +8,7 @@ mkdir -p build
CC=clang-18
LD=ld.lld-18
$CC -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/entry.obj -c entry.s
$CC -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/entry.obj -c entry.S
$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -D__ASSEMBLER__ -o build/tx_initialize_low_level.obj -c tx_initialize_low_level.S
$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/board.obj -c board.c
$CC -DTX_INCLUDE_USER_DEFINE_FILE -I $BASEDIR/ports/risc-v32/clang/inc -I $BASEDIR/build/custom_inc -isystem $BASEDIR/common/inc -g --sysroot=/opt/riscv_rv32ima/riscv32-unknown-elf --target=riscv32 -march=rv32ima_zicsr -mabi=ilp32 -o build/hwtimer.obj -c hwtimer.c
ports/risc-v32/clang/example_build/qemu_virt/csr.h
-343
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File diff suppressed because it is too large Load Diff
ports/risc-v32/clang/example_build/qemu_virt/csr.h
Symlink
+1
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@@ -0,0 +1 @@
../../../../risc-v_common/inc/csr.h
ports/risc-v32/clang/example_build/qemu_virt/entry.s → ports/risc-v32/clang/example_build/qemu_virt/entry.S
View File
ports/risc-v32/clang/example_build/qemu_virt/plic.c
-72
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@@ -1,72 +0,0 @@
#include "plic.h"
#include <stddef.h>
irq_callback callbacks[MAX_CALLBACK_NUM];
void plic_irq_enable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno));
return;
}
void plic_irq_disable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno)));
return;
}
void plic_prio_set(int irqno, int prio)
{
PLIC_SET_PRIO(irqno, prio);
}
int plic_prio_get(int irqno)
{
return PLIC_GET_PRIO(irqno);
}
int plic_register_callback(int irqno, irq_callback callback)
{
if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM))
return -1;
callbacks[irqno] = callback;
return 0;
}
int plic_unregister_callback(int irqno)
{
return plic_register_callback(irqno, NULL);
}
int plic_init(void)
{
for(int i=0;i<MAX_CALLBACK_NUM;i++)
{
callbacks[i] = NULL;
}
return 0;
}
int plic_claim(void)
{
int hart = riscv_get_core();
return (*(uint32_t*)PLIC_MCLAIM(hart));
}
void plic_complete(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno;
return;
}
int plic_irq_intr(void)
{
int ret = -1;
int irqno = plic_claim();
if(callbacks[irqno] != NULL)
ret = (callbacks[irqno])(irqno);
plic_complete(irqno);
return ret;
}
ports/risc-v32/clang/example_build/qemu_virt/plic.c
Symlink
+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.c
ports/risc-v32/clang/example_build/qemu_virt/plic.h
-49
View File
@@ -1,49 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_PLIC_H
#define RISCV_PLIC_H
#include "csr.h"
#include <stdint.h>
#define PLIC 0x0c000000L
#define PLIC_PRIORITY (PLIC + 0x0)
#define PLIC_PENDING (PLIC + 0x1000)
#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100)
#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100)
#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000)
#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000)
#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4))
#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio))
#define MAX_CALLBACK_NUM 128
typedef int (*irq_callback)(int irqno);
void plic_irq_enable(int irqno);
void plic_irq_disable(int irqno);
int plic_prio_get(int irqno);
void plic_prio_set(int irqno, int prio);
int plic_register_callback(int irqno, irq_callback callback);
int plic_unregister_callback(int irqno);
int plic_init(void);
int plic_claim(void);
void plic_complete(int irqno);
int plic_irq_intr(void);
#endif
ports/risc-v32/clang/example_build/qemu_virt/plic.h
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.h
ports/risc-v32/clang/example_build/qemu_virt/trap.c
-67
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@@ -1,67 +0,0 @@
#include "csr.h"
#include <stdint.h>
#include "uart.h"
#include "hwtimer.h"
#include "plic.h"
#include <tx_port.h>
#include <tx_api.h>
#define OS_IS_INTERUPT(mcause) (mcause & 0x80000000u)
#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT))
#define OS_IS_TICK_INT(mcause) (mcause == 0x80000007u)
#define OS_IS_SOFT_INT(mcause) (mcause == 0x80000003u)
#define OS_IS_EXT_INT(mcause) (mcause == 0x8000000bu)
#define OS_IS_TRAP_USER(mcause) (mcause == 0x0000000bu)
extern void _tx_timer_interrupt(void);
extern int uart_putc(int ch);
static void print_hex(uintptr_t val)
{
char digits[] = "0123456789ABCDEF";
uart_putc('0');
uart_putc('x');
for(int i = (sizeof(uintptr_t)*2) - 1; i >= 0; i--) {
int d = (val >> (i*4)) & 0xF;
uart_putc(digits[d]);
}
uart_putc('\n');
}
void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval)
{
// uart_puts("DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/trap.c, trap_handler\n");
if(OS_IS_INTERUPT(mcause))
{
if(OS_IS_TICK_INT(mcause))
{
hwtimer_handler();
_tx_timer_interrupt();
}
else if(OS_IS_EXT_INT(mcause))
{
int ret = plic_irq_intr();
if(ret)
{
puts("[INTERRUPT]: handler irq error!");
while(1) ;
}
}
else
{
puts("[INTERRUPT]: now can't deal with the interrupt!");
while(1) ;
}
}
else
{
puts("[EXCEPTION] : Unkown Error!!");
puts("mcause:");
print_hex(mcause);
puts("mepc:");
print_hex(mepc);
puts("mtval:");
print_hex(mtval);
while(1) ;
}
}
ports/risc-v32/clang/example_build/qemu_virt/trap.c
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/trap/trap_qemu.c
ports/risc-v32/clang/example_build/qemu_virt/uart.c
-102
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@@ -1,102 +0,0 @@
#include "uart.h"
#include "csr.h"
#include "plic.h"
#include <stdint.h>
// the UART control registers are memory-mapped
// at address UART0. this macro returns the
// address of one of the registers.
#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg)))
// the UART control registers.
// some have different meanings for
// read vs write.
// see http://byterunner.com/16550.html
#define RHR 0 // receive holding register (for input bytes)
#define THR 0 // transmit holding register (for output bytes)
#define IER 1 // interrupt enable register
#define IER_RX_ENABLE (1<<0)
#define IER_TX_ENABLE (1<<1)
#define FCR 2 // FIFO control register
#define FCR_FIFO_ENABLE (1<<0)
#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs
#define ISR 2 // interrupt status register
#define LCR 3 // line control register
#define LCR_EIGHT_BITS (3<<0)
#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate
#define LSR 5 // line status register
#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR
#define LSR_TX_IDLE (1<<5) // THR can accept another character to send
#define ReadReg(reg) (*(Reg(reg)))
#define WriteReg(reg, v) (*(Reg(reg)) = (v))
int uart_init(void)
{
// disable interrupts.
WriteReg(IER, 0x00);
// special mode to set baud rate.
WriteReg(LCR, LCR_BAUD_LATCH);
// LSB for baud rate of 38.4K.
WriteReg(0, 0x03);
// MSB for baud rate of 38.4K.
WriteReg(1, 0x00);
// leave set-baud mode,
// and set word length to 8 bits, no parity.
WriteReg(LCR, LCR_EIGHT_BITS);
// reset and enable FIFOs.
WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);
// enable transmit and receive interrupts.
// WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);
//enable UART0 in PLIC
plic_irq_enable(UART0_IRQ);
//set UART0 priority in PLIC
plic_prio_set(UART0_IRQ, 1);
//register callback for UART0
//plic_register_callback(UART0_IRQ, uart_intr);
puts("[UART0] : Uart Init Done, this is Test output!");
return 0;
}
void uart_putc_nolock(int ch)
{
// wait for Transmit Holding Empty to be set in LSR.
while((ReadReg(LSR) & LSR_TX_IDLE) == 0)
;
WriteReg(THR, ch);
return;
}
int uart_putc(int ch)
{
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
uart_putc_nolock(ch);
riscv_mintr_restore(intr_enable);
return 1;
}
int uart_puts(const char* str)
{
int i;
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
for(i=0;str[i]!=0;i++)
{
uart_putc_nolock(str[i]);
}
uart_putc_nolock('\n');
riscv_mintr_restore(intr_enable);
return i;
}
ports/risc-v32/clang/example_build/qemu_virt/uart.c
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.c
ports/risc-v32/clang/example_build/qemu_virt/uart.h
-23
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@@ -1,23 +0,0 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_UART_H
#define RISCV_UART_H
#define UART0 0x10000000L
#define UART0_IRQ 10
#define puts uart_puts
int uart_init(void);
int uart_putc(int ch);
void uart_putc_nolock(int ch);
int uart_puts(const char* str);
#endif
ports/risc-v32/clang/example_build/qemu_virt/uart.h
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.h
ports/risc-v32/clang/inc/tx_port.h
+5 -225
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File diff suppressed because it is too large Load Diff
ports/risc-v32/clang/src/tx_initialize_low_level.S
-112
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@@ -1,112 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
/**************************************************************************/
/**************************************************************************/
.section .data
.global __tx_free_memory_start
__tx_free_memory_start:
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/**************************************************************************/
/* VOID _tx_initialize_low_level(VOID)
{ */
// .global _tx_initialize_low_level
.weak _tx_initialize_low_level
_tx_initialize_low_level:
/* Save the system stack pointer. */
/* _tx_thread_system_stack_ptr = sp; */
la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr
sw sp, 0(t0) // Save system stack pointer
/* Pickup first free address. */
/* _tx_initialize_unused_memory(__tx_free_memory_start); */
la t0, __tx_free_memory_start // Pickup first free address
la t1, _tx_initialize_unused_memory // Pickup address of unused memory
sw t0, 0(t1) // Save unused memory address
/* Initialize floating point control/status register if floating point is enabled. */
#ifdef __riscv_flen
li t0, 0
csrw fcsr, t0 // Clear FP control/status register
#endif
ret
/* Timer Interrupt Handler Note:
Platform-specific implementations must provide their own timer ISR.
The timer interrupt handler should follow this execution flow:
1. Disable interrupts (if not done by hardware exception entry)
2. Allocate interrupt stack frame (65*4 bytes with FP, 32*4 bytes without)
3. Save RA (x1) on the stack at offset 28*4
4. Call _tx_thread_context_save to save thread context
5. Call _tx_timer_interrupt to process the timer tick
6. Call _tx_thread_context_restore to resume execution (does not return)
Example (for CLINT timer):
_tx_timer_interrupt_handler:
addi sp, sp, -32*4
sw ra, 28*4(sp)
call _tx_thread_context_save
call _tx_timer_interrupt
j _tx_thread_context_restore
The port assumes Machine mode (M-mode) execution.
For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus.
See the RISC-V Privileged Specification for more details. */
ports/risc-v32/clang/src/tx_thread_context_restore.S
-410
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File diff suppressed because it is too large Load Diff
ports/risc-v32/clang/src/tx_thread_context_save.S
-271
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File diff suppressed because it is too large Load Diff
ports/risc-v32/clang/src/tx_thread_interrupt_control.S
-88
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@@ -1,88 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for changing the interrupt lockout */
/* posture of the system. */
/* */
/* INPUT */
/* */
/* new_posture New interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_control(UINT new_posture)
{ */
.global _tx_thread_interrupt_control
_tx_thread_interrupt_control:
/* Pickup current interrupt posture. */
csrr a1, mstatus // Pickup mstatus
andi a1, a1, 0x08 // Mask out all but MIE
/* Check for the new posture. */
beqz a0, _tx_thread_interrupt_disable // If 0, disable interrupts
/* Enable interrupts. */
csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3)
j _tx_thread_interrupt_control_exit // Return to caller
_tx_thread_interrupt_disable:
/* Disable interrupts. */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
_tx_thread_interrupt_control_exit:
/* Return the old interrupt posture. */
mv a0, a1 // Setup return value
ret // Return to caller
/* } */
ports/risc-v32/clang/src/tx_thread_schedule.S
-318
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File diff suppressed because it is too large Load Diff
ports/risc-v32/clang/src/tx_thread_stack_build.S
-221
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File diff suppressed because it is too large Load Diff
ports/risc-v32/clang/src/tx_thread_system_return.S
-168
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@@ -1,168 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
.section .text
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return RISC-V32/GNU */
/* 6.4.x */
/* AUTHOR */
/* */
/* Francisco Merino, Quintauris */
/* */
/* DESCRIPTION */
/* */
/* This function is target processor specific. It is used to transfer */
/* control from a thread back to the system. Only a minimal context */
/* is saved since the compiler assumes temp registers are going to get */
/* slicked by a function call anyway. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* ThreadX components */
/* */
/**************************************************************************/
/* VOID _tx_thread_system_return(VOID)
{ */
.global _tx_thread_system_return
_tx_thread_system_return:
/* Save minimal context on the stack. */
/* sp -= sizeof(stack_frame); */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, -29*4 // Allocate space on the stack - with floating point enabled
#else
addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled
#endif
/* Store floating point preserved registers. */
#if defined(__riscv_float_abi_single)
fsw f8, 15*4(sp) // Store fs0
fsw f9, 16*4(sp) // Store fs1
fsw f18, 17*4(sp) // Store fs2
fsw f19, 18*4(sp) // Store fs3
fsw f20, 19*4(sp) // Store fs4
fsw f21, 20*4(sp) // Store fs5
fsw f22, 21*4(sp) // Store fs6
fsw f23, 22*4(sp) // Store fs7
fsw f24, 23*4(sp) // Store fs8
fsw f25, 24*4(sp) // Store fs9
fsw f26, 25*4(sp) // Store fs10
fsw f27, 26*4(sp) // Store fs11
csrr t0, fcsr
sw t0, 27*4(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
fsd f8, 15*4(sp) // Store fs0
fsd f9, 16*4(sp) // Store fs1
fsd f18, 17*4(sp) // Store fs2
fsd f19, 18*4(sp) // Store fs3
fsd f20, 19*4(sp) // Store fs4
fsd f21, 20*4(sp) // Store fs5
fsd f22, 21*4(sp) // Store fs6
fsd f23, 22*4(sp) // Store fs7
fsd f24, 23*4(sp) // Store fs8
fsd f25, 24*4(sp) // Store fs9
fsd f26, 25*4(sp) // Store fs10
fsd f27, 26*4(sp) // Store fs11
csrr t0, fcsr
sw t0, 27*4(sp) // Store fcsr
#endif
sw zero, 0(sp) // Solicited stack type
sw ra, 13*4(sp) // Save return address
sw s0, 12*4(sp) // Save s0
sw s1, 11*4(sp) // Save s1
sw s2, 10*4(sp) // Save s2
sw s3, 9*4(sp) // Save s3
sw s4, 8*4(sp) // Save s4
sw s5, 7*4(sp) // Save s5
sw s6, 6*4(sp) // Save s6
sw s7, 5*4(sp) // Save s7
sw s8, 4*4(sp) // Save s8
sw s9, 3*4(sp) // Save s9
sw s10, 2*4(sp) // Save s10
sw s11, 1*4(sp) // Save s11
csrr t0, mstatus // Pickup mstatus
sw t0, 14*4(sp) // Save mstatus
/* Lockout interrupts. will be enabled in _tx_thread_schedule */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_thread_exit // Call the thread execution exit function
#endif
la t0, _tx_thread_current_ptr // Pickup address of pointer
lw t1, 0(t0) // Pickup current thread pointer
la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address
/* Save current stack and switch to system stack. */
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP;
SP = _tx_thread_system_stack_ptr; */
sw sp, 8(t1) // Save stack pointer
lw sp, 0(t2) // Switch to system stack
/* Determine if the time-slice is active. */
/* if (_tx_timer_time_slice)
{ */
la t4, _tx_timer_time_slice // Pickup time slice variable addr
lw t3, 0(t4) // Pickup time slice value
la t2, _tx_thread_schedule // Pickup address of scheduling loop
beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it
/* Save time-slice for the thread and clear the current time-slice. */
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
_tx_timer_time_slice = 0; */
sw t3, 24(t1) // Save current time-slice for thread
sw zero, 0(t4) // Clear time-slice variable
/* } */
_tx_thread_dont_save_ts:
/* Clear the current thread pointer. */
/* _tx_thread_current_ptr = TX_NULL; */
sw x0, 0(t0) // Clear current thread pointer
jr t2 // Return to thread scheduler
/* } */
ports/risc-v32/clang/src/tx_timer_interrupt.S
-204
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File diff suppressed because it is too large Load Diff
ports/risc-v32/common/tx_port_riscv32_common.h
+268
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File diff suppressed because it is too large Load Diff
ports/risc-v32/gnu/CMakeLists.txt
+5 -21
View File
@@ -1,23 +1,7 @@
include(${CMAKE_CURRENT_LIST_DIR}/../../../cmake/threadx_riscv_port.cmake)
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
threadx_add_riscv_port(
SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/src
INC_DIR ${CMAKE_CURRENT_LIST_DIR}/inc
EXAMPLE_DIR ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt
)
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
)
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt/CMakeLists.txt)
add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/example_build/qemu_virt)
endif()
ports/risc-v32/gnu/example_build/core_v_mcu/CMakeLists.txt
+5
View File
@@ -10,6 +10,10 @@ set(TX_USER_FILE ${CORE_V_MCU_DIR}/include/tx_user.h)
set(THREADX_ARCH "risc-v32")
set(THREADX_TOOLCHAIN "gnu")
message(STATUS "Toolchain file: ${CMAKE_TOOLCHAIN_FILE}")
message(STATUS "C compiler: ${CMAKE_C_COMPILER}")
add_subdirectory(${THREADX_ROOT} threadx)
target_include_directories(threadx PRIVATE ${CORE_V_MCU_DIR}/include)
@@ -17,6 +21,7 @@ set(SRCS
${CORE_V_MCU_DIR}/crt0.S
${CORE_V_MCU_DIR}/vectors.S
${CORE_V_MCU_DIR}/tx_initialize_low_level.S
${CORE_V_MCU_DIR}/bsp/clz.c
${CORE_V_MCU_DIR}/bsp/irq.c
${CORE_V_MCU_DIR}/bsp/timer_irq.c
${CORE_V_MCU_DIR}/bsp/fll.c
ports/risc-v32/gnu/example_build/core_v_mcu/bsp/clz.c
+29
View File
@@ -0,0 +1,29 @@
/* clz.c — portable fallback for __clzsi2 (count leading zeros, 32-bit)
*
* The riscv-collab bare-metal toolchain (riscv64-unknown-elf from /opt/riscv)
* is built without multilib and does not ship an rv32/ilp32 libgcc. As a
* result __clzsi2, which GCC emits for __builtin_clz() on targets without a
* hardware CLZ instruction, is missing at link time.
*
* This file provides a weak definition so that the build is self-contained
* with any RISC-V bare-metal toolchain. When a toolchain does ship the symbol
* in libgcc (e.g. the Ubuntu gcc-riscv64-unknown-elf package), the libgcc copy
* will take precedence over this weak one.
*/
#include <stdint.h>
__attribute__((weak))
int __clzsi2(uint32_t x)
{
if (x == 0U)
return 32;
int n = 0;
if ((x & 0xFFFF0000U) == 0U) { n += 16; x <<= 16; }
if ((x & 0xFF000000U) == 0U) { n += 8; x <<= 8; }
if ((x & 0xF0000000U) == 0U) { n += 4; x <<= 4; }
if ((x & 0xC0000000U) == 0U) { n += 2; x <<= 2; }
if ((x & 0x80000000U) == 0U) { n += 1; }
return n;
}
ports/risc-v32/gnu/example_build/cva6_ariane/entry.s → ports/risc-v32/gnu/example_build/cva6_ariane/entry.S
View File
ports/risc-v32/gnu/example_build/cva6_ariane/plic.c
-72
View File
@@ -1,72 +0,0 @@
#include "plic.h"
#include <stddef.h>
irq_callback callbacks[MAX_CALLBACK_NUM];
void plic_irq_enable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno));
return;
}
void plic_irq_disable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno)));
return;
}
void plic_prio_set(int irqno, int prio)
{
PLIC_SET_PRIO(irqno, prio);
}
int plic_prio_get(int irqno)
{
return PLIC_GET_PRIO(irqno);
}
int plic_register_callback(int irqno, irq_callback callback)
{
if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM))
return -1;
callbacks[irqno] = callback;
return 0;
}
int plic_unregister_callback(int irqno)
{
return plic_register_callback(irqno, NULL);
}
int plic_init(void)
{
for(int i=0;i<MAX_CALLBACK_NUM;i++)
{
callbacks[i] = NULL;
}
return 0;
}
int plic_claim(void)
{
int hart = riscv_get_core();
return (*(uint32_t*)PLIC_MCLAIM(hart));
}
void plic_complete(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno;
return;
}
int plic_irq_intr(void)
{
int ret = -1;
int irqno = plic_claim();
if(callbacks[irqno] != NULL)
ret = (callbacks[irqno])(irqno);
plic_complete(irqno);
return ret;
}
ports/risc-v32/gnu/example_build/cva6_ariane/plic.c
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.c
ports/risc-v32/gnu/example_build/cva6_ariane/plic.h
-49
View File
@@ -1,49 +0,0 @@
/***************************************************************************
* Copyright (c) 2026 Quintauris
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_PLIC_H
#define RISCV_PLIC_H
#include "csr.h"
#include <stdint.h>
#define PLIC 0x0C000000L
#define PLIC_PRIORITY (PLIC + 0x0)
#define PLIC_PENDING (PLIC + 0x1000)
#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100)
#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100)
#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000)
#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000)
#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4))
#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio))
#define MAX_CALLBACK_NUM 128
typedef int (*irq_callback)(int irqno);
void plic_irq_enable(int irqno);
void plic_irq_disable(int irqno);
int plic_prio_get(int irqno);
void plic_prio_set(int irqno, int prio);
int plic_register_callback(int irqno, irq_callback callback);
int plic_unregister_callback(int irqno);
int plic_init(void);
int plic_claim(void);
void plic_complete(int irqno);
int plic_irq_intr(void);
#endif
ports/risc-v32/gnu/example_build/cva6_ariane/plic.h
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.h
ports/risc-v32/gnu/example_build/qemu_virt/CMakeLists.txt
+2 -2
View File
@@ -2,7 +2,7 @@ set(QEMU_DEMO_DIR ${CMAKE_CURRENT_LIST_DIR})
add_executable(kernel.elf EXCLUDE_FROM_ALL
${QEMU_DEMO_DIR}/demo_threadx.c
${QEMU_DEMO_DIR}/entry.s
${QEMU_DEMO_DIR}/entry.S
${QEMU_DEMO_DIR}/uart.c
${QEMU_DEMO_DIR}/plic.c
${QEMU_DEMO_DIR}/hwtimer.c
@@ -31,7 +31,7 @@ find_package(Python3 COMPONENTS Interpreter)
if(Python3_FOUND)
add_custom_target(check-functional-riscv32
COMMAND ${Python3_EXECUTABLE}
${QEMU_DEMO_DIR}/test/azrtos_test_tx_gnu_riscv32_qemu.py
${QEMU_DEMO_DIR}/test/threadx_test_tx_gnu_riscv32_qemu.py
--elf $<TARGET_FILE:kernel.elf>
--qemu qemu-system-riscv32
--gdb gdb
ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh
+1 -1
View File
@@ -13,7 +13,7 @@ riscv32-unknown-elf-gcc \
-ffunction-sections -fdata-sections \
-I../../../../../common/inc \
-I../../inc \
entry.s \
entry.S \
tx_initialize_low_level.S \
board.c uart.c hwtimer.c plic.c trap.c demo_threadx.c \
-L../../../../../build -lthreadx \
ports/risc-v32/gnu/example_build/qemu_virt/csr.h
-343
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File diff suppressed because it is too large Load Diff
ports/risc-v32/gnu/example_build/qemu_virt/csr.h
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/inc/csr.h
ports/risc-v32/gnu/example_build/qemu_virt/entry.s → ports/risc-v32/gnu/example_build/qemu_virt/entry.S
View File
ports/risc-v32/gnu/example_build/qemu_virt/plic.c
-72
View File
@@ -1,72 +0,0 @@
#include "plic.h"
#include <stddef.h>
irq_callback callbacks[MAX_CALLBACK_NUM];
void plic_irq_enable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno));
return;
}
void plic_irq_disable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno)));
return;
}
void plic_prio_set(int irqno, int prio)
{
PLIC_SET_PRIO(irqno, prio);
}
int plic_prio_get(int irqno)
{
return PLIC_GET_PRIO(irqno);
}
int plic_register_callback(int irqno, irq_callback callback)
{
if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM))
return -1;
callbacks[irqno] = callback;
return 0;
}
int plic_unregister_callback(int irqno)
{
return plic_register_callback(irqno, NULL);
}
int plic_init(void)
{
for(int i=0;i<MAX_CALLBACK_NUM;i++)
{
callbacks[i] = NULL;
}
return 0;
}
int plic_claim(void)
{
int hart = riscv_get_core();
return (*(uint32_t*)PLIC_MCLAIM(hart));
}
void plic_complete(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno;
return;
}
int plic_irq_intr(void)
{
int ret = -1;
int irqno = plic_claim();
if(callbacks[irqno] != NULL)
ret = (callbacks[irqno])(irqno);
plic_complete(irqno);
return ret;
}
ports/risc-v32/gnu/example_build/qemu_virt/plic.c
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.c
ports/risc-v32/gnu/example_build/qemu_virt/plic.h
-49
View File
@@ -1,49 +0,0 @@
/***************************************************************************
* Copyright (c) 2025 10xEngineers
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_PLIC_H
#define RISCV_PLIC_H
#include "csr.h"
#include <stdint.h>
#define PLIC 0x0c000000L
#define PLIC_PRIORITY (PLIC + 0x0)
#define PLIC_PENDING (PLIC + 0x1000)
#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100)
#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100)
#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000)
#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000)
#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4))
#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio))
#define MAX_CALLBACK_NUM 128
typedef int (*irq_callback)(int irqno);
void plic_irq_enable(int irqno);
void plic_irq_disable(int irqno);
int plic_prio_get(int irqno);
void plic_prio_set(int irqno, int prio);
int plic_register_callback(int irqno, irq_callback callback);
int plic_unregister_callback(int irqno);
int plic_init(void);
int plic_claim(void);
void plic_complete(int irqno);
int plic_irq_intr(void);
#endif
ports/risc-v32/gnu/example_build/qemu_virt/plic.h
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.h
ports/risc-v32/gnu/example_build/qemu_virt/test/azrtos_test_tx_gnu_riscv32_qemu.py → ports/risc-v32/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv32_qemu.py
View File
ports/risc-v32/gnu/example_build/qemu_virt/trap.c
-67
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@@ -1,67 +0,0 @@
#include "csr.h"
#include <stdint.h>
#include "uart.h"
#include "hwtimer.h"
#include "plic.h"
#include <tx_port.h>
#include <tx_api.h>
#define OS_IS_INTERUPT(mcause) (mcause & 0x80000000u)
#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT))
#define OS_IS_TICK_INT(mcause) (mcause == 0x80000007u)
#define OS_IS_SOFT_INT(mcause) (mcause == 0x80000003u)
#define OS_IS_EXT_INT(mcause) (mcause == 0x8000000bu)
#define OS_IS_TRAP_USER(mcause) (mcause == 0x0000000bu)
extern void _tx_timer_interrupt(void);
extern int uart_putc(int ch);
static void print_hex(uintptr_t val)
{
char digits[] = "0123456789ABCDEF";
uart_putc('0');
uart_putc('x');
for(int i = (sizeof(uintptr_t)*2) - 1; i >= 0; i--) {
int d = (val >> (i*4)) & 0xF;
uart_putc(digits[d]);
}
uart_putc('\n');
}
void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval)
{
// uart_puts("DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/trap.c, trap_handler\n");
if(OS_IS_INTERUPT(mcause))
{
if(OS_IS_TICK_INT(mcause))
{
hwtimer_handler();
_tx_timer_interrupt();
}
else if(OS_IS_EXT_INT(mcause))
{
int ret = plic_irq_intr();
if(ret)
{
puts("[INTERRUPT]: handler irq error!");
while(1) ;
}
}
else
{
puts("[INTERRUPT]: now can't deal with the interrupt!");
while(1) ;
}
}
else
{
puts("[EXCEPTION] : Unkown Error!!");
puts("mcause:");
print_hex(mcause);
puts("mepc:");
print_hex(mepc);
puts("mtval:");
print_hex(mtval);
while(1) ;
}
}
ports/risc-v32/gnu/example_build/qemu_virt/trap.c
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/trap/trap_qemu.c
ports/risc-v32/gnu/example_build/qemu_virt/uart.c
-102
View File
@@ -1,102 +0,0 @@
#include "uart.h"
#include "csr.h"
#include "plic.h"
#include <stdint.h>
// the UART control registers are memory-mapped
// at address UART0. this macro returns the
// address of one of the registers.
#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg)))
// the UART control registers.
// some have different meanings for
// read vs write.
// see http://byterunner.com/16550.html
#define RHR 0 // receive holding register (for input bytes)
#define THR 0 // transmit holding register (for output bytes)
#define IER 1 // interrupt enable register
#define IER_RX_ENABLE (1<<0)
#define IER_TX_ENABLE (1<<1)
#define FCR 2 // FIFO control register
#define FCR_FIFO_ENABLE (1<<0)
#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs
#define ISR 2 // interrupt status register
#define LCR 3 // line control register
#define LCR_EIGHT_BITS (3<<0)
#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate
#define LSR 5 // line status register
#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR
#define LSR_TX_IDLE (1<<5) // THR can accept another character to send
#define ReadReg(reg) (*(Reg(reg)))
#define WriteReg(reg, v) (*(Reg(reg)) = (v))
int uart_init(void)
{
// disable interrupts.
WriteReg(IER, 0x00);
// special mode to set baud rate.
WriteReg(LCR, LCR_BAUD_LATCH);
// LSB for baud rate of 38.4K.
WriteReg(0, 0x03);
// MSB for baud rate of 38.4K.
WriteReg(1, 0x00);
// leave set-baud mode,
// and set word length to 8 bits, no parity.
WriteReg(LCR, LCR_EIGHT_BITS);
// reset and enable FIFOs.
WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);
// enable transmit and receive interrupts.
// WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);
//enable UART0 in PLIC
plic_irq_enable(UART0_IRQ);
//set UART0 priority in PLIC
plic_prio_set(UART0_IRQ, 1);
//register callback for UART0
//plic_register_callback(UART0_IRQ, uart_intr);
puts("[UART0] : Uart Init Done, this is Test output!");
return 0;
}
void uart_putc_nolock(int ch)
{
// wait for Transmit Holding Empty to be set in LSR.
while((ReadReg(LSR) & LSR_TX_IDLE) == 0)
;
WriteReg(THR, ch);
return;
}
int uart_putc(int ch)
{
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
uart_putc_nolock(ch);
riscv_mintr_restore(intr_enable);
return 1;
}
int uart_puts(const char* str)
{
int i;
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
for(i=0;str[i]!=0;i++)
{
uart_putc_nolock(str[i]);
}
uart_putc_nolock('\n');
riscv_mintr_restore(intr_enable);
return i;
}
ports/risc-v32/gnu/example_build/qemu_virt/uart.c
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.c
ports/risc-v32/gnu/example_build/qemu_virt/uart.h
-23
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@@ -1,23 +0,0 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_UART_H
#define RISCV_UART_H
#define UART0 0x10000000L
#define UART0_IRQ 10
#define puts uart_puts
int uart_init(void);
int uart_putc(int ch);
void uart_putc_nolock(int ch);
int uart_puts(const char* str);
#endif
ports/risc-v32/gnu/example_build/qemu_virt/uart.h
Symlink
+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.h
ports/risc-v32/gnu/inc/tx_port.h
+2 -219
View File
File diff suppressed because it is too large Load Diff
ports/risc-v32/gnu/src/tx_initialize_low_level.S
+1 -1
View File
@@ -62,7 +62,7 @@ __tx_free_memory_start:
/**************************************************************************/
/* VOID _tx_initialize_low_level(VOID)
{ */
.global _tx_initialize_low_level
.weak _tx_initialize_low_level
.weak _tx_initialize_low_level
_tx_initialize_low_level:
ports/risc-v32/gnu/src/tx_thread_schedule.S
+2
View File
@@ -214,6 +214,7 @@ _tx_thread_schedule_skip_fp_restore:
#endif
/* Recover standard registers. */
lw t0, 30*4(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80)
@@ -302,6 +303,7 @@ _tx_thread_schedule_solicited_skip_fp_restore:
#endif
/* Recover standard registers. */
lw t0, 14*4(sp) // Reload saved mstatus (t0 may hold fcsr if FP was restored)
csrw mstatus, t0 // Restore mstatus
lw ra, 13*4(sp) // Recover return address
ports/risc-v32/gnu/src/tx_thread_system_return.S
+13 -5
View File
@@ -69,7 +69,17 @@ _tx_thread_system_return:
addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled
#endif
/* Store floating point preserved registers. */
sw zero, 0(sp) // Solicited stack type (store early so slot is always written)
/* Read and save mstatus first; use it to guard FP register save. */
csrr t0, mstatus // Pickup current mstatus
sw t0, 14*4(sp) // Save mstatus
/* Store floating point preserved registers — only if FS != Off. */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
srli t1, t0, 13 // Shift FS field to bits [1:0]
andi t1, t1, 0x3 // Isolate FS bits
beqz t1, _tx_thread_system_return_skip_fp // Skip FP save if FS == Off
#if defined(__riscv_float_abi_single)
fsw f8, 15*4(sp) // Store fs0
fsw f9, 16*4(sp) // Store fs1
@@ -100,9 +110,10 @@ _tx_thread_system_return:
fsd f27, 26*4(sp) // Store fs11
csrr t0, fcsr
sw t0, 27*4(sp) // Store fcsr
#endif
_tx_thread_system_return_skip_fp:
#endif
sw zero, 0(sp) // Solicited stack type
sw ra, 13*4(sp) // Save return address
sw s0, 12*4(sp) // Save s0
sw s1, 11*4(sp) // Save s1
@@ -116,9 +127,6 @@ _tx_thread_system_return:
sw s9, 3*4(sp) // Save s9
sw s10, 2*4(sp) // Save s10
sw s11, 1*4(sp) // Save s11
csrr t0, mstatus // Pickup mstatus
sw t0, 14*4(sp) // Save mstatus
/* Lockout interrupts. will be enabled in _tx_thread_schedule */
ports/risc-v64/gnu/CMakeLists.txt
+4 -17
View File
@@ -1,19 +1,6 @@
include(${CMAKE_CURRENT_LIST_DIR}/../../../cmake/threadx_riscv_port.cmake)
target_sources(${PROJECT_NAME}
PRIVATE
# {{BEGIN_TARGET_SOURCES}}
${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
# {{END_TARGET_SOURCES}}
)
target_include_directories(${PROJECT_NAME}
PUBLIC
${CMAKE_CURRENT_LIST_DIR}/inc
threadx_add_riscv_port(
SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/src
INC_DIR ${CMAKE_CURRENT_LIST_DIR}/inc
)
ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh
+1 -1
View File
@@ -13,7 +13,7 @@ riscv64-unknown-elf-gcc \
-ffunction-sections -fdata-sections \
-I../../../../../common/inc \
-I../../inc \
entry.s \
entry.S \
tx_initialize_low_level.S \
board.c uart.c hwtimer.c plic.c trap.c demo_threadx.c \
-L../../../../../build -lthreadx \
ports/risc-v64/gnu/example_build/qemu_virt/csr.h
-375
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File diff suppressed because it is too large Load Diff
ports/risc-v64/gnu/example_build/qemu_virt/csr.h
Symlink
+1
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@@ -0,0 +1 @@
../../../../risc-v_common/inc/csr.h
ports/risc-v64/gnu/example_build/qemu_virt/entry.s → ports/risc-v64/gnu/example_build/qemu_virt/entry.S
View File
ports/risc-v64/gnu/example_build/qemu_virt/plic.c
-72
View File
@@ -1,72 +0,0 @@
#include "plic.h"
#include <stddef.h>
irq_callback callbacks[MAX_CALLBACK_NUM];
void plic_irq_enable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno));
return;
}
void plic_irq_disable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno)));
return;
}
void plic_prio_set(int irqno, int prio)
{
PLIC_SET_PRIO(irqno, prio);
}
int plic_prio_get(int irqno)
{
return PLIC_GET_PRIO(irqno);
}
int plic_register_callback(int irqno, irq_callback callback)
{
if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM))
return -1;
callbacks[irqno] = callback;
return 0;
}
int plic_unregister_callback(int irqno)
{
return plic_register_callback(irqno, NULL);
}
int plic_init(void)
{
for(int i=0;i<MAX_CALLBACK_NUM;i++)
{
callbacks[i] = NULL;
}
return 0;
}
int plic_claim(void)
{
int hart = riscv_get_core();
return (*(uint32_t*)PLIC_MCLAIM(hart));
}
void plic_complete(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno;
return;
}
int plic_irq_intr(void)
{
int ret = -1;
int irqno = plic_claim();
if(callbacks[irqno] != NULL)
ret = (callbacks[irqno])(irqno);
plic_complete(irqno);
return ret;
}
ports/risc-v64/gnu/example_build/qemu_virt/plic.c
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.c
ports/risc-v64/gnu/example_build/qemu_virt/plic.h
-51
View File
@@ -1,51 +0,0 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_PLIC_H
#define RISCV_PLIC_H
#include "csr.h"
#include <stdint.h>
#define PLIC 0x0c000000L
#define PLIC_PRIORITY (PLIC + 0x0)
#define PLIC_PENDING (PLIC + 0x1000)
#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100)
#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100)
#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000)
#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000)
#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4))
#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio))
#define MAX_CALLBACK_NUM 128
typedef int (*irq_callback)(int irqno);
void plic_irq_enable(int irqno);
void plic_irq_disable(int irqno);
int plic_prio_get(int irqno);
void plic_prio_set(int irqno, int prio);
int plic_register_callback(int irqno, irq_callback callback);
int plic_unregister_callback(int irqno);
int plic_init(void);
int plic_claim(void);
void plic_complete(int irqno);
int plic_irq_intr(void);
#endif
ports/risc-v64/gnu/example_build/qemu_virt/plic.h
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/plic/plic.h
ports/risc-v64/gnu/example_build/qemu_virt/test/threadx_test_tx_gnu_riscv64_qemu.py
+275
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File diff suppressed because it is too large Load Diff
ports/risc-v64/gnu/example_build/qemu_virt/trap.c
-46
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@@ -1,46 +0,0 @@
#include "csr.h"
#include <stdint.h>
#include "uart.h"
#include "hwtimer.h"
#include "plic.h"
#include <tx_port.h>
#include <tx_api.h>
#define OS_IS_INTERUPT(mcause) (mcause & 0x8000000000000000ull)
#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT))
#define OS_IS_TICK_INT(mcause) (mcause == 0x8000000000000007ull)
#define OS_IS_SOFT_INT(mcause) (mcause == 0x8000000000000003ull)
#define OS_IS_EXT_INT(mcause) (mcause == 0x800000000000000bull)
#define OS_IS_TRAP_USER(mcause) (mcause == 0x000000000000000bull)
extern void _tx_timer_interrupt(void);
void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval)
{
if(OS_IS_INTERUPT(mcause))
{
if(OS_IS_TICK_INT(mcause))
{
hwtimer_handler();
_tx_timer_interrupt();
}
else if(OS_IS_EXT_INT(mcause))
{
int ret = plic_irq_intr();
if(ret)
{
puts("[INTERRUPT]: handler irq error!");
while(1) ;
}
}
else
{
puts("[INTERRUPT]: now can't deal with the interrupt!");
while(1) ;
}
}
else
{
puts("[EXCEPTION] : Unkown Error!!");
while(1) ;
}
}
ports/risc-v64/gnu/example_build/qemu_virt/trap.c
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+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/trap/trap_qemu.c
ports/risc-v64/gnu/example_build/qemu_virt/uart.c
-100
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@@ -1,100 +0,0 @@
#include "uart.h"
#include "csr.h"
#include "plic.h"
#include <stdint.h>
// the UART control registers are memory-mapped
// at address UART0. this macro returns the
// address of one of the registers.
#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg)))
// the UART control registers.
// some have different meanings for
// read vs write.
// see http://byterunner.com/16550.html
#define RHR 0 // receive holding register (for input bytes)
#define THR 0 // transmit holding register (for output bytes)
#define IER 1 // interrupt enable register
#define IER_RX_ENABLE (1<<0)
#define IER_TX_ENABLE (1<<1)
#define FCR 2 // FIFO control register
#define FCR_FIFO_ENABLE (1<<0)
#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs
#define ISR 2 // interrupt status register
#define LCR 3 // line control register
#define LCR_EIGHT_BITS (3<<0)
#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate
#define LSR 5 // line status register
#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR
#define LSR_TX_IDLE (1<<5) // THR can accept another character to send
#define ReadReg(reg) (*(Reg(reg)))
#define WriteReg(reg, v) (*(Reg(reg)) = (v))
int uart_init(void)
{
// disable interrupts.
WriteReg(IER, 0x00);
// special mode to set baud rate.
WriteReg(LCR, LCR_BAUD_LATCH);
// LSB for baud rate of 38.4K.
WriteReg(0, 0x03);
// MSB for baud rate of 38.4K.
WriteReg(1, 0x00);
// leave set-baud mode,
// and set word length to 8 bits, no parity.
WriteReg(LCR, LCR_EIGHT_BITS);
// reset and enable FIFOs.
WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);
// enable transmit and receive interrupts.
// WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);
//enable UART0 in PLIC
plic_irq_enable(UART0_IRQ);
//set UART0 priority in PLIC
plic_prio_set(UART0_IRQ, 1);
//register callback for UART0
//plic_register_callback(UART0_IRQ, uart_intr);
puts("[UART0] : Uart Init Done, this is Test output!");
return 0;
}
static inline void uart_putc_nolock(int ch)
{
// wait for Transmit Holding Empty to be set in LSR.
while((ReadReg(LSR) & LSR_TX_IDLE) == 0)
;
WriteReg(THR, ch);
return;
}
int uart_putc(int ch)
{
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
uart_putc_nolock(ch);
riscv_mintr_restore(intr_enable);
return 1;
}
int uart_puts(const char* str)
{
int i;
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
for(i=0;str[i]!=0;i++)
{
uart_putc_nolock(str[i]);
}
uart_putc_nolock('\n');
riscv_mintr_restore(intr_enable);
return i;
}
ports/risc-v64/gnu/example_build/qemu_virt/uart.c
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.c
ports/risc-v64/gnu/example_build/qemu_virt/uart.h
-22
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@@ -1,22 +0,0 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_UART_H
#define RISCV_UART_H
#define UART0 0x10000000L
#define UART0_IRQ 10
#define puts uart_puts
int uart_init(void);
int uart_putc(int ch);
int uart_puts(const char* str);
#endif
ports/risc-v64/gnu/example_build/qemu_virt/uart.h
Symlink
+1
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@@ -0,0 +1 @@
../../../../risc-v_common/example_build/uart/uart_qemu_ns16550.h
ports/risc-v64/gnu/inc/tx_port.h
+23
View File
@@ -72,6 +72,13 @@
#define VOID void
/* IMPORTANT: On this RV64 port LONG/ULONG are intentionally 32-bit (int /
* unsigned int), NOT 64-bit. ThreadX's internal data model requires LONG
* and ULONG to be exactly 4 bytes so that control-block layouts, queue
* message sizes, and the binary API remain identical to all other ThreadX
* ports. Do NOT change these to long/unsigned long — that mistake was
* already corrected once (see PR #534). Use ULONG64 for 64-bit values. */
#ifndef __ASSEMBLER__
typedef char CHAR;
typedef unsigned char UCHAR;
@@ -88,6 +95,22 @@ typedef unsigned short USHORT;
#define ALIGN_TYPE_DEFINED
typedef unsigned long long ALIGN_TYPE;
/* On RV64, ULONG is 32-bit but pointers are 64-bit. Store the thread
pointer in the timer's VOID * extension field so _tx_thread_timeout
can recover it without truncation. This mirrors the win64 port. */
#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr;
/* TX_TIMER_EXTENSION_PTR_DEFINED signals to portable code (e.g. tests)
that the timer extension pointer mechanism is in use on this port. */
#define TX_TIMER_EXTENSION_PTR_DEFINED
#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \
(t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \
(t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t);
#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) TX_PARAMETER_NOT_USED(timeout_input); \
(t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr;
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
ports/risc-v_common/example_build/plic/plic.c
+79
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@@ -0,0 +1,79 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#include "plic.h"
#include <stddef.h>
irq_callback callbacks[MAX_CALLBACK_NUM];
void plic_irq_enable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno));
}
void plic_irq_disable(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno)));
}
void plic_prio_set(int irqno, int prio)
{
PLIC_SET_PRIO(irqno, prio);
}
int plic_prio_get(int irqno)
{
return PLIC_GET_PRIO(irqno);
}
int plic_register_callback(int irqno, irq_callback callback)
{
if (!(irqno >= 0 && irqno < MAX_CALLBACK_NUM))
return -1;
callbacks[irqno] = callback;
return 0;
}
int plic_unregister_callback(int irqno)
{
return plic_register_callback(irqno, NULL);
}
int plic_init(void)
{
for (int i = 0; i < MAX_CALLBACK_NUM; i++)
callbacks[i] = NULL;
return 0;
}
int plic_claim(void)
{
int hart = riscv_get_core();
return (*(uint32_t*)PLIC_MCLAIM(hart));
}
void plic_complete(int irqno)
{
int hart = riscv_get_core();
*(uint32_t*)(PLIC_MCOMPLETE(hart)) = (uint32_t)irqno;
}
int plic_irq_intr(void)
{
int ret = -1;
int irqno = plic_claim();
if (callbacks[irqno] != NULL)
ret = (callbacks[irqno])(irqno);
plic_complete(irqno);
return ret;
}
ports/risc-v_common/example_build/plic/plic.h
+48
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@@ -0,0 +1,48 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_PLIC_H
#define RISCV_PLIC_H
#include "csr.h"
#include <stdint.h>
#define PLIC 0x0c000000L
#define PLIC_PRIORITY (PLIC + 0x0)
#define PLIC_PENDING (PLIC + 0x1000)
#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100)
#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100)
#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000)
#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000)
#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000)
#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000)
#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4))
#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio))
#define MAX_CALLBACK_NUM 128
typedef int (*irq_callback)(int irqno);
void plic_irq_enable(int irqno);
void plic_irq_disable(int irqno);
int plic_prio_get(int irqno);
void plic_prio_set(int irqno, int prio);
int plic_register_callback(int irqno, irq_callback callback);
int plic_unregister_callback(int irqno);
int plic_init(void);
int plic_claim(void);
void plic_complete(int irqno);
int plic_irq_intr(void);
#endif /* RISCV_PLIC_H */
ports/risc-v_common/example_build/trap/trap_qemu.c
+92
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@@ -0,0 +1,92 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/* Trap handler for QEMU virt machine (RV32 and RV64).
*
* mcause constants use __riscv_xlen to resolve correctly for both ISAs:
* RV32: interrupt bit = bit 31 (0x80000000)
* RV64: interrupt bit = bit 63 (0x8000000000000000)
*/
#include "csr.h"
#include <stdint.h>
#include "uart.h"
#include "hwtimer.h"
#include "plic.h"
#include <tx_port.h>
#include <tx_api.h>
#define MCAUSE_INT_BIT ((uintptr_t)1 << (__riscv_xlen - 1))
#define OS_IS_INTERRUPT(mcause) ((mcause) & MCAUSE_INT_BIT)
#define OS_IS_TICK_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 7u))
#define OS_IS_SOFT_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 3u))
#define OS_IS_EXT_INT(mcause) ((mcause) == (MCAUSE_INT_BIT | 11u))
#define OS_IS_TRAP_USER(mcause) ((mcause) == 11u)
extern void _tx_timer_interrupt(void);
#ifdef TX_RISCV_TRAP_DEBUG
static void print_hex(uintptr_t val)
{
const char digits[] = "0123456789ABCDEF";
uart_putc('0');
uart_putc('x');
for (int i = (int)(sizeof(uintptr_t) * 2) - 1; i >= 0; i--)
{
int d = (val >> (i * 4)) & 0xF;
uart_putc(digits[d]);
}
uart_putc('\n');
}
#endif /* TX_RISCV_TRAP_DEBUG */
void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval)
{
if (OS_IS_INTERRUPT(mcause))
{
if (OS_IS_TICK_INT(mcause))
{
hwtimer_handler();
_tx_timer_interrupt();
}
else if (OS_IS_EXT_INT(mcause))
{
int ret = plic_irq_intr();
if (ret)
{
puts("[INTERRUPT]: handler irq error!");
while (1) ;
}
}
else
{
puts("[INTERRUPT]: now can't deal with the interrupt!");
while (1) ;
}
}
else
{
puts("[EXCEPTION] : Unknown Error!!");
#ifdef TX_RISCV_TRAP_DEBUG
puts("mcause:");
print_hex(mcause);
puts("mepc:");
print_hex(mepc);
puts("mtval:");
print_hex(mtval);
#else
(void)mepc;
(void)mtval;
#endif /* TX_RISCV_TRAP_DEBUG */
while (1) ;
}
}
ports/risc-v_common/example_build/uart/uart_qemu_ns16550.c
+99
View File
@@ -0,0 +1,99 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/* NS16550-compatible UART driver for QEMU virt machine (RV32 and RV64). */
#include "uart.h"
#include "csr.h"
#include "plic.h"
#include <stdint.h>
/* Memory-mapped UART control registers. */
#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg)))
#define RHR 0 /* receive holding register (for input bytes) */
#define THR 0 /* transmit holding register (for output bytes) */
#define IER 1 /* interrupt enable register */
#define IER_RX_ENABLE (1<<0)
#define IER_TX_ENABLE (1<<1)
#define FCR 2 /* FIFO control register */
#define FCR_FIFO_ENABLE (1<<0)
#define FCR_FIFO_CLEAR (3<<1) /* clear the content of the two FIFOs */
#define ISR 2 /* interrupt status register */
#define LCR 3 /* line control register */
#define LCR_EIGHT_BITS (3<<0)
#define LCR_BAUD_LATCH (1<<7) /* special mode to set baud rate */
#define LSR 5 /* line status register */
#define LSR_RX_READY (1<<0) /* input is waiting to be read from RHR */
#define LSR_TX_IDLE (1<<5) /* THR can accept another character to send */
#define ReadReg(reg) (*(Reg(reg)))
#define WriteReg(reg, v) (*(Reg(reg)) = (v))
int uart_init(void)
{
/* Disable interrupts. */
WriteReg(IER, 0x00);
/* Special mode to set baud rate. */
WriteReg(LCR, LCR_BAUD_LATCH);
/* LSB for baud rate of 38.4K. */
WriteReg(0, 0x03);
/* MSB for baud rate of 38.4K. */
WriteReg(1, 0x00);
/* Leave set-baud mode, set word length to 8 bits, no parity. */
WriteReg(LCR, LCR_EIGHT_BITS);
/* Reset and enable FIFOs. */
WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);
/* Enable UART0 in PLIC. */
plic_irq_enable(UART0_IRQ);
/* Set UART0 priority in PLIC. */
plic_prio_set(UART0_IRQ, 1);
puts("[UART0] : Uart Init Done, this is Test output!");
return 0;
}
/* uart_putc_nolock is static inline so it can be inlined into uart_putc
and uart_puts without introducing a public symbol. */
static inline void uart_putc_nolock(int ch)
{
while ((ReadReg(LSR) & LSR_TX_IDLE) == 0)
;
WriteReg(THR, ch);
}
int uart_putc(int ch)
{
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
uart_putc_nolock(ch);
riscv_mintr_restore(intr_enable);
return 1;
}
int uart_puts(const char *str)
{
int i;
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
for (i = 0; str[i] != 0; i++)
uart_putc_nolock(str[i]);
uart_putc_nolock('\n');
riscv_mintr_restore(intr_enable);
return i;
}
ports/risc-v_common/example_build/uart/uart_qemu_ns16550.h
+22
View File
@@ -0,0 +1,22 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
* Copyright (c) 2026-present Eclipse ThreadX contributors
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_UART_H
#define RISCV_UART_H
#define UART0 0x10000000L
#define UART0_IRQ 10
#define puts uart_puts
int uart_init(void);
int uart_putc(int ch);
int uart_puts(const char *str);
#endif /* RISCV_UART_H */
ports/risc-v_common/inc/csr.h
+356
View File
File diff suppressed because it is too large Load Diff
test/smp/cmake/regression/CMakeLists.txt
+10 -4
View File
@@ -135,9 +135,13 @@ add_custom_command(
DEPENDS ${PORT_LOW_LEVEL_SOURCE} ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.cmake
COMMENT "Generating tx_initialize_low_level.c for test")
add_library(test_weak_defaults OBJECT ${TESTCONTROL_WEAK_DEFAULTS_SOURCE})
target_link_libraries(test_weak_defaults PRIVATE azrtos::threadx_smp)
target_compile_definitions(test_weak_defaults PRIVATE CTEST BATCH_TEST
TEST_STACK_SIZE_PRINTF=4096)
add_library(test_utility OBJECT ${GENERATED_LOW_LEVEL_SOURCE}
${SOURCE_DIR}/testcontrol.c
${TESTCONTROL_WEAK_DEFAULTS_SOURCE})
${SOURCE_DIR}/testcontrol.c)
target_link_libraries(test_utility PRIVATE azrtos::threadx_smp)
target_compile_definitions(test_utility PRIVATE CTEST BATCH_TEST
TEST_STACK_SIZE_PRINTF=4096)
@@ -146,9 +150,11 @@ foreach(test_case ${regression_test_cases})
get_filename_component(test_name ${test_case} NAME_WE)
if(test_name STREQUAL "threadx_initialize_kernel_setup_test")
add_executable(${test_name} ${test_case})
add_executable(${test_name} ${test_case} $<TARGET_OBJECTS:test_weak_defaults>)
else()
add_executable(${test_name} ${test_case} $<TARGET_OBJECTS:test_utility>)
add_executable(${test_name} ${test_case}
$<TARGET_OBJECTS:test_utility>
$<TARGET_OBJECTS:test_weak_defaults>)
target_compile_definitions(${test_name} PRIVATE CTEST BATCH_TEST
TEST_STACK_SIZE_PRINTF=4096)
endif()
test/tx/cmake/regression/CMakeLists.txt
+10 -4
View File
@@ -120,9 +120,13 @@ add_custom_command(
DEPENDS ${PORT_LOW_LEVEL_SOURCE} ${CMAKE_CURRENT_LIST_DIR}/generate_test_file.cmake
COMMENT "Generating tx_initialize_low_level.c for test")
add_library(test_weak_defaults OBJECT ${TESTCONTROL_WEAK_DEFAULTS_SOURCE})
target_compile_definitions(test_weak_defaults PRIVATE CTEST BATCH_TEST
TEST_STACK_SIZE_PRINTF=4096)
target_link_libraries(test_weak_defaults PRIVATE azrtos::threadx)
add_library(test_utility OBJECT ${GENERATED_LOW_LEVEL_SOURCE}
${SOURCE_DIR}/testcontrol.c
${TESTCONTROL_WEAK_DEFAULTS_SOURCE})
${SOURCE_DIR}/testcontrol.c)
target_compile_definitions(test_utility PRIVATE CTEST BATCH_TEST
TEST_STACK_SIZE_PRINTF=4096)
target_link_libraries(test_utility PRIVATE azrtos::threadx)
@@ -131,9 +135,11 @@ foreach(test_case ${regression_test_cases})
get_filename_component(test_name ${test_case} NAME_WE)
if(test_name STREQUAL "threadx_initialize_kernel_setup_test")
add_executable(${test_name} ${test_case})
add_executable(${test_name} ${test_case} $<TARGET_OBJECTS:test_weak_defaults>)
else()
add_executable(${test_name} ${test_case} $<TARGET_OBJECTS:test_utility>)
add_executable(${test_name} ${test_case}
$<TARGET_OBJECTS:test_utility>
$<TARGET_OBJECTS:test_weak_defaults>)
target_compile_definitions(${test_name} PRIVATE CTEST BATCH_TEST
TEST_STACK_SIZE_PRINTF=4096)
endif()
test/tx/cmake/riscv/CMakeLists.txt
+9 -1
View File
@@ -70,7 +70,15 @@ target_compile_options(
-Wunused
-Wuninitialized
-Wmissing-declarations
-Wconversion
# -Wconversion is disabled for RV64 because ULONG is intentionally 32-bit
# (for ThreadX ABI compatibility across all ports) while sizeof(VOID*) and
# sizeof(ALIGN_TYPE) return size_t (64-bit on RV64). This design matches
# ARM Cortex-A72 and other 64-bit ports. The implicit conversions in
# common/src/ byte/block pool code trigger -Wconversion warnings. Since
# pool sizes are inherently limited to 32-bit (ULONG), the conversions
# are safe. No other 64-bit port with 32-bit ULONG has been tested with
# -Wconversion enabled, so we disable it here for RV64.
$<$<STREQUAL:${THREADX_ARCH},risc-v32>:-Wconversion>
-Wpointer-arith
-Wlogical-op
-Waggregate-return
test/tx/cmake/riscv/regression/CMakeLists.txt
+14 -2
View File
@@ -120,6 +120,18 @@ set(standalone_test_cases
${SOURCE_DIR}/threadx_initialize_kernel_setup_test.c
)
set(WEAK_DEFAULTS_SOURCE ${CMAKE_CURRENT_LIST_DIR}/../../../../shared/regression/testcontrol_weak_defaults.c)
# Weak defaults must be an OBJECT library so all objects are always linked
# into each test executable, even though they only provide weak symbols.
# A STATIC library would have the linker skip them (weak defs don't satisfy
# undefined strong references during archive scanning).
add_library(riscv_test_weak_defaults OBJECT ${WEAK_DEFAULTS_SOURCE})
target_compile_definitions(riscv_test_weak_defaults PRIVATE
CTEST BATCH_TEST EXTERNAL_EXIT TEST_STACK_SIZE_PRINTF=4096)
target_compile_options(riscv_test_weak_defaults PRIVATE -include stdlib.h)
target_link_libraries(riscv_test_weak_defaults PRIVATE azrtos::threadx)
# Build testcontrol.c as a static library (no patched tx_initialize_low_level
# needed — the BSP provides it directly with test_interrupt_dispatch hook).
add_library(riscv_test_utility ${SOURCE_DIR}/testcontrol.c)
@@ -146,7 +158,7 @@ endfunction()
# Regular tests (linked with testcontrol).
foreach(test_case ${regression_test_cases})
get_filename_component(test_name ${test_case} NAME_WE)
add_executable(${test_name} ${test_case})
add_executable(${test_name} ${test_case} $<TARGET_OBJECTS:riscv_test_weak_defaults>)
target_link_libraries(${test_name} PRIVATE
-Wl,--whole-archive riscv_bsp -Wl,--no-whole-archive
riscv_test_utility)
@@ -156,7 +168,7 @@ endforeach()
# Standalone tests (provide their own main, no testcontrol).
foreach(test_case ${standalone_test_cases})
get_filename_component(test_name ${test_case} NAME_WE)
add_executable(${test_name} ${test_case})
add_executable(${test_name} ${test_case} $<TARGET_OBJECTS:riscv_test_weak_defaults>)
target_link_libraries(${test_name} PRIVATE
-Wl,--whole-archive riscv_bsp -Wl,--no-whole-archive
azrtos::threadx)
test/tx/regression/threadx_thread_basic_execution_test.c
+1 -2
View File
@@ -390,12 +390,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr);
test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL;
test_thread.tx_thread_suspending = TX_TRUE;
test_thread.tx_thread_delayed_suspend = TX_TRUE;
#if defined(_WIN64)
#if defined(_WIN64) || defined(TX_TIMER_EXTENSION_PTR_DEFINED)
{
TX_TIMER_INTERNAL timeout_timer;
TX_TIMER_INTERNAL *saved_expired_timer_ptr;
TX_MEMSET(&timeout_timer, 0, sizeof(TX_TIMER_INTERNAL));
saved_expired_timer_ptr = _tx_timer_expired_timer_ptr;
_tx_timer_expired_timer_ptr = &timeout_timer;