Refused the Cortex-R52 VFP option without a hard float ABI (#686)

TX_R52_ENABLE_VFP with the default soft float ABI cannot build.  The option
defines TX_ENABLE_VFP_SUPPORT, which enables the VMRS, VSTMDB and VLDMIA
blocks in the port assembly, and -mfloat-abi=soft leaves the assembler with
no FPU to accept them.  The configuration fails with eight errors of the form

  tx_thread_system_return.S:118: Error: selected processor does not support
  `vmrs r4,FPSCR' in ARM mode

none of which mentions the float ABI, so a user has to reason from VMRS back
to the option that enabled it.

The guard that exists said otherwise.  It warned that "the compiler will not
emit floating-point instructions, so the VFP context path will never be
exercised", which describes a build that succeeds and is merely pointless --
and then let configure finish, so the warning scrolled past well before the
assembler errors appeared.

It is now a FATAL_ERROR that names the fix, which is what the same file
already does six lines above for TX_R52_ENABLE_FIQ_NESTING without
TX_R52_ENABLE_FIQ.  That combination is rejected for being "meaningless",
while this one, which cannot assemble at all, was only warned about.  The
severities were the wrong way round.  The option's definition also moves
below the check, so the block reads like the FIQ nesting one.

The ABI is not promoted to hard automatically.  TX_R52_FLOAT_ABI is a cache
variable the user may have set deliberately, and silently overriding an
explicit choice is worse than refusing a combination that cannot work.

readme_threadx.txt carried the same claim, and its option list marked the FIQ
nesting dependency inline but not this one.  Both corrected.

No regression test.  Nothing in the tree asserts a configure-time failure --
there is no harness for it, and the sibling FIQ nesting guard has none either
-- so a test for this would have to introduce that mechanism for one case.
Verified by hand in both directions instead: the soft-ABI combination now
stops at configure with the message above, and the hard-ABI feature build
(VFP, FIQ, IRQ nesting, FIQ nesting) builds its eight images clean and passes
ctest 8/8 on the Armv8-R AEM FVP.  scripts/check_gcc.sh passes unchanged; it
configures the Cortex-R52 CMake stage without TX_R52_ENABLE_VFP, so the new
branch is not on its path.

Assisted-by: Claude Code (Opus 5) <noreply@anthropic.com>

ports/cortex_r52/gnu/CMakeLists.txt

@@ -60,13 +60,15 @@ if(TX_R52_ENABLE_FIQ_NESTING)
     target_compile_definitions(${PROJECT_NAME} PUBLIC TX_ENABLE_FIQ_NESTING)
 endif()
 if(TX_R52_ENABLE_VFP)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC TX_ENABLE_VFP_SUPPORT)
     if(NOT TX_R52_FLOAT_ABI STREQUAL "hard")
-        message(WARNING
-            "TX_R52_ENABLE_VFP is on but TX_R52_FLOAT_ABI is '${TX_R52_FLOAT_ABI}'. "
-            "The compiler will not emit floating-point instructions, so the VFP "
-            "context path will never be exercised. Use -DTX_R52_FLOAT_ABI=hard.")
+        message(FATAL_ERROR
+            "TX_R52_ENABLE_VFP requires TX_R52_FLOAT_ABI=hard, but it is "
+            "'${TX_R52_FLOAT_ABI}'. TX_ENABLE_VFP_SUPPORT enables the VMRS, "
+            "VSTMDB and VLDMIA blocks in the port assembly, and a soft float "
+            "ABI leaves the assembler with no FPU to accept them, so this "
+            "combination fails to assemble. Use -DTX_R52_FLOAT_ABI=hard.")
     endif()
+    target_compile_definitions(${PROJECT_NAME} PUBLIC TX_ENABLE_VFP_SUPPORT)
 endif()
 
 # Armv8-R AEM FVP example builds (boot check now, kernel demo from AR1/M2).

ports/cortex_r52/gnu/readme_threadx.txt

@@ -25,6 +25,7 @@ is empty, so no A- or R-profile port could previously be built this way.
 
     -DTX_R52_FLOAT_ABI=soft|hard      floating-point ABI, default soft
     -DTX_R52_ENABLE_VFP=ON            lazy VFP context save and restore
+                                      (requires TX_R52_FLOAT_ABI=hard)
     -DTX_R52_ENABLE_FIQ=ON            FIQ support
     -DTX_R52_ENABLE_IRQ_NESTING=ON    nested IRQ support
     -DTX_R52_ENABLE_FIQ_NESTING=ON    nested FIQ support (requires the above)
@@ -33,9 +34,11 @@ is empty, so no A- or R-profile port could previously be built this way.
     -DTX_R52_CONSOLE_PL011=ON         console on the PL011 UART, not semihosting
 
 TX_R52_ENABLE_VFP is PUBLIC: it changes which registers the context switch
-saves, so the library and the application must agree.  Pair it with
-TX_R52_FLOAT_ABI=hard, otherwise the compiler emits no floating-point
-instructions and the VFP path is never exercised.
+saves, so the library and the application must agree.  It requires
+TX_R52_FLOAT_ABI=hard, and configure refuses the combination rather than
+warning about it: the flag enables the VFP blocks in the port assembly, and a
+soft float ABI leaves the assembler with no FPU to accept them, so the build
+fails on the first VMRS rather than quietly skipping the VFP context path.
 
 Cortex-R52 always implements at least a single-precision FPU.  GCC rejects
 "-mcpu=cortex-r52+nofp" and offers only "+nofp.dp", so the soft-float