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Allowed a BASEPRI-masked interrupt to wake the Cortex-M idle loop from WFI (#711)

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The idle loop in _tx_thread_schedule masks interrupts before re-reading
_tx_thread_execute_ptr, so that an interrupt cannot make a thread ready
between that read and the WFI and then be lost. With PRIMASK that is safe:
the architecture excludes PRIMASK from the WFI wake-up condition, so the
interrupt still wakes the processor and is taken as soon as the loop
re-enables interrupts.

BASEPRI is not excluded. When TX_PORT_USE_BASEPRI is defined, the mask
written at the top of the loop is still in place at the WFI, so any
interrupt at or below TX_PORT_BASEPRI fails to wake the processor at all.
On a system where every interrupt is managed by ThreadX, that is every
interrupt, and the processor stays in WFI or in the low power mode entered
by tx_low_power_enter until something outside the mask happens.

Set PRIMASK and clear BASEPRI for the duration of the WFI, then restore
BASEPRI and clear PRIMASK. Interrupts remain masked across the whole
window, so the original race is still closed, but the wake-up condition is
now evaluated with BASEPRI clear and any enabled interrupt can end the wait.
A pending interrupt is taken at the CPSIE i, or at the existing unmask
further down the loop if it falls below TX_PORT_BASEPRI.

The change is made in the ARMv7-M and ARMv8-M sources under ports_arch,
including the module manager, and propagated to the generated ports with
the copy scripts. The ghs and keil ports do not implement
TX_PORT_USE_BASEPRI, and Cortex-M0/M0+/M23 have no BASEPRI register, so
those ports are unaffected.

Verified by assembling every patched GNU port for Cortex-M3, M4, M7, M33,
M55 and M85, with and without TX_PORT_USE_BASEPRI, TX_LOW_POWER and
TX_ENABLE_EXECUTION_CHANGE_NOTIFY, and by checking the disassembly of the
idle loop.

Fixes #279

Assisted-by: Copilot (Opus 5) <noreply@github.com>
This commit is contained in:
Frédéric Desbiens
2026-09-09 11:29:14 -04:00
committed by GitHub
parent 146d57b235
commit 3fc28d8979
50 changed files with 528 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ports/cortex_m3/ac5/src/tx_thread_schedule.s
+10
View File
@@ -262,9 +262,19 @@ __tx_ts_wait
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m3/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -268,9 +269,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m3/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -266,9 +267,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m3/iar/src/tx_thread_schedule.s
+10
View File
@@ -262,9 +262,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m33/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -279,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m33/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -275,9 +276,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m33/iar/src/tx_thread_schedule.s
+10
View File
@@ -280,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m4/ac5/src/tx_thread_schedule.s
+10
View File
@@ -262,9 +262,19 @@ __tx_ts_wait
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m4/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -268,9 +269,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m4/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -266,9 +267,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m4/iar/src/tx_thread_schedule.s
+10
View File
@@ -262,9 +262,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m52/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -279,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m52/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -275,9 +276,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m52/iar/src/tx_thread_schedule.s
+10
View File
@@ -280,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m55/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -279,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m55/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -275,9 +276,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m55/iar/src/tx_thread_schedule.s
+10
View File
@@ -280,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m7/ac5/src/tx_thread_schedule.s
+10
View File
@@ -262,9 +262,19 @@ __tx_ts_wait
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m7/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -268,9 +269,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m7/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -266,9 +267,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m7/iar/src/tx_thread_schedule.s
+10
View File
@@ -262,9 +262,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m85/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -279,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m85/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -275,9 +276,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports/cortex_m85/iar/src/tx_thread_schedule.s
+10
View File
@@ -280,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_schedule.s
+10
View File
@@ -262,9 +262,19 @@ __tx_ts_wait
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -268,9 +269,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -266,9 +267,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv7-M/threadx/iar/src/tx_thread_schedule.s
+10
View File
@@ -262,9 +262,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -320,9 +320,19 @@ __tx_ts_wait
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -333,9 +334,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -331,9 +332,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -321,9 +321,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -279,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -275,9 +276,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s
+10
View File
@@ -280,9 +280,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -320,9 +320,19 @@ __tx_ts_wait
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -333,9 +334,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -331,9 +332,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -321,9 +321,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -335,9 +336,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -334,9 +335,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -332,9 +332,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -320,9 +320,19 @@ __tx_ts_wait
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -333,9 +334,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -331,9 +332,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -321,9 +321,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -320,9 +320,19 @@ __tx_ts_wait
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -333,9 +334,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S
+11
View File
@@ -9,6 +9,7 @@
* SPDX-License-Identifier: MIT
**************************************************************************/
// Some portions generated by Codex (GPT-5).
// Some portions generated by Copilot (Opus 5).
/**************************************************************************/
@@ -331,9 +332,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER
ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s
+10
View File
@@ -321,9 +321,19 @@ __tx_ts_wait:
#endif
#ifdef TX_ENABLE_WFI
#ifdef TX_PORT_USE_BASEPRI
CPSID i // Mask every interrupt with PRIMASK, which WFI ignores
MOV r1, #0 // Clear BASEPRI so that an interrupt masked by it
MSR BASEPRI, r1 // is still able to wake the processor
#endif
DSB // Ensure no outstanding memory transactions
WFI // Wait for interrupt
ISB // Ensure pipeline is flushed
#ifdef TX_PORT_USE_BASEPRI
LDR r1, =TX_PORT_BASEPRI // Restore the BASEPRI mask
MSR BASEPRI, r1
CPSIE i // Clear PRIMASK; a pending interrupt is taken here
#endif
#endif
#ifdef TX_LOW_POWER