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Release 6.1.5

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This commit is contained in:
Yuxin Zhou
2021-03-05 05:38:33 +00:00
parent 32e3b3b25f
commit 10a7932b9d
184 changed files with 15541 additions and 1830 deletions
Download Patch File Download Diff File Expand all files Collapse all files
common/inc/tx_api.h
+16 -17
View File
@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE C */
/* 6.1.3 */
/* 6.1.5 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -43,24 +43,29 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 William E. Lamie Modified comment(s), and */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 William E. Lamie Modified comment(s), and */
/* updated product constants, */
/* added new thread execution */
/* state TX_PRIORITY_CHANGE, */
/* added macros for casting */
/* pointers to ALIGN_TYPE, */
/* resulting in version 6.1 */
/* 10-16-2020 William E. Lamie Modified comment(s), and */
/* 10-16-2020 William E. Lamie Modified comment(s), and */
/* increased patch version, */
/* resulting in version 6.1.1 */
/* 11-09-2020 Yuxin Zhou Modified comment(s), and */
/* 11-09-2020 Yuxin Zhou Modified comment(s), and */
/* moved TX_THREAD_GET_SYSTEM_ */
/* STATE to tx_api.h, */
/* resulting in version 6.1.2 */
/* 12-31-2020 William E. Lamie Modified comment(s), and */
/* 12-31-2020 William E. Lamie Modified comment(s), and */
/* increased patch version, */
/* resulting in version 6.1.3 */
/* 03-02-2021 Scott Larson Modified comment(s), and */
/* order defines numerically, */
/* add option to remove FileX */
/* pointer, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -93,7 +98,7 @@ extern "C" {
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 1
#define THREADX_PATCH_VERSION 3
#define THREADX_PATCH_VERSION 5
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX
@@ -154,7 +159,6 @@ extern "C" {
#define TX_SUCCESS ((UINT) 0x00)
#define TX_DELETED ((UINT) 0x01)
#define TX_NO_MEMORY ((UINT) 0x10)
#define TX_POOL_ERROR ((UINT) 0x02)
#define TX_PTR_ERROR ((UINT) 0x03)
#define TX_WAIT_ERROR ((UINT) 0x04)
@@ -169,6 +173,7 @@ extern "C" {
#define TX_NO_INSTANCE ((UINT) 0x0D)
#define TX_THREAD_ERROR ((UINT) 0x0E)
#define TX_PRIORITY_ERROR ((UINT) 0x0F)
#define TX_NO_MEMORY ((UINT) 0x10)
#define TX_START_ERROR ((UINT) 0x10)
#define TX_DELETE_ERROR ((UINT) 0x11)
#define TX_RESUME_ERROR ((UINT) 0x12)
@@ -422,8 +427,10 @@ typedef struct TX_THREAD_STRUCT
TX_THREAD_EXTENSION_2
/* Define a pointer type for FileX extensions. */
#ifndef TX_NO_FILEX_POINTER
VOID *tx_thread_filex_ptr;
#endif
/* Define the priority inheritance variables. These will be used
to manage priority inheritance changes applied to this thread
as a result of mutex get operations. */
@@ -1092,7 +1099,6 @@ UINT _tx_trace_interrupt_control(UINT new_posture);
#ifdef TX_ENABLE_MULTI_ERROR_CHECKING
/* Services with MULTI runtime error checking ThreadX. */
#define tx_block_allocate _txr_block_allocate
@@ -1790,7 +1796,6 @@ VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL *inte
VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, VOID **highest_stack);
VOID _tx_misra_trace_event_insert(ULONG event_id, VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, ULONG time_stamp);
UINT _tx_misra_always_true(void);
UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **pointer);
UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer);
UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool);
@@ -1823,7 +1828,6 @@ VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore
VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr);
VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id));
#define TX_MEMSET(a,b,c) _tx_misra_memset((a), (UINT) (b), (UINT) (c))
#define TX_UCHAR_POINTER_ADD(a,b) _tx_misra_uchar_pointer_add((UCHAR *) (a), (ULONG) (b))
#define TX_UCHAR_POINTER_SUB(a,b) _tx_misra_uchar_pointer_sub((UCHAR *) (a), (ULONG) (b))
@@ -1842,8 +1846,6 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
#define TX_TRACE_IN_LINE_INSERT(i,a,b,c,d,e) _tx_misra_trace_event_insert((ULONG) (i), (VOID *) (a), (ULONG) (b), (ULONG) (c), (ULONG) (d), (ULONG) (e), ((ULONG) TX_TRACE_TIME_SOURCE));
#endif
#define TX_LOOP_FOREVER (_tx_misra_always_true() == TX_TRUE)
#define TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_indirect_void_to_uchar_pointer_convert((a))
#define TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(a) _tx_misra_uchar_to_indirect_uchar_pointer_convert((a))
#define TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_block_pool_to_uchar_pointer_convert((a))
@@ -1879,7 +1881,6 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
#define TX_THREAD_NOT_USED(a) _tx_misra_thread_not_used((a))
#define TX_THREAD_ENTRY_EXIT_NOTIFY_NOT_USED(a) _tx_misra_thread_entry_exit_notify_not_used((a))
#else
/* Define the TX_MEMSET macro to the standard library function, if not already defined. */
@@ -1908,8 +1909,6 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
(b) = (TX_TIMER *) working_ptr; \
}
#define TX_LOOP_FOREVER ((UINT) 1)
#define TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR **) ((VOID *) (a)))
#define TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(a) ((UCHAR **) ((VOID *) (a)))
#define TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR *) ((VOID *) (a)))
common/inc/tx_user_sample.h
+18 -3
View File
@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_user.h PORTABLE C */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -44,9 +44,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 Yuxin Zhou Modified comment(s), */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 Yuxin Zhou Modified comment(s), */
/* resulting in version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), */
/* added option to remove */
/* FileX pointer, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -76,6 +80,7 @@
TX_DISABLE_PREEMPTION_THRESHOLD
TX_DISABLE_REDUNDANT_CLEARING
TX_DISABLE_NOTIFY_CALLBACKS
TX_NO_FILEX_POINTER
TX_NOT_INTERRUPTABLE
TX_TIMER_PROCESS_IN_ISR
@@ -98,6 +103,16 @@
#define TX_TIMER_THREAD_PRIORITY ????
*/
/* Determine if there is a FileX pointer in the thread control block.
By default, the pointer is there for legacy/backwards compatibility.
The pointer must also be there for applications using FileX.
Define this to save space in the thread control block.
*/
/*
#define TX_NO_FILEX_POINTER
*/
/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls
should be processed within the a system timer thread or directly in the timer ISR.
By default, the timer thread is used. When the following is defined, the timer expiration
common_modules/module_manager/src/txm_module_manager_stop.c
+9 -4
View File
@@ -60,7 +60,7 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance)
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_stop PORTABLE C */
/* 6.1 */
/* 6.1.5 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -108,7 +108,10 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comments, fix */
/* object delete underflow, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
UINT _txm_module_manager_stop(TXM_MODULE_INSTANCE *module_instance)
@@ -531,9 +534,8 @@ TXM_MODULE_ALLOCATED_OBJECT *object_ptr;
#endif
/* Delete the allocated objects for this module. */
while (module_instance -> txm_module_instance_object_list_count--)
while (module_instance -> txm_module_instance_object_list_count != 0)
{
/* Pickup the current object pointer. */
object_ptr = module_instance -> txm_module_instance_object_list_head;
@@ -542,6 +544,9 @@ TXM_MODULE_ALLOCATED_OBJECT *object_ptr;
/* Release the object. */
_tx_byte_release((VOID *) object_ptr);
/* Decrement count. */
module_instance -> txm_module_instance_object_list_count--;
}
/* Set the allocated list head pointer to NULL. */
common_smp/inc/tx_api.h
+82 -77
View File
File diff suppressed because it is too large Load Diff
common_smp/inc/tx_user_sample.h
+41 -26
View File
@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** User Specific */
@@ -21,30 +21,34 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_user.h PORTABLE C */
/* 6.1 */
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_user.h PORTABLE C */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains user defines for configuring ThreadX in specific */
/* ways. This file will have an effect only if the application and */
/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */
/* Note that all the defines in this file may also be made on the */
/* command line when building ThreadX library and application objects. */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This file contains user defines for configuring ThreadX in specific */
/* ways. This file will have an effect only if the application and */
/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */
/* Note that all the defines in this file may also be made on the */
/* command line when building ThreadX library and application objects. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), */
/* added option to remove */
/* FileX pointer, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -58,7 +62,7 @@
For maximum speed, the following should be defined:
TX_MAX_PRIORITIES 32
TX_MAX_PRIORITIES 32
TX_DISABLE_PREEMPTION_THRESHOLD
TX_DISABLE_REDUNDANT_CLEARING
TX_DISABLE_NOTIFY_CALLBACKS
@@ -70,10 +74,11 @@
For minimum size, the following should be defined:
TX_MAX_PRIORITIES 32
TX_MAX_PRIORITIES 32
TX_DISABLE_PREEMPTION_THRESHOLD
TX_DISABLE_REDUNDANT_CLEARING
TX_DISABLE_NOTIFY_CALLBACKS
TX_NO_FILEX_POINTER
TX_NOT_INTERRUPTABLE
TX_TIMER_PROCESS_IN_ISR
@@ -89,13 +94,23 @@
to tx_port.h for descriptions on each of these options. */
/*
#define TX_MAX_PRIORITIES 32
#define TX_MINIMUM_STACK ????
#define TX_MAX_PRIORITIES 32
#define TX_MINIMUM_STACK ????
#define TX_THREAD_USER_EXTENSION ????
#define TX_TIMER_THREAD_STACK_SIZE ????
#define TX_TIMER_THREAD_PRIORITY ????
*/
/* Determine if there is a FileX pointer in the thread control block.
By default, the pointer is there for legacy/backwards compatibility.
The pointer must also be there for applications using FileX.
Define this to save space in the thread control block.
*/
/*
#define TX_NO_FILEX_POINTER
*/
/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls
should be processed within the a system timer thread or directly in the timer ISR.
By default, the timer thread is used. When the following is defined, the timer expiration
@@ -109,10 +124,10 @@
/* Determine if in-line timer reactivation should be used within the timer expiration processing.
By default, this is disabled and a function call is used. When the following is defined,
reactivating is performed in-line resulting in faster timer processing but slightly larger
code size. */
code size. */
/*
#define TX_REACTIVATE_INLINE
#define TX_REACTIVATE_INLINE
*/
/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled,
@@ -120,7 +135,7 @@
debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */
/*
#define TX_DISABLE_STACK_FILLING
#define TX_DISABLE_STACK_FILLING
*/
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
@@ -153,9 +168,9 @@
processing when not needed. The user will also have to comment out the call to
tx_timer_interrupt, which is typically made from assembly language in
tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR
must also be used. */
must also be used and tx_timer_initialize must be removed from ThreadX library. */
/*
/*
#define TX_NO_TIMER
#ifndef TX_TIMER_PROCESS_IN_ISR
#define TX_TIMER_PROCESS_IN_ISR
ports/c667x/ccs/example_build/tx/Release/makefile
+351
View File
File diff suppressed because it is too large Load Diff
ports/cortex_m0/ac5/src/tx_thread_schedule.s
+22 -3
View File
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -240,11 +247,23 @@ __tx_ts_wait
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
__tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
ports/cortex_m0/ac6/src/tx_thread_schedule.S
+23 -2
View File
@@ -25,6 +25,10 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +39,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +72,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -244,11 +251,25 @@ __tx_ts_wait:
STR r1, [r0] @ Store it in the current pointer
CMP r1, #0 @ If non-NULL, a new thread is ready!
BNE __tx_ts_ready @
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
ports/cortex_m0/gnu/CMakeLists.txt
Regular → Executable
View File
ports/cortex_m0/gnu/src/tx_thread_context_restore.S
Executable → Regular
View File
ports/cortex_m0/gnu/src/tx_thread_context_save.S
Executable → Regular
View File
ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S
Executable → Regular
View File
ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S
Executable → Regular
View File
ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S
Executable → Regular
View File
ports/cortex_m0/gnu/src/tx_thread_schedule.S
Executable → Regular
+24 -3
View File
@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -248,11 +255,25 @@ __tx_ts_wait:
STR r1, [r0] @ Store it in the current pointer
CMP r1, #0 @ If non-NULL, a new thread is ready!
BNE __tx_ts_ready @
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
ports/cortex_m0/gnu/src/tx_thread_stack_build.S
Executable → Regular
View File
ports/cortex_m0/gnu/src/tx_thread_system_return.S
Executable → Regular
View File
ports/cortex_m0/gnu/src/tx_timer_interrupt.S
Executable → Regular
View File
ports/cortex_m0/iar/src/tx_thread_schedule.s
+23 -2
View File
@@ -28,6 +28,10 @@
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -238,11 +245,25 @@ __tx_ts_wait:
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m0/keil/src/tx_thread_schedule.s
+24 -3
View File
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -241,11 +248,25 @@ __tx_ts_wait
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
__tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
ports/cortex_m23/ac6/inc/tx_port.h
+6 -2
View File
@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M23/AC6 */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -82,6 +85,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;
ports/cortex_m23/ac6/readme_threadx.txt
+2
View File
@@ -15,6 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project
as active, then then build the library. You should now observe the compilation
and assembly of the ThreadX library. This project build produces the ThreadX
library file ThreadX_Library.lib.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
3. Demonstration System
ports/cortex_m23/gnu/inc/tx_port.h
+6 -4
View File
@@ -47,11 +47,12 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 12-31-2020 Scott Larson Modified comment(s), */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), */
/* remove unneeded headers, */
/* use builtins, */
/* resulting in version 6.1.3 */
/* use builtins, added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -84,6 +85,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;
ports/cortex_m23/gnu/readme_threadx.txt
+2 -1
View File
@@ -6,7 +6,8 @@
1. Building the ThreadX run-time Library
An example .bat file is in the example_build directory.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
2. Demonstration System
ports/cortex_m23/iar/inc/tx_port.h
+6 -2
View File
@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M23/IAR */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -85,6 +88,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;
ports/cortex_m23/iar/readme_threadx.txt
+2 -1
View File
@@ -9,7 +9,8 @@ Import all ThreadX common and port-specific source files into an IAR project.
Configure the project to build a library rather than an executable. This
results in the ThreadX run-time library file tx.a, which is needed by
the application.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
2. Demonstration System
ports/cortex_m3/ac5/src/tx_thread_schedule.s
+24 -3
View File
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -217,11 +224,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m3/ac6/src/tx_thread_schedule.S
+24 -2
View File
@@ -25,6 +25,11 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M3/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +73,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -218,11 +226,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
ports/cortex_m3/ghs/src/tx_thread_schedule.arm
+19 -2
View File
@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/GHS */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,7 +61,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -210,11 +213,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m3/gnu/CMakeLists.txt
Regular → Executable
View File
ports/cortex_m3/gnu/src/tx_thread_schedule.S
+25 -4
View File
@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M3/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -222,11 +229,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
ports/cortex_m3/iar/src/tx_thread_schedule.s
+23 -2
View File
@@ -28,6 +28,10 @@
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -216,11 +223,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m3/keil/src/tx_thread_schedule.s
+24 -3
View File
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -217,11 +224,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m33/ac5/readme_threadx.txt
+69 -69
View File
@@ -53,80 +53,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance
ports/cortex_m33/ac6/inc/tx_port.h
+6 -2
View File
@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33/AC6 */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -82,6 +85,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;
ports/cortex_m33/ac6/readme_threadx.txt
+71 -70
View File
@@ -15,7 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project
as active, then then build the library. You should now observe the compilation
and assembly of the ThreadX library. This project build produces the ThreadX
library file ThreadX_Library.lib.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
3. Demonstration System
@@ -53,80 +54,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance
ports/cortex_m33/gnu/inc/tx_port.h
+6 -2
View File
@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33/GNU */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -80,6 +83,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;
ports/cortex_m33/gnu/readme_threadx.txt
+71 -70
View File
@@ -8,7 +8,8 @@ Import all ThreadX common and port-specific source files into a GNU project.
Configure the project to build a library rather than an executable. This
results in the ThreadX run-time library file tx.a, which is needed by
the application.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
2. Demonstration System
@@ -39,80 +40,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m33/iar/inc/tx_port.h
+6 -2
View File
@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33/IAR */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -85,6 +88,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;
ports/cortex_m33/iar/readme_threadx.txt
+71 -70
View File
@@ -9,7 +9,8 @@ Import all ThreadX common and port-specific source files into an IAR project.
Configure the project to build a library rather than an executable. This
results in the ThreadX run-time library file tx.a, which is needed by
the application.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
2. Demonstration System
@@ -45,80 +46,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m4/ac5/readme_threadx.txt
+69 -67
View File
@@ -56,78 +56,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m4/ac5/src/tx_thread_schedule.s
+24 -3
View File
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m4/ac6/readme_threadx.txt
+69 -69
View File
@@ -56,80 +56,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance
ports/cortex_m4/ac6/src/tx_thread_schedule.S
+24 -2
View File
@@ -25,6 +25,11 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M4/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +73,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -238,11 +246,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
ports/cortex_m4/ghs/readme_threadx.txt
+69 -67
View File
@@ -81,78 +81,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
7. Improving Performance
ports/cortex_m4/ghs/src/tx_thread_schedule.arm
+19 -2
View File
@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/GHS */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,7 +61,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -230,11 +233,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m4/gnu/CMakeLists.txt
Regular → Executable
View File
ports/cortex_m4/gnu/readme_threadx.txt
+69 -69
View File
@@ -53,80 +53,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m4/gnu/src/tx_thread_schedule.S
+25 -4
View File
@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M4/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -242,11 +249,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
ports/cortex_m4/iar/readme_threadx.txt
+69 -69
View File
@@ -58,80 +58,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10 (sl)
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m4/iar/src/tx_thread_schedule.s
+23 -2
View File
@@ -28,6 +28,10 @@
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -236,11 +243,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m4/keil/readme_threadx.txt
+69 -67
View File
@@ -57,78 +57,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m4/keil/src/tx_thread_schedule.s
+24 -3
View File
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m7/ac5/readme_threadx.txt
+69 -67
View File
@@ -57,78 +57,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m7/ac5/src/tx_thread_schedule.s
+24 -3
View File
@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m7/ac6/readme_threadx.txt
+75 -17
View File
@@ -55,24 +55,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Stack Offset Stack Contents
Non-FPU Stack Frame:
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance
ports/cortex_m7/ac6/src/tx_thread_schedule.S
+24 -2
View File
@@ -25,6 +25,11 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M7/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +73,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -237,11 +245,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
ports/cortex_m7/ghs/readme_threadx.txt
+69 -67
View File
@@ -81,78 +81,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
7. Improving Performance
ports/cortex_m7/ghs/src/tx_thread_schedule.arm
+19 -2
View File
@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/GHS */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,7 +61,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -230,11 +233,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/cortex_m7/gnu/CMakeLists.txt
Regular → Executable
View File
ports/cortex_m7/gnu/readme_threadx.txt
+75 -17
View File
@@ -52,24 +52,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Stack Offset Stack Contents
Non-FPU Stack Frame:
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m7/gnu/src/tx_thread_context_restore.S
Executable → Regular
View File
ports/cortex_m7/gnu/src/tx_thread_context_save.S
Executable → Regular
View File
ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S
Executable → Regular
View File
ports/cortex_m7/gnu/src/tx_thread_schedule.S
Executable → Regular
+25 -4
View File
@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M7/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -241,11 +248,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@
ports/cortex_m7/gnu/src/tx_thread_stack_build.S
Executable → Regular
View File
ports/cortex_m7/gnu/src/tx_thread_system_return.S
Executable → Regular
View File
ports/cortex_m7/gnu/src/tx_timer_interrupt.S
Executable → Regular
View File
ports/cortex_m7/iar/readme_threadx.txt
+69 -69
View File
@@ -58,80 +58,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10 (sl)
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance
ports/cortex_m7/iar/src/tx_thread_schedule.s
+23 -2
View File
@@ -28,6 +28,10 @@
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -236,11 +243,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
ports/rxv2/ccrx/inc/tx_port.h
+28 -28
View File
@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** Port Specific */
@@ -21,35 +21,35 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h RX/CCRX */
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h RXv2/CCRX */
/* 6.1.3 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
/* */
/**************************************************************************/
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
@@ -271,7 +271,7 @@ extern volatile ULONG _tx_thread_system_state;
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RX/CCRX Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/CCRX Version 6.1.3 *";
#else
extern CHAR _tx_version_id[];
#endif
ports/rxv2/ccrx/src/tx_initialize_low_level.src
+40 -40
View File
@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Initialize */
;/** */
@@ -29,47 +29,47 @@
.SECTION P,CODE
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level RX/CCRX */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, setting */
;/* up a periodic timer interrupt source, saving the system stack */
;/* pointer for use in ISR processing later, and finding the first */
;/* available RAM memory address for tx_application_define. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, setting */
;/* up a periodic timer interrupt source, saving the system stack */
;/* pointer for use in ISR processing later, and finding the first */
;/* available RAM memory address for tx_application_define. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
.GLB __tx_initialize_low_level
__tx_initialize_low_level:
ports/rxv2/ccrx/src/tx_thread_context_restore.src
+39 -39
View File
@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
@@ -40,46 +40,46 @@
.GLB __tx_thread_preempt_disable
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore RX/CCRX */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling routine */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs Interrupt Service Routines */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling routine */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs Interrupt Service Routines */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
;{
.GLB __tx_thread_context_restore
ports/rxv2/ccrx/src/tx_thread_context_save.src
+36 -36
View File
@@ -35,45 +35,45 @@
.GLB __tx_thread_system_stack_ptr
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save RX/CCRX */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
;{
.GLB __tx_thread_context_save
ports/rxv2/ccrx/src/tx_thread_interrupt_control.src
+37 -37
View File
@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
@@ -30,44 +30,44 @@
;
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control RX/CCRX */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for changing the interrupt lockout */
;/* posture of the system. */
;/* */
;/* INPUT */
;/* */
;/* new_posture New interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for changing the interrupt lockout */
;/* posture of the system. */
;/* */
;/* INPUT */
;/* */
;/* new_posture New interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
;{
ports/rxv2/ccrx/src/tx_thread_schedule.src
+38 -38
View File
@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
@@ -37,47 +37,47 @@
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule RX/CCRX */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
;{
.GLB __tx_thread_schedule
ports/rxv2/ccrx/src/tx_thread_stack_build.src
+32 -32
View File
@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
@@ -31,46 +31,46 @@
;
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build RX/CCRX */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function builds a stack frame on the supplied thread's stack. */
;/* The stack frame results in a fake interrupt return to the supplied */
;/* function pointer. */
;/* */
;/* INPUT */
;/* */
;/* function pointer. */
;/* */
;/* INPUT */
;/* */
;/* thread_ptr Pointer to thread control blk */
;/* function_ptr Pointer to return function */
;/* */
;/* OUTPUT */
;/* */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_thread_create Create thread service */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
;{
.GLB __tx_thread_stack_build
ports/rxv2/ccrx/src/tx_thread_system_return.src
+39 -39
View File
@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
@@ -35,46 +35,46 @@
.GLB __tx_thread_schedule
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return RX/CCRX */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is target processor specific. It is used to transfer */
;/* control from a thread back to the system. Only a minimal context */
;/* is saved since the compiler assumes temp registers are going to get */
;/* slicked by a function call anyway. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling loop */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is target processor specific. It is used to transfer */
;/* control from a thread back to the system. Only a minimal context */
;/* is saved since the compiler assumes temp registers are going to get */
;/* slicked by a function call anyway. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling loop */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
;{
.GLB __tx_thread_system_return
ports/rxv2/ccrx/src/tx_timer_interrupt.src
+43 -43
View File
@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Timer */
;/** */
@@ -45,50 +45,50 @@
.GLB __tx_thread_context_restore
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt RX/CCRX */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function processes the hardware timer interrupt. This */
;/* processing includes incrementing the system clock and checking for */
;/* time slice and/or timer expiration. If either is found, the */
;/* interrupt context save/restore functions are called along with the */
;/* expiration functions. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_context_save Save interrupted context */
;/* _tx_timer_expiration_process Timer expiration processing */
;/* _tx_thread_time_slice Time slice interrupted thread */
;/* _tx_thread_context_restore Restore interrupted context */
;/* */
;/* CALLED BY */
;/* */
;/* interrupt vector */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function processes the hardware timer interrupt. This */
;/* processing includes incrementing the system clock and checking for */
;/* time slice and/or timer expiration. If either is found, the */
;/* interrupt context save/restore functions are called along with the */
;/* expiration functions. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_context_save Save interrupted context */
;/* _tx_timer_expiration_process Timer expiration processing */
;/* _tx_thread_time_slice Time slice interrupted thread */
;/* _tx_thread_context_restore Restore interrupted context */
;/* */
;/* CALLED BY */
;/* */
;/* interrupt vector */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
;{
.GLB __tx_timer_interrupt
ports/rxv2/gnu/inc/tx_port.h
+28 -28
View File
@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** Port Specific */
@@ -21,35 +21,35 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h RX/GNURX */
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h RXv2/GNURX */
/* 6.1.3 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
/* */
/**************************************************************************/
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
@@ -255,7 +255,7 @@ static void _tx_thread_system_return_inline(void)
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RX/GNURX Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/GNURX Version 6.1.3 *";
#else
extern CHAR _tx_version_id[];
#endif
ports/rxv2/gnu/src/tx_initialize_low_level.S
+1 -1
View File
@@ -28,7 +28,7 @@
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level RX/GNURX */
;/* _tx_initialize_low_level RXv2/GNURX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/gnu/src/tx_thread_context_restore.S
+1 -1
View File
@@ -45,7 +45,7 @@
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore RX/GNURX */
;/* _tx_thread_context_restore RXv2/GNURX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/gnu/src/tx_thread_context_save.S
+2 -12
View File
@@ -19,17 +19,7 @@
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
.global __tx_thread_system_state
.global __tx_thread_current_ptr
.global __tx_thread_system_stack_ptr
@@ -39,7 +29,7 @@
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save RX/GNURX */
;/* _tx_thread_context_save RXv2/GNURX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/gnu/src/tx_thread_interrupt_control.S
+2 -11
View File
@@ -19,22 +19,13 @@
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
.text
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control RX/GNURX */
;/* _tx_thread_interrupt_control RXv2/GNURX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/gnu/src/tx_thread_schedule.S
+2 -13
View File
@@ -19,18 +19,7 @@
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
.global __tx_thread_execute_ptr
.global __tx_thread_current_ptr
.global __tx_timer_time_slice
@@ -41,7 +30,7 @@
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule RX/GNURX */
;/* _tx_thread_schedule RXv2/GNURX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/gnu/src/tx_thread_stack_build.S
+2 -12
View File
@@ -19,23 +19,13 @@
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
.text
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build RX/GNURX */
;/* _tx_thread_stack_build RXv2/GNURX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/gnu/src/tx_thread_system_return.S
+2 -12
View File
@@ -19,17 +19,7 @@
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
.global __tx_thread_current_ptr
.global __tx_timer_time_slice
.global __tx_thread_schedule
@@ -39,7 +29,7 @@
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return RX/GNURX */
;/* _tx_thread_system_return RXv2/GNURX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/gnu/src/tx_timer_interrupt.S
+3 -15
View File
@@ -19,19 +19,7 @@
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
.global __tx_timer_time_slice
.global __tx_timer_system_clock
.global __tx_timer_current_ptr
@@ -43,13 +31,13 @@
.global __tx_thread_context_save
.global __tx_thread_time_slice
.global __tx_thread_context_restore
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt RX/GNURX */
;/* _tx_timer_interrupt RXv2/GNURX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/iar/inc/tx_port.h
+28 -28
View File
@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** Port Specific */
@@ -21,35 +21,35 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h RX/IAR */
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h RXv2/IAR */
/* 6.1.3 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
/* */
/**************************************************************************/
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
@@ -263,7 +263,7 @@ extern volatile ULONG _tx_thread_system_state;
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RX/IAR Version 6.1.3 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/IAR Version 6.1.3 *";
#else
extern CHAR _tx_version_id[];
#endif
ports/rxv2/iar/src/tx_initialize_low_level.s
+40 -40
View File
@@ -12,8 +12,8 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Initialize */
;/** */
@@ -26,47 +26,47 @@
section .text:CODE:ROOT
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level RX/IAR */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level RXv2/IAR */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, setting */
;/* up a periodic timer interrupt source, saving the system stack */
;/* pointer for use in ISR processing later, and finding the first */
;/* available RAM memory address for tx_application_define. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, setting */
;/* up a periodic timer interrupt source, saving the system stack */
;/* pointer for use in ISR processing later, and finding the first */
;/* available RAM memory address for tx_application_define. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
public __tx_initialize_low_level
__tx_initialize_low_level:
ports/rxv2/iar/src/tx_thread_context_restore.s
+40 -51
View File
@@ -12,25 +12,14 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
extern __tx_thread_system_state
extern __tx_thread_current_ptr
extern __tx_thread_preempt_disable
@@ -40,46 +29,46 @@
section .text:CODE:ROOT
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore RX/IAR */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore RXv2/IAR */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling routine */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs Interrupt Service Routines */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling routine */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs Interrupt Service Routines */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
public __tx_thread_context_restore
__tx_thread_context_restore:
ports/rxv2/iar/src/tx_thread_context_save.s
+39 -49
View File
@@ -12,67 +12,57 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
extern __tx_thread_system_state
extern __tx_thread_current_ptr
section .text:CODE:ROOT
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save RX/IAR */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save RXv2/IAR */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
;{
public __tx_thread_context_save
ports/rxv2/iar/src/tx_thread_interrupt_control.s
+36 -44
View File
@@ -19,54 +19,46 @@
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
section .text:CODE:ROOT
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control RX/IAR */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control RXv2/IAR */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for changing the interrupt lockout */
;/* posture of the system. */
;/* */
;/* INPUT */
;/* */
;/* new_posture New interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for changing the interrupt lockout */
;/* posture of the system. */
;/* */
;/* INPUT */
;/* */
;/* new_posture New interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
;{
public __tx_thread_interrupt_control
ports/rxv2/iar/src/tx_thread_schedule.s
+40 -51
View File
@@ -12,72 +12,61 @@
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
extern __tx_thread_execute_ptr
extern __tx_thread_current_ptr
extern __tx_timer_time_slice
section .text:CODE:ROOT
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule RX/IAR */
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule RXv2/IAR */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
;{
public __tx_thread_schedule
ports/rxv2/iar/src/tx_thread_stack_build.s
+1 -1
View File
@@ -27,7 +27,7 @@
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build RX/IAR */
;/* _tx_thread_stack_build RXv2/IAR */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/iar/src/tx_thread_system_return.s
+2 -2
View File
@@ -22,11 +22,11 @@
section .text:CODE:ROOT
;/**************************************************************************/
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return RX/IAR */
;/* _tx_thread_system_return RXv2/IAR */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports/rxv2/iar/src/tx_timer_interrupt.s
+1 -1
View File
@@ -36,7 +36,7 @@
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt RX/IAR */
;/* _tx_timer_interrupt RXv2/IAR */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.s → ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.S
View File
ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.s → ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.S
View File
ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.s → ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.S
View File

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