mirror of
https://github.com/rene-dev/stmbl.git
synced 2026-09-25 17:40:40 +08:00
tim8 -> tim4
This commit is contained in:
+2
-2
@@ -43,13 +43,13 @@ void Wait(uint32_t ms);
|
||||
|
||||
//hal interface TODO: move hal interface to file
|
||||
void hal_enable_rt(){
|
||||
TIM_Cmd(TIM8, ENABLE);
|
||||
TIM_Cmd(TIM4, ENABLE);
|
||||
}
|
||||
void hal_enable_frt(){
|
||||
TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
|
||||
}
|
||||
void hal_disable_rt(){
|
||||
TIM_Cmd(TIM8, DISABLE);
|
||||
TIM_Cmd(TIM4, DISABLE);
|
||||
}
|
||||
void hal_disable_frt(){
|
||||
TIM_ITConfig(TIM2, TIM_IT_Update, DISABLE);
|
||||
|
||||
+34
-46
@@ -35,71 +35,56 @@ void setup(){
|
||||
}
|
||||
|
||||
// Setup Resolver Interface
|
||||
// TIM2 triggers ADC1 and 2 at 20kHz
|
||||
// TIM4 triggers ADC1,ADC2(OC4) and TIM2(TRGO) at 1.2MHz
|
||||
// TIM2 OC1 generates resolver reference signal at 10kHz
|
||||
// DMA2 moves 4 samples to memory, generates transfer complete interrupt at 5kHz
|
||||
// DMA2 moves 60 samples to memory, generates transfer complete interrupt at 5kHz
|
||||
void setup_res(){
|
||||
/*
|
||||
tim8
|
||||
trgo -> adc
|
||||
trgo -> tim2
|
||||
|
||||
tim2
|
||||
oc -> res
|
||||
up -> frt
|
||||
|
||||
adc -> dma
|
||||
|
||||
dma
|
||||
tc -> rt
|
||||
|
||||
*/
|
||||
|
||||
// adc timer (tim8)
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
|
||||
//master timer
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
|
||||
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
|
||||
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_TimeBaseStructure.TIM_Period = 140 - 1;// 700k 168e6/1/140 = 1.2MHz
|
||||
TIM_TimeBaseStructure.TIM_Period = 70 - 1;// 84e6 / 70 = 1.2MHz
|
||||
TIM_TimeBaseStructure.TIM_Prescaler = 0;
|
||||
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
|
||||
TIM_TimeBaseInit(TIM8, &TIM_TimeBaseStructure);
|
||||
TIM_ARRPreloadConfig(TIM8,ENABLE);
|
||||
TIM_SelectOutputTrigger(TIM8, TIM_TRGOSource_Update);// trigger ADC
|
||||
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
|
||||
TIM_ARRPreloadConfig(TIM4,ENABLE);
|
||||
TIM_SelectOutputTrigger(TIM4, TIM_TRGOSource_Update);// trigger ADC
|
||||
|
||||
|
||||
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
|
||||
// debug tim4
|
||||
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
// GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
// GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_TIM8);
|
||||
//
|
||||
// TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
|
||||
// TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
|
||||
// TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
|
||||
// TIM_OCInitStructure.TIM_Pulse = 10;
|
||||
// TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
|
||||
// TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
|
||||
// TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
|
||||
// TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
|
||||
//
|
||||
// TIM_OC3Init(TIM8, &TIM_OCInitStructure);
|
||||
// TIM_OC3PreloadConfig(TIM8, TIM_OCPreload_Enable);
|
||||
// TIM_CtrlPWMOutputs(TIM8, ENABLE);
|
||||
// GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
// GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_TIM4);
|
||||
|
||||
//oc4 for adc trigger
|
||||
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
|
||||
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
|
||||
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
|
||||
TIM_OCInitStructure.TIM_Pulse = 1;
|
||||
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
|
||||
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
|
||||
|
||||
TIM_OC4Init(TIM4, &TIM_OCInitStructure);
|
||||
TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable);
|
||||
TIM_CtrlPWMOutputs(TIM4, ENABLE);
|
||||
|
||||
//resolver timer
|
||||
//slave timer
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
|
||||
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
|
||||
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_TimeBaseStructure.TIM_Period = 60 - 1;// 1.2MHz / 60 = 20kHz
|
||||
TIM_TimeBaseStructure.TIM_Period = 60 - 1;// 1.2e6 / 60 = 20kHz
|
||||
TIM_TimeBaseStructure.TIM_Prescaler = 0;
|
||||
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
|
||||
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
|
||||
TIM_SelectSlaveMode(TIM2, TIM_SlaveMode_External1);//Rising edges of the selected trigger (TRGI) clock the counter
|
||||
TIM_ITRxExternalClockConfig(TIM2, TIM_TS_ITR1);// clk = tim8->trgo
|
||||
TIM_ITRxExternalClockConfig(TIM2, TIM_TS_ITR3);// clk = TIM4 trigger out
|
||||
TIM_ARRPreloadConfig(TIM2,ENABLE);
|
||||
|
||||
// resolver reference signal
|
||||
//TODO: move to res.comp
|
||||
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
|
||||
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
|
||||
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
|
||||
@@ -133,7 +118,7 @@ void setup_res(){
|
||||
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;//data converted will be shifted to right
|
||||
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//Input voltage is converted into a 12bit number giving a maximum value of 4096
|
||||
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; //the conversion is continuous, the input data is converted more than once
|
||||
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T8_TRGO;//trigger on rising edge of TIM8
|
||||
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T4_CC4;//trigger on rising edge of TIM4 cc4
|
||||
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_Rising;
|
||||
ADC_InitStructure.ADC_NbrOfConversion = 1;//ADC_ANZ;//I think this one is clear :p
|
||||
ADC_InitStructure.ADC_ScanConvMode = ENABLE;//The scan is configured in one channel
|
||||
@@ -179,16 +164,19 @@ void setup_res(){
|
||||
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
|
||||
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
||||
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
||||
//TODO: use double buffer
|
||||
//DMA_DoubleBufferModeConfig(DMA2_Stream0, (uint32_t)ADC_DMA_Buffer1, DMA_Memory_0);
|
||||
//DMA_DoubleBufferModeCmd(DMA2_Stream0, ENABLE);
|
||||
DMA_Init(DMA2_Stream0, &DMA_InitStructure);
|
||||
|
||||
//HAL Fast realtime irq 20kHz
|
||||
NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
|
||||
//HAL Realtime irq 5kHz
|
||||
NVIC_InitStructure.NVIC_IRQChannel = DMA2_Stream0_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
|
||||
@@ -10,8 +10,8 @@ d: dma request
|
||||
b: bits
|
||||
|
||||
APB2 DMA2 168 MHz
|
||||
TIM1(ac,16b,d(cc1,cc2,cc3,cc4,trgo,up,com),adc(cc1,cc2,cc3),itr(5,2,3,4)) enc_cmd
|
||||
TIM8(ac,16b,d(cc1,cc2,cc3,cc4,up,trgo,com),adc(cc1,trgo),itr(1,2,4,5)) res_master,adc
|
||||
TIM1(ac,16b,d(cc1,cc2,cc3,cc4,up,trgo,com),adc(cc1,cc2,cc3),itr(5,2,3,4)) enc_cmd
|
||||
TIM8(ac,16b,d(cc1,cc2,cc3,cc4,up,trgo,com),adc(cc1,trgo), itr(1,2,4,5)) brake/fan pwm
|
||||
TIM9(gp2,16b,itr(2,3,10,11))
|
||||
TIM10(gp3,16b)
|
||||
TIM11(gp3,16b)
|
||||
@@ -19,13 +19,13 @@ USART1 io_header,cmd_rx
|
||||
USART6
|
||||
|
||||
APB1 DMA1 84 MHz
|
||||
TIM2(gp1,32b,d(up,cc1,cc2,cc3,cc4),adc(cc2,cc3,cc4,trgo),itr(1,8,3,4)) res_slave,res_oc
|
||||
TIM3(gp1,16b,d(cc1,cc2,cc3,cc3,up,trgo),adc(cc1,trgo),itr(1,2,5,4)) enc_fb
|
||||
TIM4(gp1,16b,d(cc1,cc2,cc3,up),adc(cc4),itr(1,2,3,8))
|
||||
TIM5(gp1,32b,d(cc1,cc2,cc3,cc4,trgo),adc(cc1,cc2,cc3),itr(2,3,4,8))
|
||||
TIM2(gp1,32b,d(up,cc1,cc2,cc3,cc4), adc(cc2,cc3,cc4,trgo),itr(1,8,3,4)) res_slave,res_oc
|
||||
TIM3(gp1,16b,d(cc1,cc2,cc3,cc3,up,trgo),adc(cc1,trgo), itr(1,2,5,4)) enc_fb
|
||||
TIM4(gp1,16b,d(cc1,cc2,cc3,up), adc(cc4), itr(1,2,3,8)) res_master,adc
|
||||
TIM5(gp1,32b,d(cc1,cc2,cc3,cc4,trgo), adc(cc1,cc2,cc3), itr(2,3,4,8))
|
||||
TIM6(ba,16b,d(up))
|
||||
TIM7(ba,16b,d(up))
|
||||
TIM12(gp2,16b,itr(4,5,13,14))
|
||||
TIM12(gp2,16b, itr(4,5,13,14))
|
||||
TIM13(gp3,16b)
|
||||
TIM14(gp3,16b)
|
||||
USART2 f1_hv
|
||||
|
||||
Reference in New Issue
Block a user