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90 lines
3.2 KiB
C
90 lines
3.2 KiB
C
/**
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* @file
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* @ingroup RTEMSBSPsShared
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* @brief Xilinx Versal Peripheral memory map.
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*/
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/*
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* Copyright (C) 2025 Airbus Defence and Space
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*
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* Written by Remi Debord <remi.debord@airbus.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_SHARED_PERIPHERAL_MAPS_VERSAL
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#define LIBBSP_SHARED_PERIPHERAL_MAPS_VERSAL
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/* Data derived from https://docs.amd.com/r/en-US/am011-versal-acap-trm/4-GB-Processor-System-Address-Map */
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/* LPD IO Peripherals */
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#define VERSAL_UART0 (0xFF000000)
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#define VERSAL_UART1 (0xFF010000)
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#define VERSAL_I2C0 (0xFF020000)
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#define VERSAL_I2C1 (0xFF030000)
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#define VERSAL_SPI0 (0xFF040000)
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#define VERSAL_SPI1 (0xFF050000)
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#define VERSAL_CAN0 (0xFF060000)
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#define VERSAL_CAN1 (0xFF070000)
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#define VERSAL_GPIO (0xFF0B0000)
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#define VERSAL_GEM0 (0xFF0C0000)
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#define VERSAL_GEM1 (0xFF0D0000)
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/* LPD System Registers */
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#define VERSAL_IPI (0xFF300000)
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#define VERSAL_TTC0 (0xFF0E0000)
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#define VERSAL_TTC1 (0xFF0F0000)
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#define VERSAL_TTC2 (0xFF100000)
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#define VERSAL_TTC3 (0xFF110000)
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#define VERSAL_LPD_SWDT (0xFF120000)
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#define VERSAL_OCM_XMPU (0xFF980000)
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#define VERSAL_LPD_XPPU (0xFF990000)
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#define VERSAL_LPD_DMA_CH0 (0xFFA80000)
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#define VERSAL_LPD_DMA_CH1 (0xFFA90000)
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#define VERSAL_LPD_DMA_CH2 (0xFFAA0000)
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#define VERSAL_LPD_DMA_CH3 (0xFFAB0000)
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#define VERSAL_LPD_DMA_CH4 (0xFFAC0000)
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#define VERSAL_LPD_DMA_CH5 (0xFFAD0000)
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#define VERSAL_LPD_DMA_CH6 (0xFFAE0000)
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#define VERSAL_LPD_DMA_CH7 (0xFFAF0000)
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/* System Interrupt Table */
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/* SPIs */
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#define VERSAL_IRQ_UART_0 50
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#define VERSAL_IRQ_UART_1 51
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#define VERSAL_IRQ_TTC_0_0 69
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#define VERSAL_IRQ_TTC_0_1 70
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#define VERSAL_IRQ_TTC_0_2 71
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#define VERSAL_IRQ_TTC_1_0 72
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#define VERSAL_IRQ_TTC_1_1 73
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#define VERSAL_IRQ_TTC_1_2 74
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#define VERSAL_IRQ_TTC_2_0 75
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#define VERSAL_IRQ_TTC_2_1 76
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#define VERSAL_IRQ_TTC_2_2 77
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#define VERSAL_IRQ_TTC_3_0 78
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#define VERSAL_IRQ_TTC_3_1 79
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#define VERSAL_IRQ_TTC_3_2 80
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#endif /* LIBBSP_SHARED_PERIPHERAL_MAPS_VERSAL */
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