bsps/arm: Add BSP for Versal RPU

2026-10-06 10:59:48 +08:00 · 2026-01-15 11:43:59 +01:00
parent 126e19aa60
commit 0b2455f6f8
40 changed files with 1524 additions and 2 deletions
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64XilinxVersal
+ *
+ * @brief This source file contains this BSP's console configuration.
+ */
+
+/*
+ * Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems/console.h>
+#include <rtems/bspIo.h>
+#include <rtems/sysinit.h>
+
+#include <bsp/irq.h>
+#include <dev/serial/arm-pl011.h>
+#include <dev/serial/versal-uart.h>
+#include <peripheral_maps/xilinx_versal.h>
+
+#include <bspopts.h>
+
+static versal_pl011_context versal_uart_instances[2] = {
+  {
+    .pl011_ctx = {
+      .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("Versal UART 0"),
+      .regs = (arm_pl011_uart *) VERSAL_UART0,
+      .irq = VERSAL_IRQ_UART_0,
+      .clock = VERSAL_CLOCK_UART,
+      .initial_baud = VERSAL_UART_DEFAULT_BAUD
+    }
+  }, {
+    .pl011_ctx = {
+      .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("Versal UART 1"),
+      .regs = (arm_pl011_uart *) VERSAL_UART1,
+      .irq = VERSAL_IRQ_UART_1,
+      .clock = VERSAL_CLOCK_UART,
+      .initial_baud = VERSAL_UART_DEFAULT_BAUD
+    }
+  }
+};
+
+rtems_status_code console_initialize(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *arg
+)
+{
+  (void) major;
+  (void) minor;
+  (void) arg;
+
+  size_t i;
+
+  rtems_termios_initialize();
+
+  for (i = 0; i < RTEMS_ARRAY_SIZE(versal_uart_instances); ++i) {
+    char uart[] = "/dev/ttySX";
+
+    uart[sizeof(uart) - 2] = (char) ('0' + i);
+    rtems_termios_device_install(
+      &uart[0],
+      &versal_uart_handler,
+      NULL,
+      &versal_uart_instances[i].pl011_ctx.base
+    );
+
+    if (i == BSP_CONSOLE_MINOR) {
+      link(&uart[0], CONSOLE_DEVICE_NAME);
+    }
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
+
+void versal_debug_console_flush(void)
+{
+  versal_uart_reset_tx_flush(
+    &versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base
+  );
+}
+
+static void versal_debug_console_out(char c)
+{
+  rtems_termios_device_context *base =
+    &versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base;
+
+  arm_pl011_write_polled(base, c);
+}
+
+static void versal_debug_console_init(void)
+{
+  rtems_termios_device_context *base =
+    &versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base;
+
+  (void) versal_uart_initialize(base);
+  BSP_output_char = versal_debug_console_out;
+}
+
+static void versal_debug_console_early_init(char c)
+{
+  rtems_termios_device_context *base =
+    &versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base;
+
+  (void) versal_uart_initialize(base);
+  BSP_output_char = versal_debug_console_out;
+  versal_debug_console_out(c);
+}
+
+static int versal_debug_console_in(void)
+{
+  rtems_termios_device_context *base =
+    &versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base;
+
+  return arm_pl011_read_polled(base);
+}
+
+BSP_output_char_function_type BSP_output_char = versal_debug_console_early_init;
+
+BSP_polling_getchar_function_type BSP_poll_char = versal_debug_console_in;
+
+RTEMS_SYSINIT_ITEM(
+  versal_debug_console_init,
+  RTEMS_SYSINIT_BSP_START,
+  RTEMS_SYSINIT_ORDER_LAST_BUT_5
+);
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This header file provides BSP-specific interfaces.
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_H
+#define LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_H
+
+/**
+ * @defgroup RTEMSBSPsARMVersalRPU \
+ *   AMD Versal SoC - Real-time Processing Unit
+ *
+ * @ingroup RTEMSBSPsARM
+ *
+ * @brief This group contains the BSP for the Real-time Processing Unit (RPU)
+ *   contained in AMD Versal SoC devices.
+ *
+ * @{
+ */
+
+#include <bspopts.h>
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#ifndef ASM
+
+#include <rtems.h>
+
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+#define BSP_ARM_GIC_CPUIF_BASE 0x00F9001000
+
+#define BSP_ARM_GIC_DIST_BASE 0xF9000000
+
+#if !defined(VERSAL_RPU_LOCK_STEP_MODE) && VERSAL_RPU_SPLIT_INDEX != 0
+#define BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY
+#endif
+
+void versal_debug_console_flush(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+/** @} */
+
+#endif /* LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_H */
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This header file provides BSP-specific interrupt interfaces.
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_VERSAL_RPU_IRQ_H
+#define LIBBSP_ARM_XILINX_VERSAL_RPU_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+
+#include <bspopts.h>
+#include <dev/irq/arm-gic-irq.h>
+#include <peripheral_maps/xilinx_versal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifndef VERSAL_RPU_LOCK_STEP_MODE
+#define BSP_IRQ_HAVE_GET_SET_AFFINITY
+#endif
+
+#define BSP_INTERRUPT_VECTOR_COUNT 188
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_XILINX_VERSAL_RPU_IRQ_H */
@@ -0,0 +1,103 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This header file provides BSP-specific memory interfaces.
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_MEMORY_H
+#define LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_MEMORY_H
+
+#include <rtems/score/armv7-pmsa.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @addtogroup RTEMSBSPsARMVersalRPU
+ *
+ * @{
+ */
+
+extern char versal_memory_atcm_begin[];
+extern char versal_memory_atcm_end[];
+extern char versal_memory_atcm_size[];
+
+extern char versal_memory_btcm_begin[];
+extern char versal_memory_btcm_end[];
+extern char versal_memory_btcm_size[];
+
+extern char versal_memory_ddr_begin[];
+extern char versal_memory_ddr_end[];
+extern char versal_memory_ddr_size[];
+
+extern char versal_memory_nocache_begin[];
+extern char versal_memory_nocache_end[];
+extern char versal_memory_nocache_size[];
+
+extern char versal_memory_devps_begin[];
+extern char versal_memory_devps_end[];
+extern char versal_memory_devps_size[];
+
+extern char versal_memory_ocm_begin[];
+extern char versal_memory_ocm_end[];
+extern char versal_memory_ocm_size[];
+
+/**
+ * @brief Versal Adaptive SoC specific set up of the MMU.
+ *
+ * Provide in the application to override the defaults in the BSP.
+ */
+void versal_setup_mpu_and_cache(void);
+
+/**
+ * @brief This table defines the Versal Adaptive SoC specific MPU
+ * regions.
+ *
+ * The table entry count is provided by ::versal_mpu_region_count.
+ *
+ * The application may provide this table to override the defaults in the BSP.
+ */
+extern const ARMV7_PMSA_Region versal_mpu_regions[];
+
+/**
+ * @brief This constant contains the entry count of the ::versal_mpu_regions
+ *   table.
+ */
+extern const size_t versal_mpu_region_count;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_MEMORY_H */
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This header file provides BSP-specific interfaces.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research Corporation (OAR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_XIL_COMPAT_H
+#define LIBBSP_ARM_XILINX_VERSAL_RPU_BSP_XIL_COMPAT_H
+
+#include <bsp/xil-compat-common.h>
+#define ARMR5
+
+#endif
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This header file provides a Time Test 27 support implementation.
+ */
+
+/*
+ * Copyright (C) 2013, 2024 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+#include <dev/irq/arm-gic-tm27.h>
+
+#endif /* __tm27_h */
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This source file contains the implementation of bsp_reset().
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+
+void bsp_reset( rtems_fatal_source source, rtems_fatal_code code )
+{
+  /* CRL_APB_RESET_CTRL */
+  volatile uint32_t *reset_ctrl = (volatile uint32_t *) 0xff5e0218;
+
+  (void) source;
+  (void) code;
+
+  versal_debug_console_flush();
+
+  /*
+   * This is a workaround for:
+   *
+   * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108658
+   */
+  __asm__ volatile ("");
+
+  while (true) {
+    /*
+     * Request a soft system reset.  This is a system-level reset which is the
+     * equivalent to asserting the external PS_SRST_B reset signal pin.
+     */
+    *reset_ctrl |= UINT32_C(0x10);
+  }
+}
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This source file contains the implementation of bsp_start().
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq-generic.h>
+#include <bsp/linker-symbols.h>
+
+#include <libcpu/arm-cp15.h>
+
+void bsp_start(void)
+{
+  bsp_interrupt_initialize();
+
+  rtems_cache_coherent_add_area(
+    bsp_section_nocacheheap_begin,
+    (uintptr_t) bsp_section_nocacheheap_size
+  );
+}
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This source file contains the implementation of bsp_start_hook_0().
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/start.h>
+
+#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
+#define ARMV7_PMSA_TEXT_SECTION BSP_START_TEXT_SECTION
+
+#include <bsp/memory.h>
+#include <libcpu/arm-cp15.h>
+
+BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
+{
+  /* Do nothing */
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
+{
+  uint32_t index = 0;
+
+  for (size_t i = 0; i < versal_mpu_region_count; ++i) {
+    const ARMV7_PMSA_Region *region = &versal_mpu_regions[i];
+    index = _ARMV7_PMSA_Add_regions(
+      index,
+      region->begin,
+      region->size,
+      region->attributes
+    );
+  }
+
+  arm_cp15_instruction_cache_invalidate();
+  arm_cp15_data_cache_all_invalidate();
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
+
+  uint32_t control = arm_cp15_get_control();
+  control &= ~ARM_CP15_CTRL_A;
+  control &= ~ARM_CP15_CTRL_V;
+  control |= ARM_CP15_CTRL_M;
+  control |= ARM_CP15_CTRL_C;
+  control |= ARM_CP15_CTRL_I;
+  control |= ARM_CP15_CTRL_Z;
+  arm_cp15_set_control(control);
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
+
+  bsp_start_clear_bss();
+}
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMVersalRPU
+ *
+ * @brief This source file contains the implementation of
+ * zynqmp_setup_mpu_and_cache().
+ */
+
+/*
+ * Copyright (C) 2026 Airbus Defence and Space
+ *
+ * Written by Remi Debord <remi.debord@airbus.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/memory.h>
+#include <bsp/start.h>
+
+BSP_START_DATA_SECTION const ARMV7_PMSA_Region
+versal_mpu_regions[] = {
+  {
+    .begin = (uintptr_t)versal_memory_atcm_begin,
+    .size = (uintptr_t)versal_memory_atcm_size,
+    .attributes = ARMV7_PMSA_READ_WRITE_UNCACHED
+  }, {
+    .begin = (uintptr_t)versal_memory_btcm_begin,
+    .size = (uintptr_t)versal_memory_btcm_size,
+    .attributes = ARMV7_PMSA_READ_WRITE_UNCACHED
+  }, {
+    .begin = (uintptr_t)versal_memory_ddr_begin,
+    .size = (uintptr_t)versal_memory_ddr_size,
+    .attributes = ARMV7_PMSA_READ_WRITE_CACHED
+  }, {
+    .begin = (uintptr_t)versal_memory_devps_begin,
+    .size = (uintptr_t)versal_memory_devps_size,
+    .attributes = ARMV7_PMSA_NON_SHAREABLE_DEVICE
+  }, {
+    .begin = (uintptr_t)versal_memory_ocm_begin,
+    .size = (uintptr_t)versal_memory_ocm_size,
+    .attributes = ARMV7_PMSA_NON_SHAREABLE_DEVICE
+  }, {
+    .begin = (uintptr_t)versal_memory_nocache_begin,
+    .size = (uintptr_t)versal_memory_nocache_size,
+    .attributes = ARMV7_PMSA_READ_WRITE_UNCACHED
+  }
+};
+
+BSP_START_DATA_SECTION const size_t
+versal_mpu_region_count = RTEMS_ARRAY_SIZE(versal_mpu_regions);
@@ -0,0 +1,89 @@
+/**
+ * @file
+ * @ingroup RTEMSBSPsShared
+ * @brief Xilinx Versal Peripheral memory map.
+ */
+
+/*
+ * Copyright (C) 2025 Airbus Defence and Space
+ *
+ * Written by Remi Debord <remi.debord@airbus.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_SHARED_PERIPHERAL_MAPS_VERSAL
+#define LIBBSP_SHARED_PERIPHERAL_MAPS_VERSAL
+
+/* Data derived from https://docs.amd.com/r/en-US/am011-versal-acap-trm/4-GB-Processor-System-Address-Map */
+
+/* LPD IO Peripherals */
+#define VERSAL_UART0 (0xFF000000)
+#define VERSAL_UART1 (0xFF010000)
+#define VERSAL_I2C0 (0xFF020000)
+#define VERSAL_I2C1 (0xFF030000)
+#define VERSAL_SPI0 (0xFF040000)
+#define VERSAL_SPI1 (0xFF050000)
+#define VERSAL_CAN0 (0xFF060000)
+#define VERSAL_CAN1 (0xFF070000)
+#define VERSAL_GPIO (0xFF0B0000)
+#define VERSAL_GEM0 (0xFF0C0000)
+#define VERSAL_GEM1 (0xFF0D0000)
+
+/* LPD System Registers */
+#define VERSAL_IPI (0xFF300000)
+#define VERSAL_TTC0 (0xFF0E0000)
+#define VERSAL_TTC1 (0xFF0F0000)
+#define VERSAL_TTC2 (0xFF100000)
+#define VERSAL_TTC3 (0xFF110000)
+#define VERSAL_LPD_SWDT (0xFF120000)
+#define VERSAL_OCM_XMPU (0xFF980000)
+#define VERSAL_LPD_XPPU (0xFF990000)
+#define VERSAL_LPD_DMA_CH0 (0xFFA80000)
+#define VERSAL_LPD_DMA_CH1 (0xFFA90000)
+#define VERSAL_LPD_DMA_CH2 (0xFFAA0000)
+#define VERSAL_LPD_DMA_CH3 (0xFFAB0000)
+#define VERSAL_LPD_DMA_CH4 (0xFFAC0000)
+#define VERSAL_LPD_DMA_CH5 (0xFFAD0000)
+#define VERSAL_LPD_DMA_CH6 (0xFFAE0000)
+#define VERSAL_LPD_DMA_CH7 (0xFFAF0000)
+
+/* System Interrupt Table */
+
+/* SPIs */
+#define VERSAL_IRQ_UART_0 50
+#define VERSAL_IRQ_UART_1 51
+
+#define VERSAL_IRQ_TTC_0_0 69
+#define VERSAL_IRQ_TTC_0_1 70
+#define VERSAL_IRQ_TTC_0_2 71
+#define VERSAL_IRQ_TTC_1_0 72
+#define VERSAL_IRQ_TTC_1_1 73
+#define VERSAL_IRQ_TTC_1_2 74
+#define VERSAL_IRQ_TTC_2_0 75
+#define VERSAL_IRQ_TTC_2_1 76
+#define VERSAL_IRQ_TTC_2_2 77
+#define VERSAL_IRQ_TTC_3_0 78
+#define VERSAL_IRQ_TTC_3_1 79
+#define VERSAL_IRQ_TTC_3_2 80
+
+#endif /* LIBBSP_SHARED_PERIPHERAL_MAPS_VERSAL */
@@ -179,17 +179,25 @@ static void xil_ttc_clock_driver_support_at_tick(xil_ttc_timecounter *tc)

 static rtems_interrupt_entry xil_ttc_interrupt_entry;

+#if (!defined(ZYNQMP_RPU_LOCK_STEP_MODE) && ZYNQMP_RPU_SPLIT_INDEX != 0)
+#define XILINX_RPU_SPLIT_INDEX ZYNQMP_RPU_SPLIT_INDEX
+#endif
+
+#if (!defined(VERSAL_RPU_LOCK_STEP_MODE) && VERSAL_RPU_SPLIT_INDEX != 0)
+#define XILINX_RPU_SPLIT_INDEX VERSAL_RPU_SPLIT_INDEX
+#endif
+
 static void xil_ttc_clock_driver_support_install_isr(
  rtems_interrupt_handler handler
 )
 {
  rtems_status_code sc;

-#if !defined(ZYNQMP_RPU_LOCK_STEP_MODE) && ZYNQMP_RPU_SPLIT_INDEX != 0
+#ifdef XILINX_RPU_SPLIT_INDEX
  Processor_mask affinity;
  _Processor_mask_From_uint32_t(
    &affinity,
-    UINT32_C(1) << ZYNQMP_RPU_SPLIT_INDEX,
+    UINT32_C(1) << XILINX_RPU_SPLIT_INDEX,
    0
  );
  (void) bsp_interrupt_set_affinity(XIL_CLOCK_TTC_IRQ, &affinity);
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- split: null
+- env-append: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value:
+  - -march=armv7-r
+  - -mthumb
+  - -mfpu=vfpv3-d16
+  - -mfloat-abi=hard
+description: |
+  ABI flags
+enabled-by: true
+links: []
+name: ABI_FLAGS
+type: build
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: versal_rpu_lock_step
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+cppflags: []
+enabled-by: true
+family: xilinx-versal-rpu
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+source: []
+type: build
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: versal_rpu_split_0
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+cppflags: []
+enabled-by: true
+family: xilinx-versal-rpu
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+source: []
+type: build
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: versal_rpu_split_1
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+cppflags: []
+enabled-by: true
+family: xilinx-versal-rpu
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+source: []
+type: build
@@ -0,0 +1,87 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: group
+cflags: []
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install: []
+ldflags: []
+links:
+- role: build-dependency
+  uid: ../grp
+- role: build-dependency
+  uid: ../start
+- role: build-dependency
+  uid: abi
+- role: build-dependency
+  uid: optlockstep
+- role: build-dependency
+  uid: optsplitindex
+- role: build-dependency
+  uid: optmematcmori
+- role: build-dependency
+  uid: optmematcmlen
+- role: build-dependency
+  uid: optmembtcmori
+- role: build-dependency
+  uid: optmembtcmlen
+- role: build-dependency
+  uid: optmemocmori
+- role: build-dependency
+  uid: optmemocmlen
+- role: build-dependency
+  uid: optmemddrori
+- role: build-dependency
+  uid: optmemddrlen
+- role: build-dependency
+  uid: optmemnocacheori
+- role: build-dependency
+  uid: optmemnocachelen
+- role: build-dependency
+  uid: optmemdevpsori
+- role: build-dependency
+  uid: optmemdevpslen
+- role: build-dependency
+  uid: optclkuart
+- role: build-dependency
+  uid: optconsoleirq
+- role: build-dependency
+  uid: optconminor
+- role: build-dependency
+  uid: ../../optxilclockttcbaseaddr
+- role: build-dependency
+  uid: ../../optxilclockttcirq
+- role: build-dependency
+  uid: ../../optxilclockttcrefclk
+- role: build-dependency
+  uid: optresetvec
+- role: build-dependency
+  uid: obj
+- role: build-dependency
+  uid: ../../dev/irq/objarmgicv2
+- role: build-dependency
+  uid: ../../obj
+- role: build-dependency
+  uid: ../../objirq
+- role: build-dependency
+  uid: ../../objdevserialarmpl011
+- role: build-dependency
+  uid: ../../objdevspizynq
+- role: build-dependency
+  uid: ../../objdevspixil
+- role: build-dependency
+  uid: ../../objmem
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: linkcmds
+- role: build-dependency
+  uid: linkcmdsmemory
+- role: build-dependency
+  uid: ../../bspopts
+type: build
+use-after: []
+use-before: []
@@ -0,0 +1,50 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  INCLUDE linkcmds.memory
+
+  REGION_ALIAS ("REGION_START",          ATCM);
+  REGION_ALIAS ("REGION_VECTOR",         ATCM);
+  REGION_ALIAS ("REGION_TEXT",           DDR);
+  REGION_ALIAS ("REGION_TEXT_LOAD",      DDR);
+  REGION_ALIAS ("REGION_RODATA",         DDR);
+  REGION_ALIAS ("REGION_RODATA_LOAD",    DDR);
+  REGION_ALIAS ("REGION_DATA",           DDR);
+  REGION_ALIAS ("REGION_DATA_LOAD",      DDR);
+  REGION_ALIAS ("REGION_FAST_TEXT",      DDR);
+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", DDR);
+  REGION_ALIAS ("REGION_FAST_DATA",      DDR);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", DDR);
+  REGION_ALIAS ("REGION_BSS",            DDR);
+  REGION_ALIAS ("REGION_WORK",           DDR);
+  REGION_ALIAS ("REGION_STACK",          DDR);
+  REGION_ALIAS ("REGION_NOCACHE",        NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+
+  bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
+
+  bsp_vector_table_in_start_section = 1;
+
+  /* define symbols required by xil_cache.c */
+  _stack_end = bsp_section_stack_end;
+  __undef_stack = bsp_section_stack_begin;
+
+  /*
+   * Please note that the OCM may be also used by bootloaders or the
+   * ARM Trusted Firmware (ATF).  You have to make sure that the OCM is shared
+   * without conflicts.
+   */
+  SECTIONS {
+    .ocm : {
+      *(SORT(.ocm*));
+    } > OCM AT > OCM
+  }
+
+  INCLUDE linkcmds.armv4
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
@@ -0,0 +1,42 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  MEMORY {
+    ATCM : ORIGIN = ${VERSAL_MEMORY_ATCM_ORIGIN:#010x}, LENGTH = ${VERSAL_MEMORY_ATCM_LENGTH:#010x}
+    BTCM : ORIGIN = ${VERSAL_MEMORY_BTCM_ORIGIN:#010x}, LENGTH = ${VERSAL_MEMORY_BTCM_LENGTH:#010x}
+    DDR : ORIGIN = ${VERSAL_MEMORY_DDR_ORIGIN:#010x}, LENGTH = ${VERSAL_MEMORY_DDR_LENGTH:#010x}
+    NOCACHE : ORIGIN = ${VERSAL_MEMORY_NOCACHE_ORIGIN:#010x}, LENGTH = ${VERSAL_MEMORY_NOCACHE_LENGTH:#010x}
+    DEVPS : ORIGIN = ${VERSAL_MEMORY_DEVPS_ORIGIN:#010x}, LENGTH = ${VERSAL_MEMORY_DEVPS_LENGTH:#010x}
+    OCM : ORIGIN = ${VERSAL_MEMORY_OCM_ORIGIN:#010x}, LENGTH = ${VERSAL_MEMORY_OCM_LENGTH:#010x}
+  }
+
+  versal_memory_atcm_begin = ORIGIN (ATCM);
+  versal_memory_atcm_end = ORIGIN (ATCM) + LENGTH (ATCM);
+  versal_memory_atcm_size = LENGTH (ATCM);
+
+  versal_memory_btcm_begin = ORIGIN (BTCM);
+  versal_memory_btcm_end = ORIGIN (BTCM) + LENGTH (BTCM);
+  versal_memory_btcm_size = LENGTH (BTCM);
+
+  versal_memory_ddr_begin = ORIGIN (DDR);
+  versal_memory_ddr_end = ORIGIN (DDR) + LENGTH (DDR);
+  versal_memory_ddr_size = LENGTH (DDR);
+
+  versal_memory_nocache_begin = ORIGIN (NOCACHE);
+  versal_memory_nocache_end = ORIGIN (NOCACHE) + LENGTH (NOCACHE);
+  versal_memory_nocache_size = LENGTH (NOCACHE);
+
+  versal_memory_devps_begin = ORIGIN (DEVPS);
+  versal_memory_devps_end = ORIGIN (DEVPS) + LENGTH (DEVPS);
+  versal_memory_devps_size = LENGTH (DEVPS);
+
+  versal_memory_ocm_begin = ORIGIN (OCM);
+  versal_memory_ocm_end = ORIGIN (OCM) + LENGTH (OCM);
+  versal_memory_ocm_size = LENGTH (OCM);
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds.memory
+type: build
@@ -0,0 +1,47 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}
+  source:
+  - bsps/arm/xilinx-versal-rpu/include/bsp.h
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/arm/xilinx-versal-rpu/include/bsp/irq.h
+  - bsps/arm/xilinx-versal-rpu/include/bsp/memory.h
+  - bsps/arm/xilinx-versal-rpu/include/bsp/xil-compat.h
+  - bsps/include/bsp/xil-compat-common.h
+- destination: ${BSP_INCLUDEDIR}/peripheral_maps
+  source:
+  - bsps/include/peripheral_maps/xilinx_versal.h
+- destination: ${BSP_INCLUDEDIR}/dev/serial
+  source:
+  - bsps/include/dev/serial/versal-uart.h
+links: []
+source:
+- bsps/arm/shared/cache/cache-cp15.c
+- bsps/arm/shared/cache/cache-v7ar-disable-data.S
+- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
+- bsps/arm/shared/start/bsp-start-memcpy.S
+- bsps/arm/xilinx-versal-rpu/console/console.c
+- bsps/shared/dev/serial/versal-uart.c
+- bsps/arm/xilinx-versal-rpu/start/bspreset.c
+- bsps/arm/xilinx-versal-rpu/start/bspstart.c
+- bsps/arm/xilinx-versal-rpu/start/bspstarthooks.c
+- bsps/arm/xilinx-versal-rpu/start/mpu-config.c
+- bsps/shared/dev/clock/xil-ttc.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/dev/getentropy/getentropy-cpucounter.c
+- bsps/shared/dev/irq/arm-gicv2-zynqmp.c
+- bsps/shared/dev/serial/console-termios.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/shared/start/gettargethash-default.c
+- bsps/shared/start/sbrk.c
+- bsps/shared/start/stackalloc.c
+type: build
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 100000000
+description: |
+  Versal UART clock frequency in Hz
+enabled-by: true
+format: '{}'
+links: []
+name: VERSAL_CLOCK_UART
+type: build
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0
+description: |
+  minor number of console device
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_CONSOLE_MINOR
+type: build
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: false
+description: |
+  Use the Termios interrupt mode in the console driver (unused by default).
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_CONSOLE_USE_INTERRUPTS
+type: build
@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+- env-enable: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by:
+  - arm/versal_rpu_split_0
+  - arm/versal_rpu_split_1
+  value: false
+- enabled-by: true
+  value: true
+description: |
+  If this option is true, then the Cortex-R5F cores of the RPU shall operate in
+  lock-step mode, otherwise they shall operate in split mode.
+enabled-by: true
+format: '{}'
+links: []
+name: VERSAL_RPU_LOCK_STEP_MODE
+type: build
@@ -0,0 +1,22 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: VERSAL_RPU_LOCK_STEP_MODE
+  value: 0x00020000
+- enabled-by: true
+  value: 0x00010000
+description: |
+  This option defines the length in bytes of the tightly-coupled memory A
+  (ATCM).
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_ATCM_LENGTH
+type: build
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0x00000000
+description: |
+  This option defines the address of the tightly-coupled memory A (ATCM)
+  origin.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_ATCM_ORIGIN
+type: build
@@ -0,0 +1,22 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: VERSAL_RPU_LOCK_STEP_MODE
+  value: 0x00020000
+- enabled-by: true
+  value: 0x00010000
+description: |
+  This option defines the length in bytes of the tightly-coupled memory B
+  (BTCM).
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_BTCM_LENGTH
+type: build
@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0x00020000
+description: |
+  This option defines the address for the tightly-coupled memory B (BTCM)
+  origin.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_BTCM_ORIGIN
+type: build
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0x01000000
+description: |
+  This option defines the length in bytes of the DDR memory area used by the
+  RPU. If the non-cacheable memory area is located in the DDR memory, then this
+  area shall be excluded from the area specified by this option.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_DDR_LENGTH
+type: build
@@ -0,0 +1,23 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: VERSAL_RPU_SPLIT_INDEX_1
+  value: 0x3f000000
+- enabled-by: true
+  value: 0x3e000000
+description: |
+  This option defines the address of the DDR memory area used by the RPU. If
+  the non-cacheable memory area is located in the DDR memory, then this area
+  shall be excluded from the area specified by this option.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_DDR_ORIGIN
+type: build
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0x40000000
+description: |
+  This option defines the length in bytes of the PS devices memory area.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_DEVPS_LENGTH
+type: build
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0xc0000000
+description: |
+  This option defines the address of the PS devices memory area.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_DEVPS_ORIGIN
+type: build
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0x00000000
+description: |
+  This option defines the length in bytes of the non-cacheable memory area.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_NOCACHE_LENGTH
+type: build
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0x00000000
+description: |
+  This option defines the address of the non-cacheable memory area.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_NOCACHE_ORIGIN
+type: build
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0x00040000
+description: |
+  This option defines the length in bytes of the On-Chip Memory (OCM).
+  Please note that the OCM may be also used by bootloaders or the
+  ARM Trusted Firmware (ATF).
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_OCM_LENGTH
+type: build
@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: 0xfffc0000
+description: |
+  This option defines the address of the On-Chip Memory (OCM).
+  Please note that the OCM may be also used by bootloaders or the
+  ARM Trusted Firmware (ATF).
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: VERSAL_MEMORY_OCM_ORIGIN
+type: build
@@ -0,0 +1,16 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: true
+  value: false
+description: |
+  reset vector address for BSP start
+enabled-by: true
+links: []
+name: BSP_START_RESET_VECTOR
+type: build
@@ -0,0 +1,27 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-in-set:
+  - 0
+  - 1
+- format-and-define: null
+- env-assign: null
+- set-value: VERSAL_RPU_SPLIT_INDEX_${VERSAL_RPU_SPLIT_INDEX}
+- substitute: null
+- env-append: ENABLE
+build-type: option
+copyrights:
+- Copyright (C) 2026 Airbus Defence and Space
+default:
+- enabled-by: arm/versal_rpu_split_1
+  value: 1
+- enabled-by: true
+  value: 0
+description: |
+  This option defines the RPU core index (0 or 1).
+enabled-by:
+  not: VERSAL_RPU_LOCK_STEP_MODE
+format: '{}'
+links: []
+name: VERSAL_RPU_SPLIT_INDEX
+type: build
@@ -8,6 +8,8 @@ copyrights:
 default:
 - enabled-by: ZYNQMP_RPU_SPLIT_INDEX_1
  value: 0xff110004
+- enabled-by: VERSAL_RPU_SPLIT_INDEX_1
+  value: 0xff110004
 - enabled-by: true
  value: 0xff110000
 description: |
@@ -8,6 +8,10 @@ copyrights:
 default:
 - enabled-by: ZYNQMP_RPU_SPLIT_INDEX_1
  value: 69
+- enabled-by: VERSAL_RPU_SPLIT_INDEX_1
+  value: 79
+- enabled-by: bsps/arm/xilinx-versal-rpu
+  value: 78
 - enabled-by: true
  value: 68
 description: |